74ALVCH16601
18-bit universal bus transceiver (3-State)
Product specification
Supersedes data of 1998 Aug 31
IC24 Data Handbook
1998 Sep 24
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
2
1998 Sep 24 853-2122 20076
FEATURES
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•MULTIBYTETM flow-through standard pin-out architecture
•Low inductance multiple VCC and ground pins for minimum noise
and ground bounce
•Current drive ± 24 mA at 3.0 V
•All inputs have bus hold circuitry
•Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74ALVCH16601 is an 18-bit universal transceiver featuring
non-inverting 3-State bus compatible outputs in both send and
receive directions. Data flow in each direction is controlled by output
enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock
(CPAB and CPBA) inputs. For A-to-B data flow, the device operates
in the transparent mode when LEAB is High. When LEAB is Low, the
A data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB is Low, the outputs are
active. When OEAB is High, the outputs are in the high-impedance
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA
and CPBA.
To ensure the high impedance state during power up or power
down, OEBA and OEAB should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
QUICK REFERENCE DATA
GND = 0V ; Tamb = 25°C; tr = tf = 2.5 ns
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH Propagation delay
An, Bn to Bn, An VCC = 2.5V, CL = 30pF
VCC = 3.3V, CL = 50pF 3.1
2.8 ns
CI/O Input/Output capacitance 8.0 pF
CIInput capacitance 4.0 pF
C
Power dissi
p
ation ca
p
acitance
p
er latch
V = GND to VCC1
Outputs enabled 21 p
F
C
PD
Po
w
er
dissipation
capacitance
per
latch
V
I =
GND
to
V
CC
1
Outputs disabled 3
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V ;
(CL × VCC2 × fo) = sum of outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C74ALVCH16601 DGG SOT364-1
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
27
28
30
29
OEAB
LEAB
A0
GND
A1
A2
A3
A4
A5
GND
A6
A7
A8
A9
A11
GND
A12
VCC
A10
A13
A14
A15
A16
A17
VCC
GND
OEBA
LEBA
CEAB
CPAB
B0
GND
B1
B2
B3
B4
B5
GND
B6
B7
B8
B9
B11
GND
B12
VCC
B10
B13
B14
B15
B16
B17
VCC
GND
CPBA
CEBA
SW00129
LOGIC SYMBOL
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
OEAB
LEAB
CPAB
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
OEBA
LEBA
CPBA
3
5
6
8
10
12
13
14
15
16
17
19
20
21
23
24
26
1
2
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
27
28
30
9
SW00130
CEAB
56 CEBA 29
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OEAB Output enable A-to-B
2 LEAB Latch enable A-to-B
3, 5, 6, 8, 9,
10, 12, 13, 14,
15, 16, 17, 19,
20, 21, 23, 24,
26
A0 to A17 Data inputs/outputs
4, 11, 18, 25,
32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 VCC Positive supply voltage
27 OEBA Output enable B-to-A
28 LEBA Latch enable B-to-A
29 CEBA Clock enable B-to-A
30 CPBA Clock input B-to-A
54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,
38, 37, 36, 34,
33, 31
B0 to B17 Data inputs/outputs
55 CPAB Clock input A-to-B
56 CEAB Clock enable A-to-B
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 4
LOGIC DIAGRAM (one section)
CE
C1
CP
1D
CE
C1
CP
1D
18 IDENTICAL CHANNELS
A1
B1
OEBA
CEBA
LEBA
CPBA
OEAB
CEAB
LEAB
CPAB
SW00132
FUNCTION TABLE INPUTS
OUTPUTS
STATUS
CEXX OEXX LEXX CPXX DATA
OUTPUTS
STATUS
X H X X X Z Disabled
X
XL
LH
HX
XH
LH
LTransparent
H L L X X NC Hold
L
LL
LL
L↑
↑h
lH
LClock + display
L
LL
LL
LL
HX
XNC Hold
XX = AB for A-to-B direction, BA for B-to-A direction
H = HIGH voltage level
L = LOW voltage level
h = HIGH state must be present one setup time before the LOW -to-HIGH transition of CPXX
l = LOW state must be present one setup time before the LOW-to-HIGH transition of CPXX
X = Don’t care
↑= LOW-to-HIGH level transition
NC = No change
Z = High impedance “off” state
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 5
LOGIC SYMBOL (IEEE/IEC)
EN1
G2
2C3
C3
G2
EN4
3D
46D
56
55
1
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
SW00133
OEAB
CPAB
LEAB
A0
A1
A2
A3
A4
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
G5
5C6
C6
G5
29
30
28
27
OEBA
CPBA
CEBA
LEBA
CEAB
A5
24
26
33
31
A16
A17
B16
B17
1
BUSHOLD CIRCUIT
To internal circuit
VCC
Data Input
SW00050
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 6
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS
MIN MAX
UNIT
VCC
DC supply voltage 2.5V range (for max. speed
performance @ 30 pF output load) 2.3 2.7
V
V
CC DC supply voltage 3.3V range (for max. speed
performance @ 50 pF output load) 3.0 3.6
V
VIDC Input voltage range 0 VCC V
VODC output voltage range 0 VCC V
Tamb Operating free-air temperature range –40 +85 °C
tr, tfInput rise and fall times VCC = 2.3 to 3.0V
VCC = 3.0 to 3.6V 0
020
10 ns/V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +4.6 V
IIK DC input diode current VI 0 –50 mA
VI
DC in
p
ut voltage
For control pins1–0.5 to +4.6
V
V
I
DC
in ut
voltage
For data inputs1–0.5 to VCC +0.5
V
IOK DC output diode current VO VCC or VO 0 50 mA
VODC output voltage Note 1 –0.5 to VCC +0.5 V
IODC output source or sink current VO = 0 to VCC 50 mA
IGND, ICC DC VCC or GND current 100 mA
Tstg Storage temperature range –65 to +150 °C
PTOT Power dissipation per package
–plastic thin-medium-shrink (TSSOP) For temperature range: –40 to +125 °C
above +55°C derate linearly with 8 mW/K 600 mW
NOTE:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 7
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltage are referenced to GND (ground = 0 V).
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
HIGH level In
p
ut voltage
VCC = 2.3 to 2.7V 1.7 1.2
V
V
IH
HIGH
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 2.0 1.5
V
V
LOW level In
p
ut voltage
VCC = 2.3 to 2.7V 1.2 0.7
V
V
IL
LOW
le
v
el
Inp
u
t
v
oltage
VCC = 2.7 to 3.6V 1.5 0.8
V
VCC =23to36V
;
V=V or V
;
IO= 100µA
VCC 02
VCC
V
CC =
2
.
3
to
3
.
6V
;
V
I =
V
IH
or
V
IL;
I
O = –
100
µ
A
V
CC
0
.
2
V
CC
VCC = 2.3V ; V I = VIH or VIL; IO = –6mA VCC0.3 VCC0.08
VO
HIGH level out
p
ut voltage
VCC = 2.3V ; V I = VIH or VIL; IO = –12mA VCC0.6 VCC0.26
V
V
OH
HIGH
le
v
el
o
u
tp
u
t
v
oltage
VCC = 2.7V ; V I = VIH or VIL; IO = –12mA VCC0.5 VCC0.14
V
VCC = 3.0V ; V I = VIH or VIL; IO = –12mA VCC0.6 VCC0.09
VCC = 3.0V ; V I = VIH or VIL; IO = –24mA VCC1.0 VCC0.28
V=23to36V
;
V=V or V
;
I = 100µA
GND
020
V
V
CC =
2
.
3
to
3
.
6V
;
V
I =
V
IH
or
V
IL;
I
O =
100
µ
A
GND
0
.
20
V
VCC = 2.3V ; V I = VIH or VIL; IO = 6mA 0.07 0.40 V
VOL LOW level output voltage VCC = 2.3V ; V I = VIH or VIL; IO = 12mA 0.15 0.70
VCC = 2.7V ; V I = VIH or VIL; IO = 12mA 0.14 0.40 V
VCC = 3.0V ; V I = VIH or VIL; IO = 24mA 0.27 0.55
VCC =23to36V
;
IIInput leakage current
V
CC =
2
.
3
to
3
.
6V
;
V V or GND
0.1 5
µ
A
I
g
V
I =
V
CC or
GND
µ
IOZ 3-State output OFF-state current VCC = 2.7 to 3.6V; VI = VIH or VIL;
VO = VCC or GND 0.1 10 µA
ICC Quiescent supply current VCC = 2.3 to 3.6V ; VI = VCC or GND; IO = 0 0.2 40 µA
∆ICC Additional quiescent supply current VCC = 2.3V to 3.6V ; VI = VCC – 0.6V; IO = 0 150 750 µA
I
Bus hold LOW sustaining current
VCC = 2.3V ; V I = 0.7V245 –
µA
I
BHL
B
u
s
hold
LOW
s
u
staining
c
u
rrent
VCC = 3.0V ; V I = 0.8V275 150 µ
A
I
Bus hold HIGH sustaining current
VCC = 2.3V ; V I = 1.7V2–45
µA
I
BHH
B
u
s
hold
HIGH
s
u
staining
c
u
rrent
VCC = 3.0V ; V I = 2.0V2–75 –175 µ
A
IBHLO Bus hold LOW overdrive current VCC = 3.6V2500 µA
IBHHO Bus hold HIGH overdrive current VCC = 3.6V2–500 µA
NOTES:
1. All typical values are at Tamb = 25°C.
2. Valid for data inputs of bus hold parts.
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 8
AC CHARACTERISTICS FOR VCC = 2.3V TO 2.7V RANGE
GND = 0V ; tr = tf ≤ 2.0ns; C L = 30pF
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 2.5V ± 0.2V UNIT
MIN TYP1MAX
Propagation delay
An, Bn to Bn, An 1.0 3.1 5.2
tPHL/tPLH Propagation delay
LEAB, LEBA to Bn, An 1, 2 1.0 3.6 6.2 ns
Propagation delay
CPAB, CPBA to Bn, An 1.0 3.4 5.9
tPZH/tPZL 3-State output enable time
OEBA, OEAB to An,Bn 3 1.1 3.1 5.3 ns
tPHZ/tPLZ 3-State output enable time
OEBA, OEAB to An,Bn 3 1.4 2.8 4.9 ns
t
Pulse width HIGH
LEAB or LEBA
2
3.3 1.6 –
ns
t
WPulse width HIGH or LOW
CPAB, CPBA
2
3.3 2.0 –
ns
Set-up time
An, Bn to CPAB, CPBA 2.3 –0.2 –
tSU Set-up time
An, Bn to LEAB, LEBA 41.3 0.1 – ns
Set-up time
CEAB, CEBA to CPAB, CPBA 2.0 –0.4 –
Hold time
An, Bn to CPAB, CPBA 1.2 0.3 –
thHold time
An, Bn to LEAB, LEBA 41.3 0.2 – ns
Hold time
CEAB, CEBA to CPAB, CPBA 1.1 0.4 –
fMAX Maximum clock frequency 150 390 – MHz
NOTE:
1. All typical values are at VCC = 2.5V and Tamb = 25°C.
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 9
AC CHARACTERISTICS FOR VCC = 3.0V TO 3.6V RANGE AND VCC = 2.7V
GND = 0V ; tr = tf = 2.5ns; CL = 50pF
LIMITS
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
MIN TYP1MAX MIN TYP MAX
Propagation delay
An, Bn to Bn, An 1.0 2.8 4.2 3.1 4.7
tPHL/tPLH Propagation delay
LEAB, LEBA to Bn, An 1, 2 1.0 3.1 4.9 3.4 5.4 ns
Propagation delay
CPAB, CPBA to Bn, An 1.3 3.1 5.0 3.5 5.8
tPZH/tPZL 3-State output enable time
OEBA to An 3 1.1 2.8 5.2 3.3 6.1 ns
tPHZ/tPLZ 3-State output disable time
OEBA to An 3 1.2 3.2 4.4 3.3 4.8 ns
t
LE pulse width
LEAB, LEBA to CPAB, CPBA
2
3.3 0.9 3.3 0.7
ns
t
WLE pulse width HIGH or LOW
CPAB, CPBA
2
3.3 0.9 3.3 1.2
ns
Set-up time
An, Bn to CPAB, CPBA 2.1 –0.2 2.4 0.0
tSU Set-up time
An, Bn to LEAB, LEBA 41.1 0.3 1.2 –0.2 ns
Set-up time
CEAB, CEBA to CPAB, CPBA 1.7 –0.2 2.0 –0.7
Hold time
An, Bn to CPAB, CPBA 1.0 –0.1 1.1 0.3
thHold time
An, Bn to LEAB, LEBA 41.4 0.1 1.6 0.1 ns
Hold time
CEAB, CEBA to CPAB, CPBA 1.1 0.4 1.2 0.6
fMAX Maximum clock frequency 150 340 150 333 MHz
NOTE:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 10
AC WAVEFORMS
VCC = 2.3 TO 2.7 V RANGE
1. VM = 0.5 V
2. VX = VOL + 0.15V
3. VY = VOH – 0.15V
4. VI = VCC
5. VOL and VOH are the typical output voltage drop that occur with
the output load.
VCC = 3.0 TO 3.6 V RANGE AND VCC = 2.7 V
1. VM = 1.5 V
2. VX = VOL + 0.3V
3. VY = VOH – 0.3V
4. VI = 2.7 V
5. VOL and VOH are the typical output voltage drop that occur with
the output load.
SW00063
An, Bn
INPUT VM
tPHL tPLH
VOL
VI
VM
GND
VOH
Bn, An
OUTPUT
Waveform 1. Input (An, Bn) to output (Bn, An) propagation
delays
SW00134
CPXX
INPUT VM
tPHL tPLH
VOL
VI
VM
GND
VOH
An, Bn
OUTPUT
tW
LEXX
INPUT
1/fmax
W aveform 2. Latch enable input (LEAB,LE
BA) and clock pulse
input (CPAB, CPBA) to output propagation delays and their
pulse width
tPLZ tPZL
VI
OEXX INPUT
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND outputs
en-
abled
outputs
en-
abled
outputs
dis-
abled
tPHZ
VM
VM
VM
tPZH
VX
VY
SW00127
W aveform 3. 3-State enable and disable times
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
VM
An, Bn
INPUT
VM
tSU
NOTE: The unshaded areas indicate when the input is permitted
to change for predictable output performance.
SW00128
tSU
th
VI
GND
VI
GND
CPXX, LEXX
INPUT
th
W aveform 4. Data set-up and hold times for the An and Bn
inputs to the LEAB, LEBA, CPAB and CPBA inputs
TEST CIRCUIT
PULSE
GENERATOR
RT
VIN D.U.T.
VOUT
CL
VCC
RL=500 Ω
SWITCH POSITION
TEST SWITCH
tPLH/tPHL Open
tPLZ/tPZL 2VCC
tPHZ/tPZH GND
Test Circuit for 3-State Outputs
Open
GND
S12VCC
DEFINITIONS
VCC
2.7V
2.7 – 3.6V
VIN
VCC
2.7V
RL =Load resistor
CL = Load capacitance includes jig and probe capacitance
RT =Termination resistance should be equal to ZOUT
of pulse generators.
SW00047
RL=500 Ω
Load circuitry for switching times
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 11
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1
Philips Semiconductors Product specification
74ALVCH1660118-bit universal bus transceiver (3-State)
1998 Sep 24 12
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICATIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appl iances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
Philips Semiconductors
811 East Arques A venue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 06-98
Document order number: 9397–750–04798
