LTC2338-18
1
233818fa
For more information www.linear.com/LTC2338-18
TYPICAL APPLICATION
FEATURES DESCRIPTION
18-Bit, 1Msps, ±10.24V
True Bipolar, Fully Differential
Input ADC with 100dB SNR
The LT C
®
2338-18 is a low noise, high speed 18-bit succes-
sive approximation register (SAR) ADC with fully differential
inputs. Operating from a single 5V supply, the LTC2338-18
has a ±10.24V true bipolar input range, making it ideal for
high voltage applications which require a wide dynamic
range. The LTC2338-18 achieves ±4LSB INL maximum,
no missing codes at 18-bits with 100dB SNR.
The LTC2338-18 has an onboard single-shot capable
reference buffer and low drift (20ppm/°C max) 2.048V
temperature compensated reference. The LTC2338-18
also has a high speed SPI-compatible serial interface that
supports 1.8V, 2.5V, 3.3V and 5V logic while also featur-
ing a daisy-chain mode. The fast 1Msps throughput with
no cycle latency makes the LTC2338-18 ideally suited
for a wide variety of high speed applications. An internal
oscillator sets the conversion time, easing external timing
considerations. The LTC2338-18 dissipates only 50mW
and automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided to reduce the power
consumption of the LTC2338-18 to 300μW for further
power savings during inactive periods.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7705765, 7961132.
APPLICATIONS
n 1Msps Throughput Rate
n ±4LSB INL (Max)
n Guaranteed 18-Bit No Missing Codes
n Fully Differential Inputs
n True Bipolar Input Ranges ±6.25V, ±10.24V, ±12.5V
n 100dB SNR (Typ) at fIN = 2kHz
n –115dB THD (Typ) at fIN = 2kHz
n Guaranteed Operation to 125°C
n Single 5V Supply
n Low Drift (20ppm/°C Max) 2.048V Internal Reference
n Onboard Single-Shot Capable Reference Buffer
n No Pipeline Delay, No Cycle Latency
n 1.8V to 5V I/O Voltages
n SPI-Compatible Serial I/O with Daisy-Chain Mode
n Internal Conversion Clock
n Power Dissipation 50mW (Typ)
n 16-Lead MSOP Package
n Programmable Logic Controllers
n Industrial Process Control
n High Speed Data Acquisition
n Portable or Compact Instrumentation
n ATE
32k Point FFT fS = 1Msps, fIN = 2kHz
+10.24V
–10.24V
+10.24V
–10.24V
–
+
SAMPLE CLOCK
233818 TA01
10µF 0.1µF
5V
REF
1.8V TO 5V
47µF
REFBUF GND
CHAIN
RDL/SDI
SDO
SCK
BUSY
CNV
LTC2338-18
VDD
2.2µF
100nF
REFIN
VDDLBYP OVDD
IN+
IN–
FREQUENCY (kHz)
0 100 200 300
500
400
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
233818 TA01
SNR = 100.3dB
THD = –117dB
SINAD = 100.2dB
SFDR = –119dB
LTC2338-18
2
233818fa
For more information www.linear.com/LTC2338-18
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ..................................................6V
Supply Voltage (OVDD) ................................................6V
Supply Bypass Voltage (VDDLBYP) ...........................3.2V
Analog Input Voltage
IN+, IN– ..............................................–16.5V to 16.5V
REFBUF ................................................................... 6V
REFIN .................................................................. 2.8V
Digital Input Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3) ........................... (GND –0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC2338C ................................................ 0°C to 70°C
LTC2338I .............................................–40°C to 85°C
LTC2338H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
1
2
3
4
5
6
7
8
V
DDLBYP
VDD
GND
IN+
IN–
GND
REFBUF
REFIN
16
15
14
13
12
11
10
9
GND
OVDD
SDO
SCK
RDL/SDI
BUSY
CHAIN
CNV
TOP VIEW
MS PACKAGE
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 110°C/W
ORDER INFORMATION
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2338CMS-18#PBF LTC2338CMS-18#TRPBF 233818 16-Lead Plastic MSOP 0°C to 70°C
LTC2338IMS-18#PBF LTC2338IMS-18#TRPBF 233818 16-Lead Plastic MSOP –40°C to 85°C
LTC2338HMS-18#PBF LTC2338HMS-18#TRPBF 233818 16-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN+Absolute Input Range (IN+) (Note 5) l–2.5 • VREFBUF – 0.25 2.5 • VREFBUF + 0.25 V
VIN–Absolute Input Range (IN–) (Note 5) l–2.5 • VREFBUF – 0.25 2.5 • VREFBUF + 0.25 V
VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN– l–5 • VREFBUF 5 • VREFBUF V
VCM Common Mode Input Range (Note 11) l–0.5 0 0.5 V
IIN Analog Input Current l–7.8 4.8 mA
CIN Analog Input Capacitance 5 pF
RIN Analog Input Resistance 2.083 kΩ
CMRR Input Common Mode Rejection Ratio fIN = 500kHz 67 dB
http://www.linear.com/product/LTC2338-18#orderinfo
LTC2338-18
3
233818fa
For more information www.linear.com/LTC2338-18
CONVERTER CHARACTERISTICS
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS. (Notes 4, 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution l18 Bits
No Missing Codes l18 Bits
Transition Noise 0.8 LSBRMS
INL Integral Linearity Error (Note 6) l–4 ±1 4 LSB
DNL Differential Linearity Error l–1 ±0.1 1 LSB
BZE Bipolar Zero-Scale Error (Note 7) l–15 0 15 LSB
Bipolar Zero-Scale Error Drift 0.01 LSB/°C
FSE Bipolar Full-Scale Error VREFBUF = 4.096V (REFBUF Overdriven) (Notes 7, 9) l–100 100 LSB
REFIN = 2.048V (Note 7) l–150 150 LSB
Bipolar Full-Scale Error Drift ±0.5 ppm/°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SINAD Signal-to-(Noise + Distortion) Ratio ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l93 97 dB
±10.24V Range, fIN = 2kHz, REFIN = 2.048V l95 100 dB
±12.5V Range, fIN = 2kHz, REFBUF = 5V l96 101 dB
SNR Signal-to-Noise Ratio ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l93.5 97 dB
±10.24V Range, fIN = 2kHz, REFIN = 2.048V l96 100 dB
±12.5V Range, fIN = 2kHz, REFBUF = 5V l98 102 dB
THD Total Harmonic Distortion ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l–111 –102 dB
±10.24V Range, fIN = 2kHz, REFIN = 2.048V l–115 –102 dB
±12.5V Range, fIN = 2kHz, REFBUF = 5V l–112 –100 dB
SFDR Spurious Free Dynamic Range ±6.25V Range, fIN = 2kHz, REFIN = 1.25V l102 113 dB
±10.24V Range, fIN = 2kHz, REFIN = 2.048V l102 117 dB
±12.5V Range, fIN = 2kHz, REFBUF = 5V l100 114 dB
–3dB Input Linear Bandwidth 7 MHz
Aperture Delay 500 ps
Aperture Jitter 4 ps
Transient Response Full-Scale Step 500 ns
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFIN Internal Reference Output Voltage 2.043 2.048 2.053 V
VREFIN Temperature Coefficient (Note 14) l2 20 ppm/°C
REFIN Output Impedance 15 kΩ
VREFIN Line Regulation VDD = 4.75V to 5.25V 0.08 mV/V
REFIN Input Voltage Range (REFIN Overdriven) (Note 5) 1.25 2.4 V
LTC2338-18
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For more information www.linear.com/LTC2338-18
REFERENCE BUFFER CHARACTERISTICS
DIGITAL INPUTS AND DIGITAL OUTPUTS
POWER REQUIREMENTS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VREFBUF Reference Buffer Output Voltage VREFIN = 2.048V l4.091 4.096 4.101 V
REFBUF Input Voltage Range (REFBUF Overdriven) (Notes 5, 9) l2.5 5 V
REFBUF Output Impedance VREFIN = 0V 13 kΩ
IREFBUF REFBUF Load Current VREFBUF = 5V (REFBUF Overdriven) (Notes 9, 10)
VREFBUF = 5V, Nap Mode (REFBUF Overdriven) (Note 9)
l1.05
0.39
1.2 mA
mA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.8 • OVDD V
VIL Low Level Input Voltage l0.2 • OVDD V
IIN Digital Input Current VIN = 0V to OVDD l–10 10 μA
CIN Digital Input Capacitance 5 pF
VOH High Level Output Voltage IO = –500µA lOVDD – 0.2 V
VOL Low Level Output Voltage IO = 500µA l0.2 V
IOZ Hi-Z Output Leakage Current VOUT = 0V to OVDD l–10 10 µA
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = OVDD 10 mA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l4.75 5 5.25 V
OVDD Supply Voltage l1.71 5.25 V
IVDD
IOVDD
INAP
ISLEEP
Supply Current
Supply Current
Nap Mode Current
Sleep Mode Current
1Msps Sample Rate (IN+ = IN– = 0V)
1Msps Sample Rate (CL = 20pF)
Conversion Done (IVDD + IOVDD)
Sleep Mode (IVDD + IOVDD)
l
l
l
10
0.4
3.9
60
11.2
4.6
225
mA
mA
mA
μA
PDPower Dissipation
Nap Mode
Sleep Mode
1Msps Sample Rate (IN+ = IN– = 0V)
Conversion Done (IVDD + IOVDD)
Sleep Mode (IVDD + IOVDD)
l
l
l
50
19.5
0.3
56
23
1.1
mW
mW
mW
LTC2338-18
5
233818fa
For more information www.linear.com/LTC2338-18
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above VDD or OVDD without
latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, ±10.24V Range, REFIN = 2.048V,
fSMPL = 1MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 00 0000 0000 0000 0000 and 11
1111 1111 1111 1111. Full-scale bipolar error is the worst-case of –FS
or +FS untrimmed deviation from ideal first and last code transitions and
includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±20.48V input
with REFIN = 2.048V.
Note 9: When REFBUF is overdriven, the internal reference buffer must be
turned off by setting REFIN = 0V.
Note 10: fSMPL = 1MHz, IREFBUF varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 13: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSMPL Maximum Sampling Frequency l1 Msps
tCONV Conversion Time l460 527 ns
tACQ Acquisition Time tACQ = tCYC – tCONV – tBUSYLH (Note 11) l460 ns
tCYC Time Between Conversions l1 µs
tCNVH CNV High Time l20 ns
tBUSYLH CNV↑ to BUSY Delay CL = 20pF l13 ns
tCNVL Minimum Low Time for CNV (Note 12) l20 ns
tQUIET SCK Quiet Time from CNV↑(Note 11) l20 ns
tSCK SCK Period (Notes 12, 13) l10 ns
tSCKH SCK High Time l4 ns
tSCKL SCK Low Time l4 ns
tSSDISCK SDI Setup Time From SCK↑(Note 12) l4 ns
tHSDISCK SDI Hold Time From SCK↑(Note 12) l1 ns
tSCKCH SCK Period in Chain Mode tSCKCH = tSSDISCK + tDSDO (Note 12) l13.5 ns
tDSDO SDO Data Remains Valid Delay from SCK↑ CL = 20pF, OVDD = 5.25V
CL = 20pF, OVDD = 2.5V
CL = 20pF, OVDD = 1.71V
l
l
l
7.5
8
9.5
ns
ns
ns
tHSDO SDO Data Remains Valid Delay from SCK↑CL = 20pF (Note 11) l1 ns
tDSDOBUSYL SDO Data Valid Delay from BUSY↓CL = 20pF (Note 11) l5 ns
tEN Bus Enable Time After RDL↓(Note 12) l16 ns
tDIS Bus Relinquish Time After RDL↑(Note 12) l13 ns
tWAKE REFBUF Wakeup Time CREFBUF = 47μF, CREFIN = 100nF 200 ms
Figure 1. Voltage Levels for Timing Specifications
0.8 • OVDD
0.2 • OVDD
50% 50%
233818 F01
0.2 • OVDD
0.8 • OVDD
0.2 • OVDD
0.8 • OVDD
tDELAY
tWIDTH
tDELAY
LTC2338-18
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TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT fS = 1Msps,
fIN = 2kHz SNR, SINAD vs Input Frequency
THD, Harmonics
vs Input Frequency
SNR, SINAD vs Input Level,
fIN = 2kHz
SNR, SINAD vs Temperature,
fIN = 2kHz
THD, Harmonics vs Temperature,
fIN = 2kHz
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code DC Histogram
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
fSMPL = 1Msps, unless otherwise noted.
FREQUENCY (kHz)
0 100 200 300
500
400
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
233818 G04
SNR = 100.3dB
THD = –117dB
SINAD = 100.2dB
SFDR = –119dB
INPUT LEVEL (dB)
MAGNITUDE (dBFS)
102.0
233818 G07
100.0
100.5
101.0
101.5
–40 –30 –20 –10
0
SNR
SINAD
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
SNR, SINAD (dBFS)
102.0
101.5
101.0
100.5
233818 G08
98.0
98.5
99.0
99.5
100.0
SINAD
SNR
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
THD, HARMONICS (dBFS)
–105
–110
233818 G09
–135
–130
–125
–120
–115
3RD
2ND
THD
FREQUENCY (kHz)
SNR, SINAD (dBFS)
110
233818 G05
60
70
80
100
90
0 25 50 75 150125100 175
200
SNR
SINAD
FREQUENCY (kHz)
–80
–150
–140
–120
–130
–110
–100
–90
0 25 50 10075 150125 175
3RD
2ND
THD
CODE
0
COUNTS
2000
1000
500
4500
3000
2500
1500
3500
4000
5000
233818 G03
σ = 0.8
0–1–2–3 4321–4
OUTPUT CODE
–3.0
INL ERROR (LSB)
2.5
2.0
1.5
1.0
0
–2.5
–2.0
–1.5
–0.5
0.5
–1.0
3.0
233818 G01
–131072 –65536 0 65536
131072
OUTPUT CODE
–0.5
DNL ERROR (LSB)
0.4
0.3
0.2
0.1
0.0
–0.4
–0.3
–0.2
–0.1
0.5
233818 G02
–131072 –65536 0 65536
131072
LTC2338-18
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Temperature Sleep Current vs Temperature
Internal Reference Output vs
Temperature
Internal Reference Output
Temperature Coefficient
Distribution CMRR vs Input Frequency Supply Current vs Sampling Rate
INL/DNL vs Temperature Full-Scale Error vs Temperature Offset Error vs Temperature
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFIN = 2.048V,
fSMPL = 1Msps, unless otherwise noted.
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
INL, DNL ERROR (LSB)
2.0
1.5
1.0
0.5
233818 G10
–2.0
–1.5
–1.0
–0.5
0
MAX INL
MAX DNL
MIN INL
MIN DNL
TEMPERATURE (°C)
CURRENT (mA)
12
233818 G13
0
2
4
6
8
10
–55 –35 –15 5 25 45 65 85 105
125
VDD
OVDD
DRIFT (ppm/°C)
1086420–2–4–6–8–10
0
NUMBER OF PARTS
5
30
15
10
20
25
35
233818 G16
TEMPERATURE (°C)
CURRENT (µA)
120
233818 G14
0
20
40
60
80
100
–55 –35 –15 5 25 45 65 85 105
125
FREQUENCY (kHz)
0 200100 300 400
500
50
CMRR (dB)
65
60
55
80
75
70
233818 G17
233818 G15
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
INTERNAL REFERENCE OUTPUT (V)
2.0484
2.0483
2.0482
2.0481
2.0476
2.0477
2.0478
2.0479
2.0480
SAMPLING FREQUENCY (kHz)
0
SUPPLY CURRENT (mA)
12
10
6
2
8
4
0500 900300 700
233818 G18
1000
400 800200 600100
VDD
OVDD
233818 G11
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
FULL-SCALE ERROR (LSB)
20
15
10
5
–20
–15
–10
–5
0
233818 G12
TEMPERATURE (°C)
–55 –35 –15 5 25 45 65 85 105
125
OFFSET ERROR (LSB)
5
4
3
2
1
–5
–4
–3
–2
–1
0
LTC2338-18
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PIN FUNCTIONS
VDDLBYP (Pin 1): 2.5V Supply Bypass Pin. The voltage
on this pin is generated via an onboard regulator off of
VDD. This pin must be bypassed with a 2.2μF ceramic
capacitor to GND.
VDD (Pin 2): 5V Power Supply. The range of VDD is 4.75V to
5.25V. Bypass VDD to GND with a 10µF ceramic capacitor.
GND (Pins 3, 6 and 16): Ground.
IN+, IN– (Pins 4, 5): Positive and Negative Differential
Analog Inputs. Typical input range ±10.24V.
REFBUF (Pin 7): Reference Buffer Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the pin
with a 47μF ceramic capacitor. The internal buffer driving
this pin may be disabled by grounding its input at REFIN.
Once the buffer is disabled, an external reference may
overdrive this pin in the range of 2.5V to 5V. A resistive
load greater than 500kΩ can be placed on the reference
buffer output.
REFIN (Pin 8): Reference Output/Reference Buffer Input.
An onboard bandgap reference nominally outputs 2.048V
at this pin. Bypass this pin with a 100nF ceramic capacitor
to GND to limit the reference output noise. If more accu-
racy is desired, this pin may be overdriven by an external
reference in the range of 1.25V to 2.4V.
CNV (Pin 9): Convert Input. A rising edge on this input
powers up the part and initiates a new conversion. Logic
levels are determined by OVDD.
CHAIN (Pin 10): Chain Mode Selector Pin. When low,
the LTC2338-18 operates in normal mode and the
RDL/SDI input pin functions to enable or disable SDO.
When high, the LTC2338-18 operates in chain mode and the
RDL/SDI pin functions as SDI, the daisy-chain serial data
input. Logic levels are determined by OVDD.
BUSY (Pin 11): BUSY Indicator. Goes high at the start of
a new conversion and returns low when the conversion
has finished. Logic levels are determined by OVDD.
RDL/SDI (Pin 12): When CHAIN is low, the part is in nor-
mal mode and the pin is treated as a bus enabling input.
When CHAIN is high, the part is in chain mode and the
pin is treated as a serial data input pin where data from
another ADC in the daisy chain is input. Logic levels are
determined by OVDD.
SCK (Pin 13): Serial Data Clock Input. When SDO is enabled,
the conversion result or daisy-chain data from another
ADC is shifted out on the rising edges of this clock MSB
first. Logic levels are determined by OVDD.
SDO (Pin 14): Serial Data Output. The conversion result or
daisy-chain data is output on this pin on each rising edge
of SCK MSB first. The output data is in 2’s complement
format. Logic levels are determined by OVDD.
OVDD (Pin 15): I/O Interface Digital Power. The range of
OVDD is 1.71V to 5.25V. This supply is nominally set to
the same supply as the host interface (1.8V, 2.5V, 3.3V,
or 5V). Bypass OVDD to GND with a 0.1μF capacitor.
LTC2338-18
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FUNCTIONAL BLOCK DIAGRAM
REFBUF = 2.5V
TO 5V
REFIN = 1.25V
TO 2.4V
IN
+
VDD = 5V
OV
DD
= 1.8V
TO 5V
IN
–
VDDLBYP = 2.5V
CHAIN
0.63× BUFFER
2× REFERENCE
BUFFER
R
4R
CNV
GND
BUSY
SDO
SCK
RDL/SDI
CONTROL LOGIC
LDO
2.048V
REFERENCE
18-BIT SAMPLING ADC SPI
PORT
+
–
233818 BD01
15k
4R R
LTC2338-18
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TIMING DIAGRAM
NAP AND ACQUIRE
CONVERT
D15 D14D17 D16 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDO
SCK
CNV
CHAIN, RDL/SDI = 0
BUSY
233818 TD01
Conversion Timing Using the Serial Interface
LTC2338-18
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APPLICATIONS INFORMATION
OVERVIEW
The LTC2338-18 is a low noise, high speed 18-bit succes-
sive approximation register (SAR) ADC with fully differential
inputs. Operating from a single 5V supply, the LTC2338-18
has a ±10.24V true bipolar input range, making it ideal for
high voltage applications which require a wide dynamic
range. The LTC2338-18 achieves ±4LSB INL maximum,
no missing codes at 18-bits and 100dB SNR.
The LTC2338-18 has an onboard single-shot capable
reference buffer and low drift (20ppm/°C max) 2.048V
temperature-compensated reference. The LTC2338-18
also has a high speed SPI-compatible serial interface that
supports 1.8V, 2.5V, 3.3V and 5V logic while also featur-
ing a daisy-chain mode. The fast 1Msps throughput with
no cycle latency makes the LTC2338-18 ideally suited
for a wide variety of high speed applications. An internal
oscillator sets the conversion time, easing external timing
considerations. The LTC2338-18 dissipates only 50mW
and automatically naps between conversions, leading to
reduced power dissipation that scales with the sampling
rate. A sleep mode is also provided to reduce the power
consumption of the LTC2338-18 to 300μW for further
power savings during inactive periods.
CONVERTER OPERATION
The LTC2338-18 operates in two phases. During the
acquisition phase, the charge redistribution capacitor
D/A converter (CDAC) is connected to the outputs of
the resistor divider networks that pins IN+ and IN– drive
to sample an attenuated and level-shifted version of the
differential analog input voltage as shown in Figure 3. A
rising edge on the CNV pin initiates a conversion. Dur-
ing the conversion phase, the 18-bit CDAC is sequenced
through a successive approximation algorithm, effectively
comparing the sampled input with binary-weighted frac-
tions of the reference voltage (e.g. VREFBUF/2, VREFBUF/4
… VREFBUF/262144) using the differential comparator. At
the end of conversion, the CDAC output approximates the
sampled analog input. The ADC control logic then prepares
the 18-bit digital output code for serial transfer.
Figure 2. LTC2338-18 Transfer Function
TRANSFER FUNCTION
The LTC2338-18 digitizes the full-scale voltage of ±5 •
REFBUF into 218 levels, resulting in an LSB size of 156µV
with REFBUF = 4.096V. The ideal transfer function is shown
in Figure 2. The output data is in 2’s complement format.
ANALOG INPUT
The analog inputs of the LTC2338-18 are fully differential
to maximize the signal swing that can be digitized. The
analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The back-to-back diodes at the inputs
form clamps that provide ESD protection. Each input
drives a resistor divider network that has a total imped-
ance of 2kΩ. The resistor divider network attenuates and
level shifts the ±2.5 • REFBUF true bipolar signal swing
of each input to the 0-REFBUF input signal swing of the
ADC core. In the acquisition phase, 45pF (CIN) from the
sampling CDAC in series with approximately 50Ω (RON)
from the on-resistance of the sampling switch is con-
nected to the output of the resistor divider network. Any
unwanted signal that is common to both inputs will be
reduced by the common mode rejection of the ADC core
and resistor divider network. The inputs of the ADC core
draw a current spike while charging the CIN capacitors
during acquisition.
INPUT VOLTAGE (V)
0V
OUTPUT CODE (TWO’S COMPLEMENT)
–1
LSB
233818 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB
–FSR/2
FSR = +FS – –FS
1LSB = FSR/262144
LTC2338-18
12
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2338-18
Figure 4. Input Signal Chain
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high im-
pedance inputs of the LTC2338-18 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the dis-
tortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when entering acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2338-18. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs which draw a small
current spike during acquisition.
Input Filtering
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter to
minimize noise. The simple 1-pole RC lowpass filter shown
in Figure 4 is sufficient for many applications.
The input resistor divider network, sampling switch on-
resistance (RON) and the sample capacitor (CIN) form a
second lowpass filter that limits the input bandwidth to
the ADC core to 7MHz. A buffer amplifier with a low noise
density must be selected to minimize the degradation of
the SNR over this bandwidth.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
Single-Ended-to-Differential Conversion
For single-ended input signals, a single-ended-to-differen-
tial conversion circuit must be used to produce a differential
signal at the inputs of the LTC2338-18. The LT
®
1469 high
speed dual operational amplifier is recommended for per-
forming single-ended-to-differential conversions as shown
in Figure 5a. In this case, the first amplifier is configured
as a unity gain buffer and the single-ended input signal
directly drives the high impedance input of this amplifier.
Figure 5b shows the resulting FFT when the LT1469 is
used to drive the LTC2338-18 in this configuration.
Fully Differential Inputs
To achieve the full distortion performance of the
LTC2338-18, a low distortion fully differential signal source
driven through the LT1469 configured as two unity gain
buffers as shown in Figure 6 can be used to get the full
data sheet THD specification of –115dB.
RON
50Ω
400Ω CIN
45pF
RON
50Ω
0.63 • V
REFBUF
CIN
45pF
IN
+
IN
–
BIAS
VOLTAGE
1.6k
1.6k 400Ω
0.63 • VREFBUF
233818 F03
6600pF
500Ω
BW = 48kHz
SINGLE-ENDED-
TO-DIFFERENTIAL
DRIVER
SINGLE-ENDED
INPUT SIGNAL
LTC2338-18
IN+
IN–
233818
F04
LT1469
233818 F05a
±10.24V
±10.24V
OUT1
OUT2
3
1
7
6
5
2
+
–
4.99k 4.99k
±10.24V +
–
Figure 5a. LT1469 Converting a ±10.24V Single-Ended
Signal to a ±20.48V Differential Input Signal
LTC2338-18
13
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For more information www.linear.com/LTC2338-18
FREQUENCY (kHz)
0 100 200 300 400
500
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
233818 F05b
SNR = 100.1dB
THD = –110dB
SINAD = 99.7dB
SFDR = –111dB
APPLICATIONS INFORMATION
Figure 7a.LTC2338-18 Internal Reference Circuit
ADC REFERENCE
There are three ways of providing the ADC reference. The
first is to use both the internal reference and reference
buffer. The second is to externally overdrive the internal
reference and use the internal reference buffer. The third
is to disable the internal reference buffer and overdrive
the REFBUF pin from an external source. The following
tables give examples of these cases and the resulting
bipolar input ranges.
Table 1. Internal Reference with Internal Buffer
REFIN REFBUF BIPOLAR INPUT RANGE
2.048V 4.096V ±10.24V
Table 2. External Reference with Internal Buffer
REFIN
(OVERDRIVE)
REFBUF BIPOLAR INPUT RANGE
1.25V (Min) 2.5V ±6.25V
2.048V 4.096V ±10.24V
2.4V (Max) 4.8V ±12V
Figure 6. LT1469 Buffering a Fully Differential Signal Source
LT1469
233818 F06
31
2
+
–
57
6
+
–
±10.24V
±10.24V ±10.24V
±10.24V
Figure 5b. 128k Point FFT Plot with fIN = 2kHz
for Circuit Shown in Figure 5a
Table 3. External Reference Unbuffered
REFIN REFBUF
(OVERDRIVE)
BIPOLAR INPUT RANGE
0V 2.5V (Min) ±6.25V
0V 5V (Max) ±12.5V
Internal Reference with Internal Buffer
The LTC2338-18 has an on-chip, low noise, low drift
(20ppm/°C max), temperature compensated bandgap
reference that is factory trimmed to 2.048V. It is internally
connected to a reference buffer as shown in Figure 7a and
is available at REFIN (Pin 8). REFIN should be bypassed to
GND with a 100nF ceramic capacitor to minimize noise. The
reference buffer gains the REFIN voltage by 2 to 4.096V at
REFBUF (Pin 7). So the input range is ±10.24V, as shown
in Table 1. Bypass REFBUF to GND with at least a 47μF
ceramic capacitor (X7R, 10V, 1210 size) to compensate
the reference buffer and minimize noise.
LTC2338-18
BANDGAP
REFERENCE
233818 F07a
47µF
100nF
6.5k
REFBUF
REFIN 15k
6.5k
REFERENCE
BUFFER
GND
External Reference with Internal Buffer
If more accuracy and/or lower drift is desired, REFIN
can be easily overdriven by an external reference since
a 15k resistor is in series with the reference as shown
in Figure7b. REFIN can be overdriven in the range from
1.25V to 2.4V. The resulting voltage at REFBUF will be
2•REFIN. So the input range is ±5 • REFIN, as shown
in Table 2. Linear Technology offers a portfolio of high
performance references designed to meet the needs of
many applications. With its small size, low power, and high
accuracy, the LTC6655-2.048 is well suited for use with
the LTC2338-18 when overdriving the internal reference.
LTC2338-18
14
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Figure7b. Using the LTC6655-2.048 as an External Reference Figure 7c. Overdriving REFBUF Using the LTC6655-5
Figure 8. CNV Waveform Showing Burst Sampling
LTC2338-18
BANDGAP
REFERENCE
LTC6655-2.048
233818 F07b
47µF
2.7µF
6.5k
REFBUF
REFIN 15k
6.5k
REFERENCE
BUFFER
GND LTC2338-18
GND
BANDGAP
REFERENCE
LTC6655-5
233818 F07c
47µF
6.5k
REFBUF
REFIN 15k
6.5k
REFERENCE
BUFFER
The LTC6655-2.048 offers 0.025% (max) initial accuracy
and 2ppm/°C (max) temperature coefficient for high pre-
cision applications. The LTC6655-2.048 is fully specified
over the H-grade temperature range and complements
the extended temperature range of the LTC2338-18 up to
125°C. Bypassing the LTC6655-2.048 with a 2.7μF to 100μF
ceramic capacitor close to the REFIN pin is recommended.
External Reference Unbuffered
The internal reference buffer can also be overdriven from
2.5V to 5V with an external reference at REFBUF as shown
in Figure 7c. So the input ranges are ±6.25V to ±12.5V,
respectively, as shown in Table 3. To do so, REFIN must
be grounded to disable the reference buffer. A 13k resis-
tor loads the REFBUF pin when the reference buffer is
disabled. To maximize the input signal swing and cor-
responding SNR, the LTC6655-5 is recommended when
overdriving REFBUF. The LTC6655-5 offers the same small
size, accuracy, drift and extended temperature range as
the LTC6655-2.048. By using a 5V reference, an SNR of
102dB can be achieved. Bypassing the LTC6655-5 with
a 47μF ceramic capacitor (X5R, 0805 size) close to the
REFBUF pin is recommended.
The REFBUF pin of the LTC2338-18 draws a charge (QCONV)
from the external bypass capacitor during each conversion
cycle. If the internal reference buffer is overdriven, the
CNV
IDLE
PERIOD
IDLE
PERIOD
233818 F08
external reference must provide all of this charge with a
DC current equivalent to IREFBUF = QCONV/tCYC. Thus, the
DC current draw of REFBUF depends on the sampling rate
and output code. In applications where a burst of samples
is taken after idling for long periods, as shown in Figure8,
IREFBUF quickly goes from approximately 390µA to a maxi-
mum of 1.2mA for REFBUF = 5V at 1Msps. This step in DC
current draw triggers a transient response in the external
reference that must be considered since any deviation in
the voltage at REFBUF will affect the accuracy of the output
code. If an external reference is used to overdrive REFBUF,
the fast settling LTC6655-5 reference is recommended.
Internal Reference Buffer Transient Response
For optimum transient performance, the internal reference
buffer should be used. The internal reference buffer uses a
proprietary design that results in an output voltage change
at REFBUF of less than 1LSB when responding to a sudden
burst of conversions. This makes the internal reference
buffer of the LTC2338-18 truly single-shot capable since the
first sample taken after idling will yield the same result as
a sample taken after the transient response of the internal
reference buffer has settled. Figure 9 shows the transient
responses of the LTC2338-18 with the internal reference
buffer and with the internal reference buffer overdriven by
the LTC6655-5, both with a bypass capacitance of 47μF.
LTC2338-18
15
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For more information www.linear.com/LTC2338-18
TIME (µs)
DEVIATION FROM FINAL VALUE (LSB)
2
0
–2
–4
233818 F09
–8
–6
0 900800700600500400300200100
1000
INTERNAL REFERENCE BUFFER
EXTERNAL SOURCE ON REFBUF
FREQUENCY (kHz)
0 100 200 300
500
400
–180
AMPLITUDE (dBFS)
–60
–40
–20
–80
–100
–120
–140
–160
0
233818 F10
SNR = 100.3dB
THD = –117dB
SINAD = 100.2dB
SFDR = –119dB
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
Fast Fourier Transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave and
analyzing the digital output using an FFT algorithm, the ADC’s
spectral content can be examined for frequencies outside the
fundamental. The LTC2338-18 provides guaranteed tested
limits for both AC distortion and noise measurements.
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 10 shows that the LTC2338-18 achieves
a typical SINAD of 100dB at a 1MHz sampling rate with
a 2kHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 10 shows
that the LTC2338-18 achieves a typical SNR of 100dB at
a 1MHz sampling rate with a 2kHz input.
Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL/2).
THD is expressed as:
THD=20log V22+V32+V42+…+ VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2338-18 provides two power supply pins: the 5V
power supply (VDD), and the digital input/output interface
power supply (OVDD). The flexible OVDD supply allows the
LTC2338-18 to communicate with any digital logic operat-
ing between 1.8V and 5V, including 2.5V and 3.3V systems.
Power Supply Sequencing
The LTC2338-18 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2338-18
has a power-on reset (POR) circuit that will reset the
LTC2338-18 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
reenters the nominal supply voltage range, the POR will
re-initialize the ADC. No conversions should be initiated
until 100ms after a POR event to ensure the re-initialization
period has ended. Any conversions initiated before this
time will produce invalid results.
Figure 9. Transient Response of the LTC2338-18 Figure 10. 32k Point FFT of the LTC2338-18
LTC2338-18
16
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Figure 11. Power Supply Current of the LTC2338-18
Versus Sampling Rate.
TIMING AND CONTROL
CNV Timing
The LTC2338-18 conversion is controlled by CNV. A ris-
ing edge on CNV will start a conversion and power up
the LTC2338-18. Once a conversion has been initiated,
it cannot be restarted until the conversion is complete.
For optimum performance, CNV should be driven by a
clean low jitter signal. Converter status is indicated by the
BUSY output which remains high while the conversion is
in progress. To ensure that no errors occur in the digitized
results, any additional transitions on CNV should occur
within 40ns from the start of the conversion or after the
conversion has been completed. Once the conversion has
completed, the LTC2338-18 powers down and begins
acquiring the input signal.
Internal Conversion Clock
The LTC2338-18 has an internal clock that is trimmed to
achieve a maximum conversion time of 527ns. With a mini-
mum acquisition time of 460ns, throughput performance
of 1Msps is guaranteed without any external adjustments.
Auto Nap Mode
The LTC2338-18 automatically enters nap mode after a
conversion has been completed and completely powers
up once a new conversion is initiated on the rising edge of
CNV. During nap mode, only the ADC core powers down
and all other circuits remain active. During nap, data from
the last conversion can be clocked out. The auto nap mode
feature will reduce the power dissipation of the LTC2338-18
as the sampling frequency is reduced. Since full power is
consumed only during a conversion, the ADC core of the
LTC2338-18 remains powered down for a larger fraction of
the conversion cycle (tCYC) at lower sample rates, thereby
reducing the average power dissipation which scales with
the sampling rate as shown in Figure 11.
Sleep Mode
The auto nap mode feature provides limited power savings
since only the ADC core powers down. To obtain greater power
savings, the LTC2338-18 provides a sleep mode. During sleep
mode, the entire part is powered down except for a small
standby current resulting in a power dissipation of 300μW.
To enter sleep mode, toggle CNV twice with no intervening
rising edge on SCK. The part will enter sleep mode on the
falling edge of BUSY from the last conversion initiated. Once
in sleep mode, a rising edge on SCK will wake the part up.
Upon emerging from sleep mode, wait tWAKE seconds before
initiating a conversion to allow the reference and reference
buffer to wake up and charge the bypass capacitors at REFIN
and REFBUF. (Refer to the Timing Diagrams section for more
detailed timing information about sleep mode.)
DIGITAL INTERFACE
The LTC2338-18 has a serial digital interface. The flexible
OVDD supply allows the LTC2338-18 to communicate with
any digital logic operating between 1.8V and 5V, including
2.5V and 3.3V systems.
The serial output data is clocked out on the SDO pin when
an external clock is applied to the SCK pin if SDO is enabled.
Clocking out the data after the conversion will yield the
best performance. With a shift clock frequency of at least
40MHz, a 1Msps throughput is still achieved. The serial
output data changes state on the rising edge of SCK and
can be captured on the falling edge or next rising edge of
SCK. D17 remains valid till the first rising edge of SCK.
The serial interface on the LTC2338-18 is simple and
straightforward to use. The following sections describe the
operation of the LTC2338-18. Several modes are provided
depending on whether a single or multiple ADCs share the
SPI bus or are daisy-chained.
SAMPLING FREQUENCY (kHz)
0
SUPPLY CURRENT (mA)
12
10
6
2
8
4
0500 900300 700
233818 F11
1000
400 800200 600100
VDD
OVDD
LTC2338-18
17
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Normal Mode, Single Device
When CHAIN = 0, the LTC2338-18 operates in normal
mode. In normal mode, RDL/SDI enables or disables the
serial data output pin SDO. If RDL/SDI is high, SDO is in
high impedance. If RDL/SDI is low, SDO is driven. Figure12
shows a single LTC2338-18 operated in normal mode
with CHAIN and RDL/SDI tied to ground. With RDL/SDI
grounded, SDO is enabled and the MSB(D17) of the new
conversion data is available at the falling edge of BUSY.
This is the simplest way to operate the LTC2338-18.
Figure 12. Using a Single LTC2338-18 in Normal Mode
CNV
LTC2338-18
BUSY
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
SDO
SCK
233818 F13a
RDL/SDI
CHAIN
233818 F12
CONVERT CONVERT
tACQ
tACQ = tCYC – tCONV – tBUSYLH
NAP AND ACQUIRENAP AND ACQUIRE
CNV
CHAIN = 0
BUSY
SCK
SDO
RDL/SDI = 0
tBUSYLH
tDSDOBUSYL
tSCK
tHSDO
tSCKH tQUIET
tSCKL
tDSDO
tCONV
tCNVH
tCYC
tCNVL
D17 D16 D15 D1 D0
1 2 3 16 17 18
LTC2338-18
18
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Normal Mode, Multiple Devices
Figure 13 shows multiple LTC2338-18 devices operating
in normal mode (CHAIN = 0) sharing CNV, SCK and SDO.
By sharing CNV, SCK and SDO, the number of required
signals to operate multiple ADCs in parallel is reduced.
Since SDO is shared, the RDL/SDI input of each ADC must
be used to allow only one LTC2338-18 to drive SDO at a
time in order to avoid bus conflicts. As shown in Figure 13,
the RDL/SDI inputs idle high and are individually brought
low to read data out of each device between conversions.
When RDL/SDI is brought low, the MSB of the selected
device is output onto SDO.
Figure 13. Normal Mode with Multiple Devices Sharing CNV, SCK, and SDO
233818 F13
D17A
SDO
SCK
CNV
BUSY
CHAIN = 0
RDL/SDIB
RDL/SDIA
D17BD16BD1BD0B
D15B
D16AD15AD1AD0A
Hi-Z Hi-ZHi-Z
tEN
tHSDO
tDSDO tDIS
tSCKL
tSCKH
tCNVL
1 2 3 16 17 18 19 20 21 34 35 36
tSCK
CONVERT
CONVERT
tQUIET
tCONV
tBUSYLH
NAP AND ACQUIRE
NAP AND
ACQUIRE
233818 F13a
RDLB
RDLA
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2338-18
SDO
A
SCK
RDL/SDI
CNV
LTC2338-18
SDO
B
SCK
RDL/SDI
CHAIN BUSY
CHAIN
LTC2338-18
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Chain Mode, Multiple Devices
When CHAIN = OVDD, the LTC2338-18 operates in
chain mode. In chain mode, SDO is always enabled and
RDL/SDI serves as the serial data input pin (SDI) where
daisy-chain data output from another ADC can be input.
This is useful for applications where hardware constraints
may limit the number of lines needed to interface to a large
number of converters. Figure 14 shows an example with
two daisy-chained devices. The MSB of converter A will
appear at SDO of converter B after 18 SCK cycles. The
MSB of converter A is clocked in at the SDI/RDL pin of
converter B on the rising edge of the first SCK.
Figure 14. Chain Mode Timing Diagram
OVDD
233818 F14a
CONVERT
IRQ
DATA IN
DIGITAL HOST
CLK
CNV
LTC2338-18
BUSY
SDO
B
SCK
RDL/SDI
CNV
LTC2338-18
SDO
A
SCK
RDL/SDI
CHAIN
OV
DD
CHAIN
233818 F14
D0A
D1A
D16A
D17A
D15B
D16B
D17B
SDOB
SDOA = RDL/SDIB
RDL/SDIA = 0
D0B
D1B
D15A
D16A
D17AD0A
D1A
1 2 3 16 17 18 19 20 34 35 36
tDSDOBUSYL
tSSDISCK
tHSDISCK
tBUSYLH
tCONV
tHSDO
tDSDO
tSCKL
tSCKH
tSCKCH
tCNVL
tCYC
CONVERT
CONVERT
SCK
CNV
BUSY
CHAIN = OV
DD
tQUIET
NAP AND ACQUIRE
NAP AND
ACQUIRE
LTC2338-18
20
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For more information www.linear.com/LTC2338-18
APPLICATIONS INFORMATION
Sleep Mode
To enter sleep mode, toggle CNV twice with no intervening
rising edge on SCK as shown in Figure 15. The part will
enter sleep mode on the falling edge of BUSY from the
last conversion initiated. Once in sleep mode, a rising edge
on SCK will wake the part up. Upon emerging from sleep
mode, wait tWAKE seconds before initiating a conversion
to allow the reference and reference buffer to wake up
and charge the bypass capacitors at REFIN and REFBUF.
Figure 15. Sleep Mode Timing Diagram
233818 F15
CONVERT CONVERTSLEEP
NAP AND
ACQUIRE
CNV
BUSY
SCK
tBUSYLH
tWAKE
tCONV
tCNVH
CONVERT CONVERTSLEEP
NAP AND
ACQUIRE
NAP AND
ACQUIRE
CNV
BUSY
SCK
tBUSYLH
tWAKE
tCONV
CONVERT
tCONV
tCNVH
CHAIN = DON’T CARE
RDL/SDI = DON’T CARE
CHAIN = DON’T CARE
RDL/SDI = DON’T CARE
LTC2338-18
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For more information www.linear.com/LTC2338-18
BOARD LAYOUT
To obtain the best performance from the LTC2338-18 a
printed circuit board (PCB) is recommended. Layout for the
PCB should ensure the digital and analog signal lines are
separated as much as possible. In particular, care should
be taken not to run any digital clocks or signals alongside
analog signals or underneath the ADC.
Recommended Layout
The following is an example of a recommended PCB layout.
A single solid ground plane is used. Bypass capacitors to
the supplies are placed as close as possible to the supply
pins. Low impedance common returns for these bypass
capacitors are essential to the low noise operation of the
ADC. The analog input traces are screened by ground.
For more details and information refer to DC1908, the
evaluation kit for the LTC2338-18.
Partial Top Silkscreen
Partial Layer 1 Component Side
LTC2338-18
22
233818fa
For more information www.linear.com/LTC2338-18
BOARD LAYOUT
Partial Layer 2 Ground Plane
Partial Layer 3 Power Plane
Partial Layer 4 Bottom Layer
LTC2338-18
23
233818fa
For more information www.linear.com/LTC2338-18
BOARD LAYOUT
Partial Schematic of Demoboard
100MHz MAX
CLK IN
3.3VPP
AIN+
AIN-
INT
EXT
REF
VREF
WP
PROG
DC590
EEPROM
SDO
SCK
CNV
RDL
BUSY
DB17 DB16
9V-10V
(NC)
BYPASS CAPS FOR U10
+ / - 10.24V
+ / - 10.24V
*
VREF
+3.3V +8.6V
+3.3V +3.3V
+5V
+3.3V
+3.3V
+3.3V
+3.3V +3.3V
+3.3V
V+
V-
V+V-
CLK
DB0
DB1
DB15
DB10
DB11
DB12
DB13
DB14
DB5
DB6
DB7
DB8
DB9
DB3
DB4
DB2
DB17
DB16
CLKOUT
DC590_DETECT
CNVST_33
CNV
SCK
SDO
BUSY
RDL
SCK
CNV
SDO
C48
10uF
6.3V
C48
10uF
6.3V
C15
0.1uF
C15
0.1uF
R8
33 OHM
R8
33 OHM
R32 0 OHMR32 0 OHM
C14
0.1uF
C14
0.1uF
C4 0.1uFC4 0.1uF
JP1JP1
1
2
3
U3
NL17SZ74
U3
NL17SZ74
CP
1
D
2
Q
3
GND
4
Q
5
CLR
6
PR
7
VCC
8
R2
1K
R2
1K
C39
OPT
1206
C39
OPT
1206
R4
33 OHM
R4
33 OHM
TP4TP4
C20
47uF
1210
10V
C20
47uF
1210
10V
C3 0.1uFC3 0.1uF
J3J3
1
3
2
4
5 6
7 8
910
11
13
12
14
C42
OPT
0603
C42
OPT
0603
R12
4.99K
R12
4.99K
R6
1K
R6
1K
C7
0.1uF
C7
0.1uF
C57 0.1uF 25VC57 0.1uF 25V
R9
0 OHM
R9
0 OHM
C58
OPT
C58
OPT
C18
OPT
0603
C18
OPT
0603
C12
0.1uF
C12
0.1uF
C2
0.1uF
C2
0.1uF
R10
4.99K
R10
4.99K
+
-
U10B
LT1469CS8
+
-
U10B
LT1469CS8
5
6
7
C44
1.0uF
25V
C44
1.0uF
25V
C11
10uF
C11
10uF
U1
LTC233X- CMS
U1
LTC233X- CMS
4
IN+
5
IN-
VDD
2
GND
3
CHAIN
10
GND
6
REFBUF
7
REFIN
8
CNV
9
VDDLBYP
1
BUSY
11
RDL/SDI
12
SCK
13
SDO
14
OVDD
15
GND
16
C5
0.1uF
C5
0.1uF
R40 4.99KR40 4.99K
R3
33 OHM
R3
33 OHM
TP3TP3
R35 0 OHMR35 0 OHM
U15
LTC6655BHMS8-5
U15
LTC6655BHMS8-5
VIN
2
SHDN
1
GND
3
OUTF
7
GND
8
GND
4
OUTS
6
GND
5
TP2TP2
R36
0 OHM
R36
0 OHM
TP6TP6
R11
4.99K
R11
4.99K
U4
NC7SVU04P5X
U4
NC7SVU04P5X
4
53
2
R37
OPT
R37
OPT
R13
1K
R13
1K
JP2JP2
1
2
3
C19
OPT
0805
C19
OPT
0805
C61
OPT
C61
OPT
R1
33 OHM
R1
33 OHM
R31
OPT
R31
OPT
C59
1.0uF
50V
C59
1.0uF
50V
C56
0.1uF
C56
0.1uF
TP7TP7
-
+
U10A
LT1469CS8
-
+
U10A
LT1469CS8
1
2
3
84
R15
OPT
R15
OPT
C40
OPT
1206
C40
OPT
1206
TP1TP1
J1
BNC
J1
BNC
R41
4.99K
R41
4.99K
C6
10uF
6.3V
C6
10uF
6.3V
E3E3
R14 0 OHMR14 0 OHM
C55 1.0uF 50VC55 1.0uF 50V
TP5TP5
C9
10uF
6.3V
C9
10uF
6.3V
P1
CON-EDGE40-100
P1
CON-EDGE40-100
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
29
29
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
38
38
39
39
40
40
C46
2.2uF
10V
C46
2.2uF
10V
C49 100pFC49 100pF
R7
1K
R7
1K
C60
0.1uF
25V
C60
0.1uF
25V
J6
BNC
J6
BNC
J4
BNC
J4
BNC
R5
49.9
1206
R5
49.9
1206
R16
OPT
R16
OPT
C43
0.1uF
25V
C43
0.1uF
25V
U2
NC7SVU04P5X
U2
NC7SVU04P5X
4
53
2
R38
OPT
R38
OPT
C13
0.1uF
C13
0.1uF
U8
NC7SZ04P5X
U8
NC7SZ04P5X
4
53
2
C10
0.1uF
C10
0.1uF
U7
24LC024-I /ST
U7
24LC024-I /ST
A0
1
A1
2
A2
3
VSS
4
SDA
5
SCL
6
WP
7
VCC
8
U6
NC7SZ66P5X
U6
NC7SZ66P5X
1
A
2
B
GND
3
4
OE
VCC
5
U9
NC7SZ04P5X
U9
NC7SZ04P5X
4
53
2
C17
0.1uF
C17
0.1uF
C16
0.1uF
C16
0.1uF
R39 0 OHMR39 0 OHM
R34 OPTR34 OPT R17
2K
R17
2K
R33 0 OHMR33 0 OHM
C47
OPT
0603
C47
OPT
0603
C1
0.1uF
C1
0.1uF
LTC2338-18
24
233818fa
For more information www.linear.com/LTC2338-18
PACKAGE DESCRIPTION
MSOP (MS16) 1107 REV Ø
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
16151413121110
12345678
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120
±.0015)
TYP
0.50
(.0197)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
Please refer to http://www.linear.com/product/LTC2338-18#packaging for the most recent package drawings.
LTC2338-18
25
233818fa
For more information www.linear.com/LTC2338-18
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 08/16 Updated graphs G01, G02, and G03 6
LTC2338-18
26
233818fa
For more information www.linear.com/LTC2338-18
LINEAR TECHNOLOGY CORPORATION 2013
LT 0816 REV A • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2338-18
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC2379-18/LTC2378-18/
LTC2377-18/LTC2376-18
18-Bit, 1.6Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
2.5V Supply, Differential Input, 101.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2380-16/LTC2378-16/
LTC2377-16/LTC2376-16
16-Bit, 2Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
2.5V Supply, Differential Input, 96.2dB SNR, ±5V Input Range, DGC,
Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2369-18/LTC2368-18/
LTC2367-18/LTC2364-18
18-Bit, 1.6Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 96.5dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2370-16/LTC2368-16/
LTC2367-16/LTC2364-16
16-Bit, 2Msps/1Msps/500ksps/250ksps
Serial, Low Power ADC
2.5V Supply, Pseudo-Differential Unipolar Input, 94dB SNR, 0V to 5V Input
Range, Pin-Compatible Family in MSOP-16 and 4mm × 3mm DFN-16 Packages
LTC2389-18/LTC2389-16 18-Bit/16-Bit, 2.5Msps Parallel/Serial ADC 5V Supply, Pin-Configurable Input Range, 99.8dB/96dB SNR, Parallel or Serial
I/O 7mm × 7mm LQFP-48 and QFN-48 Packages
LTC1609 16-Bit, 200ksps Serial ADC ±10V, Configurable Unipolar/Bipolar Input, Single 5V Supply, SSOP-28 and
SO-20 Packages
LTC1606/LTC1605 16-Bit, 250ksps/100ksps Parallel ADCs ±10V Input, 5V Supply, 75mW/55mW, SSOP-28 and SO-28 Packages
LTC1859/LTC1858/
LTC1857
16-/14-/12-Bit, 8-Channel 100ksps Serial
ADCs
±10V, SoftSpan™, Single-Ended or Differential Inputs, Single 5V Supply,
SSOP-28 Package
DACs
LTC2756/LTC2757 18-Bit, Single Serial/Parallel IOUT SoftSpan
DAC
±1LSB INL/DNL, Software-Selectable Ranges, SSOP-28/7mm × 7mm LQFP-48
Package
LTC2641 16-Bit/14-Bit/12-Bit Single Serial VOUT DAC ±1LSB INL /DNL, MSOP-8 Package, 0V to 5V Output
LTC2630 12-Bit/10-Bit/8-Bit Single VOUT DACs Internal Reference, ±1LSB INL (12 Bits), SC70 6-Pin Package
References
LTC6655 Precision Low Drift Low Noise Buffered
Reference
5V/2.5V/2.048V/1.2V, 2ppm/°C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package
LTC6652 Precision Low Drift Low Noise Buffered
Reference
5V/2.5V/2.048V/1.2V, 5ppm/°C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package
Amplifiers
LT1468/LT1469 Single/Dual 90MHz, 22V/μs, 16-Bit Accurate
Op Amp
Low Input Offset: 75μV/125µV
LT1469
–15V
233818 TA02
1
7
4
8
2
3
–
+
–
+
4.99k
LTC2338-18
IN+VDD
5V
IN–
–10.24V
10.24V
0V
–10.24V
10.24V
0V
–10.24V
10.24V
0V
15V
6
5
4.99k
47µF
REFBUF
100nF
REFIN
LT1469 Configured to Convert a ±10.24V Single-Ended Signal to a ±20.48V Differential Signal