IS41LV16400-50TE - Integrated Silicon Solution, Inc.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

IS41LV16400 ISSI®

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

FEATURES

• Extended Data-Out (EDO) Page Mode access cycle

• TTL compatible inputs and outputs; tristate I/O

• Refresh Interval: 4,096 cycles / 64 ms

• Auto refresh Mode: RAS-Only, CAS-before-RAS

(CBR), and Hidden

• Low Standby power dissipation:

– 1.8mW(max) CMOS Input Level

• Single power supply: 3.3V ± 10%

• Byte Write and Byte Read operation via two CAS

• Extended Temperature Range -30oC to 85oC

• Industrail Temperature Range -40oC to 85oC

DESCRIPTION

The ISSI IS41LV16400 is 4,194,304 x 16-bit high-perfor-

mance CMOS Dynamic Random Access Memories.

These devices offer an accelerated cycle access called

EDO Page Mode. EDO Page Mode allows 1,024 random

accesses within a single row with access cycle time as

short as 20 ns per 16-bit word. The Byte Write control, of

upper and lower byte, makes the IS41LV16400 ideal for

use in 16-bit wide data bus systems.

These features make the S41LV16400 ideally suited for

high-bandwidth graphics, digital signal processing,

high-performance computing systems, and peripheral

applications.

The IS41LV16400 is packaged in a 50-pin TSOP (Type II).

JEDEC standard pinout.

4M x 16 (64-MBIT) DYNAMIC RAM

WITH EDO PAGE MODE

KEY TIMING PARAMETERS

Parameter -50 -60 Unit

Max. RAS Access Time (tRAC)

50 60 ns

Max. CAS Access Time (tCAC)

13 15 ns

Max. Column Address Access Time (tAA)

25 30 ns

Min. EDO Page Mode Cycle Time (tPC)

20 25 ns

Min. Read/Write Cycle Time (tRC)

84 104 ns

NOVEMBER 1999

PIN CONFIGURATION

50-Pin TSOP (Type II)

VCC

I/O0

I/O1

I/O2

I/O3

VCC

I/O4

I/O5

I/O6

I/O7

VCC

RAS

VCC

GND

I/O15

I/O14

I/O13

I/O12

GND

I/O11

I/O10

I/O9

I/O8

GND

LCAS

UCAS

A11

A10

GND

PIN DESCRIPTIONS

A0-A11 Address Inputs

I/O0-15 Data Inputs/Outputs

WE Write Enable

OE Output Enable

RAS Row Address Strobe

UCAS Upper Column Address Strobe

LCAS Lower Column Address Strobe

Vcc Power

GND Ground

NC No Connection

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

FUNCTIONAL BLOCK DIAGRAM

LCAS

UCAS CAS WE

DATA I/O BUS

COLUMN DECODERS

SENSE AMPLIFIERS

MEMORY ARRAY

4,194,304 x 16

ROW DECODER

DATA I/O BUFFERS

CAS

CLOCK

GENERATOR

CONTROL

LOGICS

CONTROL

LOGIC

I/O0-I/O15

RAS RAS

A0-A11

RAS

CLOCK

GENERATOR

REFRESH

COUNTER

ADDRESS

BUFFERS

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

TRUTH TABLE

Function RAS LCAS UCAS WE OE Address tR/tCI/O

Standby

HHHXX X

High-Z

Read: Word

LLLHL

ROW/COL

DOUT

Read: Lower Byte

LLHHL

ROW/COL

Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte

LHLHL

ROW/COL

Lower Byte, High-Z

Upper Byte, DOUT

Write: Word (Early Write)

LLLLX

ROW/COL

DIN

Write: Lower Byte (Early Write)

LLHLX

ROW/COL

Lower Byte, DIN

Upper Byte, High-Z

Write: Upper Byte (Early Write)

LHLLX

ROW/COL

Lower Byte, High-Z

Upper Byte, DIN

Read-Write

(1,2)

LLL

H→LL

→H

ROW/COL

DOUT, DIN

EDO Page-Mode Read

(2)

1st Cycle:

H→LH

→L

ROW/COL

DOUT

2nd Cycle:

H→LH

→L

NA/COL

DOUT

Any Cycle:

L→HL

→H

NA/COL

DOUT

EDO Page-Mode Write

(1)

1st Cycle:

H→LH

→L

ROW/COL

DIN

2nd Cycle:

H→LH

→L

NA/COL

DIN

EDO Page-Mode

(1,2)

1st Cycle:

H→LH

→LH

→LL

→H

ROW/COL

DOUT, DIN

Read-Write 2nd Cycle:

H→LH

→LH

→LL

→H

NA/COL

DOUT, DIN

Hidden Refresh Read

(2)

L→H→L

LLHL

ROW/COL

DOUT

Write

(1,3)

L→H→L

LLLX

ROW/COL

DOUT

RAS-Only Refresh

LHHXX

ROW/NA

High-Z

CBR Refresh

(4)

H→L

LLXX X

High-Z

Notes:

1 . These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2 . These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3 . EARLY WRITE only.

4 . At least one of the two CAS signals must be active (LCAS or UCAS).

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

FUNCTIONAL DESCRIPTION

The IS41LV16400 is a CMOS DRAM optimized for

high-speed bandwidth, low power applications. During

READ or WRITE cycles, each bit is uniquely addressed

through the 22 address bits: 12 row address bits (A0~A11)

and 10 column address bits (A0~A9). The row address is

latched by the Row Address Strobe (RAS). The column

address is latched by the Column Address Strobe (CAS).

RAS is used to latch the first twelve bits and CAS is used

the latter ten bits.

The IS41LV16400 has two CAS controls, LCAS and

UCAS. The LCAS and UCAS inputs internally generates

a CAS signal functioning in an identical manner to the

single CAS input on the other 4M x 16 DRAMs. The key

difference is that each CAS controls its corresponding

I/O tristate logic (in conjunction with OE and WE and

RAS). LCAS controls I/O0 through I/O7 and UCAS

controls I/O8 through I/O15.

The IS41LV16400 CAS function is determined by the first

CAS (LCAS or UCAS) transitioning LOW and the last

transitioning back HIGH. The two CAS controls give the

IS41LV16400 both BYTE READ and BYTE WRITE cycle

capabilities.

Memory Cycle

A memory cycle is initiated by bring RAS LOW and it is

terminated by returning both RAS and CAS HIGH. To

ensures proper device operation and data integrity any

memory cycle, once initiated, must not be ended or

aborted before the minimum tRAS time has expired. A new

cycle must not be initiated until the minimum precharge

time tRP, tCP has elapsed.

Read Cycle

A read cycle is initiated by the falling edge of CAS or OE,

whichever occurs last, while holding WE HIGH. The

column address must be held for a minimum time

specified by tAR. Data Out becomes valid only when tRAC,

tAA, tCAC and tOEA are all satisfied. As a result, the access

time is dependent on the timing relationships between

these parameters.

Write Cycle

A write cycle is initiated by the falling edge of CAS and

WE, whichever occurs last. The input data must be valid

at or before the falling edge of CAS or WE, whichever

occurs last.

Refresh Cycle

To retain data, 4,096 refresh cycles are required in each

64 ms period. There are two ways to refresh the memory.

1. By clocking each of the 4,096 row addresses (A0

through A11) with RAS at least once every 64 ms. Any

read, write, read-modify-write or RAS-only cycle

refreshes the addressed row.

2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS

refresh is activated by the falling edge of RAS, while

holding CAS LOW. In CAS-before-RAS refresh cycle,

an internal 12-bit counter provides the row addresses

and the external address inputs are ignored.

CAS-before-RAS is a refresh-only mode and no data

access or device selection is allowed. Thus, the output

remains in the High-Z state during the cycle.

Extended Data Out Page Mode

EDO page mode operation permits all 1,024 columns

within a selected row to be randomly accessed at a high

data rate.

In EDO page mode read cycle, the data-out is held to the

next CAS cycle’s falling edge, instead of the rising edge.

For this reason, the valid data output time in EDO page

mode is extended compared with the fast page mode. In

the fast page mode, the valid data output time becomes

shorter as the CAS cycle time becomes shorter. There-

fore, in EDO page mode, the timing margin in read cycle

is larger than that of the fast page mode even if the CAS

cycle time becomes shorter.

In EDO page mode, due to the extended data function, the

CAS cycle time can be shorter than in the fast page mode

if the timing margin is the same.

The EDO page mode allows both read and write

operations during one RAS cycle, but the performance is

equivalent to that of the fast page mode in that case.

Power-On

After application of the VCC supply, an initial pause of

200 µs is required followed by a minimum of eight

initialization cycles (any combination of cycles containing

a RAS signal).

During power-on, it is recommended that RAS track with

VCC or be held at a valid VIH to avoid current surges.

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Parameters Rating Unit

VTVoltage on Any Pin Relative to GND –0.5 to +4.6 V

VCC Supply Voltage –0.5 to +4.6 V

IOUT Output Current 50 mA

PDPower Dissipation 1 W

TACommercial Operation Temperature 0 to +70 °C

Extended Temperature –30 to +85 °C

Industrail Temperature –40 to +85 °C

TSTG Storage Temperature –55 to +125 °C

Note:

1 . Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 3.0 3.3 3.6V V

VIH Input High Voltage 2.0 —VCC + 0.3 V

VIL Input Low Voltage –0.3 —0.8 V

TACommercial Ambient Temperature 0 —70 °C

Extended Ambient Temperature –30 —85 °C

Industrail Ambient Temperature –40 —85 °C

CAPACITANCE(1,2)

Symbol Parameter Max. Unit

CIN1Input Capacitance: A0-A11 5 pF

CIN2Input Capacitance: RAS, UCAS, LCAS, WE, OE 7pF

CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF

Notes:

1. Tested initially and after any design or process changes that may affect these parameters.

2 . Test conditions: TA = 25°C, f = 1 MHz.

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter Test Condition Speed Min. Max. Unit

IIL Input Leakage Current Any input 0V ≤ VIN ≤ Vcc –55µA

Other inputs not under test = 0V

IIO Output Leakage Current Output is disabled (Hi-Z) –55µA

0V ≤ VOUT ≤ Vcc

VOH Output High Voltage Level IOH = –2.0 mA 2.4 —V

VOL Output Low Voltage Level IOL = 2.0 mA —0.4 V

ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commerical —1mA

Extended —2mA

Industrial —2mA

ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V —0.5 mA

ICC3 Operating Current: RAS, LCAS, UCAS, -50 —160 mA

Random Read/Write(2,3,4) Address Cycling, tRC = tRC (min.) -60 —145

Average Power Supply Current

ICC4 Operating Current: RAS = VIL, LCAS, UCAS, -50 —90 mA

EDO Page Mode(2,3,4) Cycling tPC = tPC (min.) -60 —80

Average Power Supply Current

ICC5 Refresh Current: RAS Cycling, LCAS, UCAS ≥ VIH -50 —160 mA

RAS-Only(2,3) tRC = tRC (min.) -60 —145

Average Power Supply Current

ICC6 Refresh Current: RAS, LCAS, UCAS Cycling -50 —160 mA

CBR(2,3,5) tRC = tRC (min.) -60 —145

Average Power Supply Current

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4 . Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

319 Ω

50 pF

Including

jig and

scope

353 Ω

OUTPUT

3.3V

AC TEST CONDITIONS

Output load: One TTL Load and 50 pF

Input timing reference levels: VIH = 2.0V, VIL = 0.8V

Output timing reference levels: VOH = 2.0V, VOL = 0.8V

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

AC CHARACTERISTICS(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50 -60

Symbol Parameter Min. Max. Min. Max. Units

tRC Random READ or WRITE Cycle Time 84 —104 —ns

tRAC Access Time from RAS(6, 7) —50 —60 ns

tCAC Access Time from CAS(6, 8, 15) —13 —15 ns

tAA Access Time from Column-Address(6) —25 —30 ns

tRAS RAS Pulse Width 50 10K 60 10K ns

tRP RAS Precharge Time 30 —40 —ns

tCAS CAS Pulse Width(26) 8 10K 10 10K ns

tCP CAS Precharge Time(9, 25) 9—9—ns

tCSH CAS Hold Time (21) 38 —40 —ns

tRCD RAS to CAS Delay Time(10, 20) 12 37 14 45 ns

tASR Row-Address Setup Time 0 —0—ns

tRAH Row-Address Hold Time 8 —10 —ns

tASC Column-Address Setup Time(20) 0—0—ns

tCAH Column-Address Hold Time(20) 8—10 —ns

tAR Column-Address Hold Time 30 —40 —ns

(referenced to RAS)

tRAD RAS to Column-Address Delay Time(11) 10 25 12 30 ns

tRAL Column-Address to RAS Lead Time 25 —30 —ns

tRPC RAS to CAS Precharge Time 5 —5—ns

tRSH RAS Hold Time(27) 8—10 —ns

tRHCP RAS Hold Time from CAS Precharge 37 —37 —ns

tCLZ CAS to Output in Low-Z(15, 29) 0—0—ns

tCRP CAS to RAS Precharge Time(21) 5—5—ns

tOD Output Disable Time(19, 28, 29) 315 315 ns

tOE Output Enable Time(15, 16) —13 —15 ns

tOED Output Enable Data Delay (Write) 20 —20 —ns

tOEHC OE HIGH Hold Time from CAS HIGH 5 —5—ns

tOEP OE HIGH Pulse Width 10 —10 —ns

tOES OE LOW to CAS HIGH Setup Time 5 —5—ns

tRCS Read Command Setup Time(17, 20) 0—0—ns

tRRH Read Command Hold Time 0 —0—ns

(referenced to RAS)(12)

tRCH Read Command Hold Time 0 —0—ns

(referenced to CAS)(12, 17, 21)

tWCH Write Command Hold Time(17, 27) 8—10 —ns

tWCR Write Command Hold Time 40 —50 —ns

(referenced to RAS)(17)

tWP Write Command Pulse Width(17) 8—10 —ns

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)

(Recommended Operating Conditions unless otherwise noted.)

-50 -60

Symbol Parameter Min. Max. Min. Max. Units

tWPZ WE Pulse Widths to Disable Outputs 10 —10 —ns

tRWL Write Command to RAS Lead Time(17) 13 —15 —ns

tCWL Write Command to CAS Lead Time(17, 21) 8—10 —ns

tWCS Write Command Setup Time(14, 17, 20) 0—0—ns

tDHR Data-in Hold Time (referenced to RAS)39—39 —ns

tACH Column-Address Setup Time to CAS 15 —15 —ns

Precharge during WRITE Cycle

tOEH OE Hold Time from WE during 8 —10 —ns

READ-MODIFY-WRITE cycle(18)

tDS Data-In Setup Time(15, 22) 0—0—ns

tDH Data-In Hold Time(15, 22) 8—10 —ns

tRWC READ-MODIFY-WRITE Cycle Time 108 —133 —ns

tRWD RAS to WE Delay Time during 64 —77 —ns

READ-MODIFY-WRITE Cycle(14)

tCWD CAS to WE Delay Time(14, 20) 26 —32 —ns

tAWD Column-Address to WE Delay Time(14) 39 —47 —ns

tPC EDO Page Mode READ or WRITE 20 —25 —ns

Cycle Time(24)

tRASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns

tCPA Access Time from CAS Precharge(15) —30 —35 ns

tPRWC EDO Page Mode READ-WRITE 56 —68 —ns

Cycle Time(24)

tCOH Data Output Hold after CAS LOW 5 —5—ns

tOFF Output Buffer Turn-Off Delay from 1.6 12 1.6 15 ns

CAS or RAS(13,15,19, 29)

tWHZ Output Disable Delay from WE 310 310 ns

tCLCH Last CAS going LOW to First CAS 10 —10 —ns

returning HIGH(23)

tCSR CAS Setup Time (CBR REFRESH)(30, 20) 5—5—ns

tCHR CAS Hold Time (CBR REFRESH)(30, 21) 8—10 —ns

tORD OE Setup Time prior to RAS during 0 —0—ns

HIDDEN REFRESH Cycle

tREF Refresh Period (4,096 Cycles) —64 —64 ms

tTTransition Time (Rise or Fall)(2, 3) 150 150 ns

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

Notes:

1 . An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and

VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a

monotonic manner.

4. If CAS and RAS = VIH, data output is High-Z.

5. If CAS = VIL, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.

7 . Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by

the amount that tRCD exceeds the value shown.

8. Assumes that tRCD ≥ tRCD (MAX).

9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data

output buffer, CAS and RAS must be pulsed for tCP.

1 0. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is

greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.

11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is

greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.

12. Either tRCH or tRRH must be satisfied for a READ cycle.

13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.

14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS

(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN),

tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected

cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is

indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.

15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as WE going low.

18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure

that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and

OE is taken back to LOW after tOEH is met.

1 9 . The I/Os are in open during READ cycles once tOD or tOFF occur.

20 . The first χCAS edge to transition LOW.

2 1. The last χCAS edge to transition HIGH.

2 2. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

2 3. Last falling χCAS edge to first rising χCAS edge.

2 4. Last rising χCAS edge to next cycle’s last rising χCAS edge.

2 5. Last rising χCAS edge to first falling χCAS edge.

26. Each χCAS must meet minimum pulse width.

27. Last χCAS to go LOW.

28. I/Os controlled, regardless UCAS and LCAS.

29. The 3 ns minimum is a parameter guaranteed by design.

30. Enables on-chip refresh and address counters.

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

READ CYCLE

Note:

1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

tRAS tRC tRP

tAR

tCAH

tASC

tRAD tRAL

I/O

ADDRESS

UCAS/LCAS

RAS

Row Column Row

Open Open

Valid Data

tCSH

tCAS

tRSH

tCRP tCLCH

tRCD

tRAHtASR

tRRH

tRCHtRCS

tAA

tCAC tOFF(1)

tRAC

tCLC

tOES

tOE tOD

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

EARLY WRITE CYCLE (OE = DON'T CARE)

RAS

CAH

ASC

RAD

RAL

ACH

I/O

ADDRESS

UCAS/LCAS

RAS

Row Column Row

CSH

CAS

RSH

CRP

CLCH

RCD

RAH

ASR

CWL

WCR

WCH

RWL

WCS

DHR

Valid Data

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)

tRAS

tRWC tRP

tAR

tCAH

tASC

tRAD tRAL

tACH

ADDRESS

UCAS/LCAS

RAS

Row Column Row

tCSH

tCAS

tRSH

tCRP tCLCH

tRCD

tRAHtASR

tRWD tCWL

tCWD tRWL

tAWD tWP

tRCS

tCAC

tCLZ tDS tDH

tOEHtOD

tOE

tRAC tAA

I/O Open Open

Valid DOUT Valid DIN

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

EDO-PAGE-MODE READ CYCLE

Note:

1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the tPC specifications.

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCAS,

tCLCH

tCRP tRCD

tCSH tCP tCAS,

tCLCH

tCAH

tCAS,

tCLCH

tRAL

tRSH tCPtCP

tPC(1)

tASR

tRAH

tRAD

tAR

Column Column

tCAHtCAH

Column

tASCtASC

I/O

Open Open

Valid Data

tAA tAA

tCPA

tCAC tCAC

tRAC

tCOHtCLZ

tOEP

tOE

tOES tOES tOD

tOEtOEHC

Valid Data

tRCH tRRH

tAA

tCPA

tCAC tOFFtCLZ

Valid Data

tOD

tASC

tRCS

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

EDO-PAGE-MODE EARLY-WRITE CYCLE

RASP

ADDRESS

UCAS/LCAS

RAS

Row Row

CAS,

CLCH

CRP

RCD

CSH

CAS,

CLCH

CAH

CAS,

CLCH

RAL

RSH

ASR

RAH

RAD

ACH

Column Column

ACH

CAH

Column

ASC

I/O

Valid Data

ASC

WCS

WCH

CWL

RHCP

WCS

WCH

CWL

DHR

WCR

WCS

WCH

CWL

Valid Data

RWL

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)

Note:

1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both

measurements must meet the tPC specifications.

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCRP tRCD

tCSH tCP

tCAH

tCAS, tCLCH

tRAL

tRSH tCPtCP

tRAH

tRAD

tAR

tASR

Column Column

tCAHtCAH

Column

tASCtASC

tCAS, tCLCHtCAS, tCLCH

I/O

tASC

tRWD

tRCS tCWL

tWP

tAWD

tCWD

tDH

tDS

tCAC

tCLZ

tAWD

tCWD

tCWL

tWP tAWD

tCWD

tCWL

tRWL

tWP

Open Open

OUT

tOE tOE tOE tOD tOEH

tOD tOD

tDH

tDS tCPA

tAA

tCAC

tCLZ

OUT

tDH

tDS

tCAC

tCLZ

OUT

tCPA

tAA

tRAC tAA

tPC / tPRWC

(1)

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)

tRASP tRP

ADDRESS

UCAS/LCAS

RAS

Row Row

tCRP tRCD

tPC

tCSH

tCP

tCAH

tCAS

tRAL

tRSH tCPtCP

tACH

tRAH

tRAD

tAR

tASR

Column (A) Column (N)

tCAHtCAH

Column (B)

tASCtASC

tCAS tCAS

I/O

tASC

tCAC

tRCH

tDH

Open Open

Valid Data (A)

tOE

tWCS

tCAC

tCOH

DIN

tCPA

tWCH

tRAC tAA

tPC

Valid Data (B)

tWHZ

tDS

tRCS

tAA

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

AC WAVEFORMS

READ CYCLE (With WE-Controlled Disable)

RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)

tAR

tCAH tASC

tASC

tRAD

I/O

ADDRESS

UCAS/LCAS

RAS

Row Column

Open Open

Valid Data

tCSH tCAS

tCRP tRCD tCP

tRAHtASR

tRCH tRCStRCS

tAA

tCAC tWHZ

tRAC

tCLZ

tOE tOD

Column

RAS

I/O

ADDRESS

UCAS/LCAS

RAS

Row Row

Open

CRP

RAH

ASR

RPC

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)

CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)

Notes:

1 . A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.

2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.

tRAS tRAStRP tRP

I/O

UCAS/LCAS

RAS

Open

tCP

tRPC tCSR

tCHR tRPC tCSR tCHR

tRAS tRAS

tRP

UCAS/LCAS

RAS

tCRP tRCD tRSH tCHR

tAR

tASC

tRAD

ADDRESS Row Column

tRAHtASR tRAL tCAH

I/O Open Open

Valid Data

tAA

tCAC

tRAC

tCLZ tOFF

(2)

tOE tORD tOD

Undefined

Don’t Care

IS41LV16400 ISSI

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

11/18/99

ORDERING INFORMATION: 5V

Commercial Range: 0°C to 70°C

Speed (ns) Order Part No. Package

50 IS41LV16400-50T 400-mil TSOP (Type II)

60 IS41LV16400-60T 400-mil TSOP (Type II)

ORDERING INFORMATION: 3.3V

Extended Temperature Range: -30°C to 85°C

Speed (ns) Order Part No. Package

50 IS41LV16400-50TE 400-mil TSOP (Type II)

60 IS41LV16400-60TE 400-mil TSOP (Type II)

ISSI

Integrated Silicon Solution, Inc.

2231 Lawson Lane

Santa Clara, CA 95054

Tel: 1-800-379-4774

Fax: (408) 588-0806

E-mail: sales@issi.com

www.issi.com

ORDERING INFORMATION: 3.3V

Industrial Temperature Range: -40°C to 85°C

Speed (ns) Order Part No. Package

50 IS41LV16400-50TI 400-mil TSOP (Type II)

60 IS41LV16400-60TI 400-mil TSOP (Type II)