APLL APLL005 CX2001, CX2002, CX3001, CX3002 Application Notes May, 1999 (c) 1999, Chip Express Corporation. All rights reserved. IMPORTANT NOTICE This document and the product that it describes are the proprietary and confidential property of Chip Express Corporation. They may be distributed and used only under license from Chip Express, and may not be copied without the written consent of chip Express. Chip Express reserves the right to make changes to the contents of this document without notice. Chip Express assumes no responsibility for any errors that appear in this document. Chip Express reserves the right to make changes without notice to any product herein to improve reliability, function or design. Chip Express does not assume any liability arising from the application or use of any product described herein; nor does it convey any license under its patents or copyrights, or any rights of others. LIFE SUPPORT POLICY Chip Express products are not intended for use in life support appliances, devices or systems. The use of a Chip Express product in such applications, without the express written consent of the President of Chip Express, is prohibited. PATENTS The Chip Express Technology is protected by U.S. Patents 4,875,971, 4,924,287, 4,933,738, 4,960,729, 5,049,969, 5,111,273, 5,138,194, 5,260,597, 5,329,152, 5,545,904, 5,565,758 5,619,062 and pending U.S. Patent Applications, as well as corresponding patents and patent applications abroad. TRADEMARKS Chip Express QuICk, QuICk System, OneMask and The Time-to-Market Solution, QYH400TM, QYH500TM, HardArrayTM, LPGA ExpressTM, TwoMaskTM ThreeMaskTM, DQuICkTM, VQuICkTM, The ASIC Time-to-Market Solution, Gate Array ExpressTM, The Best ASIC Solution, Production ExpressTM, and Conversion ExpressTM are trademarks and registered trademarks of Chip Express Corporation. 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Chip Express May, 1999/APLL005 Table of Contents Introduction.........................................................................................................................3 APLL Operation .................................................................................................................4 APLL Components .............................................................................................................6 APLL Applications .............................................................................................................8 System Clock Skew Reduction .......................................................................................8 Frequency Synthesis........................................................................................................9 Multiplying .................................................................................................................9 Division..............................................................................................................11 Arbitrary Frequency Synthesis..................................................................................12 When Skew Reduction Is Not Required....................................................................13 APLL Implementation ......................................................................................................14 APLL Core Pin Description..........................................................................................14 BPLLLOOP Pin Description ........................................................................................14 VDDWELL Pad............................................................................................................14 Integrating An APLL Into A Design .............................................................................15 Placing I/O Pins ............................................................................................................16 Design Considerations ..................................................................................................18 APLL Start-Up Circuit......................................................................................................19 Implementation .............................................................................................................19 Explanations..................................................................................................................20 Verilog Simulation Using APLL.......................................................................................22 Functional Simulation ...................................................................................................22 Monitoring Simulation Values ......................................................................................23 Vector Generation.........................................................................................................25 Error Messages .............................................................................................................25 Troubleshooting ............................................................................................................26 Synthesis and Timing Analysis Using APLL in Synopsys Design Compiler....................27 Dividers requirements ...................................................................................................27 Defining the Clocks ......................................................................................................28 Device Testing ..................................................................................................................29 APLL Test Scheme .......................................................................................................29 VCO Test ..................................................................................................................30 Phase Detector and Charge Pump Test .....................................................................31 APLL Calculations............................................................................................................32 Choosing C and R .........................................................................................................33 Icp and N[3-8]...............................................................................................................33 APLL Spec........................................................................................................................34 APLL Power Calculations ................................................................................................37 APLL Design Requirement Summary...............................................................................39 Appendix A: Receiving APLL Data from auto_apll@chipx.com.....................................40 Chip Express APLL-1 Appendix B: APLL Example ............................................................................................41 Loop Filter Calculations ...............................................................................................42 Appendix C: APLL Available Die Locations ...................................................................43 Appendix D: Input Buffer Compensation .........................................................................44 Appendix E: Known Problems (CX2001/CX2002)..........................................................45 Chip Express APLL-2 Introduction In semiconductor manufacturing, smaller device geometries facilitate greater on-chip density and higher chip performance. System performance is compromised, however, by clock skew, which occurs when the clock on a chip is not synchronized to the system clock. The degree of clock skew varies from chip to chip because of variations in process, temperature, power supply, interconnects, and routing. As shown in Figure 1, an on-chip clock may be faster or slower than the system clock, and the two may be out of phase. An analog phase-locked loop (APLL) can solve these clock skew problems. The APLL tracks the system clock and compares it to the on-chip clock, then adjusts the latter until it matches the former in frequency and phase. Clock-Tree #1 System Clock Clock #1 Clock-Tree #2 Clock #2 Figure 1: System Clock Skew and Delay Problem Chip Express APLL-3 APLL Operation The following terms appear in this explanation of APLL operation: * Lock time: The time it takes the APLL to lock onto the system clock. Fast or slow lock time may be controlled by loop filter characteristics. Varying the R and C components controls Loop filter characteristics. (Remember that R and C define the damping-factor as well.) * Long Term Jitter: The uncertainty time window, due to the presence of noise, during which the rising edge of the feedback signal (vcoclk) occurs (refer to Figure 2). The real rising edge occurs inside this window during many cycles 2 x Long Term Jitter Ideal (expected) rising edge Figure 2: Long Term Jitter * Short Term Jitter: The maximum clock period variation from the ideal period. * Phase error (skew): The mean phase difference between the feedback clock signal (vcoclk) and the system clock (refclk). The maximum phase difference between vcoclk and refclk is defined as phase error plus long term jitter. Chip Express APLL-4 The Chip Express APLL circuitry uses the rising edges of the input signal for phase and frequency detection. When the APLL detects any phase or frequency difference between the system clock and its own clock output, it adjusts the VCO frequency until it matches the system clock, as shown by the waveforms in Figure3. When the refclk and vcoclk are identical, the APLL is locked onto the refclk (refer to Figure 3). When this happens, the APLL continues to monitor the system clock, and if any operating condition, such as a temperature increase or a voltage drop, changes, the APLL adjusts the chip clock to match the system clock again. REFCLK VCOCLK REFCLK is not synchronyzed with VCOCLK, the APLL is not locked REFCLK is synchronyzed with VCOCLK, the APLL is locked Figure 3: APLL clock Waveforms Chip Express APLL-5 APLL Components Figure 4 is a block diagram of the components of an APLL: phase detector, charge pump, voltage-controlled oscillator, and loop filter (the loop filter is implemented as an external passive component). AVDD REFCLK Phase Detector VCOCLK Q Charge Pump Voltage Controlled Oscillator PLL VLFO ZLOOP VLFI ESD Protection BPLLLOOP Pad Loop Filter Figure 4: APLL Functional Block Diagram Phase-Frequency Detector (Phase Detector): The Phase Detector monitors the phase/frequency difference between the refclk and the vcoclk, and generates a control signal when it detects a discrepancy between the two. If the refclk frequency is higher than the vcoclk frequency, its rising edge occurs before (leads) the rising edge of the vcoclk output. When this occurs, the phase detector signals the VCO to increase the frequency of the internal clock. If the rising edge of the refclk occurs after (lags) the rising edge of the vcoclk output, the detector signals the VCO to decrease internal clock frequency. If the frequency and phase of the refclk and vcoclk are the same, the detector does not generate a control signal, so the clock stays in phase. Chip Express APLL-6 Charge Pump: The charge pump converts the phase detector control signal to a change in voltage across the external filter that drives the VCO. As the voltage on the ZLOOP pin increases or decreases, the frequency of the Voltage Controlled Oscillator decreases, or increases respectively. If the voltage remains constant, the frequency of the oscillator remains constant. BPLLLOOP: The BPLLLOOP is a special IO cell that includes only ESD protection device and connects the Loop Filter to APLL. Loop Filter: The control signal that the phase detector generates for the charge pump may generate large excursions (ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The loop filter discrete components should be connected within 1/2 inch of the package pins. Voltage Controlled Oscillator (VCO): The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease as a function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the phase detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the APLL remains locked onto the system clock. Chip Express APLL-7 APLL Applications APLL circuits are used for system clock skew reduction and for frequency synthesis. System Clock Skew Reduction System Clock An internal clock is generated using the VCO-divided output from the APLL to drive an internal clock driver. Figure 5 shows a typical configuration. Input Buffer REFCLK B1 Compensation buffer VCOCLK Q APLL B2 Internal Clock Clock Tree :N Figure 5: Generating an Internal Clock By definition, the APLL keeps VCOCLK synchronized with REFCLK. In order to achieve synchronization between System Clock and Internal Clock, tpd (System Clock REFCLK) should be equal to tpd (Internal Clock VCOCLK) In other words, the delay on the REFCLK path should be compensated by an equal delay on the VCOCLK path. The input buffer (B1) can be compensated by the core logic cell (B2) with similar timing parameters (refer to Appendix C for selection of B1 and B2). In most applications, the internal clock frequency is less than the minimal VCO operating frequency. The :N divider is required to keep the VCO in the specified operating range. N should satisfy the following condition: FVCOmin < Finternal clock x N < FVCOmax Chip Express APLL-8 Frequency Synthesis Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. Multiplying For high-speed applications in high-end designs, transmission line effects cause problems because of parasitics and impedance mismatch among various on-board components. These problems can be greatly reduced by using the high frequency at the chip level only. Internal clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. The divider is placed after the clock tree, as illustrated in Figure 6. The signal on the clock tree feeding the actual design is running at Q times the system clock frequency, so the APLL matches the divider output signal to the system clock. If Q=2, and the system clock on the board is 33 MHz, then the internal clock frequency is 2x, or 66 MHz. If N=2, then the VCO frequency is 132MHz, that is inside the operating range of the VCO. This configuration reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system. !The duty-cycle of the VCO is not 50%, thus for applications that require duty cycle of 50%, another divider should be placed between the VCO and the clock tree. Chip Express APLL-9 Input Buffer System Clock REFCLK B1 APLL Q Compensation Buffer :Q B2 VCOCLK Internal Clock Clock Tree :N Figure 6: APLL Multiplying Internal Clock Frequency: F (Internal Clock)=Q x F(System Clock) In order to eliminate the delay caused by the :Q divider, divide circuitry does not directly feed the phase detector. Instead, the feedback clock is fed via an AND gate. The :Q divider should work on negative edge of the clock. Another AND gate should be placed on the system clock path to compensate for the delay introduced by the AND gate on the refclk path. The timing diagram in figure 7 shows that once VCOCLK and REFCLK are synchronized (PLL is locked), the internal clock will always be in-phase with the system clock. !The duty cycle of the :Q divider should be 1/Q x 100%, so it is actually a counter with a terminal count. !The delay clock to output of the :Q divider must be less than the "low time" of the internal clock. :Q Delay Internal Clock :Q Output 33% duty cycle B2 + AND Delay VCOCLK is synchronized with REFCLK B1 + AND Delay System Clock Internal Clock is in phase with System Clock Figure 7: Divider Circuitry Timing Diagram, Q=3 Chip Express APLL-10 Figure 8 shows how to synthesize a divided clock, i.e. a clock, which is slower than the system clock. As always, REFCLK and VCOCLK inputs are coherent in both phase and frequency. Thus, the internal clock will equal the system clock divided by M (the :M divider should meet the same requirements as :Q divider in the multiplication circuit) Division The same considerations of delay balance on REFCLK and VCOCLK paths that were explained in the previous section hold true in this case also. System Clock + tpd (B1) + tpd (AND) = REFCLK Internal Clock + tpd (B2) + tpd (AND) = VCOCLK REFCLK = VCOCLK System Clock = Internal Clock Input Buffer System Clock REFCLK :M B1 VCOCLK Q APLL B2 Compensation Buffer Internal Clock Clock Tree :N Figure 8: APLL division Internal Clock Frequency F(internal clock)=F(system clock) / M Chip Express APLL-11 Arbitrary Frequency Synthesis The combination of division and multiplication circuits allows us the possibility of synthesizing a frequency that is Q/M times the system clock frequency. Refer to Figure 9, below. As in the previous sections, the system clock and internal clock are synchronized. Input Buffer System Clock REFCLK :M B1 Compensation Buffer :Q Q APLL B2 VCOCLK Internal Clock Clock Tree :N Figure 9: Synthesis Of Arbitrary Frequency F(internal clock) = F(system clock) x Q / M Chip Express APLL-12 When Skew Reduction Is Not Required In many APLL applications the only requirement is frequency synthesis. In these applications the skew between the system clock and the internal clock is not important. Therefore there is no need for input buffer delay compensation. The :M and :Q dividers can have a 50% duty cycle. The whole circuit can be configured as shown on figure 10. Input Buffer System Clock B1 :M REFCLK VCOCLK :Q Internal Clock Q APLL Clock Tree :N Figure 10: Synthesis Of Arbitrary Frequency without system clock skew reduction F(internal clock) = F(system clock) x Q / M Chip Express APLL-13 APLL Implementation APLL Core Pin Description Pin Name AVDD Function Power AVSS Power LOCK Output NEN Input Description Positive analog supply (3.3V or 5.0V). This should be quiet, with as small an impedance as possible. It must be the same voltage as VDD. (Core VDD) Analog Ground (0V). This should be quiet, with as small an impedance as possible. Indicates both phase and frequency lock of the Q output clock (active high) NEN=0V: APLL operation enabled NEN=VDD: APLL operation disabled and APLL placed in zero power standby state REFCLK VCOCLK VLFI VLFO Q N[3:8] Input Input Input Output Output Input VDD Power VSS Power Input clock used as the frequency reference Clock from feedback divide-by counters Loop Filter input node Loop Filter output node Buffered Voltage Controlled Oscillator clock output The six most significant bits of the nine-bit feedback divide value. These are essentially dc inputs and must not change from cycle to cycle (refer to APLL spec for details). Positive digital core supply (3.3V or 5.0V). It must be the same voltage as AVDD. Digital Core Ground (0V) BPLLLOOP Pin Description (Refer to Figure 4) Pin Name ZLOOP VLFO VLFI Function Pad Input Output Description Connected to the Loop Filter Connected to the VLFO pin of the APLL Connected to the VLFI pin of the APLL VDDWELL Pad Pin Name VDDWELL Chip Express Function Power Description Provides a well bias for the I/Os next to the APLL APLL-14 Integrating An The APLL is placed in the design at the netlist level. Since the APLL core has no specific I/O place, its placement is determined APLL Into A by its associated BPLLLOOP pad. For each BPLLLOOP pad, Design the PLL cell connected to it is found, and is placed at the corner next to the BPLLLOOP cell. When placing the core cells, special attention should be given to the core cells that are connected to the PLL and are involved in high-frequency signals. High capacitance in nets connected to these cells will influence the maximum speed the VCO can operate and/or the clock skew and insertion delay. Therefore, all such logic should be placed together in one group, very close to the PLL cell. The layout software recognizes the cells that should be placed next to the PLL cell by inspecting their instance names. The instance name of each PLL is used to find all the core cells that should be placed near it. This is done based on the hierarchical separator (`.' or `/') character, which is found in the instance names and specifies the underlying hierarchy of the design. From each PLL instance name we derive a prefix. Each core cell whose name begins with that prefix is placed close to that PLL. The prefix is made from the PLL instance name with the last part (the part following the last hierarchical separator) discarded. For example, for a PLL cell whose instance name is `PR12.R1.APLL_CK', `PR12.R1.' will be the prefix. All cells whose prefix is `PR12.R1.' (the dot is part of the prefix) will be considered as one group, to be placed next to that PLL cell. Note that a cell called `PR12.R1.AA.BB' will also be placed next to that PLL, while a cell called `PR12.R15.R' will not. The meaning of this in terms of the hierarchical structure of the PLL in the netlist is this: All cells which should be placed next to the PLL cell should be contained inside one hierarchical block, and the PLL cell itself should be at the top-most level of that block. It is the designers' responsibility to create the proper hierarchical structure so that the appropriate core logic will be placed next to the PLL, avoiding large capacitance values on PLL-related critical nets. Chip Express APLL-15 ! Usually, the layout tools automatically find out which character is the hierarchical separator. However, if the PLL instance name contains both characters (`.' and `/') then the `-hierarchical_separator' switch must be given to the tan_lay script in order to specify the correct character to use. An example of code for APLL insertion is attached to this application note. Placing I/O Pins In Chip Express technology, four APLLs reside in corners of the device (for most members all of them are available - refer to Appendix B). There are 8 I/O pads in the corner next to the APLL. The VDDWELL power ring is automatically cut around these I/Os in order to provide noise isolation (refer to figure 11). The BPLLLOOP, AVDD, and AVSS pad placement is fixed and cannot be changed. One VDDWELL pad (VDDWH or VDDWL) should also be placed in order to bias the well of the I/Os next to the APLL (the well voltage should be equal to or greater than that of the periphery). A VDDC pad and a VDDWL pad can be combined into one VDDWCL pad. The placement of VDDC/VSSC supply pads, marked with (*) is highly recommended to minimize jitter and other noise-related problems. The placement of VDDC, VSSC and VDDWELL pads is arbitrary within the group. No output or bi-directional I/Os are allowed in the corner group (due to noise considerations). The AVDD should be as quiet as possible - do not short it with any digital VDDs! The VDDWELL in the corner should also be quiet - do not short it with VDDPER! Ensure that the package file (pkg) provides correct pin-pad connections. In some cases it should be changed (consult a Chip Express application engineer). Chip Express APLL-16 BPLLLOOP xl108 AVSS xl107 VSSCPAD* xl106 VDDCPAD* xl105 xt06 VDDCPAD* xt05 VSSCPAD* xt04 xt02 xt03 AVDD VDDWELL xt01 APLL VDDWELL Power Ring is cut here xl104 xl103 CX3301 Figure 11: Pad Placement AVDD VDDWELL VDDC* VSSC* VDDC* VSSC* VDDWELL AVDD BPLLLOOP AVSS VSSC* VDDC* PLL PLL BPLLLOOP AVSS VSSC* VDDC* VDDC* VSSC* AVSS BPLLLOOP PLL PLL VDDC* VSSC* AVSS BPLLLOOP AVDD VDDWELL VDDC* VSSC* VSSC* VDDC* VDDWELL AVDD Figure 12: Pin Placement Chip Express APLL-17 The following design considerations apply: Design Considerations * Jitter is affected by the noise frequency in the analog VDD/VSS. It increases when the noise level increases. It also depends on the noise in the core and periphery. Therefore, it is essential to provide a sufficient number of power and ground pads according to the rules. * To obtain the minimum skew, the System Clock input buffer should be placed as close as possible to the APLL since the core routing RC delay is not compensated for. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for analog VDD/VSS connections to the APLL core. Separate the traces from the chip's VDD/VSS supplies. - Use proper VDD/VSS de-coupling. Use good power and ground sources on the board. Chip Express APLL-18 APLL Start-Up Circuit Implementation To provide an appropriate APLL initial state (for a reliable start-up after power-up or after a long standby state), the following tri-state core buffer should always be used: NT30 PLL_RESET EN VLFI VDD D A special signal PLL_RESET should be produced (active low). When it is active (0 Volt), the VLFI node is driven to VDD, providing an initial VCO frequency of about 0 MHz, which is a good initial condition for the APLL. When PLL_RESET is not active, NT30 is in tri-state and doesn't affect the VLFI node. The PLL_RESET signal is released if, and only if, all of the following conditions have been satisfied: 1. 2. 3. 4. There is a stable REFCLK signal NEN = 0 Volt, i.e. APLL operation is enabled The dividers in the feedback path are not in RESET state The VDD and AVDD have reached their nominal value When using this tri-state buffer, remember the following: at the moment the PLL_RESET signal is released, the VCO frequency is still 0Hz, i.e. the APLL is not locked. It takes several thousand clock cycles for the APLL to lock after RESET is released. It is possible to use the same signal both for PLL_RESET and for the feedback divider RESET signal. Chip Express APLL-19 Explanations The reasons for using NT30 tri-state buffer are discussed below. 1. Reset In Feedback Path: Suppose APLL is enabled and receives a system clock signal on its REFCLK pin. Suppose also that the feedback is in RESET or DISABLE state. Then, the APLL does not receive oscillations on the VCOCLK pin. The phase detector observes that the VCOCLK frequency is lower than REFCLK frequency (VCOCLK frequency is actually 0Hz), and signals the VCO to increase frequency. Of course, this doesn't raise VCOCLK frequency, because the divider is inactive. In this way, the VCO reaches its maximum frequency, over 1GHz, corresponding to 0V ZLOOP voltage. When a RESET signal is released, the feedback divider is not able to handle the maximum VCO frequency, therefore its output will be either stuck or oscillating randomly. Input Buffer System Clock REFCLK B1 APLL Q Compensation Buffer :Q B2 VCOCLK Internal Clock RESET or DISABLE Chip Express Clock Tree :N RESET or DISABLE APLL-20 2. Long Standby State: Suppose that APLL is placed in a zero-power standby state (NEN='1') over a long period of time. Then, the ZLOOP voltage may leak to 0V for some reason. When the APLL is activated, it gets into the state previously described, i.e., V(ZLOOP)=0V corresponding to the maximum VCO frequency that the feedback cannot handle. 3. Slow Power-Up The APLL starts operating at the moment the VDD starts rising, i.e. it operates at 0.1xVDD, 0.2xVDD, ... , 1.0xVDD. The problem here is that all APLL calculations/considerations are not valid for these intermediate values of VDD (for example, the dividers might not function). If the power-up is long enough, the APLL may eventually enter into the state described in the previous paragraphs, V(ZLOOP)=0V, corresponding to the maximum VCO frequency. Chip Express APLL-21 Verilog Simulation Using APLL Two kinds of simulations are required in the Chip Express flow: functional simulation and test vectors generation simulation. Usually, the functional simulation comes first and the vectors are generated using the functional simulation results. The APLL module might slow the simulation of the whole design, so after verifying the proper operation of the APLL circuits, it is possible to disable the APLL model and inject clock frequency from the outside. APLL disabling is explained in the Vector Generation section. Note: The purpose of the APLL model is to ascertain correct use of the APLL. The characteristics of this model are not quite the same as those of an actual APLL. Therefore, lock time, jitter and VCO frequency overshoot are part of the model behavior, but the actual result will be different. Functional Simulation An example of a Verilog invocation script: verilog test_bench.v \ design.v \ -v $CE_DIRECTORY/lib/verilog/cx3001/src/cx3001_core.v \ -v $CE_DIRECTORY/lib/verilog/cx3001/src/cx3001_io.v \ +define+QUICK_TEST_NOPULL \ +pathpulse \ +nolibcell \ -a We recommend using the quick_vscript program to create the Verilog invocation script. For example: quick_vscript <top module name> test_bench.v design.v unit_delay The test_bench.v file should instantiate the design and set the parameters needed for the APLL operation: my_design inst1 ( ... ); // design instantiation Chip Express APLL-22 // The APLL instantiation name in my_design module is: inst5.pll_inst // Design specific parameters: defparam inst1.inst5.pll_inst.R1 = <R1 value>; // in Ohm defparam inst1.inst5.pll_inst.C1 = <C1 value>; // in pF defparam inst1.inst5.pll_inst.C2 = <C2 value>; // in pF // Family-specific parameters: defparam inst1.inst5.pll_inst.K = <k3 or k5 value>; // in MHz/V defparam inst1.inst5.pll_inst.Iucp = <Iucp3 or Iucp5>; // in uA All the parameters are defined in the auto_apll return mail with the subject: "APLL report". C1 and C2 values are 1000pF and 100pF by default. Familyspecific parameters can be found in the APLL Spec. These parameters should be defined for every APLL module in the design. At the beginning of the simulation, the APLL model will print the parameter values. For example: *** *** *** *** *** *** *** APLL Simulation Module Initialization Component values: R1: 3600.000000 Ohm C1: 1000.000000 pF C2: 100.000000 pF VCO Gain: 160.000000 MHz/V Unit Current: 3.280000 uA Monitoring Simulation Values In order to verify correct operation of the APLL circuits, monitor the main inputs/outputs of the APLL: REFCLK , VCOCLK , Q , LOCK An inside variable called real_period is also supplied. This variable will show the period of Q pin (period = half a cycle). Chip Express APLL-23 $monitor($realtime,, "refclk=%b vcoclk=%b q=%b real_p=%f lock=%b", inst1.inst5.pll_inst.REFCLK , inst1.inst5.pll_inst.VCOCLK , inst1.inst5.pll_inst.Q , inst1.inst5.pll_inst.real_period , inst1.inst5.pll_inst.LOCK ); Question: How will I know if the APLL is working properly? Answer: Watch the Q and real_period variables. Q will start from a low frequency value (10MHz E 100nS cycle) and will converge to the required VCO final output frequency. At the same time real_period variable will show the half-cycle value of Q frequency. Example: If the VCO output should reach 128MHz, then at the stable stage, real_period value will be 3.91ns which is 1 / (2 x 128MHz). 52.105 refclk=0 vcoclk=0 q=0 real_p=50.000000 lock=0 79.69 refclk=1 vcoclk=0 q=0 real_p=50.000000 lock=0 90.345 refclk=1 vcoclk=0 q=1 real_p=38.240000 lock=0 115.385 refclk=1 vcoclk=0 q=0 real_p=25.040000 lock=0 : : 22601.29 refclk=1 vcoclk=0 q=0 real_p=3.910000 lock=0 22601.745 refclk=1 vcoclk=1 q=0 real_p=3.910000 lock=1 22604.805 refclk=1 vcoclk=1 q=1 real_p=3.900000 lock=1 22605.485 refclk=1 vcoclk=0 q=1 real_p=3.900000 lock=1 22608.705 refclk=1 vcoclk=0 q=0 real_p=3.900000 lock=1 22612.615 refclk=1 vcoclk=0 q=1 real_p=3.910000 lock=1 * It is recommended to view those signals using a wave viewer. * It takes several thousand cycles to lock the frequency. * It is recommended to wait until the APLL is stable and then activate the rest of the design. This way you avoid setup violations due to APLL overshoot. * The exact number of cycles depends on the implementation. Chip Express APLL-24 Vector Generation Vectors are generated in order to test the chip using the Chip Express tester. During vector generation we do not want the APLL to be simulated, so the APLL model should be disabled. The clock should be supplied through the bypass mux. The APLL is disabled just by commenting out the R1 declaration line: // defparam inst1.inst5.pll_inst.R1 = <R1 value>; When this line does not exist inside the code, the APLL model will switch to vector generation mode and will not produce any signals, for example: *** APLL Simulation Module Initialization *** Component values: *** R1: 0.000000 Ohm *** C1: 1000.000000 pF *** C2: 100.000000 pF *** VCO Gain: 160.000000 MHz/V *** Unit Current: 3.280000 uA *** APLL Warning: Variable R1 is not initialized *** APLL switched to Vector Generation Mode. *** VCO output disabled. Error Messages Here is the list of error messages that the APLL model may print: *** APLL Warning: Variable R1 is not initialized *** APLL switched to Vector Generation Mode. *** VCO output disabled. R1 parameter was not defined in the test_bench file. If this is what you want, than the APLL model is now disabled. If you want to perform a functional simulation, then define R1 in your test_bench file. *** APLL Error: Frequency limit exceeded When VCO frequency reaches the value of 300MHz, the model will stop the VCO operation. Check the :Q counter, it probably stopped working at some point. Chip Express APLL-25 *** APLL Error: Pins N[8:3] are floating N3 - N8 pins are not connected. Connect N[8:3] to VDD. *** APLL Error: One of the pins N[8:3] is floating. (Has 'x' value) Some of the N3 - N8 pins are not connected. Connect N[8:3] to VDD. *** APLL Error: K variable over flow. VCO gain must be positive. Problem with K parameter definition. *** APLL Error: b1 variable over flow. Check R,C values. or *** APLL Error: b2 variable over flow. Check T value. or *** APLL Error: a1 variable over flow. Check R,C values. or *** APLL Error: a2 variable over flow. Check R,C values. Problem with parameter definition. Check units. Troubleshooting Problem: VCO frequency does not stop rising until it is stuck at 300MHz. Check: :N divider, :Q divider and the feedback loop. It probably cannot work at the VCO output frequency. Problem: VCO frequency goes up and down and does not reach its final value. Check: :N divider, :Q divider for glitches. See the Divider Requirements section. Chip Express APLL-26 Synthesis and Timing Analysis Using APLL in Synopsys Design Compiler The following diagram is a general scheme of APLL connections. Specific applications may not necessarily include all the counters and AND gates (refer to the APLL Applications section). APLL bypass System Clock apll_q Clock Input Buffer REFCLK :M B1 APLL Q :N Compensation Buffer B2 VCOCLK Clock Tree :Q Internal Clock MUX ByPass Divider :M and :Q dividers should meet the following requirements: Requirements 1. Triggered by negative clock edge 2. The duty cycle of the output signal is 1/Qx100% for :Q, 1/Mx100% for :M, i.e. counters with terminal count. 3. The delay clock to output of :Q must be less than the internal clock low time. The delay clock to output of :M must be less than the system clock low time. The :N divider is required to keep the VCO in the specified operating range. It should satisfy the following condition: FVCOmin < Finternal clock x N < FVCOmax It is recommended to synthesize the :Q and :N dividers to a frequency of 20% higher than the final frequency due to the APLL overshoot. Chip Express APLL-27 Defining the Clocks To synthesize the APLL block, you need to define the clocks correctly. Since the APLL model is not synthesizable, the Synopsys library APLL module does not have any functionality defined. In order to synthesize the three dividers properly, three clock definitions are required: SYS_CLK - System clock. Defined on the input port of this clock. INT_CLK - Defined on the CDQN output pin. Its frequency is REF_CLK x Q / M . APLL_CLK - VCO output frequency. Defined on the APLL Q output pin. Its frequency is INT_CLK * N . Uncertainty = <APLL long time jitter (max) > + <APLL Static Phase Error (max) > + <clock tree skew (max)> <APLL long time jitter> and <APLL Static Phase Error> are defined in the APLL Spec. <clock tree skew> is defined in the clock_table supplied in the Synopsys design_compiler kit. It is recommended to use clock values that are 20% faster due to the VCO frequency overshoot during the initialization phase. Example: for sys_clk=20MHz and int_clk=60MHz . Q=3 , N=2. Qclk will be int_clk xN = 120MHz. In this example we'll use jitter of 0.3nS and skew of 0.5nS. /* SysClk = 20MHz . User defined clock -> no overshoot on user clock */ create_clock ck -name SysClk -period 50 set_clock_skew SysClk -delay 0 -uncertainty 0.5 /* Internal clk 70MHz = 1.2 * 60Mhz */ create_clock my_pll/clock_tree/Z -name IntClk -period 14 set_clock_skew IntClk -uncertainty 0.8 -ideal -delay 0 /* APLL VCO clk 144Mhz = 1.2 * 120 MHz */ create_clock my_pll/pll_inst/Q -name ApllQclk -period 7 set_clock_skew ApllQclk -uncertainty 0.8 -ideal -delay 0 Chip Express APLL-28 Device Testing Correct APLL operation requires specified system clock frequency and a loop filter. It is difficult to provide both in the production test environment, where the device is tested at a clock frequency of 1MHz. In order to test the core logic on the lowspeed tester, the APLL should be bypassed as illustrated in figure 13. In bypass mode the test clock is fed directly to the core. A bypass control signal should be specified for this purpose. System Clock B1 REFCLK VCOCLK Phase Detector B2 Internal Clock Clock Tree :N Q Charge Pump Voltage Controlled Oscillator VLFO VLFI Test Clock Bypass Control PLL Figure 13: APLL Bypass Mode. APLL Test Scheme In the production environment, the APLL is not tested as a closed loop system with the external loop filter. Instead, component tests are performed for both the VCO and the Phase Detector and Charge Pump blocks. The following tests provide only a functional check of the blocks. The tests are performed by CEC. For testing in OneMask and high volume production, please consult CEC. Chip Express APLL-29 VCO Test The purpose of the test is to check whether the VCO oscillates. In this test, voltage is applied to the ZLOOP pin, and the VCO oscillations are monitored. The VCO frequency depends on the applied voltage. The following graph shows the expected VCO frequency as a function of V (ZLOOP). It is only a functionality check, therefore it is enough to choose one voltage value. 9&27UDQVIHU)XQFWLRQ ] + 0 \ F Q H X T H U ) 9'' 9 9'' 9 2 & 9 /RRS)LOWHU9ROWDJH The ZLOOP pin is always part of the application's pins so nothing special has to be done. For checking the oscillations of the VCO output, it must be divided into a lower frequency, and a path to an I/O must be logically defined. Since the APLL block will often have a divider at its VCO output, this counter can be used for the frequency testing. Chip Express APLL-30 Phase Detector and Charge Pump Test CLOCK1 The idea of the test is to provide different frequencies on the REFCLK and VCOCLK pins of the APLL (the loop is open, of course). When f(REFCLK) > f(VCOCLK), the voltage on the ZLOOP pad rises to VDD, when f(REFCLK) < f(VCOCLK), the voltage on the ZLOOP pad drops to 0v. The time needed for ZLOOP to reach either 0V or VDD depends on the difference between frequencies and on the capacitance of the tester pin. The time value is not measured, however. The Loop Filter is not required. The bypass mode circuit can be used for this test (refer to figure 14). CLOCK1 and CLOCK2 are applied to the System Clock and the Test Clock pins respectively. B1 REFCLK VCOCLK B2 Internal Clock Clock Tree :N Q CLOCK2 Bypass Control Phase Detector Charge Pump Voltage Controlled Oscillator PLL VLFO VLFI ESD Protection Pad ZLOOP BPLLLOOP f(REFCLK) > f(VCOCLK): V(ZLOOP) = 0v f(REFCLK) < f(VCOCLK): V(ZLOOP) = VDD Figure 14: Phase Detector and Charge Pump Test Chip Express APLL-31 APLL Calculations AVDD C2 = C1 10 R1 = C1 2 x D. F.req x C1 C2 R1 1 K x Icp C1 x Neq Icp - refer to APLL spec D.F.req =Required Damping Factor Neq = N x Q (Divider values) Loop Filter Damping Factor = R1 x C1 K x Icp x 2 C1 x Neq Damping Factor Units = Ohm x F x Loop Gain = MHz/V x A 1/sec = sec x =1 F sec K x Icp x R1 Neq Stability Limit of the Loop Gain = 4 x R1 x C1 x F(REFCLK) 2 2 x F(REFCLK) x R1 x C1 + 1 For Loop Stability: Loop Gain < Stability Limit of the Loop Gain UNITS: C [Farad], R [Ohm], K [MHz/V], Icp [A] Chip Express APLL-32 Choosing C and R Approximate values for C1 are around 1000pF. This should be sufficient for most applications. From here, the value of the resistor can be calculated based on the chosen damping factor. The recommended value of the damping factor is 2.0 or more. Icp and N[3-8] For skew reduction applications (where the skew between system clock and internal clock should be minimal) use N[3-8]='1' (the value of Neq is not important), i.e. connect N[3-8] pins to VDD. Use Icp=32*Iucp for APLL calculations. For other applications take N[3-8] and Icp values from the following table: Neq 256Neq 128Neq<256 64Neq<128 32Neq<64 16Neq<32 8Neq<16 Neq<8 N[8]N[7]N[6]N[5]N[4]N[3] 1 X X X X X 0 1 X X X X 0 0 1 X X X 0 0 0 1 X X 0 0 0 0 1 X 0 0 0 0 0 1 0 0 0 0 0 0 Icp 32*Iucp 32*Iucp 16*Iucp 8*Iucp 4*Iucp 2*Iucp 1*Iucp Neq = N*Q - the feedback divide-by count value X - don't care (Icp doesn't depend on these bits) Iucp = Iucp5 @AVDD = 5V Iucp = Iucp3 @AVDD = 3.3V Chip Express APLL-33 APLL Spec Note: CX3001/CX3002 APLL is 3.3V only CX2001/CX2002 APLL is 5V CX2001LV/CX2002LV APLL is 3.3V Operating Conditions: 3.3V 5V Symbol Parameter Min Typ Max Units Notes VDD Digital Supply 3 3.3 3.6 V = AVDD AVDD Analog Supply 3 3.3 3.6 V = VDD VSS Digital Ground 0.0 V AVSS Analog Ground 0.0 V Tj Junction Temp. Symbol Parameter Min Typ Max Units Notes VDD Digital Supply 4.75 5 5.25 V = AVDD AVDD Analog Supply 4.75 5 5.25 V = VDD VSS Digital Ground 0.0 27 100 0.0 AVSS Analog Ground Tj Junction Temp. V 0.0 0.0 27 C V 100 C Electrical Characteristics: Symbol Parameter IDDS Standby Current Chip Express Min Typ Max Units Notes 10 A NEN=VDD APLL-34 Timing Characteristics: Symbol f(VCO) Parameter Min VCO frequency Max Units 100 250 MHz VDD=5V 100 200 MHz VDD=3.3V 1 ns tj Input jitter tCH Input "1" time 4 tCL Input "0" time 4 tQr Output rise time Typ Notes ns ns 2 ns tQf Output fall time 2 ns tjs Short term jitter 0.01* ns See Definitions tjl Long term jitter 0.6* ns See Definitions SPE Static phase error 0 0.3** ns VDD=5V 0 0.2** ns VDD=3.3V duty Output duty cycle 40 50 60 % Maximum jitter assumes clean and stable operational environment with no other noise sources. In presence of noise, the values may change. ** SPE measured at N[3-8]='1'. It is defined as a skew between VCOCLK and REFCLK APLL pins (VCOCLK leads). * Definitions: Short term jitter (tjs) is defined as the maximum clock period variation from the ideal period. Long term jitter (tjl) is defined as the maximum offset of the actual clock output from the ideal clock. In order to keep the loop parameters within the analog APLL core reasonable (damping factor, stability margin, etc.), the following conditions must always exist. 100MHz 100MHz 1 1 0.5MHz Chip Express f(VCO) f(VCO) M Neq Fin/M 250MHz (5V) 200MHz (3.3V) 63 511 APLL-35 Conditions: Worst(3.3V): Typ(3.3V): Best(3.3V): Worst(5.0V): Typ(5.0V): Best(5.0V): 2.97V, 3.30V, 3.63V, 4.50V, 5.00V, 5.5 V, Slow Process Typ Process Fast Process Slow Process Typ Process Fast Process 100C, 27C, 0C, 100C, 27C, 0C, Analog Core Performance Values (CX2001/CX2001LV): Symbol K3 K5 Iucp3 Iucp5 Parameter 3.3V VCO Gain 5.0V VCO Gain 3.3V Unit Current 5.0V Unit Current Worst 113 128 2.85 3.04 Typ 197 217 3.96 4.23 Best 294 326 4.83 5.15 Units MHz/V MHz/V A A Worst 114 142 3.93 5.35 Typ 191 209 6.31 8.10 Best 247 257 9.57 12.0 Units MHz/V MHz/V A A Worst 101 1.83 Typ 160 3.28 Best 199 5.20 Units MHz/V A Analog Core Performance Values (CX2002/CX2002LV): Symbol K3 K5 Iucp3 Iucp5 Parameter 3.3V VCO Gain 5.0V VCO Gain 3.3V Unit Current 5.0V Unit Current Analog Core Performance Values (CX3001/2) Symbol K3 Iucp3 Chip Express Parameter 3.3V VCO Gain 3.3V Unit Current APLL-36 APLL Power Calculations Following are the current consumption equations for the CX2002LV, CX3001, CX3002 APLL (3.3 Volt) and CX2002 APLL (5 Volt). The conditions are defined as follows: Worst: Typical Best VDD(nom)x0.9 VDD(nom)x1.0 VDD(nom)x1.1 Slow Process Typical Process Fast Process 100C 25C 0C The PLL supply current comes from two power sources, VDD and AVDD. Their currents are Ivdd and Iavdd respectively and are defined as follows, with the components defined below: Ivdd = Ipfd (phase-frequency detector current) Iavdd = Ichp + Ivco (charge pump current + VCO current) Phase-Frequency Detector Current: Ipfd in A/MHz, as a function of the frequency at the inputs to the phase detector. Worst Typical Best 3.3 Volt Ipfd = 2.87 A/MHz Ipfd = 3.32 A/MHz Ipfd = 3.87 A/MHz 5 Volt Ipfd = 4.55 A/MHz Ipfd = 5.39 A/MHz Ipfd = 6.45 A/MHz Charge Pump Current: Ichp in A, as a function of Mult which is defined from the N[3-8] value (refer to the table below). N[8]N[7]N[6]N[5]N[4]N[3] 1 X X X X X 0 1 X X X X 0 0 1 X X X 0 0 0 1 X X 0 0 0 0 1 X 0 0 0 0 0 1 0 0 0 0 0 0 Chip Express Mult 32 32 16 8 4 2 1 APLL-37 3.3 Volt: Worst Typical Best Ichp = 7.065 x Mult + 245.0 A Ichp = 11.90 x Mult + 417.4 A Ichp = 17.77 x Mult + 623.7 A 5 Volt: Worst Typical Best Ichp = 7.259 x Mult + 283.8 A Ichp = 12.30 x Mult + 489.7 A Ichp = 18.30 x Mult + 735.0 A VCO Current: Ivco in A, as a function of VCO frequency, f, in MHz. 3.3 Volt Worst Typical Best Ivco = (0.002506 x f**2) + (1.119 x f) + 6.128 A Ivco = (0.001181 x f**2) + (1.433 x f) - 17.61 A Ivco = (0.001365 x f**2) + (1.136 x f) + 29.97 A 5 Volt Worst Typical Best Chip Express Ivco = (0.002000 x f**2) + (1.424 x f) + 6.264 A Ivco = (0.001786 x f**2) + (1.277 x f) + 45.52 A Ivco = (0.001908 x f**2) + (0.887 x f) + 190.0 A APLL-38 APLL Design Requirement Summary The following table will help you to determine whether anything was missed during the design. Requirement See Application Note ... AVDD, AVSS, BPLLLOOP pads are placed correctly on the chip. There is VDDWELL or VDDWCL pad in the corner group (the well in the corner is biased) There are no outputs/bi-directional I/Os in the corner group NEN polarity: NEN = 0V - APLL is enabled NEN=VDD APLL is disabled Loop Gain < Stability Limit at worst, typical and best conditions Damping factor (typical) is about 2.0 and C1=1000pF, C2=100pF :Q and :N dividers work properly at 20% higher VCO frequency For skew reduction application only: N[3-8]='1' In calculations: Icp=32*Iucp The delay clock to output of :Q is less than the "low time" of the internal clock. The delay clock to output of :M is less than the "low time" of the system clock :Q, :M dividers are triggered by a negative clock edge :Q, :M dividers are counters with terminal count There is B2, compensation buffer There is NT30 buffer connected to VLFI node. The RESET_PLL signal satisfies all conditions mentioned in the application note. 100MHz F(VCO) 200MHz Logic simulation using APLL was successively run All APLL-related components have the same prefix There is an APLL bypass path for a clock Placing I/O pins Chip Express Placing I/O pins Placing I/O pins APLL Core Pin Description APLL Calculations APLL Calculations Divider Requirements APLL Calculations APLL Applications / Divider Requirements APLL Applications / Divider Requirements APLL Applications / Divider Requirements APLL Applications / Divider Requirements APLL Applications APLL Start-Up Circuit APLL Start-Up Circuit APLL Spec Verilog Simulation Using APLL Integration an APLL into Design Device testing APLL-39 Appendix A: Receiving APLL Data From auto_apll@chipx.com The APLL simulation model resides in the simulation library supplied with the Design Kit. Parameters, recommended dividers and a sample netlist are supplied via the auto_apll mechanism. Send an e-mail to auto_apll@chipx.com with the following parameters: family=<Family Name> member=<Member Name> sys_clk=<system clock> int_clk=<internal clock> Example: For getting an APLL block for cx2001lv family, using the cx2081 member, with system clock = 25 MHz, internal clock = 50 MHz, please write the following message in your e-mail: family=cx2001lv member=cx2081 sys_clk=25 int_clk=50 auto_apll will send back the following e-mails: APLL report - contains the counter values and calculation of the loop filter components. apll.vlg - contains a gate level netlist of the APLL block and a high level description of the counters. Chip Express APLL-40 Appendix B: APLL Example ipcnnh refclk sysclk B1 vcoclk nv10d B2 cdqn9 intclk Clock Tree Phase Detector Charge Pump VLFO mxn21 Q : 16 testclk Voltage Controlled Oscillator VLFI ESD Protection PLL Pad ZLOOP BPLLLOOP D bypass pll_reset EN NT30 The following Verilog code represents the simple APLL application depicted in the above figure. Note that all cells that connect to the PLL, and are connected to highspeed signals that should have low parasitics, are given the same prefix (`apndx1pll.'). module apll_examp (sysclk,testclk,nen,bypass,lock,zloop, pll_reset); input sysclk, nen, bypass, zloop, testclk, pll_reset; output lock; hilo hilo1 ( .HI(hi1)); ipcnnh sysclk ( .Z(sysclk) , .ZI(refclk) ); pll apndx1pll.pll ( .REFCLK(refclk) , .VCOCLK(vcoclk) , .NEN(nen) , .N3(hi1) , .N4(hi1) , .N5(hi1) , .N6(hi1) , .N7(hi1) , .N8(hi1) , .VLFI(vlfi) , VLFO(vlfo) ,.Q(q) , .LOCK(lock) ); bpllloop apndx1pll.loop ( .VLFI(vlfi) , VLFO(vlfo) , .ZLOOP(zloop)); divider16 apndx1pll.divider_16 (.C(q), .Q(q_div16)); mxn21 apndx1pll.apll_mux ( .B(testclk) , .A(q_div16) , .Z(clk_tree) , .S(bypass) ); cdqn9 clock_tree ( .A(clk_tree), .Z(intclk)); nv10d apndx1pll.buff ( .A(intclk) , .Z(vcoclk) ); nt30 apndx1pll.nt ( .A(hi1), .EN(pll_reset), .Z(vlfi)); endmodule Chip Express APLL-41 Loop Filter Calculations The following spreadsheet shows the calculations for the loop filter components. For proper stability, it must be assured that the Loop Gain is less than 1/2 of the stability limit. Calculate R from the required parameters, then, after choosing the available resistor, recalculate the parameters of the system. Given data is shown in bold text and computed data is shown in plain text. Fin F(REFCLK) F_intclk F(VCO) M N Q Neq = N*Q Iucp multiplier (from table) Damping Factor (required) C1 C2 1.00E+07 1.00E+07 1.00E+07 1.60E+08 1 16 1 16 4 2 1.0E-09 1.0E-10 Worst Typical Best K5 Iucp5 Icp 1.28E+08 3.04E-06 1.22E-05 2.17E+08 4.23E-06 1.69E-05 3.26E+08 5.15E-06 2.06E-05 R1 (Suggested) R1 (Available) 12824.73 8100 8350.07 8100 6174.16 8100 1.26 1.94 2.62 7.88E+05 1.99E+07 1.86E+06 1.99E+07 3.40E+06 1.99E+07 Damping Factor ( with R1 available) Loop Gain Stability Limit of the LG Chip Express APLL-42 Appendix C: APLL Available Die Locations Generally, there are four APLLs on the chip - one for each corner: Not all of them are available for specific member (refer to the following table). APLL LOCATIONS Member CX2041 CX2081 CX2121 CX2201 CX2022A CX2052 CX3041 CX3042 CX3061 CX3122 CX3141 CX3182 CX3301 CX3422 CX3551 Top Left Top Right Bottom Left Bottom Right yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes no yes* yes* yes no no yes no yes yes yes yes yes yes yes no yes* yes* yes yes no yes yes yes yes yes yes yes yes yes The PLL placed in the location marked with (*) requires a special buffer on its Q pin for lv family (consult factory). Chip Express APLL-43 Appendix D: Input Buffer Compensation The following table contains a list of buffers that can be used for input buffer delay compensation. LOGIC BUFFER INPUT BUFFER ipcnnh ipcnnl iphnnh iphnnl ipsnnh or ipsnnl iptnnh or iptnnl CX2001 nv10d nv10 nv10d+nv10d nv10p nv10 nv10d CX2001lv nv10 nv10p nv10p nv10 nv10 nv10p CX2002 nv10p nv10 nv10p+nv10p nv10 nv10+nv10 nv10p CX2002lv nv10 nv10p nv10p nv10p+nv10p nv10+nv10 nv10p CX3001 nv10d+nv10d nv10d nv10p+nv10p nv10p nv10p+nv10p nv10d+nv10d Refer to back annotation exact timing difference between the input buffer and the logic buffer. Chip Express APLL-44 Appendix E: Known Problems (CX2001/CX2002) The APLL, as implemented on the bases CX2041, CX2081, CX2201, CXM2052M has some parametrical problems. The maximum skew between the vcoclk and the refclk is currently 1.8nSec at 5V and 1.0ns at 3v. (The rising edge of the refclk occurs after the rising edge of the vcoclk, i.e. the insertion delay is negative). Due to this skew, the LOCK mechanism can not recognize LOCK state and thus does not function properly. Refer to the section in this document entitled Integrating An APLL Into A Design. When using the APLL on current bases, (CX2041, CX2081, CX2201, CXM2052M), pins N[3:8] should be connected to VDD and should not be programmed according to the divider value. The Icp for the loop filter calculation should be taken equal to 32*Iucp. The skew parameter has been corrected in the CX2121 to 0.6nSec. When using the APLL on this base, pins N[3:8] should be programmed according to the divider value. Chip Express APLL-45