Ordering number : ENA1823 LV0221CS CMOS IC Front Monitor OE-IC for Optical Pickups http://onsemi.com Overview The LV0221CS is a front monitor optoelectronic IC for optical pickups that has a built-in photo diode compatible with three waveforms. LV0221CS is small size and type CSP packages. Functions * PIN photodiode compatible with three wavelengths incorporated. * Gain adjustment (-6dB to +6dB in 256 steps) through serial communication. * Amplifier to amplify differential output. Specifications Maximum Ratings at Ta = 25C Parameter Symbol Maximum supply voltage VCC Allowable power dissipation Pd1 Conditions Ratings Unit 6 Glass epoxy one-side substrate 55mm x 45mm x 0.8mm V 136 mW 100 mW Copper foil area (about 80%), Ta=75C Pd2 Glass epoxy one-side substrate 55mm x 45mm x 0.8mm Copper foil area (head: about 85% Tail: about 90%), Ta=75C Operating temperature Topr -20 to +85 C Storage temperature Tstg -40 to +100 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Recommended Operating Conditions at Ta = 25C Ratings Parameter Symbol Conditions Unit min typ max Operating supply voltage VCC 4.5 5 5.5 Output load capacitance CO 12 20 33 Output load resistance ZO 3 Semiconductor Components Industries, LLC, 2013 June, 2013 V pF k 82510 SY 20100803-S00005 No.A1823-1/6 LV0221CS Electrical Characteristics at Ta = 25C, VCC = 5V, RL=6k, CL=20pF Ratings Parameter Symbol Conditions Unit min Current dissipation ICC Sleep current Islp typ max 18 23.4 mA 1 mA Output voltage when shielded VC At shielding 1.8 2.0 2.2 V Output offset voltage Vofs At shielding, voltage between VOP-VON -30 0 30 mV Temperature dependence of offset voltage *1 Vofs Ta=-10 to +85C -60 0 60 Optical output voltage *1 VLC Low Gain, =780nm, G=0dB 0.21 0.262 0.31 mV/W Voltage between VOP-VON VLD Low Gain, =650nm, G=0dB 0.22 0.275 0.33 mV/W VLB Low Gain, =405nm, G=0dB 0.14 0.172 0.21 mV/W VMC Middle Gain, =780nm, G=0dB 0.66 0.83 0.99 mV/W VMD Middle Gain, =650nm, G=0dB 0.70 0.87 1.05 mV/W VMB Middle Gain, =405nm, G=0dB 0.43 0.54 0.65 mV/W VHC High Gain, =780nm, G=0dB 1.97 2.46 2.95 mV/W VHD High Gain, =650nm, G=0dB 2.07 2.58 3.10 mV/W 1.29 1.62 1.94 mV/W 5.5 6.0 6.5 1700 2200 mV 50 75 MHz 60 85 MHz 60 85 MHz 15 ns VHB High Gain, =405nm, G=0dB Light output voltage adjustment range *1 G G=0dB reference, absolute value of adjustment width D range *1 VoD Voltage between VOP-VON Frequency characteristics *1, *2 FcC -3dB(1MHz reference), =780nm V/C dB Light input = 40W(DC) + 20W(AC) FcD -3dB(1MHz reference), =650nm Light input = 40W(DC) + 20W(AC) FcB -3dB(1MHz reference), =405nm Light input = 40W(DC) + 20W(AC) Settling time *1 Tset Response time *1 Tr, Tf Vo=0.9Vp-p, output level 10 to 90% 10 ns 15 % fc=10MHz, duty=50% Overshoot *1 Ovst Vo=0.9Vp-p Undershoot *1 Unst Vo=0.9Vp-p Linearity *1 Lin At output voltage 0.5V and 1.0V 15 % -1 0 1 % (Between VOP-VON) Light-output voltage temperature dependence TC =780nm, 25C reference 10 13 16 % Voltage between VOP-VON *1, *3 TD =650nm, 25C reference 0 3 6 % TB =405nm, 25C reference 0 3 6 % Vf =785nm 10nm -0.8 0.1 =660nm 10nm -0.4 0.4 %/nm =405nm 10nm 0 1.2 %/nm Light-output voltage spectral sensitivity Voltage between VOP-VON *1 Step-step voltage ratio *1 DG (Vn-Vn-1) / Vn *100 *4 -3 0 %/nm 3 % Deviation from the ideal curve of above equation Item with *1 mark indicate the design reference value. Item with *2 mark indicate the frequency characteristics when VOP and VON are applied individually. The frequency characteristics are for the case of High / Middle / Low gain and for the case when the output voltage adjustment range is -6 to +6dB Item with *3 mark indicates the temperature dependence for the case of High / Middle / Low gain and for the case when the temperature is 25 to 85C for the output voltage adjustment range of -6 to +6dB Vn in Item with *4 mark is Vn = (sensitivity / 2 ) x 5400 / (5400-16 x GCAstep ) x light intensity (W) GCA = Gain Control Amplifier No.A1823-2/6 LV0221CS Package Dimensions unit : mm (typ) 3402 TOP VIEW 0.55 0.55 2 1.75 3 0.875 0.275 2 3 1.75 A 1 0.875 B C C B A 0.68 MAX 1 BOTTOM VIEW SIDE VIEW 0.1 (0.52) SIDE VIEW SANYO : ODCSP8(1.75X1.75) Pin Assignment TOP VIEW 3 SEN 2 GND SCLK Pin No. Pin name 1A SDIO Serial communication Data pin Positive side output pin VCC SSEL Function 1B VOP 1C VON Negative side output pin 2A SCLK Serial communication Clock pin 2C SSEL Register selection pin SSEL = Low, Open : Address 00 to 0Fh used SSEL = High : Address 10 to 1Fh used 1 SDIO A VOP B VON C 3A SEN Serial communication Enable pin 3B GND GND pin 3C VCC Power supply voltage pin PD assignment 0.875mm 1.75mm 1.75mm Center of PD 0.875mm *PD size for reference to be used for design No.A1823-3/6 LV0221CS Block diagram and Test circuit diagram VCC SEN SCLK SDIO SSEL Control Vref Serial VCC Bias Regulator Low Middle High Vo+ 20pF + + Vref Vo- 20pF GND Vref Resister table Enable selection of the register group from the SSEL pin. SSEL = Low, Open Address 7 Name Default Value 6 5 POWER 4 3 IV GAIN SEL 2 00 00 00 11: Power on 00 01: High 00 01: BD 00 01 10: Sleep 10: Middle 10: DVD 00h 11: Low 01h 1 1 1 x 1 1 1 1 1 1 1 1 1 1 1 2 1 0 x x 1 1 1 1 1 1 1 1 1 00000000 to 11111111 Name DVD GAIN 02h 1 1 1 1 Value 1 00000000 to 11111111 Name Default x BD GAIN Value Default 0 11: CD Name Default 1 GAIN SEL CD GAIN 03h 1 1 1 1 Value 1 00000000 to 11111111 Name 0Eh TEST1 (*1) Name 0Fh TEST2 (*1) SSEL = High Address 7 Name Default Value 6 5 POWER 4 3 IV GAIN SEL GAIN SEL 00 00 00 11: Power on 00 01: High 00 01: BD 00 01 10: Sleep 10: Middle 10: DVD 10h 11: Low 11: CD Name Default BD GAIN 11h 1 1 1 Value 1 Name Default DVD GAIN 12h 1 1 1 Value 1 1 00000000 to 11111111 Name Default 1 00000000 to 11111111 CD GAIN 13h Value 1 1 1 1 1 00000000 to 11111111 Name 1Eh TEST1 (*1) Name 1Fh TEST2 (*1) *1 TEST1 and TEST2 are either the time when power is applied or "00000000" is set. Do not attempt to change "00000000" during operation. "00000000" is returned when reading is made. *2 No problem in terms of operation occurs even when writing is made to the address 04h to 0Dh and 14h to 1Dh. "00000000" is returned when this address is read. No.A1823-4/6 LV0221CS Serial protocol WRITE timing chart (HOST) SEN 1 2 4 3 5 6 7 8 9 10 11 12 13 14 15 16 D6 D5 D4 D3 D2 D1 D0 15 16 (HOST) SCLK MSB A7 (HOST) SDIO A6 A4 A5 A3 A2 LSB MSB A0 D7 A1 LSB Address Mode Data (Output Data from Host) READ timing chart (HOST) SEN 1 2 4 3 5 6 7 8 9 10 11 13 12 14 (HOST) SCLK LSB MSB A7 (HOST) SDIO A6 A4 A5 A3 A2 A1 Address Mode A0 LSB MSB SDIO D7 D6 D5 D4 D3 D2 D1 D0 Data (Output Data from Host) SDIO pin load / CL=20pF (The table below shows the design reference value.) Parameter Symbol Min. Typ. Max. Unit SCL clock frequency Write fSCL 0 10 MHz SCL clock frequency Read fSCL tDSU 0 4 MHz 50 SDIO data setup time SDIO data hold time tDHO tDDLY SDIO output delay ns 50 ns 10 80 ns tENH tENL 1.6 s SEN "L" period 200 ns SCL rise time after SEN rise tSTA 60 ns SEN fall time after final SCL rise tSTO VIH 100 ns SEN "H" period Serial input "H" voltage Serial input "L" voltage 2.4 SDIO output "H" voltage VIL VOH 2.5 SDIO output "L" voltage VOL 0 WRITE V 0.6 V 2.9 3.3 V 0.3 0.8 V tENH tENL (HOST) SEN tSTA tSTO (HOST) SCLK (HOST) SDIO tDSU tDHO READ (HOST) SEN (HOST) SCLK (HOST) SDIO tDDLY SDIO No.A1823-5/6 LV0221CS Pin SDIO Type Input Equivalent circuit diagram 3V 3V Output VOP Output VON SCLK Input SSEL SEN ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PS No.A1823-6/6 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: LV0222CS-TLM-H LV0221CS-TLM-H