PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 1
FEATURES
• Four differential 2.5V/3.3V LVPECL output pairs.
• Output Frequency: ≤ 1GHz.
• Two selectable differential input pairs.
• Translates any standard single-ended or differential
input format to LVPECL output. It can accept the
following standard input formats and more:
o LVPECL, LVCMOS, LVDS, HCSL, SSTL,
LVHSTL, CML.
• Output Skew: 25ps (typ.).
• Part-to-part skew: 140ps (typ.).
• Propagation delay: 1.5ns (typ.).
• Additive Jitter: <100 fs (typ.).
• Operating Supply Voltage: 2.375V ~ 3.63V.
• Operating temperature range from -40°C to 85°C.
• Package availability: 20-pin TSSOP.
BLOCK DIAGRAM
DESCRIPTION
The PL138-48 is a high performance low-cost 1: 4 outputs
Differential LVPECL fanout buffer.
PhaseLink’s family of Differential LVPECL buffers are
designed to operate from a single power supply of 2.5V±5% or
3.3V±10%. The differential input pairs are designed to accept
most standard input signal levels, using an appropriate resistor
bias network, and produce a high quality set of outputs with
the lowest possible skew on the outputs, which is guaranteed
for part-to-part or lot-to lot skew.
Designed to fit in a small form-factor package, PL138
family offers up to 1GHz of output operation with very
low-power consumption, and lowest additive jitter of any
comparable device.
20-Pin TSSOP Package
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 2
PIN DESCRIPTIONS
Name Package Pin
# Type
(Mode) Description
LQFP-20
VEE 1 Power Power Supply pin connection
CLK-EN 2 Input (Pullup)
Synchronizing clock enable. When HIGH, clock outputs follow
clock input. When ‘Low’, Q outputs are forced low, QB outputs
are forced high. LVTTL / LVCMOS interface levels.
CLK-SEL 3 Input (Pulldown)
Clock select input. When HIGH, selects CLK1 input. When
LOW, selects CLK0 input.
LVTTL / LVCMOS interface levels.
CLK-IN0 4 Input (Pulldown) True part of differential clock input signal.
CLK-IN0B 5 Input (Pullup/Pulldown) Complementary part of differential clock input signal.
CLK-IN1 6 Input (Pulldown) True part of differential clock input signal.
CLK-IN1B 7 Input (Pullup/Pulldown) Complementary part of differential clock input signal.
DNC 8, 9 - Do Not Connect.
Vcc 10, 13, 18 Power Power Supply pin connection
QB0 ~ QB3 11, 14, 16, 19 Output LVPECL Complementary output
Q0 ~ Q3 12, 15, 17, 20 Output LVPECL True output
INPUT LOGIC BLOCK DIAGRAM
INPUT PIN CHARACTERISTICS
Parameter Min. Typ. Max. Units
Input Pulldown Resistor 75 kΩ
Pullup/Pulldown Resistors 100 kΩ
INPUT CLOCK CONTRO L SELECTION
CLK_SEL Selected Source
0 CLK-IN0
1 CLK-IN1
INPUT CLOCK FUNCTION
Inputs Outputs
CLK-EN CLKSEL Source Q0:Q3 Q0B:Q3B
0 0 CLK-IN0 Disabled Low Disabled High
0 1 CLK-IN1 Disabled Low Disabled High
1 0 CLK-IN0 Enabled Enabled
1 1 CLK-IN1 Enabled Enabled
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 3
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETERS SYMBOL MIN. MAX. UNITS
Supply Voltage VDD 4.6 V
Input Voltage, dc VI -0.5 VDD+0.5 V
Output Voltage, dc VO -0.5 VDD+0.5 V
Storage Temperature TS -65 150
°C
Ambient Operating Temperature* TA -40 85
°C
Junction Temperature TJ 110
°C
Lead Temperature (soldering, 10s) 260 °C
ESD Protection, Human Body Model 2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product
reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this
specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Parameter Symbol
-40°C 25°C 80°C
Units
Min Typ Max Min Typ Max Min Typ Max
Output High Voltage* VOH 2.215 2.320 2.420 2.275 2.350 2.420 2.275 2.35 2.420 V
Output Low Voltage* VOL 1.470 1.610 1.745 1.490 1.585 1.680 1.490 1.585 1.680 V
Input High Voltage VIH 2.075 2.420 2.135 2.420 2.135 2.420 V
Input Low Voltage VIL 1.470 1.890 1.490 1.825 1.490 1.825 V
Output Voltage Reference** VBB 1.86 1.98 1.92 2.04 1.92 2.04 V
Input High Voltage Common Mode
Range † †† VCMR 1.2 3.3 1.2 3.3 1.2 3.3 V
Input High
Current
CLK-IN0,
CLK-IN1
CLK-IN0B,
CLK-IN1B
I
IH
75 75 75 µA
Input Low
Current IIL -75 -75 -75 µA
Input and output parameters vary 1:1 with VCC when VCC varies ±10%.
* Outputs terminated with 50Ω to VCCO – 2V.
** Single-ended input operation is limited to VCC ≥ 3V in LVPECL mode.
† Common mode voltage is defined as VIH.
†† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 4
DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Parameter Symbol
-40°C 25°C 80°C
Units
Min Typ Max Min Typ Max Min Typ Max
Output High Voltage* VOH 1.415 1.520 1.620 1.475 1.550 1.620 1.475 1.55 1.620 V
Output Low Voltage* VOL 0.670 0.810 0.945 0.690 0.785 0.880 0.690 0.785 0.880 V
Input High Voltage VIH 1.275 1.620 1.335 1.620 1.335 1.620 V
Input Low Voltage VIL 0.670 1.090 0.690 1.025 0.690 1.025 V
Input High Voltage Common Mode
Range† VCMR 1.2 2.5 1.2 2.5 1.2 2.5 V
Input High
Current
CLK-IN0,
CLK-IN1
CLK-IN0B,
CLK-IN1B
I
IH
60 60 60 µA
Input Low
Current IIL -60 -60 -60 µA
Input and output parameters vary 1:1 with VCC when VCC varies ±5%.
* Outputs terminated with 50Ω to VCCO – 2V.
** Common mode voltage is defined as VIH.
† For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC + 0.3V
AC Electrical Characteristics
VCC = -3.8V to -2.375V or, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C
Parameter Symbol
-40°C 25°C 80°C
Units
Min Typ Max Min Typ Max Min Typ Max
Output Frequency fMAX 700 700 700 MHz
Propagation Delay* tPD 600 680 750 650 725 790 690 790 890 ps
Output Skew ** † tsk(o) 25 37 25 37 25 37 ps
Part-to-Part Skew *** † tsk(pp) 85 225 85 225 85 225 ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
t
APJ
0.10 0.10 0.10 ps
Peak-to-Peak Input Voltage
(Differential Configuration) VPP 150 800 1200 150 800 1200 150 800 1200 mV
Output Rise/Fall
Time 20% to 80% tR / tF 200 700 200 700 200 700 ps
All parameters are measured at f ≤ 700MHz, unless otherwise noted.
* Measured from the differential input crossing point to the differential output crossing point.
** Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross
points.
*** Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of
inputs on each device, the outputs are measured at the differential cross points.
†This parameter is defined in accordance with JEDEC Standard 65.
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 5
NOISE CHARACTERISTICS (Commercial and Industrial Temperature Devices)
Parameter Description Test Conditions Min. Typ. Max. Unit
t
APJ
Additive Phase Jitter
V DD = 3.3V, Frequency = 622.08MHz
Offset = 12KHz ~ 20MHz 20 40 fs
V DD = 3.3V, Frequency = 156.25MHz
Offset = 12KHz ~ 20MHz 50 100 fs
V DD = 3.3V, Frequency = 50MHz
Offset = 1KHz ~ 1MHz 50 100 fs
V DD = 3.3V, Frequency = 25MHz
Offset = 1KHz ~ 1MHz 50 100 fs
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
100 1000 10000 100000 1000000 10000000 100000000
Offset Frequency (Hz)
Phase Noise (dBc/Hz)
REF Input PL138-48 Output
When a buffer is used to pass a signal then the buffer will add a little bit of its own noise. The phase noise on the output of the
buffer will be a little bit more than the phase noise in the input signal. To quantify the noise addition in the buffer we compare the
Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive
Phase Jitter is as follows:
Additive Phase Jitter = (Output Phase Jitter) - (Input Phase Jitter)22
Carrier = 622.08MHz
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 6
PARAMETER MEASUREMENT INFORMATION
Output Waveform Test Circuit:
LVPECL
VCC
VEE
-1.80V to -0.375V
+2.0V
OSCILLOSCOPE
Ω50
Ω50
Channel
Channel
Ω50 Line
Ω50 Line
Differential Input Level:
CLK-INx
CLK-INxB
VCC
VEE
VPP
Cross Points
VCMR
Part-to-Part Skew:
Part 1
Part 2
Qx
QBx
Qy
QBy
tsk(pp)
Output Skew:
Qx
QBx
Qy
QBy
tsk(o)
Output Rise/Fall Time:
Qx
QBx
tR
20%
80%
tF
80%
20%
Propagation Delay:
CLK-INx
CLK-INxB
Qy
QBy
tPD
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 7
APPLICATION INFORMATION
The following circuits show different configurations for different input logic type signals. For
good signal integrity at the PL138 input, the signals need to be properly terminated according
to the logic type requirements. The signals need to be presented at the PL138 input according
to VCMR, VPP and other input requirements.
CLK-IN Input Driven by a 3.3V LVPECL Driver:
LVPECL
+3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
+3.3V
130 130
82 82
+3.3V
3.3V LVPECL Driver, Alternative Termination:
LVPECL
+3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
50 50
50
+3.3V
CLK-IN Input Driven by a CML Driver:
CML
+3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
+3.3V
50 50
+3.3V
CLK-IN Input Driven by an SSTL Driver:
SSTL
+2.5V
Ω50 Line
Ω50 Line
CLK-INx
PL138
+2.5V
120 120
120 120
+3.3V
CLK-IN Input Driven by an LVDS Driver:
LVDS
+2.5V or +3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
100
+2.5V or +3.3V
LVDS Driver, Alternative AC Coupling:
LVDS
+2.5V or +3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
+2.5V or +3.3V
1K 1K
1K 1K
100
This circuit is for compatibility only. AC coupling is not really
required for LVDS. The VCMR range of the PL138 reaches
low enough that LVDS signals can be connected directly to
the PL138 input like in the circuit to the left.
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 8
CLK-IN Input Driven by a CMOS Driver:
CMOS CLK-INx
PL138
+2.5V or +3.3V
1K
1K
0.1µF
CLK-IN Input Driven by Single Ended LVPECL:
LVPECL CLK-INx
PL138
+3.3V +3.3V
82
130
Ω50 Line 1K
0.1µF
CLK-IN Input Driven by an HCSL Driver:
HCSL
+2.5V or +3.3V
Ω50 Line
Ω50 Line
CLK-INx
PL138
+2.5V or +3.3V
1K 1K
1K 1K
50 50
HCSL presents its signals very close to the ground
rail, below the VCMR range, so the HCSL signals can
not be connected to the PL138 input directly. AC
coupling is required for HCSL signals on the PL138
input.
TERMINATION FOR LVPECL OUTPUTS
The required termination for LVPECL is 50Ω to a VCC-2V DC voltage level. Below are two schematics to
implement this termination.
LVPECL Termination Schematic #1:
PL138
VCC
Ω50 Line
Ω50 Line
LVPECL
VCC
R1 R1
R2 R2
Qx Buffer
Target
Input
LVPECL Termination Schematic #2:
PL138
VCC
Ω50 Line
Ω50 Line
LVPECL
50 50
Qx Buffer
Target
Input
RT
VCC=3.3V, Ideal values: R1=127Ω , R2=82.5Ω
Commercial values (E24): R1=130Ω , R2=82Ω
VCC=2.5V, Ideal values: R1=250Ω , R2=62.5Ω
Commercial values (E24): R1=240Ω , R2=62Ω
Schematic #2 is an alternative simplified termination.
VCC=3.3V, Ideal value: RT=48.7Ω
Commercial value: RT=50Ω (E24: 51Ω)
VCC=2.5V, Ideal value: RT=18.7Ω
Commercial value: RT=18Ω
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 9
POWER CONSIDERATIONS
Driving LVPECL outputs requires an amount of power that can warm up the chip significantly.
The general requirement for the chip is that the junction temperature should not exceed +110°C.
The power consumption can be divided into two parts:
1) Core power dissipation
2) Output buffers power dissipation
CORE POWER DISSIPATION
The chip core power is equal to VCC×IEE. With a worst case VCC and IEE the power dissipation in the core is
3.63V×45mA=163mW.
OUTPUT BUFFER POWER DISSIPATION
The output buffers are not exposed to the full VCC-VEE voltage. On the differential output, one line is at logic 1
with a small voltage across the buffer and a large output current. The other line is at logic 0 with a larger voltage
across the buffer and a smaller output current. The power dissipation per output buffer is 32mW. Only buffers that
are loaded will have power dissipation. With all 4 buffers loaded the worst case output buffer power dissipation
will be 128mW.
Total Chip Power Dissipation, worst case, is 163mW + 128mW = 291mW.
JUNCTION TEMPERATURE
How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to
the environment, also known as “junction to ambient”. The thermal resistance depends upon the type of package,
how the package is assembled to the PCB and if there is additional air flow for improved cooling. For the TSSOP
package the thermal resistance is as follows:
TSSOP 20-pin Package Air Flow Velocity in Linear Feet per Minute
0 200 500
JEDEC Standard Multi Layer PCB θJA = 73°C/W θJA = 67°C/W θJA = 64°C/W
The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to θJA ×
Power. For an ambient temperature of +85°C, all outputs loaded and no air flow, the junction temperature TJ =
85°C+73×0.291 = 106°C.
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 10
PACKAGE DRAWING (GREEN PACKAGE COMPLIANT)
TSSOP173 20L
PL138-48
2.5V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 06/06/12 Page 11
ORDERING INFORMATION (GREEN PACKAGE)
For part ordering, please contact our Sales Department:
2880 Zanker Road, San Jose, CA 95134 USA
Tel (408) 571-1668 Fax (408) 571-1688
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part/Order Number Marking Package Option
PL138-48OC
P138-48
OC
LLLLL
20-Pin TSSOP (Tube)
*Note: LLLLL designates lot number
PhaseLink Corporation, reserves the righ t to make changes in its p roducts or specificatio ns, or both at any time withou t notice. The inform ation
furnished by Phaselink is believed to be accurate and reliable. Howeve r, PhaseLink makes no guaran tee or warranty conce rning the accuracy of said
information and shall not be responsible fo r any loss or damage of whatever nature resulting from the use of, or reliance upon this produc t.
LIFE SUPPORT POLICY : PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
