74F373
Octal transparent latch (3-State)
74F374
Octal D flip-flop (3-State)
Product data
Supersedes data of 1994 Dec 05 2002 Nov 20
INTEGRATED CIRCUITS
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
2
2002 Nov 20
FEATURES
•8-bit transparent latch — 74F373
•8-bit positive edge triggered register — 74F374
•3-State outputs glitch free during power-up and power-down
•Common 3-State output register
•Independent register and 3-State buffer operation
•SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F373 4.5 ns 35 mA
TYPE TYPICAL fmax TYPICAL SUPPLY
CURRENT
(TOTAL)
74F374 165 MHz 55 mA
ORDERING INFORMATION ORDER CODE
DESCRIPTION COMMERCIAL RANGE PKG DWG #
VCC = 5 V ±10%, Tamb = 0 °C to +70 °C
20-pin plastic DIP N74F373N, N74F374N SOT146-1
20-pin plastic SOL N74F373D, N74F374D SOT163-1
20-pin plastic SSOP type II N74F373DB, N74F374DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.)
HIGH / LOW LOAD VALUE
HIGH/LOW
D0 - D7 Data inputs 1.0 / 1.0 20 µA / 0.6 mA
E (74F373) Enable input (active-HIGH) 1.0 / 1.0 20 µA / 0.6 mA
OE Output enable inputs (active-LOW) 1.0 / 1.0 20 µA / 0.6 mA
CP (74F374) Clock pulse input (active rising edge) 1.0 / 1.0 20 µA / 0.6 mA
Q0 - Q7 3-State outputs 150 / 40 3.0 mA / 24 mA
NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state.
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 3
PIN CONFIGURATION – 74F373
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
E
SF00250
LOGIC SYMBOL – 74F373
E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
VCC = Pin 20
GND = Pin 10
11
1OE
SF00251
IEC/IEEE SYMBOL – 74F373
1
EN2
2D
EN1
1
11
3
4
7
8
13
14
17
18
2
5
6
12
9
15
16
19
SF00252
PIN CONFIGURATION – 74F374
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
SF00253
IEC/IEE SYMBOL – 74F374
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
VCC = Pin 20
11
1
GND = Pin 10
OE
SF00254
IEC/IEEE SYMBOL – 74F374
1
C2
2D
EN1
1
11
3
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SF00255
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 4
LOGIC DIAGRAM FOR 74F373
VCC = Pin 20
GND = Pin 10
D0
D
EQ
Q0
3
2
D1
D
EQ
Q1
4
5
D2
D
EQ
Q2
7
6
D3
D
EQ
Q3
8
9
D4
D
EQ
Q4
13
12
D5
D
EQ
Q5
14
15
D6
D
EQ
Q6
17
16
D7
D
EQ
Q7
18
19
11
E
SF00256
1
OE
LOGIC DIAGRAM FOR 74F374
VCC = Pin 20
D0
D
CP Q
Q0
3
2
D1
D
CP Q
Q1
4
5
D2
D
CP Q
Q2
7
6
D3
D
CP Q
Q3
8
9
D4
D
CP Q
Q4
13
12
D5
D
CP Q
Q5
14
15
D6
D
CP Q
Q6
17
16
D7
D
CP Q
Q7
18
19
11
OE
CP
GND = Pin 10
SF00257
1
FUNCTION TABLE FOR 74F373
INPUTS INTERNAL OUTPUTS
OPERATING MODE
OE E Dn REGISTER Q0 - Q7
OPERATING
MODE
L H L L L
Enable and read register
L H H H H
Enable
and
read
register
L↓l L L
Latch and read register
L↓h H H
Latch
and
read
register
L L X NC NC Hold
H L X NC Z
Disable out
p
uts
H H Dn Dn Z
Disable
o
u
tp
u
ts
NOTES:
H = High-voltage level
h = HIGH state must be present one set-up time before the HIGH-to-LOW enable transition
L = Low-voltage level
l = LOW state must be present one set-up time before the HIGH-to-LOW enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓= HIGH-to-LOW enable transition
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 5
FUNCTION TABLE FOR 74F374
INPUTS INTERNAL OUTPUTS
OPERATING MODE
OE CP Dn REGISTER Q0 – Q7
OPERATING
MODE
L↑l L L
Load and read register
L↑h H H
Load
and
read
register
L↑X NC NC Hold
H↑X NC Z
Disable out
p
uts
H↑Dn Dn Z
Disable
o
u
tp
u
ts
NOTES:
H = High-voltage level
h = HIGH state must be present one set-up time before the LOW-to-HIGH clock transition
L = Low-voltage level
l = LOW state must be present one set-up time before the LOW-to-HIGH clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑= LOW-to-HIGH clock transition
↑= Not LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL PARAMETER RATING UNIT
VCC Supply voltage –0.5 to +7.0 V
VIN Input voltage –0.5 to +7.0 V
IIN Input current –30 to +5 mA
VOUT Voltage applied to output in HIGH output state –0.5 to VCC V
IOUT Current applied to output in LOW output state 48 mA
Tamb Operating free air temperature range 0 to +70 °C
Tstg Storage temperature range –65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5.0 5.5 V
VIH HIGH-level input voltage 2.0 – – V
VIL LOW-level input voltage – – 0.8 V
IIk Input clamp current – – –18 mA
IOH HIGH-level output current – – –3 mA
IOL LOW-level output current – – 24 mA
Tamb Operating free air temperature range 0 – +70 °C
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 6
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST LIMITS
UNIT
SYMBOL
PARAMETER
CONDITIONS1MIN TYP2MAX
UNIT
VO
HIGH level out
p
ut voltage
V
CC
= MIN, VIL = MAX, ±10%VCC 2.4 V
V
OH
HIGH
-
le
v
el
o
u
tp
u
t
v
oltage
CC ,IL ,
VIH = MIN, IOH = MAX ±5%VCC 2.7 3.4 V
VO
LOW level out
p
ut voltage
V
CC
= MIN, VIL = MAX, ±10%VCC 0.35 0.50 V
V
OL
LOW
-
le
v
el
o
u
tp
u
t
v
oltage
CC ,IL ,
VIH = MIN, IOL = MAX ±5%VCC 0.35 0.50 V
VIK Input clamp voltage VCC = MIN, II = IIK –0.73 –1.2 V
IIInput current at maximum input voltage VCC = MAX, VI = 7.0 V 100 µA
IIH High-level input current VCC = MAX, VI = 2.7 V 20 µA
IIL Low-level input current VCC = MAX, VI = 0.5 V –0.6 mA
IOZH Off-state output current, high-level voltage applied VCC = MAX, VO = 2.7 V 50 µA
IOZL Off-state output current, low-level voltage applied VCC = MAX, VO = 0.5 V –50 µA
IOS Short-circuit output current3VCC = MAX –60 –150 mA
ICC Supply current (total) 74F373 VCC = MAX 35 60 mA
74F374 57 86 mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5 V, Tamb = 25 °C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
AC ELECTRICAL CHARACTERISTICS
LIMITS
Tamb = +25 °C Tamb = 0 °C to +70 °C
SYMBOL PARAMETER TEST VCC = +5.0 V VCC = +5.0 V ± 10% UNIT
CONDITION CL = 50 pF; RL = 500 ΩCL = 50 pF; RL = 500 Ω
MIN TYP MAX MIN MAX
tPLH
tPHL Propagation delay
Dn to Qn Waveform 3 3.0
2.0 5.3
3.7 7.0
5.0 3.0
2.0 8.0
6.0 ns
tPLH
tPHL Propagation delay
E to Qn 74F373 W aveform 2 5.0
3.0 9.0
4.0 11.5
7.0 5.0
3.0 12.0
8.0 ns
tPZH
tPZL Output enable time
to HIGH or LOW level Waveform 6
W aveform 7 2.0
2.0 5.0
5.6 11.0
7.5 2.0
2.0 11.5
8.5 ns
tPHZ
tPLZ Output disable time
from HIGH or LOW level W aveform 6
W aveform 7 2.0
2.0 4.5
3.8 6.5
5.0 2.0
2.0 7.0
6.0 ns
fmax Maximum clock frequency W aveform 1 150 165 140 ns
tPLH
tPHL Propagation delay
CP to Qn 74F374 W aveform 1 3.5
3.5 5.0
5.0 7.5
7.5 3.0
3.0 8.5
8.5 ns
tPZH
tPZL Output enable time
to HIGH or LOW level W aveform 6
W aveform 7 2.0
2.0 9.0
5.3 11.0
7.5 2.0
2.0 12.0
8.5 ns
tPHZ
tPLZ Output disable time
from HIGH or LOW level Waveform 6
W aveform 7 2.0
2.0 5.3
4.3 6.0
5.5 2.0
2.0 7.0
6.5 ns
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 7
AC SET-UP REQUIREMENTS
LIMITS
Tamb = +25 °C Tamb = 0 °C to +70 °C
SYMBOL PARAMETER TEST VCC = +5.0 V VCC = +5.0 V ± 10% UNIT
CONDITION CL = 50 pF, RL = 500 ΩCL = 50 pF, RL = 500 Ω
MIN TYP MAX MIN MAX
tsu (H)
tsu (L) Set-up time, HIGH or LOW level
Dn to E W aveform 4 0
1.0 0
1.0 ns
th (H)
th (L)Hold time, HIGH or LOW level
Dn to E 74F373 W aveform 4 3.0
3.0 3.0
3.0 ns
tw (H) E Pulse width, HIGH Waveform 1 3.5 4.0 ns
tsu (H)
tsu (L) Set-up time, HIGH or LOW level
Dn to CP W aveform 5 2.0
2.0 2.0
2.0 ns
th (H)
th (L)Hold time, HIGH or LOW level
Dn to CP 74F374 W aveform 5 0
00
0ns
tw (H)
tw (L) CP Pulse width,
HIGH or LOW Waveform 5 3.5
4.0 3.5
4.0 ns
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
CP VMVM
VM
tw(H)
1/fmax
VM
VM
tPHL
tw(L)tPLH
Qn
SF00258
W aveform 1. Propagation delay for clock input to output,
clock pulse widths, and maximum clock frequency
tPHL
EV
MVM
VM
tw(H)
VM
VM
Qn
tPLH
SF00259
W aveform 2. Propagation delay for enable to output
and enable pulse width
Dn VMVM
VM
VM
tPHL
tPLH
Qn
SF00260
W aveform 3. Propagation delay for data to output
VMVMVMVM
VMVM
tsu(L) th(L)
tsu(H) th(H)
E
Dn
SF00261
W aveform 4. Data set-up time and hold times
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 8
AC WAVEFORMS
(continued)
For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
VMVMVMVM
VMVM
tsu(L) th(L)
tsu(H) th(H)
CP
Dn
SF00262
W aveform 5. Data set-up time and hold times
Qn, Qn
VM
VM
VM
tPHZ
tPZH
OEn
VOH -0.3V
0V
SF00263
W aveform 6. 3-State output enable time to HIGH level
and output disable time from HIGH level
VM
VM
VM
tPLZ
tPZL
VOL +0.3V
OEn
Qn, Qn
SF00264
W aveform 7. 3-State output enable time to LOW level
and output disable time from LOW level
TEST CIRCUIT AND WAVEFORMS
tw90%
VM
10%
90%
VM10%
90%
VM10%
90%
VM
10%
NEGATIVE
POSITIVE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate twtTLH tTHL
1MHz 500ns 2.5ns 2.5ns
Input pulse definition
VCC
family
74F
D.U.T.
GENERATOR
RL
CL
RT
VIN VOUT
Test circuit for 3-state outputs
tTHL (tf )
tTLH (tr )
tTLH (tr )AMP (V)
amplitude
3.0V 1.5V
VM
RL
7.0V
SWITCH POSITION
TEST SWITCH
closed
openAll other
tPLZ, tPZL
DEFINITIONS:
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to ZOUT of pulse
generators.
SF00265
PULSE
PULSE
PULSE
RL =
CL =
RT =
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 9
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 10
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 11
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 12
REVISION HISTORY
Rev Date Description
_3 20021120 Product data; third version (9397 750 10758). Supersedes 74F373_374_2 dated 1994 Dec 05
(9397 750 05119).
Engineering Change Notice 853–0369 29206 (date: 200211 15).
Modifications:
•Corrected ordering information table (from ‘N74374DB’ to ‘74F374DB’).
•Add SSOP20 (SOT339-1) package outline drawing.
_2 19941205 Product data; second version (9397 750 05119).
Engineering Change Notice 853–0369 14383 (date: 19941205).
Philips Semiconductors Product data
74F373/74F374Latch/flip-flop
2002 Nov 20 13
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Date of release: 11-02
Document order number: 9397 750 10758
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
