INTEGRATED CIRCUITS 74F373 Octal transparent latch (3-State) 74F374 Octal D flip-flop (3-State) Product data Supersedes data of 1994 Dec 05 2002 Nov 20 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 74F373 Octal transparent latch (3-State) 74F374 Octal D-type flip-flop (3-State) The 74F374 is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates. FEATURES * 8-bit transparent latch -- 74F373 * 8-bit positive edge triggered register -- 74F374 * 3-State outputs glitch free during power-up and power-down * Common 3-State output register * Independent register and 3-State buffer operation * SSOP Type II Package The register is fully edge triggered. The state of the D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop's Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-LOW output enable (OE) controls all eight 3-State buffers independent of the register operation. When OE is LOW, the data in the register appears at the outputs. When OE is HIGH, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. DESCRIPTION The 74F373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates. TYPE The data on the D inputs is transferred to the latch outputs when the enable (E) input is HIGH. The latch remains transparent to the data input while E is HIGH, and stores the data that is present one set-up time before the HIGH-to-LOW enable transition. TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 4.5 ns 35 mA TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 165 MHz 55 mA 74F373 The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. TYPE The active-LOW output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is LOW, latched or transparent data appears at the output. 74F374 When OE is HIGH, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE PKG DWG # VCC = 5 V 10%, Tamb = 0 C to +70 C 20-pin plastic DIP N74F373N, N74F374N SOT146-1 20-pin plastic SOL N74F373D, N74F374D SOT163-1 20-pin plastic SSOP type II N74F373DB, N74F374DB SOT339-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F (U.L.) HIGH / LOW LOAD VALUE HIGH/LOW Data inputs 1.0 / 1.0 20 A / 0.6 mA Enable input (active-HIGH) 1.0 / 1.0 20 A / 0.6 mA Output enable inputs (active-LOW) 1.0 / 1.0 20 A / 0.6 mA Clock pulse input (active rising edge) 1.0 / 1.0 20 A / 0.6 mA 3-State outputs 150 / 40 3.0 mA / 24 mA PINS D0 - D7 E (74F373) OE CP (74F374) Q0 - Q7 DESCRIPTION NOTE: One (1.0) FAST unit load is defined as: 20 A in the HIGH state and 0.6 mA in the LOW state. 2002 Nov 20 2 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 PIN CONFIGURATION - 74F373 PIN CONFIGURATION - 74F374 OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 E OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP SF00250 SF00253 LOGIC SYMBOL - 74F373 3 4 7 8 IEC/IEE SYMBOL - 74F374 13 14 17 18 3 D0 D1 D2 D3 D4 D5 D6 D7 11 E 11 CP 1 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 8 13 14 17 18 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 2 5 6 9 12 15 16 19 VCC = Pin 20 GND = Pin 10 VCC = Pin 20 GND = Pin 10 SF00254 SF00251 IEC/IEEE SYMBOL - 74F373 1 11 3 IEC/IEEE SYMBOL - 74F374 1 EN1 11 EN2 2D 1 3 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SF00252 2002 Nov 20 7 D0 D1 D2 D3 D4 D5 D6 D7 OE 1 4 EN1 C2 2D 1 2 4 5 7 6 8 9 13 12 14 15 17 16 18 19 SF00255 3 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 LOGIC DIAGRAM FOR 74F373 D1 4 D0 3 D E D2 7 D E Q D3 8 D E Q D4 13 D E Q D5 14 D E Q D6 17 D E Q D7 18 D E Q D E Q Q 11 E 1 OE VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 15 Q4 16 Q5 19 Q6 Q7 SF00256 LOGIC DIAGRAM FOR 74F374 D0 3 D1 4 D CP Q CP OE D2 7 D CP Q D3 8 D CP Q D4 13 D CP Q D5 14 D CP Q D6 17 D CP Q D7 18 D CP Q D CP Q 11 1 VCC = Pin 20 GND = Pin 10 2 5 6 9 Q0 Q1 Q2 Q3 12 Q4 15 Q5 16 Q6 19 Q7 SF00257 FUNCTION TABLE FOR 74F373 E Dn INTERNAL REGISTER OUTPUTS OE INPUTS L H L L L L H H H H L l L L L h H H L L X NC NC H L X NC Z H H Dn Dn Z NOTES: H = High-voltage level h = HIGH state must be present one set-up time before the HIGH-to-LOW enable transition L = Low-voltage level l = LOW state must be present one set-up time before the HIGH-to-LOW enable transition NC= No change X = Don't care Z = High impedance "off" state = HIGH-to-LOW enable transition 2002 Nov 20 OPERATING MODE Q0 - Q7 4 Enable and read register Latch and read register Hold Disable outputs Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 FUNCTION TABLE FOR 74F374 INTERNAL OUTPUTS OE INPUTS CP Dn REGISTER Q0 - Q7 L l L L L h H H L X NC NC H X NC Z H Dn Dn Z NOTES: H = High-voltage level h = HIGH state must be present one set-up time before the LOW-to-HIGH clock transition L = Low-voltage level l = LOW state must be present one set-up time before the LOW-to-HIGH clock transition NC= No change X = Don't care Z = High impedance "off" state = LOW-to-HIGH clock transition Not LOW-to-HIGH clock transition = OPERATING MODE Load and read register Hold Disable outputs ABSOLUTE MAXIMUM RATINGS Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range. SYMBOL RATING UNIT VCC Supply voltage PARAMETER -0.5 to +7.0 V VIN Input voltage -0.5 to +7.0 V IIN Input current -30 to +5 mA VOUT Voltage applied to output in HIGH output state -0.5 to VCC V IOUT Current applied to output in LOW output state 48 mA Tamb Operating free air temperature range 0 to +70 C Tstg Storage temperature range -65 to +150 C RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IIk Input clamp current - - -18 mA IOH HIGH-level output current - - -3 mA IOL LOW-level output current - - 24 mA Tamb Operating free air temperature range 0 - +70 C 2002 Nov 20 5 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN,, VIL = MAX,, VIH = MIN, IOH = MAX HIGH level output voltage HIGH-level MIN 10%VCC 2.4 5%VCC 2.7 10%VCC TYP2 MAX UNIT V 3.4 V 0.35 0.50 V 0.35 0.50 V -0.73 -1.2 V 100 A VOL O LOW level output voltage LOW-level VCC = MIN,, VIL = MAX,, VIH = MIN, IOL = MAX VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0 V IIH High-level input current VCC = MAX, VI = 2.7 V 20 A IIL Low-level input current VCC = MAX, VI = 0.5 V -0.6 mA IOZH Off-state output current, high-level voltage applied VCC = MAX, VO = 2.7 V 50 A IOZL Off-state output current, low-level voltage applied VCC = MAX, VO = 0.5 V -50 A current3 IOS Short-circuit output ICC Supply current (total) 5%VCC VCC = MAX 74F373 -60 VCC = MAX 74F374 -150 mA 35 60 mA 57 86 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25 C VCC = +5.0 V CL = 50 pF; RL = 500 Tamb = 0 C to +70 C VCC = +5.0 V 10% CL = 50 pF; RL = 500 UNIT MIN TYP MAX MIN MAX Waveform 3 3.0 2.0 5.3 3.7 7.0 5.0 3.0 2.0 8.0 6.0 ns Waveform 2 5.0 3.0 9.0 4.0 11.5 7.0 5.0 3.0 12.0 8.0 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL Propagation delay E to Qn tPZH tPZL Output enable time to HIGH or LOW level Waveform 6 Waveform 7 2.0 2.0 5.0 5.6 11.0 7.5 2.0 2.0 11.5 8.5 ns tPHZ tPLZ Output disable time from HIGH or LOW level Waveform 6 Waveform 7 2.0 2.0 4.5 3.8 6.5 5.0 2.0 2.0 7.0 6.0 ns fmax Maximum clock frequency Waveform 1 150 165 tPLH tPHL Propagation delay CP to Qn Waveform 1 3.5 3.5 5.0 5.0 7.5 7.5 3.0 3.0 8.5 8.5 ns tPZH tPZL Output enable time to HIGH or LOW level Waveform 6 Waveform 7 2.0 2.0 9.0 5.3 11.0 7.5 2.0 2.0 12.0 8.5 ns tPHZ tPLZ Output disable time from HIGH or LOW level Waveform 6 Waveform 7 2.0 2.0 5.3 4.3 6.0 5.5 2.0 2.0 7.0 6.5 ns 2002 Nov 20 74F373 74F374 6 140 ns Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 AC SET-UP REQUIREMENTS LIMITS Tamb = +25 C SYMBOL PARAMETER TEST CONDITION VCC = +5.0 V CL = 50 pF, RL = 500 MIN tsu (H) tsu (L) Set-up time, HIGH or LOW level Dn to E th (H) th (L) Hold time, HIGH or LOW level Dn to E 74F373 tw (H) E Pulse width, HIGH tsu (H) tsu (L) Set-up time, HIGH or LOW level Dn to CP th (H) th (L) Hold time, HIGH or LOW level Dn to CP tw (H) tw (L) CP Pulse width, HIGH or LOW 74F374 TYP Tamb = 0 C to +70 C VCC = +5.0 V 10% CL = 50 pF, RL = 500 MAX MIN UNIT MAX Waveform 4 0 1.0 0 1.0 ns Waveform 4 3.0 3.0 3.0 3.0 ns Waveform 1 3.5 4.0 ns Waveform 5 2.0 2.0 2.0 2.0 ns Waveform 5 0 0 0 0 ns Waveform 5 3.5 4.0 3.5 4.0 ns AC WAVEFORMS For all waveforms, VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn 1/fmax CP V M VM VM VM VM tPLH tw(L) VM Qn tPHL tPLH tw(H) tPHL Qn VM VM VM SF00260 SF00258 Waveform 3. Propagation delay for data to output Waveform 1. Propagation delay for clock input to output, clock pulse widths, and maximum clock frequency Dn tsu(H) tw(H) E VM VM tPHL Qn VM E VM VM th(H) VM tsu(L) VM th(L) VM tPLH VM SF00261 VM Waveform 4. Data set-up time and hold times SF00259 Waveform 2. Propagation delay for enable to output and enable pulse width 2002 Nov 20 VM 7 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 AC WAVEFORMS (continued) For all waveforms, VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Dn VM VM tsu(H) VM tsu(L) th(H) VM OEn VM VM th(L) tPZL CP VM tPLZ VM VM Qn, Qn VOL +0.3V SF00262 Waveform 5. Data set-up time and hold times SF00264 Waveform 7. 3-State output enable time to LOW level and output disable time from LOW level OEn VM VM tPZH tPHZ Qn, Qn VOH -0.3V VM 0V SF00263 Waveform 6. 3-State output enable time to HIGH level and output disable time from HIGH level TEST CIRCUIT AND WAVEFORMS SWITCH POSITION TEST SWITCH tPLZ, tPZL closed All other open PULSE GENERATOR 7.0V VCC tw 90% NEGATIVE PULSE 90% VM VM 10% VIN RL VOUT AMP (V) 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V D.U.T. RT CL RL Test circuit for 3-state outputs AMP (V) VM VM 10% 10% tw DEFINITIONS: 0V Input pulse definition RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 90% 90% POSITIVE PULSE INPUT PULSE REQUIREMENTS family amplitude 74F 3.0V VM 1.5V rep. rate 1MHz tw tTLH 500ns 2.5ns tTHL 2.5ns SF00265 2002 Nov 20 8 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 DIP20: plastic dual in-line package; 20 leads (300 mil) 2002 Nov 20 9 SOT146-1 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 SO20: plastic small outline package; 20 leads; body width 7.5 mm 2002 Nov 20 10 SOT163-1 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm 2002 Nov 20 11 SOT339-1 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 REVISION HISTORY Rev Date Description _3 20021120 Product data; third version (9397 750 10758). Supersedes 74F373_374_2 dated 1994 Dec 05 (9397 750 05119). Engineering Change Notice 853-0369 29206 (date: 20021115). Modifications: * Corrected ordering information table (from `N74374DB' to `74F374DB'). * Add SSOP20 (SOT339-1) package outline drawing. _2 19941205 Product data; second version (9397 750 05119). Engineering Change Notice 853-0369 14383 (date: 19941205). 2002 Nov 20 12 Philips Semiconductors Product data Latch/flip-flop 74F373/74F374 Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 11-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 2002 Nov 20 13 9397 750 10758