© 2005 Microchip Technology Inc. DS21708E-page 1
24AA04/24LC04B
Device Selection Table
Features:
Single supply with operation down to 1.8V
Low-power CMOS technology:
- 1 mA active current, ty pical
-1μA standby current, typical (I-temp)
Organized as 2 blocks of 256 bytes (2 x 256 x 8)
2-wire serial interface bus, I2C™ compatible
Schmitt Trigger inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (24AA04) and 400 kHz (24LC04B)
compatibility
Self-timed write cycle (including auto-erase)
Page write buffer for up to 16 bytes
Hardware write-protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 4,000V
1,000,000 erase/write cycles
Data retention > 200 years
8-lead PDIP, SOIC, TSSOP, DFN and MSOP
packages
5-lead SOT-23 package
Pb-free finish available
Available for extended temperature ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Description:
The Microchip Technology Inc. 24AA04/24LC04B
(24XX04* ) is a 4 Kb it El ect ric all y Era sable PROM. Th e
device is organized as two blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.8V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX04 also has a page write
capability for up to 16 bytes of data. The 24XX04 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN and MSOP packages and is
also avai lab le in t he 5-le ad SOT-23 pac k age .
Package Types
Block Diagram
Part
Number Vcc
Range Max. Clock
Frequency Temp.
Ranges
24AA04 1.8-5.5 400 kHz(1) I
24LC04B 2.5-5.5 400 kHz I, E
Note 1: 100 kHz for VCC <2.5V
A0
A1
A2
VSS
VCC
WP
SCL
SDA
1
2
3
4
8
7
6
5
PDIP, MSOP SOIC, TSSOP
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
DFN
A0
A1
A2
VSS
WP
SCL
SDA
VCC
SOT-23-5
15
4
3
SCL
Vss
SDA
WP
Vcc
2
Note: Pins A0, A1 and A2 are not used by the 24XX04. (No
intern al connect ions).
8
7
6
5
1
2
3
4
HV
EEPROM
Array
Page
YDEC
XDEC
Sense Amp.
Memory
Control
Logic
I/O
Control
Logic
I/O
WP
SDA
SCL
VCC
VSS R/W Control
Latches
Generator
4K I2C Serial EEPROM
24AA04/24LC04B
DS21708E-page 2 © 2005 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-65°C to +125°C
ESD protection on all pins......................................................................................................................................................≥ 4kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Sym. Characteristic Min. Typ. Max. Units Conditions
D1 VIH WP, SCL and SDA pins ——
D2 High-level input voltage 0.7 VCC ——V
D3 VIL Low-level input voltage 0.3 VCC V—
D4 VHYS Hysteresis of Schmitt
Trigger inputs 0.05 VCC ——V(Note)
D5 VOL Low-level output voltage 0.40 V IOL = 3.0 m A, VCC = 2.5V
D6 ILI Input leakage current ——±1μAVIN = VSS or VCC
D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC
D8 CIN,
COUT Pin capacitance
(all inputs/ou tpu t s) ——10pFVCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
D9 ICC write Operating current —0.13mAVCC = 5.5V, SCL = 400 kHz
D10 ICC read 0.05 1 mA
D11 ICCS Standby current
0.01
1
5μA
μAIndustrial
Automotive
SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
© 2005 Microchip Technology Inc. DS21708E-page 3
24AA04/24LC04B
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V
Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Sym. Characteristic Min. Typ. Max. Units Conditions
1F
CLK Clock frequency
400
100 kHz 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
2THIGH Clock high time 600
4000
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
3T
LOW Clock low time 1300
4700
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
4TRSDA and SCL rise time
(Note 1)
300
1000 ns 2.5V VCC 5.5V (Note 1)
1.8V VCC < 2.5V (24AA04)
(Note 1)
5T
FSDA and SCL fall time
300 ns (Note 1)
6T
HD:STA Start condition hold time 600
4000
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
7T
SU:STA Start condition setup
time 600
4700
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
8THD:DAT Data input hold time 0
—ns(Note 2)
9T
SU:DAT Data input setup time 100
250
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
10 TSU:STO Stop condition setup
time 600
4000
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
11 TAA Output valid from clock
(Note 2)
900
3500 ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
12 TBUF Bus free time: Time the
bus mu st be free befo r e
a new transmission can
start
1300
4700
ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
13 TOF Output fall time from VIH
minimum to VIL
maximum
20+0.1CB
250
250 ns 2.5V VCC 5.5V
1.8V VCC < 2.5V (24AA04)
14 TSP Input filter spike
suppression
(SDA and SCL pins)
50 ns (No tes 1 and 3)
15 TWC Write cycl e time
(byte or page) ——5ms
16 Endurance 1M cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The co mbine d TSP and VHYS spec ifi ca tio ns are d ue to n ew Sc hm it t Trigger i np ut s wh ic h p r ov id e i mp rov ed
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensur ed by c haracterization. For endurance estimates in a specific
applic ation, pl ease co nsult the Total Endu rance™ Model w hich ca n be obt ained fro m Micro chip’ s w eb site
at www.microchip.com.
24AA04/24LC04B
DS21708E-page 4 © 2005 Microchip Technology Inc.
FIGURE 1-1: BUS TIMING DAT A
FIGURE 1-2: BUS T IMING START/STOP
7
524
8910
12
11
14
6
SCL
SDA
IN
SDA
OUT
3
76
D4
10
Start Stop
SCL
SDA
© 2005 Microchip Technology Inc. DS21708E-page 5
24AA04/24LC04B
2.0 FUNCTIONAL DESCRIPTION
The 24XX04 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX04 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain high.
3.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3 S top Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of data
bytes transferred between Start and Stop conditions is
determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored
when doing a write operation). When an overwrite does
occur, it will replace data in a first-in first-out (FIFO)
fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The mast er device mus t ge nera te a n ext ra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to t he sla ve by no t gene rating a n Ack nowledg e bit
on the las t by te that has be en c loc ke d ou t of th e sl av e.
In this c as e, the sl ave (24 XX04) will le av e th e d at a line
high to enable the master to generate the Stop
condition.
FIGURE 3-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24XX04 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
SCL
SDA
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
24AA04/24LC04B
DS21708E-page 6 © 2005 Microchip Technology Inc.
3.6 Device Addressing
A control byte is the first byte received following the
S tar t condition from the mas ter device . The contro l byte
consis ts of a four -bit control c ode. For the 24XX04, thi s
is set as ‘1010’ binary for read and write operations.
The next two bit s of the control byte are “don’t cares” for
the 24XX04. The last bit, B0, is used by the master
device to select which of the two 256-word blocks of
memory are to be accessed. This bit is, in effect, the
Most Significant bit of the word address.
The last bit of the control byte defines the operation to
be performed. When set to ‘1’, a read operation is
select ed. W hen set to ‘0 , a write operati on is se lecte d.
Follow in g the Start condi tio n, the 24XX04 moni tors the
SDA bus checking the device type identifier being
transmitted and, upon receiving a ‘1010’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
24XX04 will select a read or write operation.
FIGU RE 3-2 : CONTROL BYT E
ALLOCATION
Operation Control
Code Block Select R/W
Read 1010 Block Addre ss 1
Write 1010 Block Address 0
10 10xxB0 R/W ACK
Start Bit
Read/Write Bit
x = “don’t care”
S
Slave Address
Acknowled ge Bit
Control Code
Block
Select
Bits
© 2005 Microchip Technology Inc. DS21708E-page 7
24AA04/24LC04B
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start condition from the master, the
dev ice co de (4 bits), the block address (3 bits) and t he
R/W bit, which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow once it has generated an Acknowledge b it during
the nint h clock cycl e. Therefor e, the next byt e transmit-
ted by the master is the word address and will be
written into the Address Pointer of the 24XX04. After
receiving another Acknowledge signal from the
24XX04, the master device will transmit the data word
to be written into the addressed memory location. The
24XX04 acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle and, during this time, the 24XX04 will not
generate Acknowledge signals (Figure 4-1).
4.2 Page Write
The write control byte, word address and the first data
byte are transm itted to the 24 XX04 in the s ame wa y as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to 16 data bytes to the
24XX04, which are temporarily stored in the on-chip
page buffer and will be written into memory once the
master has transmitted a Stop condition. Upon receipt
of each w ord, the fou r lowe r-order Add ress Poi nter bit s
are internally incremented by ‘1’. The higher-order 7
bits of the word add r ess rem ai n const ant. If the m ast er
should trans mit more than 16 w ords prior to ge neratin g
the Stop condition, the address counter will roll over
and the pre viously received dat a wil l be overwritt en. As
with th e byte wr ite oper ation, onc e the Stop con dition i s
received an internal write cycle will begin (Figure 4-2).
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: PAGE WRITE
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples o f the page buf fer size (or
‘page siz e’ ) an d end at ad dres s es tha t a re
integer multiples of [page size – 1]. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to th e nex t page as mi ght be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
Bus Acti vity
Master
SDA Line
Bus Activity
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
Block
Select
Bits
x = “don’t care”
10 10xxB0 0
S P
Bus Acti vity
Master
SDA Line
Bus Activity
S
T
A
R
T
Control
Byte Word
Address (n) Data (n) Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
Block
Select
Bits
x = “don’t care”
1010xx 0
B0
24AA04/24LC04B
DS21708E-page 8 © 2005 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiate s the internall y-timed write cycle and ACK pollin g
can then be initiated immediately. This involves the
master sending a S tart c ondition fo llowed by t he contro l
byte for a W rite command (R/W = 0). If the device is still
busy wi th the write cycle, no ACK will be returned. If the
cycle is complete, the device will return the ACK and
the master can then proceed with the next Read or
Write command. See Figure 5-1 for a flow diagram of
this operation.
FIGURE 5-1: ACKNOWLEDGE POLLING
FLOW
6.0 WRITE PROTECTION
The W P pin a llows th e user t o writ e-prote ct the entire
array (000-1FF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled.
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
© 2005 Microchip Technology Inc. DS21708E-page 9
24AA04/24LC04B
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to1’. There are three basic types
of read operat ions: current address read , rand om rea d
and sequential read.
7.1 Current Address Read
The 24XX04 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by ‘1’. Therefore, if the previous access
(either a re ad or write opera tio n) w as to ad dre ss n, the
next curren t address read operati on would access dat a
from address n + 1. Upon receipt of the sl ave add res s
with R/W bit set to ‘1’, the 24XX04 issues an acknowl-
edge and tran smits the 8-bit dat a word. The maste r will
not acknowledge the transfer , but does generate a S top
condition and the 24XX04 discontinues transmission
(Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad ope ratio n, th e w ord add res s mus t firs t
be set. This is accomplished by sending the word
address to the 24XX04 as part of a write operation.
Once th e word address is s ent, the master ge nerates a
Start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
Address Pointer is set. The master then issues the
control byt e agai n, but wi th the R/ W bit se t to a ‘ 1’. The
24XX04 will then issue an acknowledge and transmit
the 8-bit data word. The master will not acknowledge
the transfer , but do es generate a S top condition and the
24XX04, will discontinue transmission (Figure 7-2).
7.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random read, except that once the 24XX04 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX04 to transmit the next sequentially-
addressed 8-bit word (Figure 7-3).
To provide sequential reads, the 24XX04 contains an
internal Address Pointer that is incremented by one
upon completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24XX04 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 7-1: CURRENT ADDRESS READ
SP
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Control
Byte Data (n)
A
C
K
N
o
A
C
K
S
T
A
R
T
x = “don’t care”
Block
Select
Bits
101
0xx
B0 1
24AA04/24LC04B
DS21708E-page 10 © 2005 Microchip Technology Inc.
FIGURE 7-2: RANDOM READ
FIGU RE 7-3 : SEQUE NT I AL RE A D
S P
S
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
A
R
T
S
T
O
P
Control
Byte
A
C
K
Word
Address (n) Control
Byte
S
T
A
R
TData (n)
A
C
K
A
C
K
N
o
A
C
K
x = “don’t care”
Block
Select
Bits
Block
Select
Bits
10 10xx 0
B0 B0
1010xx 1
P
Bus Acti vity
Master
SDA Line
Bus Acti vity
S
T
O
P
Control
Byte
A
C
K
N
o
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + x)
A
C
K
A
C
K
A
C
K
1
© 2005 Microchip Technology Inc. DS21708E-page 11
24AA04/24LC04B
8.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.
TABLE 8-1: PIN FUNCTION TABLE
8.1 Serial Address/Data Input/Output
(SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the de vice . Sinc e it i s an open-
drain terminal, the SDA bus requires a pull-up resistor
to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
8.2 Serial Clock (SCL)
The SCL in pu t is u se d to s ynchro ni ze th e da t a tra ns fer
to and from the device.
8.3 Wr it e-Protect (WP)
The WP pin must be connected to either VSS or VCC.
If tied to VSS, normal memory operation is enabled
(read/wri te the ent ire memory 000-1 FF).
If tied to VCC, write operations are inhibited. The entire
memory will be write-protected. Read operations are
not affected.
This feature allows the user to use the 24XX04 as a
serial ROM when WP is enabled (tied to VCC).
8.4 A0, A1, A2
The A0, A1 and A2 pins are not used by the 24XX04.
They may be left floating or tied to either VSS or VCC.
Name PDIP SOIC TSSOP DFN MSOP SOT23 Description
A0 1 1 1 1 1 Not Connected
A1 2 2 2 2 2 Not Connected
A2 3 3 3 3 3 Not Connected
VSS 444 4 4 2Ground
SDA 5 5 5 5 5 3 Serial Address/Data I/O
SCL666 6 6 1Serial Clock
WP 7 7 7 7 7 5 W rite -Prote ct Input
VCC 8 8 8 8 8 4 +1.8V to 5.5V Power Supply
24AA04/24LC04B
DS21708E-page 12 © 2005 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
T/XXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Lead SOIC (150 mil) Example:
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSS OP Example:
24LC04B
I/P 13F
0527
24LC04BI
SN 0527
13F
8-Lead MSOP Example:
XXXX
TYWW
NNN
XXXXXT
YWWNNN
4L04
I527
13F
4L4BI
52713
5-Lead SOT-23 Example:
XXNN M33F
8-Lead 2x3 DFN Example:
234
527
13
XXX
YWW
NN
3
e
3
e
© 2005 Microchip Technology Inc. DS21708E-page 13
24AA04/24LC04B
Part Number
1st Line Marking Codes
TSSOP MSOP SOT-23 DFN
I Temp. E Temp. I Temp. E Temp.
24AA04 4A04 4A04T B3NN 231
24LC04B 4L04 4L4BT M3NN N3NN 234 235
Note: T = Temperature grade (I, E)
NN = Alphanumeric traceability code
Legend: XX...X Part number or part number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week o f January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the event the full Mi croch ip pa rt numbe r canno t be marke d on one line , it wil
l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
24AA04/24LC04B
DS21708E-page 14 © 2005 Microchip Technology Inc.
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
© 2005 Microchip Technology Inc. DS21708E-page 15
24AA04/24LC04B
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004
A1
Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
24AA04/24LC04B
DS21708E-page 16 © 2005 Microchip Technology Inc.
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Lengt h 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1M old ed Packag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002
A1
Standoff § 0.950.900.85.037.035.033A2Molded Packag e Thickness 1.10.043AOverall Height 0.65.026
p
Pitch 88
n
Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERS*INCHES
Units
α
A2
A
A1
L
c
β
φ
1
2D
n
p
B
E
E1
Foot A ngle φ048048
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.005” (0.127mm) per side.
JEDEC Equivalent: MO-153
Drawing No. C04-086
§ Significant Characteristic
© 2005 Microchip Technology Inc. DS21708E-page 17
24AA04/24LC04B
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
D
A
A1
L
c
(F)
α
A2
E1
E
p
B
n 1
2
φ
β
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
.037 REFFFootprint (Reference)
exceed .010" (0.254mm) per side.
Notes:
Drawing No. C04-111
*Controlling Parameter
Mold Draft Angle Top
Mold Draft Angle Bottom
Foot Angle
Lead Width
Lead Thickness
β
α
c
B
φ
.003
.009
.006
.012
Dimension Limits
Overall Height
Molded Package Thickness
Molded Package Width
Overall Length
Foot Length
Standoff
Overall Width
Number of Pins
Pitch
A
L
E1
D
A1
E
A2
.016 .024
.118 BSC
.118 BSC
.000
.030
.193 TYP.
.033
MIN
p
n
Units
.026 BSC
NOM
8
INCHES
0.95 REF
-
-
.009
.016
0.08
0.22
0.23
0.40
MILLIMETERS*
0.65 BSC
0.85
3.00 BSC
3.00 BSC
0.60
4.90 BSC
.043
.031
.037
.006
0.40
0.00
0.75
MIN
MAX NOM
1.10
0.80
0.15
0.95
MAX
8
--
-
15° -
15° -
JEDEC Equivalent: MO-187
-
-
-
15°
15°
--
--
24AA04/24LC04B
DS21708E-page 18 © 2005 Microchip Technology Inc.
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
10501050
β
Mold Draft Angle Bottom 10501050
α
Mold Draft Angle Top 0.500.430.35.020.017.014BLead Width 0.200.150.09.008.006.004
c
Lead Thickness 10501050
φ
Foot A ngle 0.550.450.35.022.018.014LFoot Lengt h 3.102.952.80.122.116.110DOverall Length 1.751.631.50.069.064.059E1Molded Pa ckag e Width 3.002.802.60.118.110.102EOverall Width 0.150.080.00.006.003.000A1Standoff § 1.301.100.90.051.043.035A2Molded Packag e Thickness 1.451.180.90.057.046.035AOverall Height 1.90.075
p1
Outside lead pitch (basic) 0.95
.038
p
Pitch 55
n
Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units
1
p
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-178
Drawing No. C04-091
§ Significant Characteristic
© 2005 Microchip Technology Inc. DS21708E-page 19
24AA04/24LC04B
8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
Exposed Pad Width
Exposed Pad Length
Contact Length
*Controlling Parameter
Contact Width
Drawing No. C04-123
Notes:
Exposed pad dimensions vary with paddle size.
Overall Width
E2
D2
L
b
E
.016
.012
.008
.047
.055
.010
.118 BSC
Number of Pins
Standoff
Contact Thickness
Overall Length
Overall Height
Pitch p
n
Units
A
A1
D
A3
Dimension Limits
8
.000 .001
.008 REF.
.079 BSC
.031
.020 BSC
MIN
INCHES
NOM
0.40
0.25
3.00 BSC
0.30
.020
.071
.012
.064
0.20
1.20
1.39
0.50
0.30
1.80
1.62
0.02
0.80
2.00 BSC
0.20 REF.
0.50 BSC
MILLIMETERS*
.002
.039
0.00
MINMAX NOM
8
0.05
1.00
MAX
3.
Package may have one or more exposed tie bars at ends.1.
Pin 1 visual index feature may vary, but must be located within the hatched area.2.
0.90.035
(Note 3)
(Note 3)
4. JEDEC equivalent: MO-229
L
E2
A3 A1
A
TOP VIEW
D
E
EXPOSED
PAD
METAL
D2
BOTTOM VIEW
21
b
p
n
(NOTE 1)
EXPOSED
TIE BAR
PIN 1
(NOTE 2)
ID INDEX
AREA
Revised 05/24/04
-- --
-- --
24AA04/24LC04B
DS21708E-page 20 © 2005 Microchip Technology Inc.
APPENDIX A: REVISIO N HIST ORY
Revision C
Corrections to Section 1.0, Electrical Characteristics.
Revision D
Added DFN package.
Revision E
Revi se d F ig ur e 3 -2 C o nt ro l B yte Al l oc at io n; Fi g ure 4- 1
Byte Write; Figure 4-2 Page Write; Section 6.0 Write
Protectio n; Figure 7-1 Curre nt Address Read ; Figure 7-
2 Random Read; Figure 7-3 Sequential Read.
© 2005 Microchip Technology Inc. DS21708E-page 21
24AA04/24LC04B
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microchi p.c om . Thi s web si te i s us ed as a m ean s
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Users of Microchip products can receive assistance
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Customers should contact their distributor,
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Technical s upport is a vailable through the web site
at: http://support.microchip.com
24AA04/24LC04B
DS21708E-page 22 © 2005 Microchip Technology Inc.
READER RESPONSE
It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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DS21708E24AA04/24LC04B
1. What are the best features of t his doc ument?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
© 2005 Microchip Technology Inc. DS21708E-page23
24AA04/24LC04B
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured
before January 2005 will have a finish of approx imately 63% Sn and 37% Pb (Sn/Pb). Please v isit www.microchip.com
for the latest information on Pb-free conversion, including conversion date codes.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. T he Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.micr ochip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.m icrochip.com /cn) to receive the most current information on our products.
PART NO. X/XX
PackageTemperature
Range
Device
Device: 24AA04: = 1.8V, 4 Kbit I2C Ser ial EE PR OM
24AA04T: = 1.8V, 4 Kbit I2C Serial EEPROM
(Tape and Reel)
24LC04B: = 2.5V, 4 Kbit I2C Serial EEPROM
24LC04BT: = 2.5V, 4 Kbit I2C Serial EEPROM
(Tape and Reel)
Temperature
Range: I = -40°C to +85°C
E = -40°C to +125°C
Package: MC = 2x3 DFN, 8-lead
P = Plastic DIP (300 mil body), 8-lead
SN = Plastic SOIC (150 mil body), 8-lead
ST = Plastic TSSO P (4.4 mm ), 8-lead
MS = Plastic Micro Small Outline (MSOP), 8-lead
OT = SOT-23, 5-lead (Tape and Reel only)
Lead Finish: Blank = Pb-free – Matte Tin (see Note 1)
G = Pb-free – Matte Tin only
Examples:
a) 24AA04-I/P: Industrial Temper ature ,
1.8V, PDIP package
b) 24AA04-I/SN: Industrial Temperature,
1.8V, SOIC package
c) 24AA04T-I/OT: Industrial Temperature,
1.8V, SOT-23 package, tape and reel
d) 24LC04B-I/P: Industrial Temperature,
2.5V, PDIP package
e) 24LC04B-E/SN: Extended Temperature,
2.5V, SOIC package
f) 24LC04BT -I/OT: Industrial Temperature,
2.5V, SOT-23 package, tape and reel
X
Lead Finish
24AA04/24LC04B
DS21708E-page 24 © 2005 Microchip Technology Inc.
NOTES:
© 2005 Microchip Technology Inc. DS21708E-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION, INCLUDING BUT NOT
LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and
its use. U se of Microc hip’s products as critical com ponents in
life support systems is not authorized except with express
written approval by Microchip. No licenses are conveyed,
implicitly or otherwise, under any Microchip intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXD EV, MXLAB,
PICMASTER, SEEVAL, SmartSensor and The Embedded
Control Solutions Company are registered trademarks of
Microchip Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Linear Active Thermistor,
MPASM , MPLIB, MPL I N K, MPSIM, PI Ckit , PICDEM,
PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,
PowerMate, Powe rTool, rfLAB, rfPICDEM , Select Mode,
Smart Serial, SmartTel, Total Endurance and WiperLock are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2005, Microchip Te chnology Incorporat ed, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its f amily of products is one of the most secure families of its kind on the market today, when used in t he
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ection f eatures of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21708E-page 26 © 2005 Microchip Technology Inc.
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