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SRC4382
1
FEATURES
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
Two-Channel, Asynchronous Sample Rate Converter withIntegrated Digital Audio Interface Receiver and Transmitter
Digital Audio Interface Receiver (DIR)
234
Two-Channel Asynchronous Sample Rate PLL Lock Range Includes Sampling RatesConverter (SRC) from 20kHz to 216kHz Dynamic Range with 60dB Input Includes Four Differential Input Line(A-Weighted): 128dB typical Receivers and an Input Multiplexer Total Harmonic Distortion and Noise Bypass Multiplexer Routes Line Receiver(THD+N) with Full-Scale Input: 125dB Outputs to Line Driver and Buffer Outputstypical
Block-Sized Data Buffers for Both Channel Supports Audio Input and Output Data Status and User DataWord Lengths Up to 24 Bits
Automatic Detection of Non-PCM Audio Supports Input and Output Sampling Streams (DTS CD/LD and IEC 61937Frequencies Up to 216kHz formats) Automatic Detection of the Input-to-Output Audio CD Q-Channel Sub-Code DecodingSampling Ratio and Data Buffer Wide Input-to-Output Conversion Range: Status Registers and Interrupt Generation16:1 to 1:16 Continuous for Flag and Error Conditions Excellent Jitter Attenuation Characteristics Low Jitter Recovered Clock Output Digital De-Emphasis Filtering for 32kHz, Two Audio Serial Ports (Ports A and B)44.1kHz, and 48kHz Input Sampling Rates
Synchronous Serial Interface to External Digital Output Attenuation and Mute Signal Processors, Data Converters, andFunctions Logic Output Word Length Reduction Slave or Master Mode Operation withSampling Rates up to 216kHz Status Registers and Interrupt Generationfor Sampling Ratio and Ready Flags Supports Left-Justified, Right-Justified, andPhilips I
2
S™ Data FormatsDigital Audio Interface Transmitter (DIT)
Supports Audio Data Word Lengths Up to Supports Sampling Rates Up to 216kHz
24 Bits Includes Differential Line Driver and
Four General-Purpose Digital OutputsCMOS Buffered Outputs
Multifunction Programmable Via Control Block-Sized Data Buffers for Both Channel
RegistersStatus and User Data
Extensive Power-Down Support Status Registers and Interrupt Generationfor Flag and Error Conditions Functional Blocks May Be DisabledIndividually When Not In UseUser-Selectable Serial Host Interface: SPI orPhilips I
2
C™ Operates From +1.8V Core and +3.3V I/OPower Supplies Provides Access to On-Chip Registers andData Buffers Small TQFP-48 Package, Compatible with theSRC4392 and DIX4192U.S. Patent No. 7,262,716
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Dolby is a registered trademark of Dolby Laboratories.3I2C, I2S are trademarks of Koninklijke Philips Electronics N.V.4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
www.ti.com
APPLICATIONS DESCRIPTION
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
DIGITAL AUDIO RECORDERS AND
The SRC4382 is a highly-integrated CMOS deviceMIXING DESKS
designed for use in professional and broadcast digitalDIGITAL AUDIO INTERFACES FOR
audio systems. The SRC4382 combines aCOMPUTERS
high-performance, two-channel, asynchronoussample rate converter (SRC) with a digital audioDIGITAL AUDIO ROUTERS AND
interface receiver (DIR) and transmitter (DIT), twoDISTRIBUTION SYSTEMS
audio serial ports, and flexible distribution logic forBROADCAST STUDIO EQUIPMENT
interconnection of the function block data and clocks.DVD/CD RECORDERS
The DIR and DIT are compatible with the AES3,SURROUND SOUND DECODERS AND
S/PDIF, IEC 60958, and EIAJ CP-1201 interfaceA/V RECEIVERS
standards. The audio serial ports, DIT, and SRC mayCAR AUDIO SYSTEMS
be operated at sampling rates up to 216kHz. The DIRlock range includes sampling rates from 20kHz to216kHz.
The SRC4382 is configured using on-chip controlregisters and data buffers, which are accessedthrough either a 4-wire serial peripheral interface(SPI) port, or a 2-wire Philips I
2
C bus interface.Status registers provide access to a variety of flagand error bits, which are derived from the variousfunction blocks. An open drain interrupt output pin isprovided, and is supported by flexible interruptreporting and mask options via control registersettings. A master reset input pin is provided forinitialization by a host processor or supervisoryfunctions.
The SRC4382 requires a +1.8V core logic supply, inaddition to a +3.3V supply for powering portions ofthe DIR, DIT, and line driver and receiver functions. Aseparate logic I/O supply supports operation from+1.65V to +3.6V, providing compatibility with lowvoltage logic interfaces typically found on digitalsignal processors and programmable logic devices.The SRC4382 is available in a lead-free, TQFP-48package, and is pin- and register-compatible with theTexas Instruments SRC4392 and DIX4192 products.
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ABSOLUTE MAXIMUM RATINGS
(1)
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
OPERATINGPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY
SRC4382IPFBT Tape and Reel, 250SRC4382 TQFP-48 PFB 40C to +85C SRC4382I
SRC4382IPFBR Tape and Reel, 2000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Power Supplies
VDD18 0.3V to +2.0VVDD33 0.3V to +4.0VVIO 0.3V to +4.0VVCC 0.3V to +4.0VDigital Input Voltage: Digital LogicRXCKI, MUTE, CPM, CS, CCLK, CDIN, CDOUT, INT, RST, MCLK, BLS, SYNC, BCKA,
0.3V to (VIO + 0.3V)BCKB, LRCKA, LRCKB, SDINA, SDINBLine Receiver Input Voltage (per pin)RX1+, RX1 , RX2+, RX2 , RX3+, RX3 , RX4+, RX4 (VDD33 + 0.3) V
PP
Input Current (all pins except power and ground) 10mAAmbient Operating Temperature 40C to +85CStorage Temperature 65C to +150C
(1) These limits are stress ratings only. Stresses beyond these limits may result in permanent damage. Extended exposure to absolutemaximum ratings may degrade device reliability. Normal operation or performance at or beyond these limits is not specified or ensured.
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ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL I/O CHARACTERISTICS
(All I/O Pins Except Line Receivers and Line Driver)
High-Level Input Voltage, V
IH
0.7 נVIO VIO V
Low-Level Input Voltage, V
IL
0 0.3 נVIO V
High-Level Input Current, I
IH
0.5 10 μA
Low-Level Input Current, V
IL
0.5 10 μA
High-Level Output Voltage, V
OH
I
O
= 4mA 0.8 נVIO VIO V
Low-Level Output Voltage, V
OL
I
O
= +4mA 0 0.2 נVIO V
Input Capacitance, C
IN
3 pF
LINE RECEIVER INPUTS(RX1+, RX1 , RX2+, RX2 , RX3+, RX3 , RX4+, RX4 )
Voltage across a givenDifferential Input Sensitivity, V
TH
150 200 mVdifferential input pair
Input Hysteresis, V
HY
150 mV
LINE DRIVER OUTPUTS(TX+, TX )
Differential Output Voltage, V
TXO
R
L
= 110 Across TX+ and TX 5.4 V
PP
MASTER CLOCK INPUT
Master Clock Input (MCLK) Frequency, f
MCLK
1 27.7 MHz
Master Clock Input (MCLK) Duty Cycle, f
MCLKD
45 55 %
ASYNCHRONOUS SAMPLE RATE CONVERTER (SRC)
Input or Output Sampling Rate, f
SIN
or f
SOUT
4 216 kHz
Input-to-Output Sampling Ratio 1:16 16:1
Interchannel Gain Mismatch 0 dB
Interchannel Phase Mismatch 0 Degrees
Dynamic Range (no weighting filter applied)
(1)
BW = 22Hz to f
SOUT
/2,f = 997Hz at 60dBFS
f
SIN
:f
SOUT
= 12kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:12kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:192kHz 125 dB
(1) Measured with an Audio Precision SYS-2722 192kHz test system with the input and output sampling frequencies asynchronous to oneanother. A-weighted dynamic range specifications will be improved by approximately 2dB to 3dB when compared to the results withoutA-weighting applied.
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SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT (continued)All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
Total Harmonic Distortion + Noise (THD+N)
(2)
BW = 22Hz to f
SOUT
/2,f = 997Hz at 0dBFS
f
SIN
:f
SOUT
= 12kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 44.1kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 48kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 96kHz:192kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:12kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:44.1kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:48kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:96kHz 125 dB
f
SIN
:f
SOUT
= 192kHz:192kHz 125 dB
Digital Interpolation Filter Characteristics
Passband 0.4535 נf
SIN
Hz
Passband Ripple 0.007 dB
Transition Band 0.4535 נf
SIN
0.5465 נf
SIN
Hz
Stop Band 0.5465 נf
SIN
Hz
Stop Band Attenuation 125 dB
Group Delay (64 samples pre-buffered) Decimation filter enabled 102.53125/f
SIN
Seconds
Group Delay (64 samples pre-buffered) Direct down-sampling enabled 102/f
SIN
Seconds
Group Delay (32 samples pre-buffered) Decimation filter enabled 70.53125/f
SIN
Seconds
Group Delay (32 samples pre-buffered) Direct down-sampling enabled 70/f
SIN
Seconds
Group Delay (16 samples pre-buffered) Decimation filter enabled 54.53125/f
SIN
Seconds
Group Delay (16 samples pre-buffered) Direct down-sampling enabled 54/f
SIN
Seconds
Group Delay (8 samples pre-buffered) Decimation filter enabled 46.53125/f
SIN
Seconds
Group Delay (8 samples pre-buffered) Direct down-sampling enabled 46/f
SIN
Seconds
Digital Decimation Filter Characteristics
Passband 0.4535 נf
SOUT
Hz
Passband Ripple 0.008 dB
Transition Band 0.4535 נf
SOUT
0.5465 נf
SOUT
Hz
Stop Band 0.5465 נf
SOUT
Hz
Stop Band Attenuation 125 dB
Group Delay Decimation filter enabled 36.46875/f
SOUT
Seconds
Group Delay Direct down-sampling enabled 0 Seconds
Digital De-Emphasis Filter Characteristics
Filter Error for All Settings De-emphasis filter enabled 0.001 dB
(2) Measured with an Audio Precision SYS-2722 192kHz test system with the input and output sampling frequencies asynchronous to oneanother.
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ELECTRICAL CHARACTERISTICS: Audio Serial Ports
ELECTRICAL CHARACTERISTICS: SPI Interface
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
ELECTRICAL CHARACTERISTICS: General, SRC, DIR, and DIT (continued)All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
DIGITAL AUDIO INTERFACE RECEIVER (DIR)
PLL Lock Range 20 216 kHz
Reference Clock Input (RXCKI) Frequency, f
RXCKI
3.5 27.7 MHz
Reference Clock Input (RXCKI) Duty Cycle, f
RXCKID
45 55 %
Recovered Clock Output (RXCKO) Frequency, f
RXCKO
3.5 27.7 MHz
Recovered Clock Output (RXCKO) Duty Cycle, f
RXCKOD
45 55 %
Recovered Clock Output (RXCKO) Intrinsic Jitter Measured cycle-to-cycle 250 ps RMS
DIGITAL AUDIO INTERFACE TRANSMITTER (DIT)
Intrinsic Output Jitter Measured cycle-to-cycle 200 ps RMS
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
AUDIO SERIAL PORTS (Port A and Port B)
LRCK Clock Frequency, f
LRCK
0 216 kHzLRCK Clock Duty Cycle, t
LRCKD
50 %BCK Clock Frequency, f
BCK
0 13.824 MHzBCK High Pulse Width, t
BCKH
10 nsBCK Low Pulse Width, t
BCKL
10 nsAudio Data Input (SDIN) Setup Time, t
AIS
10 nsAudio Data Input (SDIN) Hold Time, t
AISH
10 nsAudio Data Output (SDOUT) Delay, t
ADD
10 ns
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
HOST INTERFACE: SPI Mode
Serial Clock (CCLK) Frequency, f
CCLK
0 40 MHzCS Falling to CCLK Rising, t
CSCR
8 nsCCLK Falling to CS Rising, t
CFCS
7 nsCDIN Data Setup Time, t
CDS
7 nsCDIN Data Hold Time, t
CDH
6 nsCCLK Falling to CDOUT Data Valid, t
CFDO
3 nsCS Rising to CDOUT High-Impedance, t
CSZ
3 ns
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ELECTRICAL CHARACTERISTICS: I
2
C Standard and Fast Modes
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
HOST INTERFACE: I
2
C Standard Mode
(1)
SCL Clock Frequency, f
SCL
0 100 kHz
Hold Time Repeated START Condition, t
HDSTA
4μs
Low Period of SCL Clock, t
LOW
4.7 μs
High Period of SCL Clock, t
HIGH
4μs
Setup Time Repeated START Condition, t
SUSTA
4.7 μs
Data Hold Time, t
HDDAT
0
(2)
3.45
(3)
μs
Data Setup Time, t
SUDAT
250 ns
Rise Time for Both SDA and SDL, t
R
1000 ns
Fall Time for Both SDA and SDL, t
F
300 ns
Setup Time for STOP Condition, t
SUSTO
4μs
Bus Free Time Between START and STOP, t
BUF
4.7 μs
Capacitive Load for Each Bus Line, C
B
400 pF
Noise Margin at Low Level (including hysteresis), V
NL
0.1 נVIO V
Noise Margin at High Level (including hysteresis), V
NH
0.2 נVIO V
HOST INTERFACE: I
2
C Fast Mode
(1)
SCL Clock Frequency, f
SCL
0 400 kHz
Hold Time Repeated START Condition, t
HDSTA
0.6 μs
Low Period of SCL Clock, t
LOW
1.3 μs
High Period of SCL Clock, t
HIGH
0.6 μs
Setup Time Repeated START Condition, t
SUSTA
0.6 μs
Data Hold Time, t
HDDAT
0
(2)
0.9
(3)
μs
Data Setup Time, t
SUDAT
100
(4)
ns
Rise Time for Both SDA and SDL, t
R
20 + 0.2C
B
(5)
300 ns
Fall Time for Both SDA and SDL, t
F
20 + 0.2C
B
(5)
300 ns
Setup Time for STOP Condition, t
SUSTO
0.6 μs
Bus Free Time Between START and STOP, t
BUF
1.3 μs
Spike Pulse Width Suppressed by Input Filter, t
SP
0 50 ns
Capacitive Load for Each Bus Line, C
B
400 pF
Noise Margin at Low Level (including hysteresis), V
NL
0.1 נVIO V
Noise Margin at High Level (including hysteresis), V
NH
0.2 נVIO V
(1) All values referred to the V
IH
minimum and V
IL
maximum levels listed in the Digital I/O Characteristics section of the ElectricalCharacteristics: General, SRC, DIR, and DIT table.(2) A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IH
minimum input level) to bridge theundefined region of the falling edge of SCL.(3) The maximum t
HDDAT
has only to be met if the device does not stretch the Low period (t
LOW
) of the SCL signal.(4) A Fast mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement that t
SUDAT
be 250ns minimum mustthen be met. For the SRC4382, this is automatically the case, since the device does not stretch the Low period of the SCL signal.(5) C
B
is defined as the total capacitance of one bus line in picofarads (pF). If mixed with High-Speed mode devices, faster fall times areallowed.
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ELECTRICAL CHARACTERISTICS: Power Supplies
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwise noted.
SRC4382
PARAMETER CONDITIONS MIN TYP MAX UNITS
POWER SUPPLIES
Recommended Supply Voltage Range
VDD18 +1.65 +1.8 +1.95 V
VDD33 +3.0 +3.3 +3.6 V
VIO +1.65 +3.3 +3.6 V
VCC +3.0 +3.3 +3.6 V
Supply Current: Initial Startup All Blocks Powered Down by Default
IDD18S VDD18 = +1.8V 90 μA
IDD33S VDD33 = +3.3V 1 μA
IIOS VIO = +3.3V 270 μA
ICCS VCC = +3.3V 1 μA
Supply Current: Quiescent All Blocks Powered Up with No Clocks Applied
IDD18Q VDD18 = +1.8V 3.1 mA
IDD33Q VDD33 = +3.3V 0.5 mA
IIOQ VIO = +3.3V 0.27 mA
ICCQ VCC = +3.3V 6.6 mA
Supply Current: Dynamic All Blocks Powered Up, f
S
= 48kHz
IDD18D VDD18 = +1.8V 23 mA
IDD33D VDD33 = +3.3V 14 mA
IIOD
(1)
VIO = +3.3V 43 mA
ICCD VCC = +3.3V 8 mA
Supply Current: High Sampling Rate All Blocks Powered Up, f
S
= 192kHz
IDD18H VDD18 = +1.8V 58 mA
IDD33H VDD33 = +3.3V 15 mA
IIOH
(1)
VIO = +3.3V 44 mA
ICCH VCC = +3.3V 8 mA
Total Power Dissipation: Initial Startup All Blocks Powered Down by Default 1 mW
Total Power Dissipation: Quiescent All Blocks Powered Up with No Clocks Applied 30 mW
Total Power Dissipation: Dynamic All Blocks Powered Up, f
S
= 48kHz 256 mW
Total Power Dissipation: High Sampling Rate All Blocks Powered Up, f
S
= 192kHz 326 mW
(1) The typical VIO supply current is measured using the SRC4382EVM evaluation module with loading from the DAIMB mother-boardcircuitry. VIO supply current will be dependent upon the loading on the logic output pins.
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TIMING DIAGRAMS
LRCK
BCK
SDIN
tAIS
SDOUT
tAIH
tAOD
tBCKL
tBCKH
CS
CC KL
CDNI
CDOUT
tCFCS
tCDH
HiZ HiZ
tCSCR tCDS
tCFDO tCSZ
SDA
SCL
S R P S
tF
tHDSTA
tLOW tR
tHDDAT
tSUDAT
tF
tBUF
S=Start nCo dition R=Repea edStartt Condition P=Stop Co ditionn
tSUSTA tSUSTO
tHDSTA tSP tR
tHIGH
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
Figure 1. Audio Serial Port Timing
Figure 2. SPI Interface Timing
Figure 3. I
2
C Standard and Fast Mode Timing
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PIN CONFIGURATION
TopView TQFP
36
35
34
33
32
31
30
29
28
27
26
25
SYNC
BLS
AESOUT
VDD33
TX+
TX-
DGND2
GPO4
GPO3
GPO2
GPO1
MCLK
BCKB
LRCKB
SDINB
SDOUTB
BGND
DGND3
VIO
NC
SDOUTA
SDINA
LRCKA
BCKA
RXCKI
MUTE
RDY
DGND1
VDD18
CPM
CS
CCLK
CDIN
CDOUT
INT
RST
1
2
3
4
5
6
7
8
9
10
11
12
RX1+
RX1-
RX2+
RX2-
RX3+
RX3-
RX4+
RX4-
VCC
AGND
LOCK
RXCKO
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
SRC4382
NC=NoConnection
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
PIN DESCRIPTIONSNAME PIN NUMBER I/O DESCRIPTION
RX1+ 1 Input Line Receiver 1, Noninverting Input
RX1 2 Input Line Receiver 1, Inverting Input
RX2+ 3 Input Line Receiver 2, Noninverting Input
RX2 4 Input Line Receiver 2, Inverting Input
RX3+ 5 Input Line Receiver 3, Noninverting Input
RX3 6 Input Line Receiver 3, Inverting Input
RX4+ 7 Input Line Receiver 4, Noninverting Input
RX4 8 Input Line Receiver 4, Inverting Input
VCC 9 Power DIR Comparator and PLL Power Supply, +3.3V Nominal
AGND 10 Ground DIR Comparator and PLL Power-Supply Ground
LOCK 11 Output DIR PLL Lock Flag (active Low)
RXCKO 12 Output DIR Recovered Master Clock (tri-state output)
RXCKI 13 Input DIR Reference Clock
MUTE 14 Input SRC Output Mute (active High)
RDY 15 Output SRC Ready Flag (active Low)
DGND1 16 Ground Digital Core Ground
VDD18 17 Power Digital Core Supply, +1.8V Nominal
CPM 18 Input
Control Port Mode, 0 = SPI Mode, 1 = I
2
C Mode
CS or A0 19 Input
Chip Select (active Low) for SPI Mode or Programmable Slave Address for I
2
C Mode
CCLK or SCL 20 Input
Serial Data Clock for SPI Mode or I
2
C Mode
CDIN orA1 21 Input
SPI Port Serial Data input or Programmable Slave Address for I
2
C Mode
CDOUT or SDA 22 I/O
SPI Port Serial Data Output (tri-state output) or Serial Data I/O for I
2
C Mode
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SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
PIN DESCRIPTIONS (continued)NAME PIN NUMBER I/O DESCRIPTION
INT 23 Output Interrupt Flag (open-drain, active Low)
RST 24 Input Reset (active Low)
MCLK 25 Input Master Clock
GPO1 26 Output General-Purpose Output 1
GPO2 27 Output General-Purpose Output 2
GPO3 28 Output General-Purpose Output 3
GPO4 29 Output General-Purpose Output 4
DGND2 30 Ground DIR Line Receiver Bias and DIT Line Driver Digital Ground
TX 31 Output DIT Line Driver Inverting Output
TX+ 32 Output DIT Line Driver Noninverting Output
VDD33 33 Power DIR Line Receiver Bias and DIT Line Driver Supply, +3.3V Nominal
AESOUT 34 Output DIT Buffered AES3-Encoded Data
BLS 35 I/O DIT Block Start Clock
SYNC 36 Output DIT internal Sync Clock
BCKA 37 I/O Audio Serial Port A Bit Clock
LRCKA 38 I/O Audio Serial Port A Left/Right Clock
SDINA 39 Input Audio Serial Port A Data Input
SDOUTA 40 Output Audio Serial Port A Data Output
NC 41 No Internal Signal Connection, Internally Bonded to ESD Pad
VIO 42 Power Logic I/O Supply, +1.65V to +3.6V
DGND3 43 Ground Logic I/O Ground
BGND 44 Ground Substrate Ground, Connect to AGND (pin 10)
SDOUTB 45 Output Audio Serial Port B Data Output
SDINB 46 Input Audio Serial Port B Data Input
LRCKB 47 I/O Audio Serial Port B Left/Right Clock
BCKB 48 I/O Audio Serial Port B Bit Clock
Copyright © 2006 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
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TYPICAL CHARACTERISTICS
SamplingRate(kHz)
THD+N(dB)
32
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
52 72 92 112 132 152 172 192
SamplingRate(kHz)
THD+N(dB)
32
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
52 72 92 112 132 152 172 192
SamplingRate(kHz)
THD+N(dB)
32
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
52 72 92 112 132 152 172 192
SamplingRate(kHz)
THD+N(dB)
32
-115
-117
-119
-121
-123
-125
-127
-129
-131
-133
-135
52 72 92 112 132 152 172 192
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwisenoted.
THD+N vs INPUT SAMPLING RATE THD+N vs INPUT SAMPLING RATE(f
SOUT
= 44.1kHz and f
IN
= 997Hz at 0dBFS) (f
SOUT
= 48kHz and f
IN
= 997Hz at 0dBFS)
Figure 4. Figure 5.
THD+N vs INPUT SAMPLING RATE THD+N vs INPUT SAMPLING RATE(f
SOUT
= 96kHz and f
IN
= 997Hz at 0dBFS) (f
SOUT
= 192kHz and f
IN
= 997Hz at 0dBFS)
Figure 6. Figure 7.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 44.1kHz:44.1kHz and (f
SIN
:f
SOUT
= 44.1kHz:48kHz andInput Amplitude = 0dBFS) Input Amplitude = 0dBFS)
Figure 8. Figure 9.
12 Submit Documentation Feedback Copyright © 2006 2007, Texas Instruments Incorporated
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www.ti.com
SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwisenoted.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 44.1kHz:96kHz and (f
SIN
:f
SOUT
= 44.1kHz:192kHz andInput Amplitude = 0dBFS) Input Amplitude = 0dBFS)
Figure 10. Figure 11.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 48kHz:44.1kHz and Input Amplitude = 0dBFS) (f
SIN
:f
SOUT
= 48kHz:48kHz and Input Amplitude = 0dBFS)
Figure 12. Figure 13.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 48kHz:96kHz and Input Amplitude = 0dBFS) (f
SIN
:f
SOUT
= 48kHz:192kHz and Input Amplitude = 0dBFS)
Figure 14. Figure 15.
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SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwisenoted.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 96kHz:44.1kHz and Input Amplitude = 0dBFS) (f
SIN
:f
SOUT
= 96kHz:48kHz and Input Amplitude = 0dBFS)
Figure 16. Figure 17.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 96kHz:96kHz and Input Amplitude = 0dBFS) (f
SIN
:f
SOUT
= 96kHz:192kHz and Input Amplitude = 0dBFS)
Figure 18. Figure 19.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 192kHz:44.1kHz and (f
SIN
:f
SOUT
= 192kHz:48kHz andInput Amplitude = 0dBFS) Input Amplitude = 0dBFS)
Figure 20. Figure 21.
14 Submit Documentation Feedback Copyright © 2006 2007, Texas Instruments Incorporated
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SRC4382
SBFS030C JANUARY 2006 REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS (continued)All specifications are at T
A
= +25C, VDD18 = +1.8V, VDD33 = +3.3V, VIO = +3.3V, and VCC = +3.3V, unless otherwisenoted.
THD+N vs INPUT FREQUENCY THD+N vs INPUT FREQUENCY(f
SIN
:f
SOUT
= 192kHz:96kHz and Input Amplitude = 0dBFS) (f
SIN
:f
SOUT
= 192kHz:192kHz and Input Amplitude = 0dBFS)
Figure 22. Figure 23.
THD+N vs INPUT AMPLITUDE THD+N vs INPUT AMPLITUDE(f
SIN
:f
SOUT
= 44.1kHz:44.1kHz and (f
SIN
:f
SOUT
= 44.1kHz:48kHz andInput Frequency = 997Hz) Input Frequency = 997Hz)
Figure 24. Figure 25.
THD+N vs INPUT AMPLITUDE THD+N vs INPUT AMPLITUDE(f
SIN
:f
SOUT
= 44.1kHz:96kHz and Input Frequency = 997Hz) (f
SIN
:f
SOUT
= 44.1kHz:192kHz and Input Frequency = 997Hz)
Figure 26. Figure 27.
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