1. General description
The PCA9511A is a hot swappable I2C-bus and SMBus buffer that allows I/O card
insertion into a live backplane without corrupting the data and clock buses. Control
circuitry prevents the backplane from being connected to the card until a stop command or
bus idle occurs on the backplane without bus contention on the card. When the
connection is made, the PCA9511A provides bidirectional buffering, keeping the
backplane and card capacitances isolated.
The PCA9511A rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9511A incorporates a digital
ENABLE input pin, which enables the device when asserted HIGH and forces the device
into a low current mode when asserted LOW, and an open-drain READY output pin, which
indicates that the backplane and card sides are connected together (HIGH) or not (LOW).
During insertion, the PCA9511A SDA and SCL lines are precharged to 1 V to minimize
the current required to charge the parasitic capacitance of the chip.
2. Features
nBidirectional buffer for SDA and SCL lines increases fan out and prevents SDA and
SCL corruption during live board insertion and removal from multipoint backplane
systems
nCompatible with I2C-bus Standard-mode, I2C-bus Fast-mode, and SMBus standards
nBuilt-in V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold)
requires the bus pull-up voltage and supply voltage (VCC) to be the same
nActive HIGH ENABLE input
nActive HIGH READY open-drain output
nHigh-impedance SDA and SCL pins for VCC =0V
n1 V precharge on all SDA and SCL lines
nSupporting clock stretching and multiple master arbitration/synchronization
nOperating power supply voltage range: 2.7 V to 5.5 V
n0 Hz to 400 kHz clock frequency
nESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
nLatch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
nPackages offered: SO8, TSSOP8 (MSOP8)
PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Rev. 04 — 19 August 2009 Product data sheet
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 2 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
3. Applications
ncPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are
required to be inserted or removed from an operating system
4. Feature selection
5. Ordering information
[1] Also known as ‘MSOP8’.
Table 1. Feature selection chart
Feature PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A
idle detect yes yes yes yes yes
high-impedance SDA, SCL pins for VCC = 0 V yes yes yes yes yes
rise time accelerator circuitry on SDAn and SCLn lines - yes yes yes yes
rise time accelerator circuitry hardware disable pin for
lightly loaded systems --yes--
rise time accelerator threshold 0.8 V versus 0.6 V
improves noise margin ---yesyes
ready open-drain output yes yes - yes yes
two VCC pins to support 5 V to 3.3 V level translation with
improved noise margins --yes--
1 V precharge on all SDA and SCL lines in only yes yes - -
92 µA current source on SCLIN and SDAIN for PICMG
applications ---yes-
Table 2. Ordering information
T
amb
=
40
°
C to +85
°
C
Type number Topside
mark Package
Name Description Version
PCA9511AD PA9511A SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9511ADP 9511A TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width 3 mm SOT505-1
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 3 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
6. Block diagram
Fig 1. Block diagram of PCA9511A
002aab580
100 k
RCH3
1 V OLT
PRECHARGE 100 k
RCH4
100 k
RCH1
100 k
RCH2
CONNECT
ENABLE
BACKPLANE-TO-CARD
CONNECTION
SLEW RATE
DETECTOR SLEW RATE
DETECTOR
CONNECT CONNECT
2 mA 2 mA
BACKPLANE-TO-CARD
CONNECTION
SLEW RATE
DETECTOR SLEW RATE
DETECTOR
CONNECT CONNECT
2 mA 2 mA
SDAIN
SCLIN
0.5 pF
SCLOUT
RD
SQB
UVLO
20 pF
0.55VCC/
0.45VCC
0.5 µA
STOP BIT AND
BUS IDLE
0.55VCC/
0.45VCC
100 µs
DELAY
UVLO
ENABLE
SDAOUT
VCC
CONNECT
CONNECT
READY
GND
PCA9511A
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 4 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
7.2 Pin description
8. Functional description
Refer to Figure 1 “Block diagram of PCA9511A”.
8.1 Start-up
An undervoltage/initialization circuit holds the parts in a disconnected state which
presents high-impedance to all SDA and SCL pins during power-up. A LOW on the
ENABLE pin also forces the parts into the low current disconnected state when the ICC is
essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is
powered and the ENABLE is taken from LOW to HIGH it enters an initialization state
where the internal references are stabilized and the precharge circuit is enabled. At the
end of the initialization state the ‘Stop Bit And Bus Idle’ detect circuit is enabled. With the
ENABLE pin HIGH long enough to complete the initialization state (ten) and remaining
HIGH when all the SDA and SCL pins have been HIGH for the bus idle time or when all
pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT. The 1 V precharge circuitry
Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8
ENABLE VCC
SCLOUT SDAOUT
SCLIN SDAIN
GND READY
002aab577
1
2
3
4
6
5
8
7
PCA9511AD PCA9511ADP
ENABLE VCC
SCLOUT SDAOUT
SCLIN SDAIN
GND READY
002aab578
1
2
3
4
6
5
8
7
Table 3. Pin description
Symbol Pin Description
ENABLE 1 Chip enable. Grounding this input puts the part in a low current (< 1 µA)
mode. It also disables the rise time accelerators, isolates SDAIN from
SDAOUT and isolates SCLIN from SCLOUT.
SCLOUT 2 serial clock output to and from the SCL bus on the card
SCLIN 3 serial clock input to and from the SCL bus on the backplane
GND 4 Ground. Connect this pin to a ground plane for best results.
READY 5 open-drain output which pulls LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT, and goes HIGH when the two
sides are connected
SDAIN 6 serial data input to and from the SDA bus on the backplane
SDAOUT 7 serial data output to and from the SDA bus on the card
VCC 8 power supply
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 5 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
is activated during the initialization and is deactivated when the connection is made. The
precharge circuitry pulls up the SDA and SCL pins to 1 V through individual 100 k
nominal resistors. This precharges the pins to 1 V to minimize the worst case
disturbances that result from inserting a card into the backplane where the backplane and
the card are at opposite logic levels.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as
SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that
isolates the input capacitance from the output bus capacitance while communicating the
logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be
driven to a LOW by the part. The same is also true for the SCL pins. Noise between
0.7VCC and VCC is generally ignored because a falling edge is only recognized when it
falls below 0.7VCC with a slew rate of at least 1.25 V/µs. When a falling edge is seen on
one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small
voltage above the falling pin. The driver will pull the pin down at a slew rate determined by
the driver and the load initially, because it does not start until the first falling pin is below
0.7VCC. The first falling pin may have a fast or slow slew rate, if it is faster than the pull
down slew rate then the initial pull-down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew rate only until it is just
above the first pin voltage then they will both continue down at the slew rate of the first.
Once both sides are LOW they will remain LOW until all the external drivers have stopped
driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV
by external drivers, which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will rise until the internal
driver pulls it down to the offset voltage. When the last external driver stops driving a
LOW, that pin will rise up and settle out just above the other pin as both rise together with
a slew rate determined by the internal slew rate control and the RC time constant. As long
as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V for the
PCA9511A, the rise time accelerator’s circuits are turned on and the pull-down driver is
turned off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher
temperatures. Maximum offset (Voffset) is 0.150 V with a 10 k pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is that the I2C-bus specification of 3 mA will produce VOL < 0.4 V,
although if lightly loaded the VOL may be ~0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V,
the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of
the rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 6 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and buffer B
in series as shown in Figure 4. Consider if the VOL at the input of buffer A is 0.3 V and the
VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
Slave B and then from Slave B to Master. Before the direction change you would observe
VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output
of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ~0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred
before the data setup time. If this were the SCL line, the parts on buffer A and buffer C
would see a false clock rather than a stretched clock, which would cause a system error.
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus
resistors and the rise time accelerator current source and the effective capacitance on the
lines. If the pull-up currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides. The tPLH may be
negative if the output capacitance is less than the input capacitance and would be positive
if the output capacitance is larger than the input capacitance, when the currents are the
same.
The tPHL can never be negative because the output does not start to fall until the input is
below 0.7VCC, and the output turn on has a non-zero delay, and the output has a limited
maximum slew rate, and even if the input slew rate is slow enough that the output catches
up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL
occurs when the input is driven LOW with zero delay and the output is still limited by its
Fig 4. System with 3 buffers connected to common node
002aab581
buffer C
buffer Bbuffer A
common
node SLAVE B
SLAVE C
MASTER
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 7 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function
of the internal maximum slew rate which is a function of temperature, VCC and process, as
well as the load current and the load capacitance.
8.5 Rise time accelerators
During positive bus transitions a 2 mA current source is switched on to quickly slew the
SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9511A is exceeded.
The rising edge rate should be at least 1.25 V/µs to guarantee turn on of the accelerators.
The built-in V/∆t rise time accelerators on all SDA and SCL lines requires the bus pull-up
voltage and supply voltage (VCC) to be the same.
8.6 READY digital output
This pin provides a digital flag which is LOW when either ENABLE is LOW or the start-up
sequence described earlier in this section has not been completed. READY goes HIGH
when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of
10 k to VCC to provide the pull-up.
8.7 ENABLE low current disable
Grounding the ENABLE pin disconnects the backplane side from the card side, disables
the rise time accelerators, drives READY LOW, disables the bus precharge circuitry, and
puts the part in a low current state. When the pin voltage is driven all the way to VCC, the
part waits for data transactions on both the backplane and card sides to be complete
before reconnecting the two sides.
8.8 Resistor pull-up value selection
The system pull-up resistors must be strong enough to provide a positive slew rate of
1.25 V/µs on the SDA and SCL pins, in order to activate the boost pull-up currents during
rising edges. Choose maximum resistor value using the formula given in Equation 1:
(1)
where R is the pull-up resistor value in , VCC(min) is the minimum VCC voltage in volts,
and C is the equivalent bus capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always choose R 65.7 kfor VCC = 5.5 V
maximum, R 45 kfor VCC = 3.6 V maximum. The start-up circuitry requires logic HIGH
voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these
pull-up values are needed to overcome the precharge voltage. See the curves in Figure 5
and Figure 6 for guidance in resistor pull-up selection.
R 800 103
×VCC min()
0.6
C
-----------------------------------


PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 8 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A.
(2) Rise time without PCA9511A.
Fig 5. Bus requirements for 3.3 V systems
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9511A.
(2) Rise time without PCA9511A.
Fig 6. Bus requirements for 5 V systems
Cb (pF)
0 400300200100
002aae780
20
10
30
50
RPU
(k)
0
Rmax = 45 k
rise time = 20 ns
Rmin = 1 k
rise time = 300 ns(2)
40
(1)
Cb (pF)
0 400300200100
002aae781
70
RPU
(k)
0
10
20
30
40
50
60
(1)
Rmax = 65.7 k
rise time = 20 ns
Rmin = 1.7 k
rise time = 300 ns(2)
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 9 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
8.9 Hot swapping and capacitance buffering application
Figure 7 through Figure 10 illustrate the usage of the PCA9511A in applications that take
advantage of both its hot swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the backplane, all of the
backplane and card capacitances would add directly together, making rise time and
fall time requirements difficult to meet. Placing a bus buffer on the edge of each card,
however, isolates the card capacitance from the backplane. For a given I/O card, the
PCA9511A drives the capacitance of everything on the card and the backplane must drive
only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and
all additional cards on the backplane.
See
Application Note AN10160, ‘Hot Swap Bus Buffer’
for more information on
applications and technical assistance.
Remark: The PCA9511A can be used in any combination depending on the number of rise time accelerators that are needed
by the system. Normally only one PCA9511A would be required per bus.
Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a cPCI, VME, and AdvancedTCA
system
002aab584
R4
10 k
C1
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
R5
10 kR6
10 k
R3
10 k
ENABLE
SDAIN
SCLIN
POWER SUPPLY
HOT SWAP
CARD1_SDA
CARD1_SCL
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 1
BACKPLANE
CONNECTOR
R8
10 k
C3
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
R9
10 kR10
10 k
R7
10 k
ENABLE
SDAIN
SCLIN
POWER SUPPLY
HOT SWAP
CARD2_SDA
CARD2_SCL
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 2
R12
10 k
C5
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
R13
10 kR14
10 k
R11
10 k
ENABLE
SDAIN
SCLIN
POWER SUPPLY
HOT SWAP
CARDN_SDA
CARDN_SCL
STAGGERED CONNECTOR
I/O PERIPHERAL CARD N
R2
10 k
R1
10 k
VCC
BACKPLANE
BD_SEL
SDA
SCL
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 10 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9511A in a PCI system
002aab585
R4
10 k
C1
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
R5
10 kR6
10 k
ENABLE
SDAIN
SCLIN
CARD1_SDA
CARD1_SCL
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 1
BACKPLANE
CONNECTOR
R8
10 k
C3
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
R9
10 kR10
10 k
ENABLE
SDAIN
SCLIN
CARD2_SDA
CARD2_SCL
STAGGERED CONNECTOR
I/O PERIPHERAL CARD 2
R2
10 k
R1
10 k
VCC
BACKPLANE
SDA
SCL
C4
0.01 µF
C2
0.01 µF
Remark: See
Application Note AN255, ‘I2C repeaters, hubs, and expanders’
for more information on other devices better
optimized for long distance transmission of the I2C-bus or SMBus.
Fig 9. Repeater/bus extender application using the PCA9511A
002aab586
R7
10 k
C2
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
ENABLE
SDAIN
SCLIN
R8
10 k
VCC
SDA1
SCL1 to other
System 2
devices
I2C-bus System 2
R6
10 k
R4
10 k
C1
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
ENABLE
SDAIN
SCLIN
R1
10 k
VCC = 5 V
SDA1
SCL1
to other
System 1
devices
I2C-bus System 1
R5
10 k
long
distance
bus
R3
10 k
R2
10 k
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 11 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
9. Application design-in information
10. Limiting values
[1] Voltages with respect to pin GND.
VCC >V
CC_LOW
Rdrop is the line loss of VCC in the backplane.
Fig 10. System with disparate VCC voltages
002aab587
R4
10 k
C2
0.01 µF
SDAOUT
SCLOUT
READY
VCC
GND
ENABLE
SDAIN
SCLIN
R1
10 k
VCC
SDA
SCL
R5
10 k
Rdrop VCC_LOW
R2
10 kR3
10 k
SDA2
SCL2
Fig 11. Typical application
002aab579
ENABLE READY
GND
4
5
7
2
R5
10 kR3
10 kR4
10 k
SCLOUT
SDAOUT
1
6
3
C1
0.01 µF
8
R1
10 kR2
10 k
VCC
(2.7 V to 5.5 V)
SCLIN
SDAIN
ENABLE
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage [1] 0.5 +7 V
Vnvoltage on SDAIN, SCLIN, SDAOUT,
SCLOUT, READY, ENABLE [1] 0.5 +7 V
Toper operating temperature 40 +85 °C
Tstg storage temperature 65 +150 °C
Tsp solder point temperature 10 s max. - +300 °C
Tj(max) maximum junction temperature - +125 °C
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 12 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
11. Characteristics
Table 5. Characteristics
V
CC
= 2.7 V to 5.5 V; T
amb
=
40
°
C to +85 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Power supply
VCC supply voltage [1] 2.7 - 5.5 V
ICC supply current VCC = 5.5 V;
VSDAIN =V
SCLIN =0V [1] - 3.5 6 mA
ICC(sd) Shut-down mode supply
current VENABLE = 0 V; all other pins at
VCC or GND - 0.1 - µA
Start-up circuitry
Vpch precharge voltage SDA, SCL floating [1] 0.8 1.1 1.2 V
VIH(ENABLE) HIGH-level input voltage
on pin ENABLE - 0.5 ×VCC 0.7 ×VCC V
VIL(ENABLE) LOW-level input voltage
on pin ENABLE 0.3 × VCC 0.5 ×VCC -V
II(ENABLE) input current on pin
ENABLE VENABLE = 0 V to VCC -±0.1 ±1µA
ten enable time [2] - 110 - µs
tidle(READY) bus idle time to READY
active [1] 50 105 200 µs
tdis(EN-RDY) disable time (ENABLE to
READY) -30-ns
tstp(READY) SDAIN to READY delay
after STOP [3] - 1.2 - µs
tREADY SCLOUT/SDAOUT to
READY delay [3] - 0.8 - µs
ILZ(READY) off-state leakage current
on pin READY VENABLE =V
CC -±0.3 - µA
Ci(ENABLE) input capacitance on
pin ENABLE VI=V
CC or GND [4] - 1.9 4.0 pF
Co(READY) output capacitance on
pin READY VI=V
CC or GND [4] - 2.5 4.0 pF
VOL(READY) LOW-level output
voltage on pin READY Ipu = 3 mA; VENABLE =V
CC [1] - - 0.4 V
Rise time accelerators
Itrt(pu) transientboostedpull-up
current positive transition on SDA,
SCL; VCC = 2.7 V;
slew rate = 1.25 V/µs
[5][6] 12-mA
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 13 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
[1] This specification applies over the full operating temperature range.
[2] The enable time can slow considerably for some parts when temperature is < 20 °C.
[3] Delays that can occur after ENABLE and/or idle times have passed.
[4] Guaranteed by design, not production tested.
[5] Itrt(pu) varies with temperature and VCC voltage, as shown in Section 11.1 “Typical performance characteristics”.
[6] Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage
to the positive supply rail.
[7] The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function
of the pull-up resistor and VCC voltage is shown in Section 11.1 “Typical performance characteristics”.
[8] Cb = total capacitance of one bus line in pF.
Input-output connection
Voffset offset voltage 10 k to VCC on SDA, SCL;
VCC = 3.3 V [1][7][9] 0 110 175 mV
tPLH LOW to HIGH
propagation delay SCL to SCL and SDA to SDA;
10 k to VCC;
CL= 100 pF each side
-0-ns
tPHL HIGH to LOW
propagation delay SCL to SCL and SDA to SDA;
10 k to VCC;
CL= 100 pF each side
-70-ns
Ci(SCL/SDA) SCL and SDA input
capacitance [4] - 57pF
VOL LOW-level output
voltage VI= 0 V; SDAn, SCLn pins;
Isink = 3 mA; VCC = 2.7 V [1] 0 - 0.4 V
ILI input leakage current SDAn, SCLn pins; VCC = 5.5 V 1-+1µA
System characteristics
fSCL SCL clock frequency [4] 0 - 400 kHz
tBUF bus free time between a
STOP and START
condition
[4] 1.3 - - µs
tHD;STA hold time (repeated)
START condition [4] 0.6 - - µs
tSU;STA set-up time for a
repeated
START condition
[4] 0.6 - - µs
tSU;STO set-up time for
STOP condition [4] 0.6 - - µs
tHD;DAT data hold time [4] 300 - - ns
tSU;DAT data set-up time [4] 100 - - ns
tLOW LOW period of the
SCL clock [4] 1.3 - - µs
tHIGH HIGH period of the
SCL clock [4] 0.6 - - µs
tffall time of both SDA and
SCL signals [4][8] 20 + 0.1 ×Cb- 300 ns
trrise time of both SDA
and SCL signals [4][8] 20 + 0.1 ×Cb- 300 ns
Table 5. Characteristics
…continued
V
CC
= 2.7 V to 5.5 V; T
amb
=
40
°
C to +85 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 14 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
[9] Force VSDAIN = VSCLIN = 0.1 V, tie SDAOUT and SCLOUT through 10 k resistor to VCC and measure the SDAOUT and SCLOUT
output.
11.1 Typical performance characteristics
Fig 12. ICC versus temperature Fig 13. Itrt(pu) versus temperature
Ci=C
o> 100 pF; RPU(in) =R
PU(out) =10k
Fig 14. Input/output tPHL versus temperature Fig 15. Connection circuitry VOVI
Tamb (°C)
40 +90+25
002aab588
2.9
3.3
3.7
ICC
(mA)
2.5
3.3 V
VCC = 5.5 V
2.7 V
Tamb (°C)
40 +90+25
002aab590
4
8
12
Itrt(pu)
(mA)
0
3.0 V
VCC = 5 V
2.7 V
Tamb (°C)
40 +90+25
002aab589
70
80
90
tPHL
(ns)
60
3.3 V
VCC = 5.5 V
2.7 V
RPU (k)
0403010 20
002aab591
150
250
350
VO VI
(mV)
50
VCC = 5 V
3.3 V
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 15 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
11.2 Timing diagrams
Fig 16. Timing for ten, tidle(READY), and tdis
002aab592
ten
SDAn/SCLn
ENABLE
READY
tidle(READY) tdis
tstp(READY) is only applicable after the ten delay.
Fig 17. tstp(READY) that can occur after ten
002aab593
ten
SCLIN
SCLOUT
SDAOUT
ENABLE
READY
tstp(READY)
SDAIN
tstp(READY) is only applicable after the ten delay.
Fig 18. tstp(READY) delay that can occur after ten and tidle(READY)
002aab594
ten
tidle(READY)
SCLIN, SDAIN,
SCLOUT, SDAOUT
ENABLE
READY
tstp(READY)
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 16 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
12. Test information
RL = load resistor
CL = load capacitance includes jig and probe capacitance
RT = termination resistance should be equal to the output impedance Z0 of the pulse generators.
Fig 19. Test circuitry for switching times
PULSE
GENERATOR
VO
CL
100 pF
RL
10 k
002aab595
RT
VI
VCC
VCC
DUT
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 17 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
13. Package outline
Fig 20. Package outline SOT96-1 (SO8)
UNIT A
max. A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 5.0
4.8 4.0
3.8 1.27 6.2
5.8 1.05 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.10.25
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
1.0
0.4
SOT96-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
4
5
pin 1 index
1
8
y
076E03 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.20
0.19 0.16
0.15 0.05 0.244
0.228 0.028
0.024 0.028
0.012
0.010.010.041 0.004
0.039
0.016
0 2.5 5 mm
scale
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
99-12-27
03-02-18
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Product data sheet Rev. 04 — 19 August 2009 18 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
Fig 21. Package outline SOT505-1 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.45
0.25 0.28
0.15 3.1
2.9 3.1
2.9 0.65 5.1
4.7 0.70
0.35 6°
0°
0.1 0.10.10.94
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.7
0.4
SOT505-1 99-04-09
03-02-18
wM
bp
D
Z
e
0.25
14
85
θ
A
A2A1
Lp
(A3)
detail X
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
1.1
pin 1 index
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 19 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note
AN10365 “Surface mount reflow
soldering description”
.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
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Product data sheet Rev. 04 — 19 August 2009 20 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 22) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 6 and 7
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 22.
Table 6. SnPb eutectic process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Table 7. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 21 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
For further information on temperature profiles, refer to Application Note
AN10365
“Surface mount reflow soldering description”
.
15. Abbreviations
MSL: Moisture Sensitivity Level
Fig 22. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
Table 8. Abbreviations
Acronym Description
AdvancedTCA Advanced Telecommunications Computing Architecture
CDM Charged Device Model
cPCI compact Peripheral Component Interface
ESD Electrostatic Discharge
HBM Human Body Model
I2C-bus Inter IC bus
MM Machine Model
PCI Peripheral Component Interface
PICMG PCI Industrial Computer Manufacturers Group
SMBus System Management Bus
VME VERSAModule Eurocard
PCA9511A_4 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 04 — 19 August 2009 22 of 24
NXP Semiconductors PCA9511A
Hot swappable I2C-bus and SMBus bus buffer
16. Revision history
Table 9. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9511A_4 20090819 Product data sheet - PCA9511A_3
Modifications: Section 8.8 “Resistor pull-up value selection”, 2nd paragraph, 1st sentence: changed from
“... always choose R 16 k for VCC = 5.5 V maximum, R 24 k for VCC = 3.6 V maximum.
to “... always choose R 65.7 k for VCC = 5.5 V maximum, R 45 k for VCC = 3.6 V
maximum.
Figure 5 “Bus requirements for 3.3 V systems” updated:
changed from “rise time > 300 ns” to “rise time = 300 ns”
changed from “rise time < 20 ns” to “rise time = 20 ns”
Figure 6 “Bus requirements for 5 V systems” updated:
changed from “rise time > 300 ns” to “rise time = 300 ns”
changed from “rise time < 20 ns” to “rise time = 20 ns”
PCA9511A_3 20090720 Product data sheet - PCA9511A_2
PCA9511A_2 20090528 Product data sheet - PCA9511A_1
PCA9511A_1
(9397 750 13269) 20050815 Product data sheet - -