FW82454GX - Intel - Datasheet.Live

PRELIMINARY

Intel 450KX/GX PCIset

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PRELIMINARY

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PRELIMINARY iii

AContents

Chapter 1 Intel 450KX/GX PCIset Overview

1.0 Intel 45 0KX PCIs et .. .... ... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ .... ....... .... ........ ........ ... ........ .... ....... .5

2.0 Intel 45 0GX PCIs et .. ....... .... ........ .... ....... ........ .... ....... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ ........ ... .6

3.0 Host Bus Efficiency ..................................................................................................................................6

4.0 System Memory Map ................................................................................................................................7

4.1 Comp atibi li ty Are a .... .... .... .... .... ....... .... ........ ... ........ .... ........ ... ........ ........ ... ........ .... ........ ... ........ .... ....... .8

4.2 Extended Memory (ISA) .....................................................................................................................9

4.3 Extended Memory (EISA) .................................................................................................................10

4.4 Extended Memory (above 4 Gbytes) ................................................................................................12

4.5 System Management Mode (SMM) ..................................................................................................12

5.0 I/O Space (PB Only) .... ... ........ .... ....... .... ........ .... ....... .... ........ .... ....... .... ........ ... ........ ........ .... ....... .... ........ ..12

6.0 Memory Mapped I/O ...............................................................................................................................13

Chapter 2 82454KX/GX PCI Bridge (PB)

1.0 PB Signal Descriptions ..........................................................................................................................19

1.1 PB Signals .......................................................................................................................................19

1.2 Signa l State Durin g Res et ... .... ... .... ........ .... ....... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ ........ ..25

2.0 PB Register Description ........................................................................................................................26

2.1 Initialization and Configuration ..........................................................................................................26

2.2 I/O Space Registers ..........................................................................................................................27

2.2.1 CONFADD—Configuration Address Register ........................................................................28

2.2.2 TRC—Turbo and Reset ControL ............................................................................................29

2.2.3 CONFDATA—Configuration Data Register ............................................................................30

2.3 PCI Config ura tio n Spa ce ......... ... ........ .... ....... .... ........ .... ....... .... ........ .... ....... ........ .... ....... .... ........ .... ..30

2.4 PB PCI Configuration Registers .......................................................................................................32

2.4.1 VID—Vendor Identification Register .......................................................................................34

2.4.2 DID—Device Identification Register .......................................................................................34

2.4.3 PCICMD—PCI Command Register .......................................................................................34

2.4.4 PCISTS—PCI Status Register ...............................................................................................35

2.4.5 RID—Revision Identification Register ....................................................................................36

2.4.6 CLASSC—Class Code Register ............................................................................................36

2.4.7 CLSIZE—Cache Line Size Register ......................................................................................36

2.4.8 PLTMR—PCI Latency Timer ..................................................................................................37

2.4.9 HEADT—Header Type Register .............................................................................................37

2.4.10 BIST—Bist register ..............................................................................................................37

2.4.1 1 TSM— To p of Sy stem Memo ry Reg iste r .... .... .... ....... .... ........ .... ....... .... ........ .... ....... .... ........ ..38

2.4.12 PDM—PCI Decode Mode ....................................................................................................38

iv PRELIMINARY

2.4.13 BDNUM—Bridge Device Number Register ..........................................................................39

2.4.14 PBNUM—PCI Bus Number Register ...................................................................................39

2.4.15 PSBNUM—Subordinate Bus Number Register ...................................................................40

2.4.16 PBC—PB Configuration Register .........................................................................................40

2.4.17 DCC—Deturbo Counter Register .........................................................................................41

2.4.18 CRWC—CPU Read/Write Control Register .........................................................................41

2.4.19 PRWC—PCI Read/Write Control .........................................................................................42

2.4.20 SMME—SMRAM Enable Register .......................................................................................43

2.4.21 VBAE—Video Buffer Area Enable Register .........................................................................43

2.4.22 PAM[0:6]—Programmable Attribute MAp Register ...............................................................44

2.4.23 ERRCMD—Error Reporting Command Register .................................................................45

2.4.24 ERRSTS—Error Reporting Status Register .........................................................................45

2.4.25 MGR—Memory Gap Range Register ..................................................................................46

2.4.26 MGUA—Memory Gap Upper Address Register ...................................................................46

2.4.27 PFB—PCI Frame Buffer Register .........................................................................................47

2.4.28 HMGSA—High Memory Gap Range Start Address Register ..............................................48

2.4.29 HMGEA—High Memory Gap End Address Register ...........................................................48

2.4.30 IOSR1—I/O Space Range 1 Register (82454GX Only) .......................................................49

2.4.31 PCIRSR—PCI Reset Register .............................................................................................49

2.4.32 IOSR2—I/O Space Range 2 Register (82454GX Only) .......................................................50

2.4.33 APICR—I/O APIC Range Register ......................................................................................50

2.4.34 CONFVR—Configuration Values Driven on Reset Register ................................................51

2.4.35 CSCONFV—Captured System Configuration Va lues Register ............................................52

2.4.36 SMMR—SMRAM Range Register .......................................................................................53

2.4.37 HBIOSR—High BIOS Range Register .................................................................................53

2.4.38 EXERRCMD—PB Extended Error Reporting Command Register ......................................53

2.4.39 EXERRSTS—PB Extended Error Reporting Status ............................................................55

2.4.40 PBRTMR—PB Retry Timers ................................................................................................56

3.0 PB Functional Description ....................................................................................................................57

3.1 Memory and I/O Map ........................................................................................................................57

3.1.1 Memory Address Map ............................................................................................................57

3.1.2 I/O Address Map ....................................................................................................................59

3.2 Host Bus Interface ............................................................................................................................60

3.3 PCI Bus Interf ace ..............................................................................................................................61

3.4 Data Integrity and Error Handling .....................................................................................................62

3.4. 1 Host Bus Err ors .... .... .... ....... .... ........ ... ........ .... ........ ... ........ .... ....... ........ .... ........ ... ........ .... .......62

3.4. 2 PCI Bus Errors . .... .... .... ....... ........ .... ....... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ ........ ...62

3.4.2.1 PB Master Operation on PCI ....................................................................................63

3.4.2.2 PB Target Operation on PCI .....................................................................................63

3.5 Dual PB Architectures (82454GX Only) ............................................................................................65

PRELIMINARY v

3.6 Peripheral Operation and Performance ............................................................................................68

3.6.1 Matching Peripherals to the 450KX/GX .................................................................................68

3.6.2 Distributing Peripherals Within the I/O Subsystem .................................................................69

3.6.3 PCI-to-PCI Bridges ................................................................................................................69

3.6.4 BIOS Performance Tuning ......................................................................................................69

3.7 Clock, Reset, and Configuration .......................................................................................................70

3.7.1 System clocking .....................................................................................................................70

3.7.1.1 Host Bus Clock .........................................................................................................70

3.7.1.2 PCI Clock ..................................................................................................................71

3.7.2 System Reset .........................................................................................................................71

3.7.3 System Initialization ...............................................................................................................72

3.7.4 Dual PB Configuration (82454GX only) .................................................................................72

3.7.5 Using the 82379AB SIO.A PCI-to-ISA Bridge with the 450KX/GX .........................................73

3.8 Host to PCI Bus Command Translation ............................................................................................76

3.9 PCI to Host Bus Command Translation ............................................................................................77

4.0 PB Pinout and Package Information .....................................................................................................79

4.1 Pin Assignment .................................................................................................................................79

4.2 Package Information .........................................................................................................................87

Chapter 3 Memory Controller (MC)

1.0 MC Signal Description ...........................................................................................................................93

1.1 DC Signals ........................................................................................................................................93

1.2 DP Signals ........................................................................................................................................96

1.3 MIC Signals ......................................................................................................................................98

1.4 Signa l State Durin g Res et ... .... ... .... ........ .... ....... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ ........100

2.0 MC Regis ter D es crip tion ... ........ ....... .... ........ .... ....... .... ........ .... ....... .... ........ ... ........ .... ........ ... ........ ........101

2.1 Initialization and Configuration ........................................................................................................101

2.2 I/O Space Registers ........................................................................................................................102

2.2.1 CONFADD—Configuration Address Register ......................................................................103

2.2.2 CONFDATA—Configuration Data Register ..........................................................................103

2.3 MC Configur ation Registers ............................................................................................................104

2.3.1 VID—Vendor Identification Register .....................................................................................105

2.3.2 DID—Device Identification Register .....................................................................................105

2.3.3 PCICMD—PCI Command Register .....................................................................................106

2.3.4 PCISTS—PCI Status Register .............................................................................................106

2.3.5 RID—Revision Identification Register ..................................................................................106

2.3.6 CLASSC—Class Code Register ..........................................................................................107

2.3.7 BASEADD—MC Base Address Register (450GX only) .......................................................107

2.3.8 CDNUM—Controller Device Number Register ....................................................................108

2.3.9 CMD—Command Register ..................................................................................................108

vi PRELIMINARY

2.3.10 SMME—SMRAM Enable Register .....................................................................................110

2.3. 11 VB RE—Vide o Bu ffer Region Ena ble Regis te r ..... ... ........ .... ....... .... ........ .... ....... .... ........ ..... 1 10

2.3.12 PAM[0:6]—Programmable Attribute Map Registers ...........................................................110

2.3.13 DRL—DRAM Row Limit (0 to 7) .........................................................................................111

2.3.14 SBCERRADD—Single Bit Correctable Error Address Register .........................................112

2.3.15 MG—Memory Gap Register ..............................................................................................113

2.3.16 MGUA—Memory Gap Upper Address Register .................................................................114

2.3.17 LMG—Low Memory Gap Register .....................................................................................114

2.3.18 HMGSA—High Memory Gap Start Address Register ........................................................115

2.3.19 HMGEA—High Memory Gap End Address Register .........................................................115

2.3.20 APICR—I/O APIC Range Register ....................................................................................115

2.3.21 UERRADD—Uncorrectable Error Address Register ..........................................................116

2.3.22 MEMTIM—Memory Timing Register ..................................................................................116

2.3.23 SMMR—SMRAM Range Register .....................................................................................119

2.3.24 HBIOSR—High BIOS Gap Range Register .......................................................................119

2.3.25 MERRCMD—Memory Error Reporting Command ............................................................120

2.3.26 MERRSTS—Memory Error Status Register ......................................................................120

2.3.27 SERRCMD—System Error Reporting Command Register ................................................121

2.3.28 SERRSTS—System Error Status Register ........................................................................122

2.4 Memory Configuration Determination Algorithm .............................................................................122

3.0 MC Functional Description ..................................................................................................................123

3.1 Memory and I/O Map ......................................................................................................................123

3.2 Host Bus Interface ..........................................................................................................................124

3.3 DRAM Interface ..............................................................................................................................125

3.3.1 DRAM Configurations ..........................................................................................................127

3.3.1.1 Memory Interface Component (MIC) ......................................................................127

3.3.1.2 4-Way DRAM Configuration (450GX Only) .............................................................128

3.3.1 .3 2-Wa y DRAM con fig urati on .. .... .... ........ ....... .... ........ .... ....... .... ........ .... ....... .... ........ . 1 29

3.3.1.4 Non-Interleaved DRAM configuration .....................................................................130

3.4 Clocks and Reset ............................................................................................................................131

3.4.1 Clocks ..................................................................................................................................131

3.4.2 Reset ....................................................................................................................................131

4.0 MC Pinout and Package Information ..................................................................................................132

4.1 82453KX/82453GX (DC) Pin Assignment ......................................................................................132

4.2 82452GX/82452KX (DP) Pin Assignment ......................................................................................135

4.3 82451GX/82451KX (MIC) Pin Assignment .....................................................................................142

4.4 82453GX/82453KX (DC) Package Dimensions ..............................................................................145

4.5 82452GX/82452KX (DP) Package Dimensions ..............................................................................146

4.6 82451GX/82451KX (MIC) Package Dimensions ............................................................................148

PRELIMINARY vii

Chapter 4 PCIset E lectrical Specifications

1.0 Electrical Characteristics ....................................................................................................................151

1.1 Test Pins and Unused Pins .............................................................................................................151

1.2 Signa l Grou ps ... .... ... .... .... ........ ... ........ ........ ... ........ .... ........ ... ........ .... ....... .... ........ .... ....... .... ........ ....151

1.2.1 The Power Good Signal— PWRGD .....................................................................................152

1.3 Maximum Ratings ...........................................................................................................................153

1.4 DC Specifications ...........................................................................................................................154

1.5 AC Specifications ............................................................................................................................157

1.5.1 Wa veforms ...........................................................................................................................160

2.0 Signal Quality .......................................................................................................................................162

2.1 I/O Signal Simulations—Ensuring I/O Timings ...............................................................................162

2.2 Signa l Qua lit y Speci fi catio ns ... ... .... .... ........ ... ........ ........ .... ....... .... ........ ... ........ .... ........ ... ........ .... ....163

2.3 PCIset Ringback Specification ........................................................................................................163

2.4 450KX/GX Undershoot Specification ..............................................................................................165

3.0 Therm al Spe ci fic atio ns ......... .... ....... ........ .... ....... .... ........ .... ....... .... ........ .... ....... .... ........ .... ....... .... ........166

Index

Alphabet ize d Index .. .... .... ... ........ .... ....... .... ........ .... ....... .... ........ ....... .... ........ .... ....... .... ........ .... ....... .... ........169

viii PRELIMINARY

PRELIMINARY 1

APCIset Overview

Chapter 1

Intel 450KX/GX PCIset Overview

2PRELIMINARY

PCIset Overview A

APCIset Overvi e w

PRELIMINARY 3

PCIset Product Overview

■PCIset Ho st Bus Support

— Supports Pentium Pro Processor

at 60 MHz, and 66 M Hz Bus Speeds

— 64-Bit Data and 36-Bit Address Bus

— Parity Protection on Control

Signals

— Dual-Processor Support (450KX)

— Up to Eight Deep In-Order Queue

— Fou r Deep Outbound Request

Queue

— Four Cache Li ne Read and Write

Buffers

— GTL+ Bus Driver Technology

■Host-to-PCI Bridge ( PB)

— Combi nes Both t he Control and

Data Path in a Single Chip

— Synchronous PCI Interface

— 32-bit Address/ Data PCI Bus (64-bit

Dual Cycle Address Support)

— Parity Protection on All PCI Bus

Signals

— Four Deep Inbound Request Queue

— Data Coll ection /Write Assembly of

Line Bursts.

— Support for 3.3V & 5V PCI Devices

— Available i n 304 Pin QFP or 352 pin

BGA

— ECC Protection on Host Dat a Bus

(450GX)

— Quad-Processor Support (450GX)

— Inte rnal Bridge Arbi ter For T wo PBs

in a system (450GX)

■Memory Controller (MC)

— 1 GB Maximum Memory (450KX)

— 2-W ay inte rleaved and Non-

Interleaved Memory Organizations

— Supports 3. 3V and 5V SIMMs

— Supports Standard 32- o r 36-bit

SIMMs or 72-bit DIMM s

— Supports 4 Mbit, 16 Mbit, and

64 Mbit DRAM Technology

— Single Bit Error Correction, Double

Bit and Nibble Error Detection

— Memory Array Power Management

— Recovers DRAM Memo ry Behi nd

Programmable Mem ory Gaps

— Read Page Hit 8-1-1-1 (at 66 MHz,

60 ns DRAM)

— Read Page Miss 11-1-1-1 ( 66 MHz ,

60 ns DRAM)

— Read Page M iss + Precharge 14-1-1-

1 (66 MHz, 60 ns DRAM)

— Available i n 208-Pin QFP for the DC;

240- Pin QFP or 256-Pin BGA for the

DP; 144-Pin QFP for the MIC

■On-Chip Digital PLL (Both PB and MC)

■Test Suppo rt (JTAG) (Both PB and MC)

— 4 GBs Maximum Main Memory (per

82453GX)

— 4-Way and 2-Way interleaved, and

Non-Int erleaved Me mory

Organizations (450GX)

— Up to Two MCs in a System (450GX)

This document describes both the Intel 450KX and 450GX PCIsets. Unshaded areas apply to both the

PC Isets. Shad ed areas, like this one, describe the 450 GX operations that diff er from the 450KX.

The Intel 450KX/GX PCIsets provide a high-performance system solution for Pentium Pro processor-based

PCI systems by combining high integration, high performance technology with a scalable architecture that is

capable of high throughput for up to four Pentium Pro processors. Scalability provides a wide range of system

solutions from cost-effective uniprocessor systems to high-end multiprocessor systems without sacrificing

performance. For systems requiring extensive I/O (e.g., file servers), a second PB can be easily added

providing two high-performance PCI bus structures. The flexibility of the memory controller permits easy

expan s ion fr om a s im pl e n on - in ter l ea v ed or ga ni z ation to a 2- way or 4-w a y int er l ea ved orga niza t io n to inc r e as e

performance. Extended error checking and logging, ECC, and the ability to build in redundancy (e.g, multiple

processo rs and du al PCI bridges) provides a comprehensive solution for systems requiring high reliabilit y.

The PC Iset may cont ain design de fects or errors k nown as errata. Curr ent chara cterized errata are available

up on requ est.

4PRELIMINARY

PCIset Overview A

Figure 1. 450KX/GX Simplified Syste m Block Diagram

PCI Bus

Main Memory

MIC

DC DP

Pentium Pro

(1 Gb yte Max)

PCI Bus

(x4)

PCI-to-ISA Bridge

ISA Device

PCI

Device

ISA Bus

Host Bus

PCI

Device

PCI

Device PCI

Device

(4 Gbyte Max)

PCI-to-EISA Bridge

EISA Device

ISA Device

EISA De vice

EISA Bus

Internal

Arbitration

APIC Bus

Note: 450KX: Supports one P B, on e MC, and up to two processors.

450GX: Supports up to two PBs, two MCs, and four processors on the host bus.

Pentium Pro Pentium Pro Pentium Pro

Processor Processor

Processor

Main Memory

MIC

DC DP

(4 Gbyte M ax)

(x4)

PRELIMINARY 5

APCIset Overview

1.0 INTEL 450KX PCISET

The 450 KX de skt o p PC Is et con si st s of th e 82 45 4KX PCI Bri dge ( P B) a nd the Memo r y Con tr o lle r (M C) . Th e MC

consists of the 82453KX DRAM Controller (DC), the 82452KX Data Path (DP), and four 82451KX Memory

Interface Components (MIC). Th e system con figuration using the Intel 450 KX PCIset supports one PB, one MC

an d up to two Pentium Pro processors (Figure 1). An ISA subsystem is also lo cated below the PB. For Pentium

Pro processor bus error detection, the 450KX generates and checks parity over the address and

request/response signal lines. This feature can be enabled/disabled during system configuration.

KX PCI Bridge (PB)

The PB i s a sing le-ch ip h ost-to -PCI Bridg e. A ri ch s et of CPU-to -PCI an d PCI-t o-CP U bu s trans acti on tra nsla -

tio ns opt imiz e bu s ba nd wid th an d impr ov e sy st em per f orma nc e. Al l I SA an d EI SA r eg ions ar e sup por t ed. T hree

programmable memory gaps can be created—a PCI Frame Buffer Region with specialized frame buffer

attributes and two general-purpose memory gaps (called the Memory Gap Region and the High Memory Gap

Region).

The PB takes ad vantage of the Penti um Pro process or ratio c locki ng schem e to assu re modularity now and

upgradability in the future. The PB has a synchronous interface to the Pentium Pro processor bus and supports

a derived clock for the synchronous PCI interface. The PB derives either a 30 or 33 MHz PCI clock output from

the Pentium Pro processor bus clock. The PB PCI signals are 5 volt tolerant and can be used with either 5 volt

or 3.3 volt PCI devices.

KX Memory Controller (MC)

The combined MC (DC, DP, and four MICs) act as one physical load on the Pentium Pro processor bus. The

DC prov ides cont rol f or the D RAM mem ory subs yst em, t he DP p rovi des t he da ta pat h, an d th e four MI Cs ar e

used to interface the MC datapath with the DRAM memory subsystem.

The memory configuration can be either 2-way interleaved or non-interleaved. Both single-sided and double-

sided SIMMs are supported. DRAM technologies up to 64 Mbits at speeds of 50ns, 60ns, and 70ns can be

used. Asymmetric DRAM is supported up to two bits of asymmetry (e.g., 12 row address lines and 10 column

address lines). The maximum memory size is 1 Gbyte for the 2-way interleaved configuration and 512 Mbytes

for the non-interleaved configuration using 16 Mbit technology. In addition to these memory configurations, the

MC provides data integrity features including ECC in the memory array. These features, as well as a set of

error reporting mechanisms, can be selected via configuration of the MC. Each interleave provides a 64-bit

data path to main memory (72-bits including ECC).

The MC is PC compatible. All ISA and EISA regions are decoded and shadowed based on programmable

configurations. Regions above 1 Mbyte with size 1 Mbyte or larger that are not mapped to memory may be

reclaimed by setting the appropriate configuration in the MC. Three programmable memory gaps can be

created and are called the

Low Memory Gap Region

, the

Memory Gap Region

and the

High Memory Gap

Region

6PRELIMINARY

PCIset Overview A

2.0 INTEL 450GX PCISET

3.0 HOST BUS EFFICIENCY

The Pentium Pro processor bus achieves high bus efficiency by providing support for multiple, pipelined trans-

actions. A single Pentium Pro processor may have up to four transactions outstanding at the same time, and

can be conf igured to support up to eight transactio ns active on the Pentium Pro processor bus at any one time.

The PB and MC support a choice of one or eight active transactions on the Pentium Pro processor system bus

at one time (In-Order Queue depth).

The number of transactions tha t can target a particular bus client is conf igured separat ely from the total number

of transactions allowed on the bus. Each PB can accept up to four transactions into its Outbound Request

Queue that target its associated PCI bus. The PB also contains a four deep Inbound Queue that holds PCI

initiated requests directed to the Pentium Pro processor bus. Each MC can accept up to four transactions that

target its associated memory space.

The Intel 450GX PCI s et includes the features di scussed for the Intel 450KX PCIset and provides the additional

capabilities described in this section. This PCIset consists of the 82454GX PCI B ridge (PB) and the Memory

Controller (MC). The MC for the 450GX consists of the 82453GX DRAM Controller (DC), the 82452GX Data

Path (DP), and four 82451GX Memory Interface Controllers (MIC). The 450GX permits two PBs and two MCs in

a system. In addition to parity support on the host bus described for the 450KX, the 450GX generates and

checks ECC over the host data lines. This feature c an be enabl ed/disabled during configuration.

One aspect of the 450GX is that it can be used as a drop-in replacement for an 450KX design. Additional pins

are added in such a way that proper wiring of 450KX test pins (GTLHI, TESTLO, and TESTHI) will allow an

450GX to operate in the same system while functioning exactly as an 450KX.

GX PCI Bridge (PB)

Two 82454GX PBs can be used in a system. Dual PBs provide a modular approach to I/O performance

improvements. Compatibility versus speed are addressed with an optional compatibility operating mode to

guarantee standard bus compa tible operation when needed, and a llow bus concurrency when possibl e.

In a dual PB system, one PB is configured by strapping options at power-up to be the

Compatibility PB

. This PB

provides the PC compatible path to Boot ROM and the ISA/EISA bus. The second PB is configured by the

strapping options to be the

Auxili ary P B

. The Co mpa tib ility PB is t he hi ghes t pri ority brid ge to en su re a prop er

response time for ISA bus masters. When two PBs are on the host bus, the Compatibility PB handles arbitration

with an i ntern al arbiter.

GX Memory Controller (MC)

The memory configuration can be either 4-way interleaved, 2-way interleaved, or non-interleaved. Both single-

sided and doub le-sided SIMMs are supported. DRAM technologies up to 64Mbit at speeds of 50ns, 60ns, and

70ns can be used. Asymmetric DRAM is supported up to two bits of asymmetry ( e.g., 12 row address lines and

10 column address lines). The maximum memory size is 4 Gbytes for the 4-way interleaved configuration, 2

Gbytes for the 2-way interleaved configuration, and 1 Gbyte for the non-interleaved configuration using 64 Mbit

techno logy. The MC provides a 64-bit data pa th to mai n memory (7 2-bit s incl uding ECC) for each interleave

(288 bits for a 4-way interleave design).

PRELIMINARY 7

APCIset Overview

Both the PB and MC provide four 32-byte buffers for outbound data and four 32-byte buffers for inbound data.

Fo r the P B, t he ou tbo und d ata refer s to CP U- to-P CI writ es or PCI rea ds fr om th e CPU b us an d in boun d dat a

refer s to PCI-to -CPU writes or CPU reads f rom PCI. F or t he MC outb ound data refers to CP U writes to m ain

memory and inbound data refer s to CPU reads of main m emory.

The maximum data transf er that is supported by the Pentium Pro processor bus is four 64-bit wide transfers.

This transfer satisfies the 32-byte cache line size of the Pentium Pro processor interface. The Pentium Pro

processo r supports operations that are not c ompleted in the order in which they were requested. This ‘def erred

response’ capability allows the P entium Pro processor bus to be freed to execute other requests while waiting

for the response from a request to a device with relatively long latency. Note that the 450 PCIset does not defer

requests to itself, nor does it (the PB) allow its transactions to be deferred.

4.0 SYS TEM MEMORY MAP

A Pe n tium Pr o p roces s or s y st em can h ave up to 64 Gby tes o f addres sable mem ory. T h e lowe r 1 Mby t e of this

memory address space is divided into regions that can be individually controlled with programmable attributes

such as disab le, read/write, wr ite only, or read only.

At the high es t level, th e ad dr e s s sp ace is di vi ded in t o fo ur c on cept ual r eg io ns as s how n in Fig ure 2. Th es e are

the 0–1 Mbyte Compatibility Area, the 1 Mbyte to 16 Mbyte Extended Memory region used by ISA, the 16

Mbyte to 4 Gbyte Extended Memory region used by EISA, and the 4 Gbyte to 64 Gbyte Extended Memory

introduced by 36 bit addressing. Each of the regions are divided into subregions, as described in the following

sections.

Figure 2. Pentium Pro Processor Memory Address Space.

For the 450GX, up to two MCs can be placed in the address space spanned by these regions. In a PC archi-

tecture, the only restrictio ns on memory plac ement are that there be me mory st ar ting at address 0 and that

there be enough memory to operate a system. The MCs in a system need not have contiguous address

spaces. Each MC also supports two memory ranges for the memory connected to the MC, by providing a high

memory gap range register that defines the space between the two ranges of memory. This range effectively

defines the top address for the lower memory range and the base address for the upper memory range.

Compatibility

Area

Extended

Memory

(ISA)

Extended

Memory

(EISA)

1MB

15MB

4GB - 16MB

100_0000

F_FFFF

FF_FFFF

10_0000

Extended

Memory

(above 4GB) 64GB - 4GB

F_FFFF_FFFF

1_0000_0000

FFFF_FFFF

8PRELIMINARY

PCIset Overview A

4 .1 C om pat ib ility A re a

The first region of memory is called the Compatibility Area because it was defined for early PCs. This region is

divided into 5 subregions, as shown in Figure 3.

Figure 3. Expanded View of Compatibility Area.

DOS Region

T he D OS Regi on is 640 Kbyt es in the a ddres s ra ng e 00 000h –9F FFFh . DOS ap plic atio ns execu te h er e. T his

re gion is furth er di vide d int o tw o par ts. The 51 2 Kby te area at 0 0000 h–7F FFF h is al ways m app ed to m emo r y

on the Pentium Pro processor b us (en abled in the MC), while the 12 8 Kbyte area from 80000h–9FFFFh can be

mapp ed to mem ory on t he Pen tium Pro pr o ce s so r bus or P C I mem o ry (e na ble d in the P B) . Thi s r e gio n can be

programmed as disabled, read/write, wr ite onl y, or read only.

Graphics Adapter Memory

The 128 Kbyte Graphics Adapter Memory region at A0000h–BFFFFh is nor mally mapped to a video device on

the PCI bus. Typically, this is a VGA controller. If ther e are no graphics compatible devices, this region can be

us ed as system memory. The range A000 0h–AFFFFh (64 Kbyt es) is also the default region for SMM spa ce.

The SMM region can be re-mapped by programming the SMM Range Register in the PB and MC.

ISA Expansion

The 128 Kbyte ISA expansion region is divided into eight 16 Kbyte blocks that can be independently

programmed as disabled, read/write, write only, or read only providing the capability to “shadow” these regions

in main memory. Typically, these blocks are mapped through the PB to ISA space.

System BIOS

Extended

System BIOS ISA

Video BIOS

Graphics

Adapter

ISA Window /

Memory

DOS Area

64KB

128KB

640KB

A_0000

C_0000

E_0000

F_0000

F_FFFF

ISA

Expansion/

DOS

Region

Channel I/O

Memory

8_0000

C_8000

Memory

Compatibility

Area

Extended

Memory

(ISA)

Extended

Memory

(EISA)

1MB

FFFF_FFFF

100_0000

F_FFFF

FF_FFFF

10_0000

Extended

Memory

(above 4G B)

F_FFFF_FFFF

1_0000_0000

PRELIMINARY 9

APCIset Overview

Hi storic al ly, th e 32 K by te reg ion from C 0 00 0h –C 7 FF F h has c o ntain ed the v i deo BIO S lo c ate d on a vide o c ard

in the ISA Expansion Area. However, in the high integration por table and desktop market video BIOS is more

likely to b e locat ed in the Extended System BIOS or Sy stem BIOS re gions t hat start at E0000h.

The 96 K byte area from C8000h–DFFFFh has usually been made available to expand memory win dows in

16 Kbyte blocks, depending on the requirements of other channel devices in the corresponding ISA space.

More recently, PCMCIA devices for the portable market have been assigned within th is region.

This region coul d also be u s ed as Sy stem Mana gement M ode (SMM) mem ory.

Extended System BIOS

This 64 Kbyte region from E0000h–EFFFFh is divided into four 16 Kbyte blocks and may be mapped either to

the memory co ntroller or the PCI bridge. This region c an be programm ed as disabled, rea d/writ e, write only, or

read only, provi ding the capability to shadow th ese re gions in main me mory. Typically, this area is used for RAM

or ROM.

System BI OS

The 64 Kbyte region from F0000h–FFFFFh is treated as a single block. After power-on reset, the PB (Compat-

ibility PB in an 450GX dual PB system) has this area R/W enabled to respond to fetches during system init ial-

ization. The MC(s) and Auxiliary PBs (450GX PCIset) have this area R/W disabled. This region can be

p rogra mme d as di sable d, re ad/w r ite, wr it e only, o r rea d only, p rovidi ng t he ca pabi lit y to sh ad ow the se reg ion s

in main me m ory.

4.2 Extended Memo ry (ISA)

The ISA Extended Memory region in Figur e 4 covers 15 Mbytes ranging from 100000h–FFFFFFh. There are

three programmable ranges that may be mapped to the ISA Extended Memory region of the MC—the Low

Memory Gap range, the Memory Gap Range, and the High memory Gap Range. Memory in these ranges, that

would normally be “l ost”, is recovered by the MC by extending the effectiv e top of system memory, if reclaiming

is e na bled. The M emo r y G ap R ang e an d H igh M emo r y Ga p ra nge a re also pr ogramm able rang es i n the PB.

The PB also has a programmable PCI Frame Buffer Range.

Low Memory Gap Range (MC Only)

The Low Memory Gap range can start on any 1 Mbyte boundary in the ISA or EISA Extended Memory region,

and can be 1, 2, 4, 8, 16, or 32 Mbytes. This region defines a “hole” in system DRAM space where accesses

can be directed to the PCI bus. The Low Memory Gap Ra nge is us ed by ISA d evices su ch as LA N or linear

frame buffers which are mapped into the ISA Extended region, o r by any EISA or PCI device. The Low Memory

Gap Range must reside at the lowest address of the three memory gaps, if it is enabled.

PCI Frame Buffer Range (PB Only)

The PCI Frame Buffer range can start on any 1 Mbyte boundary in either the ISA Extended Memory region or

the EISA Extended Memory Region, and can be 1, 2, 4, 8, 16,or 32 Mbytes.

10 PRELIMINARY

PCIset Overview A

Memory Gap Ra nge (MC and PB)

The Memory Gap Range can start on any 1 Mbyte boundary, above 1 Mbyte, and can 1, 2, 4, 8, 16, or 32

Mbytes. This region defines a “hole” in system DRAM space where accesses can be directed to the PCI bus.

T he M emo ry Gap Ra nge is u sed by IS A devic es su ch a s LA N or li near fram e buffer s wh ich are map ped int o

the ISA Extended region, or by any EISA or PCI device. The Memor y Gap Range must reside above the Low

Memo ry Ga p Ra ng e an d below the Hig h Me m ory Ga p R an ge, if it is enabl ed .

High Memory Gap Range (MC and PB)

The High Memory Space Gap can star t on any 1 Mbyte boundary in either the ISA Extended Memor y region,

EISA Extended Memory Region, or the Extended Memory Region above 4Gbyte, and can extend up to 64

Gigabytes. It is defined by specifying a start and end address, both on 1 Mbyte boundaries. The High Memory

Gap Range is provided as additional support for memory mapped I/O. The High Memory Gap Range must

reside at the highest address of the three mem ory gap range registers, if it is enabled.

Figure 4. Expanded View of Extended Memory (ISA)

4.3 Extended Memory (EISA)

The EISA Extended Memory region covers the 16 Mbyte to 4 Gbyte range (1000000h–FFFFFFFFh). This

region is divided into three sections—System BIOS, APIC configuration space, and system memory. The APIC

configuration space is contained within the system memory region (Figure 5). The Low Memory Gap, Memor y

Gap, and High Memory Gap ranges can also be enabled in this region.

15MB

System Memory

(Memory or PCI)

10_0000

FF_FFFF

Compatibility

Area

Extended

Memory

(ISA)

Extended

Memory

(EISA)

FFFF_FFFF

100_0000

F_FFFF

FF_FFFF

10_0000

Extended

Memory

(a bove 4G B)

F_FFFF_FFFF

PB Only

MC Onl y

Not e: If th e PCI Fr ame B uffer Ra nge is e nabled in the PB (a cc esses forwar ded to PCI ), t he Low M emo r y

Gap in the MC can be used to create a gap in main memory for the corresponding memory address

range (MC ignores these accesses).

Hig h Memory

Ga p R a n g e

Memory

Gap Range

PCI Frame

Buffer Range

Low Memory

Ga p R a n g e

PRELIMINARY 11

APCIset Overview

Figure 5. Expanded View of Extended Memory (EISA).

System BI OS

Th e top 2 Mby tes o f th e EI SA Ex tend ed M emory re gi on is use d fo r Sys tem BIO S (Hig h B IOS) . Thi s is w her e

th e Pe ntiu m Pro pro ces sor be gins exe cuti on a fte r res et. I f the PC I bus is br idge d to an ISA bus, this reg ion is

aliased to the top 128 Kbyte of the ISA Extended Memory range.

The actual address space required for system BIOS is less than 2 Mbytes. Howev er, the minimum Pentium Pro

processor MTTR range for this region is 2 Mbytes. This establishes the minimum size for this gap. The MC

supports ena bling or disablin g this region for access to the MC memory via the HBIOSR Register.

I/O APIC Configuration Space

The FEC00000h (4GB minus 20 MB) to FEC0FFFFh range is reserved for APIC configuration space which

includes the default I/O APIC configuration space. Note that there is no I/O APIC unit in either the MC or PB.

The default Local APIC configuration space is FEE00000h–FEE00FFFh.

Pentium Pro processor accesses to the Local APIC configuration space do not result in external bus activity

since the Local APIC configuration spa ce is interna l to the Pentium Pro processor. However, an MTRR must be

programmed to make the Local APIC range uncacheable (UC). The L ocal APIC base ad dress in each Pent ium

Pro processor s hould be relo cated to the FEC000 00h (4GB minus 20 MB) to FEC0F FFFh range so that one

MTRR can be programmed to 64 Kbyte for the Local and I/O APICs.

System BIOS

I/O APIC

128KB

100_0000

FEC0_0000

FECO_FFFF

FFFE_0000

FFFF_FFFF

System Memory

(Memory/PCI)

Configuration

Space

Compatibility

Area

Extended

Memory

(ISA)

Extended

Memory

(EISA)

FFFF_FFFF

100_0000

F_FFFF

FF_FFFF

10_0000

Extended

Memory

(above 4GB)

F_FFFF_FFFF

System Memory

(Memory/PCI)

64KB

PB Only

MC Only

Note: If the PCI Frame Buffer Range is enabled in the PB (accesses forwarded to PCI), the Low Memory

Gap in the MC can be used to create a gap in main memory for the corresponding memory

addr e s s ra ng e (MC ig no r es the se acc es s es ) .

Hig h Memory

Gap Range

Memory

Gap Range

PCI Frame

Gap Range

Low Memory

Gap Range

12 PRELIMINARY

PCIset Overview A

I/O APIC units (there should be at least one for each I/O subsystem) are located beginning at the default base

address FEC00000h. The first I/O APIC (unit #0) is at FEC00000h. Each I/O APIC unit is located at

FEC0x000h where x is I/O APIC unit 0 through F.

The address range between the APIC Conf iguration space and the High BIOS (FED00000h–FFDFFFFFh) is

alw a ys mapp ed to lo ca l memory unl e ss th e ra ng e is ab o v e top of ph ys ica l memory or Th e H igh BI OS and API C

Range are disabled in the PB and the range falls within a memory gap range. The MC supports enabling or

disabling this re gion for acces s to the MC memory via the I/O APIC Range Register.

4.4 Exten de d Memory (above 4 Gbytes)

The Extended Memor y region is from 4 Gbyte to 64 Gbyte (100000000h–FFFFFFFFF h). The PB and MC can

be mapped into this range. The Memor y Gap Range and High Memor y Gap Range are both available for use

within the Extended memory region (above 4 Gbyte).

4.5 Sy stem Manageme nt Mode (SMM)

A Pentium Pro processor asserts SMMEM# in its Request Phase if it is operating in System Management

Mode. SM code resides in SM memory space. SM memory can overlap with memor y residing on the Pentium

Pro processor bus or memory normally residing on the PCI bus. The MC and PB determine where SM memory

space is located through the value programmed in their respective SMM Range Registers.

5.0 I/O SPACE (PB ONLY)

The PB optionally supports ISA expansion aliasing (Figure 6). When ISA expansion aliasing is enabled, the

ranges designated as I/O Expansion are internally aliased to the 100–3FFh range before the I/O Space Range

registers are checked. Note that all devices on the Pentium Pro pr ocessor bus that are mapped into I/ O space

must have I/O aliasing consistently en abled /disabled.

For t he Inte l 45 0G X PC I se t , the P B al low s I/O a ddress es t o be m app ed t o the Pen tiu m Pro pr o ce s so r bu s or

through designated bridges in a multi bridge system. Two I/O Space Range registers allow the PB to decode

two I/O address ranges. If the addr ess ra nge is enabled, trans actions targ eting that range are forwarded to the

PCI bus. If the address range is disabled, the tr ansaction is ignored.

PRELIMINARY 13

APCIset Overview

6.0 MEMORY MAPPED I/O

Th e PB allows mem or y addre sse s t o be m app ed to the hos t bus, or for t he 45 0GX P CIs et, thr ough the o the r

bridge in a dual PB system. Memory mapped I/O devices can be located anywhere in the 64 Gbyte address

space. The Frame Buffer Range allows the PB to decode memory mapped I/O space exte nding up to 4 Gbyte.

The Memory Space Gap and High Memory Gap registers allow the PB to decode two address ranges

extending up to 64 Gbytes.

Figure 6. View of I/O Space

0000

FFFF

0000

FFFF

I/O

Space Gap 2

Remaining

I/O Space

3FF

400

ISA Alias Mode

Disabled ISA Alias Mode

Enabled

100

ISA Expansion

I/O Space

7FF

800

500 I/O Spac e

BFF

C00

900

ISA Expansion

I/O Space

(aliased to 100-3FF)

ISA Expans ion

(aliase d to 100-3FF)

and Aliases

Note: The Compatibility PB defaults to claiming all I/O transactions. If a range is enabled in the Auxiliar y

PB, the same range must be disabled in the Compatibility PB.

I/O

Space Gap 1

I/O

Sp ac e Ga p 2

I/O

Sp ac e G ap 1

14 PRELIMINARY

PCIset Overview A

PRELIMINARY 15

A82454KX/GX (PB)

Chapter 2

82454KX/GX PCI Bridg e (PB)

16 PRELIMINARY

82454KX/GX (PB) A

A82454KX/GX (PB)

PRELIMINARY 17

82454KX/GX PCI Bridge (PB)

■Supports the P entium Pr o Processo r at

60 MH z and 66 MHz Bus Speeds

■PCI Specification 2.0 Compliant

■64-Bit Data Bus and 36-Bi t Address Bus

■P arity Protection on Control Signals

■Up to Eight Deep In-Order Queue

■Four Deep Outbound Request Queue

■Dual-Processor Suppor t (450KX)

■Four Cache Line Size Read and Write

Buffers

■GTL+ Host Bus Interface

■Synchronous PCI Interface

— ECC Protection on Data Bus

(450GX)

— Quad-processor Support (450GX)

■32-bit Addre ss/Data PCI Bus (64-bit Dual

Cycle Address Support)

■Parity Protecti on on All PCI Bus Signals

■Four Deep Inbound Request Queue

■Data Collection/W rite Assembly of Line

Bursts.

■Single Chip: Combine d Contr oller and

Data Path in a 304-Pin QFP or 352 BGA

■Support for 3.3V and 5V PCI De vices

■On-Chip Digital PLL (DPLL)

■Component and In-Sys tem Connectivity

Test Support (JTAG)

— Interna l Bridge Arbiter For T wo PBs

in a system (450GX)

The 8245 4KX/G X PB are si ngle-ch ip PC-c ompa tible host-to -PCI b ri dges. A ric h set of Host-to -PCI and PCI-to -

Host bus transaction translations optimize bus bandwidth and improve system performance. All ISA and EISA

regions are suppor ted. Three programmable memory gaps can be created—a PCI Frame Buffer Region and

two general-purpose memory gaps (the Memory Gap Region and the High Memory Gap Region). The PB has

a synchronous interface to the Pentium Pro processor bus and supports a derived clock for the synchronous

P C I i nter face. T h e P B gene ra te s an d check s E CC ove r th e ho st data bus (8254 5G X on ly ) , a nd g ener a tes an d

checks parity over the address and request/response signal lines (both 82454KX and 82454GX). The PB also

checks address and data parity on t he PCI bus . F or th e 82454GX, two P Bs can be used in a syst em.

The Intel 450KX/GX PCIsets may contain design defects or errors known as errata. Current characterized

errata ar e available upon r equest.

This document describes both the 82454KX and 82454GX PBs. Unshaded areas descr ibe features common to

th e 824 54KX and 82 454G X . S hade d are as, like t his on e, desc r ibe the 8245 4GX opera tio ns tha t dif fe r fr om the

82454KX.

18 PRELIMINARY

82454KX/GX (PB) A

Figure 1. 82454KX/GX Simplified Block Diagram

Gray Areas indicate GX Only pins

Host

Bus

Interface

PCI

Interface

BPRI#

ADS#

LOCK#

A[35:3]#

REQ[4:0]#

RP#

AP[1:0]#

AERR#

BNR#

HIT#

HITM#

DEFER#

RS[2:0]#

RSP#

TRDY#

DRDY#

DBSY#

D[63:0]#

DEP[7:0]#

FLUSH#

BERR#

BINIT#

SMIACT#

AD[31:0]

C/BE[3:0]#

PTRDY#

STOP#

PLOCK#

DEVSEL#

PAR

IRDY#

FRAME#

PERR#

SERR#

PREQ#

PGNT#

MEMREQ#

FLSHBF#

MEMACK#

Clock,

Reset

and

Support

Bridge

Sideband

IOREQ#

IOGNT#

GTLREFV

BCLK

RESET#

CRESET#

INIT#

PCLKIN

PCLK

PWRGD

PCIRST#

Test TCK

TDI

TDO

TMS

TRST#

TESTLOW

RECVEN

PRELIMINARY 19

A82454KX/GX (PB)

1.0 PB SIGNAL DESCRIPTIONS

This section contains a detailed description of each signal. The signals are arranged in functional groups

according to their interface.

Note that the ‘#’ symbol at the end of a signal name i ndicat es that the active, or asserted state occur s when the

signal is at a low v oltag e level. When ‘#’ is not present at the end of a signal name, the signal is asserted when

at the high voltage level.

The terms assertion an d negation are used exte nsively. This is done to avoid confusio n when working with a

mixture of ‘active-low’ and ‘active-high’ signals. The term assert, or assertion indicates that a signal is active,

independent of whether that level is represented by a high or low voltage. The term negate, or negation

indicates that a signal is inactive.

The following notations are used to describe the signal type.

Input

is a standa rd input-only signal.

Totem

Pol e Output is a standar d active driver.

I/O

Input/Output

is bi-directional, tri-state signal.

GTL+

Processor bus signal defined for 1.5V operation.

CMOS Rail-to-Rail

CMOS

Tolerant to 5V levels.

PCI CMOS sign al specifically meeting PCI Specific ation 2.0.

Analog Referenc e Vol t a ge.

1.1 PB Signals Table 1. Host Bus Interface Signals

Signal Type Description

A[35:3]# I/O,

GTL+ AD DRESS BUS. A[3 5:3]# contai ns the transaction address on the clock cycle with

AD S# asse rted. Byte enables , deferred ID, and additional transaction information

are encoded on these lines du ring the cycle following AD S#. Note th at the PB nev er

as serts Defer E nable when it is a bus mast er.

ADS# I/O,

GTL+ AD DRESS STROBE. ADS# is asserted during the first cycle of the Request Phase

to indicate v alid address and command signals.

AERR# I/O,

GTL+ AD DRESS ERROR . AERR# is asserted by any agent that detects an address parity

error, If enable d in the EXERRCMD Register.

AP[1:0]# I/O,

GTL+ AD DRESS PARITY. AP1# cov ers A[35:24]# and AP0# covers A[23:3]#. AP[1:0]# is

va li d on bo t h cy c le s of the re qu es t.

BERR# I/O,

GTL+ BUS ERROR. BERR# is asserted by any agent that observes an unrecoverable bus

protocol violation, if enabled in the EXERRCMD Register.

BINIT# I/O,

GTL+ BUS INITIALIZATION. BINIT# is asserted to re-initialize the bus. The PB

terminates an y ongoing PC I transaction at this time and resets its inbound a nd

outbound queues. No configuration registers or error logging registers are affected.

BNR# I/O,

GTL+ BLOCK NEXT REQUEST. BNR# is asserted by an agent to prevent the request

bus owner from issuing further requests.

BPRI# I/O,

GTL+ PRIORITY AGENT BUS REQUEST. BPR I# is issued by the high priority bus agent

to acquire the request bus. The high priority agent is always the next bus owner.

20 PRELIMINARY

82454KX/GX (PB) A

D[63:0]# I/O,

GTL+ DATA BUS. The data bus consists of eight bytes. All bytes are valid for line

transfers. The valid bytes are determined by th e byte enab les that are asserted in

the second cycle of the request phase.

DBSY# I/O,

GTL+ DATA BUSY. DBSY # is asserted by the data bus o wne r to hold the data bus for the

next cycle. DBSY# is not asserted for single cycle transfers.

DEFER# I/O,

GTL+ DEFER. DEFER# is driven by the addressed agent to indicate that the tran saction

cannot be guaranteed b us completion.

DEP[7:0]# I/O,

GTL+ DATA ECC. On the host bus, DEP[7:0]# are used for ECC on the D[63:0]# signals.

DRDY# I/O,

GTL+ DATA READY. DRDY# is driven by the data bus owner for each cycle that contains

valid data. DRDY# is negated to indicate idle cycles during the data phase.

FLUSH# O,

CMOS FLUSH. The PB asserts FLUSH# to caus e the pro c essor to stop ca ching new lines ,

writeback all cache lines in th e Modif ied state, and disable further caching until

FLUSH # is negated.

In an 8245 4GX dual PB system this signal is only available on the Compatibility PB

and is not a v ailable on the Auxiliary PB.

HIT# I/O,

GTL+ HIT. The PB asserts HIT# and HITM# together to extend the snoop window of a

transaction targeting its PCI bus. Si nce the P B is not a caching agent, it never

asserts HIT# alone.

HITM# I/O,

GTL+ HIT MODIFIED. The PB asserts HIT# and HITM# together to extend the snoop

window of a transaction targeting its PCI bus. Since the PB is not a caching agent, it

nev er asserts HITM# alone.

LOCK# I/O,

GTL+ LOCK. The LO CK# signal is asserted for an indivi sible sequence of transactio ns.

REQ[4:0]# I/O,

GTL+ REQUEST TYPE. REQ[4:0]# contain the command on the clock with ADS#

asserted and data size/length information on the next clock.

RP# I/O,

GTL+ REQUEST PARITY. RP # is even parity that co ver s REQ[4:0]# and ADS #. RP# is

valid on both cycles of the request.

RS[2:0]# I/O,

GTL+ RESPONSE. RS[2:0]# enco de the response to a request.

RSP# I/O,

GTL+ RESPONSE PARITY. RSP# provid es respons e parity for RS[2:0]#.

SMIACT# O,

CMOS SMI ACKNOWLEDGE. SMIACT# is asserted when the PB det ects a ho st SMI

Acknowledge special transaction (regardless of its initiator) with SMMEM# asserted.

Once asserted, SMIACT # remains asserted until the PB detects a

ho st SMI

Acknowledge special transaction with SMMEM# negated.

In an 8245 4GX dual PB system this signal is only available on the Compatibility PB

and is not a v ailable on the Auxiliary PB.

TRDY# I/O,

GTL+ TARGET READY. TRDY# is driven by the target of the data to indicate it is ready to

rec e ive da t a.

Table 1. Host Bus Interface Signals (Continued)

Signal Type Description

PRELIMINARY 21

A82454KX/GX (PB)

Table 2. PCI Interface Signals

Signal Type Description

AD[31:0] I/O,

PCI PCI ADDRESS/DATA. Addresses and data are multiplexed on this bus. Th e

physical byte address is ou tput du ring the address phase and the data follows in

the subsequent data phase(s).

C/BE[3:0]# I/O,

PCI BUS COMMAND AND BYTE ENABLES. C/BE[3:0]# cont ains commands during

the addre ss phase and b y te enables during the data phase.

DEVSEL# I/O,

PCI DEVICE SELECT. DEVSEL# is driven by the de vice that has decoded its address

as the target of the current access.

FLSHBF# I,

CMOS FLUSH BUFFERS. This sideband signal is typically generated by a standard PCI

bus bridge (e.g., ISA or EISA bridge) to command the PB to flush all write post

buffers po inted toward the PCI bus and disable further posting. Once all b uffers are

flushed, the PB asserts MEMACK# until FLSHBF# is negated.

FLSHBF# MEMREQ# Function

0 0 No Action.

01 Reserved.

1 0 APIC Flus h. Flush bu ffers pointing tow ard PCI.

1 1 Guaranteed Access Time (GAT) mode. Guarantee PCI

bus immediate acce ss to the CPU bus. Flush al l buffers,

request queues, empty in-order queue, a nd retain host

bus owne r s hip.

FRAME# I/O,

PCI PCI FRAM E. FRAME# is d rive n by a master to indicate the be ginning and end of a

transaction.

IRDY# I/O,

PCI PCI INITIATOR READY. IRDY# is asserted by the master to indicate that it is able

to complete the current data transfer.

MEMACK# O,

CMOS MEMORY ACKNOWL EDGE. MEMACK# is generated in response to FLSHBF# or

MEMREQ# generated by a standard bus br idge.

MEMREQ# I,

CMOS ME MORY REQUEST. This sideband signal is typically generated by a standard

bridge (e.g., ISA or EISA bridge) to guarantee access latency from standard bus

mas ters to main m emory (s ee FLSHBF# descript ion). O nce all buffers h ave been

flushed, the PB asserts MEMACK# continuous ly until MEMREQ# is negated.

PAR I/O,

PCI PCI PARITY. PAR i s driven to ev en parity across AD[31:0] a nd C/BE [3:0]# by the

master during address and write data phases. The target drives PAR during read

d at a ph as es.

PERR# I/O,

PCI PCI PARITY ERROR. PERR# is pulsed by an agent receiving data with bad parity

one clock after PAR is asser ted.

PGNT# I,

CMOS PCI GRANT. PG NT# indicates to the PB that it has been granted the PCI bus.

PLOCK# I/O,

PCI PCI LOCK. PLoc k# is asserted by an a gent requiring excl usive acce ss to a target.