To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclose d by Renesa s Electronics such as that disclosed through our website.
2. Renesas Electronics does not assum e any liability for inf ringement of patents, co pyrights, or other int ellectual property rights
of third parties by or arising from the use of Renesas Elec tronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, m odify, copy, or otherw ise misappropriate an y Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losse s incurred by
you or third parties arising from the use of these circuits, software, or information.
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does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
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“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appli ances; mac hine tools; personal electronic equipm ent; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the m aximum rating , opera ting supply voltag e range, movement power voltage ra nge, heat radiation
characteristics, installation and other product characteristic s. Re nesas Electronics shall have no liabil ity for malfunctions or
damages arising out of the use of Re nesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliabili ty of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation res istance design. Pleas e be sure to implement saf ety measures to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
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Directive. Renesas Electronics assum es no liability for damage s or losses occurring as a result of your noncom pliance with
applicable laws and regulatio ns.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions re garding the information conta ined in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Re nesas Electronics produc t(s)” means any product develope d or manufactured by or for Re nesas Electronics.
H8/3039 Group,
H8/3039F-ZTAT™
Hardware Manual
16
User’s Manual
Rev.3.00 2007.03
Renesas 16-Bit Single-Chip Microcomputer
H8 Family / H8/300H Series
H8/3039 HD64F3039F
HD64F3039TE
HD64F3039VF
HD64F3039VTE
HD6433039F
HD6433039TE
HD6433039VF
HD6433039VTE
H8/3038 HD6433038F
HD6433038TE
HD6433038VF
HD6433038VTE
H8/3037 HD6433037F
HD6433037TE
HD6433037VF
HD6433037VTE
H8/3036 HD6433036F
HD6433036TE
HD6433036VF
HD6433036VTE
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
Rev.3.00 Mar. 26, 2007 Page ii of xxii
REJ09B0353-0300
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Notes regarding these materials
Rev.3.00 Mar. 26, 2007 Page iii of xxii
REJ09B0353-0300
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in
the manual.
The input pins of CMOS products are generally in the high-impedance state. In
operation with an unused pin in the open-circuit state, extra electromagnetic noise is
induced in the vicinity of LSI, an associated shoot-through current flows internally, and
malfunctions may occur due to the false recognition of the pin state as an input signal.
Unused pins should be handled as described under Handling of Unused Pins in the
manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the
states of pins are not guaranteed from the moment when power is supplied until the
reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on
reset function are not guaranteed from the moment when power is supplied until the
power reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has
become stable. When switching the clock signal during program execution, wait until the
target clock signal has stabilized.
When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization
of the clock signal. Moreover, when switching to a clock signal produced with an
external resonator (or by an external oscillator) while program execution is in progress,
wait until the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different type number,
confirm that the change will not lead to problems.
The characteristics of MPU/MCU in the same group but having different type numbers
may differ because of the differences in internal memory capacity and layout pattern.
When changing to products of different type numbers, implement a system-evaluation
test for each of the products.
Rev.3.00 Mar. 26, 2007 Page iv of xxii
REJ09B0353-0300
Rev.3.00 Mar. 26, 2007 Page v of xxii
REJ09B0353-0300
Preface
The H8/3039 Group comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern contro ller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3039 Group to adapt quickly and flexibly to a variety of conditions.
In addition to its mask-ROM versions, the H8/3039 Group has an F-ZTAT™ version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manua l describes the H8/3039 Group hardware. For details o f the instruction set, r efer to the
H8/300H Series Software Manual.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Rev.3.00 Mar. 26, 2007 Page vi of xxii
REJ09B0353-0300
Rev.3.00 Mar. 26, 2007 Page vii of xxii
REJ09B0353-0300
Main Revisions for This Edition
Item Page Revision (See Manual for Details)
All — • Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8/3039 Series → (After) H8/3039 Group
2.3 Address Space
Figure 2.2 Memory
Map
20 Figure amended
1. Normal mode (64-Kbyte mode)
H'0000
H'FFFF
5.2.2 Interrupt Priority
Registers A and B
(IPRA, IPRB)
Interrupt Priority
Register B (IPRB)
91 Description amended
Bit
Initial value
Read/Write
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
—
0
R/W
4
—
0
R/W
3
IPRB3
0
R/W
0
—
0
R/W
2
IPRB2
0
R/W
1
IPRB1
0
R/W
5.2.3 IRQ Status
Register (ISR) 93 Description amended
Bits 5, 4, 1 and 0—IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F,
IRQ4F, IRQ1F, and IRQ0F): These bits indicate the status of
IRQ5, IRQ4, IRQ1, and IRQ0 interrupt requests.
5.2.4 IRQ Enable
Register (IER) 94 Description amended
Bit
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
Reserved bits
Bits 5, 4, 1, and 0—IRQ5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E,
IRQ4E, IRQ1E, IRQ0E): These bits enable or disable IRQ5 ,
IRQ4 , IRQ1 , IRQ0 interru pts.
Rev.3.00 Mar. 26, 2007 Page viii of xxii
REJ09B0353-0300
Item Page Revision (See Manual for Details)
5.3.3 Interrupt Vector
Table
Table 5.3 Interrupt
Sources, Vector
Addresses, and Priority
98 Table amended
WOVI (interval timer)
5.5.4 Usage Notes
Figure 5.9 IRQnF Flag
when Interrupt
Exception Handling is
not Executed
109 Figure amended
1 read 0 written
1 read 0
written
Generation condition (2)
(Inadvertent clearing)
6.4.2 Precautions on
Setting ASTCR and
ABWCR*
131 Description amended
Modes 5 and 7
ASTCR0 = 0
ABWCR = H'FC
11.2.8 Bit Rate
Register (BRR) 349 Description added
The baud rate generator is con trol led sep arate ly for the
individual channels, so different values may be set for each.
Table 11.3 Examples
of Bit Rates and BRR
Settings in
Asynchronous Mode
351 Table amended
φ
φφ
φ (MHz)
12
Bit Rate
(bits/s) n N Error
(%)
300 277 0.16
11.3.4 Synchronous
Operation
Clock
376 Description amended
An internal clock generated by the on-chip baud rate generator
or an external clock input from the SCK pin can be selected by
clearing or setting the CKE1 and CKE0 bits in SCR and the C/
A
bit in SMR. See table 11.9.
Rev.3.00 Mar. 26, 2007 Page ix of xxii
REJ09B0353-0300
Item Page Revision (See Manual for Details)
16.2.1 Connecting a
Crystal Resonator
Table 16.2 Crystal
Resonator Parameters
500 Preliminary deleted
18.1.3 AC
Characteristics
Table 18.5 Control
Signal Timing
532 Table amended
Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Unit Test Conditions
RES setup time t
RESS
200 —200 —200 —ns Figure 18.10
RES pulse width t
RESW
10 —10 —10 —tcyc
Mode programming
setup time (MD
0
, MD
1
,
MD
2
)
t200 —200 —200 —ns
MDS
18.1.4 A/D Conversion
Characteristics 535 Newly added
18.2.2 DC
Characteristics
Table 18.10
Permissible Output
Currents
541 Table amended
Item
Permissible output
low current (total) Total of 27 pins
including ports 1, 2, 5
and B
A.1 Instruction List
8. Block transfer
instructions
576 Table amended
Mnemonic Operation
EEPMOV. W —if R4 ≠0 then
repeat @R5 →@R6
R5+1 →R5
R6+1 →R6
R4−1 →R4
until R4=0
else next
Operand Size
A.3 Number of States
Required for Execution
Table A.4 Number of
Cycles per Instruction
584 Table amended
Instruction Mnemonic
Word Data
Access
M
Internal
Operation
N
BSR BSR d:16 Normal 2
Advanced 2
Rev.3.00 Mar. 26, 2007 Page x of xxii
REJ09B0353-0300
All trademarks and registered trademarks are the property of their respective owners.
Rev.3.00 Mar. 26, 2007 Page xi of xxii
REJ09B0353-0300
Contents
Section 1 Overview............................................................................................................. 1
1.1 Overview........................................................................................................................... 1
1.2 Block Diagram.................................................................................................................. 6
1.3 Pin Description.................................................................................................................. 7
1.3.1 Pin Arrangement.................................................................................................. 7
1.3.2 Pin Functions ....................................................................................................... 8
1.4 Pin Functions ............................................................................................................... ..... 12
Section 2 CPU ...................................................................................................................... 17
2.1 Overview........................................................................................................................... 17
2.1.1 Features................................................................................................................ 17
2.1.2 Differences from H8/300 CPU............................................................................. 18
2.2 CPU Operating Modes...................................................................................................... 19
2.3 Address Space................................................................................................................... 20
2.4 Register Configuration...................................................................................................... 21
2.4.1 Overview.............................................................................................................. 21
2.4.2 General Registers................................................................................................. 22
2.4.3 Control Registers ................................................................................................. 23
2.4.4 Initial CPU Register Values................................................................................. 24
2.5 Data Formats..................................................................................................................... 25
2.5.1 General Register Data Formats............................................................................ 25
2.5.2 Memory Data Formats......................................................................................... 27
2.6 Instruction Set................................................................................................................... 28
2.6.1 Instruction Set Overview ..................................................................................... 28
2.6.2 Instructions and Addressing Modes..................................................................... 29
2.6.3 Tables of Instructions Classified by Function...................................................... 31
2.6.4 Basic Instruction Formats.................................................................................... 40
2.6.5 Notes on Use of Bit Manipulation In structions.................................................... 41
2.7 Addressing Modes and Effective Address Calculation..................................................... 41
2.7.1 Addressing Modes ............................................................................................... 41
2.7.2 Effective Address Calculation ............................................................................. 45
2.8 Processing States............................................................................................................... 49
2.8.1 Overview.............................................................................................................. 49
2.8.2 Program Execution State...................................................................................... 49
2.8.3 Exception-Handling State.................................................................................... 50
2.8.4 Exception-Handling Sequences ........................................................................... 51
2.8.5 Reset State............................................................................................................ 53
Rev.3.00 Mar. 26, 2007 Page xii of xxii
REJ09B0353-0300
2.8.6 Power-Down State............................................................................................... 53
2.9 Basic Operational Timing................................................................................................. 54
2.9.1 Overview.............................................................................................................. 54
2.9.2 On-Chip Memory Access Timing........................................................................ 54
2.9.3 On-Chip Supporting Module Access Timing ...................................................... 55
2.9.4 Access to External Address Space....................................................................... 56
Section 3 MCU Operating Modes .................................................................................. 57
3.1 Overview........................................................................................................................... 57
3.1.1 Operating Mode Selection ................................................................................... 57
3.1.2 Register Configuration......................................................................................... 58
3.2 Mode Control Register (MDCR) ...................................................................................... 59
3.3 System Control Register (SYSCR)................................................................................... 60
3.4 Operating Mode Descriptions........................................................................................... 62
3.4.1 Mode 1................................................................................................................. 62
3.4.2 Mode 3................................................................................................................. 62
3.4.3 Mode 5................................................................................................................. 62
3.4.4 Mode 6................................................................................................................. 62
3.4.5 Mode 7................................................................................................................. 62
3.5 Pin Functions in Each Operating Mode ............................................................................ 63
3.6 Memory Map in Each Operating Mode ............................................................................ 63
3.7 Restrictions on Use of Mode 6.......................................................................................... 72
Section 4 Exception Handling ......................................................................................... 75
4.1 Overview........................................................................................................................... 75
4.1.1 Exception Handling Types and Priority............................................................... 75
4.1.2 Exception Handling Operation ............................................................................ 75
4.1.3 Exception Vector Table....................................................................................... 76
4.2 Reset.................................................................................................................................. 78
4.2.1 Overview.............................................................................................................. 78
4.2.2 Reset Sequence.................................................................................................... 78
4.2.3 Interrupts after Reset............................................................................................ 80
4.3 Interrupts........................................................................................................................... 80
4.4 Trap Instruction................................................................................................................. 81
4.5 Stack Status after Exception Handling.............................................................................. 81
4.6 Notes on Stack Usage ....................................................................................................... 82
Section 5 Interrupt Controller.......................................................................................... 83
5.1 Overview........................................................................................................................... 83
5.1.1 Features................................................................................................................ 83
5.1.2 Block Diagram..................................................................................................... 84
Rev.3.00 Mar. 26, 2007 Page xiii of xxii
REJ09B0353-0300
5.1.3 Pin Configuration................................................................................................. 85
5.1.4 Register Configuration......................................................................................... 85
5.2 Register Descriptions....................................................................................................... .86
5.2.1 System Control Register (SYSCR)...................................................................... 86
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 88
5.2.3 IRQ Status Register (ISR).................................................................................... 93
5.2.4 IRQ Enable Register (IER).................................................................................. 94
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 95
5.3 Interrupt Sources............................................................................................................... 96
5.3.1 External Interrupts ............................................................................................... 96
5.3.2 Internal Interrupts................................................................................................. 97
5.3.3 Interrupt Vector Table.......................................................................................... 97
5.4 Interrupt Operation............................................................................................................ 100
5.4.1 Interrupt Handling Process................................................................................... 100
5.4.2 Interrupt Sequence............................................................................................... 105
5.4.3 Interrupt Response Time...................................................................................... 106
5.5 Usage Notes...................................................................................................................... 107
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 107
5.5.2 Instructions that Inhibit Interr upts........................................................................ 108
5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 108
5.5.4 Usage Notes......................................................................................................... 108
Section 6 Bus Controller.................................................................................................... 111
6.1 Overview........................................................................................................................... 111
6.1.1 Features................................................................................................................ 111
6.1.2 Block Diagram..................................................................................................... 112
6.1.3 Input/Output Pins................................................................................................. 113
6.1.4 Register Configuration......................................................................................... 113
6.2 Register Descriptions....................................................................................................... . 114
6.2.1 Access State Control Register (ASTCR) ............................................................. 114
6.2.2 Wait Control Register (WCR).............................................................................. 115
6.2.3 Wait State Controller Enable Register (WCER).................................................. 116
6.2.4 Address Control Register (ADRCR).................................................................... 117
6.3 Operation........................................................................................................................... 119
6.3.1 Area Division....................................................................................................... 119
6.3.2 Bus Control Signal Timing.................................................................................. 121
6.3.3 Wait Modes.......................................................................................................... 123
6.3.4 Interconnections with Memory (Example) .......................................................... 129
6.4 Usage Notes...................................................................................................................... 131
6.4.1 Register Write Timing ......................................................................................... 131
6.4.2 Precautions on Setting ASTCR and ABWCR...................................................... 131
Rev.3.00 Mar. 26, 2007 Page xiv of xxii
REJ09B0353-0300
Section 7 I/O Ports.............................................................................................................. 133
7.1 Overview........................................................................................................................... 133
7.2 Port 1................................................................................................................................. 137
7.2.1 Overview.............................................................................................................. 137
7.2.2 Register Descriptions........................................................................................... 138
7.2.3 Pin Functions in Each Mode................................................................................ 140
7.3 Port 2................................................................................................................................. 142
7.3.1 Overview.............................................................................................................. 142
7.3.2 Register Descriptions........................................................................................... 143
7.3.3 Pin Functions in Each Mode................................................................................ 145
7.3.4 Input Pull-Up Transistors..................................................................................... 147
7.4 Port 3................................................................................................................................. 148
7.4.1 Overview.............................................................................................................. 148
7.4.2 Register Descriptions........................................................................................... 148
7.4.3 Pin Functions in Each Mode................................................................................ 150
7.5 Port 5................................................................................................................................. 152
7.5.1 Overview.............................................................................................................. 152
7.5.2 Register Descriptions........................................................................................... 153
7.5.3 Pin Functions in Each Mode................................................................................ 155
7.5.4 Input Pull-Up Transistors..................................................................................... 156
7.6 Port 6................................................................................................................................. 157
7.6.1 Overview.............................................................................................................. 157
7.6.2 Register Descriptions........................................................................................... 158
7.6.3 Pin Functions in Each Mode................................................................................ 160
7.7 Port 7................................................................................................................................. 163
7.7.1 Overview.............................................................................................................. 163
7.7.2 Register Description............................................................................................. 163
7.8 Port 8................................................................................................................................. 164
7.8.1 Overview.............................................................................................................. 164
7.8.2 Register Descriptions........................................................................................... 165
7.8.3 Pin Functions....................................................................................................... 167
7.9 Port 9................................................................................................................................. 168
7.9.1 Overview.............................................................................................................. 168
7.9.2 Register Descriptions........................................................................................... 168
7.9.3 Pin Functions....................................................................................................... 170
7.10 Port A................................................................................................................................ 172
7.10.1 Overview.............................................................................................................. 172
7.10.2 Register Descriptions........................................................................................... 173
7.10.3 Pin Functions ....................................................................................................... 175
7.11 Port B................................................................................................................................ 182
7.11.1 Overview.............................................................................................................. 182
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REJ09B0353-0300
7.11.2 Register Descriptions........................................................................................... 182
7.11.3 Pin Functions ....................................................................................................... 184
Section 8 16-Bit Integrated Timer Unit (ITU)............................................................ 191
8.1 Overview........................................................................................................................... 191
8.1.1 Features................................................................................................................ 191
8.1.2 Block Diagrams ................................................................................................... 194
8.1.3 Input/Output Pins................................................................................................. 199
8.1.4 Register Configuration......................................................................................... 201
8.2 Register Descriptions....................................................................................................... . 204
8.2.1 Timer Start Register (TSTR) ................................................................................ 204
8.2.2 Timer Synchro Register (TSNC) ......................................................................... 206
8.2.3 Timer Mode Register (TMDR)............................................................................ 208
8.2.4 Timer Function Control Register (TFCR)............................................................ 211
8.2.5 Timer Output Master Enable Register (TOER) ................................................... 214
8.2.6 Timer Output Control Register (TOCR).............................................................. 216
8.2.7 Timer Counters (TCNT) ...................................................................................... 218
8.2.8 General Registers (GRA, GRB)........................................................................... 219
8.2.9 Buffer Registers (BRA, BRB).............................................................................. 220
8.2.10 Timer Control Registers (TCR) ........................................................................... 221
8.2.11 Timer I/O Control Register (TIOR)..................................................................... 223
8.2.12 Timer Status Register (TSR)................................................................................ 225
8.2.13 Timer Interrupt Enable Register (TIER).............................................................. 227
8.3 CPU Interface.................................................................................................................... 228
8.3.1 16-Bit Accessible Registers................................................................................. 228
8.3.2 8-Bit Accessible Registers ................................................................................... 231
8.4 Operation........................................................................................................................... 232
8.4.1 Overview.............................................................................................................. 232
8.4.2 Basic Functions.................................................................................................... 234
8.4.3 Synchronization ................................................................................................... 243
8.4.4 PWM Mode.......................................................................................................... 245
8.4.5 Reset-Synchronized PWM Mode......................................................................... 249
8.4.6 Complementary PWM Mode............................................................................... 252
8.4.7 Phase Counting Mode.......................................................................................... 261
8.4.8 Buffering.............................................................................................................. 263
8.4.9 ITU Output Timing.............................................................................................. 269
8.5 Interrupts........................................................................................................................... 272
8.5.1 Setting of Status Flags.......................................................................................... 272
8.5.2 Clearing of Status Flags....................................................................................... 274
8.5.3 Interrupt Sources.................................................................................................. 275
8.6 Usage Notes...................................................................................................................... 276
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REJ09B0353-0300
Section 9 Programmable Timing Pattern Controller................................................. 291
9.1 Overview........................................................................................................................... 291
9.1.1 Features................................................................................................................ 291
9.1.2 Block Diagram..................................................................................................... 292
9.1.3 TPC Pins.............................................................................................................. 293
9.1.4 Registers............................................................................................................... 294
9.2 Register Descriptions........................................................................................................ 295
9.2.1 Port A Data Direction Register (PADDR)........................................................... 295
9.2.2 Port A Data Register (PADR).............................................................................. 295
9.2.3 Port B Data Direction Register (PBDDR) ........................................................... 296
9.2.4 Port B Data Register (PBDR) .............................................................................. 296
9.2.5 Next Data Register A (NDRA)............................................................................ 297
9.2.6 Next Data Register B (NDRB)............................................................................. 299
9.2.7 Next Data Enable Register A (NDERA).............................................................. 301
9.2.8 Next Data Enable Register B (NDERB).............................................................. 302
9.2.9 TPC Output Control Register (TPCR)................................................................. 303
9.2.10 TPC Output Mode Register (TPMR)................................................................... 306
9.3 Operation .......................................................................................................................... 308
9.3.1 Overview.............................................................................................................. 308
9.3.2 Output Timing ..................................................................................................... 309
9.3.3 Normal TPC Output............................................................................................. 310
9.3.4 Non-Overlapping TPC Output............................................................................. 312
9.3.5 TPC Output Triggering by Input Capture............................................................ 314
9.4 Usage Notes...................................................................................................................... 315
9.4.1 Operation of TPC Output Pins............................................................................. 315
9.4.2 Note on Non-Overlapping Output........................................................................ 315
Section 10 Watchdog Timer............................................................................................. 317
10.1 Overview........................................................................................................................... 317
10.1.1 Features................................................................................................................ 317
10.1.2 Block Diagram..................................................................................................... 318
10.1.3 Pin Configuration................................................................................................. 318
10.1.4 Register Configuration......................................................................................... 319
10.2 Register Descriptions........................................................................................................ 319
10.2.1 Timer Counter (TCNT)........................................................................................ 319
10.2.2 Timer Control/Status Register (TCSR)................................................................ 320
10.2.3 Reset Control/Status Register (RSTCSR)............................................................ 322
10.2.4 Notes on Register Access..................................................................................... 324
10.3 Operation .......................................................................................................................... 326
10.3.1 Watchdog Timer Operation ................................................................................. 326
10.3.2 Interval Timer Operation ..................................................................................... 327
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10.3.3 Timing of Setting of Overflow Flag (OVF)......................................................... 328
10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................... 329
10.4 Interrupts........................................................................................................................... 329
10.5 Usage Notes...................................................................................................................... 330
Section 11 Serial Communication Interface................................................................ 331
11.1 Overview........................................................................................................................... 331
11.1.1 Features................................................................................................................ 331
11.1.2 Block Diagram..................................................................................................... 333
11.1.3 Input/Output Pins................................................................................................. 334
11.1.4 Register Configuration......................................................................................... 335
11.2 Register Descriptions........................................................................................................ 336
11.2.1 Receive Shift Register (RSR)............................................................................... 336
11.2.2 Receive Data Register (RDR).............................................................................. 336
11.2.3 Transmit Shift Register (TSR)............................................................................. 337
11.2.4 Transmit Data Register (TDR)............................................................................. 337
11.2.5 Serial Mode Register (SMR)................................................................................ 338
11.2.6 Serial Control Register (SCR).............................................................................. 341
11.2.7 Serial Status Register (SSR)................................................................................. 345
11.2.8 Bit Rate Register (BRR) ...................................................................................... 349
11.3 Operation........................................................................................................................... 358
11.3.1 Overview.............................................................................................................. 358
11.3.2 Operation in Asynchronous Mode....................................................................... 360
11.3.3 Multiprocessor Communication........................................................................... 369
11.3.4 Synchronous Operation........................................................................................ 376
11.4 SCI Interrupts.................................................................................................................... 384
11.5 Usage Notes...................................................................................................................... 385
Section 12 Smart Card Interface ..................................................................................... 391
12.1 Overview........................................................................................................................... 391
12.1.1 Features................................................................................................................ 391
12.1.2 Block Diagram..................................................................................................... 392
12.1.3 Pin Configuration................................................................................................. 393
12.1.4 Register Configuration......................................................................................... 393
12.2 Register Descriptions........................................................................................................ 394
12.2.1 Smart Card Mode Register (SCMR).................................................................... 394
12.2.2 Serial Status Register (SSR)................................................................................. 396
12.3 Operation........................................................................................................................... 397
12.3.1 Overview.............................................................................................................. 397
12.3.2 Pin Connections................................................................................................... 398
12.3.3 Data Format ......................................................................................................... 399
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REJ09B0353-0300
12.3.4 Register Settings .................................................................................................. 401
12.3.5 Clock.................................................................................................................... 403
12.3.6 Data Transfer Operations..................................................................................... 405
12.4 Usage Note........................................................................................................................ 411
Section 13 A/D Converter................................................................................................. 415
13.1 Overview........................................................................................................................... 415
13.1.1 Features................................................................................................................ 415
13.1.2 Block Diagram..................................................................................................... 416
13.1.3 Input Pins............................................................................................................. 417
13.1.4 Register Configuration......................................................................................... 418
13.2 Register Descriptions........................................................................................................ 419
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 419
13.2.2 A/D Control/Status Register (ADCSR) ............................................................... 420
13.2.3 A/D Control Register (ADCR) ............................................................................ 422
13.3 CPU Interface.................................................................................................................... 423
13.4 Operation .......................................................................................................................... 424
13.4.1 Single Mode (SCAN = 0) .................................................................................... 424
13.4.2 Scan Mode (SCAN = 1)....................................................................................... 426
13.4.3 Input Sampling and A/D Conversion Time ......................................................... 428
13.4.4 External Trigger Input Timing............................................................................. 429
13.5 Interrupts........................................................................................................................... 430
13.6 Usage Notes...................................................................................................................... 430
Section 14 RAM.................................................................................................................. 435
14.1 Overview........................................................................................................................... 435
14.1.1 Block Diagram..................................................................................................... 436
14.1.2 Register Configuration......................................................................................... 436
14.2 System Control Register (SYSCR)................................................................................... 437
14.3 Operation .......................................................................................................................... 438
Section 15 ROM.................................................................................................................. 439
15.1 Overview........................................................................................................................... 439
15.2 Overview of Flash Memory.............................................................................................. 440
15.2.1 Features................................................................................................................ 440
15.2.2 Block Diagram..................................................................................................... 441
15.2.3 Pin Configuration................................................................................................. 442
15.2.4 Register Configuration......................................................................................... 442
15.3 Register Descriptions........................................................................................................ 443
15.3.1 Flash Memory Control Register (FLMCR).......................................................... 443
15.3.2 Erase Block Register (EBR) ................................................................................ 447
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REJ09B0353-0300
15.3.3 RAM Control Register (RAMCR)....................................................................... 449
15.3.4 Flash Memory Status Register (FLMSR)............................................................. 451
15.4 On-Board Programming Modes........................................................................................ 452
15.4.1 Boot Mode ........................................................................................................... 455
15.4.2 User Program Mode............................................................................................. 460
15.5 Programming/Erasing Flash Memory............................................................................... 462
15.5.1 Program Mode ..................................................................................................... 463
15.5.2 Program-Verify Mode.......................................................................................... 464
15.5.3 Erase Mode .......................................................................................................... 466
15.5.4 Erase-Verify Mode............................................................................................... 466
15.6 Flash Memory Protection.................................................................................................. 468
15.6.1 Hardware Protection ............................................................................................ 468
15.6.2 Software Protection.............................................................................................. 470
15.6.3 Error Protection.................................................................................................... 471
15.6.4 NMI Input Disable Conditions............................................................................. 473
15.7 Flash Memory Emulation by RAM................................................................................... 474
15.8 Flash Memory PROM Mode............................................................................................. 475
15.8.1 PROM Mode Setting............................................................................................ 475
15.8.2 Memory Map ....................................................................................................... 476
15.8.3 PROM Mode Operation....................................................................................... 476
15.8.4 Memory Read Mode............................................................................................ 479
15.8.5 Auto-Program Mode............................................................................................ 482
15.8.6 Auto-Erase Mode................................................................................................. 484
15.8.7 Status Read Mode................................................................................................ 485
15.8.8 PROM Mode Transition Time............................................................................. 487
15.8.9 Notes on Memory Programming.......................................................................... 488
15.9 Notes on Flash Memory Programming/Erasing................................................................ 488
15.10 Mask ROM Overview....................................................................................................... 494
15.10.1 Block Diagram..................................................................................................... 494
15.11 Notes on Ordering Mask ROM Version Chip................................................................... 495
Section 16 Clock Pulse Generator.................................................................................. 497
16.1 Overview........................................................................................................................... 497
16.1.1 Block Diagram..................................................................................................... 498
16.2 Oscillator Circuit............................................................................................................... 498
16.2.1 Connecting a Crystal Resonator........................................................................... 499
16.2.2 External Clock Input............................................................................................ 501
16.3 Duty Adjustment Circuit................................................................................................... 504
16.4 Prescalers .......................................................................................................................... 504
16.5 Frequency Divider............................................................................................................. 504
16.5.1 Register Configuration......................................................................................... 504
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16.5.2 Division Control Register (DIVCR) .................................................................... 505
16.5.3 Usage Notes......................................................................................................... 506
Section 17 Power-Down State......................................................................................... 507
17.1 Overview........................................................................................................................... 507
17.2 Register Configuration...................................................................................................... 509
17.2.1 System Control Register (SYSCR)...................................................................... 509
17.2.2 Module Standby Control Register (MSTCR) ...................................................... 511
17.3 Sleep Mode....................................................................................................................... 513
17.3.1 Transition to Sleep Mode..................................................................................... 513
17.3.2 Exit from Sleep Mode.......................................................................................... 513
17.4 Software Standby Mode.................................................................................................... 514
17.4.1 Transition to Software Standby Mode................................................................. 514
17.4.2 Exit from Software Standby Mode ...................................................................... 514
17.4.3 Selection of Oscillator Waiting Time af ter Exit from Software Standby Mode.. 515
17.4.4 Sample Application of Software Standby Mode.................................................. 516
17.4.5 Usage Note........................................................................................................... 516
17.5 Hardware Standby Mode .................................................................................................. 517
17.5.1 Transition to Hardware Standby Mode................................................................ 517
17.5.2 Exit from Hardware Standby Mode..................................................................... 517
17.5.3 Timing for Hardware Standby Mode................................................................... 518
17.6 Module Standby Function................................................................................................. 519
17.6.1 Module Standby Timing...................................................................................... 519
17.6.2 Read/Write in Module Standby ........................................................................... 519
17.6.3 Usage Notes......................................................................................................... 519
17.7 System Clock Output Disabling Function......................................................................... 520
Section 18 Electrical Characteristics.............................................................................. 521
18.1 Electrical Characteristics of Mask ROM Version............................................................. 521
18.1.1 Absolute Maximum Ratings................................................................................ 521
18.1.2 DC Characteristics............................................................................................... 522
18.1.3 AC Characteristics............................................................................................... 530
18.1.4 A/D Conversion Characteristics........................................................................... 535
18.2 Electrical Characteristics of Flash Memory Version ........................................................ 536
18.2.1 Absolute Maximum Ratings................................................................................ 536
18.2.2 DC Characteristics............................................................................................... 537
18.2.3 AC Characteristics............................................................................................... 543
18.2.4 A/D Conversion Characteristics........................................................................... 548
18.2.5 Flash Memory Characteristics ............................................................................. 549
18.3 Operational Timing........................................................................................................... 552
18.3.1 Bus Timing .......................................................................................................... 552
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18.3.2 Control Signal Timing ......................................................................................... 556
18.3.3 Clock Timing....................................................................................................... 558
18.3.4 TPC and I/O Port Timing..................................................................................... 558
18.3.5 ITU Timing.......................................................................................................... 559
18.3.6 SCI Input/Output Timing..................................................................................... 560
Appendix A Instruction Set.............................................................................................. 561
A.1 Instruction List.................................................................................................................. 561
A.2 Operation Code Maps....................................................................................................... 577
A.3 Number of States Required for Execution ........................................................................ 580
Appendix B Internal I/O Register Field........................................................................ 590
B.1 Addresses.......................................................................................................................... 590
B.2 Function ............................................................................................................................ 597
Appendix C I/O Block Diagrams.................................................................................... 655
C.1 Port 1 Block Diagram ....................................................................................................... 655
C.2 Port 2 Block Diagram ....................................................................................................... 656
C.3 Port 3 Block Diagram ....................................................................................................... 657
C.4 Port 5 Block Diagram ....................................................................................................... 658
C.5 Port 6 Block Diagram ....................................................................................................... 659
C.6 Port 7 Block Diagram ....................................................................................................... 661
C.7 Port 8 Block Diagram ....................................................................................................... 662
C.8 Port 9 Block Diagram ....................................................................................................... 664
C.9 Port A Block Diagram....................................................................................................... 668
C.10 Port B Block Diagram....................................................................................................... 671
Appendix D Pin States....................................................................................................... 674
D.1 Port States in Each Mode.................................................................................................. 674
D.2 Pin States at Reset............................................................................................................. 676
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode................................................................. 679
Appendix F Product Lineup ............................................................................................. 680
Appendix G Package Dimensions................................................................................... 681
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REJ09B0353-0300
Section 1 Overview
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REJ09B0353-0300
Section 1 Overview
1.1 Overview
The H8/3039 Group comprises microcomputers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core featuring an original Renesas Technology
architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern contro ller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The H8/3039 Group consists of four models: the H8/3039 with 128 kbytes of ROM and 4 kbytes
of RAM, the H8/3038 with 64 kbytes of ROM and 2 kbytes of RAM, the H8/3037 with 32 kbytes
of ROM and 1 kbytes of RAM, and the H8/3036 with 16 kbytes of ROM and 512 bytes of RAM.
The five MCU operating modes offer a choice of expanded mode, single-chip mode and address
space size.
In addition to the mask-ROM version of the H8/3039 Group, an F-ZTAT™ version with an on-
chip flash memory that can be freely programmed and reprogrammed by the user after the board is
installed is also available. This version enables users to respond quickly and flexibly to changing
application specifications, growing production volumes, and other conditions.
Table 1.1 summarizes the features of the H8/3039 Group.
Note: F-ZTAT is a trademark of Renesas Technology Corp.
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 2 of 682
REJ09B0353-0300
Table 1.1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 18 MHz
• Add/subtra ct: 111 ns
• Multipl y/d ivi de: 778 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bit s)
• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
• Bit accumula tor function
• Bit manipulation instructions with register-indirect specification of bit
positions
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 3 of 682
REJ09B0353-0300
Feature Description
Memory H8/3039
• ROM: 128 kbytes
• RAM: 4 kbytes
H8/3038
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3037
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/3036
• ROM: 16 kbytes
• RAM: 512 bytes
Interrupt controller • Five external interrupt pins: NMI, IRQ0, IRQ1, IRQ4, IRQ5
• 25 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address spa ce can be partit ion ed into eigh t areas, with indepen dent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes
16-bit integrated
timer unit (ITU) • Five 16-bit timer channels, capable of processing up to 12 pulse outputs
or 10 pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 4 of 682
REJ09B0353-0300
Feature Description
Programmable
timing pattern
controller (TPC)
• Maximum 15-bit pulse output, using ITU as time base
• Up to three 4-bit pulse output groups and one 3-bit pulse output group (or
one 15-bit group, one 8-bit group, or one 7-bit group)
• Non-overlap mode available
Watchdog timer
(WDT), 1 channel • Reset signal can be generated by overflow
• Reset signal can be output externally (However, not available with the
F-ZTAT version.)
• Usable as an interval timer
Serial
communication
interface (SCI),
2 channels
• Selection of asynchronous or synchronous mode
• Full duplex: can transmit and receive simultaneously
• On-chip baud-rate generator
• Smart card interface functions added (SCI0 only)
A/D converter • Resolution: 10 bits
• Eight channels, wi th selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• Can be externally triggered
I/O ports • 55 input/output pins
• 8 input-only pins
Operating modes Five MCU operating modes
Mode Address Space Address Pins Bus Width
Mode 1 1 Mbyte A0 to A19 8 bits
Mode 3 16 Mbytes A23 to A08 bits
Mode 5 1 Mbyte A0 to A19 8 bits
Mode 6 64 kbytes — —
Mode 7 1 Mbyte — —
• On-chip ROM is disabled in modes 1 and 3
Power-down state • Sleep mode
• Software standb y mode
• Hardware stan dby mode
• Module stan db y functi on
• Programmable System clock frequency division
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 5 of 682
REJ09B0353-0300
Feature Description
Other features • On-chip clock oscillator
Product lineup Model (5 V) Model (3 V)*Package ROM
HD64F3039F HD64F3039VF 80-pin QFP (FP-80A) Flash memory
HD64F3039TE HD64F3039VTE 80-pin TQFP (TFP-80C)
HD6433039F HD6433039VF 80-pin QFP (FP-80A) Mask ROM
HD6433039TE HD6433039VTE 80-pin TQFP (TFP-80C)
HD6433038F HD6433038VF 80-pin QFP (FP-80A) Mask ROM
HD6433038TE HD6433038VTE 80-pin TQFP (TFP-80C)
HD6433037F HD6433037VF 80-pin QFP (FP-80A) Mask ROM
HD6433037TE HD6433037VTE 80-pin TQFP (TFP-80C)
HD6433036F HD6433036VF 80-pin QFP (FP-80A) Mask ROM
HD6433036TE HD6433036VTE 80-pin TQFP (TFP-80C)
Note: *There are two 3 V versions: one with VCC = 2.7 V to 5.5 V and φ = 2 to 8 MHz,
and one with VCC = 3.0 V to 5.5 V and φ = 2 to 10 MHz. However, there is only
one flash memory version, wi t h VCC = 3.0 to 5.5 V and φ = 2 to 10 MHz.
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 6 of 682
REJ09B0353-0300
1.2 Block Diagram
Figure 1.1 shows an internal block diagram of the H8/3039 Group.
P7
7
/AN
7
P7
6
/AN
6
P7
5
/AN
5
P7
4
/AN
4
P7
3
/AN
3
P7
2
/AN
2
P7
1
/AN
1
P7
0
/AN
0
AV
CC
AV
SS
PA
7
/TP
7
/TIOCB
2
/A
20
PA
6
/TP
6
/TIOCA
2
/A
21
PA
5
/TP
5
/TIOCB
1
/A
22
PA
4
/TP
4
/TIOCA
1
/A
23
PA
3
/TP
3
/TIOCB
0
/TCLKD
PA
2
/TP
2
/TIOCA
0
/TCLKC
PA
1
/TP
1
/TCLKB
PA
0
/TP
0
/TCLKA
PB
7
/TP
15
/ADTRG
PB
5
/TP
13
/TOCXB
4
PB
4
/TP
12
/TOCXA
4
PB
3
/TP
11
/TIOCB
4
PB
2
/TP
10
/TIOCA
4
PB
1
/TP
9
/TIOCB
3
PB
0
/TP
8
/TIOCA
3
P2
7
/A
15
P2
6
/A
14
P2
5
/A
13
P2
4
/A
12
P2
3
/A
11
P2
2
/A
10
P2
1
/A
9
P2
0
/A
8
P1
7
/A
7
P1
6
/A
6
P1
5
/A
5
P1
4
/A
4
P1
3
/A
3
P1
2
/A
2
P1
1
/A
1
P1
0
/A
0
P9
5
/SCK
1
/IRQ
5
P9
4
/SCK
0
/IRQ
4
P9
3
/RxD
1
P9
2
/RxD
0
P9
1
/TxD
1
P9
0
/TxD
0
P5
3
/A
19
P5
2
/A
18
P5
1
/A
17
P5
0
/A
16
Data bus (lower)
Bus
controller
Clock osc.
H8/300H CPU
ROM
(Flash memory,
mask ROM)
RAM
16-bit
integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Interrupt
controller
Serial
communication
interface
(SCI) × 2 channel
Watchdog
timer
(WDT)
A/D converter
Port 3
P6
5
/WR
P6
4
/RD
P6
3
/AS
P6
0
/WAIT
P8
1
/IRQ
1
P8
0
/IRQ
0
MD
1
MD
0
EXTAL
XTAL
φ
STBY
RES
RESO/FWE*
NMI
V
CC
V
CC
V
SS
V
SS
V
SS
P3
7
/D
7
P3
6
/D
6
P3
5
/D
5
P3
4
/D
4
P3
3
/D
3
P3
2
/D
2
P3
1
/D
1
P3
0
/D
0
Port 2Port 1 Port 5
Port 9
Port 7Port APort B
Note: * Mask ROM: RESO
Flash memory: FWE
Port 8 Port 6
Address bus
Data bus (upper)
MD
2
Figure 1.1 Block Diagram
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 7 of 682
REJ09B0353-0300
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1.2 shows the pin arrangement of the H8/3039 Group.
P7
1
/AN
1
P7
0
/AN
0
AV
SS
RESO/FWE*
P6
5
/WR
P6
4
/RD
P6
3
/AS
V
CC
XTAL
EXTAL
V
SS
NMI
RES
STBY
φ
MD
1
MD
0
P6
0
/WAIT
P5
3
/A
19
P5
2
/A
18
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TIOCA
3
/TP
8
/PB
0
TIOCB
3
/TP
9
/PB
1
TIOCA
4
/TP
10
/PB
2
TIOCB
4
/TP
11
/PB
3
TOCXA
4
/TP
12
/PB
4
TOCXB
4
/TP
13
/PB
5
MD
2
ADTRG/TP
15
/PB
7
TxD
0
/P9
0
RxD
0
/P9
2
IRQ
4
/SCK
0
/P9
4
V
SS
D
0
/P3
0
D
1
/P3
1
D
2
/P3
2
D
3
/P3
3
D
4
/P3
4
D
5
/P3
5
D
6
/P3
6
D
7
/P3
7
PA
7
/TP
7
/TIOCB
2
/A
20
PA
6
/TP
6
/TIOCA
2
/A
21
PA
5
/TP
5
/TIOCB
1
/A
22
PA
4
/TP
4
/TIOCA
1
/A
23
PA
3
/TP
3
/TIOCB
0
/TCLKD
PA
2
/TP
2
/TIOCA
0
/TCLKC
PA
1
/TP
1
/TCLKB
PA
0
/TP
0
/TCLKA
P9
5
/SCK
1
/IRQ
5
P9
3
/RxD
1
P9
1
/TxD
1
P8
1
/IRQ
1
P8
0
/IRQ
0
AVcc
P7
7
/AN
7
P7
6
/AN
6
P7
5
/AN
5
P7
4
/AN
4
P7
3
/AN
3
P7
2
/AN
2
V
CC
A
0
/P1
0
A
1
/P1
1
A
2
/P1
2
A
3
/P1
3
A
4
/P1
4
A
5
/P1
5
A
6
/P1
6
A
7
/P1
7
V
SS
A
8
/P2
0
A
9
/P2
1
A
10
/P2
2
A
11
/P2
3
A
12
/P2
4
A
13
/P2
5
A
14
/P2
6
A
15
/P2
7
A
16
/P5
0
A
17
/P5
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Top view
(FP-80A, TFP-80C)
Note: * Mask ROM: RESO
Flash memory: FWE
Figure 1.2 Pin Arrangement (FP-80A, TFP-80C Top View)
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 8 of 682
REJ09B0353-0300
1.3.2 Pin Functions
Pin Assign ments in Each Mode
Table 1.2 lists the FP-80A and TFP-80C pin assignments in each mode.
Table 1.2 FP-80A and TFP-80C Pin Assignments in Each Mode
Pin Name
Pin
No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode
Flash memory
1PB
0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
NC
2PB
1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
NC
3PB
2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
NC
4PB
3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
NC
5PB
4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
NC
6PB
5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
NC
7MD
2MD2MD2MD2MD2VSS
8PB
7/TP15/
ADTRG PB7/TP15/
ADTRG PB7/TP15/
ADTRG PB7/TP15/
ADTRG PB7/TP15/
ADTRG NC
9P9
0/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0NC
10 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0VSS
11 P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
NC
12 VSS VSS VSS VSS VSS VSS
13 D0D0D0P30P30I/O0
14 D1D1D1P31P31I/O1
15 D2D2D2P32P32I/O2
16 D3D3D3P33P33I/O3
17 D4D4D4P34P34I/O4
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Rev.3.00 Mar. 26, 2007 Page 9 of 682
REJ09B0353-0300
Pin Name
Pin
No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode
Flash memory
18 D5D5D5P35P35I/O5
19 D6D6D6P36P36I/O6
20 D7D7D7P37P37I/O7
21 VCC VCC VCC VCC VCC VCC
22 A0A0P10/A0P10P10A0
23 A1A1P11/A1P11P11A1
24 A2A2P12/A2P12P12A2
25 A3A3P13/A3P13P13A3
26 A4A4P14/A4P14P14A4
27 A5A5P15/A5P15P15A5
28 A6A6P16/A6P16P16A6
29 A7A7P17/A7P17P17A7
30 VSS VSS VSS VSS VSS VSS
31 A8A8P20/A8P20P20A8
32 A9A9P21/A9P21P21A9
33 A10 A10 P22/A10 P22P22A10
34 A11 A11 P23/A11 P23P23A11
35 A12 A12 P24/A12 P24P24A12
36 A13 A13 P25/A13 P25P25A13
37 A14 A14 P26/A14 P26P26A14
38 A15 A15 P27/A15 P27P27A15
39 A16 A16 P50/A16 P50P50A16
40 A17 A17 P51/A17 P51P51VSS
41 A18 A18 P52/A18 P52P52VSS
42 A19 A19 P53/A19 P53P53VSS
43 P60/WAIT P60/WAIT P60/WAIT P60P60NC
44 MD0MD0MD0MD0MD0VSS
45 MD1MD1MD1MD1MD1VSS
46 φφφφφNC
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Rev.3.00 Mar. 26, 2007 Page 10 of 682
REJ09B0353-0300
Pin Name
Pin
No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode
Flash memory
47 STBY STBY STBY STBY STBY VCC
48 RES RES RES RES RES RES
49 NMI NMI NMI NMI NMI VCC
50 VSS VSS VSS VSS VSS VSS
51 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL
52 XTAL XTAL XTAL XTAL XTAL XTAL
53 VCC VCC VCC VCC VCC VCC
54 AS AS AS P63P63NC
55 RD RD RD P64P64NC
56 WR WR WR P65P65VCC
57 RESO/
FWE*
RESO/
FWE*
RESO/
FWE*
RESO/
FWE*
RESO/
FWE*FWE
58 AVSS AVSS AVSS AVSS AVSS VSS
59 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0NC
60 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1NC
61 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2NC
62 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3NC
63 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4NC
64 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5NC
65 P76/AN6P76/AN6P76/AN6P76/AN6P76/AN6NC
66 P77/AN7P77/AN7P77/AN7P77/AN7P77/AN7NC
67 AVCC AVCC AVCC AVCC AVCC VCC
68 P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0VSS
69 P81/IRQ1P81/IRQ1P81/IRQ1P81/IRQ1P81/IRQ1VSS
70 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1NC
71 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1NC
72 P95/SCK1/
IRQ5
P95/SCK1/
IRQ5
P95/SCK1/
IRQ5
P95/SCK1/
IRQ5
P95/SCK1/
IRQ5
VCC
73 PA0/TP0/
TCLKA PA0/TP0/
TCLKA PA0/TP0/
TCLKA PA0/TP0/
TCLKA PA0/TP0/
TCLKA CE
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 11 of 682
REJ09B0353-0300
Pin Name
Pin
No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode
Flash memory
74 PA1/TP1/
TCLKB PA1/TP1/
TCLKB PA1/TP1/
TCLKB PA1/TP1/
TCLKB PA1/TP1/
TCLKB OE
75 PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
PA2/TP2/
TIOCA0/
TCLKC
WE
76 PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
PA3/TP3/
TIOCB0/
TCLKD
NC
77 PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1/A23
PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1
PA4/TP4/
TIOCA1
NC
78 PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1/A22
PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1
PA5/TP5/
TIOCB1
NC
79 PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2/A21
PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2
PA6/TP6/
TIOCA2
NC
80 PA7/TP7/
TIOCB2
A20 PA7/TP7/
TIOCB2
PA7/TP7/
TIOCB2
PA7/TP7/
TIOCB2
NC
Notes: Pins marked NC should be left unconnected.
For details about PROM mode see section 15, ROM.
*Mask ROM: RESO
Flash Memory: FWE
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 12 of 682
REJ09B0353-0300
1.4 Pin Functions
Table 1.3 summarizes the pin functions.
Table 1.3 Pin Functions
Type Symbol Pin No. I/O Name and Function
Power VCC 21,
53 Input Power: For connection to the power supply.
Connect all VCC pins to the system power
supply.
VSS 12,
30,
50
Input Ground: For connection to ground (0 V).
Connect all VSS pins to the 0-V system power
supply.
Clock XTAL 52 Input For connection to a crystal resonator
For examples of crystal resonator and
external clock input, see section 16, Clock
Pulse Generator.
EXTAL 51 Input For connection to a crystal resonator or input
of an external clock signal. For examples of
crystal resonator and external clock input, see
section 16, Clock Pulse Generator.
φ46 Output System clock: Supplies the system clock to
external dev ices
Operating
mode control MD2,
MD1,
MD0
7,
45,
44
Input Mode 2 to mode 0: For setting the operating
mode, as follows. These pins should not be
changed during opera t ion .
MD2MD1MD0Operating Mode
000—
0 0 1 Mode 1
010—
0 1 1 Mode 3
100—
1 0 1 Mode 5
1 1 0 Mode 6
1 1 1 Mode 7
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 13 of 682
REJ09B0353-0300
Type Symbol Pin No. I/O Name and Function
System
control RES 48 Input Reset input: When driven low, this pin resets
the chip
RESO/
FWE 57 Output/
Input Reset output (Mask ROM version): Outputs
WDT-generated reset signal to an external
device.
Write enable signal (F-ZTAT version): Flash
memory write contr ol sig nal.
STBY 47 Input Standby: When driven low, this pin forces a
transition to hardware standby mode
Interrupts NMI 49 Input Nonmaskable interrupt: Requests a
nonmaskable interrupt
IRQ5, IRQ4
IRQ1, IRQ0
72, 11,
69, 68 Input Interrupt request 5, 4, 1, 0: Maskable
interrupt request pins
Address bus A23 to A20,
A19 to A8,
A7 to A0
77 to 80,
42 to 31,
29 to 22
Output Address bus: Outputs address signals
Data bus D7 to D020 to 13 Input/
output Data bus: Bidirectional data bus
Bus control AS 54 Output Address strobe: Goes low to indicate va lid
address output on the address bus
RD 55 Output Read: Goes low to indicate reading from the
external addr es s spac e.
WR 56 Output Write: Goes low to indicate writing to the
external address space indicates valid data on
the data bus.
WAIT 43 Input Wait: Requests insertion of wait states in bus
cycles during access to the external addres s
space.
TCLKD to
TCLKA 76 to 73 Input Clock input A to D: Ex ternal clock inputs16-bit
integrated
timer unit
(ITU) TIOCA4 to
TIOCA0
3, 1, 79,
77, 75 Input/
Output Input capture/output compare A4 to A0:
GRA4 to GRA0 output compare or input
capture, or PWM output
TIOCB4 to
TIOCB0
4, 2, 80,
78, 76 Input/
output Input capture/output compare B4 to B0
GRB4 to GRB0 output compare or input
capture, or PWM output
TOCXA45 Output Output compare XA4: PWM out put
TOCXB46 Output Output compare XB4: PWM out put
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 14 of 682
REJ09B0353-0300
Type Symbol Pin No. I/O Name and Function
Programmable
timing pattern
controller
(TPC)
TP15,
TP13 to TP0
8, 6 to 1
80 to 73 Output TPC output 15 , 13 to 0 : Pulse output
TxD1,
TxD0
70, 9 Output Transmit data:(channels 0 and 1): SCI data
output
Serial com-
munication
interface
(SCI) RxD1,
RxD0
71, 10 Input Receive data:(c hannels 0 and 1): SCI data
input
SCK1,
SCK0
72, 11 Input/
output Serial clock:(channels 0 and 1): SCI clock
input/output
AN7 to AN066 to 59 Input Analog 7 to 0: Analog input pinsA/D
converter ADTRG 8 Input A/D trigger: External trigger input for starting
A/D conversion
AVCC 67 Input Power supply pin and reference voltage input
pin for the A/D converter. Connect to the
system power supply when not using the A/D
converter.
AVSS 58 Input Ground pin for the A/D converter. Connect to
system power-supply (0 V).
I/O ports P17 to P1029 to 22 Input/
output Port 1: Eight input/output pins. The direction
of each pin can be selected in the port 1 data
direction register (P1DDR).
P27 to P2038 to 31 Input/
output Port 2: Eight input/output pins. The direction
of each pin can be selected in the port 2 data
direction register (P2DDR).
P37 to P3020 to 13 Input/
output Port 3: Eight input/output pins. The direction
of each pin can be selected in the port 3 data
direction register (P3DDR).
P53 to P5042 to 39 Input/
output Port 5: Four input/output pins. The direction of
each pin can be selected in the port 5 data
direction register (P5DDR).
P65 to P63,
P60
56 to 54,
43 Input/
output Port 6: Four input/output pins. The direction of
each pin can be selected in the port 6 data
direction register (P6DDR).
P77 to P7066 to 59 Input Port 7: Eight input pins
P81, P8069, 68 Input/
output Port 8: Two input/output pins. The di rection of
each pin can be selected in the port 8 data
direction register (P8DDR).
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 15 of 682
REJ09B0353-0300
Type Symbol Pin No. I/O Name and Function
I/O ports P95 to
P90
72, 11
71, 10
70, 9
Input/
output Port 9: Six input/output pins. The direction of
each pin can be selected in the port 9 data
direction register (P9DDR).
PA7 to
PA0
80 to 73 Input/
output Port A: Eight input/output pins. The direction
of each pin can be selected in the port A data
direction register (PADDR).
PB7, PB5
to PB0
8, 6to1 Input/
output Port B: Seven input/output pins. The direction
of each pin can be selected in the port B data
direction register (PBDDR).
Section 1 Overview
Rev.3.00 Mar. 26, 2007 Page 16 of 682
REJ09B0353-0300
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 17 of 682
REJ09B0353-0300
Section 2 CPU
2.1 Overview
The H8/300H CPU is a high-speed central processing un it with an internal 32-bit architecture that
is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general
registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
2.1.1 Features
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 series object programs without alteration
• General-register architecture
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)
• Sixty-two basic instructions
8/16/32-b it ar ithmetic and logic in str uctions
Multiply and divide instructio ns
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx: 16, or #xx: 3 2]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
• 16-Mbyte linear address space
• High-speed operation
All frequen tly-used instructio ns execute in two to four states
Maximum clock frequency: 18 MHz
8/16/32-bit register-register add/subtract: 111 ns
8 × 8-bit register-reg ister multiply: 778 ns
16 ÷ 8-bit register-register divide: 778 ns
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 18 of 682
REJ09B0353-0300
16 × 16-bit register-register multiply: 1222 ns
32 ÷ 16-bit register-register divide: 1222 ns
• Two CPU operating modes
Normal mode
Advanced mode
• Low-power mode
Transition to power-down state by SLEEP instruction
2.1.2 Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8/300H has the following enhancements.
• More general registers
Eight 16-bit registers have been added.
• Expanded address space
Advanced mode supports a maximum 16-Mbyte address space.
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Data transfer, arithmetic, and logic instructions can operate on 32-bit data.
Signed multiply/divide instr uctions and other instructions have been added.
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 19 of 682
REJ09B0353-0300
2.2 CPU Operating Modes
The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1.
Unless specified otherwise, all descriptions in this manual refer to advanced mode.
CPU operating modes
Normal mode Maximum 64 kbytes, program
and data areas combined
Maximum 16 Mbytes, program
and data areas combined
Advanced mode
Figure 2.1 CPU Operating Modes
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 20 of 682
REJ09B0353-0300
2.3 Address Space
The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of a
normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address sp ace
depending on the MCU operation mode. Figure 2.2 shows the address ranges of the H8/3039
Group. For further details see section 3.6, Memory Map in Each Operating Mode.
The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are
ignored.
H'000000
H'FFFFFF
(b) 16-Mbyte mode(a) 1-Mbyte mode
2. Advanced mode1. Normal mode (64-Kbyte mode)
H'00000
H'FFFFF
H'0000
H'FFFF
Figure 2.2 Memory Map
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 21 of 682
REJ09B0353-0300
2.4 Register Configuration
2.4.1 Overview
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers.
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
0707015
(SP)
23 0
PC
7
CCR 6543210
IUIHUNZVC
General Registers (ERn)
Control Registers (CR)
Legend:
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Figure 2.3 CPU Registers
Section 2 CPU
Rev.3.00 Mar. 26, 2007 Page 22 of 682
REJ09B0353-0300
2.4.2 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (E R0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, prov iding a maximum sixteen 8-bit
registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
ER0 to ER7
E registers
(extended registers)
E0 to E7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
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General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
Free area
Stack area
SP (ER7)
Figure 2.5 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC) and the 8-bit condition code register
(CCR).
Program Counter (PC)
This 24-b it coun ter indicates th e address of the next instruction the CPU will execute. Th e length
of all CPU instru ctions is 2 bytes (one word) or a multiple o f 2 bytes, so the least significan t PC
bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.
Condition Code Register (CCR)
This 8-bit r egister contains internal CPU statu s in f ormation, including the interrupt mask bit (I)
and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by sof twar e u sin g the
LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask
bit. For details see section 5, In terrupt Controller.
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Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is ex ecuted, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L in struction is executed, th e H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instru ctions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to sto r e the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operatio ns can be performe d on CCR by the LD C,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and
UI bits, see section 5, Interrupt Controller.
2.4.4 Initial CPU Register Values
In reset exception handling, PC is initialized to a value loaded from th e vector table, an d the I b it
in CCR is set to 1 . The other CCR bits and the gen eral registers are not initialized. In particular,
the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an
MOV.L instruction executed immediately after a reset.
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2.5 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.5.1 General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
7
RnH
RnL
RnH
RnL
RnH
RnL
1-bit data
1-bit data
4-bit BCD data
4-bit BCD data
Byte data
Byte data
6543210
70
Don't care
76543210
70
Don't care
Don't care
70
43
Lower digitUpper digit
743
Lower digitUpper digit
Don't care 0
70
Don't care
MSB LSB
Don't care 70
MSB LSB
Data Type Data Format
General
Register
Legend:
RnH:
RnL: General register RH
General register RL
Figure 2.6 General Register Data Formats
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Rn
En
ERn
Word data
Word data
Longword data
General
RegisterData Type Data Format
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
Legend:
ERn:
En:
Rn:
MSB:
LSB:
General register
General register E
General register R
Most significant bit
Least significant bit
Figure 2.7 General Register Data Formats
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2.5.2 Memory Data Formats
Figure 2.8 shows the data fo rmats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
76543210Address L
Address L
LSB
MSB
MSB
LSB
70
MSB LSB
1-bit data
Byte data
Word data
Longword data
AddressData Type Data Format
Address 2m
Address 2m + 1
Address 2n
Address 2n + 1
Address 2n + 2
Address 2n + 3
Figure 2.8 Memory Data Formats
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
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2.6 Instruction Set
2.6.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions, which are classified as shown in table 2.1.
Table 2.1 Instruction Classification
Function Instruction Types
Data transfer MOV, PUSH*1, POP*1, MOVTPE*2, MOVFPE*23
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,
MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU 18
Logic operations AND, OR, XOR, NOT 4
Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,
BIXOR, BLD, BILD, BST, BIST 14
Branch Bcc*3, JMP, BSR, JSR, RTS 5
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9
Block data transfer EEPMOV 1
Total 62 types
Notes: 1. POP.W Rn is iden tical to MOV.W @SP+, Rn.
PUSH.W Rn is identical to MOV.W Rn, @–SP.
POP.L ERn is identical to MOV.L @SP+, Rn.
PUSH.L ERn is identical to MOV.L Rn, @–SP.
2. These instructions are not available on the H8/3039 Group.
3. Bcc is a generic branching instruction.
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2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the instructions available in the H8/300H CPU.
Table 2.2 Instructions and Addressing Modes
Addressing Modes
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:24, ERn)
@ERn+/@–ERn
@aa:8
@aa:16
@aa:24
@(d:8, PC)
@(d:16,PC)
@@aa:8
Implied
MOV BWL BWL BWL BWL BWL BWL B BWL BWL ————
POP, PUSH ————————————WL
Data
transfer
MOVFPE,
MOVTPE ———————B—————
ADD, CMP BWL BWL ———————————
SUB WL BWL ———————————
ADDX, SUBX B B ———————————
ADDS, SUBS — L ———————————
INC, DEC —BWL ———————————
DAA, DAS — B ———————————
MULXU,
MULXS,
DIVXU, DIVXS
—BW ———————————
NEG —BWL ———————————
Arithmetic
operations
EXTU, EXTS —WL ———————————
AND, OR,
XOR BWL BWL ———————————Logic
operations
NOT —BWL ———————————
Shift ins tructions —BWL ———————————
Bit manipulation —BB———B——————
Branch Bcc, BSR ————————— ——
JMP, JSR —— ————— —— —
RTS ————————————
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Addressing Modes
Function Instruction
#xx
Rn
@ERn
@(d:16,ERn)
@(d:24, ERn)
@ERn+/@–ERn
@aa:8
@aa:16
@aa:24
@(d:8, PC)
@(d:16,PC)
@@aa:8
Implied
TRAPA ————————————System
control RTE ————————————
SLEEP ————————————
LDC B BWWWW—WW————
STC —BWWWW—WW————
ANDC, ORC,
XORC B————————————
NOP ————————————
Block data transfer ————————————BW
Legend:
B: Byte
W: Word
L: Longword
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2.6.3 Tables of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation
used in these tab les is d e f ined as follows.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition cod e regist er
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
–Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Exclusi ve log ical OR
→Move
¬NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
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Table 2.3 Data Transfer Instructions
Instruction Size*Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in the H8/3039 Group.
MOVTPE B Rs → (EAs)
Cannot be used in the H8/3039 Group.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is iden tical to
MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @ –SP. Similarly, PUSH.L ERn is identical to MOV.L ERn,
@–SP.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4 Arithmetic Operation Instructions
Instruction Size*Function
ADD,
SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from data in a general register. Use the SUBX or
ADD instruction.)
ADDX,
SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on data in two general
registers, or on immediate data and data in a general register.
INC,
DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decrem en ted by 1 only.)
ADDS,
SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA,
DAS B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Instruction Size*Function
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immed iate data, and sets CCR accordin g to the result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by padding with zeros.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.5 Logic Operation Instructions
Instruction Size*Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one's complement of general register contents.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Instruction Size*Function
SHAL,
SHAR B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL,
SHLR B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL,
ROTR B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL,
ROTXR B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry bit.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.7 Bit Mani pulation In st ructions
Instruction Size*Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The
bit number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower 3 bits of a
general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Instruction Size*Function
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-O Rs the carry flag with a specif ied bit in a genera l regist er or
memory operand and stores the result in the carry flag.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: *Size refers to the operand size.
B: Byte
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Table 2.8 Branching Instruct ions
Instruction Size Function
Bcc —Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
Bcc (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP —Branches unconditionally to a specified address
BSR —Branches to a subroutine at a specified address
JSR —Branches to a subroutine at a specified address
RTS —Returns from a subroutine
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Table 2.9 System Control Instructions
Instruction Size*Function
TRAPA —Starts trap-instruction exception handling
RTE —Returns from an exception-handling routine
SLEEP —Causes a transition to the power-down state
LDC B/W (EAs) → CCR
Moves the sour ce opera nd cont ents to the condition code register. The
condition code register size is one byte, but in transfer from memory, data
is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination locati on. The condition code
register size is one byte, but in transfer to memory, data is written by word
access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ # IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically ex clu si ve-O Rs t he cond iti on code register with immediate data.
NOP —PC + 2 → PC
Only increments the program counter.
Note: *Size refers to the operand size.
B: Byte
W: Word
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Table 2.10 Block Transfer Instruction
Instruction Size Function
EEPMOV.B —if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general registers
R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5: Starting source address
ER6: Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.4 Basic Instruction Formats
The H8/300H instr uctions consist of 2-byte (1-word) units. An instr uction consists of an oper ation
field (OP field), a register f ield ( r field) , an eff ectiv e addr ess extension (EA field), and a condition
field (cc).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the
first 8 bits are 0 (H'00).
Condition Field: Specifies the branch ing condition of Bcc in structions.
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Figure 2.9 shows examples of instruction formats.
op NOP, RTS, etc.
op rn rm
op rn rm
EA (disp)
Operation field only
ADD.B Rn, Rm, etc.
Operation field and register fields
MOV.B @(d:16, Rn), Rm
Operation field, register fields, and effective address extension
BRA d:8
Operation field, effective address extension, and condition field
op cc EA (disp)
Figure 2.9 Instruction Formats
2.6.5 Notes on Use of Bit Manipulation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the
byte, then write the byte back. Care is required when these instructions are used to access registers
with write-only bits, or to access ports.
The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling
routine, for example, if it is kno wn that the flag is set to 1, it is no t necessary to read the flag ahead
of time.
2.7 Addressing Modes and Effective Address Calculation
2.7.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer instructions can use all addressing modes except program-
counter relative and memory indirect. Bit manipulation instructions use register direct, register
indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET,
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BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit
number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16, ERn)/@d:24, ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement @Ern+
@–ERn
5 Absolute addres s @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8, PC)/@(d:16, PC)
8 Memory indirect @@aa:8
1. Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2. Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand.
3. Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an
address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the
sum specify the address of a memory operand. A 16-bit displacement is sign-extended when
added.
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4. Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrem ent—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instru ction code, and the lower 24 bits of the result become the address of a m e mor y
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or long word access, the resulting
register value should be ev en.
5. Absolute Address—@aa:8, @aa:16, or @aa:24
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute
address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16- bit absolute address the
upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space.
Table 2.12 indicates the accessible address ranges.
Table 2.12 Absolute Address Acce ss Ranges
Absolute
Address 1-Mbyte Modes 16-Mbyte Modes
8 bits (@aa:8) H'FFF00 to H'FFFFF
(1,048,320 to 1,048,575) H'FFFF00 to H'FFFFFF
(16,776,960 to 16,777,215)
16 bits (@aa:16) H'00000 to H'07FFF,
H'F8000 to H'FFFFF
(0 to 32,767, 1,015,808 to 1,048,575)
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
(0 to 32,767, 16,744,448 to 16,777,215)
24 bits (@aa:24) H'00000 to H'FFFFF
(0 to 1,048,575) H'000000 to H'FFFFFF
(0 to 16,777,215)
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6. Immediate—#xx:8, #xx:16, or #xx:32
The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction cod e s of some bit manipulation instructions co ntain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7. Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended to 24 bits and added to the 24-bit PC contents to generate a
24-bit branch address. The PC value to which the displacement is added is the address of th e first
byte of the next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64
words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The
resulting value should be an even number.
8. Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute
address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF).
Note that the first part of this range is also the exception vector area. For further details see section
5, Interrupt Controller.
Specified by @aa:8 Reserved
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
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When a word-size or longword-size memory operand is specified, or when a branch address is
specified, if the specified memory address is odd, the least significant bit is regarded as 0. The
accessed data or instruction code therefore begins at the preceding address. See section 2.5.2,
Memory Data Formats.
2.7.2 Effective Address Calculation
Table 2.13 explains how an effective address is calculated in each addressing mode. In th e
1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to
generate a 20-bit effective address.
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Table 2.13 Effective Address Calculation
Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Register direct (Rn)
1Operand is general
register contents
op rm rn
Register indirect (@ERn)
2
op r
General register contents
31 0 23 0
Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
3
op r
General register contents
31 0
23 0
disp Sign extension disp
Register indirect with post-increment
or pre-decrement
4
General register contents
31 0 23 0
1, 2, or 4
op r
General register contents
31 0
23 0
1, 2, or 4
op r
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Register indirect with post-increment
@ERn+
Register indirect with pre-decrement
@ÐERn
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Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Absolute address
@aa:8
5
op
Program-counter relative
@(d:8, PC) or @(d:16, PC)
70
23 0
abs
23 087
@aa:16
op abs
23 016 15
H'FFFF
Sign
extension
@aa:24
op
23 0
abs
Immediate
#xx:8, #xx:16, or #xx:32
6Operand is immediate data
op disp
23 0
PC contents
disp
op IMM
Sign
extension
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Addressing Mode and
Instruction FormatNo. Effective Address Calculation Effective Address
Memory indirect
@@aa:8
8
op
23 0
abs 23 087
H'0000
Memory contents
31 0
abs
Legend:
r, rm, rn:
op:
disp:
IMM:
abs:
Register field
Operation field
Displacement
Immediate data
Absolute address
Advanced mode
op
23 0
abs 23 087
H'0000
15 0
abs
16 15
Normal mode
H'00Memory contents
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2.8 Processing States
2.8.1 Overview
The H8/300H CPU has four processing states: the program execution state, exception-hand ling
state, power-down state, and reset state. The power-down state includes sleep mode, software
standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure
2.13 indicates the state transitions.
Processing states Program execution state
Reset state
Power-down state
The CPU executes program instructions in sequence
A transient state in which the CPU executes a hardware sequence
(saving PC and CCR, fetching a vector, etc.) in response to a reset,
interrupt, or other exception
The CPU and all on-chip supporting modules are initialized and halted
The CPU is halted to conserve power
Sleep mode
Software standby mode
Hardware standby mode
Exception-handling state
Figure 2.11 Processing States
2.8.2 Program Execution State
In this state the CPU executes program instructions in normal sequence.
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2.8.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from
the exception vector table and branches to that address. In interrupt and trap exception hand ling
the CPU references the stack pointer (ER7) and saves the program counter and condition code
register.
Types of Exception Handling and Their Priority: Exception handling is performed for resets,
interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their
priority. Trap instruction exceptions are accepted at all times in the program execution state.
Table 2.14 Exception Handling Ty pe s and Priority
Priority Type of Exception Detection Timing Start of Exception Handling
High Reset Synchronized with
clock Exception handling starts
immediately when RES changes
from low to high
Interrupt End of instruction
execution or end of
exception handling*
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Low
Trap instruction When TRAPA instruction
is exec uted Exception handling starts when
a trap (TRAPA) instruction is
executed
Note: *Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,
or immediately after reset exception handling.
Figure 2.12 classifies the exception sources. For further details about exception sources, vector
numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt
Controller.
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Exception
sources
Reset
Interrupt
Trap instruction
External interrupts
Internal interrupts (from on-chip supporting modules)
Figure 2.12 Classification of Exception Sources
Exception-handling state
Program execution state
Sleep mode
Software standby mode
Power-down state
End of
exception
handling
Exception
Interrupt
SLEEP
instruction
with SSBY = 0
SLEEP instruction
with SSBY = 1
NMI, IRQ , IRQ ,
or IRQ interrupt
STBY = high, RES = low
RES = high
01
2
Notes: 1.
2.
From any state except hardware standby mode, a transition to the reset state occurs
whenever goes low.
From any state, a transition to hardware standby mode occurs when goes low.
RES
STBY
Hardware standby mode*
2
Reset state*
1
Figure 2.13 State Transitions
2.8.4 Exception-Handling Sequences
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
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including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSC R) is set to 1, the CPU set s th is set to 1, the CPU set s the I bit in the condition code
register to 1 . If th e UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the cond ition
code register to 1. Then the CPU fetches a start address from the exception vector table and
execution branches to that address.
Figure 2.14 shows the stack after the exception-handling sequence.
SPÐ4
SPÐ3
SPÐ2
SPÐ1
SP (ER7)
Before exception
handling starts
SP (ER7)
SP+1
SP+2
SP+3
SP+4
After exception
handling ends
Stack area
CCR
PC
Even
address
Pushed on stack
Legend:
CCR:
SP: Condition code register
Stack pointer
Notes: 1.
2.
PC is the address of the first instruction executed after the return from the
exception-handling routine.
Registers must be saved and restored by word access or longword access,
starting at an even address.
Figure 2.14 Stack Structure after Exception Handling
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2.8.5 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. The I
bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state.
Reset exception handling starts when the RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details see section 10,
Watchdog Timer.
2.8.6 Power-Down State
In the power-down state the CPU stops operating to conserve power. There are three modes: sleep
mode, software standby mode, and hardware standby mode.
Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the
SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop
immediately after execution of the SLEEP instruction, but the contents of CPU registers are
retained.
Softwa re Standby Mode: A transition to software standby mode is made if the SLEEP
instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and cloc k halt and all
on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long
as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained.
The I/O ports also remain in their existing states.
Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input
goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting
modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are
retained.
For further information see section 17, Power-Down State.
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2.9 Basic Operational Timing
2.9.1 Overview
The H8/300H CPU operates according to the system clock (φ). The interval from one rise of the
system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of
two or three states. The CPU uses different methods to access on-chip memo ry, the on-chip
supporting modules, and the external address space. Access to the external address space can be
controlled by the bus cont roll er.
2.9.2 On-Chip Memory Access Timing
On-chip memory is accessed in two states. The data bus is 16 bits wide , p ermitting both byte an d
word access. Figure 2.15 shows the on-ch ip memory access cycle. Figure 2.16 indicates the pin
states.
T state
Bus cycle
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
φ
1T state
2
Read data
Address
Write data
Figure 2.15 On-Chip Memory Access Cycle
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T
, RD, WRAS
φ
1T2
Address bus
D7 to D0
High
Address
High impedance
Figure 2.16 Pin States during On-Chip Memory Access
2.9.3 On-Chip Supporting Module Acces s Timing
The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access
timing. Figure 2.18 indicates the pin states.
Internal address bus
Internal read signal
Internal data bus
Internal write signal
Address
Internal data bus
φ
T state
Bus cycle
1T state
2T state
3
Read
access
Write
access Write data
Read data
Figure 2.17 Access Cycle for On-Chip Supporting Modules
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Address
T
, RD, WR AS
φ
1
T
2
Address bus
D
7
to D
0
High
High impedance
T
3
Figure 2.1 8 Pin States during Access to O n-Chip Supporting Modules
2.9.4 Access to External Address Space
The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings
determine whether each area accessed in two or three states. For details see section 6, Bus
Controller.
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Section 3 MCU Operati ng Mo des
3.1 Overview
3.1.1 Operating Mode Selectio n
The H8/3039 Group has five operating modes (modes 1, 3, 5 to7) that are selected by the mode
pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines expanded mode or
single-chip mode.
Table 3.1 Operating Mo de Select ion
Mode Pins Description
Operating
Mode MD2MD1MD0Address Space Initial Bus
Mode*1On-Chip
ROM On-Chip
RAM
— 000 — — — —
Mode 1 0 0 1 Expanded mode 8 bits Disabled Enabled*1
Mode 2 0 1 0 — — — —
Mode 3 0 1 1 Expanded mode 8 bits Disabled Enabled*1
Mode 4 1 0 0 — — — —
Mode 5 1 0 1 Expanded mode 8 bits Enabled Enabled*1
Mode 6 1 1 0 Single-chip normal mode — Enabled Enabled*2
Mode 7 1 1 1 Single-chip advanced mode — Enabled Enabled*2
Notes: 1. If the RAM enable bit (RAME) in the system control register (SYSCR) is cleared to 0,
these addresses become external addresses.
2. In mode 6 and 7, clearing bit RAME in SYSCR to 0 and reading the on-chip RAM
always return H'FF, and write access is ignored. For details, see section 14.3,
Operation.
For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbytes.
Modes 1 and 3 are on-chip ROM disable expanded modes capable of accessing external memory
and peripheral devices.
Mode 1 supports a maximum address space of 1 Mbyte.
Mode 3 supports a maximum address space of 16 Mbytes.
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Mode 5 is externally expanded mode that enables access to external memory and peripheral
devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space
of 1 Mbyte.
Modes 6 and 7 are single-chip modes that op erate using the on-chip ROM, RAM, and registers.
All I/O ports are available. Mode 6 is a normal mode with 64-kbyte address space. Mode 7 is an
advanced mode with a maximum address space of 1 Mbyte.
The H8/3039 Group can be used only in modes 1, 3, or 5 to 7. The inputs at the mode pins must
select one of these seven modes. The inputs at the mode pins must not be changed during
operation.
3.1.2 Register Configuration
The H8/3039 Group has a mode control register (MDCR) that indicates the inputs at the mode
pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers.
Table 3.2 Registers
Address*Name Abbreviation R/W Initial Value
H'FFF1 Mode control register MDCR R Undetermined
H'FFF2 System control register SYSCR R/W H'0B
Note: *The lower 16 bits of the address are indicated.
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3.2 Mode Control Register (MDCR)
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3039
Group.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—
R
2
MDS2
—
R
1
MDS1
—
R
***
Mode select 2 to 0
Bits indicating the current
operating mode
Reserved bits
Note: Determined by pins MD to MD .
20
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins
MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS1 and
MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latch ed when MDCR is read.
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3.3 System Control Register (SYSCR)
SYSCR is an 8-bit register that controls the operation of the H8/3039 Group.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
Enables transition to software standby mode
User bit enable
Selects whether to use UI bit in CCR
as a user bit or an interrupt mask bit
NMI edge select
Selects the valid edge
of the NMI input
Reserved bit
RAM enable
Enables or
disables
on-chip RAM
Standby timer select 2 to 0
These bits select the waiting time at
recovery from software standby mode
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. (For further
information abou t software standby mode see section 17, Power-Down State.)
When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear
this bit, write 0.
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sl eep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4 —St andby Timer Select (STS2 to STS0) : These bits select the length of time the CPU
and on-chip supporting modules wait for the internal clock oscillator to settle when software
standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at
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least 7 ms at the system clock rate. For fur th e r inform ation about waiting tim e selection, see
section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Waiting time = 8,192 states (Initial value)
0 0 1 Waiting time = 16,384 states
0 1 0 Waiting time = 32,768 states
0 1 1 Waiting time = 65,536 states
1 0 0 Waiting time = 131,072 states
1 0 1 Waiting time = 1,024 states
11 —Illegal sett ing
Bit 3—Use r Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a
user bit or an inter rup t m a sk bit.
Bit 3
UE Description
0 UI bit in CCR is used as an interrupt mask bit
1 UI bit in CCR is used as a user bit (Initial value)
Bit 2—NMI Edge Sele ct (NMIEG) : Selects the valid ed ge of the NMI input.
Bit 2
NMIEG Description
0 An interrupt is requested at the falling edge of NMI (Initial value)
1 An interrupt is requested at the rising edge of NMI
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized by th e rising edge of the RES signal. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
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3.4 Operating Mode Descriptions
3.4.1 Mode 1
Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space. Th e initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.2 Mode 3
Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a
maximum 16-Mbyte address space. The initial b us mode after a reset is 8 bits, with 8-bit access to
all areas. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release contr ol register
(BRCR). (In this mode A20 is always used for address output.)
3.4.3 Mode 5
Ports 1, 2, and 5 can function as address pins A19 to A0, permitting access to a maximum 1-Mbyte
address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus,
the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set
to 1. The address b us width can be selected freely by setting DDR of ports 1, 2, and 5. The initial
bus mode after a reset is 8 bits, with 8-bit access to all areas.
3.4.4 Mode 6
This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available.
Mode 6 is a normal mode with 64-kbyte address space.
3.4.5 Mode 7
This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip
ROM, RAM, and registers. All I/O ports are available.
Note: The H8/3039 Group cannot be used in mode 2 and 4.
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3.5 Pin Functions in Each Operating Mode
The pin functions of po rts 1 to 3, port 5 and port A vary depending on the operating mode. Table
3.3 indicates their functions in each operating mode.
Table 3.3 Pin Functions in Each Mode
Port Mode 1 Mode 2*1Mode 3 Mode 4*1Mode 5 Mode 6 Mode 7
Port 1 A7 to A0— A7 to A0—P17 to P10*2P17 to P10P17 to P10
Port 2 A15 to A8— A15 to A8—P27 to P20*2P27 to P20P27 to P20
Port 3 D7 to D0— D7 to D0— D7 to D0P37 to P30P37 to P30
Port 5 A19 to A16 — A19 to A16 —P53 to P50*2P53 to P50P53 to P50
Port A PA7 to PA4—PA6 to PA4*3, A20 —PA7 to PA4PA7 to PA4PA7 to PA4
Notes: 1. H8/3039 Group cannot be used in these modes.
2. Initial state. These pins become address output pins when the corresponding bits in the
data direction registers (P1DDR, P2DDR, P5DDR) are set to 1.
3. Initial state A20 is always an address output pin. PA6 to PA4 are switched over to A23 to
A21 output by writing 0 in bits 7 to 5 of ADRCR.
3.6 Memory Map in Each Operating Mode
Figure 3.1 shows a memory map of the H8/3039. Figure 3.2 shows a memory map of the H8/3038.
Figure 3.3 shows a memory map of the H8/3037. Figure 3.4 shows a memory map of the H8/3036.
The address space is divided into eight areas.
Modes 1, 3 and 5 are the 8-bit bus mode.
The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte
modes (modes 1, 5, and 7) and 16-Mbyte mode (mode 3), and 64-kbyte mode (mode 6). The
address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and
@aa:16) also differs.
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H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM*
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Note: * External addresses can be accessed by disabling on-chip RAM.
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM*
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FF8000
H'FFEF0F
H'FFEF10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Figure 3.1 H8/3039 Memory Map in Each Operating Mode (1)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 65 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled) Mode 7
(single-chip advanced mode)
Mode 6
(single-chip normal mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM*
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'FEF0F
H'FEF10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Vector area
On-chip ROM
On-chip RAM
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FEF10
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'1FFFF
H'F8000
Note: * External addresses can be accessed by disabling on-chip RAM.
On-chip ROM
On-chip RAM
On-chip I/O
registers
H'0000
H'00FF
H'FF1C
H'FFFF
H'F70F
H'F710
8-bit memory-indirect
branch addresses
8-bit absolute addresses
F'FF00
F'FF0F
Vector area
Figure 3.1 H8/3039 Memory Map in Each Operating Mode (2)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 66 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FF8000
H'FFEF10
H'FFF70F
H'FFF710
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.2 H8/3038 Memory Map in Each Operating Mode (1)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 67 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
H'08000
H'0FFFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled) Mode 7
(single-chip advanced mode)
Mode 6
(single-chip normal mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM*2
Reserved*1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'DFFFF
H'E0000
H'FEF10
H'FF70F
H'FF710
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Vector area
On-chip ROM
On-chip RAM
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FF710
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'0FFFF
H'07FFF
H'F8000
Notes:
Reserved*1
1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
H'0000
H'00FF
H'F70F
H'F710
8-bit memory-indirect
branch addresses
8-bit absolute addresses
H'FF00
H'FF0F
On-chip
I/O registers
Vector area
H'FFFF
H'FF1C
On-chip ROM
On-chip RAM
Figure 3.2 H8/3038 Memory Map in Each Operating Mode (2)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 68 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'FEF10
H'FFB0F
H'FFB10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FF8000
H'FFEF10
H'FFFB0F
H'FFFB10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.3 H8/3037 Memory Map in Each Operating Mode (1)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 69 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
H'08000
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled) Mode 7
(single-chip advanced mode)
Mode 6
(single-chip normal mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM*2
Reserved*1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'DFFFF
H'E0000
H'FEF10
H'FFB0F
H'FFB10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Vector area
On-chip ROM
On-chip RAM
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FFB10
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'07FFF
H'F8000
Notes:
Reserved*1
1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
H'0000
H'00FF
H'7FFF
H'FB10
8-bit memory-indirect
branch addresses
8-bit absolute addresses
Vector area
H'FF00
H'FF0F
On-chip ROM
On-chip
RAM
H'FF1C
H'FFFF
On-chip I/O
registers
Figure 3.3 H8/3037 Memory Map in Each Operating Mode (2)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 70 of 682
REJ09B0353-0300
H'00000
H'000FF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 1
(1-Mbyte expanded modes with
on-chip ROM disabled)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'FEF10
H'FFD0F
H'FFD10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
Mode 3
(16-Mbyte expanded modes with
on-chip ROM disabled)
H'000000
H'0000FF
H'007FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
H'1FFFFF
H'200000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External
address
space
Vector area
On-chip RAM*
2
Reserved*
1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FF8000
H'FFEF10
H'FFFD0F
H'FFFD10
H'FFFF00
H'FFFF0F
H'FFFF10
H'FFFF1B
H'FFFF1C
H'FFFFFF
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
Notes: 1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
Figure 3.4 H8/3036 Memory Map in Each Operating Mode (1)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 71 of 682
REJ09B0353-0300
H'00000
H'000FF
H'03FFF
H'07FFF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Mode 5
(1-Mbyte expanded mode with
on-chip ROM enabled) Mode 7
(single-chip advanced mode)
Mode 6
(single-chip normal mode)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
External address
space
Vector area
On-chip ROM
On-chip RAM*2
Reserved*1
External
address
space
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'F8000
H'DFFFF
H'E0000
H'FEF10
H'FFD0F
H'FFD10
H'FFF00
H'FFF0F
H'FFF10
H'FFF1B
H'FFF1C
H'FFFFF
H'00000
H'000FF
8-bit memory-indirect
branch addresses
16-bit absolute
addresses (first half)
Vector area
On-chip ROM
On-chip RAM
On-chip I/O
registers
8-bit absolute addresses
16-bit absolute addresses
(second half)
H'FFD10
H'FFF00
H'FFF0F
H'FFF1C
H'FFFFF
H'03FFF
H'F8000
Notes:
Reserved*1
1. Do not access the reserved area.
2. External addresses can be accessed by disabling on-chip RAM.
H'0000
H'00FF
H'3FFF
H'FD10
F'FF00
F'FF0F
H'FF1C
H'FFFF
8-bit memory-indirect
branch addresses
8-bit absolute addresses
Vector area
On-chip ROM
On-chip RAM
On-chip I/O
registers
Figure 3.4 H8/3036 Memory Map in Each Operating Mode (2)
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 72 of 682
REJ09B0353-0300
3.7 Restrictions on Use of Mode 6
In mode 6 (single-chip normal mode), on-chip ROM area data is undefined if address H'10000 or
above (64 kbytes or above) is accessed, and therefore instruction code fetch and data read
operations may not always be performed normally.
However, there is no problem with address H'10000 and above if th e lower 16-bit address is an
on-chip RAM (H'F710 to H'FF0F) or internal I/O register (H'FF1C to H'FFFF) address.
Table 3.4 shows the restrictions concerning each addressing mode.
Table 3.4 Access Restrictions in Mode 6 (Single-Chip Normal Mode)
Conditions
Addressing Mode Restricted Item Address Range Operation Restricti o n
Register di rect (Rn) No problem
Register i ndirec t
(@ERn) Contents of ERn H' 00010000 or
above, with lower
16 bits in range
H'0000 to H'F710
Read data is
undefined.
Writes are
invalid.
Set upper 16 bits of ERn
to H'0000; or, write
same data as in
H'00000–H'0FFFF to
H'10000–H'1FFFF in
on-chip ROM.
Register i ndirec t with
displacement
(@(d:16,ERn),
@(d:16,ERn))
Value of ERn
contents plus
displacement
Register i ndirec t with
post-increment
(@ERn+)
Register i ndirec t with
pre-decrement
(@ERn-)
Value of ERn
contents
increment ed (or
decremented) by
1, 2, or 4
Absolute address
(@aa:8) No problem
Absolute address
(@aa:16) Value of @aa
sign-extended to
24 bits
H'010000 or
above, with lower
16 bits in range
H'0000 to H'F710
Read data is
undefined.
Writes are
invalid.
Do not specify H'8000
or above as absolute
address; or, write sam e
data as in H'00000–
H'0FFFF to H'10000–
H'1FFFF in on-chip
ROM.
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 73 of 682
REJ09B0353-0300
Conditions
Addressing Mode Restricted Item Address Range Operation Restricti o n
Absolute address
(@aa:24) Value of @aa H' 010000 or
above, with lower
16 bits in range
H'0000 to H'F710
Read data is
undefined.
Writes are
invalid.
Do not access
addresses i n range
shown under conditions;
or, write sam e data as in
H'00000–H'0FFFF to
H'10000–H'1FFFF in
on-chip ROM.
Immediate No problem
Program-counter
relative
(@(d:8,PC),
@(d:16,PC))
Value of PC plus
displacement H' 010000 or
above, with lower
16 bits in range
H'0000 to H'F710
Does not
operate
normally
since
instruction
code is
undefined.
Do not access
addresses i n range
shown under conditions;
or, write sam e data as in
H'00000–H'0FFFF to
H'10000–H'1FFFF in
on-chip ROM.
Memory indirect
(@@aa:8) No problem
Section 3 MCU Operating Modes
Rev.3.00 Mar. 26, 2007 Page 74 of 682
REJ09B0353-0300
Section 4 Exception Handling
Rev.3.00 Mar. 26, 2007 Page 75 of 682
REJ09B0353-0300
Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are
accepted at all times in the program execution state.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the
RES pin
Interrupt Interrupt requests are handled when execution of the
current instruction or handling of the current exception
is completed
Low Trap instruct ion (TRAPA) Started by execut ion of a trap instruc tio n (TRAPA)
4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows.
1. The program counter (PC) and condition code register (CCR) are pushed onto the stack.
2. The CCR interrupt ma sk bit is set to 1.
3. A vector address corresponding to the exception source is generated, and program execution
starts from the address indicated in the vector address.
For a reset exception, steps 2 and 3 above are carried out.
Section 4 Exception Handling
Rev.3.00 Mar. 26, 2007 Page 76 of 682
REJ09B0353-0300
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4.1. Different vectors are assigned to
different exception sources. Table 4.2 lists the exception sources and their vector addresses.
Exception
sources
• Reset
• Interrupts
• Trap instruction
External interrupts:
Internal interrupts:
NMI, IRQ0, IRQ1, IRQ4, IRQ5
25 interrupts from on-chip
supporting modules
Figure 4.1 Exception Sources
Section 4 Exception Handling
Rev.3.00 Mar. 26, 2007 Page 77 of 682
REJ09B0353-0300
Table 4.2 Exception Vector Table
Vector Address*1
Exception Source Vector Number Normal Mode Advanced Mode
Reset 0 H'0000 to H'0001 H'0000 to H'0003
Reserved for system use 1 H'0002 to H'0003 H'0004 to H'0007
2 H'0004 to H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'0009 H'0010 to H'0013
5 H'000A to H'000B H'0014 to H'0017
6 H'000C to H'000D H'0018 to H'001B
External interrupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap instruction (4 sources) 8 H'0010 to H'0011 H'0020 to H'0023
9 H'0012 to H'0013 H'0024 to H'0027
10 H'0014 to H'0015 H'0028 to H'002B
11 H'0016 to H'0017 H'002C to H'002F
External interrupt IRQ012 H'0018 to H'0019 H'0030 to H'0033
IRQ113 H'001A to H'001B H'0034 to H'0037
Reserved for system use 14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interrupt IRQ416 H'0020 to H'0021 H'0040 to H'0043
IRQ517 H'0022 to H'0023 H'0044 to H'0047
Reserved for system use 18 H'0024 to H'0025 H'0048 to H'004B
19 H'0026 to H'0027 H'004C to H'004F
Internal interrupts*220
to
60
H'0028 to H'0029
to
H'0078 to H'0079
H'0050 to H'0053
to
H'00F0 to H'00F3
Notes: 1. Lower 16 bits of the address.
2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table.
Section 4 Exception Handling
Rev.3.00 Mar. 26, 2007 Page 78 of 682
REJ09B0353-0300
4.2 Reset
4.2.1 Overview
A reset is the highest-prior ity exception. When the RES pin goes low, all processing halts and the
H8/3039 Group enters the reset state. A reset initializes the internal state of the CPU and the
registers of the on-chip supporting modules. Reset exception handling begins when the RES pin
changes from low to high.
The chip can also be reset by overflow of the watchdog timer. For details see section 10,
Watchdog Timer.
4.2.2 Reset Sequence
The H8/3039 Group enters the reset state when the RES pin goes low.
To ensure th at the chip is r eset, hold the RES pin low for at least 20 ms at power-up. To reset the
chip during operation, hold the RES pin low for at least 10 system clock (φ) cycles. When using
the flash memory version, hold at "Low" level for a least 1usec. See appendix D.2, Pin States at
Reset, for the states of the pins in the reset state.
When the RES pin goes high after being held low for the necessary time, the H8/3039 Group chip
starts reset exception hand ling as follows.
• The internal state of the CPU and the registers of th e on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
• The contents of the reset vector address (H'0000 to H'0003 in advanced mode) are read, and
program execution starts from the address indicated in the vector address.
Figure 4.2 shows the reset sequence in modes 5 and 7.
Section 4 Exception Handling
Rev.3.00 Mar. 26, 2007 Page 79 of 682
REJ09B0353-0300
(2) (4) (6)
(5)(3)(1)
φ
RES
Internal
address bus
Internal read
signal
Internal write
signal
Internal data bus
(16-bit width)
Vector fetch Internal
processing
Prefetch of
first program
instruction
(1), (3)
(2), (4)
(5)
(6)
Address of reset vector: (1) = H'000000, (3) = H'000002
Start address (contents of reset vector)
Start address
First instruction of program
Figure 4.2 Reset Sequence (Modes 5 and 7)
Section 4 Exception Handling
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4.2.3 Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC an d CCR
will not be saved correctly, leading to a program crash. To prevent this, all interrupt req uests,
including NMI, are disabled immediately after a reset. The first instruction of the program is
always executed immediately after the reset state en ds. This instruction should initialize the stack
pointer (example: MOV.L #xx:32, SP).
4.3 Interrupts
Interrupt exception handling can be requested by five external sources (NMI, IRQ 0, IRQ1, IRQ4,
IRQ5) and 25 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt
sources and indicates the number of interrupts of each type.
The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit
integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each
interrupt source has a separate vector address.
NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the
interrup t controller. The interrupt controller can assig n interrupts other than NMI to two priority
levels, and arbitrate between simultaneous interrupts. In terru pt priorities are assigne d in interrupt
priority registers A and B (IPRA and IPRB) in the interrupt controller.
For details on interrupts see section 5, Interrupt Controller.
Interrupts
External interrupts
Internal interrupts
NMI (1)
IRQ0, IRQ1, IRQ4, IRQ5 (4)
WDT* (1)
ITU (15)
SCI (8)
A/D converter (1)
Notes: Numbers in parentheses are the number of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates
an interrupt request at every counter overflow.
Figure 4.3 Interrupt Sources and Number of Interrupts
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4.4 Trap Instruction
Trap instruction exception handling star ts wh en a TRAPA instruction is executed. If the UE bit is
set to 1 in the system control register (SYSCR), the exception handling seq uence sets the I bit to 1
in CCR. If the UE b it is 0, the I and UI bits ar e both set to 1. The TRAPA instruction fetches a
start address from a vector table entry corresponding to a vector number from 0 to 3, which is
specified in th e instruction code .
4.5 Stack Status after Exception Handling
Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
SP-4
SP-3
SP-2
SP-1
SP (ER7) →
SP (ER7)
SP+1
SP+2
SP+3
SP+4
→
Before exception handling After exception handling
CCR
PC
PC
PC
E
H
LEven address
Save on stack
Legend:
PCE:
PCH:
PCL:
CCR:
SP:
Notes: PC indicates the address of the first instruction that will be executed after return.
Saving and restoring of registers must be conducted at even addresses in word-size
or longword-size units.
1.
2.
Bits 23 to 16 of program counter (PC)
Bits 15 to 8 of program counter (PC)
Bits 7 to 0 of program counter (PC)
Condition code register
Stack pointer
Stack area
Figure 4.4 Stack after Completion of Exception Handling (Advanced Mode)
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4.6 Notes on Stack Usage
When accessing word data or longword data, the H8/3039 Group regards the lowest address bit as
0. The stack should always be accessed by word access or longword access, and the value of the
stack pointer (SP, ER7) should always be kept even. Use the following instructions to save
registers:
PUSH.W Rn (or MOV.W Rn, @–SP)
PUSH.L ERn (or MOV.L ERn, @–SP)
Use the following instructions to restore registers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.5 shows an example of what
happens when the SP value is odd.
TRAPA instruction executed
CCR
Legend:
SP
PC
R1L
PC
SP
SP
MOV. B R1L, @-ER7
SP set to H'FFEFF Data saved above SP CCR contents lost
Condition code register
Program counter
General register R1L
Stack pointer
Note: The diagram illustrates modes 1, 3, and 5.
H'FFEFA
H'FFEFB
H'FFEFC
H'FFEFD
H'FFEFF
CCR:
PC:
R1L:
SP:
Figure 4.5 Operation when SP Value is Odd
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Section 5 Interrupt Controller
5.1 Overview
5.1.1 Features
The interrupt controller has the following features:
• Interrupt p riority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three -level masking by the I and UI bits in the CPU condition code r egi ste r (CCR)
• Independent vect or address es
All interrup ts ar e independently vectored; the interrupt service routine does not hav e to
identify th e interrupt source.
• Five external interrupt pins
NMI has the highe st priority and is always accepted; either the rising or falling edge can be
selected. For each of IRQ0, IRQ1, IRQ4, and IRQ5, sensing of the falling edge or level sensing
can be selected independently.
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5.1.2 Block Diagram
Figure 5.1 shows a block diagram of the interrupt controller.
ISCR IER IPRA, IPRB
.
.
.
OVF
TME
ADI
ADIE
.
.
.
.
.
.
.
CPU
CCR
I
UI
UE
SYSCR
I:
IER:
IPRA:
IPRB:
ISCR:
ISR:
SYSCR:
UE:
UI:
NMI
input
IRQ input IRQ input
section ISR
Interrupt controller
Priority
decision logic
Interrupt
request
Vector
number
Interrupt mask bit
IRQ enable register
Interrupt priority register A
Interrupt priority register B
IRQ sense control register
IRQ status register
System control register
User bit enable
User bit/interrupt mask bit
Legend:
Figure 5.1 Interrupt Controller Block Diagram
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5.1.3 Pin Configuration
Table 5.1 lists th e interrupt pins.
Table 5.1 Interrupt Pins
Name Abbreviation I/O Function
Nonmaskable interrupt NMI Input Nonmaskable interrupt, rising edge or
falling edge selectable
External interrupt
request 5, 4, 1, and 0 IRQ5, IRQ4, and
IRQ1, IRQ0
Input Maskable interrupts, falling edge or level
sensing selectable
5.1.4 Register Configuration
Table 5.2 lists th e r e gisters of the interrupt co ntroller.
Table 5.2 Interrupt Controller Registers
Address*1Name Abbreviation R/W Initial Value
H'FFF2 System control register SYSCR R/W H'0B
H'FFF4 IRQ sense control register ISCR R/W H'00
H'FFF5 IRQ enable register IER R/W H'00
H'FFF6 IRQ status register ISR R/(W)*2H'00
H'FFF8 Interrupt priority register A IPRA R/W H'00
H'FFF9 Interrupt priority register B IPRB R/W H'00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written, to clear flags.
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5.2 Register Descriptions
5.2.1 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the
action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM.
Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register
(SYSCR).
SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
Standby timer
select 2 to 0
User bit enable
Selects whether to use the UI bit in CCR
as a user bit or interrupt mask bit
NMI edge select
Selects the NMI input edge
Reserved bit
RAM enable
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Bit 3—Use r Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an
interrupt mask bit.
Bit 3
UE Description
0 UI bit in CCR is used as interrupt mask bit
1 UI bit in CCR is used as user bit (Initial value)
Bit 2—NMI Edge Sele ct (NMIEG) : Selects the NMI input edge.
Bit 2
NMIEG Description
0 Interrupt is reques ted at falling edge of NMI input (Initial value)
1 Interrupt is reques ted at rising edge of NMI input
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5.2.2 Interrupt Priority Reg isters A a nd B (IPRA, IPRB)
IPRA and IPRB are 8 - bit readable/writab le r e gisters that control interrupt priority.
Interrupt Priority Register A (IPRA)
IPRA is an 8-bit r eadable/writable register in which interrupt priority lev e ls can be set.
Bit
Initial value
Read/Write
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
—
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
0
IPRA0
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
Priority level A7
Selects the priority level of IRQ interrupt requests
Priority level A2
Selects the priority level of
ITU channel 0 interrupt requests
Priority level A3
Selects the priority level of
WDT interrupt requests
Priority level A1
Selects the priority level
of ITU channel 1
interrupt requests
Priority
level A0
Selects the
priority level
of ITU
channel 2
interrupt
requests
Selects the priority level of IRQ1 interrupt requests
Priority level A6
Reserved bit
Selects the priority level of IRQ4 and IRQ5
interrupt requests
Priority level A4
0
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IPRA is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ0 in terrupt requests.
Bit7
IPRA7 Description
0 IRQ0 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ0 interrupt requests have priority level 1 (high priority)
Bit 6—Priority Level A6 (IPRA6): Selects the priority level of IRQ1 in terrupt requests.
Bit6
IPRA6 Description
0 IRQ1 interrupt requests have priority level 0 (low priority) (Initial value)
1 IRQ1 interrupt requests have priority level 1 (high priority)
Bit 5—Reserved bit: This bit can be written and read, but it do es not aff ect interrupt priority.
Bit 4—Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests.
Bit4
IPRA4 Description
0IRQ
4, IRQ5 interrupt requests have priority level 0 (low priority) (Initial value)
1IRQ
4, IRQ5 interrupt requests have priority level 1 (high priority)
Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WTD inter rupt requests.
Bit3
IPRA3 Description
0 WDT interrupt requests have priority level 0 (low priority) (Initial value)
1 WDT interrupt requests have priority level 1 (high priority)
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Bit 2—Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests.
Bit2
IPRA2 Description
0 ITU channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 0 interrupt requests have priority level 1 (high priority)
Bit 1—Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests.
Bit1
IPRA1 Description
0 ITU channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 1 interrupt requests have priority level 1 (high priority)
Bit 0—Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests.
Bit0
IPRA0 Description
0 ITU channel 2 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 2 interrupt requests have priority level 1 (high priority)
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Interrupt Priority Register B (IPRB)
IPRB is an 8-bit readable/writable reg ister in which interrupt priority leve ls can be set.
Bit
Initial value
Read/Write
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
—
0
R/W
4
—
0
R/W
3
IPRB3
0
R/W
0
—
0
R/W
2
IPRB2
0
R/W
1
IPRB1
0
R/W
Priority level B7
Selects the priority level of ITU channel 3 interrupt requests
Priority level B3
Selects the priority level of SCI
channel 0 interrupt requests
Selects the priority level of SCI
channel 1 interrupt requests
Priority level B2
Priority level B1
Selects the priority level
of A/D converter
interrupt request
Reserved bit
Selects the priority level of ITU channel 4 interrupt requests
Priority level B6
Reserved bits
IPRB is initialized to H'00 by a reset and in hardware standby mode.
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Bit 7—P r iority Level B7 (IPRB7) : Selects the prior ity level of ITU channel 3 interrupt requests.
Bit7
IPRB7 Description
0 ITU channel 3 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 3 interrupt requests have priority level 1 (high priority)
Bit 6—P r iority Level B6 (IPRB6) : Selects the prior ity level of ITU channel 4 interrupt requests.
Bit6
IPRB6 Description
0 ITU channel 4 interrupt requests have priority level 0 (low priority) (Initial value)
1 ITU channel 4 interrupt requests have priority level 1 (high priority)
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—P r iority Level B3 (IPRB3) : Selects the prior ity level of SCI channel 0 interrupt requests.
Bit3
IPRB3 Description
0 SCI channel 0 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI channel 0 interrupt requests have priority level 1 (high priority)
Bit 2—P r iority Level B2 (IPRB2) : Selects the priority level of SCI channel 1 interrupt requests.
Bit2
IPRB2 Description
0 SCI channel 1 interrupt requests have priority level 0 (low priority) (Initial value)
1 SCI channel 1 interrupt requests have priority level 1 (high priority)
Bit 1—P r iority Level B1 (IPRB1) : Selects the priority level of A/D converter interrupt requests.
Bit1
IPRB1 Description
0 A/D converter interrupt requests have priority level 0 (low priority) (Initial value)
1 A/D converter interrupt requests have priority level 1 (high priority)
Bit 0—Reserved: This bit cannot be modified and is always read as 0.
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5.2.3 IRQ Status Register (ISR)
ISR is an 8-bit readable/writable register that indicates the status of IRQ0, IRQ1, IRQ4, and IRQ5
interrupt requests.
Bit
Initial value
Read/Write
7
—
0
—
These bits indicate IRQ
5
and IRQ
4
interrupt request status
Note: Only 0 can be written, to clear flags.
*
6
—
0
—
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W)*
3
—
0
—
2
—
0
—
1
IRQ1F
0
R/(W)*
0
IRQ0F
0
R/(W)*
IRQ
5
to IRQ
4
flags These bits indicates IRQ
1
and IRQ
0
interrupt request status
IRQ
1
, IRQ
0
flags
Reserved bits Reserved bits
ISR is initialized to H'00 by a reset and in h a rdware stan dby mode.
Bits 7, 6, 3 and 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 5, 4, 1 and 0—IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F):
These bits indicate the status of IRQ5, IRQ4, IRQ1, and IRQ0 interrupt requests.
Bits 5, 4, 1, and 0
IRQ5F, IRQ4F,
IRQ1F, and IRQ0F Description
0 [Clearing cond iti ons ] (Initial val ue)
• 0 is written in IRQn F after reading the IRQnF flag when IRQnF = 1.
• IRQnSC = 0, IRQn input is high, and interrupt exception handling is
ca rri ed out.
• IRQnSC = 1 and IRQn interrupt exception handling is carried out.
1 [Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5, 4, 1 and 0
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5.2.4 IRQ Enable Register (IER)
IER is an 8-bit readable/writable register that enables or disables IRQ0, IRQ1, IRQ4, and IRQ5
interrupt requests.
Bit
Initial value
Read/Write
7
—
0
R/W
These bits enable or disable
IRQ
5
and IRQ
4
interrupts
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
—
0
R/W
2
—
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
IRQ
5
to IRQ
4
enable These bits enable or disable
IRQ
1
and IRQ
0
interrupts
IRQ
1
to IRQ
0
enable
Reserved bits Reserved bits
IER is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3, and 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 5, 4, 1, and 0—IRQ5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E):
These bits enable or disable IRQ5, IRQ4, IRQ1, IRQ0 interrupts.
Bits 5, 4, 1, and 0
IRQ5E, IRQ4E,
IRQ1E, and IRQ0E Description
0IRQ
5, IRQ4, IRQ1, IRQ0 interrupts are disabled (Initial value)
1IRQ
5, IRQ4, IRQ1, IRQ0 interrupts are enabled
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5.2.5 IRQ Sense Co nt rol Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ5, IRQ4, IRQ1, and IRQ0
Bit
Initial value
Read/Write
7
—
0
R/W
These bits select level sensing or falling-edge
sensing for IRQ
5
and IRQ
4
interrupts
6
—
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
—
0
R/W
2
—
0
R/W
1
IRQ1SC
0
R/W
0
IRQ0SC
0
R/W
IRQ
5
and IRQ
4
sense control
These bits select level sensing or falling-edge
sensing for IRQ
1
and IRQ
0
interrupts
IRQ
1
and IRQ
0
sense control
Reserved bits Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7, 6, 3, and 2—Reserved: These bits are readable/writable and do not affect selection of
level sensing or falling-edg e sensing.
Bits 5, 4, 1, and 0—IRQ5, IRQ4, IRQ1,,and IRQ0 Sense Control ( IRQ5SC, IRQ4SC, IRQ1SC,
IRQ0SC): These bits selects whether interrupts IRQ5, IRQ4, IRQ1, IRQ0 are requested by level
sensing of pins IRQ5, IRQ4, IRQ1, IRQ0 or by falling-edge sensing.
Bits 5, 4, 1, and 0
IRQ5SC, IRQ4SC,
IRQ1SC, IRQ0SC Description
0 Interrupts are requested when IRQ5, IRQ4, IRQ1, IRQ0 inputs are low
(Initial value)
1 Interrupts are requested by falling-edge input at IRQ5, IRQ4, IRQ1, IRQ0
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5.3 Interrupt Sources
The interrupt sour ces include external interrupts (NMI, IRQ5, IRQ4, IRQ1 and IRQ0) and 25
internal interrupts.
5.3.1 External Interrupts
There are five external interrupts: NMI, and IRQ5, IRQ4, IRQ1, and IRQ0. Of these, NMI, IRQ0,
IRQ1, can be used to exit software standby mode.
NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the
I and UI bits in CCR. Th e NMI EG bit in SYSCR selects whether an interrupt is requ ested by the
rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector
number 7.
IRQ5, IRQ4, IRQ1, IRQ0 Interrupts: These interrupts are requested by input signals at pins IRQ5,
IRQ4, IRQ1, IRQ0. The IRQ5, IRQ4, IRQ1, IRQ0 interrupts have the following features.
• ISCR settings can select whether an interrup t is requested by the low level of the input at pins
IRQ5, IRQ4, IRQ1, IRQ0, or by the falling edge.
• IER settings can enable or disable the IRQ5, IRQ4, IRQ1, IRQ0 interrupts.
Interrupt priority levels can be assigned by four bits in IPRA (IPRA7, IPRA6, and IPRA4).
• The status of IRQ5, IRQ4, IRQ1, IRQ0 interrupt requests is indicated in ISR. The ISR flags can
be cleared to 0 by software.
Figure 5.2 shows a block diagram of interrupts IRQ5, IRQ4, IRQ1, IRQ0.
input
Edge/level
sense circuit
IRQnSC
IRQnF
S
R
Q
IRQnE
IRQn interrupt
request
Clear signal
IRQn
Note: n = 5, 4, 1 and 0
Figure 5.2 Block Diagram of Interrupts IRQ5, IRQ4, IRQ1, and IRQ0
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Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF).
φ
IRQn
IRQnF
input pin
Note: n = 5, 4, 1 and 0
Figure 5.3 Timing of Setting of IRQnF
Interrupts IRQ5, IRQ4, IRQ1, IRQ0 have vector numbers 17, 16, 13, 12. These interrupts are
detected regardless of whether the corresponding pin is set for input or output. When using a pin
for external interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output.
5.3.2 Internal Interrupts
Twenty-five internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.
5.3.3 Interrupt Vect or Table
Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5.3.
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Table 5.3 Interrupt Sources, Vect or Addresses, and P r iority
Vector Address*
Interrupt Source Origin Vector
Number Normal Mode Advanced Mode I P R Priority
NMI External pi ns 7 H'000E to H'000F H'001C to H'001F —High
IRQ012 H'0018 to H'0019 H'0030 to H'0033 IP RA7
IRQ113 H'001A to H'001B H'0034 to H0037 IPRA6
Reserved —14
15
H'001C to H'001D
H'001E to H'001F
H'0038 to H'003B
H'003C to H'003F
—
IRQ4External pins 16 H' 0020 to H'0021 H'0040 t o H' 0043 IP RA4
IRQ517 H'0022 to H' 0023 H'0044 to H'0047
Reserved —18
19
H'0024 to H'0025
H'0026 to H'0027
H'0048 to H'004B
H'004C to H'004F
WOVI (interv al timer) Wat chdog timer 20 H'0028 to H'0029 H'0050 t o H' 0053 IP RA3
Reserved —21
22
23
H'002A to H'002B
H'002C to H'002D
H'002E to H'002F
H'0054 to H'0057
H'0058 to H'005B
H'005C to H'005F
IMIA0 (compare match/
input capture A0)
IMIB0 (compare match/
input capture B0)
OVI0 (overflow 0)
ITU channel 0 24
25
26
H'0030 to H'0031
H'0032 to H'0033
H'0034 to H'0035
H'0060 to H'0063
H'0064 to H'0067
H'0068 to H'006B
IPRA2
Reserved —27 H'0036 to H'0037 H' 006C to H'006F
IMIA1 (compare match/
input capture A1)
IMIB1 (compare match/
input capture B1)
OVI1 (overflow 1)
ITU channel 1 28
29
30
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D
H'0070 to H'0073
H'0074 to H'0077
H'0078 to H'007B
IPRA1
Reserved —31 H'003E to H'003F H'007C to H'007F
IMIA2 (compare match/
input capture A2)
IMIB2 (compare match/
input capture B2)
OVI2 (overflow 2)
ITU channel 2 32
33
34
H'0040 to H'0041
H'0042 to H'0043
H'0044 to H'0045
H'0080 to H'0083
H'0084 to H'0087
H'0088 to H'008B
IPRA0
Reserved —35 H'0046 to H'0047 H' 008C to H'008F
Section 5 Interrupt Controller
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Vector Address*
Interrupt Source Origin Vector
Number Normal Mode Advanced Mode I P R Priority
IMIA3 (compare match/
input capture A3)
IMIB3 (compare match/
input capture B3)
OVI3 (overflow 3)
ITU channel 3 36
37
38
H'0048 to H'0049
H'004A to H'004B
H'004C to H'004D
H'0090 to H'0093
H'0094 to H'0097
H'0098 to H'009B
IPRB7
Reserved —39 H'004E to H'004F H'009C to H'009F
IMIA4 (compare match/
input capture A4)
IMIB4 (compare match/
input capture B4)
OVI4 (overflow 4)
ITU channel 4 40
41
42
H'0050 to H'0051
H'0052 to H'0053
H'0054 to H'0055
H'00A0 to H'00A3
H'00A4 to H'00A7
H'00A8 to H'00AB
IPRB6
Reserved —43
44
45
46
47
48
49
50
51
H'0056 to H'0057
H'0058 to H'0059
H'005A to H'005B
H'005C to H'005D
H'005E to H'005F
H'0060 to H'0061
H'0062 to H'0063
H'0064 to H'0065
H'0066 to H'0067
H'00AC to H'00AF
H'00B0 to H'00B3
H'00B4 to H'00B7
H'00B8 to H'00BB
H'00BC to H'00BF
H'00C0 to H'00C3
H'00C4 to H'00C7
H'00C8 to H'00CB
H'00CC to H'00CF
—
ERI0 (receiv e error 0)
RXI0 (receiv e data full 0)
TXI0 (transmit data
empty 0)
TEI0 (transmit end 0)
SCI channel 0 52
53
54
55
H'0068 to H'0069
H'006A to H'006B
H'006C to H'006D
H'006E to H'006F
H'00D0 to H'00D3
H'00D4 to H'00D7
H'00D8 to H'00DB
H'00DC to H'00DF
IPRB3
ERI1 (receiv e error 1)
RXI1 (receiv e data full 1)
TXI1 (transmit data
empty 1)
TEI1 (transmit end 1)
SCI channel 1 56
57
58
59
H'0070 to H'0071
H'0072 to H'0073
H'0074 to H'0075
H'0076 to H'0077
H'00E0 to H'00E3
H'00E4 to H'00E7
H'00E8 to H'00EB
H'00EC to H'00EF
IPRB2
ADI (A/D end) A/D 60 H'0078 to H'0079 H'00F0 to H'00F3 I PRB1 Low
Note: *Lower 16 bits of the address .
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5.4 Interrupt Operation
5.4.1 Interrupt Handling P r ocess
The H8/3039 Group handles interrupts differently depending on the setting of the UE bit. When
UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and
UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I,
and UI bits.
NMI interrupts are always accepted except in the reset and hard ware standby states. IRQ interrupts
and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests
are ignored when the enable bits are cleared to 0.
Table 5.4 UE, I, and UI Bit Settings and I nterrupt Handling
SYSCR CCR
UE I UI Description
10—All interrupts are accepted. Interrupts with priority level 1 have
higher priority.
1 — No interrupts are accepted except NMI.
00—All interrupts are accepted. Interrupts with priority level 1 have
higher priority.
1 0 NMI and interrupts with priority level 1 are accepted.
1 No interrupts are accepted except NMI.
UE = 1
Interrupts IRQ0, IRQ1, IRQ4, and IRQ5 and interrupts from th e on-chip supporting modules can all
be masked by the I bit in the CPU's CCR. Interrupts ar e masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure
5.4 is a flowchart showing how interrupts are accepted when UE = 1.
Section 5 Interrupt Controller
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Program execution state
Interrupt requested?
NMI?
No
Yes
No
Yes
No
Priority level 1?
No
IRQ0?
Yes No
IRQ1?
Yes ADI?
Yes
No
IRQ0?
Yes No
IRQ1?
Yes ADI?
Yes
No
I = 0?
Yes
Save PC and CCR
I 1
Branch to interrupt
service routine
←
Pending
Yes
Read vector address
Figure 5.4 Process Up to Interrupt Acceptance when UE = 1
Section 5 Interrupt Controller
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• If an interrupt cond ition occurs and the corresponding inter rupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same I PR settin g are reque sted simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt con troller ch ecks the I bit. If the I bit is cleared to 0, the selected interru p t requ e st
is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held
pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In inte rrupt ex c ep tion handling, PC an d CCR are saved to the stack a rea. The PC value that is
saved indicates the address of the fir st in str uction that will be executed after the return from the
interrupt ser vice routine.
• Next the I bit is set to 1 in CCR, masking all interrupts except NM I.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
UE = 0
The I and UI bits in the CPU's CCR and th e IPR bits enable thr ee-level masking of IRQ0, IRQ1,
IRQ4, and IRQ5 interrupts and interrupts f rom the on-chip supporting modules.
• Interrupt req uests with priority level 0 are masked when th e I bit is set to 1, and are unmasked
when the I bit is cleared to 0.
• Interrupt requests with priority lev el 1 are masked when the I and UI bits are both set to 1, and
are unmasked when either the I bit or the UI bit is cleared to 0.
For examp le, if the in ter rup t enable bits of all interrupt r equ ests are set to 1, IPRA is set to
H'10, and IPRB is set to H'00 (giving IRQ4 and IRQ5 interrupt requests priority over other
interrupts), interrupts are masked as follows:
a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ4 > IRQ5 > IRQ0 …).
b. If I = 1 and UI = 0, only NMI, IRQ4, and IRQ5 are unmasked.
c. If I = 1 and UI = 1, all interrupts are masked except NMI.
Figure 5.5 shows the transitions among the above states.
Section 5 Interrupt Controller
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All interrupts are
unmasked Only NMI, IRQ , and
IRQ are unmasked
Exception handling,
or I 1, UI 1
←←
a. b.
4
5
All interrupts are
masked except NMI
c.
UI 0
←
I 0
←Exception handling,
or UI 1
←
I 0
←
I 1, UI 0
←←
Figure 5.5 Interrupt Masking State Transitions (Example)
Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0.
• If an interrupt cond ition occurs and the corresponding inter rupt enable bit is set to 1, an
interrupt r equ est is sent to the interrupt controller.
• When the interrupt controller receives one or more interrupt requests, it selects the highest-
priority request, following the IPR interrupt priority settings, and holds other requests pending.
If two or more interrupts with the same I PR settin g are reque sted simultaneously, the interrupt
controller follows the priority order shown in table 5.3.
• The interrupt con troller ch ecks the I bit. If the I bit is cleared to 0, the selected interru p t requ e st
is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and
the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt
requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only
NMI is accepted; all other interrupt requests are held pending.
• When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
• In inte rrupt ex c ep tion handling, PC an d CCR are saved to the stack a rea. The PC value that is
saved indicates the address of the fir st instruction that will be execu ted after the return from the
interrupt ser vice routine.
• The I and UI bits a re set to 1 in CCR, mask ing all inte rrup t s e xcept NMI.
• The vector address of the accepted interrupt is generated, and the interrupt service routine
starts executing from the address indicated by the contents of the vector address.
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Program execution state
Interrupt requested?
NMI?
No
Yes
No
Yes
No
Priority level 1?
No
IRQ0?
Yes No
IRQ1?
Yes ADI?
Yes
No
IRQ0?
Yes No
IRQ1?
Yes ADI?
Yes
No
I = 0?
Yes
No
I = 0?
Yes
UI = 0?
Yes
No
Save PC and CCR
I 1, UI 1
←
Pending
Branch to interrupt
service routine
Yes
←
Read vector address
Figure 5.6 Process Up to Interrupt Acceptance when UE = 0
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5.4.2 Interrupt Sequence
Figure 5.7 shows the interrupt sequence in mode 5 when the program code and stack are in an on -
chip memory area.
φ
Address
bus
Interrupt
request
signal
Internal
read signal
Internal
write signal
Internal
data bus
(1)
(2), (4)
(3)
(5)
(7)
Note: Mode 5, with program code and stack in on-chip memory area.
Interrupt level
decision and wait
for end of instruction
Interrupt accepted
Instruction
prefetch Internal
processing Stack Vector fetch Internal
processing
Prefetch of
interrupt
service routine
instruction
High
Instruction prefetch address (not executed;
return address, same as PC contents)
Instruction code (not executed)
Instruction prefetch address (not executed)
SP – 2
SP – 4
(6), (8)
(9), (11)
(10), (12)
(13)
(14)
PC and CCR saved to stack
Vector address
Starting address of interrupt service routine (contents of
vector address)
Starting address of interrupt service routine; (13) = (10), (12)
First instruction of interrupt service routine
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
Figure 5.7 Int errupt Sequence (Mode 5, Stack in O n- Chip Memory)
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5.4.3 Interrupt Response Time
Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request un til the
first instruction of the interrupt service routine is executed.
Table 5.5 Interrupt Response Time
External Memory
8-Bit Bus
No. Item On-Chip
Memory 2 States 3 States
1 Interrupt priority decision 2*12*12*1
2 Maximum number of states 1 to 23 1 to 27 1 to 31*4
until end of current instruction
3 Saving PC and CCR to stack 4 8 12*4
4 Vector fetch 4 8 12*4
5 Instruction prefetch*24812*4
6 Internal processing*3444
Total 19 to 41 31 to 57 43 to 73
Notes: 1. 1 state for internal interrupts.
2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt
service routine.
3. Internal processing after the interrupt is accepted and internal processing after prefetch.
4. The number of states increases if wait states are inserted in external memory access.
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5.5 Usage Notes
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction
When an instr uction clears an interrupt en able bit to 0 to disable the interrupt, the interrup t is not
disabled un til af ter execution of the instruction is completed. If an interrupt o ccurs while a BCLR,
MOV, or other instru ction is being executed to clear its interrupt enable bit to 0, at the instant
when execution o f the instruction ends the in terru pt is still enabled, so its interrupt exception
handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception
handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored.
This also applies to the clearing of an interrupt flag.
Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the ITU's TIER.
IMIA exception handlingTIER write cycle by CPU
φ
TIER address
Internal
address bus
Internal
write signal
IMIEA
IMIA
IMFA interrupt
signal
Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction
This type of contention will not occur if the interrupt is m asked when the interrupt en able bit o r
flag is cleared to 0.
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5.5.2 Instructions that Inhibit Interrupts
The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after
determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is
currently executing one of these interrupt- inhib iting instructions, however, when the instructio n is
completed the CPU always continues by executing the next instruction.
5.5.3 Interrupts during EEPMOV Instruction Execution
The EEPMOV.B and EEPMOV.W instr uctions differ in their reaction to interrupt requests.
When the EEPMOV.B instru ction is executing a transfer, no interrupts are accep ted until the
transfer is completed, not even NMI.
When the EEPMOV.W instr uction is executing a transfer, interrup t r equ ests other than NMI are
not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at
a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction.
Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution:
L1: EEPMO V.W
MOV.W R4, R4
BNE L1
5.5.4 Usage Notes
The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read
while set to 1. However, it is possible f or th e I RQn F f lag to be clear ed by mistak e simply by
writing 0 to it, irrespective of whether it h a s been read while set to 1, with the result that interrupt
exception h andling is not executed. This will occur when the following conditions are met.
1. Setting Co nditions
(1) Multiple external interrupts (I RQa, IRQb) ar e being used.
(2) Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and
clearing by hardware for the IRQbF flag.
(3) A bit-manipulation instruction is used on the IRQ status register for clearing the IRQaF flag, or
else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other
bits are written as a byte unit.
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2. Generation Conditions
(1) A read o f the ISR reg ister is executed to clear the IRQaF flag while it is set to 1, then the
IRQbF flag is cleared by the execution of interrupt exception handling.
(2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag setting).
(IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1 before ISR is
written to.)
If the above settin g conditions (1) to (3) and generation conditions (1) and (2) are all fulfilled,
when the ISR write in generation condition (2) is performed the IRQbF flag will be clear ed
inadverten tly, and interrupt exception handling will not be executed.
However, this inadvertent clearing of the IRQbF flag will not occur if 0 is written to this flag even
once between generation conditions (1) and (2).
1 read 0 written
1 read 1
written
1 read 0 written
1 read 0
written
IRQb
executed
Generation condition (1) Generation condition (2)
(Inadvertent clearing)
IRQaF
IRQbF
Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed
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Either of the methods shown below should be used to preven t this problem.
Method 1: When clearing the IRQaF flag, read ISR as a byte unit instead of using a bit-
manipulation instruction, and write a byte v alue that clears the IRQaF flag to 0 and sets the other
bits to 1.
Example: When a = 0
MOV.B @ISR, R0L
MOV.B #HFE, R0L
MOV. B R0L, @ISR
Method 2: Perform dummy processing within the IRQb interrupt exception handling routine to
clear the IRQbF flag.
Example: When b = 1
IRQB MOV.B #HFD, R0L
MOV. B R0L, @ISR
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Section 6 Bus Controller
6.1 Overview
The H8/3039 Group has an on-chip bus controller that divides the external address space into eight
areas and can assign different bus specifications to each. This enables different types of memory to
be connected easily.
6.1.1 Features
Features of th e bus controller are listed b elow.
• Independent settings for address areas 0 to 7
128-kbyte areas in 1-Mbyte mode.
2-Mbyte areas in 16-Mbyte mode.
Areas can be designated for two-state or three-state access.
• Four wait modes
Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected.
Zero to three wait states can be inserted automatically.
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6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the bus controller.
Bus control
circuit
ASTCR
WCER
Internal data bus
Access state control signal
Wait request signal
Internal signals
Wait-state
controller
WCR
Area
decoder
Internal
address bus
WAIT
Legend:
ASTCR:
WCER:
WCR:
Access state control register
Wait state controller enable register
Wait control register
Figure 6.1 Block Diagram of Bus Controller
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6.1.3 Input/Out put Pins
Table 6.1 summarizes the bus controller's input/output pins.
Table 6.1 Bus Controller Pins
Name Abbreviation I/O Function
Address strobe AS Output Strobe signal indicating valid address output on
the address bus
Read RD Output Strobe signal indicating reading from the external
address spa ce
Write WR Output Strobe signal indicating writing to the external
address space, with valid data on the data
bus(D7 to D0)
Wait WAIT Input Wait request signal for access to external three-
state-access areas
6.1.4 Register Configuration
Table 6.2 summarizes the bus controller's registers.
Table 6.2 Bus Controller Registers
Address*Name Abbreviation R/W Initial Value
H'FFED Access state control register ASTCR R/W H'FF
H'FFEE Wait control regi ster WCR R/W H'F3
H'FFEF Wait state controller enable r egi ster WCER R/W H'FF
H'FFF3 Address control register ADRCR R/W H'FE
Note: *Lower 16 bits of the address .
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6.2 Register Descriptions
6.2.1 Access State Control Register (ASTCR)
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
Initial value
Read/Write
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
0
AST0
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
Bits selecting number of states for access to each area
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0 Description
0 Areas 7 to 0 are accessed in two states
1 Areas 7 to 0 are accessed in three states (Initial value)
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
Therefore, in the single-chip modes (modes 6 and 7), the set value is meaningless.
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6.2.2 Wait Control Register (WCR)
WCR is an 8-bit readable/writab le r e gister that selects the wait mo d e for the wait-state controller
(WSC) and specifies the number of wait states.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
WMS1
0
R/W
0
WC0
1
R/W
2
WMS0
0
R/W
1
WC1
1
R/W
Wait count 1/0
These bits select the
number of wait states
inserted
Reserved bits
Wait mode select 1/0
These bits select the wait mode
WCR is initia lized to H'F3 by a r e set and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit3
WMS1 Bit2
WMS0 Description
0 0 Programmable wait mode (Initial value)
1 No wait states in serted by wait-state controller
1 0 Pin wait mode 1
1 Pin auto-wait mode
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Bits 1 and 0—Wa it Count 1 and 0 (WC1/0) : These bits select the number of wait states inserted
in access to external three-state-access areas.
Bit1
WC1 Bit0
WC0 Description
0 0 No wait states inserted by wait-state controller
1 1 state inserted
1 0 2 states inserted
1 3 states inserted (Initial value)
6.2.3 Wait State Controller Enable Register (WCER)
WCER is an 8-bit readable/writable register that en ables or disables wait-state control of external
three-state-access areas by the wait-state controller.
Bit
Initial value
Read/Write
7
WCE7
1
R/W
6
WCE6
1
R/W
5
WCE5
1
R/W
4
WCE4
1
R/W
3
WCE3
1
R/W
0
WCE0
1
R/W
2
WCE2
1
R/W
1
WCE1
1
R/W
Wait state controller enable 7 to 0
These bits enable or disable wait-state control
WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or
disable wait-state control of external three-state-access areas.
Bits 7 to 0
WCE7 to WCE0 Description
0 Wait-state control disabled (pin wait mode 0)
1 Wait-state control enabled (Initial value)
WCER enables or disables wait-state control of external three-state-access areas. Therefore, in the
single-chip modes (modes 6 and 7), the set value is meaningless.
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6.2.4 Address Control Register (ADRCR)
ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21.
Bit
Initial value
Read/Write
Initial value
Read/Write
7
A
23
E
1
—
1
R/W
6
A
22
E
1
—
1
R/W
5
A
21
E
1
—
1
R/W
4
—
1
—
1
—
3
—
1
—
1
—
0
—
0
R/W
0
R/W
2
—
1
—
1
—
1
—
1
—
1
—
Address 23 to 21 enable
These bits enable PA
6
to
PA
4
to be used for A
23
to
A
21
address output
Reserved bits
Modes 1
and 5 to 7
Mode 3
ADRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing
0 in this bit enables A23 address output from PA4. In modes other than 3 this bit cannot be
modified and PA4 has its ordinary input/output functions
Bit 7
A23E Description
0PA
4 is the A23 address output pin
1PA
4 is the PA4/TP4/TIOCA1 input/output pin (Initial value)
Bit 6—Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing 0
in this bit enables A22 address output from PA5. In modes other than 3 this bit cannot be modified
and PA5 has its ordinary input/output functions.
Bit 6
A22E Description
0PA
5 is the A22 address output pin
1PA
5 is the PA5/TP5/TIOCB1 input/ou tput pin (Initial val ue)
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Bit 5—Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing
0 in this bit enables A21 address output from PA6. In modes other than 3 this bit cannot be modified
and PA6 has its ordinary input/output functions.
Bit 5
A21E Description
0PA
6 is the A21 address output pin
1PA
6 is the PA6/TP6/TIOCA2 input/output pin (Initial value)
Bits 4 to 0—Reserved
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6.3 Operation
6.3.1 Area Division
The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the
1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6.2 shows a general view of the
memory map.
Notes: There is no area division in modes 6 and 7.
1. The number of access states to on-chip ROM, on-chip RAM, and on-chip I/O registers is fixed.
2. This area follows area 7 specifications when the RAME bit in SYSCR is 0.
3. This area follows area 7 specifications.
H'00000 Area 0 (128 kbytes)
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
Area 7 (128 kbytes)
On-chip RAM*
1
*
2
External address space*
3
On-chip I/O registers*
1
a.
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'FFFFF
b.
H'000000 Area 0 (2 Mbytes)
Area 1 (2 Mbytes)
Area 2 (2 Mbytes)
Area 3 (2 Mbytes)
Area 4 (2 Mbytes)
Area 5 (2 Mbytes)
Area 6 (2 Mbytes)
Area 7 (2 Mbytes)
On-chip RAM*
1
*
2
External address space*
3
On-chip I/O registers*
1
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FFFFFF
H'00000
Area 1 (128 kbytes)
Area 2 (128 kbytes)
Area 3 (128 kbytes)
Area 4 (128 kbytes)
Area 5 (128 kbytes)
Area 6 (128 kbytes)
H'1FFFF
H'20000
H'3FFFF
H'40000
H'5FFFF
H'60000
H'7FFFF
H'80000
H'9FFFF
H'A0000
H'BFFFF
H'C0000
H'DFFFF
H'E0000
H'FFFFF
1-Mbyte modes with
on-chip ROM disabled
(mode 1)
16-Mbyte modes with
on-chip ROM disabled
(mode 3)
c. 1-Mbyte mode with
on-chip ROM enabled
(mode 5)
Area 7 (128 kbytes)
On-chip RAM*
1
*
2
External address space*
3
On-chip I/O registers *
1
On-chip ROM*
1
Area 0 (128 kbytes)
Figure 6.2 Access Area Map (Mode 1, 3, and 5)
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 120 of 682
REJ09B0353-0300
The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in
table 6.3.
Table 6.3 Bus Specifications
ASTCR WCER WCR Bus Specifications
ASTn WCEn WMS1 WMS0 Bus
Width Access
States Wait Mode
0——— 82 Disabled
10—— 8 3 Pin wait mode 0
1 0 0 8 3 Programmable wait mode
1 8 3 Disabled
1 0 8 3 Pin wait mode 1
1 8 3 Pin auto-wait mode
Note: n = 0 to 7
Section 6 Bus Controller
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6.3.2 Bus Control Signal Timing
8-Bit, Three-State-Access Areas
Figure 6.3 shows the timing of bus control signals for an 8-bit, th ree-state-access area. Wait states
can be inserted.
Bus cycle
φ
Address bus
AS
RD
D
7
to D
0
WR
D
7
to D
0
Read
access
Write
access
External address
Valid
Valid
T
1
T
2
T
3
Figure 6.3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area
Section 6 Bus Controller
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8-Bit, Two-State-Access Areas
Figure 6.4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait states
cannot be inserted.
φ
Bus cycle
Address bus
AS
RD
D
7
to D
0
WR
D
7
to D
0
Read
access Valid
Valid
Write
access
T
1
T
2
External address
Figure 6.4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
Section 6 Bus Controller
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6.3.3 Wait Modes
Four wait modes can be selected for each area as shown in table 6.4.
Table 6.4 Wait Mode Selectio n
ASTCR WCER WCR
ASTn Bit WCEn Bit WMS1 Bit WMS0 Bit WSC Control Wait Mode
0———Disabled No wai t states
10 ——Disabled Pin wait mode 0
1 0 0 Enabled Programmable wait mode
1 Enabled No wait states
1 0 Enabled Pin wait mode 1
1 Enabled Pin auto-wait mode
Note: n = 0 to 7
The ASTn and WCEn bits can be set independently for each area. Bits WMS1 and WMS0 apply
to all areas. All areas for which WSC contro l is enabled operate in the same wait mode.
Section 6 Bus Controller
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Pin Wait Mode 0
The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During
access to an external three-state-access area, if the WAIT pin is low at the fall of the system clock
(φ) in the T2 state, a wait state (TW) is inserted. If the WAIT p in remains lo w, wait states con tinue
to be inserted until the WAIT signal goes high. Figure 6.5 shows the timing.
φ
Address bus
Data bus
AS
RD
WR
Data bus
T
1
T
2
T
W
T
W
T
3
Inserted by WAIT signal
Write data
***
Read data
Read
access
Write
access
External address
WAIT pin
Note: * Arrows indicate time of sampling of the WAIT pin.
Figure 6.5 Pin Wait Mode 0
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 125 of 682
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Pin Wait Mode 1
In all accesses to external three-state-access areas, the number of wait states (TW) selected by bits
WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (φ) in the last of
these wait states, an ad ditional wait state is inserted . If the WAIT pin rema ins low, wait states
continue to be inserted until the WAIT signal goes high.
Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
If the wait count is 0 , this mode operates in th e sam e way as pin wait mode 0.
Figure 6.6 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait
state is inserted by WAIT input.
Address bus
Data bus
AS
RD
WR
T
1 T
2 T
W T
W T
3
Write data
*
Read data
*
Read
access
Write
access
Note: * Arrows indicate time of sampling of the WAIT pin.
φ
WAIT pin
Data bus
External address
Write data
Inserted by
wait count Inserted by
WAIT signal
Figure 6.6 Pin Wait Mode 1
Section 6 Bus Controller
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Pin Auto-Wait Mode
If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are
inserted.
In pin auto-wait mode, if the WAIT pin is low at the fall of the sy stem clock (φ) in the T2 state, the
number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states
are inserted even if the WAIT pin remains low.
Figure 6. 7 shows the timing when the wait count is 1.
φ
Address bus
Data bus
AS
RD
WR
Data bus
T
1 T
2 T
3 T
1 T
2 T
W T
3
**
Read data Read data
Write data Write data
Read
access
Write
access
Note: * Arrows indicate time of sampling of the WAIT pin.
External address External address
WAIT
Figure 6.7 Pin Auto-Wait Mode
Section 6 Bus Controller
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Programmable Wait Mode
The number of wait states (TW) selected by bits WC1 and WC0 are inserted in all accesses to
external three-state-access areas. Figure 6.8 shows the timing when the wait count is 1 (WC1 = 0,
WC0 = 1).
T
1
T
2
T
W
T
3
φ
Address bus
AS
RD
WR
Data bus
Data bus
External address
Read data
Write data
Read
access
Write
access
Figure 6.8 Programmable Wait Mode
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 128 of 682
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Example of Wait State Control Settings
A reset initializes A STCR and WCER to H'FF and WCR to H'F3, selecting programmable wait
mode and three wait states for all areas. Software can select other wait modes for individual areas
by modifying the ASTCR, WCER, and WCR settings. Figure 6.9 shows an example of wait mode
settings.
76543210
0
0
—
0
0
—
0
1
—
0
1
—
1
0
0
1
0
0
1
1
1
1
1
1
Bit:
ASTCR H'0F:
WCER H'33:
WCR H'F3:
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
3-state-access area,
programmable wait mode
3-state-access area,
programmable wait mode
3-state-access area,
pin wait mode 0
3-state-access area,
pin wait mode 0
2-state-access area,
no wait states inserted
2-state-access area,
no wait states inserted
2-state-access area,
no wait states inserted
2-state-access area,
no wait states inserted
Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR.
Figure 6.9 Wait Mode Settings (Example)
Section 6 Bus Controller
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6.3.4 Interconnections with Memory (Example)
For each area, the bus controller can select two- or three-state access. In three-state-access areas,
wait states can be inserted in a variety of modes, simplifying th e connection of both high-speed
and low-speed devices.
Figure 6.10 shows a memory map for this example.
A 32-kword × 8-bit EPROM is connected to area 2. This device is accessed in three states via an
8-bit bus.
Two 32-kword × 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 3. These
devices are accessed in two states via an 8-bit bus.
One 32-kword × 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an 8-bit
bus, using three-state access with an additional wait state inserted in pin auto-wait mod e.
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 130 of 682
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Area 2
8-bit, three-state-access area
Area 0
Area 1
Area 3
8-bit, two-state-access area
Areas 4, 5, 6
Area 7
8-bit, three-state-access area
(one auto-wait state)
On-chip ROM
EPROM
Not used
SRAM1, 2
Not used
SRAM3
Not used
On-chip RAM
On-chip I/O registers
H'00000
H'3FFFF
H'40000
H'1FFFF
H'20000
H'47FFF
H'48000
H'5FFFF
H'60000
H'6FFFF
H'70000
H'7FFFF
H'E0000
H'E7FFF
H'FFFFF
The bus width and the number of access states of the on-chip memories and I/O registers
are fixed; they cannot be changed by register setting.
Note:
Figure 6.10 Memory Map (H8/3039 Mode 5)
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 131 of 682
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6.4 Usage Notes
6.4.1 Register Write Timing
ASTCR and WCER Write Ti ming
Data written to ASTCR or WCER takes effect startin g from the next bus cycle. Figure 6.11 shows
the timing when an instruction fetched from area 2 changes area 2 from three-state access to two-
state access.
φ
Address
T
1 T
2 T
3 T
1 T
2 T
3 T
1 T
2
ASTCR address
3-state access to area 2 2-state access
to area 2
Figure 6.11 ASTCR Write Timing
6.4.2 Precautions on Setting ASTCR and ABWCR*
Use the H8/3039 Group on-chip program to set ASTCR and ABWCR as shown below, so that the
on-chip ROM access cycle for H8/3039 Group can be emulated using the evaluation chip for
support tools.
Modes 5 and 7
ASTCR0 = 0
ABWCR = H'FC
Note: * The ABWCR (bus width control register; lower 16-bit address: H'FFEC) is not built
onto this LSI. For detailed features of the ABWCR, see the H8/3048 Group,
H8/3048F-ZTATTM Hardware Manual.
Section 6 Bus Controller
Rev.3.00 Mar. 26, 2007 Page 132 of 682
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Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 133 of 682
REJ09B0353-0300
Section 7 I/O Ports
7.1 Overview
The H8/3039 Group has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input
port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplex ed as
shown in table 7.1.
Each port has a data direction register (DDR) for selecting inpu t or output, and a data register
(DR) for storing output data. In addition to these registers, ports 2, and 5 have an input pull-up
control register (PCR) for switching input pull-up transistors on and off.
Ports 1 to 3 and ports 5 , 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A,
and B can drive one TTL load and a 30-pF capacitive load. Ports 1 to 3 and ports 5, 6, 8, 9, A, and
B can drive a Darlington pair. Ports 1, 2, 5, and B can drive LEDs (with 10-mA current sink). Pins
P81, P80, PA7 to PA0, and PB3 to PB0 have Schmitt-trigger input circuits.
For block diagrams of the ports see appendix C, I/O Block Diagrams.
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 134 of 682
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Table 7.1 Port Functions
Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
Port 1 • 8-bit I/ O port
• Can drive
LEDs
P17 to P10/
A7 to A0
Address out put
pins (A7 to A0)Address output
(A7 to A0) and
generic input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/ output
Port 2 • 8-bit I/ O port
• Input pull-up
• Can drive
LEDs
P27 to P20/
A15 to A8
Address output pi ns (A15 to
A8)Address output
(A15 to A8) and
generic input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/ output
Port 3 • 8-bit I/ O port P37 to P30/
D7 to D0
Data input/output (D7 to D0) Generic input/ output
Port 5 • 4-bit I/ O port
• Input pull-up
• Can drive
LEDs
P53 to P50/
A19 to A16
Address out put (A 19 to A16) Address output
(A19 to A16) and
4-bit generic
input
DDR = 0:
generic input
DDR = 1:
address output
Generic input/ output
Port 6 • 4-bit I/ O port P65/WR,
P64/RD,
P63/AS
Bus control signal output (WR, RD, AS)
P60/WAIT Bus control signal input/ output ( WAIT) and 1-bit
generic input/out put
Generic input/ output
Port 7 • 8-bit Input
port P77 to P70/
AN7 to AN0
Analog input (AN7 to AN0) to A/D converter, and generic input
Port 8 P81/ IRQ1IRQ1 input and 1-bit generic input/output
• 2-bit I/O port
•P8
1 and P80
have Schmitt
inputs P80/IRQ0IRQ0 input and 1-bit generic input/output
IRQ1 and IRQ0 input
and generic input/
output
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 135 of 682
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Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
Port 9 • 6-bit I/ O
port P95/SCK1/IRQ5,
P94/SCK0/IRQ4,
P93/RxD1,
P92/RxD0,
P91/TxD1,
P90/TxD0
Input and output (SCK1, S CK 0, RxD1, RxD0, TxD1, TxD0) for serial
communicati on i nterf aces 1 and 0 (SCI0, 1), IRQ5 and IRQ4 input, and
6-bit generic input/output
Port A • 8-bit I/O port
•Schmitt
inputs
PA7/TP7/
TIOCB2/A20
Output (TP7)
from pro-
grammable
timing pattern
controller
(TPC), input
or output
(TIOCB2) f or
16-bit
integrated
timer unit
(ITU), and
generic
input/output
Address
output (A20)TP C output (TP7), ITU input or output
(TIOCB2), and generic input/ output
PA6/TP6/
TIOCA2/A21,
PA5/TP5/
TIOCB1/A22,
PA4/TP4/
TIOCA1/A23
TPC output
(TP6 to TP4),
ITU input
and output
(TIOCA2,
TIOCB1,
TIOCA1), and
generic input/
output
TPC output
(TP
6
to TP
4
),
ITU input
and output
(TIOCA2,
TIOCB1,
TIOCA1),
address
output
(A23 to A21),
and generic
input/output
TPC output (TP6 to TP4), ITU input and
output (TIOCA 2, T IOCB1, TIOCA1), and
generic input/out put
PA3/TP3/
TIOCB0/
TCLKD,
PA2/TP2/
TIOCA0/
TCLKC,
PA1/TP1/
TCLKB,
PA0/TP0/
TCLKA
TPC output (TP3 to TP0), ITU input and output (TCLKD, TCLKC,
TCLKB, TCLK A, TIOCB0, TIOCA 0), and generic input/output
Section 7 I/O Ports
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Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7
PB7/TP15/
ADTRG TPC output (TP15), trigger input (ADTRG) to A/D converter, and generic
input/output.
Port B • 7-bit I/Oport
• Can drive
LEDs
•PB
3 to PB0
have Schmitt
inputs
PB5/TP13/
TOCXB4,
PB4/TP12/
TOCXA4
PB3/TP11/
TIOCB4,
PB2/TP10/
TIOCA4,
PB1/TP9/
TIOCB3,
PB0/TP8/
TIOCA3
TPC output (TP13 to TP8), ITU input and output (TOCXB4, TOCXA4,
TIOCB4, TIOCA4, TIOCB3, TIOCA3), and generic input/output
Section 7 I/O Ports
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7.2 Port 1
7.2.1 Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. The pin
functions differ between the expanded modes with on-chip ROM disabled, expanded modes with
on-chip ROM enabled, and single-chip mode. In modes 1, 3 (expanded modes with on-chip ROM
disabled), they are address bus output pins (A7 to A0).
In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction
register (P1DDR) can designate pins fo r address bus output (A7 to A0) or generic input. In modes 6
and 7 (single-chip mode), port 1 is a generic input/output port.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair.
Port 1
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
P1 /A
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
7
6
5
4
3
2
1
0
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
7
6
5
4
3
2
1
0
Port 1 pins Modes 6 and 7Modes 1 and 3
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
P1 (input)/A (output)
7
6
5
4
3
2
1
0
Mode 5
7
6
5
4
3
2
1
0
Figure 7.1 Port 1 Pin Configuration
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 138 of 682
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7.2.2 Register Descriptions
Table 7.2 summarizes the registers of port 1.
Table 7.2 Port 1 Registers
Initial Value
Address*Name Abbreviation R/W Modes 1, 3 Mo d e s 5 to 7
H'FFC0 Port 1 data direction
register P1DDR W H'FF H'00
H'FFC2 Port 1 data register P1DR R/W H'00 H'00
Note: *Lower 16 bits of the address .
Port 1 Data Direction Register (P1DDR)
P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1.
Bit
Modes
1, 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
P1 DDR
1
—
0
W
7
6
P1 DDR
1
—
0
W
6
5
P1 DDR
1
—
0
W
5
4
P1 DDR
1
—
0
W
4
3
P1 DDR
1
—
0
W
3
2
P1 DDR
1
—
0
W
2
1
P1 DDR
1
—
0
W
1
0
P1 DDR
1
—
0
W
0
Port 1 data direction 7 to 0
These bits select input or
output for port 1 pins
P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P1DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Section 7 I/O Ports
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Port 1 Data Register (P1DR)
P1DR is an 8-b it r eadable/writable reg ister that stores data for pins P17 to P10.
Bit
Initial value
Read/Write
7
P1
0
R/W
Port 1 data 7 to 0
These bits store data for port 1 pins
7
6
P1
0
R/W
6
5
P1
0
R/W
5
4
P1
0
R/W
4
3
P1
0
R/W
3
2
P1
0
R/W
2
1
P1
0
R/W
1
0
P1
0
R/W
0
When a bit in P1DDR is set to 1, if p o rt 1 is read the value of the corresp onding P1DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P1DDR is cleared to 0, if
port 1 is read the corresponding pin level is read.
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting .
Section 7 I/O Ports
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7.2.3 Pin Functions in Each Mode
The pin functions of port 1 differ between mode 1, 3 (expanded mode with on-chip ROM
disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip
mode). The pin functions in each mode are described as follows.
Modes 1 and 3
Address output can be selected for each pin in port 1. Figure 7.2 shows the pin functions in modes
1 and 3.
Port 1
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
7
6
5
4
3
2
1
0
Figure 7.2 Pin Functions in Modes 1 and 3 (Port 1)
Mode 5
Address output or generic input can be selected for each pin in port 1. A pin becomes an address
output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared
to 0. Following a reset, all pins are input pins. To use a pin for address output, its P1DDR bit must
be set to 1. Figure 7.3 shows the pin functions in mode 5.
Section 7 I/O Ports
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Port 1
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
7
6
5
4
3
2
1
0
When P1DDR = 1
P1 (input)
P1 (input)
P1 (input)
P1 (input)
P1 (input)
P1 (input)
P1 (input)
P1 (input)
7
6
5
4
3
2
1
0
When P1DDR = 0
Figure 7.3 Pin Functions in Mode 5 (Port 1)
Modes 6 and 7 (Single-Chip Mode)
Input or output can be selected separately for each pin in port 1. A pin becomes an output pin if
the corresponding P1DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.4
shows the pin functions in modes 6 and 7.
Port 1
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
P1 (input/output)
7
6
5
4
3
2
1
0
Figure 7.4 Pin Functions in Modes 6 and 7 (Port 1)
Section 7 I/O Ports
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7.3 Port 2
7.3.1 Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. Pin functions
differ according to operation mode.
In modes 1 and 3 (expanded mode with on-chip ROM disabled), port 2 consists of address bus
output pins (A15 to A8). In mode 5 (expanded mode with on-chip ROM enabled), settings in the
port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or
generic input. In modes 6 and 7 (single-chip mode), port 2 is a generic input/output port.
Port 2 has software-programm a ble built-in pull-up tr ansisto r s. Pins in port 2 can drive one TTL
load and a 90-pF capacitive load. They can also drive a Darlington transistor pair.
Port 2
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
7
6
5
4
3
2
1
0
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
15
14
13
12
11
10
9
8
Port 2 pins Mode 6 and 7Modes 1 and 3
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
P2 (input)/A (output)
7
6
5
4
3
2
1
0
Modes 5
15
14
13
12
11
10
9
8
Figure 7.5 Port 2 Pin Configuration
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 143 of 682
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7.3.2 Register Descriptions
Table 7.3 summarizes the registers of port 2.
Table 7.3 Port 2 Registers
Initial Value
Address*Name Abbreviation R/W Mo des 1 and 3 Modes 5 to 7
H'FFC1 Port 2 data direction
register P2DDR W H'FF H'00
H'FFC3 Port 2 data register P2DR R/W H'00 H'00
H'FFD8 Port 2 input pull-up
control register P2PCR R/W H'00 H'00
Note: *Lower 16 bits of the address .
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2.
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
P2 DDR
1
—
0
W
7
6
P2 DDR
1
—
0
W
6
5
P2 DDR
1
—
0
W
5
4
P2 DDR
1
—
0
W
4
3
P2 DDR
1
—
0
W
3
2
P2 DDR
1
—
0
W
2
1
P2 DDR
1
—
0
W
1
0
P2 DDR
1
—
0
W
0
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P2DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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Port 2 Data Register (P2DR)
P2DR is an 8-b it r eadable/writable reg ister that stores data for pins P27 to P20.
Bit
Initial value
Read/Write
7
P2
0
R/W
Port 2 data 7 to 0
These bits store data for port 2 pins
7
6
P2
0
R/W
6
5
P2
0
R/W
5
4
P2
0
R/W
4
3
P2
0
R/W
3
2
P2
0
R/W
2
1
P2
0
R/W
1
0
P2
0
R/W
0
When a bit in P2DDR is set to 1, if p o rt 2 is read the value of the corresp onding P2DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P2DDR is cleared to 0, if
port 2 is read the corresponding pin level is read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting .
Port 2 Input P ull- Up Control Register (P 2PCR)
P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port
2.
Bit
Initial value
Read/Write
7
P2 PCR
0
R/W
Port 2 input pull-up control 7 to 0
These bits control input pull-up
transistors built into port 2
7
6
P2 PCR
0
R/W
6
5
P2 PCR
0
R/W
5
4
P2 PCR
0
R/W
4
3
P2 PCR
0
R/W
3
2
P2 PCR
0
R/W
2
1
P2 PCR
0
R/W
1
0
P2 PCR
0
R/W
0
When a P2DDR bit is cleared to 0 (selecting generic input) in modes 7 to 5, if the corresponding
bit fro m P27PCR to P20PCR is set to 1, th e input pull-up tr ansistor is turned on.
P2PCR is initialized to H'00 by a r e set and in hardware standby mod e . In so f tware standby mode it
retains its previous setting .
Section 7 I/O Ports
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7.3.3 Pin Functions in Each Mode
The pin functions of port 2 differ between mode 1, 3 (expanded mode with on-chip ROM
disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip
mode). The pin functions in each mode ar e described followings.
Modes 1 and 3
Address output can be selected for each pin in port 2. Figure 7.6 shows the pin functions in modes
1 and 3.
Port 2
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
15
14
13
12
11
10
9
8
Figure 7.6 Pin Functions in Modes 1 and 3 (Port 2)
Mode 5
Address output or generic input can be selected for each pin in port 2. A pin becomes an address
output pin if the corresponding P2DDR bit is set to 1, and a generic input pin if this bit is cleared
to 0. Following a reset, all pins are input pins. To use a pin for address output, its P2DDR bit must
be set to 1. Figure 7.7 shows the pin functions in modes 5.
Section 7 I/O Ports
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REJ09B0353-0300
Port 2
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
A (output)
15
14
13
12
11
10
9
8
When P2DDR = 1
P2 (input)
P2 (input)
P2 (input)
P2 (input)
P2 (input)
P2 (input)
P2 (input)
P2 (input)
7
6
5
4
3
2
1
0
When P2DDR = 0
Figure 7.7 Pin Functions in Modes 1 and 3 (Port 2)
Modes 6 and 7
Input or output can be selected separately for each pin in port 2. A pin becomes an output pin if
the corresponding P2DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.8
shows the pin functions in modes 6 and 7.
Port 2
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
7
6
5
4
3
2
1
0
Figure 7.8 Pin Functions in Modes 6 and 7 (Port 2)
Section 7 I/O Ports
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7.3.4 Input Pull-Up Transistors
Port 2 has built-in MOS input pull-up tran sistors that can be controlled by software. These input
pull-up transistors can be turned on and off individually.
When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up
transistor is tu r ned on.
The input pull-up transistors are turned off by a reset and in hardware standby mode. In software
standby mode they retain their previous state.
Table 7.4 summarizes the states of the input pull-up transistors in each mode.
Table 7.4 Input Pull- Up Transisto r States (Port 2)
Mode Reset Hardware Standby
Mode Software Standby
Mode Other Modes
1
3Off Off Off Off
5
6
7
Off Off On/Off On/Off
Legend:
Off: The input pull-up transistor is always off.
On/Off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off.
Section 7 I/O Ports
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7.4 Port 3
7.4.1 Overview
Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7.9. Port 3 is a data
bus in modes 1, 3 and 5 (expanded modes) and a generic input/output port in mode 6 and 7
(single-chip mode).
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair.
Port 3
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
P3 /D
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
7
6
5
4
3
2
1
0
D (input/output)
D (input/output)
D (input/output)
D (input/output)
D (input/output)
D (input/output)
D (input/output)
D (input/output)
7
6
5
4
3
2
1
0
Port 3 pins Modes 6 and 7Modes 1, 3 and 5
Figure 7.9 Port 3 Pin Configuration
7.4.2 Register Descriptions
Table 7.5 summarizes the registers of port 3.
Table 7.5 Port 3 Registers
Address*Name Abbreviation R/W Initial Value
H'FFC4 Port 3 data direction register P3DDR W H'00
H'FFC6 Port 3 data register P3DR R/W H'00
Note: *Lower 16 bits of the address .
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Port 3 Data Direction Register (P3DDR)
P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3.
Bit
Initial value
Read/Write
7
P3 DDR
0
W
Port 3 data direction 7 to 0
These bits select input or output for port 3 pins
7
6
P3 DDR
0
W
6
5
P3 DDR
0
W
5
4
P3 DDR
0
W
4
3
P3 DDR
0
W
3
2
P3 DDR
0
W
2
1
P3 DDR
0
W
1
0
P3 DDR
0
W
0
Modes 1, 3, and 5: Port 3 functions as a data bus. P3DDR is ignored.
Modes 6 and 7: Port 3 functions as an input/output port. A pin in port 3 becomes an output pin if
the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0.
P3DDR is a write-only register. Its value cannot be read. All bits retu rn 1 wh en read.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P3DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 3 Data Register (P3DR)
P3DR is an 8-b it r eadable/writable reg ister that stores data for pins P37 to P30.
Bit
Initial value
Read/Write
7
P3
0
R/W
Port 3 data 7 to 0
These bits store data for port 3 pins
7
6
P3
0
R/W
6
5
P3
0
R/W
5
4
P3
0
R/W
4
3
P3
0
R/W
3
2
P3
0
R/W
2
1
P3
0
R/W
1
0
P3
0
R/W
0
When a bit in P3DDR is set to 1, if p o rt 3 is read the value of the corresp onding P3DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P3DDR is cleared to 0, if
port 3 is read the corresponding pin level is read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting .
Section 7 I/O Ports
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7.4.3 Pin Functions in Each Mode
The pin functions of port 3 differ between modes 1, 3 and 5 and modes 6 and 7. The pin functions
in each mode are described below.
Modes 1, 3 and 5
All pins of port 3 automatically become data inpu t/output pins. Figure 7.10 shows the pin
functions in modes 1, 3 and 5.
Port 3
D7 (input/output)
D6 (input/output)
D5 (input/output)
D4 (input/output)
D3 (input/output)
D2 (input/output)
D1 (input/output)
D0 (input/output)
Figure 7.10 Pin Functions in Modes 1, 3 and 5 (Port 3)
Section 7 I/O Ports
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Modes 6 and 7
Input or output can be selected separately for each pin in port 3. A pin becomes an output pin if
the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.11
shows the pin functions in modes 6 and 7.
Port 3
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
P3 (input/output)
7
6
5
4
3
2
1
0
Figure 7.11 Pin Functions in Modes 6 and 7 (Port 3)
Section 7 I/O Ports
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7.5 Port 5
7.5.1 Overview
Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7.12. The pin
functions differ depending on the operating mode.
In modes 1, 3 (expanded modes with on-chip ROM disabled), port 5 consists of address output
pins (A19 to A16). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port
5 data direction register (P5DDR) designate pins for address bus ou tput (A19 to A16) or generic
input. In mode 6 and 7 (single-chip mode), port 5 is a generic input/output port.
Port 5 has software-programmable built-in pull-up transistors. Port 5 can drive one TTL load and a
90-pF capacitiv e load. They can also dr ive an LED or a Darlington transistor pair.
Port 5
P5 /A
P5 /A
P5 /A
P5 /A
3
2
1
0
19
18
17
16
A (output)
A (output)
A (output)
A (output)
19
18
17
16
P5 (input)/A (output)
P5 (input)/A (output)
P5 (input)/A (output)
P5 (input)/A (output)
3
2
1
0
Port 5
pins Modes 1, 3 Mode 5
P5 (input/output)
P5 (input/output)
P5 (input/output)
P5 (input/output)
3
2
1
0
Modes 6 and 7
19
18
17
16
Figure 7.12 Port 5 Pin Configuration
Section 7 I/O Ports
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7.5.2 Register Descriptions
Table 7.6 summarizes the registers of port 5.
Table 7.6 Port 5 Registers
Initial Value
Address*Name Abbreviation R/W Modes 1 and 3 Modes 5 to 7
H'FFC8 Port 5 data direction
register P5DDR W H'FF H'F0
H'FFCA Port 5 data register P5DR R/W H'F0 H'F0
H'FFDB Port 5 input pull-up
control register P5PCR R/W H'F0 H'F0
Note: *Lower 16 bits of the address .
Port 5 Data Direction Register (P5DDR)
P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5.
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
—
1
—
1
—
6
—
1
—
1
—
5
—
1
—
1
—
4
—
1
—
1
—
3
P5 DDR
1
—
0
W
3
2
P5 DDR
1
—
0
W
2
1
P5 DDR
1
—
0
W
1
0
P5 DDR
1
—
0
W
0
Reserved bits Port 5 data direction 3 to 0
These bits select input or
output for port 5 pins
P5DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P5DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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Port 5 Data Register (P5DR)
P5DR is an 8-b it r eadable/writable reg ister that stores data for pins P53 to P50.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
P5
0
R/W
3
2
P5
0
R/W
2
1
P5
0
R/W
1
0
P5
0
R/W
0
Reserved bits These bits store data
for port 5 pins
Port 5 data 3 to 0
When a bit in P5DDR is set to 1, if p o rt 5 is read the value of the corresp onding P5DR bit is
returned directly, regardless of the actual state of the pin. When a bit in P5DDR is cleared to 0, if
port 5 is read the corresponding pin level is read.
Bits P57 to P54 are reserved. They cannot be modified and are always read as 1.
P5DR is initialized to H'F0 by a reset and in hardware standby mod e . In so f twar e standby mode it
retains its previous setting .
Port 5 Input P ull- Up Control Register (P 5PCR)
P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port
5.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
P5 PCR
0
R/W
3
2
P5 PCR
0
R/W
2
1
P5 PCR
0
R/W
1
0
P5 PCR
0
R/W
0
Reserved bits These bits control input pull-up
transistors built into port 5
Port 5 input pull-up control 3 to 0
When a P5DDR bit is cleared to 0 (selecting generic input) in modes 5 to 7, if the corresponding
bit fro m P53PCR to P50PCR is set to 1, th e input pull-up tr ansistor is turned on.
P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting .
Section 7 I/O Ports
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7.5.3 Pin Functions in Each Mode
The pin functions differ between mode 1, 3 (expanded modes with on-chip ROM disabled), mode
5 (expanded modes with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin
functions in each mode are described below.
Modes 1 and 3
Address output can be selected for each pin in port 5. Figure 7.13 shows the pin functions in
modes 1 and 3.
Port 5
A (output)
A (output)
A (output)
A (output)
19
18
17
16
Figure 7.13 Pin Functions in Modes 1 and 3 (Port 5)
Mode 5
Address output or generic input can be selected for each pin in port 5. A pin becomes an address
output pin if the corresponding P5DDR bit is set to 1, and a generic input pin if this bit is cleared
to 0. Following a reset, all pins are input pins. To use a pin for address output, its P5DDR must be
set to 1. Figure 7.14 shows the pin functions in mode 5.
Port 5
A (output)
A (output)
A (output)
A (output)
19
18
17
16
When P5DDR = 1
P5 (input)
P5 (input)
P5 (input)
P5 (input)
3
2
1
0
When P5DDR = 0
Figure 7.14 Pin Functions in Mo de 5 (Port 5)
Section 7 I/O Ports
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REJ09B0353-0300
Modes 6 and 7
Input or output can be selected separately for each pin in port 5. A pin becomes an output pin if
the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.15
shows the pin functions in modes 6 and 7.
Port 5
P5 (input/output)
P5 (input/output)
P5 (input/output)
P5 (input/output)
3
2
1
0
Figure 7.15 Pin Functions in Mode 6 and 7 (Port 5)
7.5.4 Input Pull-Up Transistors
Port 5 has built-in MOS input pull-up tran sistors that can be controlled by software. These input
pull-up transistors can be turned on and off individually.
When a P5PCR bit is set to 1 and the corresponding P5DDR bit is cleared to 0, the input pull-up
transistor is tu r ned on.
The input pull-up transistors are turned off by a reset and in hardware standby mode. In software
standby mode they retain their previous state.
Table 7.7 summarizes the states of the input pull-up transistors in each mode.
Table 7.7 Input Pull- U p Transistor States (Port 5)
Mode Reset Hardware Standby Mode Software Standby Mode Other Modes
1
3Off Off Off Off
5
6
7
Off Off On/Off On/Off
Legend:
Off: The input pull-up transistor is always off.
On/Off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off.
Section 7 I/O Ports
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7.6 Port 6
7.6.1 Overview
Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR,
RD, AS, and WAIT).
Figure 7.16 shows the pin configuration of port 6. In modes 1, 3 and 5, the pin functions are WR,
RD, AS, and P60/WAIT. In modes 6 and 7, port 6 is a generic input/output port.
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair.
Port 6
P6 /
P6 /
P6 /
P6 /
5
4
3
0
WR
RD
AS
WAIT
Port 6 pins
WR
RD
AS
P6
0
Modes 1, 3 and 5
P6
P6
P6
P6
5
4
3
0
Modes 6 and 7
(input/output)
(input/output)
(input/output)
(input/output)
(output)
(output)
(output)
(input/output)/WAIT (input)
Figure 7.16 Port 6 Pin Configuration
Section 7 I/O Ports
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7.6.2 Register Descriptions
Table 7.8 summarizes the registers of port 6.
Table 7.8 Port 6 Registers
Initial Value
Address*Name Abbreviation R/W Modes 1, 3, and 5 Modes 6 and 7
H'FFC9 Port 6 data direction
register P6DDR W H'F8 H'80
H'FFCB Port 6 data register P6DR R/W H'80 H'80
Note: *Lower 16 bits of the address .
Port 6 Data Direction Register (P6DDR)
P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6.
Bit
Initial value
Read/Write
7
—
1
—
6
—
0
W
5
P6 DDR
0
W
5
4
P6 DDR
0
W
4
3
P6 DDR
0
W
3
2
—
0
W
1
—
0
W
0
P6 DDR
0
W
0
Port 6 data direction 5 to 3, 0
These bits select input or output for port 6 pins
Reserved bits
Bits 7, 6, 2, and 1 are reserved.
P6DDR is a write-only register. Its value cannot be read. All bits retu rn 1 wh en read.
P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P6DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Section 7 I/O Ports
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Port 6 Data Register (P6DR)
P6DR is an 8-b it r eadable/writable reg ister that stores data for pins P65 to P63 and P60.
Bit
Initial value
Read/Write
7
—
1
—
6
—
0
R/W
5
P6
0
R/W
5
4
P6
0
R/W
4
3
P6
0
R/W
3
2
—
0
R/W
1
—
0
R/W
0
P6
0
R/W
0
Reserved bits Port 6 data 5 to 3, 0
These bits store data for port 6 pins
When a bit in P6DDR is set to 1, if p o rt 6 is read the value of the corresp onding P6DR bit is
returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level
is read. Bits 7, 6, 2, and 1 are reserved. Bit 7 cannot be modified and always reads 1. Bits 6, 2, and
1 can be written and read, but cannot be used as por ts. If bit 6, 2, or 1 in P6DDR is r ead while its
value is 1, th e value of the corresponding bit in P6 DR will be read. If bit 6, 2, or 1 in P6DDR is
read while its valu e is 0, it will always read 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting .
Section 7 I/O Ports
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7.6.3 Pin Functions in Each Mode
Modes 1, 3, and 5
P65 to P63 function as bus control output pins. P60 is either a bus control input pin or generic
input/output pin, functioning as an output pin when bit P60DDR is set to 1 and an input pin when
this bit is cleared to 0. Figure 7.17 and table 7.9 indicate the pin functions in modes 1, 3, and 5.
Port 6
WR
RD
AS
P6
0
(input/output)/WAIT (input)
(output)
(output)
(output)
Figure 7.17 Pin Functions in Mo de s 1, 3, and 5 (Port 6)
Section 7 I/O Ports
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Table 7.9 Port 6 Pin Functions in Modes 1, 3, and 5
Pin Pin Functions and Selection Me thod
P65/WR Functions as follows regardless of P65DDR
P65DDR 0 1
Pin function WR output
P64/RD Functions as follows regardless of P64DDR
P64DDR 0 1
Pin function RD output
P63/AS Functions as follows regardless of P63DDR
P63DDR 0 1
Pin function AS output
P60/WAIT Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the pin
function as follow s
WCER All 1s Not all 1s
WMS1 0 1 —
P60DDR 0 1 0*0*
Pin function P60 input P60 output WAIT input
Note: *Do not set bit P60DDR to 1.
Section 7 I/O Ports
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Modes 6 and 7
Input or output can be selected separately for each pin in port 6. A pin becomes an output pin if
the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.18
shows the pin functions in modes 6 and 7.
Port 6
P6
P6
P6
P6
5
4
3
0
(input/output)
(input/output)
(input/output)
(input/output)
Figure 7.18 Pin Functions in Modes 6 and 7 (Port 6)
Section 7 I/O Ports
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7.7 Port 7
7.7.1 Overview
Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin
functions are the same in all operating modes. Figure 7.19 shows the pin configuration of port 7.
Port 7
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
P7 (input)/AN (input)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port 7 pins
Figure 7.19 Port 7 Pin Configuration
7.7.2 Register Description
Table 7.10 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction
register.
Table 7.10 Port 7 Data Register
Address*Name Abbreviation R/W Initial Value
H'FFCE Port 7 data register P7DR R Undetermined
Note: *Lower 16 bits of the address .
Section 7 I/O Ports
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Port 7 Data Register (P7DR)
Bit
Initial value
Read/Write
Note: * Determined by pins P7 to P0.
0
P7
—
R
*
0
1
P7
—
R
*
1
2
P7
—
R
*
2
3
P7
—
R
*
3
4
P7
—
R
*
4
5
P7
—
R
*
5
6
P7
—
R
*
6
7
P7
—
R
*
7
When P7DR is read, the pin levels are always read.
7.8 Port 8
7.8.1 Overview
Port 8 is a 2-bit input/output port that is also used for IRQ1 and IRQ0 input. Figure 7.20 shows the
pin configuration of port 8.
Pin P80 functions as input/output pin or as an IRQ0 input pin. Pins P81 function as either input pins
or IRQ1 input pins in modes 1, 3, and 5, and as input/output pins or IRQ1 input pins in modes 6 and
7.
Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a
Darlington transistor pair. Pins P81 and P80 have Schmitt-trigger inputs.
Port 8
Port 8 pins
P81 (input)/IRQ1 (input)
P80 (input/output)/IRQ0 (input)
Modes 1, 3, and 5
P81/IRQ1
P80/IRQ0
P81 (input/output)/IRQ1 (input)
P80 (input/output)/IRQ0 (input)
Modes 6 and 7
Figure 7.20 Port 8 Pin Configuration
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 165 of 682
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7.8.2 Register Descriptions
Table 7.11 summarizes the registers of port 8.
Table 7.11 Port 8 Registers
Address*Name Abbreviation R/W Initial Value
H'FFCD Port 8 data direction register P8DDR W H'E0
H'FFCF Port 8 data register P8DR R/W H'E0
Note: *Lower 16 bits of the address .
Port 8 Data Direction Register (P8DDR)
P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8.
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
W
3
—
0
W
2
—
0
W
1
P8 DDR
0
W
1
0
P8 DDR
0
W
0
Reserved bits Port 8 data direction 1 and 0
These bits select input or
output for port 8 pins
Bit
Initial value
Read/Write
P8DDR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P8DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
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Port 8 Data Register (P8DR)
P8DR is an 8-b it r eadable/writable reg ister that stores data for pins P81 to P80.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
R/W
3
—
0
R/W
2
—
0
R/W
1
P8
0
R/W
1
0
P8
0
R/W
0
Reserved bits Port 8 data 1 and 0
These bits store data
for port 8 pins
When a bit in P8DDR is set to 1, if p o rt 8 is read the value of the corresp onding P8DR bit is
returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level
is read.
Bits 7 to 2 are reserved. Bits 7 to 5 cannot be modified and always read 1. Bit 4, 3, and 2 can be
written and read, but it cannot be used for port input or output. If bit 4, 3, and 2 of P8DDR is read
while its value is 1, bit 4, 3 and 2 of P8DR is read directly. If bit 4, 3, and 2 of P8DDR is read
while its value is 0, it always reads 1.
P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting .
Section 7 I/O Ports
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7.8.3 Pin Functions
The port 8 pins are also used for IRQ1 and IRQ0. Table 7.12 describes the selection of pin
functions.
Table 7.12 Port 8 Pin Functions
Pin Pin Functions and Selection Method
P81/IRQ1Bit P81DDR selects the pin function as follows
P81DDR 0 1
Modes 1, 3, and 5 Modes 6 and 7
Pin function P81 input Illegal setting P81 output
IRQ1 input
P80/IRQ0Bit P80DDR selects the pin function as follows
P80DDR 0 1
Pin function P80 input P80 output
IRQ0 input
Section 7 I/O Ports
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7.9 Port 9
7.9.1 Overview
Port 9 is a 6-bit input/output port that is also used for input and output (TxD 0, TxD1, RxD0, RxD1,
SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5
and IRQ4 input.
Port 9 has the same set of pin functions in all operating modes. Figure 7.21 shows the pin
configuration of port 9.
Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a
Darlington transistor pair.
Port 9
P9 (input/output)/SCK
P9 (input/output)/SCK
P9 (input/output)/RxD (input)
P9 (input/output)/RxD (input)
P9 (input/output)/TxD (output)
P9 (input/output)/TxD (output)
5
4
3
2
1
0
Port 9 pins
1
0
(input/output)/IRQ (input)
(input/output)/IRQ (input)
5
4
1
0
1
0
Figure 7.21 Port 9 Pin Configuration
7.9.2 Register Descriptions
Table 7.13 summarizes the registers of port 9.
Table 7.13 Port 9 Registers
Address*Name Abbreviation R/W Initial Value
H'FFD0 Port 9 data direction register P9DDR W H'C0
H'FFD2 Port 9 data register P9DR R/W H'C0
Note: *Lower 16 bits of the address .
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Port 9 Data Direction Register (P9DDR)
P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P9 DDR
0
W
5
4
P9 DDR
0
W
4
3
P9 DDR
0
W
3
2
P9 DDR
0
W
2
1
P9 DDR
0
W
1
0
P9 DDR
0
W
0
Reserved bits Port 9 data direction 5 to 0
These bits select input or
output for port 9 pins
A pin in port 9 becomes an output pin if the corresponding P9DDR bit is set to 1, and an input pin
if this bit is cleared to 0.
P9DDR is a write-only register. Its value cannot be read. All bits retu rn 1 when read.
P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode
it retains its previous setting. I f a P9DDR bit is set to 1, the corresponding pin maintains its output
state in software standby mode.
Port 9 Data Register (P9DR)
P9DR is an 8-bit readable/writable register that stores output data for pins P95 to P90.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P9
0
R/W
4
P9
0
R/W
4
3
P9
0
R/W
3
2
P9
0
R/W
2
1
P9
0
R/W
1
0
P9
0
R/W
0
Reserved bits Port 9 data 5 to 0
These bits store data
for port 9 pins
5
When a bit in P9DDR is set to 1, if p o rt 9 is read the value of the corresp onding P9DR bit is
returned . When a bit in P9DDR is cleared to 0, if por t 9 is read the corresponding pin level is read.
Bits 7 and 6 are reserved. They cannot be modified and are always read as 1.
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 170 of 682
REJ09B0353-0300
P9DR is initia lized to H'C0 by a r e set and in hardware standby m ode . In so ftware standby mode it
retains its previous setting .
7.9.3 Pin Functions
The port 9 pins are also used for SCI input and output (TxD, RxD, SCK), and for IRQ5 and IRQ4
input. Table 7.14 describes the selection of pin functions.
Table 7.14 Port 9 Pin Functions
Pin Pin Functions and Selection Method
P95/SCK1/
IRQ5
Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P95DDR select
the pin function as follows
CKE1 0 1
C/A01—
CKE0 0 1 ——
P95DDR 0 1 ———
Pin function P95
input P95
output SCK1 output SCK1 output SCK1 input
IRQ5 input
P94/SCK0/
IRQ4
Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI, and bit P94DDR select
the pin function as follows
CKE1 0 1
C/A01—
CKE0 0 1 ——
P94DDR 0 1 ———
Pin function P94
input P94
output SCK0 output SCK0 output SCK0 input
IRQ4 input
Section 7 I/O Ports
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REJ09B0353-0300
Pin Pin Functions and Selection Method
P93/RxD1Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows
RE 0 1
P93DDR 0 1 —
Pin function P93 input P93 output RxD1 input
P92/RxD0Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as
follows
SMIF 0 1
RE 0 1 —
P92DDR 0 1 ——
Pin function P92 input P92 output RxD0 input RxD0 input
P91/TxD1Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows
TE 0 1
P91DDR 0 1 —
Pin function P91 input P91 output TxD1 output
P90/TxD0Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function as
follows
SMIF 0 1
TE 0 1 —
P90DDR 0 1 ——
Pin function P90 input P90 output TxD0 output TxD0 output*
Note: *Functions as the TxD0 output pin, but there are two states: one in which
the pin is driven, and another in which the pin is at high impedance.
Section 7 I/O Ports
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REJ09B0353-0300
7.10 Port A
7.10.1 Overview
Port A is an 8-bit input/output port th at is also used for output ( T P7 to TP0) from the programmable
timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0,
TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), and
address output (A23 to A20). Figure 7.22 shows the pin configuration of port A.
Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a
Darlington transistor pair. Port A has Schmitt-trigger inputs.
Port A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /A
PA /TP /TIOCA /A
PA /TP /TIOCB /TCLKD
PA /TP /TIOCA /TCLKC
PA /TP /TCLKB
PA /TP /TCLKA
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)
PA (input/output)/TP (output)/TIOCA (input/output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Port A pins Modes 1, 5 and 7
7
6
5
4
3
2
1
0
20
21
22
23
2
2
1
1
0
0
2
2
1
1
0
0
A (output)
PA (input/output)/TP (output)/TIOCA (input/output) /A (output)
PA (input/output)/TP (output)/TIOCB (input/output) /A (output)
PA (input/output)/TP (output)/TIOCA (input/output) /A (output)
PA (input/output)/TP (output)/TIOCB (input/output)/TCLKD (input)
PA (input/output)/TP (output)/TIOCA (input/output)/TCLKC (input)
PA (input/output)/TP (output)/TCLKB (input)
PA (input/output)/TP (output)/TCLKA (input)
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Mode 3
2
1
1
21
22
23
0
0
20
Figure 7.22 Port A Pin Configuration
Section 7 I/O Ports
Rev.3.00 Mar. 26, 2007 Page 173 of 682
REJ09B0353-0300
7.10.2 Register Descriptions
Table 7.15 summarizes the registers of port A.
Table 7.15 Port A Registers
Initial Value
Address*Name Abbreviation R/W Modes 1, 5, and 7 Mode 3
H'FFD1 Port A data direction
register PADDR W H'00 H'80
H'FFD3 Port A data register PADR R/W H'00 H'00
Note: *Lower 16 bits of the address .
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. The
corresponding PADDR bit should also be set when a pin is used as a TPC output.
7
PA DDR
0
W
1
—
Port A data direction 7 to 0
These bits select input or output for port A pins
7
6
PA DDR
0
W
0
W
6
5
PA DDR
0
W
0
W
5
4
PA DDR
0
W
0
W
4
3
PA DDR
0
W
0
W
3
2
PA DDR
0
W
0
W
2
1
PA DDR
0
W
0
W
1
0
PA DDR
0
W
0
W
0
Bit
Initial value
Read/Write
Initial value
Read/Write
Modes
1, 5, and 7
Mode 3
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. However, in mode 3, PA7 DDR is fixed at 1, and PA7 functions as an
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 in mod es 1, 5 and 7 and to H'80 in mode 3 by a reset and in
hardware standby mode. In software standby mode it retains its prev ious setting . If a PADDR bit
is set to 1, the corresponding pin maintains its output state in software standby mode.
Section 7 I/O Ports
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Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores data for pins PA7 to PA0.
Bit
Initial value
Read/Write
0
PA
0
R/W
0
1
PA
0
R/W
1
2
PA
0
R/W
2
3
PA
0
R/W
3
4
PA
0
R/W
4
5
PA
0
R/W
5
6
PA
0
R/W
6
7
PA
0
R/W
7
Port A data 7 to 0
These bits store data for port A pins
When a bit in PADDR is set to 1, if port A is read the value of the correspond in g PADR bit is
returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin
level is read.
PADR is initialized to H'00 by a reset and in hardware standby mode. In sof twar e standby mode it
retains its previous setting .
When port A pins are used for TPC output, PADR stores output data for TPC output groups 0 and
1. If a bit in the next data enable register (NDERA) is set to 1, the corresponding PADR bit cannot
be written. In this case, PADR can be updated only when data is transferred from NDRA.
Section 7 I/O Ports
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REJ09B0353-0300
7.10.3 Pin Functions
The port A pins are also used for TPC output (TP7 to TP0), ITU input/output (TIOCB2 to TI OCB0,
TIOCA2 to TIOCA0) and input (TCLKD, TCLKC, TCLKB, TCLKA), and as address bus pins (A23
to A20). Table 7.16 describes the selection of pin functions.
Table 7.16 Port A P in F unctions
Pin Pin Functions and Selection Method
PA7/TP7/
TIOCB2/
A20
The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0
in TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function
as follows
Mode 1, 5 to 7 3
ITU channel 2
settings (1) in table below (2) in table below —
PA7DDR —011—
NDER7 ——01—
Pin function TIOCB2 output PA7
input PA7
output TP7
output A20
output
TIOCB2 input*
Note: *TIOCB2 input when IOB2 = 1 and PWM2 = 0.
ITU channel 2
settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PA6/TP6/
TIOCA2/
A21
The mode setting, bit A21E in BRCR, ITU channel 2 settings (bit PWM2 in TMDR and
bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA6DDR in PADDR s elect
the pin function as follows
Mode 1, 5 to 7 3
A21E — 10
ITU
channel 2
settings
(1) in
table
below
(2) in table below (1) in
table
below
(2) in table below —
PA6DDR —011—011—
NDER6 ——01—— 01—
Pin
function TIOCA
2
output PA6
input PA6
output TP6
output TIOCA
2
output PA6
input PA6
output TP6
output A21
output
TIOCA2 input*TIOCA2 input*
Note: *TIOCA2 input when IOA2 = 1.
ITU
channel 2
settings (2) (1) (2) (1)
PWM2 0 1
IOA2 0 1 —
IOA1 0 0 1 ——
IOA0 0 1 —— —
Section 7 I/O Ports
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REJ09B0353-0300
Pin Pin Functions and Selection Method
PA5/TP5/
TIOCB1/
A22
The mode setting, bit A22E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and
bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit PA5DDR in PADDR s elect
the pin function as follows
Mode 1, 5 to 7 3
A22E — 10
ITU
channel 1
settings
(1) in
table
below
(2) in table below (1) in
table
below
(2) in table below —
PA5DDR —011—011—
NDER5 —— 01——01—
Pin
function TIOCB
1
output PA5
input PA5
output TP5
output TIOCB
1
output PA5
input PA5
output TP5
output A22
output
TIOCB1 input*TIOCB1 input*
Note: *TIOCB1 input when IOB2 = 1 and PWM1 = 0.
ITU
channel 1
settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
Section 7 I/O Ports
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REJ09B0353-0300
Pin Pin Functions and Selection Method
PA4/TP4/
TIOCB1/
A23
The mode setting, bit A23E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and
bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA4DDR in PADDR s elect
the pin function as follows
Mode 1, 5 to 7 3
A23E — 10
ITU
channel 1
settings
(1) in
table
below
(2) in table below (1) in
table
below
(2) in table below —
PA4DDR —011—011—
NDER4 —— 01——01—
Pin
function TIOCA
1
output PA4
input PA4
output TP5
output TIOCA
1
output PA4
input PA4
output TP4
output A23
output
TIOCA1 input*TIOCA1 input*
Note: *TIOCA1 input when IOA2 = 1.
ITU
channel 1
settings (2) (1) (2) (1)
PWM1 0 1
IOA2 0 1 —
IOA1 001——
IOA0 0 1 —— —
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PA3/TP3/
TIOCB0/
TCLKD
ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits
TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in
PADDR select the pin function as follows
ITU
channel 0
settings
(1) in table below (2) in table below
PA3DDR —011
NDER3 ——01
TIOCB0 output PA3 input PA3 output TP3 outputPin
function TIOCB0 input*1
TCLKD input*2
Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0.
2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to
TCR0.
ITU
channel 0
settings (2) (1) (2)
IOB2 0 1
IOB1 0 0 1 —
IOB0 0 1 ——
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Pin Pin Functions and Selection Method
PA2/TP2/
TIOCA0/
TCLKC
ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits
TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA
2
DDR in PADDR
select the pin function as follows
ITU
channel 0
settings
(1) in table below (2) in table below
PA2DDR —011
NDER2 ——01
TIOCA0 output PA2 input PA2 output TP2 outputPin
function TIOCA0 input*1
TCLKC input*2
Notes: 1. TIOCA0 input when IOA2 = 1.
2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to
TCR0.
ITU
channel 0
settings (2) (1) (2) (1)
PWM0 0 1
IOA2 0 1 —
IOA1 001——
IOA0 0 1 —— —
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PA1/TP1/
TCLKB Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function as follows
PA1DDR 0 1 1
NDER1 —01
PA1 input PA1 output TP1 outputPin
function TCLKB input*
Note: *TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0,
and TPSC0 = 1 in any of TCR4 to TCR0.
PA0/TP0/
TCLKA Bit NDER0 in NDERA and bit PA0DDR in PADDR select the pin function as follows
PA0DDR 0 1 1
NDER0 —01
PA0 input PA0 output TP0 outputPin
function TCLKA input*
Note: *TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 =
TPSC0 = 0 in any of TCR4 to TCR0.
Section 7 I/O Ports
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7.11 Port B
7.11.1 Overview
Port B is a 7-bit input/output port that is also used for TPC output (TP15, TP13 to TP8), ITU
input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3) and ITU output (TOCXB4, TOCXA4), and
ADTRG input to the A/D converter. Port B has the same set of pin functions in all operating
modes. Figure 7.23 shows the pin configuration of port B.
Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive an LED or
a Darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs.
Port B
PB (input/output)/TP (output)/ADTRG (input)
PB (input/output)/TP (output)/TOCXB (output)
PB (input/output)/TP (output)/TOCXA (output)
7
5
4
3
2
1
0
Port B pins
15
13
12
11
10
9
8
4
4
PB (input/output)/TP (output)/TIOCB (input/output)
PB (input/output)/TP (output)/TIOCA (input/output)
PB (input/output)/TP (output)/TIOCB (input/output)
PB (input/output)/TP (output)/TIOCA (input/output)
4
4
3
3
Figure 7.23 Port B Pin Configuration
7.11.2 Register Descriptions
Table 7.17 summarizes the registers of port B.
Table 7.17 Port B Registers
Address*Name Abbreviation R/W Initial Value
H'FFD4 Port B data direction register PBDDR W H'00
H'FFD6 Port B data register PBDR R/W H'00
Note: *Lower 16 bits of the address .
Section 7 I/O Ports
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Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that can select input or output for each pin in port B.
Bit
Initial value
Read/Write
7
PB DDR
0
W
7
6
—
0
W
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
Port B data 7, 5 to 0
These bits select input or output for port B pins
Reserved bit
A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin
if this bit is cleared to 0.
Bit 6 is reserv ed.
PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read .
PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software stan dby mode
it retains its previous setting. I f a PBDDR bit is set to 1, th e corresponding pin maintains its output
state in software standby mode.
Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable r egister th at stores data for pins PB7, PB5 to PB0.
Bit
Initial value
Read/Write
0
PB
0
R/W
0
1
PB
0
R/W
1
2
PB
0
R/W
2
3
PB
0
R/W
3
4
PB
0
R/W
4
5
PB
0
R/W
5
6
—
0
R/W
7
PB
0
R/W
7
Port B data 7, 5 to 0
These bits store data for port B pins
Reserved bit
When a bit in PBDDR is set to 1, if port B is read th e value of the correspond ing PBDR bit is
returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin
level is read. Bit 6 is reserved. Bit 6 can be written and read, but cannot be used for a port input or
output.
Section 7 I/O Ports
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If bit 6 in PBDDR is read while its value is 1, the value of bit 6 in PBDR will be r ead directly. If
bit 6 in PBDDR is read while its value is 0, it will alway s b e read as 1.
PBDR is initialized to H'00 by a reset an d in hardware standby mode. In sof twar e standby mode it
retains its previous setting .
When port B pins are used for TPC output, PBDR stores output data for TPC output groups 2 and
3. If a bit in the next data enable register (NDERB) is set to 1, the corresponding PBDR bit cannot
be written. In this case, PBDR can be updated only when data is transferred from NDRB.
7.11.3 Pin Functions
The port B pins are also used for TPC output (TP15, TP13 to TP8), ITU input/output (TIOCB4,
TIOCB3, TIOCA4, TIOCA3) and output (TOCXB4, TOCXA4), and ADTRG input. Table 7.18
describes the selection of pin functions.
Section 7 I/O Ports
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Table 7.18 Po rt B Pin Functions
Pin Pin Functions and Selection Method
Bit TRGE in ADCR, bit NDER15 in NDERB and bi t PB7DDR in PBDDR select the pin
function as follow s
PB7/
TP15/
ADTRG PB7DDR 0 1 1
NDER15 —01
Pin function PB7 input PB7 output TP15 output
ADTRG input*
Notes: *ADTRG input when TRGE = 1.
ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in
NDERB, and bit PB5DDR in PBDDR select the pin function as follows
PB5/
TP13/
TOCXB4EXB4,
CMD1 Not both 1 Both 1
PB5DDR 0 1 1 —
NDER13 —01 —
Pin function PB5 input PB5 output TP13 output TOCX B4 output
ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in
NDERB, and bit PB4DDR in PBDDR select the pin function as follows
PB4/
TP12/
TOCXA4EXA4,
CMD1 Not both 1 Both 1
PB4DDR 0 1 1 —
NDER12 —01 —
Pin function PB4 input PB4 output TP12 output TOCX A4 output
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PB3/
TP11/
TIOCB4
ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and
bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB
3
DDR in PBDDR select
the pin function as follows
ITU channel
4 settings (1) in table below (2) in table below
PB3DDR —01 1
NDER11 ——01
Pin function TIOCB4 output PB3 input PB3 output TP11 output
TIOCB4 input*
Note: *TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1.
ITU channel
4 settings (2) (2) (1) (2) (1)
EB4 0 1
CMD1 —01
IOB2 —0001—
IOB1 —001——
IOB0 —01———
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PB2/
TP10/
TIOCA4
ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and
bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB
2
DDR in PBDDR select
the pin function as follows
ITU channel
4 settings (1) in table below (2) in table below
PB2DDR —011
NDER11 ——01
Pin function TIOCA4 output PB2 input PB2 output TP10 output
TIOCA4 input*
Note: *TIOCA4 input when CMD1 = PWM4 = 0 and IOB2 = 1.
ITU channel
4 settings (2) (2) (1) (2) (1)
EA4 0 1
CMD1 —01
PWM4 —01—
IOA2 —0001——
IOA1 —001———
IOA0 —01————
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PB1/TP9/
TIOCB3
ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and
bits IOB2 to IOB0 in TIOR3), bit NDER11 in NDERB, and bit PB
1
DDR in PBDDR select
the pin function as follows
ITU channel
3 settings (1) in table below (2) in table below
PB1DDR —011
NDER9 ——01
Pin function TIOCB3 output PB1 input PB1 output TP9 output
TIOCB3 input*
Note: *TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1.
ITU channel
3 settings (2) (2) (1) (2) (1)
EB3 0 1
CMD1 —01
IOB2 —0001—
IOB1 —001——
IOB0 —01———
Section 7 I/O Ports
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Pin Pin Functions and Selection Method
PB0/TP8/
TIOCA3
ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and
bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR s elect
the pin function as follows
ITU channel
3 settings (1) in table below (2) in table below
PB0DDR —011
NDER8 ——01
Pin function TIOCA3 output PB0 input PB0 output TP8 output
TIOCA3 input*
Note: *TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1.
ITU channel
3 settings (2) (2) (1) (2) (1)
EA3 0 1
CMD1 —01
PWM3 —01—
IOA2 —0001——
IOA1 —001———
IOA0 —01————
Section 7 I/O Ports
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Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 191 of 682
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Section 8 16-Bit Integrated Timer Unit (ITU )
8.1 Overview
The H8/3039 Gr oup has a built-in 16-b it integrated timer-pulse unit (ITU) with five 16-bit timer
channels.
8.1.1 Features
ITU features are listed below.
• Capability to process up to 12 pulse outputs or 10 pulse inputs
• Ten general registers (GRs, two per channel) with independently-assignable ou tput compare or
input capture functions
• Selection of eight counter clock sources for each channel:
Internal clocks: φ, φ/2, φ/4, φ/8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
• Five operating modes selectable in all channels:
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
Input capture function
Rising edge, falling edge, or both edges (selectable)
Counter clearing function
Counters can be cleared by compare match or input capture
Synchronization
Two or more timer counters (TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
five-phase PWM output is possible
• Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
Section 8 16-Bit Integrated Timer Unit (ITU)
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• Three additional modes selectable in channels 3 and 4
Reset-synchronized PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
complementary waveforms.
Complementary PWM mode
If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of
non-overlapping complementary waveforms.
Buffering
Input capture registers can be double-buffered. Output compare registers can be updated
automatically.
• High-speed access via internal 16-bit bus
The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed
via a 16-bit bus.
• Fifteen interrupt sources
Each channel has two compare match/input capture interrupts and an ov erflow interrupt. All
interrupts can be requested independently.
• Output triggering of programmable pattern controller (TPC)
Compare match/inpu t capture signals from channels 0 to 3 can be used as TPC output triggers.
Table 8.1 summarizes the ITU functions.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 193 of 682
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Table 8.1 ITU F unctions
Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4
Clock source s Internal clocks: φ, φ/2, φ/4 , φ/8
External clocks: TCL KA, TCLKB, TCLKC, TCLKD , selecta bl e i ndependently
General regist ers
(output compare/
input capture registers)
GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4
Buffer registers — — — BRA3, BRB3 BRA4, BRB4
Input/output pi ns TIOCA0, TIOCB0TIOCA1, TIOCB1TIOCA2, TIOCB 2TIOCA3, T IO C B3TIOCA4, TIOCB 4
Output pins — — — — TOCXA4,
TOCXB4
Counter cleari ng
function GRA0/GRB0
compare match
or input capture
GRA1/GRB1
compare match
or input capture
GRA2/GRB2
compare match
or input capture
GRA3/GRB3
compare match
or input capture
GRA4/GRB4
compare match
or input capture
0OOOOO
1OOOOO
Compare
match
output Toggle O O — O O
Input capture function O O O O O
Synchronization O O O O O
PWM modeOOOOO
Reset-synchronized
PWM mode ———O O
Complementary PWM
mode ———O O
Phase counting mode — — O — —
Buffering — — — O O
Interrupt sources Three sources
• Compare
match/input
capture A0
• Compare
match/input
capture B0
•Overflow
Three sources
• Compare
match/input
capture A1
• Compare
match/input
capture B1
•Overflow
Three sources
• Compare
match/input
capture A2
• Compare
match/input
capture B2
•Overflow
Three sources
• Compare
match/input
capture A3
• Compare
match/input
capture B3
•Overflow
Three sources
• Compare
match/input
capture A4
• Compare
match/input
capture B4
•Overflow
Legend:
O: Available
—: Not available
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 194 of 682
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8.1.2 Block Diagrams
ITU Block Diagram (Overall)
Figure 8.1 is a block diagram of the ITU.
16-bit timer channel 4
16-bit timer channel 3
16-bit timer channel 2
16-bit timer channel 1
16-bit timer channel 0
Module data bus
Bus interface
Internal data bus
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TOCXA4, TOCXB4
Clock selector
Control logic
TIOCA0 to TIOCA4
TIOCB0 to TIOCB4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
TOER:
TOCR:
TSTR:
TSNC:
TMDR:
TFCR:
Legend:Timer output master enable register (8 bits)
Timer output control register (8 bits)
Timer start register (8 bits)
Timer synchro register (8 bits)
Timer mode register (8 bits)
Timer function control register (8 bits)
Figure 8.1 ITU Block Diagram (Overall)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Block Diagram of Channels 0 and 1
ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2.
Clock selector
Comparator
Control logic
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA
0
TIOCB
0
IMIA0
IMIB0
OVI0
TCNT
GRA
GRB
TCR
TIOR
TIER
TSR
Module data bus
Legend:
TCNT:
GRA, GRB:
TCR:
TIOR:
TIER:
TSR:
Timer counter (16 bits)
General registers A and B (input capture/output compare registers) (16 bits 2)
Timer control register (8 bits)
Timer I/O control register (8 bits)
Timer interrupt enable register (8 bits)
Timer status register (8 bits)
×
Figure 8.2 Block Diagram of Channels 0 and 1 (for Channel 0)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Block Diagram of Channel 2
Figure 8.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1
output.
Clock selector
Comparator Control logic
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TIOCA
2
TIOCB
2
IMIA2
IMIB2
OVI2
TCNT2
GRA2
GRB2
TCR2
TIOR2
TIER2
TSR2
Module data bus
Legend:
TCNT2:
GRA2, GRB2:
TCR2:
TIOR2:
TIER2:
TSR2:
Timer counter 2 (16 bits)
General registers A2 and B2 (input capture/output compare registers)
(16 bits 2)
Timer control register 2 (8 bits)
Timer I/O control register 2 (8 bits)
Timer interrupt enable register 2 (8 bits)
×
Timer status register 2 (8 bits)
Figure 8.3 Block Diagram of Channel 2
Section 8 16-Bit Integrated Timer Unit (ITU)
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Block Diagrams of Channels 3 and 4
Figure 8.4 is a block diagram of channel 3. Figure 8.5 is a block diagram of channel 4.
TCNT3
BRA3
Legend:
TCNT3:
GRA3, GRB3:
BRA3, BRB3:
TCR3:
TIOR3:
TIER3:
TSR3:
Timer counter 3 (16 bits)
General registers A3 and B3 (input capture/output compare registers)
(16 bits 2)
Buffer registers A3 and B3 (input capture/output compare buffer registers)
(16 bits 2)
Timer control register 3 (8 bits)
Clock selector
Comparator
Control logic
GRA3
BRB3
GRB3
TCR3
TIOR3
TIER3
TSR3
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
TIOCA
3
TIOCB
3
Module data bus
×
IMIA3
IMIB3
OVI3
Timer I/O control register 3 (8 bits)
Timer interrupt enable register 3 (8 bits)
Timer status register 3 (8 bits)
×
Figure 8.4 Block Diagram of Channel 3
Section 8 16-Bit Integrated Timer Unit (ITU)
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TCNT4
BRA4
Legend:
TCNT4:
GRA4, GRB4:
BRA4, BRB4:
TCR4:
TIOR4:
TIER4:
TSR4:
Timer counter 4 (16 bits)
General registers A4 and B4 (input capture/output compare registers)
(16 bits 2)
Buffer registers A4 and B4 (input capture/output compare buffer registers)
(16 bits 2)
Timer control register 4 (8 bits)
Clock selector
Comparator Control logic
GRA4
BRB4
GRB4
TCR4
TIOR4
TIER4
TSR4
Module data bus
×
TCLKA to
TCLKD
φ, φ/2,
φ/4, φ/8
Timer I/O control register 4 (8 bits)
Timer interrupt enable register 4 (8 bits)
Timer status register 4 (8 bits)
×
TOCXA
4
TOCXB
4
TIOCA
4
TIOCB
4
IMIA4
IMIB4
OVI4
Figure 8.5 Block Diagram of Channel 4
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.1.3 Input/Out put Pins
Table 8.2 summarizes the ITU pins.
Table 8.2 ITU Pins
Channel Name Abbre-
viation Input/
Output Function
Common Clock input A TCLKA Input External clock A input pin
(phase-A input pin in phase cou ntin g
mode)
Clock input B TCLKB Input External clock B input pin
(phase-B input pin in phase cou ntin g
mode)
Clock input C TCLKC Input External clock C inpu t pin
Clock input D TCLKD Input External clock D inpu t pin
0 Input capture/output
compare A0 TIOCA0Input/
output GRA0 output compare or input capture pin
PWM output pin in PWM mode
Input capture/ outp ut
compare B0 TIOCB0Input/
output GRB0 output compare or input capture pin
1 Input capture/output
compare A1 TIOCA1Input/
output GRA1 output compare or input capture pin
PWM output pin in PWM mode
Input capture/ outp ut
compare B1 TIOCB1Input/
output GRB1 output compare or input capture pin
2 Input capture/output
compare A2 TIOCA2Input/
output GRA2 output compare or input capture pin
PWM output pin in PWM mode
Input capture/ outp ut
compare B2 TIOCB2Input/
output GRB2 output compare or input capture pin
3 Input capture/output
compare A3 TIOCA3Input/
output GRA3 output compare or input capture pin
PWM output pin in PWM mode,
complementary PWM mode, or reset-
synchronized PWM mode
Input capture/ outp ut
compare B3 TIOCB3Input/
output GRB3 output compare or input capture pin
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Section 8 16-Bit Integrated Timer Unit (ITU)
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Channel Name Abbre-
viation Input/
Output Function
4 Input capture/output
compare A4 TIOCA4Input/
output GRA4 output compare or input capture pin
PWM output pin in PWM mode,
complementary PWM mode, or reset-
synchronized PWM mode
Input capture/ outp ut
compare B4 TIOCB4Input/
output GRB4 output compare or input capture pin
PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Output compare XA4 TOCXA4Output PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Output compare XB4 TOCXB4Output PWM output pin in complementary PWM
mode or reset-synchronized PWM mode
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.1.4 Register Configuration
Table 8.3 summarizes the ITU registers.
Table 8.3 ITU Registers
Channel Address*1Name Abbre-
viation R/W Initial
Value
Common H'FF60 Timer start register TSTR R/W H'E0
H'FF61 Timer synchro register TSNC R/W H'E0
H'FF62 Timer mode register TMDR R/W H'80
H'FF63 Timer function control register TFCR R/W H'C0
H'FF90 Timer output master enable register TOER R/W H'FF
H'FF91 Timer output control register TOCR R/W H'FF
0 H'FF64 Timer contro l regist er 0 TCR0 R/W H'80
H'FF65 Timer I/O control register 0 TIOR0 R/W H'88
H'FF66 Timer interrupt enable register 0 TIER0 R/W H'F8
H'FF67 Timer status register 0 TSR0 R/(W)*2H'F8
H'FF68 Timer counter 0 (high) TCNT0H R/W H'00
H'FF69 Timer counter 0 (low) TCNT0L R/W H'00
H'FF6A General register A0 (high) GRA0H R/W H'FF
H'FF6B General register A0 (low) GRA0L R/W H'FF
H'FF6C General register B0 (high) GRB0H R/W H'FF
H'FF6D General register B0 (low) GRB0L R/W H'FF
1 H'FF6E Timer control register 1 TCR1 R/W H'80
H'FF6F Timer I/O control register 1 TIOR1 R/W H'88
H'FF70 Timer interrupt enable register 1 TIER1 R/W H'F8
H'FF71 Timer status register 1 TSR1 R/(W)*2H'F8
H'FF72 Timer counter 1 (high) TCNT1H R/W H'00
H'FF73 Timer counter 1 (low) TCNT1L R/W H'00
H'FF74 General register A1 (high) GRA1H R/W H'FF
H'FF75 General register A1 (low) GRA1L R/W H'FF
H'FF76 General register B1 (high) GRB1H R/W H'FF
H'FF77 General register B1 (low) GRB1L R/W H'FF
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 202 of 682
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Channel Address*1Name Abbre-
viation R/W Initial
Value
2 H'FF78 Timer control register 2 TCR2 R/W H'80
H'FF79 Timer I/O control register 2 TIOR2 R/W H'88
H'FF7A Timer interrupt enable register 2 TIER2 R/W H'F8
H'FF7B Timer status register 2 TSR2 R/(W)*2H'F8
H'FF7C Timer counter 2 (high) TCNT2H R/W H'00
H'FF7D Timer counter 2 (low) TCNT2L R/W H'00
H'FF7E General register A2 (high) GRA2H R/W H'FF
H'FF7F General register A2 (low) GRA2L R/W H'FF
H'FF80 General register B2 (high) GRB2H R/W H'FF
H'FF81 General register B2 (low) GRB2L R/W H'FF
3 H'FF82 Timer control register 3 TCR3 R/W H'80
H'FF83 Timer I/O control register 3 TIOR3 R/W H'88
H'FF84 Timer interrupt enable register 3 TIER3 R/W H'F8
H'FF85 Timer status register 3 TSR3 R/(W)*2H'F8
H'FF86 Timer counter 3 (high) TCNT3H R/W H'00
H'FF87 Timer counter 3 (low) TCNT3L R/W H'00
H'FF88 General register A3 (high) GRA3H R/W H'FF
H'FF89 General register A3 (low) GRA3L R/W H'FF
H'FF8A General register B3 (high) GRB3H R/W H'FF
H'FF8B General register B3 (low) GRB3L R/W H'FF
H'FF8C Buffer register A3 (high) BRA3H R/W H'FF
H'FF8D Buffer register A3 (low) BRA3L R/W H'FF
H'FF8E Buffer register B3 (high) BRB3H R/W H'FF
H'FF8F Buffer register B3 (low) BRB3L R/W H'FF
Section 8 16-Bit Integrated Timer Unit (ITU)
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Channel Address*1Name Abbre-
viation R/W Initial
Value
4 H'FF92 Timer control register 4 TCR4 R/W H'80
H'FF93 Timer I/O control register 4 TIOR4 R/W H'88
H'FF94 Timer interrupt enable register 4 TIER4 R/W H'F8
H'FF95 Timer status register 4 TSR4 R/(W)*2H'F8
H'FF96 Timer counter 4 (high) TCNT4H R/W H'00
H'FF97 Timer counter 4 (low) TCNT4L R/W H'00
H'FF98 General register A4 (high) GRA4H R/W H'FF
H'FF99 General register A4 (low) GRA4L R/W H'FF
H'FF9A General register B4 (high) GRB4H R/W H'FF
H'FF9B General register B4 (low) GRB4L R/W H'FF
H'FF9C Buffer register A4 (high) BRA4H R/W H'FF
H'FF9D Buffer register A4 (low) BRA4L R/W H'FF
H'FF9E Buffer register B4 (high) BRB4H R/W H'FF
H'FF9F Buffer register B4 (low) BRB4L R/W H'FF
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2 Register Descriptions
8.2.1 Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that starts and stop s the timer counter (TCNT) in
channels 0 to 4.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
STR4
0
R/W
3
STR3
0
R/W
2
STR2
0
R/W
1
STR1
0
R/W
0
STR0
0
R/W
Reserved bits Counter start 4 to 0
These bits start and
stop TCNT4 to TCNT0
TSTR is initialized to H'E0 by a reset and in standby mode.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4).
Bit4
STR4 Description
0 TCNT4 is halted (Initial val ue)
1 TCNT4 is counting
Bit 3—Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3).
Bit 3
STR3 Description
0 TCNT3 is halted (Initial val ue)
1 TCNT3 is counting
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bit 2—Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2).
Bit 2
STR2 Description
0 TCNT2 is halted ( Initi al val ue)
1 TCNT2 is counting
Bit 1—Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1).
Bit 1
STR1 Description
0 TCNT1 is halted ( Initi al val ue)
1 TCNT1 is counting
Bit 0—Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0).
Bit 0
STR0 Description
0 TCNT0 is halted ( Initi al val ue)
1 TCNT0 is counting
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.2 Timer Synchro Register (TSNC)
TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate
independently or synchronously. Channels are synchronized by setting the corresponding bits to 1.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
SYNC4
0
R/W
3
SYNC3
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
Reserved bits Timer sync 4 to 0
These bits synchronize
channels 4 to 0
TSNC is initialized to H'E0 by a reset and in stan dby mode.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or
synchronously.
Bit 4
SYNC4 Description
0 Channel 4's timer counter (TCNT4) operates independently TCNT4 is preset and
cleared inde pen dent ly of other channels (Initi al val ue)
1 Channel 4 operates synchronously
TCNT4 can be synchronously preset and cleared
Bit 3—Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or
synchronously.
Bit 3
SYNC3 Description
0 Channel 3's timer counter (TCNT3) operates independently TCNT3 is preset and
cleared inde pen dent ly of other channels (Initi al val ue)
1 Channel 3 operates synchronously
TCNT3 can be synchronously preset and cleared
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bit 2—Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or
synchronously.
Bit 2
SYNC2 Description
0 Channel 2's timer counter (TCNT2) operates independently TCNT2 is preset and
cleared inde pen dent ly of other channels (Initi al val ue)
1 Channel 2 operates synchronously
TCNT2 can be synchronously preset and cleared
Bit 1—Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or
synchronously.
Bit 1
SYNC1 Description
0 Channel 1's timer counter (TCNT1) operates independently TCNT1 is preset and
cleared inde pen dent ly of other channels (Initi al val ue)
1 Channel 1 operates synchronously
TCNT1 can be synchronously preset and cleared
Bit 0—Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or
synchronously.
Bit 0
SYNC0 Description
0 Channel 0's timer counter (TCNT0) operates independently TCNT0 is preset and
cleared inde pen dent ly of other channels (Initi al val ue)
1 Channel 0 operates synchronously
TCNT0 can be synchronously preset and cleared
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.3 Timer Mode Register (TMDR)
TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also
selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2.
Bit
Initial value
Read/Write
7
—
1
—
6
MDF
0
R/W
5
FDIR
0
R/W
4
PWM4
0
R/W
3
PWM3
0
R/W
0
PWM0
0
R/W
2
PWM2
0
R/W
1
PWM1
0
R/W
Reserved bit
PWM mode 4 to 0
These bits select PWM
mode for channels 4 to 0
Phase counting mode flag
Selects phase counting mode for channel 2
Flag direction
Selects the setting condition for the overflow
flag (OVF) in timer status register 2 (TSR2)
TMDR is initialized to H'80 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in
phase counting mode.
Bit 6
MDF Description
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in phase countin g mode
When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an
up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts
both risin g and falling edges o f TCLKA and TCLKB, and counts up or down as follows.
Counting Direction Down-Counting Up-Counting
TCLKA pin High Low Low High
TCLKB pin Low High High Low
Section 8 16-Bit Integrated Timer Unit (ITU)
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In phase counting mode channel 2 operates as above regardless of the external clock edges
selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in
timer control register 2 (TCR2). Phase counting mode takes precedence over these settings.
The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare
match/input capture settings and interr upt functions of timer I/O control register 2 (TIOR2), timer
interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase
counting mode.
Bit 5—Flag Direction (FDIR): Designates the setting condition for the overflow flag (OVF) in
timer status register 2 (TSR2). The FDIR designation is valid in all modes in channel 2.
Bit 5
FDIR Description
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows (Initial value)
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Bit 4—PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode.
Bit 4
PWM4 Description
0 Channel 4 operates normally (Initial value)
1 Channel 4 operates in PWM mode
When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The
output goes to 1 at compare match with general register A4 (GRA4), and to 0 at compare match
with general register B4 (GRB4).
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in the timer f unction control register (T FCR) , the CMD1 and CMD0 setting takes
precedence and the PWM4 setting is ignored.
Bit 3—PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode.
Bit 3
PWM3 Description
0 Channel 3 operates normally (Initial value)
1 Channel 3 operates in PWM mode
Section 8 16-Bit Integrated Timer Unit (ITU)
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When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The
output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match
with general register B3 (GRB3).
If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and
CMD0 in the timer f unction control register (T FCR) , the CMD1 and CMD0 setting takes
precedence and the PWM3 setting is ignored.
Bit 2—PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode.
Bit 2
PWM2 Description
0 Channel 2 operates normally (Initial value)
1 Channel 2 operates in PWM mode
When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The
output goes to 1 at compare match with general register A2 (GRA2), and to 0 at compare match
with general register B2 (GRB2).
Bit 1—PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode.
Bit 1
PWM1 Description
0 Channel 1 operates normally (Initial value)
1 Channel 1 operates in PWM mode
When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The
output goes to 1 at compare match with general register A1 (GRA1), and to 0 at compare match
with general register B1 (GRB1).
Bit 0—PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode.
Bit 0
PWM0 Description
0 Channel 0 operates normally (Initial value)
1 Channel 0 operates in PWM mode
When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The
output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match
with general register B0 (GRB0).
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.4 Timer Function Control Register (TFCR)
TFCR is an 8-bit readable/writable register that selects complementary PWM mode, reset-
synchronized PWM mode, and buffering for channels 3 and 4.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
CMD1
0
R/W
4
CMD0
0
R/W
3
BFB4
0
R/W
0
BFA3
0
R/W
2
BFA4
0
R/W
1
BFB3
0
R/W
Reserved bits
Combination mode 1/0
These bits select complementary
PWM mode or reset-synchronized
PWM mode for channels 3 and 4
Buffer mode B4 and A4
These bits select buffering of
general registers (GRB4 and
GRA4) by buffer registers
(BRB4 and BRA4) in channel 4
Buffer mode B3 and A3
These bits select buffering
of general registers (GRB3
and GRA3) by buffer
registers (BRB3 and BRA3)
in channel 3
TFCR is initialized to H'C0 by a reset and in standby mod e.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bits 5 and 4—Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels
3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode.
Bit 5
CMD1 Bit 4
CMD0 Description
0 0 Channels 3 and 4 operate normally (Initial value)
1
1 0 Channels 3 and 4 operate together in complementary PWM mode
1 Channels 3 and 4 operate together in reset-synchronized PWM mode
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode b its (PWM4 and PWM3) in TMDR. Settin g s of
timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in
complementary PWM mode and reset-synchronized PWM mode, however. When complementary
PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and
SYNC4 both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4 .
Bit 3
BFB4 Description
0 GRB4 operates normally (Initial val ue)
1 GRB4 is buffered by BRB4
Bit 2—Buffer Mo de A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2
BFA4 Description
0 GRA4 operates normally (Initial val ue)
1 GRA4 is buffered by BRA4
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bit 1—Buf fer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3 .
Bit 1
BFB3 Description
0 GRB3 operates normally (Initial val ue)
1 GRB3 is buffered by BRB3
Bit 0—Buf fer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0
BFA3 Description
0 GRA3 operates normally (Initial val ue)
1 GRA3 is buffered by BRA3
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.5 Timer Output Master Enable Register (TOER)
TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3
and 4.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
EXB4
1
R/W
4
EXA4
1
R/W
3
EB3
1
R/W
0
EA3
1
R/W
2
EB4
1
R/W
1
EA4
1
R/W
Reserved bits
Master enable TOCXA
4
, TOCXB
4
These bits enable or disable output
settings for pins TOCXA
4
and TOCXB
4
Master enable TIOCA
3
, TIOCB
3
, TIOCA
4
, TIOCB
4
These bits enable or disable output settings for pins
TIOCA
3
, TIOCB
3
, TIOCA
4
, and TIOCB
4
TOER is initialized to H'FF by a reset and in standby mode.
Bits 7 and 6—Reserved: These bits cannot be modified and are always read as 1.
Bit 5—Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4.
Bit 5
EXB4 Description
0TOCXB
4
output is disabled regardless of TFCR settings (TOCXB
4
operates as a generic
input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in
channel 1.
1TOCXB
4 is enabled for output according to TFCR settings (Initial value)
Bit 4—Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4.
Bit 4
EXA4 Description
0TOCXA
4
output is disabled regardless of TFCR settings (TOCXA
4
operates as a generic
input/output pin).
If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1.
1TOCXA
4 is enabled for output according to TFCR settings (Initial value)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bit 3—Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3.
Bit 3
EB3 Description
0TIOCB
3
output is disabled regardless of TIOR3 and TFCR settings (TIOCB
3
operates as
a generic input/output pin).
If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1.
1TIOCB
3 is enabled for output according to TIOR3 and TFCR setting s (Initial value)
Bit 2—Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4.
Bit 2
EB4 Description
0TIOCB
4
output is disabled regardless of TIOR4 and TFCR settings (TIOCB
4
operates as
a generic input/output pin).
If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1.
1TIOCB
4 is enabled for output according to TIOR4 and TFCR setting s (Initial value)
Bit 1—Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4.
Bit 1
EA4 Description
0TIOCA
4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4
operates as a generic input/output pin).
If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1.
1TIOCA
4 is enabled for output according to TIOR4, TMDR, and TFCR settings
(Initial value)
Bit 0—Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3.
Bit 0
EA3 Description
0TIOCA
3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3
operates as a generic input/output pin).
If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1.
1TIOCA
3 is enabled for output according to TIOR3, TMDR, and TFCR settings
(Initial value)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.6 Timer Output Control Register (TOCR)
TOCR is an 8-bit readable/writable reg ister that selects externally tr iggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
XTGD
1
R/W
3
—
1
—
0
OLS3
1
R/W
2
—
1
—
1
OLS4
1
R/W
Reserved bits Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
Reserved bits
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4
XTGD Description
0 Input capture A in channel 1 is used as an external trigger signal in complementary
PWM mode and re set-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in the timer output master enable register
(TOER) are cleared to 0, disabling ITU output.
1 External triggering is disabled (Initial value)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bits 3 and 2—Reserved: These bits cannot be modified and are always read as 1.
Bit 1—Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 1
OLS4 Description
0TIOCA
3, TIOCA4, and TIOCB4 pin outputs are inverted
1TIOCA
3, TIOCA4, and TIOCB4 pin outputs are not inverted (Initial value)
Bit 0—Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and
reset-synchronized PWM mode.
Bit 0
OLS3 Description
0TIOCB
3, TOCXA4, and TOCXB4 pin outputs are inverted
1TIOCB
3, TOCXA4, and TOCXB4 pin outputs are not inverted (Initi al val ue)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.7 Timer Counters (TCNT)
TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel.
Channel Abbreviation Function
0 TCNT0
1 TCNT1
Up-counter
2 TCNT2 Phase counting mode: up/down-counter
Other modes: up-counter
3 TCNT3
4 TCNT4
Complementary PWM mode: up/down-counter
Other modes: up-counter
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The
clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR).
TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and
an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM
mode and up-counters in other modes.
TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or
by input capture to GRA or GRB (counter clearing function) in the same channel.
When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in
the timer status register (TSR) of the corresponding ch annel.
When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in
TSR of the corresponding channel.
The TCNTs are linked to the CPU by an internal 16- bit bu s and can be written or read by either
word access or byte access.
Each TCNT is initialized to H'0000 by a reset and in standby mode.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.8 General Registers (GRA, GRB)
The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel.
Channel Abbreviation Function
0GRA0, GRB0
1GRA1, GRB1
2GRA2, GRB2
Output compare/input capture register
3GRA3, GRB3
4GRA4, GRB4
Output compare/input capture register; can be by buffer registers
BRA and BRB
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
A general register is a 16-bit readable/writab le re gister that can function as either an ou tput
compare register or an input capture register. The function is selected by settings in the timer I/O
control register (TIOR).
When a general register is used as an output compare register, its value is constantly compared
with the TCNT value. When the two values match ( compare match), the IMFA or IMFB flag is set
to 1 in the timer status register (TSR). Compare match output can be selected in TIOR.
When a general register is used as an input capture register, rising edges, falling edges, or both
edges of an external input capture signal are detected and the current TCNT value is stored in the
general register. Th e corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The
valid edge or edges of the input capture signal are selected in TIOR.
TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized
PWM mode.
General register s ar e linked to the CPU by an internal 16-bit bus and can be written or read by
either word access or byte access.
General register s ar e initialized to the output compare function (with no outp ut signal) by a reset
and in standby mode. The initial v alue is H'FFFF.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 220 of 682
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8.2.9 Buffer Registers (BRA, BRB)
The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3
and 4.
Channel Abbreviation Function
3 BRA3, BRB3
4 BRA4, BRB4
Used for buffering
• When the corresponding GRA or GRB functions as an output
compare register, BRA or BRB can function as an output compare
buffer register: the BRA or BRB value is automatically transferred
to GRA or GRB at compare match
• When the corresponding GRA or GRB functions as an input
capture register, BRA or BRB can function as an input capture
buffer register: the GRA or GRB value is automatically transferred
to BRA or BRB at input capture
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
A buffer register is a 16-bit readable/writable register that is used when buffering is selected.
Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR.
The buffer register and general register operate as a pair. When the general register functions as an
output compare register, the buffer register functions as an output compare buffer register. When
the general register functions as an input capture register, the buffer register functions as an input
capture buffer register.
The buffer registers are lin ked to the CPU by an internal 16-bit bus and can be written or r ead by
either word or byte access.
Buffer registers are initialized to H'FFFF by a reset and in standby mode.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.2.10 Timer Control Registers (TCR)
TCR is an 8-bit register. Th e ITU has five TCRs, one in each channel.
Channel Abbreviation Function
0 TCR0
1 TCR1
2 TCR2
3 TCR3
4 TCR4
TCR controls the timer counter. The TCRs in all channels are
function all y ident ic al. When pha se cou nting mode is selec ted in
channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to
TPSC0 in TCR2 are ignored.
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Timer prescaler 2 to 0
These bits select the
counter clock
Reserved bit
Clock edge 1/0
These bits select external clock edges
Counter clear 1/0
These bits select the counter clear source
Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects
the edge or edges of extern al clock sources, and selects how the counter is cleared.
TCR is initialized to H'8 0 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 222 of 682
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Bit 6
CCLR1 Bit 5
CCLR0 Description
0 0 TCNT is not clea red (Initial value)
1 TCNT is cleared by GRA compare match or input capture *1
1 0 TCNT is cleared by GRB compare match or input capture*1
1 Synchronous clear: TCNT is cle ared in synchr oni zation with other
synchronized timers*2
Notes: 1. TCNT is cleared by com pare match when the general r egi ster fun cti ons as an outp ut
compare match register, and by input capture when the general register functions as an
input capture register.
2. Selected in the timer synchro register (TSNC).
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4
CKEG1 Bit 3
CKEG0 Description
0 0 Count rising edges (Initial value)
1 Count falling edges
1 — Count both edges
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Function
000Internal clock: φ(Initial value)
1 Internal clock: φ/2
1 0 Internal clo ck: φ/4
1 Internal clock: φ/8
100External clock A: TCLKA input
1 External clock B: TCLKB input
1 0 External clo ck C: TC LKC input
1 External clock D: TCLKD input
Section 8 16-Bit Integrated Timer Unit (ITU)
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When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only
falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts
the edge or edges selected by bits CKEG1 and CKEG0.
When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to
TPSC0 in TCR2 are ignored. Phase counting takes precedence.
8.2.11 Timer I/O Control Register (TIOR)
TIOR is an 8-bit register. The ITU has five TIORs, one in each channel.
Channel Abbreviation Function
0TIOR0
1TIOR1
2TIOR2
3TIOR3
4TIOR4
TIOR controls the general registers. Some functions differ in PWM
mode. TIOR3 and TIOR4 settings are ignored when complementary
PWM mode or reset-synchronized PWM mode is selected in
channels 3 and 4.
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
I/O control A2 to A0
These bits select GRA
functions
Reserved bit
I/O control B2 to B0
These bits select GRB functions
Reserved bit
Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture
function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the
output compare function is selected, TIOR also selects the type of output. If input capture is
selected, TIOR also selects the edge or edges of the input capture signal.
TIOR is initialized to H'8 8 by a reset and in stan dby mode.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 224 of 682
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Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bits 6 to 4—I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function.
Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 Function
0 0 0 No output at compare match (Initial value)
1
GRB is an output
compare register 0 output at GRB compare match*1
1 0 1 output at GRB compare match*1
1 Output toggles at GRB compare match
(1 output in channel 2)*1 *2
1 0 0 GRB captures rising edge of input
1 GRB captures falling edge of input
10
1
GRB is an input
capture register
GRB captures both edges of input
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bits 2 to 0—I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function.
Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 Function
0 0 0 No output at compare match (Initial value)
1 0 output at GRA compare match*1
10
GRA is an output
compare register
1 output at GRA compare match*1
1 Output toggles at GRA compare match
(1 output in channel 2)*1 *2
1 0 0 GRA captures rising edge of input
1 GRA captures falling edge of input
10
1
GRA is an input
capture register
GRA captures both edges of input
Notes: 1. After a reset, the output is 0 until the first compare match.
2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output
instead.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 225 of 682
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8.2.12 Timer Status Register (TSR)
TSR is an 8-bit register. The ITU has five TSRs, one in each channel.
Channel Abbreviation Function
0TSR0
1TSR1
2TSR2
3TSR3
4TSR4
Indicates input capture, compare match, and overflow status
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—*
2
OVF
0
R/(W)
Reserved bits
Note: * Only 0 can be written to clear the flag.
*
1
IMFB
0
R/(W) *
0
IMFA
0
R/(W)
Overflow flag
Status flag indicating
overflow or underflow
Input capture/compare match flag B
Status flag indicating GRB compare
match or input capture
Input capture/compare match flag A
Status flag indicating GRA compare
match or input capture
Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or
underflow and GRA or GRB compare match or input capture. These flags are interrupt sources
and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register
(TIER).
TSR is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 226 of 682
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Bit 2—Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow.
Bit 2
OVF Description
0 [Clearing condition] (Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF*
Notes: *TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow
occurs only under the following conditions:
1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR)
2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0
in TFCR)
Bit 1—Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB
compare match or input capture events.
Bit 1
IMFB Description
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB (Initial value)
1 [Setting conditions]
• TCNT = GRB when GRB functions as a compare match register.
• TCNT value is transferred to GRB by an input capture signal, when GRB functions
as an input capture register.
Bit 0—Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA
compare match or input capture events.
Bit 0
IMFA Description
0 [Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA. (Initial value)
1 [Setting conditions]
• TCNT = GRA when GRA functions as a compare match register.
• TCNT value is transferred to GRA by an input capture signal, when GRA functions
as an input capture register.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 227 of 682
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8.2.13 Timer Interrupt Enable Register (TIER)
TIER is an 8-bit register. The ITU has five TIERs, one in each channel.
Channel Abbreviation Function
0 TIER0 Enables or disables interrupt requests.
1TIER1
2TIER2
3TIER3
4TIER4
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
OVIE
0
R/W
1
IMIEB
0
R/W
0
IMIEA
0
R/W
Reserved bits
Overflow interrupt enable
Enables or disables OVF
interrupts
Input capture/compare match
interrupt enable B
Enables or disables IMFB interrupts
Input capture/compare match
interrupt enable A
Enables or disables IMFA
interrupts
Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt
requests and general register compare match and input capture interrupt requests.
TIER is initialized to H'F8 by a reset and in standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Bit 2—Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the
overflow flag (OVF) in TSR when OVF is set to 1 .
Bit 2
OVIE Description
0 OVI interrupt requested by OVF is disabled (Initial value)
1 OVI interrupt requested by OVF is enabled
Bit 1—Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the
interrup t r eque sted by the IMFB flag in TSR when IMFB is set to 1.
Bit 1
IMIEB Description
0 IMIB interrupt requested by IMFB is disabled (Initial value)
1 IMIB interrupt requested by IMFB is enabled
Bit 0—Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the
interrupt r eque sted by the IMFA flag in TSR when I M FA is set to 1.
Bit 0
IMIEA Description
0 IMIA interrupt requested by IMFA is disabled (Initial value)
1 IMIA interrupt requested by IMFA is enabled
8.3 CPU Interface
8.3.1 16-Bit Accessible Registers
The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A
and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data
bus. These registers can be written or read a word at a time, or a byte at a time.
Figures 8.6 and 8.7 show ex amples of word access to a timer counter (TCNT). Figures 8.8, 8.9,
8.10, and 8.11 show examples of byte access to TCNTH and TCNTL.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 229 of 682
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Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.6 Access to Timer Counter (CPU Writes to TCNT, Word)
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.7 Access to Timer Counter (CPU Reads TCNT, Word)
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte)
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 230 of 682
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Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte)
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.10 Access to Timer Counter (CPU Reads TCNT, Upper Byte)
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCNTH TCNTL
Figure 8.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.3.2 8-Bit Accessible Registers
The registers other than the timer counters, general registers, and buffer registers are 8-bit
registers. These registers are linked to the CPU by an internal 8-bit data bus.
Figures 8.12 and 8.13 show examples of byte read and write access to a TCR.
If a word-size data transfer in struction is executed, two byte transfers are performed.
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCR
Figure 8.12 TCR Access (CPU Writes to TCR)
Internal data bus
CPU
H
L Bus interface
H
LModule
data bus
TCR
Figure 8.13 TCR Access (CPU Reads TCR)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4 Operation
8.4.1 Overview
A summary of operations in the various modes is given below.
Normal Operation: Each channel has a timer counter and general registers. The timer counter
counts up, and can operate as a free-running counter, periodic counter, or extern al event counter.
General registers A and B can be used for input capture or output compare.
Synchronous Opera tion: The timer counters in designated channels are preset synchronously.
Data written to the tim er counter in any one of these channels is simultaneously written to the
timer counters in the other channels as well. The timer counters can also be cleared synchronously
if so designated by the CCLR1 and CCLR0 bits in the TCRs.
PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare
match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending
on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB
automatically become output compare registers.
Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
complementary waveforms. (The three phases are related by having a common transition point.)
When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically
function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and
TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates
independently, and is not compared with GRA4 or GRB4.
Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with
non-overlapping complementary wavefo rms. When complementary PWM mode is selected
GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and
TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins.
TCNT3 and TCNT4 operate as up/down-counters.
Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and
TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is
selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/down-
counter.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Buffering:
• If the general register is an output compare register
When compare match occurs the buffer register value is transferred to the general register.
• If the general register is an input captu re register
When input capture occurs the TCNT value is transferred to the general register, and the
previous general register value is transferred to the buffer register.
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change counting direction.
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at GRA3 compare match.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.2 Basic Functions
Counter Operation
When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR), the timer counter
(TCNT) in the corresponding channel starts counting. The counting can be free-running or
periodic.
Sample setup procedure for counter: Figure 8.14 shows a sample procedure for setting up a
counter.
Counter setup
Select counter clock
Type of counting?
Periodic counting
Select counter clear source
Select output compare
register function
Set period
Start counter
Free-running counting
Start counter
Periodic counter Free-running counter
1
2
3
4
55
Yes
No
Figure 8.14 Counter Setup Procedure (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source
is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external
clock signal.
2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare
match or GRB compare match.
3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in
step 2.
4. Write the count period in GRA or GRB, whichever was selected in step 2.
5. Set the STR bit to 1 in TSTR to start the timer counter.
Free-running and periodic counter operation: A reset leaves the counters (TCNTs) in ITU
channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the
corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the
overflo w flag ( OVF) is set to 1 in the timer status re gister (TSR). If the corresponding OVIE b it is
set to 1 in the tim er interrupt enable register, a CPU interrupt is requested . After th e over f low, the
counter continues counting up from H'0000. Figure 8.15 illustrates free-running counting.
TCNT value
H'FFFF
H'0000
STR0 to
STR4 bit
OVF
Time
Figure 8.15 Free-Running Counter Operatio n
When a channel is set to have its counter cleared by compare match, in that channel TCNT
operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1
or CCLR0 in the timer contro l register (TCR) to have the counter cleared by compare match, and
set the count period in GRA or GRB. After these settings, the counter starts counting up as a
periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or
GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the
correspo nding IMIEA or IMIEB b it is set to 1 in TIER, a CPU interrupt is requested at this time.
After the compare match, TCNT continues countin g up from H'0000. Figure 8.16 illustrates
periodic counting.
Section 8 16-Bit Integrated Timer Unit (ITU)
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TCNT value
GR
H'0000
STR bit
IMF
Time
Counter cleared by general
register compare match
Figure 8.16 Periodic Counter Operation
Count timing:
• Internal clock source
Bits TPSC2 to TPSC0 in TCR selec t the system clock (φ) or one of three internal clock sources
obtained by prescaling the system clock (φ/2, φ/4, φ/8).
Figure 8.17 shows the timing.
φ
TCNT input
TCNT
Internal
clock
N – 1 N N + 1
Figure 8.17 Count Timing for Internal Clock Sources
• External clock source
Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its
valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or
both edges can be selected.
The pulse width of the external clock signal must be at least 1.5 system clocks when a single
edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses
will not be counted correctly.
Figure 8.18 shows the timing when both edges are detected.
Section 8 16-Bit Integrated Timer Unit (ITU)
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φ
TCNT input
TCNT
External
clock input
N – 1 N N + 1
Figure 8.18 Count Timing for External Clock Sources (when Both Edges are Detected)
Waveform Output by Compa re Match
In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or
TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1.
Sample setup pro cedure f or wavefo rm output by compare match: Figure 8.19 shows a sample
procedure for setting up waveform output by compare match.
Output setup
Select waveform
output mode
Set output timing
Start counter
Waveform output
Select the compare match output mode (0, 1, or
toggle) in TIOR. When a waveform output mode
is selected, the pin switches from its generic input/
output function to the output compare function
(TIOCA or TIOCB). An output compare pin outputs
Set a value in GRA or GRB to designate the
compare match timing.
Set the STR bit to 1 in TSTR to start the timer
counter.
1
2
3
0 until the first compare match occurs.
1.
2.
3.
Figure 8.19 Setup Procedure for Waveform Output by Compare Match (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 238 of 682
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Examples of waveform output: Figure 8.20 shows examples of 0 and 1 output. TCNT operates
as a free-running coun ter, 0 output is selected for compare match A, and 1 output is selected for
compare match B. When the pin is already at the selected output level, the pin level does not
change.
Time
H'FFFF
GRB
TIOCB
TIOCA
GRA
No change
No change
No change
No change
1 output
0 output
TCNT value
H'0000
Figure 8.20 0 and 1 Output (Examples)
Figure 8.21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by
compare match B. Toggle output is selected for both compare match A and B.
GRB
TIOCB
TIOCA
GRA
TCNT value
Time
Counter cleared by compare match with GRB
Toggle
output
Toggle
output
H'0000
Figure 8.21 Toggle Output (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Output compare timing: The compare match signal is generated in the last state in which TCNT
and the general register match (when TCNT changes from the matching value to the next value).
When the com pare match signal is g enerated, the output value selected in TIOR is output at the
output compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare
match signal is not generated until the next counter clock pulse.
Figure 8.22 shows the output compare timing.
N + 1N
N
φ
TCNT input
clock
TCNT
GR
Compare
match signal
TIOCA,
TIOCB
Figure 8.22 Output Compare Timing
Section 8 16-Bit Integrated Timer Unit (ITU)
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Input Capture Function
The TCNT value can be captured into a general register when a transition occurs at an input
capture/output compare pin (TIOCA or TIOCB). Captu r e can take p lace on the rising ed ge, falling
edge, or both edges. The inpu t capture function can be used to measure pulse width or period.
Sample setup pro cedure f or input capture: Figure 8.23 shows a sample procedure for setting up
input capture.
Input selection
Select input-capture input
Start counter
Input capture
Set TIOR to select the input capture function of a
general register and the rising edge, falling edge,
or both edges of the input capture signal. Clear the
port data direction bit to 0 before making these
TIOR settings.
Set the STR bit to 1 in TSTR to start the timer
counter.
1
2
1.
2.
Figure 8.23 Setup Procedure for Input Capture (Example)
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Examples of input capture: Figure 8.24 illustrates input capture when the falling edge of TIOCB
and both edges of TIOCA are selected as capture edges. TCNT is cleared by input capture into
GRB.
H'0005
H'0180
Time
H'0180
H'0160
H'0005
H'0000
TIOCB
TIOCA
GRA
GRB
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0160
Figure 8.24 Input Capture (Example)
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Input capture signal timing: Input capture on the rising edge, falling edge, or both edges can be
selected by settings in TIOR. Figure 8.25 shows the timing when the rising edge is selected. The
pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture,
and 2.5 system clocks for capture of both edges.
N
N
φ
Input-capture input
Internal input
capture signal
TCNT
GRA, GRB
Figure 8.25 Input Capture Signal Ti ming
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.3 Synchronization
The synchron ization function enables two or more tim er counters to be synchronized by writing
the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or
more timer counters can also be cleared simultaneously (synchronous clear). Synchronization
enables additional general registers to be associated with a single time base. Synchronization can
be selected for all channels (0 to 4).
Sample Setup Pr ocedure for Synchroniza tion
Figure 8.26 shows a sample procedure for setting up synchronization.
Setup for synchronization
Synchronous preset
Set the SYNC bits to 1 in TSNC for the channels to be synchronized.
When a value is written in TCNT in one of the synchronized channels, the same value is
simultaneously written in TCNT in the other channels.
1.
2.
2
3
1
5
4
5
Select synchronization
Synchronous preset
Write to TCNT
Synchronous clear
Clearing
synchronized to this
channel?
Select counter clear source
Start counter
Counter clear Synchronous clear
Start counter
Select counter clear source
Yes
No
Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture.
Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously.
Set the STR bits in TSTR to 1 to start the synchronized counters.
3.
4.
5.
Figure 8.26 Setup Pro cedure f or Synchronizatio n ( Ex ample)
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Example of Synchronization
Figure 8.27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are
set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0.
Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1,
and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A
three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further
information on PWM mode, see section 8.4.4, PWM Mode.
TIOCA
2
Time
TIOCA
1
TIOCA
0
GRA2
H'0000
GRA1
GRB2
GRA0
GRB1
GRB0
Value of TCNT0 to TCNT2 Cleared by compare match with GRB0
Figure 8.27 Synchronization (Example)
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8.4.4 PWM Mode
In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.
GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which
the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a
PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can
be selected in all chan nels (0 to 4).
Table 8.4 summarizes the PWM output pins and corresponding registers. If the same value is set
in GRA and GRB, the output does not change when compare match occurs.
Table 8.4 PWM Output Pins and Registers
Channel Output Pin 1 Output 0 Output
0TIOCA
0GRA0 GRB0
1TIOCA
1GRA1 GRB1
2TIOCA
2GRA2 GRB2
3TIOCA
3GRA3 GRB3
4TIOCA
4GRA4 GRB4
Section 8 16-Bit Integrated Timer Unit (ITU)
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Sample Setup P r ocedure for PWM Mode
Figure 8.28 shows a sample procedure for setting up PWM mode.
PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source. If an
external clock source is selected, set
bits CKEG1 and CKEG0 in TCR to
select the desired edge(s) of the
external clock signal.
PWM mode
Select counter clock 1
Select counter clear source 2
Set GRA 3
Set GRB 4
Select PWM mode 5
Start counter 6
2. Set bits CCLR1 and CCLR0 in TCR
to select the counter clear source.
3. Set the time at which the PWM
waveform should go to 1 in GRA.
4. Set the time at which the PWM
waveform should go to 0 in GRB.
5. Set the PWM bit in TMDR to select
PWM mode. When PWM mode is
selected, regardless of the TIOR
contents, GRA and GRB become
output compare registers specifying
the times at which the PWM
goes to 1 and 0. The TIOCA pin
automatically becomes the PWM
output pin. The TIOCB pin conforms
to the settings of bits IOB1 and IOB0
in TIOR. If TIOCB output is not
desired, clear both IOB1 and IOB0 to 0.
6. Set the STR bit to 1 in TSTR to start
the timer counter.
Figure 8.28 Setup Procedure for PWM Mode (Example)
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Examples of PWM Mode
Figure 8.29 shows examples of operation in PWM mode. The PWM waveform is output from the
TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with
GRB.
In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized
operation and free-running counting are also possible.
TCNT value Counter cleared by compare match with GRA
Time
GRA
GRB
TIOCA
a. Counter cleared by GRA
TCNT value Counter cleared by compare match with GRB
Time
GRB
GRA
TIOCA
b. Counter cleared by GRB
H'0000
H'0000
Figure 8.29 PWM Mode (Example 1)
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Figure 8.30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%.
If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB,
the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a
higher value than GRA, the duty cycle is 100%.
TCNT value Counter cleared by compare match with GRB
Time
GRB
GRA
TIOCA
a. 0% duty cycle
TCNT value Counter cleared by compare match with GRA
Time
GRA
GRB
TIOCA
b. 100% duty cycle
Write to GRA Write to GRA
Write to GRB Write to GRB
H'0000
H'0000
Figure 8.30 PWM Mode (Example 2)
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8.4.5 Reset-Synchronized PWM Mode
In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of
complementary PWM waveforms, all having one waveform transition point in common.
When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4,
and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an up-counter.
Table 8.5 lists the PWM output pins. Table 8.6 summarizes the register settings.
Table 8.5 Output Pins in Reset-Synchronized PWM Mode
Channel Output Pin Description
3TIOCA
3PWM output 1
TIOCB3PWM output 1' (complementary waveform to PWM output 1)
4TIOCA
4PWM output 2
TOCXA4PWM output 2' (complementary waveform to PWM output 2)
TIOCB4PWM output 3
TOCXB4PWM output 3' (complementary waveform to PWM output 3)
Table 8.6 Register Settings in Reset-Synchro nized PWM Mo de
Register Setting
TCNT3 Initially set to H'0000
TCNT4 Not used (operates independently)
GRA3 Specifies the count period of TCNT3
GRB3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
Section 8 16-Bit Integrated Timer Unit (ITU)
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Sample Setup P rocedure for Reset-Synchronized PWM Mo de
Figure 8.31 shows a sample procedure for setting up reset-synchronized PWM mode.
Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to
halt TCNT3. Reset-synchronized
PWM mode must be set up while
TCNT3 is halted.
Reset-synchronized PWM mode
Stop counter 1
Select counter clock 2
Select counter clear source 3
Select reset-synchronized
PWM mode 4
Set TCNT 5
Set general registers 6
2. Set bits TPSC2 to TPSC0 in TCR to
select the counter clock source for
channel 3. If an external clock source
is selected, select the external clock
edge(s) with bits CKEG1 and CKEG0
in TCR.
3. Set bits CCLR1 and CCLR0 in TCR3
to select GRA3 compare match as
the counter clear source.
4. Set bits CMD1 and CMD0 in TFCR to
select reset-synchronized PWM mode.
TIOCA
3
, TIOCB
3
, TIOCA
4
, TIOCB
4
,
TOCXA
4
, and TOCXB
4
automatically
become PWM output pins.
5. Preset TCNT3 to H'0000. TCNT4
need not be preset.
Start counter 7
6. GRA3 is the waveform period register.
Set the waveform period value in
GRA3. Set transition times of the
PWM output waveforms in GRB3,
GRA4, and GRB4. Set times within
the compare match range of TCNT3.
X GRA3 (X: setting value)
≤
7. Set the STR3 bit in TSTR to 1 to start
TCNT3.
Figure 8.31 Setup Pro cedure for Reset-Synchro nized PWM Mode (Example)
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Example of Reset-Synchronized PWM Mode
Figure 8.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as
an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4.
When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM
outputs toggle at compare match with GRB3 , GRA4, GRB4, and TCNT3 respectively, and when
the counter is cleared.
TCNT3 value Counter cleared at compare match with GRA3
Time
GRA3
GRB3
GRA4
GRB4
H'0000
TIOCA3
TIOCB3
TIOCA4
TOCXA4
TIOCB4
TOCXB4
Figure 8.32 Operation in Reset-Synchronized PWM Mode (Example)
(when OLS3 = O LS4 = 1)
For the settings and operation when reset-synchronized PWM mode and buffer mode are both
selected, see section 8.4.8, Buffering.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.6 Complementary PWM Mode
In complementary PWM mode channels 3 and 4 are combined to output three pairs of
complementary, non-overlapping PWM waveforms.
When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and
TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as up/down-
counters.
Table 8.7 lists the PWM output pins. Table 8.8 summarizes the register settings.
Table 8.7 Output Pins in Complementary PWM Mode
Channel Output Pin Description
3TIOCA
3PWM output 1
TIOCB3PWM output 1' (non-overlapping complementary waveform to PWM
output 1)
4TIOCA
4PWM output 2
TOCXA4PWM output 2' (non-overlapping complementary waveform to PWM
output 2)
TIOCB4PWM output 3
TOCXB4PWM output 3' (non-overlapping complementary waveform to PWM
output 3)
Table 8.8 Register Settings in Complementary PWM Mo de
Register Setting
TCNT3 Initially specifies the non-overlap margin (diffe rence to TCNT4)
TCNT4 Initially set to H'0000
GRA3 Specifies the upper limit value of TCNT3 minus 1
GRB3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3
GRA4 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4
GRB4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4
Section 8 16-Bit Integrated Timer Unit (ITU)
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Setup Procedure for Complementary PWM Mode
Figure 8.33 shows a sample procedure for setting up complementary PWM mode.
Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in
TSTR to halt the timer counters.
Complementary PWM mode must be
set up while TCNT3 and TCNT4 are
halted.
Complementary PWM mode
Stop counting 1
Select counter clock 2
Select complementary
PWM mode 3
Set TCNTs 4
Set general registers 5
Start counters 6
2. Set bits TPSC2 to TPSC0 in TCR to
select the same counter clock source
for channels 3 and 4. If an external
clock source is selected, select the
external clock edge(s) with bits
CKEG1 and CKEG0 in TCR. Do not
select any counter clear source
with bits CCLR1 and CCLR0 in TCR.
3. Set bits CMD1 and CMD0 in TFCR
to select complementary PWM mode.
TIOCA
3
, TIOCB
3
, TIOCA
4
, TIOCB
4
,
TOCXA
4
, and TOCXB
4
automatically
become PWM output pins.
4. Clear TCNT4 to H'0000. Set the
non-overlap margin in TCNT3. Do not
set TCNT3 and TCNT4 to the same
value.
5. GRA3 is the waveform period
register. Set the upper limit value of
TCNT3 minus 1 in GRA3. Set
transition times of the PWM output
waveforms in GRB3, GRA4, and
GRB4. Set times within the compare
match range of TCNT3 and TCNT4.
T X (X: initial setting of GRB3,
GRA4, or GRB4. T: initial setting of
TCNT3)
≤
6. Set bits STR3 and STR4 in TSTR to
1 to start TCNT3 and TCNT4.
Note: After exiting complementary PWM mode, to resume operating in complementary
PWM mode, follow the entire setup procedure from step 1 again.
Figure 8.33 Setup Procedure for Complementary PWM Mode (Example)
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Clearing Complementary PWM Mode
Figure 8.34 shows a sample procedure for clearing complementary PWM mode.
Complementary PWM mode
Normal operation
Clear complementary mode 1
Stop counting 2
1.
2.
Clear bit CMD1 in TFCR to 0, and set
channels 3 and 4 to normal operating
mode.
After setting channels 3 and 4 to normal
operating mode, wait at least one clock
count before clearing bits STR3 and
STR4 of TSTR to 0 to stop the counter
operation of TCNT3 and TCNT4.
Figure 8.34 Clearing Procedure for Complementary PWM Mode (Example)
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Examples of Complementary PWM Mode
Figure 8.35 shows an example of operation in co mplementary PWM mode. TCNT3 and TCNT4
operate as up/down-counters, counting down from compare match between TCNT3 and GRA3
and counting up from the point at which TCNT4 underflows. During each up-and-down counting
cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4,
and GRB4. Since TCNT3 is initially set to a high e r value than TCNT4, compare ma tch even ts
occur in the sequence TCNT3, TCNT4, TCNT4, TCNT3.
TCNT3 and
TCNT4 values Down-counting starts at compare
match between TCNT3 and GRA3
Time
GRA3
GRB3
GRA4
GRB4
H'0000
TIOCA
3
TIOCB
3
TIOCA
4
TOCXA
4
TIOCB
4
TOCXB
4
TCNT3
TCNT4
Up-counting starts when
TCNT4 underflows
Figure 8.35 Operation in Complementary PWM Mode (Example 1)
(when OLS3 = O LS4 = 1)
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Figure 8.36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in
complementary PWM mode. In this example the outputs change at compare match with GRB3, so
waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larg er than
GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For
further information see section 8.4.8, Buffering.
TCNT3 and
TCNT4 values
Time
GRA3
GRB3
TIOCA3
TIOCB30% duty cycle
a. 0% duty cycle
TCNT3 and
TCNT4 values
Time
GRA3
GRB3
TIOCA3
TIOCB3
100% duty cycle
b. 100% duty cycle
H'0000
H'0000
Figure 8.36 Operation in Complementary PWM Mo de (Example 2)
(when OLS3 = O LS4 = 1)
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In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at th e transitions
between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and
the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer
conditions also differ. Timing diagrams are shown in figures 8.37 and 8.38.
TCNT3
GRA3
IMFA
Buffer transfer
signal (BR to GR)
GR
N Ð 1 N N + 1 N N Ð 1
N
Set to 1
Flag not set
No buffer transfer
Buffer transfer
Figure 8.37 Overshoot Timing
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TCNT4
OVF
Buffer transfer
signal (BR to GR)
GR
H'0001 H'0000 H'FFFF H'0000
Set to 1
Flag not set
No buffer transfer
Buffer transfer
Underflow Overflow
Figure 8.38 Undershoot Timing
In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when
an underflow occurs. When buffering is selected, buffer register contents are transferred to the
general register at compare match A3 during up-counting, and when TCNT4 underflows.
General Regist er Set tings in Complementary PWM Mode
When setting up general registers for complementary PWM mode or changing their settings
during operation, note the following points.
• Initial settings
Do not set valu es f rom H'0000 to T – 1 (where T is the initial value of TCNT3) . After the
counters start and the first compare match A3 event has occurred , however, settings in this
range also become possible.
• Changing settings
Use the buffer registers. Co rrect waveform output may not be obtained if a general register is
written to directly.
• Cautions on changes of general register settings
Figure 8.39 shows six correct examples and one incorrect example.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 259 of 682
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GRA3
GR
H'0000
BR
GR
Not allowed
Figure 8.39 Changing a General Register Setting by Buffer Transfer (Example 1)
Buffer transfer at transition from up-counting to down-counting
If the general register value is in the range from GRA3 – T + 1 to GRA3, do not transfer a
buffer register value outside this range. Conversely, if the general register value is outside
this range, do n o t transfer a value with in this range. See figure 8.40.
GRA3 + 1
GRA3
GRA3 – T + 1
GRA3 – T
Illegal changes
TCNT3
TCNT4
Figure 8.40 Changing a General Register Setting by Buffer Transfer (Caution 1)
Buffer transfer at transition from down-counting to up-counting
If the general register value is in the range from H'0000 to T – 1, do not transfer a buffer
register value outside this range. Conversely, when a general register valu e is outside this
range, do not transfer a value within this range. See figure 8.41.
Section 8 16-Bit Integrated Timer Unit (ITU)
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T
T – 1
H'0000
H'FFFF
Illegal changes
TCNT3
TCNT4
Figure 8.41 Changing a General Register Setting by Buffer Transfer (Caution 2)
General register settings outside the counting range (H'0000 to GRA3)
Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to
a value outside the counting range. When a buffer register is set to a value outside the
counting rang e, then later restored to a value within the counting range, the counting
direction (up or down) must be the same both times. See figure 8.42.
0% duty cycle 100% duty cycle
Write during down-counting Write during up-counting
GRA3
GR
H'0000
Output pin
Output pin
BR
GR
Figure 8.42 Changing a General Register Setting by Buffer Transfer (Example 2)
Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow
before wr iting to the buffer register.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.7 Phase Counting Mode
In phase counting mode the phase difference between two external clock inputs (at the TCLKA
and TCLKB pins) is detected, and TCNT2 counts up or down accordingly.
In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock
input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to
TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in
TIOR2, TIER2, TSR2 , GRA2, and GRB2 are valid. The input capture and output compare
functions can be used, and interrupts can be generated.
Phase counting is available only in channel 2.
Sample Setup P rocedure for Phase Co unt ing Mode
Figure 8.43 shows a sample procedure for setting up phase counting mode.
Phase counting mode
Select phase counting mode
Select flag setting condition
Start counter
1
2
3
Phase counting mode
1.
2.
3.
Set the MDF bit in TMDR to 1 to select
phase counting mode.
Select the flag setting condition with
the FDIR bit in TMDR.
Set the STR2 bit to 1 in TSTR to start
the timer counter.
Figure 8.43 Setup Procedure for Phase Counting Mode (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Example of Phase Counting Mode
Figure 8.44 shows an example of operations in phase counting mode. Table 8.9 lists the up-
counting and down-counting conditions for TCNT2.
In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The
phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must
also be at least 1.5 states, and the pu lse width must be at least 2.5 states. See figure 8.45.
TCNT2 value
Counting up Counting down
Time
TCLKB
TCLKA
Figure 8.44 Operation in Phase Counting Mode (Example)
Table 8.9 Up/Down Counting Conditions
Counting Direction Up-Counting Down-Counting
TCLKA pin High Low High Low
TCLKB pin Low High Low High
TCLKA
TCLKB
Phase
difference Phase
difference Pulse width Pulse width
Overlap Overlap
Phase difference and o v erlap:
Pulse width: at least 1.5 states
at least 2.5 states
Figure 8.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.8 Buffering
Buffering operates differently depending on whether a general register is an output compare
register or an input capture register, with further differences in reset-synchronized PWM mode and
complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations
under the conditions mentioned above are described next.
• General register used for ou tput compare
The buffer register value is transferred to the general register at compare match. See
figure 8.46.
Compare match signal
Comparator TCNTGRBR
Figure 8.46 Compare Match Buffering
• General register used for input capture
The TCNT value is transferred to the general register at input capture. The previous general
register value is transferred to the buffer register.
See figure 8.47.
Input capture signal
BR GR TCNT
Figure 8.47 Input Capture Buffering
• Complementary PWM mode
The buffer register value is transferred to the general register when TCNT3 and TCNT4
change countin g direction. This occurs at the following two tim es:
When TCNT3 matches GRA3
When TCNT4 underflows
• Reset-synchronized PWM mode
The buffer register value is transferred to the general register at compare match A3.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 264 of 682
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Sample Buffering Setup Procedure
Figure 8.48 shows a sample buffering setup procedure.
Buffering
Select general register functions
Set buffer bits
Start counters
Buffered operation
11.
2.
3.
2
3
Set TIOR to select the output compare or input
capture function of the general registers.
Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR
to select buffering of the required general registers .
Set the STR bits to 1 in TSTR to start the timer
counters.
Figure 8.48 Buffering Setup Procedure (Example)
Examples of Buffering
Figure 8.49 shows an example in which GRA is set to function as an output compare register
buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match,
and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting,
when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA.
This operation is repeated each time compare match A occurs. Figure 8.50 shows the transfer
timing.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 265 of 682
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GRB
H'0250
H'0200
H'0100
H'0000
BRA
GRA
TIOCB
TIOCA
TCNT value Counter cleared by compare match B
Time
Toggle
output
Toggle
output
Compare match A
H'0200
H'0250
H'0100
H'0200 H'0100
H'0200
H'0200
Figure 8.49 Register Buffering (Example 1: Buffering of Output Compare Register)
φ
TCNT
BR
GR
Compare
match signal
Buffer transfer
signal
n n + 1
nN
N
Figure 8.50 Compare Match and Buffer Transfer Timing (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Figure 8.51 shows an example in which GRA is set to function as an input capture register
buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the
input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because
of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous
GRA value is simu ltaneously transferred to BRA. Figure 8.52 show s the transfer tim ing.
H'0180
H'0160
H'0005
H'0000
TIOCB
TIOCA
GRA
BRA
GRB
H'0005
H'0160
H'0005
H'0180
TCNT value Counter cleared by
input capture B
Time
Input capture A
H'0160
Figure 8.51 Register Buf f ering (Example 2: Buffering of Input Ca pt ure Register)
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 267 of 682
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φ
TCNT
GR
BR
TIOC pin
Input capture
signal
n n + 1 N
n
M
N + 1
N
n
M
m
n
M
Figure 8.52 Input Capture and Buffer Tra nsfer Timing (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Figure 8.53 shows an example in which G RB3 is buf fered by BRB3 in complementary PWM
mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform
with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and
when TCNT4 underflows.
TCNT3 and
TCNT4 values
Time
GRA3
H'0999
H'0000
TCNT3
TCNT4
GRB3
H'1FFF
BRB3
GRB3
TIOCA3
TIOCB3
H'0999
H'0999 H'0999
H'1FFF H'0999
H'1FFF H'1FFF H'0999
Figure 8.53 Register Buffering (Example 4: Buffering in Complementary PWM Mode)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.4.9 ITU Output Timing
The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or in verted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER
In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER. An
arbitrary value can be output by appropriate settings of the data register (DR) and data direction
register (DDR) of the correspo ndin g input/output port. Fig ure 8.54 illustrates the tim ing of the
enabling and disabling of ITU output by TOER.
φ
Address
TOER
ITU output pin
TOER address
Timer output I/O port
Generic input/outputITU output
T
1
T
2
T
3
Figure 8.54 Timing of Disabling of ITU Output by Writing to TOER (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Timing of Disa bling of ITU Output by External Trigger
If the XTGD bit is cleared to 0 in TOCR in reset-syn chronized PWM mode or co mpleme ntary
PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are
cleared to 0 in TOER, disabling ITU output. Figure 8.55 shows the timing.
φ
TIOCA1 pin
TOER
ITU output I/O port ITU output I/O port
Generic
input/output Generic
input/output
ITU outputITU output
Input capture
signal
ITU output
pins
NNH'C0 H'C0
Legend:
N: Arbitrary setting (H'C1 to H'FF)
Figure 8.55 Timing of Disabling of ITU Output by External Trigger (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Timing o f Output Inversion by TOCR
The output levels in reset-synchronized PWM mode and complementary PWM mode can be
inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 8.56 shows
the timing.
φ
Address
TOCR
ITU output pin
TOCR address
Inverted
T
1 T
2 T
3
Figure 8.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example)
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.5 Interrupts
The ITU has two type s of interrupts: input capture/compare match interrupts, and overflow
interrupts.
8.5.1 Setting of Status Flags
Timing of Setting of IMFA and IMFB at Compare Match
IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general
register (GR). The compare match signal is generated in the last state in which the values match
(when TCNT is updated from the matching count to the next count). Therefore, when TCNT
matches a gen eral register, the compare match signal is not generated until the next timer clock
input. Figure 8.57 shows the timing of the setting of IMFA and IMFB.
φ
TCNT
GR
IMF
IMI
TCNT input
clock
Compare
match signal
NN + 1
N
Figure 8.57 Timing of Setting of IMFA and IMFB by Compare Match
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Timing o f Setting of IMFA and IMFB by Input Capture
IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously
transferred to the corresponding general register. Figure 8.58 shows the timing.
Input capture
signal
N
N
φ
IMF
TCNT
GR
IMI
Figure 8.58 Timing of Setting of IMFA and IMFB by Input Capture
Timing of Setting of Overflow Flag (OVF)
OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to
H'FFFF. Figure 8.59 shows the timing.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Overflow
signal
H'FFFF H'0000
φ
TCNT
OVF
OVI
Figure 8.59 Timing of Setting of OVF
8.5.2 Clearing of Status Flags
If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8.60 shows the timing.
φ
Address
IMF, OVF
TSR write cycle
TSR address
T1T2T3
Figure 8.60 Timing of Clearing of Status Flags
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.5.3 Interrupt Sources
Each ITU channel can generate a compare match/input capture A interrupt, a comp are match/input
capture B interrupt, and an ov erflow interrupt. In total there are 15 interrupt sources, all
independently vectored. An interrupt is requested when the interrupt request flag and interrupt
enable bit are both set to 1.
The priority order of the channels can be modified in interrupt priority registers A and B (IPRA
and IPRB). For details see section 5, Interrupt Controller.
Table 8.10 lists the in ter r upt sources.
Table 8.10 ITU Interrupt Sources
Channel Interrupt Source Description Priority*
0IMIA0
IMIB0
OVI0
Compare match/input capture A0
Compare match/input capture B0
Overflow 0
High
1IMIA1
IMIB1
OVI1
Compare match/input capture A1
Compare match/input capture B1
Overflow 1
2IMIA2
IMIB2
OVI2
Compare match/input capture A2
Compare match/input capture B2
Overflow 2
3IMIA3
IMIB3
OVI3
Compare match/input capture A3
Compare match/input capture B3
Overflow 3
4IMIA4
IMIB4
OVI4
Compare match/input capture A4
Compare match/input capture B4
Overflow 4 Low
Note: *The priority immediately after a reset is indicated. In ter-channel priorities can be
changed by settings in IPRA and IPRB.
Section 8 16-Bit Integrated Timer Unit (ITU)
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8.6 Usage Notes
This section describes contention and other matters requiring sp ecial attention during ITU
operations.
Contention between TCNT Write and Clear
If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing of the counter takes
priority and the write is not performed. See figure 8.61.
φ
Address
Internal write signal
Counter clear signal
TCNT
TCNT write cycle
TCNT address
N H'0000
T
1
T
2
T
3
Figure 8.61 Contention between TCNT Write and Clear
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Contention between TCNT Word Write and Increment
If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and
TCNT is not incremented. See figure 8.62.
φ
Address
Internal write signal
TCNT input clock
TCNT N
TCNT address
M
TCNT write data
TCNT word write cycle
T
1
T
2
T
3
Figure 8.62 Contention between TCNT Word Write and Increment
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between TCNT Byte Write and Increment
If an increment pulse occurs in the T2 or T3 state of a TCNT byte write cycle, writing takes priority
and TCNT is not in cr em ented. The TCNT byte that was not written retains its p r evious value. See
figure 8.63, which shows an increment pulse occurring in the T2 state of a byte write to TCNTH.
φ
Address
Internal write signal
TCNT input clock
TCNTH
TCNTL
TCNTH byte write cycle
T1T2T3
N
TCNTH address
M
TCNT write data
XXX + 1
Figure 8.63 Contention between TCNT Byte Write and Increment
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between General Register Write and Compare Match
If a compare match occurs in the T3 state of a general register wr ite cycle, writing takes prio r ity
and the compare match signal is inhibited. See figure 8.64.
φ
Address
Internal write signal
TCNT
GR
Compare match signal
General register write cycle
T
1
T
2
T
3
N
GR address
M
N N + 1
General register write data
Inhibited
Figure 8.64 Contention between General Register Write and Compare Match
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between TCNT Write and Overflow or Underflow
If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority and the counter
is not incremented. OVF is set to 1. The same holds for underflow. See figure 8.65.
φ
Address
Internal write signal
TCNT input clock
Overflow signal
TCNT
OVF
H'FFFF
TCNT address
M
TCNT write data
TCNT write cycle
T1T2T3
Figure 8.65 Contention between TCNT Write and Overflow
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between General Register Read a nd Input Capture
If an input capture signal occurs during the T3 state of a general register read cycle, the value
before input capture is read. See figure 8.66.
φ
Address
Internal read signal
Input capture signal
GR
Internal data bus
GR address
X
General register read cycle
T1T2T3
XM
Figure 8.66 Content io n bet ween General Register Read a nd Input Capture
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between Counter Clearing by Input Capture and Counter Increment
If an input capture signal and counter increment signal occur simultaneously, the counter is
cleared according to the input capture signal. The counter is not incremented by the increment
signal. The value before the counter is cleared is transferred to the general register. See figure
8.67.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
GR N
N H'0000
Figure 8.67 Contention between Counter Clearing by Input Capture and
Counter Increment
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between General Register Write and Input Capture
If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes
priority and th e write to the general register is no t perf ormed. See figure 8.68.
φ
Address
Internal write signal
Input capture signal
TCNT
GR M
GR address
General register write cycle
T1T2T3
M
Figure 8.68 Content io n bet ween General Register Write a nd Input Capture
Note on Waveform Period Setting
When a counter is cleared by compare match, the counter is cleared in the last state at which the
TCNT value matche s the general register v alue, at the time when this value would normally be
updated to the next count. The actual counter frequency is therefore given by the following
formula:
f = φ
(N + 1)
(f: counter frequency. φ: system clock frequency. N: value set in general register.)
Section 8 16-Bit Integrated Timer Unit (ITU)
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Contention between Buf fer Register Write and I nput Capture
If a buffer register is used for input capture buffering and an input capture sign al occurs in the T3
state of a write cycle, input capture takes prior ity and the write to the buffer register is not
performed. See figure 8.69.
φ
Address
Internal write signal
Input capture signal
GR
BR
BR address
Buffer register write cycle
T
1
T
2
T
3
NX
MN
TCNT value
Figure 8.69 Contention between Buffer Register Write and Input Capture
Section 8 16-Bit Integrated Timer Unit (ITU)
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Note on Synchro nous Preset
When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of
all synchronized counters assume the same value as the counter that was addressed.
(Example) When channels 2 and 3 are synchronized
• Byte write to channel 2 or byte write to channel 3
TCNT2
TCNT3
W
Y
X
Z
TCNT2
TCNT3
A
A
X
X
TCNT2
TCNT3
Y
Y
A
A
TCNT2
TCNT3
W
Y
X
Z
TCNT2
TCNT3
A
A
B
B
• Word write to channel 2 or word write to channel 3
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Upper byte Lower byte
Write A to upper byte
of channel 2
Write A to lower byte
of channel 3
Write AB word to
channel 2 or 3
Note on Setup of Reset-Synchronized PWM Mode and Complement ary PWM Mode
When setting bits CMD1 and CMD0 in TFCR, take the following precautions:
• Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped.
• Do not switch directly between reset-synchronized PWM mode and complementary PWM
mode. First switch to normal mode (by clearing bit CMD1 to 0), then select reset-synchronized
PWM mode or complementary PWM mode.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 286 of 682
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ITU Operating Modes
Table 8.11 (a) ITU Operating Modes (Channel 0)
Register Settings
TSNC TMDR TFCR TOCR TOER TIOR0 TCR0
Reset-
Synchro-
nized
PWM
Comple-
mentary
PWM
Output
Level
Select
Synchro-
nization Buffer-
ing Master
Enable Clear
Select Clock
Select
Operating Mode
MDF FDIR PWM XTGD IOA IOB
Synchronous preset SYNC0 = 1 —— — — ——— —
PWM mode ——PWM0 = 1 — — ——— — — *
Output compare A ——PWM0 = 0 — — ——— —IOA2 = 0
Other bits
unrestricted
Output compare B —— — — ——— — IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM0 = 0 — — ——— —IOA2 = 1
Other bits
unrestricted
Input capture B ——PWM0 = 0 — — ——— — IOB2 = 1
Other bits
unrestricted
Counter By compare —— — — ——— — CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare —— — — ——— — CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC0 = 1 —— — — ——— — CCLR1 = 1
chronous CCLR0 = 1
clear
Legend: : Setting available (valid). —: Setting does not affect this mode.
Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
Section 8 16-Bit Integrated Timer Unit (ITU)
Rev.3.00 Mar. 26, 2007 Page 287 of 682
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Table 8.11 (b) ITU Operat ing Modes (Channel 1)
Register Settings
TSNC TMDR TFCR TOCR TOER TIOR1 TCR1
Reset-
Synchro-
nized
PWM
Comple-
mentary
PWM
Output
Level
Select
Synchro-
nization Buffer-
ing Master
Enable Clear
Select Clock
Select
Operating Mode
MDF FDIR PWM XTGD IOA IOB
Synchronous preset SYNC1 = 1 —— — — —— — —
PWM mode ——PWM1 = 1 —————— — *
1
Output compare A ——PWM1 = 0 ——————IOA2 = 0
Other bits
unrestricted
Output compare B —— — — —— — — IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM1 = 0 ———*
2
——IOA2 = 1
Other bits
unrestricted
Input capture B ——PWM1 = 0 —————— IOB2 = 1
Other bits
unrestricted
Counter By compare —— — — —— — — CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare —— — — —— — — CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC1 = 1 —— — — —— — — CCLR1 = 1
chronous CCLR0 = 1
clear
Legend: : Setting available (valid). —: Setting does not affect this mode.
Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Table 8.11 (c) ITU Operating Modes (Channel 2)
Register Settings
TSNC TMDR TFCR TOCR TOER TIOR2 TCR2
Reset-
Synchro-
nized
PWM
Comple-
mentary
PWM
Output
Level
Select
Synchro-
nization Buffer-
ing Master
Enable Clear
Select Clock
Select
Operating Mode
MDF FDIR PWM XTGD IOA IOB
Synchronous preset SYNC2 = 1 ———————
PWM mode —PWM2 = 1 ——————— *
Output compare A —PWM2 = 0 ——————IOA2 = 0
Other bits
unrestricted
Output compare B ———————IOB2 = 0
Other bits
unrestricted
Input capture A —PWM2 = 0 ——————IOA2 = 1
Other bits
unrestricted
Input capture B —PWM2 = 0 —————— IOB2 = 1
Other bits
unrestricted
Counter By compare ——————— CCLR1 = 0
clearing match/input CCLR0 = 1
capture A
By compare ——————— CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC2 = 1 ——————— CCLR1 = 1
chronous CCLR0 = 1
clear
Phase counting MDF = 1 —————— —
mode
Legend: : Setting available (valid). —: Setting does not affect this mode.
Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously , the compare match signal is inhibited.
Section 8 16-Bit Integrated Timer Unit (ITU)
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Table 8.11 (d) ITU Operat ing Modes (Channel 3)
Register Settings
TSNC TMDR TFCR TOCR TOER TIOR3 TCR3
Comple-
mentary
PWM
Reset-
Synchro-
nized PWM
Output
Level
Select
Synchro-
nization Master
Enable Clear
Select Clock
Select
Operating Mode
MDF FDIR PWM Buffering XTGD IOA IOB
Synchronous preset SYNC3 = 1 —— ——
PWM mode ——PWM3 = 1 CMD1 = 0 CMD1 = 0 —— —
Output compare A ——PWM3 = 0 CMD1 = 0 CMD1 = 0 —— IOA2 = 0
Other bits
unrestricted
Output compare B —— CMD1 = 0 CMD1 = 0 —— IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM3 = 0 CMD1 = 0 CMD1 = 0 ——EA3 ignored IOA2 = 1
Other bits Other bits
unrestricted unrestricted
Input capture B ——PWM3 = 0 CMD1 = 0 CMD1 = 0 ——EB3 ignored IOB2 = 1
Other bits Other bits
unrestricted unrestricted
Counter By compare —— Illegal setting: —— CCLR1 = 0
clearing match/input CMD1 = 1 CCLR0 = 1
capture A CMD0 = 0
By compare —— CMD1 = 0 CMD1 = 0 —— CCLR1 = 1
match/input CCLR0 = 0
capture B
Syn- SYNC3 = 1 —— Illegal setting: —— CCLR1 = 1
chronous CMD1 = 1 CCLR0 = 1
clear CMD0 = 0
Complementary —— —CMD1 = 1 CMD1 = 1 ——CCLR1 = 0
*
5
PWM mode CMD0 = 0 CMD0 = 0 CCLR0 = 0
Reset-synchronized —— —CMD1 = 1 CMD1 = 1 ——CCLR1 = 0
PWM mode CMD0 = 1 CMD0 = 1 CCLR0 = 1
Buf fering —— BFA3 = 1 ——
(BRA) Other bits
unrestricted
Buffering —— BFB3 = 1 ——
(BRB) Other bits
unrestricted
Legend: : Setting available (valid). —: Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. Use the input capture A function in channel 1.
*
2
*
1
*
1
*
1
*
1
*
1
*
1
*
6
*
6
*
4
*
3
*
3
Section 8 16-Bit Integrated Timer Unit (ITU)
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Table 8.11 (e) ITU Operating Modes (Channel 4)
Register Settings
TSNC TMDR TFCR TOCR TOER TIOR4 TCR4
Comple-
mentary
PWM
Reset-
Synchro-
nized PWM
Output
Level
Select
Synchro-
nization Master
Enable Clear
Select Clock
Select
Operating Mode
MDF FDIR PWM Buffering XTGD IOA IOB
Synchronous preset SYNC4 = 1 —— ——
PWM mode ——PWM4 = 1 CMD1 = 0 CMD1 = 0 —— —
Output compare A ——PWM4 = 0 CMD1 = 0 CMD1 = 0 —— IOA2 = 0
Other bits
unrestricted
Output compare B —— CMD1 = 0 CMD1 = 0 —— IOB2 = 0
Other bits
unrestricted
Input capture A ——PWM4 = 0 CMD1 = 0 CMD1 = 0 ——EA4 ignored IOA2 = 1
Other bits Other bits
unrestricted unrestricted
Input capture B ——PWM4 = 0 CMD1 = 0 CMD1 = 0 ——EB4 ignored IOB2 = 1
Other bits Other bits
unrestricted unrestricted
Counter By compare —— Illegal setting: —— CCLR1 = 0
clearing match/input CMD1 = 1 CCLR0 = 1
capture A CMD0 = 0
By compare —— Illegal setting: —— CCLR1 = 1
match/input CMD1 = 1 CCLR0 = 0
capture B CMD0 = 0
Syn- SYNC4 = 1 —— Illegal setting: —— CCLR1 = 1
chronous CMD1 = 1 CCLR0 = 1
clear CMD0 = 0
Complementary —— —CMD1 = 1 CMD1 = 1 ——CCLR1 = 0
PWM mode CMD0 = 0 CMD0 = 0 CCLR0 = 0
Reset-synchronized —— —CMD1 = 1 CMD1 = 1 ——
*6
*6
*5
PWM mode CMD0 = 1 CMD0 = 1
Buffering —— BFA4 = 1 ——
(BRA) Other bits
unrestricted
Buffering —— BFB4 = 1 ——
(BRB) Other bits
unrestricted
Legend: : Setting available (valid). —: Setting does not affect this mode.
Notes: 1. Master enable bit settings are valid only during waveform output.
2. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited.
3. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected.
4. When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. W aveform output is not affected.
5. In complementary PWM mode, select the same clock source for channels 3 and 4.
6. TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently, without affecting waveform output.
*2
*1
*1
*4
*4
*4
*3
*3
*1
*1
*1
*1
Section 9 Programmable Timing Pattern Controller
Rev.3.00 Mar. 26, 2007 Page 291 of 682
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Section 9 Programmable Timing Pattern Controller
9.1 Overview
The H8/3039 Gr oup has a built-in program m a ble timing pattern controller (T PC)* that provid es
pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse
outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and
independently.
9.1.1 Features
TPC features are listed below.
• 15-bit output data
Maximum 15-bit data can be output. TPC output can be enabled on a bit-by-bit basis.
• Four output groups and one 3-bit output.
Output trigger signals can be selected in 4-bit groups to provide up to three different 4-bit
outputs and one 3-bit output.
• Selectable output trigger signals
Output trigger signals can be selected for each group from the compare-match signals of four
ITU channels.
• Non-overlap mode
A non-overlap margin can be provided between pulse outputs.
Note: * Note that since this LSI does not have a TP14 pin, it is a 15-bit programmable timing
pattern controller (TPC).
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9.1.2 Block Diagram
Figure 9.1 shows a block diagram of th e TPC.
PADDR
NDERA
TPMR
PBDDR
NDERB
TPCR
Internal
data bus
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
15
14
13
12
11
10
Control logic
ITU compare match signals
Pulse output
pins, group 3
PBDR
PADR
Legend:
TPMR:
TPCR:
NDERB:
NDERA:
PBDDR:
PADDR:
NDRB:
NDRA:
PBDR:
PADR:
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
TPC output mode register
TPC output control register
Next data enable register B
Next data enable register A
Port B data direction register
Port A data direction register
Next data register B
Next data register A
Port B data register
Port A data register
NDRB
NDRA
( )*
Note: * Since this LSI does not have this pin, this signal cannot be output to the outside.
9
8
7
6
5
4
3
2
1
0
Figure 9.1 TPC Block Diagram
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9.1.3 TPC Pins
Table 9.1 summarizes the TPC output pins.
Table 9.1 TPC Pins
Name Symbol I/O Function
TPC output 0 TP0Output Group 0 pulse output
TPC output 1 TP1Output
TPC output 2 TP2Output
TPC output 3 TP3Output
TPC output 4 TP4Output Group 1 pulse output
TPC output 5 TP5Output
TPC output 6 TP6Output
TPC output 7 TP7Output
TPC output 8 TP8Output Group 2 pulse output
TPC output 9 TP9Output
TPC output 10 TP10 Output
TPC output 11 TP11 Output
TPC output 12 TP12 Output Group 3 pulse output
TPC output 13 TP13 Output
(TPC output 14)*(TP14)*(Output)*
TPC output 15 TP15 Output
Note: *Since this LSI does not have this pin, this signal cannot be output to the outside.
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9.1.4 Registers
Table 9.2 summarizes the TPC registers.
Table 9.2 TPC Registers
Address*1Name Abbreviation R/W Initial Value
H'FFD1 Port A data direction register PADDR W H'00
H'FFD3 Port A data register PADR R/(W)*2H'00
H'FFD4 Port B data direction register PBDDR W H'00
H'FFD6 Port B data register PBDR R/(W)*2H'00
H'FFA0 TPC output mode register TPMR R/W H'F0
H'FFA1 TPC output control regi ster TPCR R/W H'FF
H'FFA2 Next data enable register B NDERB R/W H'00
H'FFA3 Next data enable register A NDERA R/W H'00
H'FFA5/
H'FFA7*3Next data register A NDRA R/W H'00
H'FFA4/
H'FFA6*3Next data register B NDRB R/W H'00
Notes: 1. Lower 16 bits of the address.
2. Bits used for TPC output cannot be written.
3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output
groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA
address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB
is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by
settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6
for group 2 and H'FFA4 for group 3.
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9.2 Register Descriptions
9.2.1 Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
Initial value
Read/Write
7
PA DDR
0
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
7
6
PA DDR
0
W
6
5
PA DDR
0
W
5
4
PA DDR
0
W
4
3
PA DDR
0
W
3
2
PA DDR
0
W
2
1
PA DDR
0
W
1
0
PA DDR
0
W
0
Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output mu st
be set to 1. For further information about PADDR, see section 7.10, Port A.
9.2.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
Initial value
Read/Write
Note: * Bits selected for TPC output by NDERA settings become read-only bits.
0
PA
0
R/(W)
0
1
PA
0
R/(W)
1
2
PA
0
R/(W)
2
3
PA
0
R/(W)
3
4
PA
0
R/(W)
4
5
PA
0
R/(W)
5
6
PA
0
R/(W)
6
7
PA
0
R/(W)
7
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
********
For further information about PADR, see section 7.10, Port A.
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9.2.3 Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Bit
Initial value
Read/Write
7
PB DDR
0
W
Port B data direction 7, 5 to 0
These bits select input or
output for port B pins
7
6
—
0
W
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
Reserved bit
Port B is multip lexed with pin s TP15, TP13 to TP8. Bits corresponding to pins used for TPC output
must be set to 1. For further information about PBDDR, see section 7.11, Port B.
9.2.4 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
Bit
Initial value
Read/Write
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
0
PB
0
R/(W)
0
1
PB
0
R/(W)
1
2
PB
0
R/(W)
2
3
PB
0
R/(W)
3
4
PB
0
R/(W)
4
5
PB
0
R/(W)
5
6
—
0
R/(W)
7
PB
0
R/(W)
7
Port B data 7, 5 to 0
These bits store output data
for TPC output groups 2 and 3
********
Reserved bit
For further information about PBDR, see section 7.11, Port B.
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9.2.5 Next Data Register A (NDRA)
NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups
1 and 0 (pins TP7 to TP0). During TPC output, when an ITU co mpare match event specified in
TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of
NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or
different output triggers.
NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Same Trigger for TPC Output G roups 0 and 1
If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address
is H'FFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFA7
consists entirely of reserved bits that cannot be modified and always read 1.
Address H'FFA5
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Next data 7 to 4
These bits store the next output
data for TPC output group 1
Address H'FFA7
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits
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Different Triggers for TPC Output Groups 0 and 1
If TPC output groups 0 and 1 are triggered by different compare match events, the address of the
upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is
H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that
cannot be modified and always read 1.
Address H'FFA5
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
Reserved bitsNext data 7 to 4
These bits store the next output
data for TPC output group 1
Address H'FFA7
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
Reserved bits
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9.2.6 Next Data Register B (NDRB)
NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups
3 and 2 (pins TP15 to TP8)*. During TPC output, when an ITU compare match event specified in
TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of
NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or
different output triggers.
NDRB is initialized to H'00 by a reset and in hardware standby mod e . I t is not initialized in
software standby mode.
Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside.
Same Trigger for TPC Output G roups 2 and 3
If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address
is H'FFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFA6
consists entirely of reserved bits that cannot be modified and always read 1.
Address H'FFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Next data 15 to 12
These bits store the next output
data for TPC output group 3
Address H'FFA6
Bit
Initial value
Read/Write
0
—
1
—
1
—
1
—
2
—
1
—
3
—
1
—
4
—
1
—
5
—
1
—
6
—
1
—
7
—
1
—
Reserved bits
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Different Triggers for TPC Output Groups 2 and 3
If TPC output groups 2 and 3 are triggered by different compare match events, the address of the
upper 4 bits of NDRB (group 3)* is H'FFA4 and the address of the lower 4 bits (group 2) is
H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that
cannot be modified and always read 1.
Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip.
Address H'FFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
—
1
—
2
—
1
—
1
—
1
—
0
—
1
—
Reserved bitsNext data 15 to 12
These bits store the next output
data for TPC output group 3
Address H'FFA6
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
Next data 11 to 8
These bits store the next output
data for TPC output group 2
Reserved bits
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9.2.7 Next Data Enable Register A (NDERA)
NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0
(TP7 to TP0) on a bit-by-bit basis.
Bit
Initial value
Read/Write
0
NDER0
0
R/W
1
NDER1
0
R/W
2
NDER2
0
R/W
3
NDER3
0
R/W
4
NDER4
0
R/W
5
NDER5
0
R/W
6
NDER6
0
R/W
7
NDER7
0
R/W
Next data enable 7 to 0
These bits enable or disable
TPC output groups 1 and 0
If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in
the TPC output control register (TPCR) occurs, th e NDRA value is automa tically transferred to
the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is
not transferred from NDRA to PADR and the output value does not change.
NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC
output groups 1 and 0 (TP7 to TP0) on a bit-by-b it basis .
Bits 7 to 0
NDER7 to NDER0 Description
0 TPC outputs TP7 to TP0 are disabled
(NDR7 to NDR0 are not transferred to PA7 to PA0) (Initial value)
1 TPC outputs TP7 to TP0 are enabled
(NDR7 to NDR0 are transfe rred to PA7 to PA0)
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9.2.8 Next Data Enable Register B (NDERB)
NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2
(TP15 to TP8)* on a bit-by-bit basis .
Bit
Initial value
Read/Write
0
NDER8
0
R/W
1
NDER9
0
R/W
2
NDER10
0
R/W
3
NDER11
0
R/W
4
NDER12
0
R/W
5
NDER13
0
R/W
6
NDER14
0
R/W
7
NDER15
0
R/W
Next data enable 15 to 8
These bits enable or disable
TPC output groups 3 and 2
If a bit is enabled for TPC output by NDERB, then when the IT U compare match event selected in
the TPC output control register ( T PCR) occurs, the NDRB v alue is automatically tr ansferred to the
corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not
transferred from NDRB to PBDR and the output value does not change.
NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not in itialized in
software standby mode.
Bits 7 to 0—Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC
output groups 3 and 2 (TP15 to TP8)* on a bit-by-bit basis.
Bits 7 to 0
NDER15 to NDER8 Description
0 TPC outputs TP15 to TP8 are disabled
(NDR15 to NDR8 are not transferred to PB7 to PB0) (Initial value)
1 TPC outputs TP15 to TP8 are enabled
(NDR15 to NDR8 are transferred to PB7 to PB0)
Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside.
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9.2.9 TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
Initial value
Read/Write
7
G3CMS1
1
R/W
6
G3CMS0
1
R/W
5
G2CMS1
1
R/W
4
G2CMS0
1
R/W
3
G1CMS1
1
R/W
0
G0CMS0
1
R/W
2
G1CMS0
1
R/W
1
G0CMS1
1
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP
15
to TP
12
)*
Group 2 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 2
(TP
11
to TP
8
)
Group 1 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 1
(TP
7
to TP
4
)
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP
3
to TP
0
)
Note: * Since this LSI does not have a TP
14
pin, the TP
14
signal cannot be output to the outside.
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP15 to TP12)*.
Bit 7
G3CMS1 Bit6
G3CMS0 Description
0 0 TPC output group 3 (TP15 to TP12)* is triggered by compare match
in ITU channel 0
1 TPC output group 3 (TP15 to TP12)* is triggered by compare match
in ITU channel 1
1 0 TPC output group 3 (TP15 to TP12)* is triggered by compare match
in ITU channel 2
1 TPC output group 3 (TP15 to TP12)* is triggered by compare match
in ITU channel 3 (Initial value)
Note: *Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip.
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits
select the compare match event that triggers TPC output group 2 (TP11 to TP8).
Bit 5
G2CMS1 Bit4
G2CMS0 Description
0 0 TPC output group 2 (TP
11
to T P
8
) is triggered by compare match in
ITU channel 0
1 TPC output group 2 (TP
11
to T P
8
) is triggered by compare match in
ITU channel 1
1 0 TPC output group 2 (TP
11
to T P
8
) is triggered by compare match in
ITU channel 2
1 TPC output group 2 (TP
11
to T P
8
) is triggered by compare match in
ITU channel 3 (Initial value)
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Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits
select the compare match event that triggers TPC output group 1 (TP7 to TP4).
Bit 3
G1CMS1 Bit2
G1CMS0 Description
0 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in
ITU channel 0
1 TPC output group 1 (TP7 to TP4) is triggered by compare match in
ITU channel 1
1 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in
ITU channel 2
1 TPC output group 1 (TP7 to TP4) is triggered by compare match in
ITU channel 3 (Initial value)
Bits 1 and 0—Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits
select the compare match event that triggers TPC output group 0 (TP3 to TP0).
Bit1
G0CMS1 Bit0
G0CMS0 Description
0 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in
ITU channel 0
1 TPC output group 0 (TP3 to TP0) is triggered by compare match in
ITU channel 1
1 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in
ITU channel 2
1 TPC output group 0 (TP3 to TP0) is triggered by compare match in
ITU channel 3 (Initial value)
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9.2.10 TPC Output Mode Register (TPMR)
TPMR is an 8-bit r eadable/writable reg ister that selects normal or non-overlapping TPC ou tput f or
each group.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
G3NOV
0
R/W
0
G0NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
Group 3 non-overlap
Selects non-overlapping TPC
output for group 3 (TP to TP )*
Reserved bits
Group 2 non-overlap
Selects non-overlapping TPC
output for group 2 (TP to TP )
Group 1 non-overlap
Selects non-overlapping TPC
output for group 1 (TP to TP )
Group 0 non-overlap
Selects non-overlapping TPC
output for group 0 (TP to TP )
15 12
11 8
74
30
Note: * Since this LSI does not have a TP
14
pin, the TP
14
signal cannot be output to the outside.
The output trigger period of a non-overlapping TPC outpu t waveform is set in general register B
(GRB) in the IT U channel selected for output triggering. The non-overlap margin is set in general
register A (GRA). The output values change at compare match A and B. For details see section
9.3.4, Non-Overlapping TPC Output.
TPMR is initialized to H'F0 by a reset and in h a rdware standby mode. It is not initialized in
software standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
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Bit 3—Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for
group 3 (TP15 to TP12)*.
Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip.
Bit 3
G3NOV Description
0 Normal TPC output in group 3 (output values change at compare match A in the
selected ITU cha nnel ) (Initial val ue)
1 Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare
match A and B in the selected ITU channel)
Bit 2—Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for
group 2 (TP11 to TP8).
Bit 2
G2NOV Description
0 Normal TPC output in group 2 (output values change at compare match A in the
selected ITU cha nnel ) (Initial val ue)
1 Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare
match A and B in the selected ITU channel)
Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for
group 1 (TP7 to TP4).
Bit 1
G1NOV Description
0 Normal TPC output in group 1 (output values change at compare match A in the
selected ITU cha nnel ) (Initial val ue)
1 Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare
match A and B in the selected ITU channel)
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Bit 0—Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for
group 0 (TP3 to TP0).
Bit 0
G0NOV Description
0 Normal TPC output in group 0 (output values change at compare match A in the
selected ITU cha nnel ) (Initial val ue)
1 Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare
match A and B in the selected ITU channel)
9.3 Operation
9.3.1 Overview
When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output
is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents.
When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit
contents are transferred to PADR or PBDR to update the output values.
Figure 9. 2 illustrates the TPC outp ut operation. Table 9.3 summarizes the TPC o perating
conditions.
DDR NDER
QQ
TPC output pin
DR NDR
C
QD QDInternal
data bus
Output trigger signal
Figure 9.2 TPC Output Operation
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Table 9.3 TPC Operating Condit ions
NDER DDR Pin Function
0 0 Generic input port
1 Generic output port
1 0 Generic input port (but the DR bit is a read-only bit, and when compare
match occurs , the NDR bit va lue is transferred to the DR bit)
1 TPC pulse output
Sequential o utput of up to 16-bit patterns is possible by writing new outp ut data to NDRA and
NDRB before the next compare match. For information on non-overlapping operation, see section
9.3.4, Non-Overlapping TPC Output.
9.3.2 Output Timing
If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output
when the selected compare match event occurs. Figure 9.3 shows the timing of these operations
for the case of normal output in groups 0 and 1, triggered by compare match A.
φ
TCNT
GRA
Compare
match A signal
NDRA
PADR
TP to TP
07
N
N
n
m
m
N + 1
n
n
Figure 9.3 Timing of Transfer of Next Data Register Contents and Output (Example)
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9.3.3 Normal TPC Output
Sample Setup Pr ocedure for Normal TP C Output
Figure 9.4 shows a sample procedure for setting up normal TPC output.
Normal TPC output
Set next TPC output data
Compare match? No
Yes
Set next TPC output data
ITU setup
Port and
TPC setup
ITU setup 10
11
9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Set TIOR to make GRA an output compare
register (with output inhibited).
Set the TPC output trigger period.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TIER.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port
pins to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
Select the ITU compare match event to be
used as the TPC output trigger in TPCR.
Set the next TPC output values in the NDR bits.
Set the STR bit to 1 in TSTR to start the
timer counter.
At each IMFA interrupt, set the next output
values in the NDR bits.
1
2
3
4
5
6
7
8
Select GR functions
Set GRA value
Select counting operation
Select interrupt request
Start counter
Set initial output data
Select port output
Enable TPC output
Select TPC output trigger
Figure 9.4 Setup Procedure for Normal TPC Output (Example)
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Example of Normal TPC Output (Example of Five-Phase Pulse Output)
Figure 9.5 shows an example in which the TPC is used for cyclic five-phase pulse output.
GRA
H'0000
NDRA
PADR
TP7
TP6
TP5
TP4
TP3
•
•
•
•
Time
80
TCNT
TCNT value
C0 40 60 20 30 10 18 08 88 80 C0
Compare match
The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
H'F8 is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRA.
The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents
are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRA.
Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts.
00
80 C0 40 60 20 30 10 18 08 88 80 C0 40
Figure 9.5 Normal TPC Output Example (Five-Phase Pulse Output)
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9.3.4 Non-Overlapping TPC Output
Sample Setup P rocedure for Non-Overlapping TPC Output
Figure 9.6 shows a sample procedure for setting up non-overlapping TPC output.
Non-overlapping
TPC output
Set next TPC output data
Compare match A? No
Yes
Set next TPC output data
Start counter
ITU setup
Port and
TPC setup
ITU setup
Set initial output data
Set up TPC output
Enable TPC transfer
Select TPC transfer trigger
Select non-overlapping groups
1
2
3
4
12
10
11
5
6
7
8
9
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Set TIOR to make GRA and GRB output
compare registers (with output inhibited).
Set the TPC output trigger period in GRB
and the non-overlap margin in GRA.
Select the counter clock source with bits
TPSC2 to TPSC0 in TCR. Select the counter
clear source with bits CCLR1 and CCLR0.
Enable the IMFA interrupt in TIER.
Set the initial output values in the DR bits
of the input/output port pins to be used for
TPC output.
Set the DDR bits of the input/output port pins
to be used for TPC output to 1.
Set the NDER bits of the pins to be used for
TPC output to 1.
In TPCR, select the ITU compare match
event to be used as the TPC output trigger.
In TPMR, select the groups that will operate
in non-overlap mode.
Set the next TPC output values in the NDR
bits.
Set the STR bit to 1 in TSTR to start the timer
counter.
At each IMFA interrupt, write the next output
value in the NDR bits.
Select GR functions
Set GR values
Select counting operation
Select interrupt requests
Figure 9.6 Set up P r ocedure for Non-Overla pping TPC Output (Exa mple)
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Example of Non-Overla pping TPC Output
(Example of F our-Phase Complement ary Non-Overlapping Output )
Figure 9.7 shows an example of the use of TPC output for four-phase complementary non-
overlapping pulse output.
GRB
H'0000
NDRA
PADR
TP
7
TP
6
TP
5
TP
4
TP
3
TP
2
TP
1
TP
0
Time
95
00
65
95
59 56 95 65
05 65 41 59 50 56 14 95 05 65
TCNT
period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable
IMFA interrupts.
H'FF is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
TCNT value
Non-overlap margin
The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output
compare registers and the counter will be cleared by compare match B. The TPC output trigger
•
•
•
•
Bits G1NOV and G0NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is
written in NDRA.
The timer counter in this ITU channel is started. When compare match B occurs, outputs change from
1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed
by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRA.
Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95...
at successive IMFA interrupts.
GRA
Figure 9.7 Non-Overlapping TPC Output Example (Four-Phase Complementary
Non-Overlapping Pulse Output)
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9.3.5 TPC Output Triggering by Input Capt ure
TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions
as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by
the input capture signal. Figure 9.8 shows the timing.
φ
TIOC pin
Input capture
signal
NDR
DR N
N
M
Figure 9.8 TP C Output Triggering by Input Capture (Example)
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9.4 Usage Notes
9.4.1 Operation of TPC Output Pins
TP0 to TP15* are multiplexed with ITU pin fun c tions. When ITU output is enab led, th e
corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits
takes place, however, regardless of the usage of the pin.
Pin functions should be changed only under conditio ns in which the output trigger even t will not
occur.
Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside.
9.4.2 Note on Non-Overlapping Output
During non-overlapping operation, the tran sfer of NDR bit values to DR bits takes place as
follows.
1. NDR bits are always transferred to DR bits at compare match A.
2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their valu e is 1.
Figure 9.9 illustrates the non-overlapping TPC output operation.
DDR NDER
QQ
TPC output pin
DR NDR
C
QD QD
Compare match A
Compare match B
Figure 9.9 Non-Overlapping TPC Output
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Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A. NDR contents should not be altered during the interval from compare match B
to compare match A (the non-overlap margin).
This can be accomplished by having the IMFA interrupt service routine write the next data in
NDR, or by h aving the IMFA interrupt activate the DMAC. The n e xt data must be written before
the next compare match B occurs.
Figure 9.10 shows the timing relationships.
Compare
match A
Compare
match B
NDR write
NDR
NDR write
DR
0/1 output 0/1 output0 output 0 output
Do not write
to NDR in this
interval
Do not write
to NDR in this
interval
Write to NDR
in this interval
Write to NDR
in this interval
Figure 9.10 Non-Overlapping Operation and NDR Write Timing
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Section 10 Watchdog Timer
10.1 Overview
The H8/3039 Group has an on-chip watchdog timer (WDT). The WDT has two selectable
functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an
interval timer. As a watchdog timer, it generates a reset signal for the H8/3039 Group chip if a
system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval
timer operation, an interval timer interrupt is requested at each TCNT overflow.
10.1.1 Features
WDT features are listed below.
• Selection of eight counter clock sources
φ/2, φ/32, φ/64, φ/128, φ/256, φ/512, φ/2048, or φ/4096
• Interval timer option
• Timer counter overflow generates a reset signal or interrupt.
The reset signal is generated in watchdog tim er operation. An interv al tim er inter rup t is
generated in inter val timer operation.
• Watchdog timer reset signal resets the entire H8/3039 Group chip internally, and can also be
output externally.*
The reset signal generated by timer counter overflow during watchdog timer operation resets
the entire H8/3039 Group in ternally. An external reset signal can be output from the RESO pin
to reset other system devices simultaneously.
Note: * The RESO pin of the mask ROM version is the dedicated FWE input pin of the F-
ZTAT version. Therefore, the F-ZTAT version cannot output the reset signal to the
outside.
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10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the WDT.
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
TCNT
TCSR
RSTCSR
Reset control
Interrupt signal
Reset
(internal, external)
(interval timer) Interrupt
control
Overflow
Clock Clock
selector
Read/
write
control
Internal
data bus
Internal clock sources
Legend:
TCNT:
TCSR:
RSTCSR:
Timer counter
Timer control/status register
Reset control/status register
Figure 10.1 WDT Block Diagram
10.1.3 Pin Configuration
Table 10.1 describes the WDT output pin.*
Note: * Shows the mask ROM version pin. The F-ZTAT does not have any pins used by the
WDT. For F-ZTAT version, see section 15.9, Notes on Flash Memory
Programming/Erasing.
Table 10.1 WDT Pin
Name Abbreviation I/O Function
Reset output RESO Output*External output of the watchdog timer reset signal
Note: *Open-drain output. Externally pull-up to Vcc whether or not the reset output is used
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10.1.4 Register Configuration
Table 10.2 summarizes the WDT registers.
Table 10.2 WDT Registers
Address*1
Write*2Read Name Abbreviation R/W Initial Value
H'FFA8 H'FFA8 Timer control/status register TCSR R/(W)*3H'18
H'FFA9 Timer counter TCNT R/W H'00
H'FFAA H'FFAB Reset cont rol/ stat us register RSTCSR R/(W)*3H'3F
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7 to clear the flag.
10.2 Register Descriptions
10.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable and writable* up-counter.
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
When the TME bit is set to 1 in TCSR, TCNT starts cou nting pulses generated from an in ternal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), th e OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a r e set and when
the TME bit is cleared to 0.
Note: * TCNT is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
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10.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode
and clock source.
Note: * TCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
Bit
Initial value
Read/Write
Note: * Only 0 can be written to clear the flag.
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Overflow flag
Status flag indicating overflow
Clock select
These bits select the
TCNT clock source
Timer mode select
Selects the mode
Timer enable
Selects whether TCNT runs or halts
Reserved bits
Bits 7 to 5 are in itialized to 0 by a reset and in stan dby mode. Bits 2 to 0 are initialized to 0 by a
reset. In softwar e stan dby mode bits 2 to 0 are not initialized, but retain their previous values.
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Bit 7—Overflow Flag (OVF): Th is status flag indicates that the timer counter has overflowed
from H'FF to H'00.
Bit 7
OVF Description
0 [Clearing condition]
Cleared by reading OVF when OVF = 1, then writing 0 in OVF (Initial value)
1 [Setting condition]
Set when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/IT
ITIT
IT): Selects whether to use the WDT as a watchdog timer or
interval timer. I f used as an interval timer, the WDT generates an interval timer interrupt request
when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when
TCNT overflows.
Bit 6
WT/IT
ITIT
IT Description
0 Interval timer: reques ts interval timer interrupts (Initial value)
1 Watchdog timer: generates a reset signal
Bit 5—Timer Enable (TME) : Selects whether TCNT runs or is halted.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted (Initial value)
1 TCNT is counting
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2/1/0): Th ese bits select one of eight internal clock sources,
obtained by prescaling the system clock (φ), for input to TCNT.
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Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0 Description
000φ/2 (Initial value)
1φ/32
10φ/64
1φ/128
100φ/256
1φ/512
10φ/2048
1φ/4096
10.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable and writable* register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Note: * RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on
Register Access.
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written in bit 7 to clear the flag.
2. With the mask ROM version, enable and disable can be set. With the F-ZTAT version,
do not set enable.
7
WRST
0
R/(W)*
1
6
RSTOE
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Watchdog timer reset
Indicates that a reset signal has been generated
Reserved bits
Reset output enable*
2
Enables or disables external output of the reset signal
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
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Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signa l r e sets the entire chip
internally. I f bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin*1 to
initialize external sy stem devices.
Bit 7
WRST Description
0 [Clearing conditions ] (Initial val ue)
(1) Cleared to 0 by reset signal input at RES pin
(2) Cleared by reading WRST when WRST = 1, then writing 0 in WERST
1 [Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Out put Enable (RSTOE): Enables or disables external output at the RESO pin*1 of
the reset signal generated if TCNT overflows during watchdog timer operation.
Bit 6
RSTOE Description
0 Reset signal is not output externally (Initial value)
1 Reset signal is output exter nal ly*2
Notes: 1. Mask ROM version. Dedicated FWE input pin for F-ZTAT version.
2. Mask ROM version. Do not set to 1 with the F-ZTAT version.
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
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10.2.4 Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR
These registers must be written by a word transfer instruction. They cannot be wr itten by byte
instruction s. Fig ure 10.2 shows the for mat of data written to TCNT and TCSR. TCNT an d TCSR
both have the same write address. The write data must be contained in the lower byte of the
written word. The upper byte m ust contain H'5A (passwor d for TCNT) or H'A5 (password for
TCSR). This transf er s the write data fro m the lower byte to TCNT or TCSR.
15 8 7 0
H'5A Write dataAddress H'FFA8*
15 8 7 0
H'A5 Write dataAddress H'FFA8*
TCNT write
TCSR write
Note: * Lower 16 bits of the address.
Figure 10.2 Format of Data Written to TCNT and TCSR
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Writing to RSTCSR
RSTCSR must be written by a wor d transfer instruction. It cannot be written by byte tran sf er
instruction s. Fig ure 10.3 shows the fo rmat of data written to RSTCSR. To wr ite 0 in the WRST
bit, the write data must have H'A5 in the upper by te and H'00 in the lower byte. The H'00 in the
lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit, the upper byte must
contain H'5A and the lower byte must contain the write data. Writing this wo r d transfers a write
data value into the RSTOE bit.
15 8 7 0
H'A5 H'00Address H'FFAA*
15 8 7 0
H'5A Write dataAddress H'FFAA*
Writing 0 in WRST bit
Writing to RSTOE bit
Note: * Lower 16 bits of the address.
Figure 10.3 Format of Data Written to RSTCSR
Reading TCNT, TCSR, and RSTCSR
These registers are read like other registers. Byte access instructions can be used. The read
addresses are H'FFA8 for TCSR, H'FFA9 fo r T CNT, and H'FFAB for RST CSR, as listed in table
10.3.
Table 10.3 Read Addresses of TCNT, TCSR, and RSTCSR
Address*Register
H'FFA8 TCSR
H'FFA9 TCNT
H'FFAB RSTCSR
Note: *Lower 16 bits of the address .
Section 10 Watchdog Timer
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10.3 Operation
Operations when the WDT is used as a watchdog timer and as an interval timer are described
below.
10.3.1 Watchdog Timer Operation
Figure 10.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the
WT/IT and TME b its to 1 in TCSR. Software must prevent TCNT overflow by r ewr iting the
TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and
overflows due to a system crash etc., the H8/3039 Group is internally reset for a duration of 518
states.
The watchdog reset sig n a l can be externally output from the RESO pin* to reset external system
devices. The reset signal is output externally for 132 states. External output can be enabled or
disabled by the RSTOE bit in RSTCSR.
A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can
distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR.
If a RES reset and a watchdog reset occur simultaneously, the RES r e set takes prior ity.
Note: * Mask ROM version.
Since the RES pin is a dedicated FWE input pin with the F-ZTAT version, the reset
signal cannot be output to the outside.
Section 10 Watchdog Timer
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H'FF
H'00
RESO
WDT overflow
Start H'00 written
in TCNT Reset
TME set to 1
H'00 written
in TCNT
Internal
reset signal
518 states
132 states
TCNT count
value
OVF = 1
Figure 10.4 Watchdog Timer Operation (Mask ROM Version)
10.3.2 Interval Timer Operation
Figure 10 .5 illustr a tes interval timer operation. To use the WDT as an interval timer , clear bit
WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each
TCNT overflow. This function can be used to generate interval timer interrupts at regular
intervals.
TCNT
count value
Time t
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
Interval
timer
interrupt
WT/ = 0
TME = 1
IT
H'FF
H'00
Figure 10.5 Interval Timer Operation
Section 10 Watchdog Timer
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10.3.3 Timing of Setting of Overflow Flag (OVF)
Figure 10 .6 sh ows the timing of settin g of the OVF flag in TCSR. The OVF flag is set to 1 when
TCNT overflows. At the same time, a reset sign a l is generated in watchdog tim er oper a tion, or an
interval timer interrupt is genera ted in interval timer operation.
φ
TCNT
Overflow signal
OVF
H'FF H'00
Figure 10.6 Timing of Setting of OVF
Section 10 Watchdog Timer
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10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)
The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR.
Figure 10.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is
set to 1 when TCNT overflows and OVF is set to 1 . At the same time an internal r eset signal is
generated for the entire H8/3039 Group chip. This internal reset signal clears OVF to 0, but the
WRST bit rema ins set to 1. The reset ro utine must therefo r e clear the WRST bit.
φ
TCNT
Overflow signal
OVF
WRST
H'FF H'00
WDT internal
reset
Figure 10.7 Timing of Setting of WRST Bit and Internal Reset
10.4 Interrupts
During interval timer operation, an overflow generates an interval timer interrupt (WOVI) . The
interval timer interrupt is reque sted whenever the OVF bit is set to 1 in TCSR.
Section 10 Watchdog Timer
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10.5 Usage Notes
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write
takes priority and the timer count is not incremented. See figure 10.8.
φ
TCNT
TCNT NM
Counter write data
T
3
T
2
T
1
Write cycle: CPU writes to TCNT
Internal write
signal
TCNT input
clock
Figure 10.8 Contention between TCNT Write and Increment
Changing CKS2 to CKS0 Va lues
Halt TCNT by clearing the TME bit to 0 in TCSR before changin g the values of bits CKS2 to
CKS0.
Section 11 Serial Communication Interface
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Section 11 Serial Communication Interface
11.1 Overview
The H8/3039 Group has a serial communication interface (SCI) with two independent channels.
The two channels are functionally identical. The SCI can communicate in asynchronous or
synchronous mode. It also has a multiprocessor communication function for serial commun icatio n
among two or mo re processors.
When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted
independently. For details see section 17.6, Module Standby Function.
Channel 0 (SCI0) also has a smart card interface function conforming to the ISO/IEC7816-3
(Identification Card) standard. This function supports serial communication with a smart card. For
details, see section 12, Smart Card Interface.
11.1.1 Features
SCI features are listed below.
• Selection of asynchronous or synchronous mode for serial communication
a. Asynchronous mode
Serial data communication is synchronized one character at a time. The SCI can communicate
with a universal asynchronous receiver/transmitter (UART), asynchronous communication
interface adapter (ACIA), or other chip that employs standard asynchronous serial
communication. It can also communicate with two or more other processors using the
multiprocessor communication function. There are twelve selectable serial d a ta
communication formats.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity bit: even, odd, or none
Multiprocessor bit: 1 or 0
Receive error detection: parity, overrun, and framing errors
Break detection: by reading the RxD level directly when a framing error occurs
Section 11 Serial Communication Interface
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b. Synchronous mode
Serial data communication is synchronized with a clock signal. The SCI can communicate with
other chips having a synchronous communication function. There is one serial data
communication format.
Data length: 8 bits
Receive error detection: overrun errors
• Full-duplex communication
The transmitting and receivin g sections are in d epend ent, so th e SCI can transmit and receive
simultaneously. The transmitting an d receiving sections are both double-buffered, so serial
data can be transmitted and received continuously.
• Built-in baud rate generator with selectable bit rates
• Selectable transmit/receive clock so urces: internal clock from baud rate generator, or external
clock from the SCK pin.
• Four types of interrupts
Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested
independently.
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11.1.2 Block Diagram
Figure 11.1 shows a block diagram of the SCI.
RxD
TxD
SCK
RDR
RSR
TDR
TSR
SSR
SCR
SMR
BRR
Module data bus
Bus interface
Internal
data bus
Transmit/
receive control
Baud rate
generator
φ
φ/4
φ/16
φ/64
Clock
Parity generation
Parity check
TEI
TXI
RXI
ERI
Legend:
External clock
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Figure 11.1 SCI Block Diagram
Section 11 Serial Communication Interface
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11.1 .3 Input/Out put Pins
The SCI has the serial pins for each channel as listed in table 11.1.
Table 11.1 SCI Pins
Channel Name Abbreviation I/O Function
0 Serial cloc k pin SCK0Input/output SCI0 clock input/output
Receive data pin RxD0Input SCI0 receive data input
Transmit data pin TxD0Output SCI0 transmit data output
1 Serial cloc k pin SCK1Input/output SCI1 clock input/output
Receive data pin RxD1Input SCI1 receive data input
Transmit data pin TxD1Output SCI1 transmit data output
Section 11 Serial Communication Interface
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11.1.4 Register Configuration
The SCI has the internal registers as listed in table 11.2. These registers select asynchronous or
synchronous mode, specify the data format and bit rate, and control the transmitter and receiver
sections.
Table 11.2 Registers
Channel Address*1Name Abbreviation R/W Initial Value
0 H'FFB0 Serial mode register SMR R/W H'00
H'FFB1 Bit rate register BRR R/W H'FF
H'FFB2 Serial control register SCR R/W H'00
H'FFB3 Transmit data register TDR R/W H'FF
H'FFB4 Serial status register SSR R /(W)*2H'84
H'FFB5 Receive data register RDR R H ' 00
1 H'FFB8 Serial mode register SMR R/W H'00
H'FFB9 Bit rate register BRR R/W H'FF
H'FFBA Serial control register SCR R/W H'00
H'FFBB Transmit data register TDR R/W H'FF
H'FFBC Serial status register SSR R/(W)*2H'84
H'FFBD Receive data register RDR R H' 00
Notes: 1. Lower 16 bits of the address.
2. Only 0 can be written to clear flags.
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11.2 Register Descriptions
11.2.1 Receive Shift Register (RSR)
RSR is an 8-bit register that receives serial data.
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first,
thereby converting the data to parallel data. When 1 byte has been received, it is automatically
transferred to RDR. The CPU cannot read or write RSR directly.
11.2.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received serial data.
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into
RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to
be received continuously.
RDR is a read-o nly register. Its conten ts cannot be modified by the CPU. RDR is in itialized to
H'00 by a reset and in standby mode.
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11.2.3 Transmit Shift Register (TSR)
TSR is an 8-bit r e gister used to transmit serial data.
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
The SCI loads tr ansmit data from TDR in to TSR, then transm its the data serially from the TxD
pin, LSB (bit 0) first. After transmittin g one data byte, the SCI au tomatically loads the n ext
transmit data from TDR into TSR and starts transmittin g it. If the TDRE flag is set to 1 in SSR,
however, the SCI does not load the TDR conten ts into TSR. The CPU cannot read or write TSR
directly.
11.2.4 Transmit Data Register (TDR)
TDR is an 8-bit register that stores data for serial transmission.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
When the SCI detects that TSR is empty , it moves tran smit data written in TDR from TDR into
TSR and starts serial transmission. Continuous serial transmission is possible by writing the next
transmit da ta in TDR during serial transmission f rom TSR.
The CPU can always read an d write TDR. TDR is initialized to H'FF by a reset and in standby
mode.
Section 11 Serial Communication Interface
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11.2.5 Serial Mode Register (SMR)
SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock
source for the baud rate generator.
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Communication mode
Selects asynchronous or synchronous mode
Clock select 1/0
These bits select the
baud rate generatorÕs
clock source
Character length
Selects character length in asynchronous mode
Parity enable
Selects whether a parity bit is added
Parity mode
Selects even or odd parity
Stop bit length
Selects the stop bit length
Multiprocessor mode
Selects the multiprocessor
function
The CPU can always read an d write SMR. SMR is initialized to H'00 b y a reset and in standby
mode.
Bit 7—Communication Mode (C/A
AA
A): Selects whether the SCI operates in asynchronous or
synchronous mode.
Bit 7
C/A
AA
ADescription
0 Asynchronous mode (Initial value)
1 Synchronous mode
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Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data leng th in asynchronous mode. In
synchronous mode the data length is 8 bits regardless of the CHR setting.
Bit 6
CHR Description
0 8-bit data (Initial val ue)
1 7-bit data*
Note: *When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted.
Bit 5—Parity Enable (PE): In async hro nou s m ode, this bit enables or disables the addition of a
parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode
the parity bit is neither added nor check ed, regard less of the PE setting.
Bit 5
PE Description
0 Parity bit not added or checked (Initial value)
1 Parity bit added and checke d *
Note: *When PE is set to 1, an even or odd parity bit is added to transmit data ac cording to the
even or odd parity mode selected by the O/E bit, and the parity bit in receive data is
checked to see that it matches the even or odd mode selected by the O/E bit.
Bit 4—Parity Mode (O/E
EE
E): Selects even or odd parity. The O/E bit setting is valid in
asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit.
The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled
in asynchronous mode.
Bit 4
O/E
EE
EDescription
0 Even parity*1(Initial val ue)
1 Odd parity*2
Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even
number of 1s in the transmitted character and parity bit combined. Receive data must
have an even number of 1s in the received character and parity bit combined.
2. When odd parity is selected, the parity bit added to transmit data makes an odd number
of 1s in the transmitted character and parity bit combined. Receive data must have an
odd number of 1s in the received character and parity bit combined.
Bit 3—St op Bit Le ngth (STOP): Selects one or two stop bits in asynchronous mode. Th is setting
is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit
setting is ignored.
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Bit 3
STOP Description
0 One stop bit*1(Initi al value)
1 Two stop bits*2
Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character.
2. Two stop bi ts (with value 1) are added at the end of each transmitted character.
In receiving, only the first stop bit is checked, regardless of the STOP bit setting . If th e second
stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the
next incoming character.
Bit 2—Multiprocessor Mode (MP): Selects a multiprocessor format. Wh en a multiprocesso r
format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is
valid only in asynchronous mode. It is ignored in synchronous mode.
For fur ther information on th e multiprocessor comm unication function , see section 11.3.3,
Multiprocessor Comm unication.
Bit 2
MP Description
0 Multiprocessor function disabled (Initial value)
1 Multiprocessor format selected
Bits 1 and 0—Clock Select 1 and 0 (CKS1/0): Th ese bits select the clock source of the on-chip
baud rate generator. Four clock sources are available: φ, φ/4, φ/16, and φ/64.
For the relationship between the clock source, bit rate register setting, and baud rate, see section
11.2.8, Bit Rate Register (BRR).
Bit 1
CKS1 Bit 0
CKS0 Description
00φ clock se lect ed (Initial value)
01φ/4 clock selected
10φ/16 clock selected
11φ/64 clock selected
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11.2.6 Serial Control Register (SCR)
SCR enables the SCI transmitter and receiver, enables or disables serial clock output in
asynchro nou s mode, enables or disables interrupts, and selects th e transmit/receive clock source.
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Transmit interrupt enable
Enables or disables transmit-data-empty interrupts (TXI)
Clock enable 1/0
These bits select the
SCI clock source
Receive interrupt enable
Enables or disables receive-data-full interrupts (RXI) and
receive-error interrupts (ERI)
Transmit enable
Enables or disables the transmitter
Receive enable
Enables or disables the receiver
Multiprocessor interrupt enable
Enables or disables multiprocessor
interrupts
Transmit end interrupt enable
Enables or disables transmit-
end interrupts (TEI)
The CPU can always read an d write SCR. SCR is initialized to H'0 0 by a reset and in stan dby
mode.
Section 11 Serial Communication Interface
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Bit 7—Transmit Interrupt Enable (TIE): Enables or disables the transmit-d ata-empty interrupt
(TXI) requested when the TDRE flag in SSR is set to 1 due to transfer o f serial transmit data fro m
TDR to TSR.
Bit 7
TIE Description
0 Transmit-data-empty interrupt request (TXI) is disabled*(Initial val ue)
1 Transmit-data-empty interrupt request (TXI) is enabled
Note: *TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then
clearing it to 0; or by clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI)
requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to
RDR; also enables or disables the receive-error interrupt (ERI).
Bit 6
RIE Description
0 Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled*
(Initial value)
1 Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled
Note: *RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF,
FER, PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operation s.
Bit 5
TE Description
0 Transmitting disabled*1(Initial value)
1 Transmitting enabled*2
Notes: 1. The TDRE flag is fixed at 1 in SSR.
2. In the enabled state, serial transmitting starts when the TDRE flag in SSR is cleared to
0 after writing of transmit data into TDR. Select the transmit format in SMR before
setting the TE bit to 1.
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Bit 4—Receive Enable (RE): Enables or disables the start of SCI serial receiving operations.
Bit 4
RE Description
0 Receiving disabled*1(Initial value)
1 Receiving enabled*2
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These
flags retain their previous values.
2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous
mode, or serial clock input is detected in synchronous mode. Select the receive format
in SMR before setting the RE bit to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or d isables multiprocessor interrup ts.
The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR.
The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE Description
0 Multiprocessor interrupts are disabled (normal receive operation) (Initial value)
[Clearing cond iti ons ]
• The MPIE bit is cleared to 0
• MPB = 1 in received data
1 Multiprocessor interrupts are enabled*
Receive-data-f ull interrupts (RXI), rece iv e-error int errupt s (ERI), and sett ing of the
RDRF, FER, and ORER status flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note: *The SCI does not transfer receive data from RSR to RDR, does not detect receive
errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives
data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the
MPIE bit to 0, and enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR) and
setting of the FER and ORER flags.
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Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain new transmit d ata when the MSB is transmitted .
Bit 2
TEIE Description
0 Transmit-end interrupt requests (TEI) are disabled*(Initial val ue)
1 Transmit-end interrupt requests (TEI) are enabled*
Note: *TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in
SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by
clearing the TEIE bit to 0.
Bits 1 and 0—Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0,
the SCK pin can be used for generic input/output, serial clock output, or serial clock input.
The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally
clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external
clock source is selected (CKE1 = 1). After setting the CKE1 and CKE0 bits, select the SCI
operating mode in SMR. For further details on selection of the SCI clock source, see table 11.9.
Bit 1
CKE1 Bit 0
CKE0 Description
0 0 Asynchronous mode Internal clock, SCK pin avail abl e for generic
input/output*1
Synchronous mode Internal clock, SCK pin used for serial clock output*1
0 1 Asynchronous mode Internal clock, SCK pin used for clock output*2
Synchronous mode Internal clock, SCK pin used for serial clock output
1 0 Asynchronous mode External clock, SCK pin used for clock input*3
Synchronous mode External clock, SCK pin used for serial clock input
1 1 Asynchronous mode External clock, SCK pin used for clock input*3
Synchronous mode External clock, SCK pin used for serial clock input
Notes: 1. Initial val ue
2. The output clock frequency is the same as the bit rate.
3. The input clock frequency is 16 time s the bit rate.
Section 11 Serial Communication Interface
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11.2.7 Serial Status Register (SSR)
SSR is an 8-bit register containin g multiprocessor bit values, and status flag s that indicate the SCI
operating status.
Bit
Initial value
Read/Write
Note: * Only 0 can be written to clear the flag.
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Transmit data register empty
Status flag indicating that transmit data has been transferred from TDR into
TSR and new data can be written in TDR
Multiprocessor
bit transfer
Value of multi-
processor bit to
be transmitted
Receive data register full
Status flag indicating that data has been received and stored in RDR
Overrun error
Status flag indicating detection of a receive overrun error
Framing error
Status flag indicating detection of a receive
framing error
Parity error
Status flag indicating detection of
a receive parity error
Transmit end
Status flag indicating end of
transmission
*****
Multiprocessor bit
Stores the received
multiprocessor bit value
The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER,
and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The
TEND and MPB flags are read-only bits that cannot be written.
Section 11 Serial Communication Interface
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SSR is initialized to H'84 by a reset and in standby mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data
from TDR in to TSR and the next ser ial tr ansmit data can be written in TDR.
Bit 7
TDRE Description
0 TDR contains valid transmit data
[Clearing cond iti on]
Software reads TDRE while it is set to 1, then writes 0
1 TDR does not contain valid transmit data (Initial value)
[Setting conditions]
• The chip is reset or enters standby mode
• The TE bit in SCR is cleared to 0
• TDR contents are loaded into TSR, so new data can be written in TDR
Bit 6—Receive Data Register Full (RDRF): Indicates that RDR contains new receive data.
Bit 6
RDRF Description
0 RDR does not contain new receive data (Initi al value)
[Clearing cond iti ons ]
• The chip is reset or enters standby mode
• Software reads RDRF while it is set to 1, then writes 0
• The DMAC reads data from RDR
1 RDR con t ains ne w receive dat a
[Setting condition]
When serial data is received normally and transferred from RSR to RDR
Note: The RDR contents and RDRF fl ag are not affected by detection of receive errors or by
clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still
set to 1 when reception of the next data ends, an overrun error occurs and receive data is
lost.
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Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5
ORER Description
0 Receiving is in progress or has ended normally (Initial value)*1
[Clearing cond iti ons ]
• The chip is reset or enters standby mode
• Software reads ORER while it is set to 1, then writes 0
1 A receive overrun error occurred*2
[Setting condition]
Reception of the next serial data ends when RDRF = 1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its
previous value.
2. RDR continues to hold the receive data before the overrun error, so subsequent receive
data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 4—Framing Error (FER): Indicates that data reception ended abnormally due to a framing
error in asynchronous mode.
Bit 4
FER Description
0 Receiving is in progress or has ended normally (Initial value)*1
[Clearing cond iti ons ]
• The chip is reset or enters standby mode
• Software reads FER while it is set to 1, then writes 0
1 A receive framing error occurred*2
[Setting condition]
The stop bit at the end of receive data is checked and found to be 0
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous
value.
2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not
checked. When a framing error occurs the SCI transfers the receive data into RDR but
does not set the RDRF flag. Serial receiving cannot continue whil e the FER flag is set
to 1. In synchronous mode, serial transmitting is also disabled.
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Bit 3—Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER Description
0 Receiving is in progress or has ended normally*1 (Initial value)
[Clearing cond iti on]
The chip is reset or enters standby mode. Software reads PER while it is set to 1, then
writes 0
1 A receive parity error occurred*2
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the even or
odd parity setting of O/E in SMR
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
value.
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Bit 2—Transmit End (T EN D ): Indicates that when the last bit of a serial character was
transmitted TDR d id not contain ne w tr ansm it data, so transmission has end ed. The TEND flag is
a read-only bit and cannot be written.
Bit 2
TEND Description
0 Transmiss ion is in progre ss
[Clearing cond iti on]
Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag
1 End of transmission (Initial value)
[Setting conditions]
• The chip is reset or enters standby mode. The TE bit is cleared to 0 in SCR
• TDRE is 1 when the last bit of a serial character is transmitted
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Bit 1—Multiprocessor Bit (MPB): Stores the value of th e multiprocessor bit in receive data
when a multip rocesso r f ormat is used in asynchro nou s mode. MPB is a read-only bit and cannot
be written.
Bit 1
MPB Description
0 Multiprocessor bit value in receive data is 0*(Initial value)
1 Multiprocessor bit value in receive data is 1
Note: *If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its
previous value.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocesso r format is selected for transmitting in asy nchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting .
Bit 0
MPBT Description
0 Multiprocessor bit value in transmit data is 0 (Initial value)
1 Multiprocessor bit value in transmit data is 1
11.2.8 Bit Rate Regist er (BRR)
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud
rate generator clock source, determines the serial communication bit rate.
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
The CPU can always r ead and write BRR. BRR is initialized to H'FF by a r e set and in stand by
mode.
The baud rate generator is controlled separately for the individual channels, so diff erent values
may be set for each.
Table 11.3 shows ex amples of BRR settings in asynchronous mode. Table 11.4 shows exam ples of
BRR settings in synchronous mode.
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Table 11.3 Exa mples of Bit Rate s and BRR Settings in Asynchronous Mode
φ
φφ
φ (MHz)
2 2.097152 2.4576 3
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0 0 155 0.16
1200 0 51 0.16 0 54 –0.70 0 63 0 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0 0 38 0.16
4800 0 12 0.16 0 13 –2.48 0 15 0 0 19 –2.34
9600 0 6 –6.99 0 6 –2.48 0 7 0 0 9 –2.34
19200 0 2 8.51 0 2 13.78 0 3 0 0 4 –2.34
31250 0 1 0 0 1 4.86 0 1 22.88 0 2 0
38400 0 1 –18.62 0 1 –14.67 0 1 0 —— —
φ
φφ
φ (MHz)
3.6864 4 4.9152 5
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 191 0 1 207 0.16 1 255 0 2 64 0.16
300 1 95 0 1 103 0.16 1 127 0 1 129 0.16
600 0 191 0 0 207 0.16 0 255 0 1 64 0.16
1200 0 95 0 0 103 0.16 0 127 0 0 129 0.16
2400 0 47 0 0 51 0.16 0 63 0 0 64 0.16
4800 0 23 0 0 25 0.16 0 31 0 0 32 –1.36
9600 0 11 0 0 12 0.16 0 15 0 0 15 1.73
19200 0 5 0 0 6 –6.99 0 7 0 0 7 1.73
31250 —— — 03 0 0 4 –1.70 0 4 0
38400 0 2 0 0 2 8.51 0 3 0 0 3 1.73
Section 11 Serial Communication Interface
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φ
φφ
φ (MHz)
6 6.144 7.3728 8
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03
150 1 77 0.16 2 79 0 2 95 0 2 103 0.16
300 1 155 0.16 1 159 0 1 191 0 1 207 0.16
600 1 77 0.16 1 79 0 1 95 0 1 103 0.16
1200 0 155 0.16 0 159 0 0 191 0 0 207 0.16
2400 0 77 0.16 0 79 0 0 95 0 0 103 0.16
4800 0 38 0.16 0 39 0 0 47 0 0 51 0.16
9600 0 19 –2.34 0 19 0 0 23 0 0 25 0.16
19200 0 9 –2.34 0 9 0 0 11 0 0 12 0.16
31250 0 5 0 0 5 2.40 0 6 5.33 0 7 0
38400 0 4 –2.34 0 4 0 0 5 0 0 6 –6.99
φ
φφ
φ (MHz)
9.8304 10 12 12.288
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08
150 2 127 0 2 129 0.16 2 155 0.16 2 159 0
300 1 255 0 2 64 0.16 2 77 0.16 2 79 0
600 1 127 0 1 129 0.16 1 155 0.16 1 159 0
1200 0 255 0 1 64 0.16 1 77 0.16 1 79 0
2400 0 127 0 0 129 0.16 0 155 0.16 0 159 0
4800 0 63 0 0 64 0.16 0 77 0.16 0 79 0
9600 0 31 0 0 32 –1.36 0 38 0.16 0 39 0
19200 0 15 0 0 15 1.73 0 19 –2.34 0 19 0
31250 0 9 –1.70 0 9 0 0 11 0 0 11 2.40
38400 0 7 0 0 7 1.73 0 9 –2.34 0 9 0
Section 11 Serial Communication Interface
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φ
φφ
φ (MHz)
14 14.7456 16 18
Bit Rate
(bits/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 248 –0.17 3 64 0.70 3 70 0.03 3 79 –0.12
150 2 181 0.16 2 191 0 2 207 0.16 2 233 0.16
300 2 90 0.16 2 95 0 2 103 0.16 2 116 0.16
600 1 181 0.16 1 191 0 1 207 0.16 1 233 0.16
1200 1 90 0.16 1 95 0 1 103 0.16 1 116 0.16
2400 0 181 0.16 0 191 0 0 207 0.16 0 233 0.16
4800 0 90 0.16 0 95 0 0 103 0.16 0 116 0.16
9600 0 45 –0.93 0 47 0 0 51 0.16 0 58 –0.69
19200 0 22 –0.93 0 23 0 0 25 0.16 0 28 1.02
31250 0 11 0 0 14 –1.70 0 15 0 0 17 0.00
38400 0 10 3.57 0 11 0 0 12 0.16 0 14 –2.34
Section 11 Serial Communication Interface
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Table 11. 4 Examples of Bit Rat e s and BRR Sett ings in Synchro nous Mode
φ
φφ
φ (MHz)
2 4 8 10 16 18
Bit Rate
(bits/s)nNnNnNnNnNnN
110 3 70 ——————————
250 2 124 2 249 3 124 ——3 249 ——
500 1 249 2 124 2 249 ——3 124 3 140
1 k 1 124 1 249 2 124 ——2 249 3 69
2.5 k 0 199 1 99 1 199 1 249 2 99 2 112
5 k 0 99 0 199 1 99 1 124 1 199 1 224
10 k 0 49 0 99 0 199 0 249 1 99 1 112
25 k 0 19 0 39 0 79 0 99 0 159 0 179
50 k 0 9 0 19 0 39 0 49 0 79 0 89
100 k 0 4 0 9 0 19 0 24 0 39 0 44
250 k 0 1 0 30709015017
500 k 0 0*0103040708
1 M 0 0*01——0304
2 M 0 0*——01——
2.5 M ——00*————
4 M 0 0*——
Legend:
Blank: No setting available
—: Setting possible, but error occurs
*: Continuous transmission/reception not possible
Note: Settings with an error of 1% or less are recommended.
Section 11 Serial Communication Interface
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The BRR setting is calculated as follows:
Asynchronous mode:
N = φ
64 × 22n–1 × B × 106 – 1
Synchronous mode:
N = φ
8 × 22n–1 × B × 106 – 1
B: Bit rate (bits/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: System clo ck frequ ency (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3)
(For the clock sources and values of n, see the following table.)
SMR Settings
n Clock Source CKS1 CKS0
0φ00
1φ/4 0 1
2φ/16 1 0
3φ/64 1 1
The bit rate error in asynchronous mode is calculated as follows.
Error (%) = { φ ×106
(N + 1) × B × 64 × 22n–1 – 1} × 100
Section 11 Serial Communication Interface
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Table 11.5 indicates the maximu m bit rates in asynchronous mode for various system clock
frequencies. Tables 11.6 and 11.7 indicate the maximum bit rates with external clock input.
Table 11. 5 Maximum Bit Rate s for Various F requencies (Asynchro nous Mode)
Settings
φ
φφ
φ (MHz) Maximum Bit Rate (bits/s) n N
2 62500 0 0
2.097152 65536 0 0
2.4576 76800 0 0
3 93750 0 0
3.6864 115200 0 0
4 125000 0 0
4.9152 153600 0 0
5 156250 0 0
6 187500 0 0
6.144 192000 0 0
7.3728 230400 0 0
8 250000 0 0
9.8304 307200 0 0
10 312500 0 0
12 375000 0 0
12.288 384000 0 0
14 437500 0 0
14.7456 460800 0 0
16 500000 0 0
17.2032 537600 0 0
18 562500 0 0
Section 11 Serial Communication Interface
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Table 11. 6 Maxi mum Bit Rate s with External Clo ck Input (Asynchronous Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.5000 31250
2.097152 0.5243 32768
2.4576 0.6144 38400
3 0.7500 46875
3.6864 0.9216 57600
4 1.0000 62500
4.9152 1.2288 76800
5 1.2500 78125
6 1.5000 93750
6.144 1.5360 96000
7.3728 1.8432 115200
8 2.0000 125000
9.8304 2.4576 153600
10 2.5000 156250
12 3.0000 187500
12.288 3.0720 192000
14 3.5000 218750
14.7456 3.6864 230400
16 4.0000 250000
17.2032 4.3008 268800
18 4.5000 281250
Section 11 Serial Communication Interface
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Table 11.7 Maximum Bit Rat es with External Clo c k Input (Synchro nous Mode)
φ
φφ
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s)
2 0.3333 333333.3
4 0.6667 666666.7
6 1.0000 1000000.0
8 1.3333 1333333.3
10 1.6667 1666666.7
12 2.0000 2000000.0
14 2.3333 2333333.3
16 2.6667 2666666.7
18 3.0000 3000000.0
Section 11 Serial Communication Interface
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11.3 Operation
11.3.1 Overview
The SCI has an asynchronous mode in which characters are synchronized individually, and a
synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous or synchronous mode and the
communication format are selected in SMR, as shown in table 11.8. The SCI clock source is
selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 11.9.
Asynchronous Mode:
• Data length is selectable: 7 or 8 bits.
• Parity and multiprocessor bits ar e selectable, and so is the stop bit length (1 or 2 bits). Th ese
selections determine the communication format and character length.
• In receiving, it is possible to detect framing errors, parity errors, overrun erro rs, and the break
state.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and can output a serial clock signal with a frequency matching the bit rate.
When an external clock is selected, the external clock input must have a frequency
16 times the bit rate. (The on-chip baud rate generator is not used.)
Synchronous Mode:
• The communication format has a fixed 8-bit data length.
• In receiving, it is possible to detect overrun errors.
• An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
and outputs a serial clock signal to external devices.
When an external clock is selected, the SCI operates on the input serial clock. The on-chip
baud rate generator is not used.
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 359 of 682
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Table 11.8 SMR Settings and Serial Communication Formats
SMR Settings SCI Communication Format
Bit 7
C/A
AA
ABit 6
CHR Bit 2
MP Bit 5
PE Bit 3
STOP Mode Data
Length
Multi-
processor
Bit Parity
Bit
Stop
Bit
Length
00000 8-bit dataAbsentAbsent1 bit
00001
Asynchronous
mode 2 bits
00010 Present1 bit
00011 2 bits
01000 7-bit data Absent1 bit
01001 2 bits
01010 Present1 bit
01011 2 bits
001—0 8-bit data Present Absent 1 bit
001—12 bits
011—0 7-bit data 1 bit
011— 1
Asynchronous
mode (multi-
processor
format) 2 bits
1———— Synchronous
mode 8-bit data Absent None
Table 11.9 SMR and SCR Settings and S CI Clock Source Selection
SMR SCR Settings
SCI Communication Format
Bit 7
C/A
AA
ABit 1
CKE1 Bit 0
CKE0 Mode Clock Source SCK Pin Function
0 0 0 SCI does not use the SCK pin
00 1
Internal
Outputs a clock with frequency
matching the bit rate
01 0
01 1
Asynchronous
mode
External Inputs a clock with frequency
16 times the bit rate
10 0
10 1
Internal Outputs the serial clock
11 0
11 1
Synchronous
mode
External Inputs the serial clock
Section 11 Serial Communication Interface
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11.3.2 Operation in Asynchronous Mode
In asynchronous mode each transmitted or receiv ed character begins with a start bit and ends with
a stop bit. Serial communication is synchronized one ch aracter at a time.
The transmitting and receiving sections of the SCI are independent, so full-duplex communication
is possible. The transmitter and receiver are both double buffered, so data can be written and read
while transmitting and receiving are in progress, enabling continuous transmitting and receiving.
Figure 11.2 shows the general format of asynchronous serial communication. In asynchronous
serial communication the communication line is normally held in the mark (high) state. The SCI
monitors the line and starts serial communication when the line goes to the space (low) state,
indicating a start bit. One serial character consists of a start bit (low), data (LSB fir st), parity bit
(high or low), and stop bit (high), in that order.
When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit.
The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate.
Receive data is latched at the center of each bit.
Serial data 0 1 1
1Idle (mark) state
1
D0 D1 D2 D3 D4 D5 D6 D7 0/1
(LSB) (MSB)
Start
bit Transmit or receive data P arity
bit Stop
bit
One unit of data (character or frame)
1 bit 7 bits or 8 bits 1 bit or
no bit 1 bit or
2 bits
Figure 11.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with
Parity and 2 Stop Bits)
Section 11 Serial Communication Interface
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Communication Formats
Table 11.10 shows the 12 communication formats that can be selected in asynchronous mode. The
format is selected by settings in SMR.
Table 11.10 Serial Communication Formats (Asynchronous Mode)
123456789101112
8-bit data
STOP
8-bit data
8-bit data
8-bit data
7-bit data
7-bit data
7-bit data
7-bit data
8 bit data
8 bit data
7-bit data
7-bit data
S
S
S
S
S
S
S
S
S
S
S
S
STOP
STOP
P
STOP
P
STOP
STOP
STOP STOP
STOP
STOP STOP
STOP
P
P
MPB
STOP STOP
STOP
MPB
MPB
MPB
STOP STOP
Legend:
S:
STOP:
P:
MPB:
Start bit
Stop bit
Parity bit
Multiprocessor bit
CHR PE MP STOP
SMR Settings
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
—
—
—
—
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Serial Communication Format and Frame Length
STOP
Section 11 Serial Communication Interface
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Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A
bit in SMR and bits CKE1 and CKE0 in SCR. See table 11.9.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The
frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 11.3 so that
the rising edge of the clock occurs at the center of each transmit data bit.
0 D0D1D2D3D4D5D6D70/1 1 1
1 frame
Figure 11.3 Phase Relationship between Output Clock and Serial Data
(Asynchrono us Mo de)
Transmitting and Receiving Data
SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following th e pro c edur e given below. Clear ing TE to 0 sets the TDRE flag to 1 and initializes
TSR. Clearing RE to 0 , however, does not initialize the RDRF, PER, FER, and ORER flags and
RDR, which retain their previous con ten ts.
When an exter nal clock is used, the clock should not be stopped during initialization or subsequent
operation. SCI operation becomes unreliable if the clock is stopped.
Figure 11.4 shows a sample flowchart for initializing the SCI.
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 363 of 682
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Clear TE and RE bits
to 0 in SCR
Transmitting or receiving
No
Yes
1.
2.
3.
4.
Select the communication format in SMR.
Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
Select communication
format in SMR
1
Set value in BRR
2
3
Set TE or RE bit to 1 in SCR
Set RIE, TIE, TEIE, and
MPIE bits as necessary 4
1 bit interval
elapsed?
Wait
Wait for at least the interval required to transmit or receive
1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE,
TIE, TEIE, and MPIE bits as necessary. Setting the TE
or RE bit enables the SCI to use the TxD or RxD pin.
Start of initialization
Set CKE1 and CKE0 bits
in SCR (leaving TE and
RE bits cleared to 0)
Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0. If clock output is selected in
asynchronous mode, clock output starts immediately after
the setting is made in SCR.
Figure 11.4 Sample Flowchart for SCI Initialization
Section 11 Serial Communication Interface
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Transmitt ing Serial Data (Asynchrono us Mode): Figure 11.5 shows a sample flowchart for
transmitting ser ial data and indicates the procedure to follow.
Start transmitting
Read TDRE flag in SSR
TDRE = 1?
Write transmit data
in TDR and clear TDRE
flag to 0 in SSR
All data
transmitted?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit data
in TDR and clear the TDRE flag to 0.
Read TEND flag in SSR
TEND = 1? No
Yes
Output break
signal? No
Yes
Clear TE bit to 0 in SCR
4
1.
2.
3.
4.
Clear DR bit to 0,
set DDR bit to 1
Initialize
To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE
flag to 0.
To output a break signal at the end of serial transmission:
set the DDR bit to 1 and clear the DR bit to 0
(DDR and DR are I/O port registers), then clear the
TE bit to 0 in SCR.
Figure 11.5 Sample Flowchart for Transmitting Serial Data
Section 11 Serial Communication Interface
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In transm itting serial data, th e SCI o perates as follo ws.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data fro m TDR into TSR, the SCI sets the TDRE f lag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requ ests a transmit-data-empty in ter rupt
(TXI) at this tim e.
Serial transmit da ta is tr ansmitted in the f ollowing order from the TxD pin:
Start bit: One 0 bit is output.
Transmit data: 7 or 8 bits are output, LSB first.
Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one m ultiprocessor
bit is output. Formats in which neither a parity bit nor
a multipro cessor bit is output can also be selected.
Stop bit: One or two 1 bits (stop bits) are output.
Mark state: Output of 1 continues until the start bit of the next
transmit da ta.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next fram e . If th e TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs th e stop bit,
then continues output of 1 in the mark state. If the TEIE bit is set to 1 in SCR, a tran smit-end
interrupt ( TEI) is requested at this time.
Figure 11.6 shows an ex ample of SCI transmit operation in asynchronous mode.
1Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit 1
Idle (mark)
state
TDRE
TEND
TXI
interrupt
request
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
interrupt
request
1 frame
TEI interrupt request
Figure 11.6 Example of SCI Transmit Operation in Asynchronous Mode
(8-Bit Data with Parity and 1 Stop Bit)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 366 of 682
REJ09B0353-0300
Receiving Serial Data (Asynchronous Mode): Figure 11.7 shows a sample flowchart for
receiving serial data and indicates the procedure to follow.
Start receiving
Read RDRF flag in SSR
RDRF = 1?
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
PER FER
ORER = 1?
Clear RE bit to 0 in SCR
Finished
receiving?
End
Error handling
(continued on next page)
1
4
No
Yes
Yes
No
No
Yes
1.
2., 3.
4.
5.
SCI initialization: the receive data function of
the RxD pin is selected automatically.
Receive error handling and break
detection: if a receive error occurs, read the
ORER, PER, and FER flags in SSR to identify
the error. After executing the necessary error
handling, clear the ORER, PER, and FER
flags all to 0. Receiving cannot resume if any
of the ORER, PER, and FER flags remains
set to 1. When a framing error occurs, the
RxD pin can be read to detect the break state.
SCI status check and receive data read: read
SSR, check that RDRF is set to 1, then read
receive data from RDR and clear the RDRF
flag to 0. Notification that the RDRF flag has
changed from 0 to 1 can also be given by the
RXI interrupt.
To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the stop bit of the current
frame is received.
Read ORER, PER,
and FER flags in SSR 2
5
Initialize
∨∨ 3
Figure 11.7 Sample Flowchart for Receiving Serial Data (1)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 367 of 682
REJ09B0353-0300
No
No
No
No
Yes
Yes
Yes
Yes
Framing error handling
PER = 1?
ORER = 1?
Overrun error handling
FER = 1?
Break?
Error handling
Parity error handling
Clear ORER, PER, and
FER flags to 0 in SSR
Clear RE bit to 0 in SCR
End
3
Figure 11.7 Sample Flowchart for Receiving Serial Data (2)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 368 of 682
REJ09B0353-0300
In receiving, the SCI operates as follows.
• The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes
internally and starts receiving.
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
After receiving data, the SCI makes the following checks:
Parity check: The number of 1s in the receive data must match the even or odd parity
setting of the O/E bit in SMR.
Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop
bit is checked.
Status check: The RDRF flag must be 0 so that receive data can be transferred fr om
RSR into RDR.
If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error)*, the SCI operates as indicated in table 11.11.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
is not set to 1. Be sure to clear the error flag s.
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
(RXI) is requ e sted. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
Table 11.11 Receive Error Conditions
Receive Error Abbreviation Condition Data Transfer
Overrun error ORER Receiving of next data ends
while RDRF flag is still set to 1
in SSR
Receive data not tran sferre d
from RSR to RDR
Framing error FER Stop bit is 0 Receive data transferred
from RSR to RDR
Parity error PER Parity of receive data differs
from even/odd parity setting in
SMR
Receive data transferre d
from RSR to RDR
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 369 of 682
REJ09B0353-0300
Figure 11.8 shows an example of SCI receive operation in asynchronous mode.
1Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit 1
Idle (mark)
state
RDRF
FER
RXI
request
1 frame Framing error,
ERI request
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
Figure 11.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
11.3.3 Multiprocessor Communication
The multipr ocessor communication function enables sev e ral processors to share a single serial
communication line. The processors communicate in asynchronous mode using a fo rmat with an
addition a l multiprocessor bit (multipro cessor format).
In multiprocessor communication , each receiving processor is ad d r essed by an ID. A serial
communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a
data-sending cycle. The multiprocessor bit distinguishes ID-sending cy cles from data-sending
cycles.
The transmitting p rocesso r starts b y sending the ID of the receiving processo r with which it wants
to communicate as d a ta with the multiprocessor bit set to 1. Next the transmitting pro cessor sends
transmit data with the multiprocessor bit cleared to 0.
Receiving pr ocessors skip incoming data until they receive data with the multiprocessor bit set to
1. When they receive data with the multiprocessor bit set to 1, receiving pro cesso rs compare the
data with their IDs. The receiving processor with a matching ID continues to receive further
incoming data. Processors with IDs not matching the received data skip further incoming data
until they ag ain receive data with the multiprocessor bit set to 1. Multiple processors can send and
receive data in this way.
Figure 11.9 shows an example of communication among different processors using a
multiprocessor form at.
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 370 of 682
REJ09B0353-0300
Communication Formats
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is
selected. For details see table 11.11.
Clock
See the description of asynchronous mode.
Transmitting
processor
Receiving
processor A
Serial communication line
Receiving
processor B Receiving
processor C Receiving
processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial data H'01 H'AA
(MPB = 1) (MPB = 0)
ID-sending cycle: receiving
processor address Data-sending cycle:
data sent to receiving
processor specified by ID
Legend:
MPB: Multiprocessor bit
Figure 11.9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 371 of 682
REJ09B0353-0300
Transmitting and Receiving Data
Transmitting Multiprocessor Serial Data: Figure 11.10 shows a sample flowchart for
transmitting multiprocessor serial data and ind icates the procedure to follow.
No
No
No
No
Yes
Yes
Yes
Yes
Initialize
Start transmitting
Read TDRE flag in SSR
TDRE = 1?
Write transmit data in
TDR and set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Read TEND flag in SSR
TEND = 1?
1
2
3
4
1.
2.
3.
4.
SCI initialization: the transmit data
output function of the TxD pin is
selected automatically.
SCI status check and transmit data
write: read SSR, check that the TDRE
flag is 1, then write transmit
data in TDR. Also set the MPBT flag to
0 or 1 in SSR. Finally, clear the TDRE
flag to 0.
To continue transmitting serial data:
after checking that the TDRE flag is 1,
indicating that data can be written,
write data in TDR, then clear the TDRE
flag to 0.
To output a break signal at the end of
serial transmission: set the DDR bit to
1 and clear the DR bit to 0 (DDR and
DR are I/O port registers), then clear
the TE bit to 0 in SCR.
Output break signal?
Clear DR bit to 0, set DDR bit to 1
Clear TE bit to 0 in SCR
End
Figure 11.10 Sample Flowchart for Transmitting Multiprocessor Serial Data
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 372 of 682
REJ09B0353-0300
In transm itting serial data, th e SCI o perates as follo ws.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data fro m TDR into TSR, the SCI sets the TDRE f lag to 1 and starts
transmitting. If the TIE bit in SCR is set to 1, the SCI re quests a transm it-data-emp ty interrupt
(TXI) at this tim e.
Serial transmit da ta is tr ansmitted in the f ollowing order from the TxD pin:
Start bit: One 0 b it is output.
Transmit data: 7 or 8 bits are output, LSB f ir st.
Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
Stop bit: One or two 1 bits (stop bits) are output.
Mark state: Output of 1 bits con tinue s until the start bit of the next transmit data.
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next
frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop bit, then
continue s output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a tr ansmit-end
interrup t ( TEI) is r equested at this time.
Figure 11.11 shows an example of SCI transmit o peration using a mu ltiprocessor for m at.
1Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data
Multi-
processor
bit
Start
bit
0D0 D1 D7 0/1
Stop
bit
1
Data 1
Idle (mark)
state
TDRE
TEND
TXI
request TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
TXI
request
1 frame
TEI request
Serial
data
Multi-
processor
bit
Figure 11.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 373 of 682
REJ09B0353-0300
Receiving Multiprocessor Serial Data: Figure 11.12 shows a sample flowchart for receiving
multipro cessor serial data and indicates the procedure to follow.
Initialize
Start receiving
Read RDRF flag in SSR
RDRF = 1?
Read receive data from RDR
Read ORER and FER flags in SSR
FER ∨ ORER = 1 ?
Read RDRF flag in SSR
Read receive data from RDR
RDRF = 1?
Finished receiving?
Clear RE bit to 0 in SCR
Error handling
(continued on next page)
End
1
2
4
5
1.
2.
3.
4.
5.
SCI initialization: the receive data function
of the RxD pin is selected automatically.
ID receive cycle: set the MPIE bit to 1 in SCR.
SCI status check and ID check: read SSR,
check that the RDRF flag is set to 1, then read
data from RDR and compare with the
processor's own ID. If the ID does not match,
set the MPIE bit to 1 again and clear the
RDRF flag to 0. If the ID matches, clear the
RDRF flag to 0.
SCI status check and data receiving: read
SSR, check that the RDRF flag is set to 1,
then read data from RDR.
Receive error handling and break detection:
if a receive error occurs, read the
ORER and FER flags in SSR to identify the error.
After executing the necessary error handling,
clear the ORER and FER flags both to 0.
Receiving cannot resume while either the ORER
or FER flag remains set to 1. When a framing
error occurs, the RxD pin can be read to detect
the break state.
Yes
Yes
Yes
No
Yes
Yes
No
No
No
3
Set MPIE bit to 1 in SCR
Read ORER and FER flags in SSR
Yes
FER ∨ ORER = 1 ?
Own ID?
No
No
Figure 11.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 374 of 682
REJ09B0353-0300
No
No
Yes
No
Yes
Yes
Error handling
ORER = 1?
Overrun error handling
FER = 1?
Break?
Framing error handling
Clear ORER and FER
flags to 0 in SSR
Clear RE bit to 0 in SCR
End
5
Figure 11.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 375 of 682
REJ09B0353-0300
Figure 11.13 shows an example of SCI receive operation using a multiprocesso r format.
1Start
bit
0D0 D1 D7 1
Stop
bit
1
Data (ID1) MPB Start
bit
0D0 D1 D7 0
Stop
bit
1
Data (data1) MPB 1
Idle (mark)
state
MPIE
RDRF
RDR value ID1
RXI request
(multiprocessor
interrupt), MPIE = 0
RXI handler reads
RDR data and clears
RDRF flag to 0
Not own ID, so
MPIE bit is set
to 1 again
No RXI request,
RDR not updated
a. Own ID does not match data
1Start
bit
0D0 D1 D7 1
Stop
bit
1
Data (ID2) MPB Start
bit
0D0 D1 D7 0
Stop
bit
1
Data (data2) MPB 1
Idle (mark)
state
MPIE
RDRF
RDR value ID2
RXI request
(multiprocessor
interrupt), MPIE = 0
RXI interrupt handler
reads RDR data and
clears RDRF flag to 0
Own ID, so receiving
continues, with data
received by RXI
interrupt handler
MPIE bit is set
to 1 again
b. Own ID matches data
ID1 Data 2
Figure 11.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and
One Stop Bit)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 376 of 682
REJ09B0353-0300
11.3.4 Synchronous Operation
In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses.
This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clo ck but are otherwise indep e nden t, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmittin g or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 11.14 shows the general format in synchronous serial communication.
Serial clock
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
LSB MSB
Don't care Don't care
One unit (character or frame) of serial data
Transfer direction
* *
Note: * High except in continuous transmitting or receiving
Figure 11.14 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is placed on the co mmunication line from one
falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After
output of the MSB, the communication line remains in the state of the MSB. In synchronous mode
the SCI receives data by synchronizing with the rise of the serial clock.
Communication Format
The data length is fixe d at 8 bits. No parity bit or multip rocessor bit can be added.
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected by clearing or setting the CKE1 and CKE0 bits in SCR and the C/A bit in
SMR. See table 11.9. When the SCI operates on an internal clock, it outputs the clock signal at the
SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains in th e high state.
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 377 of 682
REJ09B0353-0300
Transmitting and Receiving Data
SCI Initializa tion (Synchro nous Mode): Before transmitting or receiving, clear the TE and RE
bits to 0 in SCR, then initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 an d
initializes TSR. Clearin g the RE bit to 0, howev e r , doe s not initialize the RDRF, PER, FER, and
ORE flags and RDR, which retain their previous contents.
Figure 11.15 shows a sample flowchart for initializin g the SCI.
Clear TE and RE
bits to 0 in SCR
1 bit interval
elapsed?
Start transmitting or receiving
No
Yes
1.
2.
3.
4.
Select the clock source in SCR. Clear the RIE, TIE, TEIE,
MPIE, TE, and RE bits to 0.
Select the communication format in SMR.
Write the value corresponding to the bit rate in BRR.
This step is not necessary when an external clock is used.
Note: In simultaneous transmitting and receiving, the TE and RE
bits should be cleared to 0 or set to 1 simultaneously.
1
2
Set CKE1 and CKE0 bits in
SCR (leaving TE and RE
bits cleared to 0)
3
Set TE or RE to 1 in SCR
Set RIE, TIE, and TEIE
bits as necessary 4
Wait
Wait for at least the interval required to transmit or receive
one bit, then set the TE or RE bit to 1 in SCR. Also set
the RIE, TIE, and TEIE bits as necessary.
Setting the TE or RE bit enables the SCI to use the
TxD or RxD pin.
Start of initialization
Set value in BRR
Select communication
format in SMR
Figure 11.15 Sample Flowchart for SCI Initialization
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 378 of 682
REJ09B0353-0300
Transmitt ing Serial Data (Synchronous Mode): Figure 11.16 shows a sample flowchart for
transmitting ser ial data and indicates the procedure to follow.
Start transmitting
Read TDRE flag in SSR
TDRE = 1?
Write transmit data in
TDR and clear TDRE flag
to 0 in SSR
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read SSR,
check that the TDRE flag is 1, then write transmit
data in TDR and clear the TDRE flag to 0.
Read TEND flag in SSR
No
Yes
1.
2.
3.
Initialize
Clear TE bit to 0 in SCR
To continue transmitting serial data: after checking
that the TDRE flag is 1, indicating that data can be
written, write data in TDR, then clear the TDRE flag
to 0.
All data
transmitted?
TEND = 1?
Figure 11.16 Sample Flowchart for Serial Transmitting
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 379 of 682
REJ09B0353-0300
In transm itting serial data, th e SCI o perates as follo ws.
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI
recognizes that TDR contains new data, and loads this data from TDR into TSR.
• After loading the data fro m TDR into TSR, the SCI sets the TDRE f lag to 1 and starts
transmitting. If the TIE bit is set to 1 in SCR, the SCI requ ests a transmit-data-empty in ter rupt
(TXI) at this tim e.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin in order from LSB (bit 0) to MSB (bit 7).
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI
loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE
flag is 1, the SCI sets the TEND flag to 1 in SSR, and af ter transmitting the MSB, ho lds the
TxD pin in the MSB state. If the TEIE bit in SCR is set to 1 , a transmit-end interrupt ( TEI) is
requested at this time.
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 11.17 shows an example of SCI transmit operation.
Transmit
direction
Serial clock
Serial data
TDRE
TEND
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
TXI
request
TXI
request TEI
request
1 frame
Figure 11.17 Example of SCI Transmit Operation
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 380 of 682
REJ09B0353-0300
Receiving Serial Data (Synchronous Mode): Figure 11.18 shows a sample flowchart for
receiving serial data and indicates the pr ocedure to follow. When switching from asynchronous
mode to synchronous mode, make sure that th e ORER, PER, and FER flags are cleared to 0. If the
FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will
be disabled.
Start receiving
Read RDRF flag in SSR
Read receive data
from RDR, and clear
RDRF flag to 0 in SSR
Read ORER flag in SSR
Clear RE bit to 0 in SCR
End
Error handling
(continued on next page)
1
4
5
No
Yes
Yes
No
Yes
3
1.
2., 3.
4.
5.
SCI initialization: the receive data function of
the RxD pin is selected automatically.
Receive error handling: if a receive error
occurs, read the ORER flag in SSR, then after
executing the necessary error handling, clear
the ORER flag to 0. Neither transmitting nor
receiving can resume while the ORER flag
remains set to 1.
SCI status check and receive data read: read
SSR, check that the RDRF flag is set to 1,
then read receive data from RDR and clear
the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be
given by the RXI interrupt.
To continue receiving serial data: check the
RDRF flag, read RDR, and clear the RDRF
flag to 0 before the MSB (bit 7) of the current
frame is received.
Initialize
No
RDRF = 1?
ORER = 1?
Finished
receiving?
2
Figure 11.18 Sample Flowchart for Serial Receiving (1)
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 381 of 682
REJ09B0353-0300
3
End
Error handling
Overrun error handling
Clear ORER flag to 0 in SSR
Figure 11.18 Sample Flowchart for Serial Receiving (2)
In receiving, the SCI operates as follows.
• The SCI synchronizes with serial clock input or output and initializes internally.
• Receive data is stored in RSR in order from LSB to MSB.
After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be
transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received
data is stored in RDR. If the check does not pass (receive error), the SCI operates as indicated
in table 11.11. If any receive error is detected, the subsequent data transmission/reception is
disabled.
• After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a receive-
data-full interrupt (RXI). If th e ORER f lag is set to 1 and the RIE bit in SCR is also set to 1 ,
the SCI requests a receive-error interrupt (ERI).
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 382 of 682
REJ09B0353-0300
Figure 11.19 shows an example of SCI receive operation.
Serial clock
Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI
request
Receive direction
RDRF
ORER
RXI interrupt handler
reads data in RDR and
clears RDRF flag to 0
RXI
request Overrun error,
ERI request
1 frame
Figure 11.19 Example of SCI Receive Operation
Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 11.20
shows a sample flowchart for transmittin g and receiving serial data simultaneously and indicates
the procedure to follow.
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 383 of 682
REJ09B0353-0300
No
Yes
No
Yes
Yes
No
Yes
No
Initialize
Start transmitting and receiving
Read TDRE flag in SSR
TDRE = 1?
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
RDRF = 1?
Read RDRF flag in SSR
Read receive data from RDR
and clear RDRF flag to 0 in SSR
Read ORER flag in SSR
ORER = 1?
End of transmitting and
receiving?
1
2
5
3
1.
2.
3.
4.
5.
SCI initialization: the transmit data
output function of the TxD pin and
receive data input function of the
RxD pin are selected, enabling
simultaneous transmitting and
receiving.
SCI status check and transmit
data write: read SSR, check that
the TDRE flag is 1, then write
transmit data in TDR and clear
the TDRE flag to 0.
Error handling
Note: When switching from transmitting or receiving to simultaneous
transmitting and receiving, clear the TE and RE bits both to 0,
then set the TE and RE bits both to 1.
Clear TE and RE bits to 0 in SCR
End
Notification that the TDRE flag has
changed from 0 to 1 can also be
given by the TXI interrupt.
Receive error handling: if a receive
error occurs, read the ORER flag in
SSR, then after executing the neces-
sary error handling, clear the ORER
flag to 0.
Neither transmitting nor receiving
can resume while the ORER flag
remains set to 1.
SCI status check and receive
data read: read SSR, check that
the RDRF flag is 1, then read
receive data from RDR and clear
the RDRF flag to 0. Notification
that the RDRF flag has changed
from 0 to 1 can also be given
by the RXI interrupt.
To continue transmitting and
receiving serial data: check the
RDRF flag, read RDR, and clear
the RDRF flag to 0 before the
MSB (bit 7) of the current frame
is received. Also check that
the TDRE flag is set to 1, indicat-
ing that data can be written, write
data in TDR, then clear the TDRE
flag to 0 before the MSB (bit 7) of
the current frame is transmitted.
4
Figure 11.20 Sample Flowchart for Serial Transmitting
Section 11 Serial Communication Interface
Rev.3.00 Mar. 26, 2007 Page 384 of 682
REJ09B0353-0300
11.4 SCI Interrupts
The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error
interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11.12
lists the interrupt sources and indicates their priority. These in terru pts can be enabled and disabled
by the TIE, RIE, and TEIE bits in SCR. Each inter r upt request is sent separately to the interrupt
controller.
The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. Th e TEI interrupt is
requested when the TEND flag is set to 1 in SSR.
The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI in ter rupt is
requested when the ORER, PER, or FER flag is set to 1 in SSR.
Table 11.12 SCI Interrupt Sources
Interrupt Description Priority
ERI Receive error (ORER, FER, or PER) High
RXI Receive data register full (RDRF)
TXI Transmit data register empty (TDRE)
TEI Transmit end (TEND) Low
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11.5 Usage Notes
Note the following points when using the SCI.
TDR Write and TDRE Flag
The TDRE flag in SSR is a statu s flag indicating the loading of transmit data f rom TDR into TSR.
The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR.
Data can be written in to TDR regardless of the state of the TDRE flag. If new data is written in
TDR when the TDRE flag is 0 , the old data stored in TDR will be lo st because this data ha s not
yet been transfer r ed to TSR. Before writing transmit data in TDR, be sur e to check that the TDRE
flag is set to 1.
Simultaneous Multiple Receive Errors
Table 11.13 indicates the state of SSR status flags when mu ltiple receive errors occur
simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so
receive data is lost.
Table 11.13 SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF ORER FER PER
Receive Data
Transfer
RSR →
→→
→ RDR Receive Errors
1100×Overrun error
0010 Framing error
0001 Parity error
1110×Overrun error + framing error
1101×Overrun error + parity error
0011 Framing error + parity error
1111×Overrun error + framing error + parity error
Notes: : Receiv e data is transferred from RSR to RDR.
×: Receive data is not transferred from RSR to RDR.
Section 11 Serial Communication Interface
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Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate,
so if the FER flag is cleared to 0 it will be set to 1 again.
Sending a Break Signal
When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or
output) of which are determined by DR and DDR bits. This feature can be used to send a break
signal.
After the serial tran smitter is initialized, the DR value substitutes for the mark state until the TE
bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR
bits should therefore both be set to 1 beforehand.
To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0.
When the TE bit is clear ed to 0 the transmitter is initialized, regardless of its current state, so th e
TxD pin becomes an input/output port outputting the value 0.
Receive Error Flags and Transmitter Operation (Synchronous Mode Only)
When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting ,
even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to
transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0.
Receive Data Sampling Timing in Asynchronous Mode and Receive Margin
In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In
receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the
base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure
11.21.
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Internal
base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
0715 0 715 0
D
0
D
1
8 clocks
16 clocks
Start bit
Figure 11.21 Receive Data Sampling Timing in Asynchronous Mode
The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = | ( 0.5 – 1
2N ) – (L – 0.5) F | D – 0.5 |
N (1 + F) | × 100% ..........(1)
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2).
When D = 0.5, F = 0:
M = [0.5 – 1/(2 × 16)] × 100%
= 46.875%..........................................................................................(2)
This is a theoretical v a lue. A reasonable margin to allo w in system design is 20% to 30%.
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Restrictions in Synchronous Mode
When data transmission is performed using an external clock source as the serial clock, an interval
of at least 5 states is necessary between clearing the TDRE flag in SSR and the start (falling edge)
of the first transmit clock pulse corresponding to each frame (figure 11.22). This interval is also
necessary when performing continuous transmission. If this condition is not satisfied, an operation
error may occur.
TDRE
TXD
SCK
t*
X0 X1 X2 X3 X4 X5 X6 X7
Note: * Make sure that t is at least 5 states.
t*
Y0 Y1 Y2 Y3
Continuous transmission
Figure 11.22 Transmission in Synchronous Mode ( Example)
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Restrictions when Switching from SCK Pin to Port Function in Synchro nous SCI
1. Problem in Operation
After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is
switched to th e port function at th e end of tr ansmission, a low-level signa l is output for one
half-cycle before the port output state is established.
When switching to the port function by making the following settings while DDR = 1, DR = 1,
C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle.
(1) End of serial data transmission
(2) TE bit = 0
(3) C/A bit = 0 ... switchover to port output
(4) Occurrence of low-level output (see figure 11.23)
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 6 Bit 7
(2) TE = 0
(3) C/A = 0
(1) End of transmission (4) Low-level output
Half-cycle low-level output occurs
Figure 11.23 Operation when Switching from SCK Pin Function to Port Pin Function
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2. Usage Note
The procedure shown below should be used to prevent low-level output when switching from
the SCK pin function to the port function.
As this procedure temporarily places the SCK pin in the input state, the SCK/port pin should
be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0,
CKE0 = 0, and TE = 1, make the following settings in the order shown.
(1) End of serial data transmission
(2) TE bit = 0
(3) CKE1 bit = 1
(4) C/A bit = 0 ... switchover to port output
(5) CKE1 bit = 0
SCK/port
Data
TE
C/A
CKE1
CKE0
Bit 6 Bit 7
(2) TE = 0
(5) CKE1 = 0
(3) CKE1 = 1
(4) C/A = 0
(1) End of transmission
High-level output
Figure 11.24 Operation when Switching from SCK Pin Function to Port Pin Function
(Preventing Low-Level Output)
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Section 12 Smart Card Interface
12.1 Overview
SCI0 supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification
Card) as a serial communication interface extension function.
Switching between the normal serial communication interface and the Smart Card interface is
carried out by means of a register setting.
12.1.1 Features
Features of the Smart Card interface supported by the H8/3039 Group are as follows.
• Asynchronous mode
Data length: 8 bits
Parity bit generation and checking
Transmission of erro r signal (parity error) in receive mode
Error sig nal detection and automatic da ta retransmission in transmit mode
Direct convention and inverse convention both supported
• On-chip baud rate generator allows any bit rate to be selected
• Three interrupt sources
Three interrupt sources (transmit data empty, receive data full, and transmit/receive error)
that can issue requests independ ently
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12.1.2 Block Diagram
Figure 12.1 shows a block diagram of the Smart Card interface.
Bus interface
TDR
RSR
RDR
Module data bus
TSR
SCMR
SSR
SCR
Transmission/
reception control
BRR
Baud rate
generator
Internal
data bus
RxD
0
TxD
0
SCK
0
Parity generation
Parity check
Clock
φ
φ/4
φ/16
φ/64
TXI
RXI
ERI
SMR
Legend:
SCMR:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Smart Card mode register
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Bit rate register
Figure 12.1 Block Diagram of Smart Card Interface
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12.1.3 Pin Configuration
Table 12.1 shows the Smart Card interface pin configuration.
Table 12.1 Smart Card Interface Pins
Pin Name Abbreviation I/O Function
Serial clock pin 0 SCK0Output SCI0 clock output
Receive data pin 0 RxD0Input SCI0 receive data input
Transmit data pin 0 TxD0Output SCI0 transmit data output
12.1.4 Register Configuration
Table 12.2 sho ws the registers used by the Smart Card interf ace. Details of SMR, BRR, SCR,
TDR, and RDR are the same as for the normal SCI function: see the register descriptions in
section 11, Serial Communication Interface.
Table 12.2 Smart Card Interface Registers
Address*1Name Abbreviation R/W Initial Value
H'FFB0 Serial mode register SMR R/W H'00
H'FFB1 Bit rate register BRR R/W H'FF
H'FFB2 Serial co ntrol register SCR R/W H'00
H'FFB3 Transmit data register TDR R/W H'FF
H'FFB4 Serial sta t us regi ster SSR R/(W)*2H'84
H'FFB5 Receive data register RDR R H' 00
H'FFB6 Smart card mode
register SCMR R/W H'F2
Notes: 1. Lower 16 bits of the address.
2. Can only be written with 0 for flag clea ring.
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12.2 Register Descriptions
Registers added with the Smart Card interface and bits for which the function changes are
described here.
12.2.1 Sma rt Ca rd Mode Register (SCMR)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Reserved bits
Smart card data transfer direction
Selects the serial/parallel conversion format
Smart card data invert
Inverts data logic levels
Smart card interface
mode select
Enables or disables
the smart card
interface function
SCMR is an 8-bit readable/writable register that selects the Smart Card interface function.
SCMR is initial ized to H'F2 by a reset, and in standby mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion
format.
Bit 3
SDIR Description
0 TDR contents are transmitted LSB-first (Initial value)
Receive data is stored in RDR LSB-first
1 TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
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Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This
function is used together with the SDIR bit for communication with an inverse convention card.
The SINV bit do e s not af f ect the logic level of the parity bit. For par ity-related setting procedures,
see section 12.3.4, Register Settings.
Bit 2
SINV Description
0 TDR contents are transmitted as they are (Initial value)
Receive data is stored as it is in RDR
1 TDR contents are inverted before being transmitted
Receive data is stored in inverted form in RDR
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
Bit 0—Smart Card Interface Mode Select (SMIF): This bit enables or disables the Smart Card
interface function.
Bit 0
SMIF Description
0 Smart Card interface function is disabled (Initial value)
1 Smart Card interface function is enabled
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12.2.2 Serial Status Register (SSR)
Bit
Initial value
R/W
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
ERS
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Error signal status
Status flag indicating that an
error signal has been received
Transmit end
Status flag indicating
end of transmission
Note: * Only 0 can be written to bits 7 to 3, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial
Status Register ( SSR) .
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
Bit 4
ERS Description
0 Indicates normal data transmission, with no error signal returned
[Clearing cond iti ons ] (Initial value)
• Upon reset, in standby mode, or in module stop mode
• When 0 is written to ERS after reading ERS = 1
1 Indicates that the receiving device sent an error signal reporting a parity error
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bi t in SCR to 0 does not affect the ERS flag, which retains its previous
state.
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Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial
Status Register ( SSR) .
However, the setting conditions for the TEND bit are as shown below.
Bit 2
TEND Description
0 Transmiss ion is in progre ss
[Clearing cond iti on] (Initial value)
When 0 is written to TDRE after reading TDRE = 1
1 End of transmission
[Setting conditions]
• Upon reset and in standby mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a
1-byte serial character
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
12.3 Operation
12.3.1 Overview
The main functions of the Smart Card interface are as follows.
• One frame consists of 8-bit and plus a parity bit.
• In transmissio n, a guard time of at least 2 etu (Eleme ntary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and th e start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If the error sig nal is sampled dur ing tr ansmission, the same data is tran smitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no clocked synchronous
communication function.
Section 12 Smart Card Interface
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12.3.2 Pin Connections
Figure 12.2 shows a schematic diagram of Smart Card interface related pin connections.
In communication with an IC card, since both transmission and reception are carried out on a
single data transmission line, th e TxD0 pin and RxD0 pin should be connected with the LSI pin.
The data transmission line should be pulled up to the VCC power supply with a resistor.
When the clock generated on the Smart Card interface is used by an IC card, the SCK0 pin output
is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal
clock.
LSI port output is used as the reset signal.
Other pins must normally be connected to the power supply or ground.
H8/3039 Group
Chip
Connected equipment
IC card
TxD
0
RxD
0
SCK
0
Px (port)
I/O
CLK
RST
Data line
V
CC
Clock line
Reset line
Figure 12.2 Schematic Diagram of Smart Card Interface Pin Connections
Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed
transmission/reception is possible, enabling self-diagnosis to be carried out.
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12.3.3 Data Format
Figure 12.3 shows the Smart Card interface data format. In reception in this mode, a parity check
is carried out on each frame, and if an error is detected an error signal is sent back to the
transmitting end, and retransmission of the data is requested. If an error signal is sampled during
transmission, the same da ta is r e tr ansmitted.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When there is no parity error
Transmitting station output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When a parity error occurs
Transmitting station output
DE
Receiving station
output
Start bit
Data bits
Parity bit
Error signal
Legend:
Ds:
D0 to D7:
Dp:
DE:
Figure 12.3 Smart Card Interface Data Format
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The operation sequence is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
up resistor.
[2] The tr an smitting station star ts a date transfer of one frame. The data frame starts with a start bit
(Ds, low-level). Then 8 data bits (D0 to D7) and a par ity bit (Dp) follows.
[3] With the Smart Card interface, the data line then returns to th e high-impedance state. The data
line is pulled high with a pull-up r e sistor.
[4] The receiving station carries out a parity check.
If there is no parity error and the data is received normally, the receiving station waits for
reception of the next data.
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to reque st r e transmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data
frame.
If it does receive an error signal, however , it returns to step [2] and retransmits the erroneous
data.
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12.3.4 Register Settings
Table 12.3 shows a bit map of the registers used by the smart card interface.
Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described
below.
Table 12.3 Smart Card Interface Register Settings
Bit
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SMR 0 0 1 O/E1 0 CKS1 CKS0
BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR TIE RIE TE RE 0 0 0 CKE0
TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR TDRE RDRF ORER ERS PER TEND 0 0
RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
SCMR ————SDIR SINV —SMIF
Note: —: Unused bit.
SMR Setting: The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to
1 if of the inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section
12.3.5, Clock.
BRR Setting: BRR is used to set the bit rate. See section 12.3.5, Clock, for the method of
calculating the v a lue to be set.
SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI.
For details, see section 11, Serial Communication Interface.
Bit CKE0 specifies the clock output. Set these bits to 0 if a clock is not to be output, or to 1 if a
clock is to be output.
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SCMR Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set
to 1 if of the inverse convention type.
The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the
inverse convention type.
The SMIF bit is set to 1 in the case of the Smart Card interface.
Examples of register settings and the waveform of the start char acter are shown below for the two
types of IC card (direct convention and inverse convention).
• Direct convention (SDIR = SINV = O/E = 0)
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
AZZAZZZAAZ(Z) (Z) State
With the direct convention type, the logic 1 level co rresponds to state Z and the logic 0 level to
state A, and transf er is performed in LSB-first order. The start character data above is H'3B.
The parity bit is 1 sin ce even parity is stipulated for the Smart Card.
• Inverse convention (SDIR = SINV = O/E = 1)
Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp
AZZAAAAAAZ(Z) (Z) State
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level
to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F.
The parity bit is 0, corresponding to state Z, since even parity is stipulated for th e Smart Card.
With the H8/3039 Group, inversion specified by the SINV bit applies only to the data bits, D7
to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies
to both tran smission and reception).
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12.3.5 Clock
Only an internal clock generated by the on-chip baud rate generator can be used as the
transmit/receive clock for the smart card interface. The bit rate is set with BRR an d the CKS1 and
CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 12.5 shows
some samp le bit rates.
If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate
is output from the SCK0 pin.
B = φ
1488 × 22n–1 × (N + 1) × 106
Where: N = Value set in BRR (0 ≤ N ≤ 255)
B = Bit rate (bit/s)
φ = Operating frequency* (MHz)
n = See table 12.4
Table 12.4 Correspondence betwee n n and CKS1, CKS0
n CKS1 CKS0
00 0
11
21 0
31
Note: * If the gear function is used to divide the system clock frequency, use the divided
frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency
division.
Table 12.5 Exa mples of Bit Rate B ( bit/s) for Various BRR Settings (When n = 0)
φ
φφ
φ (MHz)
N 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00
0 9600.0 13440.9 14400.0 17473.1 19200.0 21505.4 24193.5
1 4800.0 6720.4 7200.0 8736.6 9600.0 10752.7 12096.8
2 3200.0 4480.3 4800.0 5824.4 6400.0 7168.5 8064.5
Note: Bit rates are rounded off to one decimal place.
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The method of calculating the value from the operating frequency and bit rate, on the other hand,
is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specif ied.
N = φ
1488 × 22n–1 × B × 106 – 1
Table 12.6 Exa mples of BRR Settings for Bit Rate B (bit/s) (When n = 0)
φ
φφ
φ (MHz)
7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00
bit/s N Error N Error N Error N Error N Error N Error N Error
9600 0 0.00 1 30 1 25 1 8.99 1 0.00 1 12.01 2 15.99
Table 12.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
φ
φφ
φ (MHz) Maximum Bit Rate (bit/s) N n
7.1424 9600 0 0
10.00 13441 0 0
10.7136 14400 0 0
13.00 17473 0 0
14.2848 19200 0 0
16.00 21505 0 0
18.00 24194 0 0
The bit rate error is given by the following fo rmula:
Error (%) = ( φ
1488 × 22n–1 × B × (N + 1) × 106 – 1) × 100
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12.3.6 Data Transfer Operations
Initialization
Before transmitting an d receivin g data, in itialize the SCI as described be lo w. Initializatio n is also
necessary when switching from transmit mode to receive mode, or vice versa.
[1] Clear the TE and RE bits in SCR to 0.
[2] Clear the error flags ERS, PER, and ORER in SSR to 0.
[3] Set the O/E bit and CKS1 an d CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and
set the STOP and PE bits to 1.
[4] Set the SMIF, SDIR, and SI NV bits in SCMR.
When the SMIF bit is set to 1, the TxD0 and RxD0 pins are both switched from ports to SCI
pins, and are placed in the high-impedance state.
[5] Set the value corresponding to the bit rate in BRR.
[6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0.
If the CKE0 b it is set to 1, the clock is ou tput f rom the SCK0 pin.
[7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
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Serial Data Transmission
As data transm ission in smart card mode involves error signal sampling and retransmission
processing, the processing procedure is different from that for the normal SCI. Figure 12.4 shows
an example of the transmission processing flow, and figure 12.5 shows the relation between a
transmit operation and the internal registers.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2 ] and [3] until it can be conf irmed that the TEND flag in SSR is set to 1.
[4] Write the tran sm it data to TDR, clear the TDRE flag to 0, and perform the transmit o peration.
The TEND flag is cleared to 0.
[5] When tr ansmitting data continuously, go back to step [2].
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt servicing is possible.
If transmissio n ends and the TEND flag is set to 1 wh ile the TIE bit is set to 1 and interrupt
requests are en abled, a transmit data empty in ter rup t ( T XI) re quest will b e generated. If an error
occurs in transmission and the ERS f lag is set to 1 while the RIE bit is set to 1 and in ter rup t
requests are enabled, a transfer error interrupt (ERI) reque st will be generated.
For details, see the f ollowing Interrupt Operations.
Section 12 Smart Card Interface
Rev.3.00 Mar. 26, 2007 Page 407 of 682
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Initialization
No
Yes
Clear TE bit to 0
Start transmission
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
Error processing
TEND = 1?
All data transmitted?
TEND = 1?
ERS = 0?
ERS = 0?
Figure 12.4 Example of Transmission Processing Flow
Section 12 Smart Card Interface
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TDR TSR
(shift register)
(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
Data 1
Data 1
Data 1
Data 1 ; Data remains in TDR
I/O signal line output
In case of normal transmission: TEND flag is set
In case of transmit error: ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Data 1
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data has been completed.
Figure 12.5 Relation Between Transmit Operation and Internal Registers
Serial Data Reception
Data reception in Smart Card mode uses the same processing procedure as for the normal SCI.
Figure 12.6 shows an ex ample of the transmission processing flow.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either flag is set, perform
the appropriate receive error processing, then clear both the ORER and the PER flag to 0.
[3] Repeat steps [2] and [3] until it can be confirmed that th e RDRF f lag is set to 1.
[4] Read the receive data from RDR.
[5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2].
[6] To end reception, clear the RE bit to 0.
Section 12 Smart Card Interface
Rev.3.00 Mar. 26, 2007 Page 409 of 682
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Initialization
Read RDR and clear
RDRF flag in SSR to 0
Clear RE bit to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and
PER = 0
RDRF = 1?
All data received?
Yes
Figure 12.6 Example of Reception Processing Flow
With the above processing, interrupt servicing is possible.
If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests
are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in
reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI)
request will b e generated.
For details, see In ter rupt Operation below.
If a parity error occurs during reception and the PER is set to 1, th e receiv ed data is still
transferred to RDR, and therefore this data can be read.
Section 12 Smart Card Interface
Rev.3.00 Mar. 26, 2007 Page 410 of 682
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Mode Switching Operation
When switching from receive mode to transmit mode, first confirm that the receive operation has
been completed, th en start from initialization, clearing RE bit to 0 and setting TE bit to 1. Th e
RDRF flag or the PER and ORER flags can be used to check that the receive operation has been
completed.
When switching from transmit mode to receive mode, first confirm that the transmit operation has
been completed, th en start from initialization, clearing TE bit to 0 and setting RE bit to 1. The
TEND flag can be used to check that the transmit operation has been completed.
Interrupt Operation
There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI)
requests, transfer erro r interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The
transmit end interrupt (TEI) request is not used in this mode.
When the TEND flag in SSR is set to 1, a TXI interrupt request is gener ated.
When the RDRF flag in SSR is set to 1, an RXI interru pt request is gener a ted.
When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
The relationship between the operating states and interrupt sources is shown in table 12.8.
Table 12.8 Smart Ca rd Mode Operating States and Interrupt So urces
Operating State Flag Mask Bit Interrupt Source
Transmit Mode Normal operation TEND TIE TXI
Error ERS RIE ERI
Receive Mode Normal operation RDRF RIE RXI
Error PER, ORER RIE ERI
Section 12 Smart Card Interface
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12.4 Usage Note
The following points should be noted when using the SCI as a smart card interface.
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode
In smart card interface mode, the SCI operates on a basic clock with a frequency of 372 times the
transfer rate.
In reception, the SCI samples the falling edge of the start bit using the basic clo ck, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of
the basic clock . This is illustrated in f igur e 12.7.
Internal
basic
clock
372 clocks
186 clocks
Receive
data (RxD)
Synchro-
nization
sampling
timing
D0 D1
Data
sampling
timing
185 371 0
371
185 0
0
Start bit
Figure 12.7 Receive Data Sampling Timing in Smart Card Mode
Section 12 Smart Card Interface
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Thus the reception margin in smart card interface mode is given by the following formula.
M = (0.5 – 1
2N ) – (L – 0.5) F – D – 0.5
N (1 + F) × 100%
Where M: Reception margin (%)
N: Ratio of bit rate to clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequ ency deviation
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as
follows.
When D = 0.5 and F = 0,
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Section 12 Smart Card Interface
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Retransfer Operations
Retransfer operations are performed by the SCI in receive mode and transmit mode as described
below.
• Retransfer operation when SCI is in receive mode
Figure 12.8 illustrates the retransfer operation when the SCI is in receive mode.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this tim e, an ERI interrupt reque st is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
[2] The RDRF bit in SSR is not set for a fram e in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
error signal tr ansmission.
D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp(DE)DsD0D1D2D3D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
RDRF
[1]
PER
[2]
[3]
[4]
Figure 12.8 Retransfer Operation in SCI Receive Mode
Section 12 Smart Card Interface
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• Retransfer operation when SCI is in transmit mode
Figure 12.9 illustrates the re tr ansfer operatio n when the SCI is in transm it mode.
[6] If an error signal is sent back from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enab led at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next
parity b it is sam pled.
[7] The TEND b it in SSR is not set for a f rame for which an error signal indicating an abnormality
is received.
[8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
[9] If an error signal is not sent back from the receiving end, transmission of one frame, including
a retransfer, is ju dged to have been completed, and the TEND bit in SSR is set to 1. If the TIE
bit in SCR is enabled at this time, a TXI inter r upt request is gen erated.
D0D1D2D3D4D5D6D7Dp DE DsD0D1D2D3D4D5D6D7Dp (DE) DsD0D1D2D3D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[6]
ERS
Transfer to TSR from TDR
[7] [9]
[8]
Transfer to TSR from TDR Transfer to TSR
from TDR
Figure 12.9 Retransfer Operation in SCI Transmit Mode
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 415 of 682
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Section 13 A/D Converter
13.1 Overview
The H8/3039 Group includes a 10-bit successive-approximations A/D converter with a selection
of up to eight analog input channels.
When the A/D converter is not used, it can be halted independently to conserve power. For details
see section 17.6, Module Standby Function.
13.1.1 Features
A/D converter features are listed below.
• 10-b it resolution
• Eight input channels
• Selectable analog conversion voltage range
The analog voltage conversion range can be programmed by input of an analog reference
voltage at the AVCC pin.
• High-speed conversion
Conversion time: minimum 7.4 µs per channel (with 18 MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and -hold function
• A/D conversion can be externally triggered
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 416 of 682
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13.1.2 Block Diagram
Figure 13.1 shows a block diagram of the A/D converter.
Module data bus
Bus interface
Internal
data bus
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
Successive-
approximations register
10-bit D/A
AV
AV
CC
SS
Analog
multi-
plexer
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Sample-and-
hold circuit
Comparator
+
–
Control circuit
ADTRG
φ/8
φ/16
ADI
interrupt
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 13.1 A/D Converter Block Diagram
Section 13 A/D Converter
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13.1.3 Input Pins
Table 13.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into
two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power
supply for the analog circuits in the A/D converter.
Table 13.1 A/D Converter Pins
Pin Name Abbrevi-
ation I/O Function
Analog power supply pin AVCC Input Analog power supply and reference voltage
Analog ground pin AVSS Input Analog ground and reference voltage
Analog input pin 0 AN0Input Group 0 analog inputs
Analog input pin 1 AN1Input
Analog input pin 2 AN2Input
Analog input pin 3 AN3Input
Analog input pin 4 AN4Input Group 1 analog inputs
Analog input pin 5 AN5Input
Analog input pin 6 AN6Input
Analog input pin 7 AN7Input
A/D external trigger input pin ADTRG Input External trigger input for starting A/D
conversion
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 418 of 682
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13.1.4 Register Configuration
Table 13.2 summarizes the A/D converter's registers.
Table 13.2 A/D Converter Registers
Address*1Name Abbreviation R/W Initial Value
H'FFE0 A/D data register A (high) ADDRAH R H'00
H'FFE1 A/D data register A (low) ADDRAL R H'00
H'FFE2 A/D data register B (high) ADDRBH R H'00
H'FFE3 A/D data register B (low) ADDRBL R H'00
H'FFE4 A/D data register C (high) ADDRCH R H'0 0
H'FFE5 A/D data register C (low) ADDRCL R H'00
H'FFE6 A/D data register D (high) ADDRDH R H'0 0
H'FFE7 A/D data register D (low) ADDRDL R H'00
H'FFE8 A/D control/status register ADCSR R/(W)*2H'00
H'FFE9 A/D control register ADCR R/W H'7F
Notes: 1. Lower 16 bits of the address
2. Only 0 can be written in bit 7 to clear the flag.
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 419 of 682
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13.2 Register Descriptions
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
Initial value
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
A/D conversion data
10-bit data giving an
A/D conversion result
Reserved bits
Read/Write
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-b it read-on ly registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that always read 0. Table 13.3 indicates the pairings of analog input
channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 13.3, CPU
Interface.
The A/D data register s ar e initialized to H'0000 by a reset and in standby mode.
Table 13.3 Analo g Input Channe ls and A/D Data Reg isters
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
Section 13 A/D Converter
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13.2.2 A/D Control/Status Register (ADCSR)
Bit
Initial value
Read/Write
7
ADF
0
R/(W)*
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
A/D end flag
Indicates end of A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
A/D start
Starts or stops A/D conversion
Scan mode
Selects single mode or scan mode
Clock select
Selects the A/D conversion time
Channel select 2 to 0
These bits select analog
input channels
Note: * Only 0 can be written to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing conditi on] (Initial value)
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1 [Setting conditions]
• Single mode: A/D conversion ends
• Scan mode: A/D conversion ends in all selected channels
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Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE Description
0 A/D end interrupt request (ADI) is disabl ed (Initial value)
1 A/D end interrupt request (ADI) is enabled
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during
A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin.
Bit 5
ADST Description
0 A/D conversion is stopped (Initial value)
1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends.
Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a
transition to standby mode.
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 13.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
Bit 3—Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before
switching the conversion time.
Bit 3
CKS Description
0 Conversion time = 266 states (maximum) (Initial value)
1 Conversion time = 134 states (maximum)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 422 of 682
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Group
Selection Channel Selection Description
CH2 CH1 CH0 Single Mode Scan Mode
000AN
0 (Initial value) AN0
1AN
1AN0, AN1
10 AN
2AN0 to AN2
1AN
3AN0 to AN3
100AN
4AN4
1AN
5AN4, AN5
10 AN
6AN4 to AN6
1AN
7AN4 to AN7
13.2.3 A/D Co ntrol Register (ADCR)
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Trigger enable
Enables or disables external triggering of A/D conversion
Reserved bits
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7
TRGE Description
0 A/D conversion cannot be externally triggered (Initial value)
1 A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
Section 13 A/D Converter
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13.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be accessed directly by the CPU, the lower byte is read
through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte v alue is transferred into TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is possible
to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 13.2 shows the data flow for access to an A/D data register.
Upper-byte read
Bus interface Module data bus
CPU
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower-byte read
Bus interface Module data bus
CPU
(H'40)
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
Figure 13.2 A/D Data Register Access Operation (Reading H'AA40)
Section 13 A/D Converter
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13.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
13.4.1 Single Mode (SCAN = 0)
Single mode shou ld be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conver sion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making
the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be
set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next.
Figure 13.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 =
1), the A/D interrupt is enabled (ADIE = 1) , and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D conver ter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D inter r upt handling routine star ts.
5. The ro u tine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Executio n of the A/D interrupt handling ro utine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
Section 13 A/D Converter
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ADIE
ADST
ADF
State of channel 0
(AN )
Set
Set Set
Clear Clear
Idle
Idle
Idle
Idle
Idle
A/D conversion (1) A/D conversion (2)
Idle
Read conversion result
A/D conversion result (1) Read conversion result
A/D conversion result (2)
Vertical arrows ( ) indicate instructions executed by software.
0
1
2
3
A/D conversion
starts
*
*
*
*
*
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Note: *
Figure 13.3 Example of A/D Converter Operation
(Single Mode, Channel 1 Selected)
Section 13 A/D Converter
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13.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5)
starts immediately. A/D conversion continues cyclically on the selected channels until the ADST
bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers
corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making th e necessary changes, set the ADST bit to 1. A/D conversion will start again from the
first channel in the group. The ADST bit can be set at the same time as the m ode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 13.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), an alog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF f lag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrup t is r equested at this time.
5. Steps 2 to 4 are repeated as long as the ADST b it remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 427 of 682
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ADST
ADF
State of channel 0
(AN )
0
1
2
3
Continuous A/D conversion
Set Clear
*1
Clear
*1
Idle A/D conversion (1) Idle
Idle
Idle
A/D conversion (4) Idle
A/D conversion (2)
Idle
A/D conversion (5)
Idle
A/D conversion (3)
Idle
Idle
Transfer A/D conversion result (1) A/D conversion result (4)
A/D conversion result (2)
A/D conversion result (3)
1.
2.
A/D conversion time
Notes:
*
2
*1
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Vertical arrows ( ) indicate instructions executed by software.
Data currently being converted is ignored.
Figure 13.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 428 of 682
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13.4.3 Input Sampling and A/D Co nversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 13.5 shows the A/D
conversion timing. Table 13.4 indicates the A/D conversion time.
As indicated in figure 13.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 13.4.
In scan mode, the values given in table 13.4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
φ
Address bus
Write signal
Input sampling
timing
ADF
(1)
(2)
t
D
t
SPL
t
CONV
Legend:
(1):
(2):
t :
t :
t :
D
SPL
CONV
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
A/D conversion time
Figure 13.5 A/D Conversion Timing
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 429 of 682
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Table 13.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Symbol Min Typ Max Min Typ Max
Synchronization delay tD10 —17 6 — 9
Input sampling tim e tSPL —63 ——31 —
A/D conversion time tCONV 259 —266 131 —134
Note: Values in the table are numbers of states.
13.4.4 External Trigg er Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger in put is en abled at the ADTRG pin. A high-to-low tr ansition at the ADTRG pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 13.6 shows the
timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 13.6 External Trigger Input Timing
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 430 of 682
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13.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
13.6 Usage Notes
The following points should be noted when using the A/D converter.
Setting Rang e of Analog Power Supply and Other P ins
(1) Analog input voltage range
The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the
range AVSS ≤ ANn ≤ AVCC.
(2) Relation between AVCC, AVSS and VCC, VSS
As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is
not used, the AVCC and AVSS pins must on no account be left open.
If conditions (1) and (2) above are not met, the reliability of the device may be adversely affected.
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must b e isolated from the analog input signals (AN0 to AN7), and analog
power supply and reference voltage (AVCC) by the analog ground (AVSS). Also, the analog ground
(AVSS) should be connected at one point to a stable digital ground (VSS) on th e board.
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7) and analog power supply (AVCC) should be connected
between AVCC and AVSS as shown in figure 13.7.
Also, the bypass capacitors connected to AVCC and the filter capacitor connected to AN0 to AN7
must be connected to AVSS.
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 431 of 682
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If a filter capacitor is connected as shown in figure 13.7, the input currents at the analog input pins
(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Therefore careful consideration is required
when deciding the circuit constants.
AVCC
*1AN0 to AN7
AVSS
Notes: Values are reference values.
1.
2. Rin: Input impedance
Rin*2100 Ω
0.1 µF
0.01 µF10 µF
Figure 13.7 Example o f Analog Input Pr otection Circuit
Table 13.5 Analog Pin Specificat ions
Item Min Max Unit
Analog input capacitance —20 pF
Permissible signal source impedance —10*kΩ
Note: *When VCC = 4.0 V to 5.5 V and φ ≤ 12 MHz
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 432 of 682
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20 pF
To A/D
converter
AN0 to
AN7
10 kΩ
Note: Values are reference values.
Figure 13.8 Analog Input Pin Equiva lent Circuit
A/D Conversion Precision Definitions
H8/3039 Group A/D conversion precision definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 13.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 13.10).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.9).
• Nonlinearity er ror
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.
• Absolute pr ecision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 433 of 682
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111
110
101
100
011
010
001
000 FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
1
82
83
85
8
4
86
87
8
Figure 13.9 A/D Conversion Precision Definitions (1)
FS
Offset error
Nonlinearity
error
Actual A/D conversion
characteristic
Analog
input voltage
Digital output
Ideal A/D conversion
characteristic
Full-scale error
Figure 13.10 A/D Conversion Precision Definitions (2)
Section 13 A/D Converter
Rev.3.00 Mar. 26, 2007 Page 434 of 682
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Permissible Signal Source Impedance
H8/3039 Group analog input is designed so that conversion precision is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion precision.
When converting in the single mode, if a large capacitance is provided externally, the input load
will essentially comprise only the internal input resistance of 10 kΩ, and the signal source
impedance is ignored.
However, sin ce a low-pass filter effect is ob tained in this case, it may not be possible to follow an
analog signal with a large differential coefficient (e.g., voltage regulation 5 mV/µs or greater).
When converting a high-speed analog signal and when performing conversion in the scan mode, a
low-impedance buffer should be inserted.
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVSS.
Care is also required to in sure that filter circuits d o not communicate with digital signals on th e
mounting board, thus acting as antennas.
A/D converter
equivalent circuit
H8/3039 Group
20 pF
Cin =
15 pF
10 kΩ
Up to 10 kΩ
Low-pass
filter C
Up to 0.1 µF
Sensor output
impedance
Sensor input
Note: Values are reference values.
Figure 13.11 Example of Ana log Input Circuit
Section 14 RAM
Rev.3.00 Mar. 26, 2007 Page 435 of 682
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Section 14 RAM
14.1 Overview
The H8/3039 has 4 kbytes of on-chip static RAM, H8/3038 has 2 kbytes, H8/3037 has 1 kbyte,
and H8/3036 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU
accesses both byte data and word data in two states, making the RAM suitable for rapid data
transfer.
The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the
on-chip RAM.
Table 14.1 shows the address of the on-chip RAM in each operating mode.
Table 14.1 The Address o f the On-Chip RAM in Each Operating Mode
Mode H8/3039
(4 kbytes) H8/3038
(2 kbytes) H8/3037
(1k byte) H8/3036
(512 bytes)
Modes 1, 5, 7 H'FEF10 to
H'FFF0F H'FF710 to
H'FFF0F H'FFB10 to
H'FFF0F H'FFD10 to
H'FFF0F
Mode 3 H'FFEF10 to
H'FFFF0F H'FFF710 to
H'FFFF0F H'FFFB10 to
H'FFFF0F H'FFFD10 to
H'FFFF0F
Mode 6 H'F710 to
H'FF0F H'F710 to
H'FF0F H'FB10 to
H'FF0F H'FD10 to
H'FF0F
Section 14 RAM
Rev.3.00 Mar. 26, 2007 Page 436 of 682
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14.1.1 Block Diagram
Figure 14.1 shows a block diagram of the on-chip RAM.
H'FEF10*
H'FEF12*
H'FFF0E*
H'FEF11*
H'FEF13*
H'FFF0F*
Bus interface SYSCR
On-chip RAM
Even addresses Odd addresses
Legend:
SYSCR: System control register
Note: * Lower 20 bits of the address
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 14.1 RAM Block Diagram (H8/3039 in Mo des 1, 5 and 7)
14.1.2 Register Configuration
The on-chip RAM is controlled by the system control register (SYSCR). Table 14.2 gives the
address an d initial value of SYSCR.
Table 14.2 RAM Control Register
Address*Name Abbreviation R/W Initial Value
H'FFF2 System control register SYSCR R/W H'0B
Note: *Lower 16 bits of the address
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14.2 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
2
NMIEG
0
R/W
1
—
1
—
0
RAME
1
R/W
Software standby Standby timer select 2 to 0
User bit enable
NMI edge select
Reserved bit
RAM enable bit
Enables or
disables
on-chip RAM
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RA M Enable ( R AME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value)
Section 14 RAM
Rev.3.00 Mar. 26, 2007 Page 438 of 682
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14.3 Operation
When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip
RAM when addressing the addresses shown in table 14.1 in each operation mode. When the
RAME bit is cleared to 0 in modes 1, 3, and 5 (expanded modes), external address space is
accessed. When the RAME bit is cleared to 0 in modes 6 and 7 (single-chip modes), the on-chip
RAM is not accessed. Read operation always reads H'FF and disables writing .
The on-chip RAM is con nected to the CPU by a 16-bit wide data bu s and can be read and wr itten
on a byte or a word basis.
Byte data can be accessed in two states using the higher 8 bits of the data bus. Word data
beginning from an even address can be accessed in two states using the 16-bit data bus.
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 439 of 682
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Section 15 ROM
15.1 Overview
The H8/3039 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8/3038 has 64
kbytes, the H8/3037 has 32 kbytes and H8/3036 has 16 kbytes. The ROM is connected to the CPU
by a 16-bit data bus. The CPU accesses both byte and word data in two states, enabling rapid data
transfer.
The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM. See table 15.1.
The on-chip flash memory product (H8/3039F-ZTAT) can be erased and programmed on-board as
well as with a general-purpose PROM programmer.
Table 15.1 Opera t ing Mode and ROM
Mode Pins
Mode MD2MD1MD0On-Chip ROM
Mode 1
(1-Mbyte expanded mode with on-chip ROM disabled) 0 0 1 Disabled (external
address area)
Mode 2
(1-Mbyte expanded mode with on-chip ROM disabled)*010
Mode 3
(16-Mbyte expanded mode with on-chip ROM disabled) 011
Mode 4
(16-Mbyte expanded mode with on-chip ROM disabled)*100
Mode 5
(16-Mbyte expanded mode with on-chip ROM enabled) 1 0 1 Enabled
Mode 6 (single-chip normal mode) 1 1 0
Mode 7 (single-chip advanced mode) 1 1 1
Note: *Modes 2 and 4 cannot be used with this LSI. Do not set the mode pin to mode 2 or 4.
Section 15 ROM
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15.2 Overview of Flash Memory
15.2.1 Features
The features of the flash memory are summarized below.
• Four flash memo ry operating modes
Program mode
Erase mode
Program-verif y mode
Erase-verify mode
• Programming/erase methods
The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase. The
block to be erased can be specified by setting the corresponding bit. There are block areas of
32 kbytes × 3 blocks, 28 kbytes × 1 block, and 1 kbyte × 4 blocks .
• Programm ing/er a se times
The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming,
equivalent to 300 µs (typ.) per byte, and the erase time is 100 ms (typ.) per block.
• Reprogram ming capability
The flash memory can be reprogrammed up to 100 times.
• On-board programming modes
There are two modes in which flash memory can be programmed/erased/verified on-board:
Boot mode
User program mode
• Automatic bit r a te ad justment
With data transf er in boot mode, the this LSI's bit rate can be automatically adju sted to match
the transfer bit rate of the host (9600 bps and 4800 bps).
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• PROM mode
Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as
well as in on-board programming mode.
• Protect modes
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase/verify operations.
Section 15 ROM
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15.2.2 Block Diagram
Figure 15.1 shows a block diagram of the flash memory.
Bus interface/controller
On-chip Flash memory
(128 kbytes)
Operating
mode
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
FWE pin*
1
Mode pins
FLMCR*
2
EBR*
2
RAMCR*
2
FLMSR*
2
H'00000
H'00002
H'00001
H'00003
H'1FFFE H'1FFFF
even address odd address
Legend:
FLMCR: Flash memory control register
EBR: Erase block register
RAMCR: RAM control register
FLMSR: Flash memory status register
Notes: 1. Functions as the FWE pin in the flash memory versions and as the RESO pin in the
mask ROM versions.
2. The registers that control the flash memory versions (FLMCR, EBR, RAMCR, and
FLMSR) are used in the flash memory versions only. They are not provided in the
mask ROM versions. Reading the corresponding addresses in a mask ROM version
will always return 1s, and writes to these addresses are disabled.
H'1FFFC H'1FFFD
Figure 15.1 Block Diagram of Flash Memory
Section 15 ROM
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15.2.3 Pin Configuration
The flash memory is controlled by means of the pins shown in table 15.2.
Table 15.2 Flash Memory Pins
Pin Name Abbreviation I/O Function
Reset RES Input Reset
Flash write enable FWE*Input Flash program/erase protection by hardware
Mode 2 MD2Input Sets this LSI operating mode
Mode 1 MD1Input Sets this LSI operating mode
Mode 0 MD0Input Sets this LSI operating mode
Transmit data TxD1Output Serial transmit data output
Receive data RxD1Input Serial receive data input
Notes: The transmit data and receive data pins are used in boot mode.
*In the mask ROM versions, the FWE pin functions as the RESO pin.
15.2.4 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 15.3.
Table 15.3 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address*1
Flash memory control register FLMCR R/W H'00*2H'FF40
Erase block regi ster EBR R/W H'00 H'FF42
RAM control register RAMCR R/W H'F1 H'FF47
Flash memory status register FLMSR R H'7F H'FF4D
Notes: 1. Lower 16 bits of the address.
2. When a high level is input to the FWE pin, the initial value is H'80.
The registers in table 15.3 are used in the flash memory versions only. Reading the corresponding
addresses in a m a sk ROM version will alway s re turn 1s, and writes to these addresses are disabled.
Section 15 ROM
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15.3 Register Descriptions
15.3.1 Flash Memory Control Register (FLMCR)
FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode
or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by
setting SWE to 1 when FWE = 1, then setting the PSU bit, and fin a lly setting the P bit. Erase
mode is enter e d by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting
the E bit. FLMCR is initial ized by a reset, and in h ardware standby mode and software stan dby
mode. Its in itial v a lue is H'80 when a high level is inpu t to the FWE pin, and H'00 when a low
level is input. In mode 6 the FWE pin must be fixed low, as flash memory on-board programming
is not supported. Therefore, bits in this register cannot be set to 1 in mode 6. When on-chip flash
memory is disabled, a read will return H'00, and writes ar e invalid. When setting bits 6 to 0 in this
register to 1, each bit should be set individually.
Writes to the ESU, PSU, EV and PV bits in FLMCR are enabled only when FWE = 1 and SWE =
1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to th e P bit only
when FWE = 1, SWE = 1, and PSU = 1.
Section 15 ROM
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Bit
Modes
1 to 4,
and 6
7
0
R0
R0
R0
R0
R0
R0
R0
R
Initial value
Read/Write
Initial value
Read/Write
Modes
5 and 7 1/0
R0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
FWE EV
6543210
ESU PSU PV E P
Program setup
Prepares for a transition to program mode.
Erase setup
Prepares for a transition to erase mode.
Erase mode
Designates transition
to or exit from erase
mode
Program mode
Designates
transition to
or exit from
program mode
Program-verify mode
Designates transition to
or exit from program-verify
mode
Erase-verify mode
Designates transition to
or exit from erase-verify
mode
Flash write enable bit
Sets hardware protection against flash memory programming/erasing.
Software write enable bit
Enables or disables the flash memory.
SWE
Bit 7—Flash Write Enable Bit (FWE): Sets hardware protection against flash memory
programming/erasing. When using this bit, refer to section 15.9, Notes on Flash Memory
Programming/Erasing.
Bit 7
FWE Description
0 When a low level is input to the FWE pin (hardware-protected state)
1 When a high level is input to the FWE pin
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Bit 6—Software Write Enable Bit (SWE)*1 *2: This bit enables/disables flash memory
programming/erasing. This bit should be set before setting FLMCR bits 5 to 0, and EBR bits 7 to
0. Do not set the ESU, PSU, EV, PV, E, or P bits at the same time.
Bit 6
SWE Description
0 Program/erase disabled (Initial value)
1 Program/erase enabled
[Setting condition]
When FWE = 1
Bit 5—Erase Setup Bit (ES U )*1: Prepares for a transition to erase mode. Do not set the SWE,
PSU, EV, PV, E, or P bit at the same time.
Bit 5
ESU Description
0 Erase setup cleared (Initial value)
1 Erase setup
[Setting condition]
When FWE = 1, and SWE = 1
Bit 4—Program Setup Bit (PSU)*1: Prepares for a transition to program mode. Do not set the
SWE, ESU, EV, PV, E, or P bit at the same time.
Bit 4
PSU Description
0 Program setup cleared (Initial val ue)
1 Program setup
[Setting condition]
When FWE = 1, and SWE = 1
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Bit 3—Erase-Verify (EV)*1: Selects erase-verify mode transition or clearing. Do not set the
SWE, ESU, PSU, PV, E, or P bit at the same time.
Bit 3
EV Description
0 Erase-verify mode cleared (Initial value)
1 Transition to erase-verify mode
[Setting condition]
When FWE = 1, and SWE = 1
Bit 2—Program-Verify (PV)*1: Selects program-verify mode transition or clearing. Do not set
the SWE, ESU, PSU, EV, E, or P bit at the same time.
Bit 2
PV Description
0 Program-verify mode cleared (Initial value)
1 Transition to program-verify mode
[Setting condition]
When FWE = 1, and SWE = 1
Bit 1—Erase (E)*1 *3: Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU,
EV, PV, or P bit at the same time.
Bit 1
E Description
0 Erase mode cleared (Initial value)
1 Transition to erase mode
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
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Bit 0—Program (P)*1 *3: Selects program mode transition or clearing. Do not set the SWE, ESU,
PSU, EV, PV, or E bit at the same time.
Bit 0
P Description
0 Program mode cleared (Initial val ue)
1 Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Notes: 1. Do not set two o r more bits at the same time.
Do not turn off VCC when a bit is set.
2. Do n o t set/clear the SWE bit simultaneo usly with other bits (ESU, PSU, EV, PV, E, P) .
3. Set the P and E bits according to the program and erase algorithms shown in section
15.5, Programming/Erasing Flash Memory.
For the usage precautions, see section 15.9, Notes on Flash Memory
Programming/Erasing.
15.3.2 Erase Block Register (EBR)
EBR is an 8-bit register that desig nates the flash memory block for erasure. EBR is initialized to
H'00 by a reset, in hardware standby mode, or software standby mode, when a high level is not
input to the FWE terminal, or when the FLMCR SWE bit is 0 when a high level is applied to the
FWE terminal. When a bit is set in EBR, the corresponding block can be erased. Other blocks are
erase - protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not
set bits in EBR to erase two or more b locks at the same time.
Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block
configuration is shown in table 15.4. To erase all the blocks, erase each block sequentially.
This LSI does not support the on-board programming mode in mode 6, so bits in this register
cannot be set to 1 in mode 6.
Section 15 ROM
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Bit 7
EB7 EB3
6543210
EB5 EB4 EB2 EB1 EB0
EB6
Modes
1 to 4,
and 6
0
R0
R0
R0
R0
R0
R0
R0
R
Initial value
Read/Write
Initial value
Read/Write
Modes
5 and 7 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
Bits 7 to 0—Block 7 to 0 (EB7 to EB0): These bits select blocks (EB7 to EB0) to be erased.
Bits 7 to 0
EB7 to EB0 Description
0 Block EB7 to EB0 is not selected. (Initial value)
1 Block EB7 to EB0 is selected.
Note: Set each bit of EBR to H'00 except when erasing.
Table 15.4 Flash Memory Erase Blocks
Block (Size) Address
EB0 (1 kbyte) H'00000 to H'003FF
EB1 (1 kbyte) H'00400 to H'007FF
EB2 (1 kbyte) H'00800 to H'00BFF
EB3 (1 kbyte) H'00C00 to H'00FFF
EB4 (28 kbytes) H'01000 to H'07FFF
EB5 (32 kbytes) H'08000 to H'0FFFF
EB6 (32 kbytes) H'10000 to H'17FFF
EB7 (32 kbytes) H'18000 to H'1FFFF
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15.3.3 RAM Contro l Register (RAMCR)
RAMCR selects the RAM area used when emulating real-time reprogramming of the flash
memory.
Bit 7
—RAMS
6543210
——— RAM2 RAM1 —
RAM2/1
This bit is used with
bit 3 to set the RAM
area.
RAM select
This bit is used with
bits 2 and 1 to set
the RAM area.
Reserved bits
Reserved bit
Modes
1 to 4 1
—1
—1
—1
—0
R0
R0
R1
—
Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7 1
—1
—1
—1
—0
R/W*0
R/W*0
R/W*1
—
Note: * Cannot be set to 1 in mode 6.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—RAM Select (RAMS): Is used with bits 2 to 1 to reassign an area to RAM (see table 15.5).
The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and
programming is enabled.* In modes other than 5 to 7, 0 is always read and wr iting is disabled.
It is initialized by a reset and in hardware standby mode. It is not initialized in software standby
mode.
When bit 3 is set, all flash-memory blocks are protected from programming and erasing.
Bits 2 to 1—RAM2 to RAM1: These bits are used with bit 3 to reassign an area to RAM (see
table 15.5). The initial setting f or this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled)
and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled.
They are initialized by a r eset and in hardware standby mode. They are not initialized in software
standby mode.
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Bit 0—Reserved: This bit cannot be modified and is always read as 1.
Note: * Flash memory emulation by RAM is not supported for Mode 6 (single chip normal
mode), so programming is possible, but do not set 1.
When performing flash memory emulation by RAM, the RAME bit in SYSCR must be
set to 1.
Table 15.5 RAM Area Reassign ment
Bit 3 Bit 2 Bit 1
RAM Area RAMS RAM2 RAM1 RAM
Emulation State
H'FFF800 to H'FFFBFF 0 0/1 0/1 No emulation
H'000000 to H'0003FF 1 0 0 Mapping RAM
H'000400 to H'0007FF 1 0 1
H'000800 to H'000B FF 1 1 0
H'000C00 to H'000FFF 1 1 1
ROM block
EB0–EB3
(H'00000–H'00FFF)
ROM area RAM area
H'00000
H'00400
H'00800
H'00C00
EB0
EB1
EB3
Real RAM
H'003FF
H'007FF
H'00BFF
H'00FFF
H'FEF10
H'FF800
H'FFC00
H'FF7FF
H'FFBFF
H'FFF0F
Mapping RAM
EB2
RAM overlap area
(H'FF800–H'FFBFF)
RAM
selection
area
ROM
selection
area
Figure 15.2 Example of Overlap ROM Area and RAM Area
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15.3.4 Flash Memory Status Register (FLMSR)
The flash memory status register (FLMSR) detects flash memory errors.
Bit
Initial value
Read/Write
7
0
FLER —
6543210
1111111
R———————
——————
Reserved bits
Flash memory error
Status flag indicating that
an error was detected during
programming or erasing
Bit 7—Flash Memory Error (FLER): Indicates that an error occurred while flash memory was
being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode.
Bit 7
FLER Description
0 Flash memory program/erase protection (error protection*1) is disabled (Initial value)
[Clearing cond iti on]
WDT reset, reset by RES pin, or hardware standby mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection*1) is enabled
[Setting conditions]
1. Flash memory was read*2 while being programmed or erased (including vector or
instruction fetch, but not including reading of a RAM area overlapped onto flash
memory).
2. A hardware exception-handling sequence (other than a reset, invalid instruction,
trap instruction, or zero-divide exception) was executed just before programming or
erasing.*3
3. The SLEEP instruction (including software standby mode) was executed during
programming or erasing.
Notes: 1. For details, see section 15.6.3, Error Protection.
2. The read data has undetermined values.
3. Before stack and ve ctor read by ex ception handling.
Bits 6 to 0—Reserved: These bits cannot be modified and are always read as 1.
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15.4 On-Board Programming Modes
When pins are set to on-board programming mode, program/erase/verify operations can be
performed on the on-chip flash memory. There are two on-board programming modes: boot mode
and user program mode. The pin settings for transition to each of these modes are shown in table
15.6. In mode 6 (on-chip ROM enabled) in this LSI, the boot mode and user program mode cannot
be used. For the notes on FWE pin set/reset, see section 15.9, Notes on Flash Memory
Programming/Erasing.
Table 15.6 Setting On-Board Programming Modes
Mode FWE MD2MD1MD0Notes
Boot mode mode 5 1*10*2010: V
IL
mode 7 0*2111: V
IH
User program mode mode 5 1 0 1
mode 7 1 1 1
Notes: 1. For the High level input timing, see items (6) and (7) of Notes on Using the Boot Mode.
2. In the boot mode, the MD2 setting becomes inverted input.
In the boot mode, the mode control register (MDCR) can be used to monitor the s tatus
of modes 5 and 7 in the same way as in the normal mode.
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On-Board Programming Modes
• Boot mode
Flash memory
This chip
RAM
Host
Programming control
program
SCI
Application program
(old version)
Programming control
program
New application
program
Programming control
program
New application
program
Flash memory
This chip
RAM
Host
SCI
Application program
(old version)
Boot program area
New application
program
Flash memory
This chip
RAM
Host
SCI
Flash memory
erase
Boot program
Flash memory
This chip
Program execution state
RAM
Host
SCI
New application
program
Boot program
1. Initial state
The flash memory is in the erased state when the
device is shipped. The description here applies to
the case where the old program version or data
is being rewritten. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
this chip (originally incorporated in the chip) is
started, an SCI communication check is carried
out, and the boot program required for flash
memory erasing is automatically transferred to
the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM by SCI communication is
executed, and the new application program in the
host is written into the flash memory.
Boot programBoot program
Boot program area Programming
control program
Figure 15.3 Boot Mode
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• User program mode
Flash memory
This chip
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
This chip
RAM
Host
SCI
New application
program
Flash memory
This chip
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
This chip
Program execution state
RAM
Host
SCI
Boot program
Boot program
Application program
(old version)
New application
program
1. Initial state
(1) The program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When the FWE pin is driven high, user software
confirms this fact, executes the transfer program
in the flash memory, and transfers the
programming/erase control program to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Application program
(old version)
Transfer
program
FWE assessment
program
Transfer program
FWE assessment
program
Transfer program
Transfer
program
Figure 15.4 User Program Mode (Example)
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15.4.1 Boot Mode
When boot mode is used, the flash memory programming control program must be prepared in the
host beforehand. The channel 1 SCI to be used is set to asynchronous mode.
In reset start, after setting this LSI pin to the boot mode, start the microcomputer boot program,
measure the Low period of the data sent from the host, and select the bit rate register (BRR) value
beforehand. Then enable reception of the user program from the outside using the serial
communication interface (SCI) on this LSI, and write the received user program to on-chip RAM.
After the program has been stored the end of writing, execution branches to the top address
(H'FF300) of the on-chip RAM, execute the program written on the on-chip RAM, and enable
flash memory program/erase.
The system configuration in boot mode is shown in figure 15.5, and the boot program mode
execution procedure in figure 15.6.
RXD1
TXD1
SCI1
This LSI
Flash memory
Write data reception
Verify data transmission
Host
On-chip RAM
Figure 15.5 System Configuration in Boot Mode
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After branching to the
RAM boot program area
(H'FEF10 to H'FF2FF),
this LSI checks the data in
the flashmemory user area.
After sending H'AA, this LSI
branches to the RAM area
(H'FF300) and executes the user
program transferred to the RAM.
Transfer
end byte count
N = 0?
All data = H'FF?
Yes
Yes
No
No
1
2
3
4
5
6
7
1
2
3
4
5
6
8
7
8
9
Erase all blocks of flash
memory.*3
Set this LSI to the boot mode and reset starts the LSI.
Set the host to the prescribed bit rate (4800, 9600)
and consecutively send H'00 data in 8-bit data,
1 stop bit format.
This LSI repeatedly measures the RXD1 pin Low
period and calculates the asynchronous
communication bit rate at which the host
performs transfer.
At the end of SCI bit rate adjustment, this LSI sends
one byte of H'00 data to signal the end of adjustment.
Check if the host normally received the one byte bit
rate adjustment end signal sent from this LSI and
sent one byte of H'55 data.
After H'55 is sent, the host receives H'AA and sends
the byte count of the user program that is
transferred to this LSI.
Send the 2-byte count in upper byte and lower byte
order. Then sequentially send the program set by
the user.
This LSI sequentially sends (echo back) each byte of
the received byte count and user program to the host
as verification data.
This LSI sequentially writes the received user
program to the on-chip RAM area (H'FF300–H'FFEFF).
Before executing the transferred user program, this LSI
checks if data was written to flash memory after
control branched to the RAM boot program area
(H'FEF10–H'FF2FF). If data was already written to
flash memory, all the blocks are erased.
9
Notes: 1.
2.
3.
After sending H'AA, this LSI branches to the on-chip
RAM area (H'FF300) and executes the user program
written to that area.
The RAM area that can be used by the user is
3.0 kbytes. Set the transfer byte count to within
3.0 kbytes. Always send the 2-byte transfer byte
count in upper byte and lower byte order.
Transfer byte count example: For 256 bytes (H'0100),
upper byte H'01, lower byte H'00.
Set the part that controls the user program flash
memory at the program according to the flash
memory programming/erase algorithms described later.
When a memory cell malfunctions and cannot be
erased, this LSI sends one H'FF byte as an erase
error and stops the erase operation and subsequent
operations.
This LSI transfers the user
program to RAM.*2
Start
Set pins to boot program mode
and execute reset-start
Host transfers data (H'00)
continuously at prescribed bit rate
This LSI measures low period
of H'00 data transmitted by host
This LSI calculates bit rate
and sets value in bit rate register
After bit rate adjustment, this LSI
transmits one byte of H'00 data to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
indication (H'00), and transmits
one byte of H'55 data
After receiving H'55, this LSI
sends H'AA and receives two bytes
of the byte count (N) of the program
transferred to the on-chip RAM.*1
This LSI
calculates the remaining
number of bytes to be sent (N = N − 1).
Figure 15.6 Boot Mode Execution Procedure
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Automatic SCI Bit Rate Adjustment
Start
bit Stop
bit
D0 D1 D2 D3 D4 D5 D6 D7
Low period (9 bits) measured (H'00 data) High period
(1 or more bits)
Figure 15.7 Measuring the Low Period of the Communication Data from the Host
When boot mode is initiated, this LSI measures the low period of the asynchronous SCI
commun icatio n data ( H '00) transmitted continuou sly f rom the host (figure 15.7). The SCI
transmit/receive format should b e set as follows: 8-bit data, 1 stop bit, no parity. This LSI
calculates the bit rate of the transmission f r om the host from the measur ed low period, and
transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should
confirm that this adjustment end indication (H'00) has been received normally, and transmit one
H'55 byte to the LSI. If reception canno t b e performe d no rmally , in itiate boot mode again (reset),
and repeat the above operations. Depending on the host's transmission bit rate and th e system
clock frequen cy of this LSI, th er e will be a discrepancy between the bit rates of the host and the
LSI. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800 and 9600
bps*1.
Table 15.7 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of this LSI bit rate is possible. The boot program should be executed within this system
clock range*2.
Table 15.7 Syste m Clock Frequencies for which Aut omatic Adjustment of This LSI Bit
Rate Is Possible
Host Bit Rate (bps) System Clock Frequency for which Automatic Adjustment
of This LSI Bit Rate Is Possible (MHz)
9600 8 to 18
4800 4 to 18
Notes: 1. The host bit rate settings are 4800 and 9600bps only. Do not use any other setting.
2. This LSI m a y automatically adjusts the bit rate except for bit rate and system clock
combinatio ns as shown in table 15.7. However, the bit rate of the host and this LSI will
be different and subsequent transfers will not b e carried out n ormally. Therefore,
always execute the boot mode within the range of the bit rate and system clock
combinations shown in table 15.7.
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On-Chip RAM Area Divisions in Boot Mode
In boot mode, the RAM area is divided into an area used by the boot program and an area to which
the user program is transferred via the SCI, as shown in figure 15.8. The boot program area can be
used when a transition is made to the execution state for the user program transferred to RAM.
H'FEF10
H'FFF0F
User program
transfer area
Boot program
area
H'FF300
Notes: 1. The boot program area cannot be used until a transition is made to the execution
state for the user program transferred to RAM. Note also that the boot program
remains in this RAM area even after control branches to the user program.
2. When flash memory emulation is performed using RAM, part of the user program
transfer area (H'FF800 to H'FFBFF) is used as an area for carrying out emulation,
and therefore user program transfer must not be performed to this area.
(Approximately 1kbyte)
(Approximately
3.0 kbytes)
Figure 15.8 RAM Areas in Boot Mode
Notes on using the boot mode
(1) When th is LSI comes out of reset in boot mode, it measures th e low period the input at the
SCI's RXD1 pin. The reset should end with RXD1 high. After the reset ends, it tak es about 100
states for this LSI to get ready to measure the low period of the RXD1 input.
(2) If an y data has been written to th e flash m emory (if all data is not H'FF), all flash memory
blocks are erased when this mode is executed. Therefore, boot mode should be used for initial
on-board programming, or for forced recovery if the program to be activated in user program
mode is accidentally erased and user program mode cannot be executed, for example.
(3) Interrupts cannot be used during programming or erasing of flash memory.
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(4) The RXD1 and TXD1 pins should be pulled up on the board.
(5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing
the RE and TE bits in serial control register (SCR)) before bran ching to the user program.
However, th e adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD1 pin
is in the high level output state (P9DDR P91DDR=1, P9DR P91DR=1).
Before branching to the user program the value of the general registers in the CPU are also
undefined. Therefore, the general registers must be initialized immediately after control
branches to the user program. Since the stack poin ter ( SP) is implicitly used dur ing subroutine
call, etc., a stack area must be specified for use by the user program.
There are no other internal I/O r egisters in which th e initial value is changed.
(6) Transition to the boot mode executes a reset-start of this LSI after setting the MD0 to MD2 and
FWE pins according to the mode setting conditions shown in table 15 .6.
At this time, this LSI latch es the status of the mode pin inside th e m icrocomputer to maintain
the boot mode status at the reset clear (startup with Low → High) timing*1.
To clear boot mode, it is necessary to drive the FWE pin low during the reset, and then execute
reset release*1. The following points must be noted:
(a) Before making a transition from the boot mode to the regular mode, the microcomputer
boot mode must be reset by reset input via the RES pin . At this time, the RES pin must be
hold at low level for at least 20 system clock.*3
(b) Do not change the input levels at the mode pins (MD2 to MD0) or the FWE pin while in
boot mode. When making a mode transition, first enter the reset state by inputting a low
level to the RES pin. When a watchdog timer reset was generated in the boot mode, the
microcomputer mode is not reset and the on-chip boot program is restarted regardless of
the state of the mode pin.
(c) Do not input low level to the FWE pin while the boot progr am is execu tin g and when
programming/erasing flash memory.*2
(7) If the mode pin and FWE pin input levels are changed from 0 V to VCC or from VCC to 0 V
during a reset ( while a low level is being input to the RES pin), the microcomputer's operating
mode will chan ge.
Therefore, since the state of the address dual port and bus control output signals (AS, RD, WR)
changes, use of these pins as output signals during reset must be disabled outside the
microcomputer.
Notes: 1. The mode pin and FWE pin input must satisfy the mode programming setup time (t MDS)
relative to the r eset clear timing.
2. For notes on FWE pin High/Low, see section 15.9, Notes on Flash Memory
Programming/Erasing.
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3. See section 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory
Programming/Erasing. With the mask ROM version of the H8/3039, H8/3038,
H8/3037, and H8/3036, the minimum reset period during operation is 10 system
clocks. However, the flash memory versions of the H8/3039 requires a minimum of 20
system c l ocks.
15.4.2 User Program Mode
When set to the user program mode, this LSI can erase and program its flash memory by executing
a user program. Therefore, on-chip flash memory on-board programming can be performed by
providing a means of controlling FWE and supplying the write data on the board and providing a
write program in a part of the program area.
To select this mode, set the LSI to on-chip ROM enable modes 5 and 7 and apply a high level to
the FWE pin. In this mode, the peripheral functions, other than flash memory, are performed the
same as in modes 5 and 7.
Since the flash memory cannot be read while it is being programmed/erased, place a programming
program on external memory , or transfer the programming program to RAM area, and execute it
in the RAM. In mode 6, do not program/erase the flash memory. When setting mode 6, always
input low level to the FWE pin.
Figure 15.9 shows the procedure for executing when transferred to on-chip RAM. During reset
start, starting from the user program mode is possible.
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FWE = high
(user program mode)
Branch to program in RAM.
Transfer on-board programming
program to RAM.
Reset start
MD
2
− MD
0
= 101, 111
Execute on-board programming
program in RAM
(flash memory reprogramming).
Input low level to FWE after SWE
bit clear (user program mode exit)
Execute user application
program in flash memory.
<Procedure>
The user writes a program that executes steps 3 to 8 in advance
as shown below .
Sets the mode pin to an on-chip ROM enable mode
(mode 5 or 7).
Starts the CPU via reset.
(The CPU can also be started from the user program
mode by setting the FWE pin to High level during reset;
that is, during the period the RES pin is a low level.)
Transfers the on-board programming program to RAM.
Branches to the program in RAM.
Sets the FWE pin to a high level.*
(Switches to user program mode.)
After confirming that the FWE pin is a high level, executes
the on-board programming program in RAM. This
reprograms the user application program in flash memory.
At the end of reprograming, clears the SWE bit, and exits
the user program mode by switching the FWE pin from
a high level to a low level.*
Branches to, and executes, the user application program
reprogrammed in flash memory.
1
2
3
4
5
6
7
8
For notes on FWE pin High/Low, see section 15.9, Notes
on Flash Memory Programming/Erasing.
Note: *
1
2
3
4
5
6
7
8
Figure 15.9 User Program Mode Execution Procedure (Example)
Note: Normally do not apply a high level to the FWE pin. To prevent erroneous programming or
erasing in the even t of program runaway, etc., apply a high level to the FWE pin only
when programming/erasing flash memory (including flash memory emulation by RAM).
If program runaway, etc. causes overprogramming or overerasing of flash memory, the
memory cells will n ot operate normally.
Also, while a high level is applied to the FWE pin, the watchdog timer should be activated
to prevent overprogramming or overerasing due to program runaway, etc.
In mode 6, do not reprogram flash memory. When setting mode 6, always set the FWE pin
to a low level.
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15.5 Programming/Erasing Flash Memory
A software method, using the CPU, is employed to program and erase flash memory in the on -
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR.
For a description of state transition by FLMCR bit setting, see figure 15.10.
The flash memory cannot be read while being programmed or erased. Therefore, the program that
controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
For the programming/erasing notes, see section 15.9, Notes on Flash Memory
Programming/Erasing. For the wait time after each bit in FLMCR is set or cleared, see section
18.2.5, Flash Memory Characteristics.
Notes: 1. Operation is no t guaranteed if setting/resetting o f the SWE, ESU, PSU, EV, PV, E, and
P bits in FLMCR is executed by a program in flash memory.
2. When programming or erasing, set the FWE pin input level to the high level, and set
FWE to 1. (pr ogr am ming/erasing will no t be execu ted if FWE = 0 ).
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Normal mode
On-board
programming mode
software reprogramming
disable state
Erase setup state Erase mode
Programming mode
Erase-verify mode
Program setup state
Program-verify mode
ESU = 1
ESU = 0
SWE = 1
SWE = 0
FWE = 1 FWE = 0 *
1
*
2
*
3
EV = 1
EV = 0
E = 1
E = 0
PV = 1
PV = 0
P = 1
P = 0
PSU =1
PSU = 0
Software
reprogramming
enable state
Notes: : Normal mode : On-board programming mode
1. Do not make a state transition by setting or clearing two or more bits at the same time.
2. After transition from the erase mode to the erase setup state, do not make a transition to the erase mode
without going through the software reprogramming enable state.
3. After transition from the programming mode to the program setup state, do not switch to the programming
mode without going through the software reprogramming enable state.
Figure 15.10 State Transition by Setting of Each Bit of FLMCR
15.5.1 Program Mode
Follow the procedure shown in the prog ram/program-verify flowchart in figure 15.11 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrif icing program data reliability. Prog ramming should be carr ied out 32 bytes at a
time.
For the wait time (x , y, z, α, β, γ, ε, η) after setting or clearing each bit in the flash memory
control register (FLMCR) and the maximum programming count (N), see table 18.15.
Following the elapse of (x) µs or more after the SWE b it is set to 1 in flash m emor y control
register (FLMCR), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the reprogram data area written consecutively to the write add r esses.
(The lower 8 bits o f the first address written to must b e H'00, H'20, H'40, H'60, H'80, H'A0, H'C0,
or H'E0.) 32 consecutive byte data transfers are performed. The program address and program data
are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer
than 32 bytes; in this case, H'FF data must be wr itten to the extra addresses.
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Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (y + z + α + ß) µs as the WDT overflow period. Preparation for entering
program mode (program setup) is performed next by setting the PSU bit in FLMCR. The
operating mode is then switched to program mode by setting the P bit in FLMCR after the elapse
of at least (y) µs.
The time while the P b it is set is the flash memo r y programming time. Make a program setting so
that the time fo r one progr amming operation is with in the range of (z) µs.
The wait time after P bit setting must be changed according to the nu mber of reprogramming
loops. For details, see section 18.2.5, Flash Memory Characteristics.
15.5.2 Program-Verify Mode
In program-verify mode, the data written in program mode is read to check whether it has been
correctly written in the flash memory.
Clear the P bit in FLMCR, th en wait for at least (α) µs before clearing the PSU bit to exit pr ogr am
mode. After exiting pro gram m ode, the watchdog timer setting is also cleared . Then the operating
mode is switched to program-verify mode by setting the PV bit in FLMCR. Before reading in
program-verify mode, a dummy write of H'FF data should be made to the addresses to be read.
The dummy write should be executed after the elapse of (γ) µs or more. When the flash memory is
read in this state (verify data is read in 16-bit u nits), the data at the latched address is read . Wait at
least (ε) µs after the dummy write before performing this read operation. Next, the originally
written data is comp ar ed with th e verify data, and reprogram data is computed (see figure 15.11)
and transferred to RAM. After verification of 32 bytes of data has been completed, exit program-
verify mode, wait for at least (η) µs, then determine whether 32-byte programming has finished. If
reprogramming is necessary, set program mode again, and repeat the program/program-verify
sequence as before. However, ensure that the program/program-verify sequence is not repeated
more than (N) times on the same bits.
Note: A 32-byte area to store program data and a 32-byte area to store reprog ram data are
required in RAM.
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Start
End of programming
Set SWE bit in FLMCR
Wait (x) µs
Consecutively write 32-byte data in
reprogram data area in RAM to flash memory
Programming operation counter n ← 1
Set PSU bit in FLMCR
Wait (y)
µs
Set P bit in FLMCR
Wait (z) µs
Clear P bit in FLMCR
Wait (α) µs
Clear PSU bit in FLMCR
Wait (
β) µs
Set PV bit in FLMCR
Wait (γ) µs
Store 32-byte write data in write data area
and reprogram data area
Enable WDT
Start of programming
NG
No
OK
*6
*6
*5
*4
*6
*3
*6
*6
*6
*1
*2
*6
*6*7
End of programming
*6
Disable WDT
Set verify start address
Programming end flag ← 0
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
Transfer computation result to reprogram
data area
Increment verify address
Reprogram data computation
Clear PV bit in FLMCR
Wait (η) µs
Clear SWE bit in FLMCR
Programming end
flag
← 1 (unfinished)
Programming OK?
32-byte
data verification completed?
Programming end flag = 0?
Programming failure
Yes
Yes
Yes
Clear SWE bit in FLMCR
n > N?
n ← n + 1
Notes: 1. Programming should be performed in the erased state.
(Perform 32-byte programming on memory after all 32 bytes
have been erased.)
2. Data transfer is performed by byte transfer (word transfer is not
possible), with the write start address at a 32-byte boundary.
The lower 8 bits of the first address written to must be H'00,
H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data
transfer must be performed even if writing fewer than 32 bytes;
in this case, H'FF data must be written to the extra addresses.
3. Verify data is read in 16-bit (word) units. (Byte-unit reading is
also possible.)
4. Reprogram data is determined by the computation shown in the
table below (comparison of data stored in the program data
area with verify data). Programming of reprogram data 0 bits is
executed in the next programming loop. Therefore, even bits for
which programming has been completed will be programmed
again if the result of the subsequent verify operation is NG.
5. An area for storing write data (32 bytes) and an area for storing
reprogram data (32 bytes) must be provided in RAM. The
contents of the latter are rewritten in accordance with the
reprogramming data computation.
6. The values of x, y, z, α, β, γ, ε, η, and N are shown in section
18.2.5, Flash Memory Characteristics.
7. The value of z depends on the number of reprogramming loops
(n). Details are given in section 18.2.5, Flash Memory
Characteristics.
No
Write Verify Reprogram
Data Data Data Comments
0 0 1 Programming completed
0 1 0 Programming incomplete; reprogram
1 0 1 —
1 1 1 Still in erased state; no action
RAM
Program data storage
area (32 bytes)
Reprogram data storage
area (32 bytes)
No
Reprogram
Figure 15.11 Program/Program-Verify Flowchart
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15.5.3 Erase Mode
Flash memory erasing should be performed block by block following the procedure shown in the
erase/erase-verify flowchart (single-block erase) shown in figure 15.12.
For the wait time (x , y, z, α, β, γ, ε, η) after setting or clearing of each bit in the flash memory
control register (FLMCR) and the maximum erase count (N), see table 18.15.
To erase the contents of flash memory, make a 1 bit setting for the flash memory area to be erased
in erase block register (EBR) at least (x) µ s after setting the SWE bit to 1 in FLMCR. Next, the
watchdog timer (WDT) is set to prevent ov ererasing due to program runaway, etc. Set a value
greater than (z) ms + (y + α + ß) µs as the WDT overflow period. Preparation for entering erase
mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is
then switched to erase mode by setting th e E b it in FLMCR after the elapse of at least (y) µs.
The time dur ing wh ich the E bit is set is the f lash memory erase time. Ensure that the erase time
does not exceed (z) ms.
Note: With f lash memory er asing, preprogramming (setting all data in the memory to be erased
to "0") is not necessary before starting the erase procedure.
15.5.4 Erase-Verify Mode
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least (α) µs
before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer
setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV
bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be made
to the addresses to be read. The dummy write should be executed after the elap se of (γ) µs or more.
When the flash m e m ory is read in this state (verify data is read in 16-bit units), th e data at the
latched add r ess is read. Wait at least (ε) µs after the dummy write before performing this read
operation. If the read data has been erased (all "1"), a dummy write is performed to the next
address, and erase-verify is performed. If the read data is unerased, set erase mode again, and
repeat the erase/erase-verify sequence as before. However, do not repeat the erase/erase-verify
sequence more than (N) times.
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End of erasing
Start
Set SWE bit in FLMCR
Wait (x) µs
Set E bit in FLMCR
Wait (z) ms
Erase counter n ← 1
Set EBR
Enable WDT
*2
*4
*5
*2
*2
*2
*2
Set block start address
to verify address
*2
*2
*2*2
*2
*3
Start of erase
Clear E bit in FLMCR
Wait (α) µs
Clear ESU bit in FLMCR
Wait (β) µs
Set EV bit in FLMCR
Wait (γ) µs
H'FF dummy write to verify address
Wait (ε) µs
Read verify data
Clear EV bit in FLMCR
Wait (η) µsClear EV bit in FLMCR
Wait (η) µs
Clear SWE bit in FLMCR
Disable WDT
End of erase
*1
Verify data = H'FFFF?
Last address of block?
Erase failure
Clear SWE bit in FLMCR
n > N?
No
No
YES
Yes
Yes
Notes: 1. Preprogramming (setting erase block data to all 0s) is not necessary.
2. The values of x, y, z, α, β, γ, ε, η, and N are shown in section 18.2.5, Flash Memory Characteristics.
3. Verify data is read in 16-bit (word) units. (Byte-unit reading is also possible.)
4. Set only one bit in EBR two or more bits must not be set simultaneously.
5. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn.
Set ESU bit in FLMCR
Wait (y) µs
n ← n + 1
Increment
verify address
No
Re-erase
Figure 15.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)
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15.6 Flash Memory Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
15.6.1 Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted. Hardware protection is reset by settings in the flash memory control register
(FLMCR) and erase block register (EBR). In the case of error protection, the P bit and E bit can be
set, but a transition is not made to program mode or erase mode. (See table 15.8.)
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Table 15.8 Hardware Protection
Function
Item Description Program Erase Verify*1
FWE pin
protection • When a low lev el is inp ut to the FWE
pin, FLMCR and EBR are initialized,
and the program/erase-protected state
is entered.*4
No*2No*3No
Reset/standby
protection • In a reset (including a WDT overflow
reset) and in standby mode, FLM C R
and EBR are initialized, and the
program/erase-protected state is
entered.
• In a reset via the RES pin, the reset
state is not entered unless the RES pin
is held low until oscillation stabilizes
after powering on (The minimum
oscillation stabilization time is 20ms).
In the case of a reset during operation,
hold the RES pin low for at least 20
system clock cycles.*5
No No*3No
Error protection • When a microcomputer operation error
(error generation (FLER=1)) was
detected while flash memory was being
programmed/erased, error protection is
enabled. At this time, the FLMCR and
EBR settings are held, but
programming/erasing is aborted at the
time the error was generated. Error
protection is released only by a reset
via the RES pin or a WDT reset, or in
the hardware standby mode.
No No*3Yes
Notes: 1. Two modes: program-verify and erase-verify.
2. The RAM area that overlapped flash memory is deleted.
3. All blocks bec om e uneras abl e and spec ifi cat ion by blo ck is im pos si ble.
4. For more information, see section 15.9, Notes on Flas h Memory Programming/Erasing.
5. See sections 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory
Programming/Erasing. This LSI requires a minimum reset time during operation of 20
system clocks.
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15.6.2 Software Protection
Software protection can be implemented by setting the RAMS bit in RAM control register
(RAMCR) and erase block register (EBR). Wh en software protection is in effect, setting the P or E
bit in flash memory control register (FLMCR) does not cause a transition to program mode or
erase mode. (See table 15.9.)
Table 15.9 Software Protection
Function
Item Description Program Erase Verify*1
Emulation
protection*2Setting the RAMS bit in RAMCR sets the
program/erase-protected state for all
blocks.
No*2No*3Yes
Block
specification
protection
Erase protection can be set for indi vidu al
blocks by settings in erase block register
(EBR).*4
However, program protection is disabled.
Setting EBR to H'00 places all blocks in the
erase-protected state.
—No Yes
Notes: 1. Two modes: program-verify mode and erase-verify mode.
2. Programming to the RAM area that overlaps flash memory is possible.
3. All blocks become unerasable, and specification by block is impossible.
4. Set H'00 in the EBR bits, except for erase.
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15.6.3 Error Protection
In error protection, an error is detected when this LSI runaway occurs during flash memory
programming/erasing*1, or operation is not performed in accord ance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
If the LSI malfunctions during flash memo ry programming/erasing, the FLER bit*2 is set to 1 in
flash memory status register (FLMSR) and the error protection state is entered. The FLMCR and
EBR settings*3 are retained, but program mode or erase mode is aborted at the point at which the
error occurred. Wh en 1 is set in the FLER bit, transitio n to the program mode or erase mode
cannot be made even by setting the P and E bits in FLMCR. However, PV and EV bit in FLMCR
setting is enabled, and a transition can be made to verify mode.
Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware
standby mode.
Figure 15.13 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is
disabled. For more information, see section 15.6.4, NMI Input Disable Conditions.
2. For a detailed description of the FLER bits setting conditions, see section 15.3.4, Flash
Memory Status Register (FLMSR).
3. Data can b e written to FLMCR and EBR. Ho wever, when transition to the software
standby mode was made in the error protection state, the registers are initialized.
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Memory read enable
Verify-read enable
Programming enable
Erasing enable
RD:
VF:
PR:
ER:
Legend: Memory read disabled
Verify-read disabled
Programming disabled
Erasing disabled
Registers (FLMCR, EBR) initialize state
RD:
VF:
PR:
ER:
INIT:
Error occurrence
P=1 or E=1
P = 0 and E = 0
Error occurrence
(software standby mode)
Reset or hardware standby mode
Reset, hardware standby mode,
or software standby mode
Reset release, hardware standby
mode release, and software
standby mode release
Reset or hardware
standby mode
Reset or hardware
standby mode
Program mode
Erase mode
Memory read verify mode
Reset or standby mode
(hardware protection)
Error protection mode Error protection mode
(software standby mode)
Software
standby mode
Software standby
mode release
RD VF PR ER FLER = 0
RD VF PR ER FLER = 0
RD VF PR ER FLER = 1
RD VF PR ER INIT FLER = 1
RD VF PR ER INIT FLER = 0
Figure 15.13 Flash Memory State Transitions
(When High Lev e l Apply to F W E P i n in Modes 5 and 7 (On-Chip ROM Enabled))
The error protection function is disabled for errors other than the FLER bit set conditions. If
considerable time elapses up to transit to this protection state, the flash memory may already be
damaged. As a result, this function cannot completely protect the flash memory against damage.
Therefore, to prevent such erroneous operation, operation must be carried out correctly in
according with the program/erase algorithms in the state that flash write enable (FWE) is set. In
addition, the operation must be always carried out correctly by supervising microcomputer errors
inside and outside the chip with the watchdog timer, etc. At transition to this protection mo d e , the
flash memory may be erroneously programmed or erased, or its abort may result in incomplete
Section 15 ROM
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programming and erasing. In such cases, always forcibly return (reprogram) by boot mode.
However, overprogramming and overerasing may prevent the boot mode from starting normally.
15.6 .4 NMI Inp ut Disable Condit ions
While flash memory is being programmed/erased and the boot program is executing in the boot
mode (however, period up to branching to on-chip RAM area)*1, NMI input is disabled because
the programming/erasing operations have priority.
This is done to avoid the following operation states:
1. Generation of an NMI input during programming/erasing violates the program/erase
algorithms and normal operation can not longer be assured.
2. Vector-read cannot be carried out normally*2 during NMI exception handling during
programming/erasing and the microcomputer runs away as a result.
3. If an NMI input is generated during boot program execution, the normal boot mode sequence
cannot be executed.
Therefore, this LSI has conditions that exceptionally disable NMI inputs only in the on-board
programming mode. However, this does not assure normal programming/erasing and
microcomputer op eration.
Thus, in the FWE application state, all requests, including NMI, inside and outside the
microcomputer, exception handling, and bus release must be restricted. NMI inputs are also
disabled in the error protection state and the state that holds the P or E bit in FLMCR during flash
memory emulation by RAM.
Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area (H'FEF10
to H'FF2FF). (This branch occurs immediately after user program transfer was
completed.)
Therefore, after branching to RAM area, NMI input is enab led in states other than the
program/erase state. Thus, interrupt requests inside and outside the microcomputer
must be disab led until initial writing by user pr ogr am (writin g of vector table and NMI
processing program, etc.) is completed.
2. In this case, vector read is not perf orm ed normally for the follo wing two reasons:
a. The correct value cannot be read even by reading the flash memory during
programming/erasing. (Value is undefined.)
b. If a value has not yet been written to the NMI vector tab le, NMI exception h a ndlin g
will not be per formed correctly.
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15.7 Flash Memory Emulation by RAM
Erasing and programming the flash memory takes time, which can make it difficult to tune
parameters and other data in real time. In this case, overlapping part (H'FF800 to H'FFBFF) of
RAM onto a small block area of flash memory can be performed to emulate real-time
reprogramming of flash memory. This RAM reassignment is performed using bits 3 to 1 in the
RAM control register (RAMCR).
After the RAM area change, two areas can be accessed: the overlapped flash memory area and the
original RAM area (H'FF800 to H'FFBFF). For a description of the RAMCR and RAM area
setting procedure, see section 15.3.3, RAM Control Register (RAMCR).
Example of real-time emulation of flash memory
An example of RAM area H'FF800 to H'FFBFF overlapping EB2 (H'00800 to H'00BFF) flash
memory area is shown below.
H'00000
H'00800
H'FEF10
H'FFC00
H'FF800
H'FFF0F
H'00BFF
H'00FFF
EB2
area
Flash memory
space
On-chip
RAM area
Block area
*
Overlapping RAM
(Real RAM area)
(Image RAM area)
Procedure:
Part (H'FF800 to H'FFBFF) of RAM
overlaps the area (EB2) needed to carry out
real-time reprogramming.
(Bits 3 to 1 in the RAMCR are set to 1, 1, 0
and the overlap flash memory area (EB2)
is selected.)
Real-time reprogramming is carried out using
the overlapping RAM.
After the reprogramming data is verified, RAM
overlapping is released. (RAMS bits are cleared.)
The data written to H'FF800 to H'FFBFF in RAM
are written to flash memory space.
1.
2.
3.
4.
Note: *When part (H'FF800 to H'FFBFF) of RAM
overlapped a small block area of flash
memory, the overlapped flash memory
area cannot be accessed. This area can
be accessed by releasing overlapping.
H'FFBFF
Figure 15.14 Example of RAM Overlapping Operation
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Notes on use of the RAM emulation function
(1) Notes on flash write enable (FWE) high/low
Care is necessary to prevent erroneous programming/erasing at FWE = high/low, the same as
in the on-board programming mode. To prevent erroneous programming and erasing due to
program runaway, etc., during FWE application, in particular, the watchdog timer should be
set when the P, or E bit is set to 1 in FLMCR, even while the emulation function is be ing u sed .
For more information, see section 15.9, Notes on Flash Memory Programming/Erasing.
(2) NMI input disable conditions
When the P and E bits in FLMCR are set, NMI input is disabled, the same as normal
program/erase even when using the emulation function.
NMI input is cleared when the P and E bits are reset (including watchdog timer reset), in the
standby mode, when a high level is not applied to FWE, and when the SWE bit in FLMCR is 0
in state in which a high level is input to FWE.
15.8 Flash Memory PROM Mode
15.8.1 PROM Mode Setting
This LSI has a PROM mode, besides an on-board programming mode, as a flash memory
program/erase mode. In the PROM mode, a program can be freely written to the on-chip ROM
using a PROM programmer that supports the Renesas Technology 128 kbytes flash memory on-
chip microcomputer device type.
For notes on PROM mode use, see sections 15.8.9, Notes on Memory Programming and 15.9,
Notes on Flash Memory Programming/Erasing.
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15.8.2 Memory Map
Figure 15.15 shows the PROM mode memory map.
This LSI
H'00000
H'1FFFF
H'00000
H'1FFFF
Address in
MCU mode Address in
PROM mode
On-chip ROM
area
Figure 15.15 PROM Mode Memory Map
15.8.3 PROM Mode Operation
Table 15.10 shows how the different operating modes are set when using PROM mode, and table
15.11 lists the commands used in PROM mode. Details of each mode are given below.
• Memory Read Mode
Memory read mode supports byte reads.
• Auto-Program Mode
Auto-program mode supports programming of 128 bytes at a time. Status polling is used to
confirm the end of auto-programming.
• Auto-Erase Mode
Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used
to confirm the end of auto-erasing.
• Status Read Mode
Status polling is used for auto-programming and auto-erasing, and normal termination can be
confirmed by reading the I/O 6 signal. In status read mode, error information is output if an
error occurs.
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Table 15.10 Settings for Each Operating Mode in PR OM Mode
Pin Names*3
Mode FWE CE
CECE
CE OE
OEOE
OE WE
WEWE
WE D0 to D7A0 to A17
Read VCC or 0 L L H Data output Ain
Output disable VCC or 0LHHHi-Z X
Command write VCC or 0 L H L Data input Ain*2
Chip disable*1VCC or 0HXXHi-Z X
Legend:
L: Low level
H: High level
X: Undefined
Hi-Z: High impedance
Notes: For command writes when making a transition to auto-program or auto-erase mode, input
Vcc (V) to FWE.
1. Chip disable is not a standby state; internally, it is an operation state.
2. Ain indicates that there is also address input in auto-program mode.
3. The pin names are those assigned in this LSI PROM mode.
Table 15.11 PROM Mode Commands
1st Cycle 2nd Cycle
Command Name Number
of Cycles Mode Address Data Mode Address Data
Memory read mode 1 Write X H'00 Read RA Dout
Auto-program mode 129 Write X H'40 Write WA Din
Auto-erase mode 2 Write X H'20 Write X H'20
Status read mode 2 Write X H'71 Write X H'71
Legend:
RA: Read address
WA: Program address
Dout: Read data
Din: Program data
Note: In auto-program mode, 129 cycles are required for command writing by a simultaneous
128-byte write.
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Table 15.12 DC Characteristics in Memory Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ±5°C
Item Symbol Min Typ Max Unit Test Conditions
Input high
voltage 07–00, A16–A0VIH 2.2 —Vcc +0.3 V
Input low
voltage 07–00, A16–A0VIL 0.3 —0.8 V
OE, CE, WE VT–1.0 —2.5 VSchmitt trigger
input voltage VT+2.0 —3.5 V
VT+ – VT–0.4 —— V
Output high
voltage 07–00VOH 2.4 —— VI
OH = –200 µA
Output low
voltage 07–00VOL ——0.45 V IOL = 1.6 mA
Input leakage
current 07–00, A16–A0| ILI | ——2µA
VCC current Reading Icc —40 65 mA
Programming Icc —50 85 mA
Erasing Icc —50 85 mA
Note: For the electrical characteristics of the flash memory version, see section 18.2.1, Absolute
Maximum Ratings.
Exceeding the absolute maximum ratings may cause permanent damage to the chip.
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15.8.4 Memory Read Mode
AC Characteristics
Table 15.13 AC Characteristics in Memory Read Mode Transition
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
A16–A0
I/O7–I/O0
OE
WE
Command write
t
ceh
t
ds
t
dh
t
f
t
r
t
nxtc
Note: Data is latched on the rising edge of WE.
t
ces
t
wep
Memory read mode
Address stable
Figure 15.16 Timing Waveform in Memory Read Mode Transition
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Table 15.14 AC Characteristics in Memory Contents Read
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Access tim e tacc —20 µs
CE output delay time tce —150 ns
OE output delay ti me toe —150 ns
Output disable delay time tdf —100 ns
Data output hold time toh 5 — ns
CE
A16–A0
I/O7–I/O0
OE
WE V
IH
V
IL
V
IL
t
acc
t
oh
t
oh
t
acc
Address stable Address stable
Figure 15.17 CE
CECE
CE/OE
OEOE
OE Enable State Read
CE
A16–A0
I/O7–I/O0
V
IH
OE
WE
t
ce
t
acc
t
oe
t
oh
t
oh
t
df
t
ce
t
acc
t
oe
Address stable Address stable
t
df
Figure 15.18 CE
CECE
CE/OE
OEOE
OE Clock Rea d
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 481 of 682
REJ09B0353-0300
Table 15.15 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
WE rise time tr—30 ns
WE fall time tf—30 ns
CE
A16–A0
I/O7–I/O0
OE
WE
Another mode command write
t
ceh
t
ds
t
dh
t
f
t
r
t
nxtc
Note: Do not enable WE and OE simultaneously.
t
ces
t
wep
Memory read mode
Address stable
Figure 15.19 Transition From Memory Read Mode to Another Mode
Section 15 ROM
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15.8.5 Auto-Program Mode
AC Characteristics
Table 15.16 AC Characteristics in Auto-Program Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time twsts 1 — ms
Status polling access time tspa —150 ns
Address setup time tas 0 — ns
Address hold time tah 60 —ns
Memory write time twrite 1 3000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
Write setup time tpns 100 —ns
Write end setup time tpnh 100 —ns
Section 15 ROM
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Address stable
CE
FWE
A16–A0
I/O5–I/O0
I/O6
I/O7
OE
WE
tas tah
tdh
tds
tftr
twep twsts
twrite
tspa
tpns
tpnh
tnxtc tnxtc
tceh
tces
Programming operation
end identification signal
Programming normal
end identification signal
Data transfer
1byte to 128bytes
H'40 H'00
Figure 15.20 Auto-Program Mode Timing Waveforms
Cautions on Use of Auto-Program Mode
• In auto-program mode, 128 bytes are programmed simultaneously. This shou ld be carried out
by executing 128 consecutive byte transfers.
• A 128-byte data transfer is necessary even when programming fewer than 128 by tes. In this
case, H'FF data must be wr itten to the extra addr esses.
• If a value other than an effective address is input, processing will switch to a memory write
operation but a wr ite error will be flagged.
• Memory address transfer is performed in the second cycle (figure 15.20). Do not perform
transfer after the second cy cle.
• Do not perform a command write during a programming operation.
• Perform one auto-programming operation for a 128-byte block for each address.
Characteristics are not guaranteed for two or more programming operations.
• Confirm normal end of auto-programming by checking I/O 6. Alternatively, status read mode
can also be used for this purpose.
Section 15 ROM
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15.8.6 Auto-Erase Mode
AC Characteristics
Table 15.17 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
Status polling start time tests 1 — ms
Status polling access time tspa —150 ns
Memory erase time terase 100 40000 ms
WE rise time tr—30 ns
WE fall time tf—30 ns
Erase setup time tens 100 —ns
Erase end setup time tenh 100 —ns
CE
FWE
A16–A0
I/O5–I/O0
I/O6
I/O7
OE
WE
t
ests
t
erase
t
spa
t
dh
t
ds
tftr
t
wep
t
ens
tenh
t
nxtc
t
nxtc
tceh
tces
Erase end
identification signal
Erase normal and
confirmation signal
H'20 H'20 H'00
Figure 15.21 Auto-Erase Mode Timing Waveforms
Section 15 ROM
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Caution on Use of Erase-Program Mode
• Auto-erase mode supports only entire memory erasing.
• Do not perform a command write during auto-erasing.
• Confirm normal end of auto-erasing by checking I/O 6. Alternatively, status read mode can
also be used for this purpose.
15.8.7 Status Read Mode
AC Characteristics
Table 15.18 AC Characteristics in Status Read Mode
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, Ta = 25°C ± 5°C
Item Symbol Min Max Unit Notes
Command write cycle tnxtc 20 —µs
CE hold time tceh 0 — ns
CE setup time tces 0 — ns
Data hold time tdh 50 —ns
Data setup time tds 50 —ns
Write pulse width twep 70 —ns
OE output delay ti me toe —150 ns
Disable delay time tdf —100 ns
CE output delay time tce —150 ns
WE rise time tr—30 ns
WE fall time tf—30 ns
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 486 of 682
REJ09B0353-0300
CE
A16–A0
I/O7–I/O0
OE
WE
t
dh
t
df
t
ds
tftr
t
wep
t
nxtc
t
nxtc
tftr
t
wep
t
ds
t
dh
t
nxtc
tceh tceh
toe
tces tces
tce
H'71 H'71
Note: I/O3 and I/O2 are undefined.
Figure 15.22 Status Read Mode Timing Waveforms
Table 15.19 Status Read Mode Return Commands
Pin Name I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Attribute Normal
end
identification
Command
error Program-
ming error Erase
error ——Program-
ming or
erase count
exceeded
Effective
address
error
Initial va lu e 0 0 0 0 0 0 0 0
Indications Normal
end: 0
Abnormal
end: 1
Command
error: 1
Otherwise:
0
Program-
ming
error: 1
Otherwise:
0
Erase
error: 1
Otherwise:
0
——Count
exceeded:
1
Otherwise:
0
Effective
address
error: 1
Otherwise:
0
Notes on st atus read mode
After exiting auto-program mode or auto-erase mode, status read mode must be executed without
dropping the power supply.
Immediately after powering on, or once powering off, the return command is undefined.
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 487 of 682
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15.8.8 PROM Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup
period. After the PROM mode setup time, a transition is made to memory read mode.
Table 15.20 Stipulated Transition Times to Command Wait State
Item Symbol Min Max Unit Notes
Standby release (oscillation
settling time) tosc1 20 —ms
PROM mode setup time tbmv 10 —ms
VCC hold time tdwn 0 — ms
V
CC
RES
FWE
Memory read
mode
Command wait
state
Command wait state
Normal/abnormal
end identification
Auto-program mode
Auto-erase mode
t
osc1
t
bmv
t
dwn
Note: Set the FWE input pin low level, except in the auto-program and auto-erase modes.
Figure 15.23 Oscilla t ion Stabilization Time, Bo ot Program Transfer Time
Section 15 ROM
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15.8.9 Notes on Memory Programming
• When programming addresses which have previously been programmed, carry out auto-
erasing before auto-programming (figure 15.24).
• When performing programming using PROM mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-pr ogramming.
Notes: 1. The flash mem ory is initially in the erased state when the device is shipped by Renesas.
For other chips for which the erasure history is unknown, it is recommended that auto-
erasing be executed to check and supplement the initialization (erase) level.
2. In the PROM mode, auto-programming to a 128-byte programming unit block should
be performed only once.
Do not perform ad ditional programming to a p rogrammed 128-byte p rogramming unit
block.
To reprogram, perform auto-programming after auto-erasing.
Reprogram to
programmed address
Auto-erase (chip batch)
Auto-program
End
Figure 15.24 Reprogramming to Programmed Address
15.9 Notes on Flash Memory Programming/Erasing
The following describes notes when using the on-bo ard programming mode, RAM emulation
function, and PROM mode.
(1) Prog r am/erase with the specif ied voltage and timing.
Applied voltages in excess of the rating can permanently damage the device.
Use a PROM writer that supports the Renesas Technology 128 kbytes flash memory on-board
microcomputer device type.
Do not set the PROM writer at the HN28F101. If the PROM writer is set to the HN28F101 by
mistake, a high level can be input to the FWE pin and the LSI can be destroyed.
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 489 of 682
REJ09B0353-0300
(2) Notes on powering on/powering off (See figures 15.25 to 15.27.)
Input a high level to the FWE pin after verifying Vcc. Before turning off Vcc, set the FWE pin
to a low level.
When powering on and powering off the Vcc power supply, fix the FWE pin a low level and
set the flash memory to the hard ware protection mode.
Be sure that the p owering on and powering off timing is satisfied even when the power is
turned off and b a ck on in th e event of a power interruption, etc. If this timing is not satisfied,
microcomputer runaway, etc., may cause overp rogramming or overerasing and the memory
cells may not operate normally.
(3) Notes on FWE pin High/Low switching (See figures 15.25 to 15.27.)
Input FWE in the state microcomputer operation is verified. If the microcomputer does not
satisfy the op e r a tion confirmation state, f ix the FWE pin at a low level to set the protection
mode.
To prevent erroneous programming/erasing of flash memory, note the following in FWE pin
High/Low switching:
•Apply an inpu t to the FWE pin af ter the Vcc voltage has stabilized within the rated voltage.
If an input is app lied to the FWE pin when the micro computer Vcc voltage does not satisfy
the rated voltage, flash memory may be erroneously programmed or erased because the
microcomputer is in the unconfirmed state.
•Apply an inpu t to the FWE pin when the oscillation has stab ilized (after the oscillation
stabilization time) .
When turning on the Vcc power, apply an input to the FWE pin after holding the RES pin
at a low level during the oscillation stabilization time (tosc1=20ms). Do not apply an inp ut to
the FWE pin when oscillation is stopped or unstable.
•In the boot mode, perform FWE pin High/Low switching during reset.
In transition to the boot mode, input FWE = High lev e l an d set MD2 to MD0 while the RES
input is low. At this time, the FWE and MD2 to MD0 inputs must satisfy the mode
programming setup time (tMDS) relative to the reset clear timing. The mode program m ing
setup time is necessar y for RES reset timing even in transition from the boot mode to
another mode.
In reset du r ing operation, the RES pin must be held at a low level for at least 20 system
clocks.
•In the user prog ram mode, FWE = High/Low switching is possible regardless of the RES
input.
FWE input switching is also possible during program execution on flash memory.
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 490 of 682
REJ09B0353-0300
•Apply an input to FWE when the program is not running away.
When applying an input to the FWE pin, the program execution state must be supervised
using a watchdog timer, etc.
•Input low level to the FWE pin when the SWE, ESU, PSU, EV, PV, E, and P bits in
FLMCR have been cleared.
Do not erroneously set the SWE, ESU, PSU, EV, PV, E, and P bits when FWE High/Low.
(4) Do not input a constant high level to the FWE pin.
To prevent erroneous programming/erasing in the event of program runaway, etc., input a high
level to the FWE pin only when programming/erasing flash memory (including flash memory
emulation by RAM). Avoid system configurations that constantly input a high level to the
FWE pin. Handle program runaway, etc. by starting the watchdog timer so that flash memory
is not overprogrammed/overerased even while a high level is input to the FWE pin.
(5) Program/erase the flash memory in accordance with the recommended algorithms.
The recommended algorithms can program/erase the flash memory without applying voltage
stress to the device or sacrificing the reliability of the program data.
When setting the PSU and ESU bits in FLMCR, set the watchdog timer for program runaway,
etc.
(6) Do not set/clear the SWE bit while a program is executing on flash memory.
Before performing flash memory program execution or data read, clear the SWE bit.
If the SWE bit is set, the flash data can be reprogrammed, but flash memory cannot be
accessed for purposes other than verify (verify during programming/erase).
Similarly perform flash memory program execution and data read after clearing the SWE bit
even when using the RAM emulation function with a high level input to the FWE pin.
However, RAM area that overlaps flash memory space can be read/programmed whether the
SWE bit is set o r cleared.
(7) Do not use an interrup t during flash memory programming or erasing.
Since programming/erase operations (including emulation by RAM) have priority when a high
level is input to the FWE pin, disable all interrupt requests, including NMI.
(8) Do not perfo rm ad ditional programming. Reprogram flash memo ry af ter erasing.
With on-board programming, program to 32-byte programming unit blocks one time only.
Program to 128-byte programming unit blocks one time only even in the PROM mode. Erase
all the programming unit blocks before reprogramming.
Bus release must also be disabled.
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 491 of 682
REJ09B0353-0300
(9) Before programming, check that the chip is correctly mounted in th e PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
(10) Do not touch the socket adapter or chip during programming. Touching either of these can
cause contact faults and write errors.
: Flash memory access disabled period
(x: Wait time after SWE setting)*
2
: Flash memory reprogrammable period
(Flash memory program execution and data read, other than verify, are disabled.)
1. Always fix the level by pulling down or pulling up the mode pins (MD
2
to MD
0
)
until powering off, except for mode switching.
2. See section 18.2.5, Flash Memory Characteristics.
Notes:
φ
V
CC
FWE
t
OSC1
Min 0 µs
Min 0 µs
t
MDS
t
MDS
MD
2
to MD
0
*
1
RES
SWE bit
SWE
set SWE
clear
Programming and
erase possible
Wait
time: x
Figure 15.25 Powering On/Off Timing (Boot Mode)
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 492 of 682
REJ09B0353-0300
: Flash memory access disabled period
(x: Wait time after SWE setting)*
2
: Flash memory reprogrammable period
(Flash memory program execution and data read, other than verify, are disabled.)
1. Always fix the level by pulling down or pulling up the mode pins (MD
2
to MD
0
)
except for mode switching.
2. See section 18.2.5, Flash Memory Characteristics.
Notes:
φ
V
CC
FWE
tOSC1
Min 0 µs
tMDS
MD
2
to MD
0
*
1
RES
SWE bit
SWE
set SWE
clear
Programming and
erase possible
Wait
time: x
Figure 15.26 Powering On/Off Timing (User Program Mode)
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 493 of 682
REJ09B0353-0300
: Flash memory access disabled time
(x: Wait time after SWE setting)
*
3
: Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES input
is necessary.
During this switching period (period during which a low level is input to the RES pin), the state of the address
dual port and bus control output signals (AS,RD,WR) changes.
Therefore, do not use these pins as output signals during this switching period.
2. When making a transition from the boot mode to another mode, the mode programming setup time t
MDS
relative
to the RES clear timing is necessary.
3. See section 18.2.5, Flash Memory Characteristics.
Notes:
φ
V
CC
FWE
t
OSC1
Min 0 µs
t
MDS
*
2
t
MDS
t
MDS
t
RESW
MD
2
to MD
0
RES
SWE bit
Mode switching*
1
Mode
switching*
1
Boot mode User
mode User
mode
User program mode User
program
mode
SWE set SWE clear
Programming and
erase possible
Wait
time: x
Programming
and
erase
possible
Programming
and
erase
possible
Wait
time: x Programming and
erase possible
Wait
time: x Wait
time: x
Figure 15.27 Mode Transition Timing
(Example: Boot Mode →
→→
→ User Mode ↔
↔↔
↔ User Program Mode)
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 494 of 682
REJ09B0353-0300
15.10 Mask ROM Overview
15.10.1 Block Diagram
Figure 15.28 shows a block diagram of the ROM.
H'00000
H'00002
H'1FFFE
H'00001
H'00003
H'1FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
On-chip ROM
Even addresses Odd addresses
Figure 15.28 ROM Block Diagram (H8/3039)
Section 15 ROM
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REJ09B0353-0300
15.11 Notes on Ordering Mask ROM Version Chip
When ordering the H8/3039 Group chips with a mask ROM, note the following.
• When ordering through an EPROM, use a 128-kbyte one.
• Fill all the unused addresses with H'FF as shown in figure15.29 to make the ROM data size
128 kbytes for all H8/3039 Group chips, which incorporate different sizes of ROM. This
applies to ordering through an EPROM and through electrical data transfer.
• The flash memory versions only registers for flash memory control (FLMCR, EBR, RAMCR,
and FLMSR) are not provided in the mask ROM versions. Reading the corresponding
addresses in a m a sk ROM version will alway s re turn 1s, and writes to these addresses are
disabled. This must be borne in mind when switching from the flash memory versions to a
mask ROM version.
HD6433039
(ROM: 128 kbytes)
Address:
H'00000–H'1FFFF
H'00000
H'1FFFF
Note: * Program H'FF to all addresses in these areas.
HD6433038
(ROM: 64 kbytes)
Address:
H'00000–H'0FFFF
H'00000
H'1FFFF
Not used*
Not used*
HD6433037
(ROM: 32 kbytes)
Address:
H'00000–H'07FFF
H'00000
H'07FFF
H'08000
H'0FFFF
H'10000
H'1FFFF
Not used*
HD6433036
(ROM: 16 kbytes)
Address:
H'00000–H'03FFF
H'00000
H'03FFF
H'04000
H'1FFFF
Figure 15.29 Mask ROM Addresses a nd Data
Section 15 ROM
Rev.3.00 Mar. 26, 2007 Page 496 of 682
REJ09B0353-0300
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 497 of 682
REJ09B0353-0300
Section 16 Clock Pulse Generator
16.1 Overview
This LSI has a built-in clock pu lse generator (CPG) that gen e r a tes the system clock (φ) and other
internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency divider divides the clock
frequency to generate the system clock (φ). The system clock is output at the φ pin*1 and furnished
as a master clock to prescalers that supply clock signals to the on-chip supporting modules.
Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by
settings in a division control register (DIVCR). Power consumption in the chip is reduced in
almost direct proportion to the frequency division ratio*2.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
setting in the module standby contro l register (MSTCR). For details, see section 17.7,
System Clock Output Disabling Function.
2. The division ratio of the frequency divider can be changed dynamically during
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
φ = EXTAL × n
EXTAL: Frequency of crystal resonator or extern al clock signal
n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 498 of 682
REJ09B0353-0300
16.1.1 Block Diagram
Figure 16.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
CPG
φφ/2 to φ/4096
Oscillator Duty
adjustment
circuit Prescalers
Frequency
divider
Division
control
register
Data bus
Figure 16.1 Block Diagram of Clock Pulse Generator
16.2 Oscillator Circuit
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock
signal.
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 499 of 682
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16.2.1 Connecting a Crystal Resonator
Circuit Configura tion
A crystal resonator can be connected as in the example in figure 16.2. The damping resistance Rd
should be selected according to table 16.1. An AT-cut parallel-resonance crystal should be used.
EXTAL
XTAL
C
L1
C
L2
C = C = 10 pF to 22 pF
L1 L2
Rd
Figure 16.2 Connection of Crystal Resonator (Example)
Table 16.1 Damping Resistance Value (Example)
Frequency (MHz) 2 4 8 10121618
Rd (Ω
ΩΩ
Ω)1 k 500 200 0 0 0 0
Crystal Resonator
Figure 16.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have
the characteristics listed in table 16.2.
XTAL
LRs
C
L
C
O
EXTAL
AT-cut parallel-resonance type
Figure 16.3 Crystal Resonator Equivalent Circuit
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 500 of 682
REJ09B0353-0300
Table 16.2 Crystal Resonator Parameters
Frequency (MHz) 24810121618
Rs max (Ω
ΩΩ
Ω)500 120 80 70 60 50 40
Co max (pF) 7777777
Use a crystal resonator with a frequency equal to the system clock frequency (φ).
Notes on Board Design
When a crystal resonator is connected, the following points should be noted:
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 16. 4.
When the board is designed, the crystal resonator and its load capacitors should be placed as close
as possible to the XTAL and EXTAL pins.
XTAL
EXTAL
C
L2
C
L1
LSI
Avoid Signal A Signal B
Figure 16.4 Example of Incorrect Board Design
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 501 of 682
REJ09B0353-0300
16.2.2 External Clock Input
Circuit Configura tion
An external clock signal can be input as shown in the examples in figure 16.5. In example b, the
clock should be held high in standby mode.
If the XTAL pin is left open, the stray capacitance should not exceed 10 pF.
EXTAL
XTAL
EXTAL
XTAL 74HC04
External clock input
Open
External clock input
a. XTAL pin left open
b. Complementary clock input at XTAL pin
Figure 16.5 External Clock Input (Ex amples)
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 502 of 682
REJ09B0353-0300
External Clock
The external clock frequency should be equal to the system clock frequency ( φ). Table 16.3 and
figure 16.6 indicate the clock timing.
Table 16.3 Clock Timing
VCC =
2.7 V to 5.5 V VCC =
5.0 V ±10%
Item Symbol Min Max Min Max Unit Test Conditions
External clo ck r ise
time tEXr — 10 — 5 ns Figure 16.6
External clo ck f all
time tEXf —10 —5 ns
External clock — 30 70 30 70 % φ ≥ 5 MHz
input duty (a/tcyc)40604060%φ < 5 MHz
φ clock width duty
(b/tcyc)—40604060%
Figure
16.6
tcyc
a
EXTAL
tEXr tEXf
VCC × 0.5
tcyc
b
φVCC × 0.5
Figure 16. 6 External Clock Input Timing
Section 16 Clock Pulse Generator
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REJ09B0353-0300
Table 16.4 and figure 16.7 show the timing for the external clock output stabilization delay time.
The oscillator and duty correction cir cuit have the function of regulating the waveform of the
external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL
pin, internal clock signal output is confirmed after the elapse of the external clock output
stabilization de lay time (tDEXT). As clock signal output is not confirmed during the tDEXT period, the
reset signal should be driven low and the reset state maintained during this time.
Table 16.4 External Clock Output St abilization Dela y Time
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V
Item Symbol Min Max Unit Notes
External clock output stabili zati on
delay time tDEXT*500 —µs Figure 16.7
Note: *tDEXT includes a 10 tcyc RES pulse width (tRESW).
VCC
STBY
EXTAL
φ
RES
tDEXT*
Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW).
2.7 V
VIH
Figure 16.7 External Clock Output St abilization Delay Time
Section 16 Clock Pulse Generator
Rev.3.00 Mar. 26, 2007 Page 504 of 682
REJ09B0353-0300
16.3 Duty Adjustment Circuit
When the oscillato r f requency is 5 MHz or higher , the duty adjustment circuit adjusts the duty
cycle of the clock sig nal from the oscillator to g enerate the system clock (φ).
16.4 Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
16.5 Frequency Divider
The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
16.5.1 Register Configuration
Table 16.5 summarizes the frequency division register.
Table 16.5 Frequency Division Register
Address*Name Abbreviation R/W Initial Value
H'FF5D Division control register DIVCR R/W H'FC
Note: *The lower 16 bits of the address are shown.
Section 16 Clock Pulse Generator
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16.5.2 Division Control Register (DIVCR)
DIVCR is an 8- bit readable/writable register that selects the division ratio of the frequency
divider.
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
DIV0
0
R/W
2
—
1
—
1
DIV1
0
R/W
Reserved bits Divide bits 1 and 0
These bits select the
frequency division ratio
DIVCR is initialized to H'FC by a reset and in hardware standby m ode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: These bits cannot be modified and are always read as 1.
Bits 1 and 0—Divide (DIV1 and DIV0): These bits select the frequency division ratio, as
follows.
Bit 1
DIV1 Bit 0
DIV0 Frequency Division Ratio
0 0 1/1 (Initial val ue)
011/2
101/4
111/8
Section 16 Clock Pulse Generator
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16.5.3 Usage Notes
The DIVCR setting changes the φ frequency, so note the following points.
• Select a frequency division ratio that stays within the assured operation range specified for the
clock cycle time tcyc in th e AC electrical characteristics. Note that φMIN = 1 MHz. Avoid settings
that give system clock frequencies less than 1 MHz.
All on-chip module operations are based on φ. Note that the timing of timer operation s, serial
communication, and other time-dependent processing differs before and after any change in the
division ratio. The waiting time for exit from software standby mode also changes when the
division ra tio is changed. For details, see sectio n 17.4.3, Selectio n of Oscillator Waiting Time af ter
Exit from Software Standby Mode
Section 17 Power-Down State
Rev.3.00 Mar. 26, 2007 Page 507 of 682
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Section 17 Power-Down State
17.1 Overview
This LSI has a power-down state that greatly reduces power consumption by halting CPU
functions, and a module standby function that reduces power consumption by selectively halting
on-chip modules. The power-down state includes the following three modes:
• Sleep mode
• Software standby mode
• Hardware standby mode
The module standby function can halt on-chip supporting modules independently of the power-
down state. The modules that can be halted are the ITU, SCI0, SCI1, and A/D converter.
Table 17.1 indicates the method s of entering and exiting these power-down modes and the status
of the CPU and on -chip supporting modules in each mode.
Section 17 Power-Down State
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Table 17.1 Power-Down State and Module Standby F unction
State
Entering
Conditions CPU
Registers
Supporting
Modules
Exiting
Methods
Mode Clock CPU ITU SCI0 SCI1 A/D RAM
Sleep SLEEP instruc- Active Halted Held Active Active Active Active Active Held • Interrupt
mode tion executed •
RES
while SSBY = 0 • STBY
in SYSCR
Software SLEEP instruc- Halted Halted Held Halted Halted Halted Halted Halted Held • NMI
standby tion executed and and and and and • IRQ0to IRQ1
mode while SSBY = 1 reset reset reset reset reset •
RES
in SYSCR • STBY
Hardware Low input at Halted Halted Undeter Halted Halted Halted Halted Halted Held*2•STBY
standby STBY pin mined and and and and and • RES
mode reset reset reset reset reset
Module Corresponding Active Active — Halted*1Halted*1Halted*1Halted*1Active • STBY
standby
function bit set to 1 in and and and and •
RES
MSTCR reset reset reset reset • Clear MSTCR
bit to 0*3
φ clock
output
φoutput
High
output
High
impedance
High
impedance*1
—
I/O
Ports
Held
Held
High
impedance
Notes: 1. State in which the corresponding MSTCR bit was set to 1. For details see section 17.2.2, Module Standby Control Register (MSTCR).
2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode.
3. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first
clear the MSTCR bit to 0, then set up the module registers again.
Legend:
SYSCR: System control register
SSBY: Software standby bit
MSTCR: Module standby control register
—
Section 17 Power-Down State
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17.2 Register Configuration
This LSI has a system control register (SYSCR) that controls the power-down state, and a module
standby control register (MSTCR) that controls the module standby function. Table 17.2
summarizes this register.
Table 17.2 Register Configuration
Address*Name Abbreviation R/W Initial Value
H'FFF2 System control register SYSCR R/W H'0B
H'FF5E Module standby contro l
register MSTCR R/W H'40
Note: *Lower 16 bits of the address .
17.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
Enables transition to
software standby mode
RAM enable
Standby timer select 2 to 0
These bits select the
waiting time at exit from
software standby mode
User bit enable
NMI edge select
Reserved bit
SYSCR is an 8-bit readable/writable register. Bit 7 ( SSBY) and bits 6 to 4 (STS2 to STS0) control
the power-down state. For information on the other SYSCR bits, see section 3.3, System Control
Register (SYSCR).
Section 17 Power-Down State
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Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0 .
Bit 7
SSBY Description
0 SLEEP instruction causes transition to sleep mode (Initial value)
1 SLEEP instruction causes transition to software standby mode
Bits 6 to 4 —St andby Timer Select (STS2 to STS0) : These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock fr eque ncy so that the waiting time (for th e clock to stabilize) will be at least 7 ms. See
table 17.3. If an external clock is used, any setting is per mitted.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Waiting time = 8192 states (Initial value)
1 Waiting time = 16384 states
1 0 Waiting time = 32768 states
1 Waiting time = 65536 states
1 0 0 Waiting time = 131072 states
0 1 Waiting time = 1024 states
1 — Illegal setting
Section 17 Power-Down State
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17.2.2 Module Standby Control Register (MSTCR)
MSTCR is an 8-bit readable/writable register that controls output of the system clock (φ). It also
controls the module standby function, which places individual on-chip supporting modules in the
standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter
modules.
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
—
1
—
5
MSTOP5
0
R/W
4
MSTOP4
0
R/W
3
MSTOP3
0
R/W
0
MSTOP0
0
R/W
2
—
0
—
1
—
0
—
φ clock stop
Enables or disables
output of the system clock
Module standby 5 to 3, and 0
These bits select modules
to be placed in standby
Reserved bit Reserved bit
MSTCR is initialized to H'40 by a reset and in hardware standby mode . I t is not initialized in
software standby mode.
Bit 7—φ
φφ
φ Clock Stop (PSTOP): Enables or disables output of the system clock (φ).
Bit 7
PSTOP Description
0 System clock outp ut is enab led (Initial val ue)
1 System clock outp ut is disa bled
Bit 6—Reserved: This bit cannot be modified and is always read as 1.
Bit 5—Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby.
Bit 5
MSTOP5 Description
0 ITU operates norma lly (Initial value)
1 ITU is in standby state
Section 17 Power-Down State
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Bit 4—Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby.
Bit 4
MSTOP4 Description
0 SCI0 operates normally (Initial value)
1 SCI0 is in standby state
Bit 3—Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby.
Bit 3
MSTOP3 Description
0 SCI1 operates normally (Initial value)
1 SCI1 is in standby state
Bits 2 to 1—Reserved: Bits 2 to 1 are r e ser ved.
Bit 0—Module Standby 0 (MSTOP0): Selects whether to place the A/D converter in standby.
Bit 0
MSTOP0 Description
0 A/D converter operates normally (Initial value)
1 A/D converter is in standby state
Section 17 Power-Down State
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17.3 Sleep Mode
17.3.1 Transition to Sleep Mode
When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the
SLEEP instruction causes a transition from the program execution state to sleep mode.
Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal
registers are retained. The on-chip supporting modules do not halt in sleep mode. On-chip
supporting modules which have been placed in standby by the module standby function, however,
remain ha lted.
17.3.2 Exit from Sleep Mode
Sleep mode is exited by an in terrupt, or by input at the RES or STBY pin.
Exit by Interrupt: An interru pt terminates sleep mode and cau ses a transition to th e interr upt
exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting
module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by
an interrupt other then NMI if the interrupt is ma sked by interrupt prior ity settings (IPR) and the
settings o f the I and UI bits in CCR.
Exit by RES
RESRES
RES Input: Low input at th e RES pin exits from sleep mode to the reset state.
Exit by STBY
STBYSTBY
STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby
mode.
Section 17 Power-Down State
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17.4 Software Standby Mode
17.4.1 Transition to Software Standby Mode
To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in
SYSCR.
In software standby mode, current dissipation is reduced to an extremely low level because the
CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset
and halted. As long as the specified voltage is supplied, however, CPU register contents and on-
chip RAM data are retained. The settings of the I/O ports are also held.
17.4.2 Exit from So ftware Standby Mode
Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or
by input at the RES or STBY pin.
Exit by Interrupt: When an NMI, IRQ0, or IRQ1 interrupt request signal is received, the clock
oscillator beg in s o perating. After the oscillator settling time selected by bits STS2 to STS0 in
SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and
interrupt exception handling begins. Software standby mode is not exited if the interrupt enable
bits of interrupts IRQ0, and IRQ1 are cleared to 0, or if these interrupts are masked in the CPU.
Exit by RES
RESRES
RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are
supplied im mediately to the entire chip. The RES signal must be held low long enough for the
clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling.
Exit by STBY
STBYSTBY
STBY Input: Low input at the STBY pin causes a transition to hardware standby mode.
Section 17 Power-Down State
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17.4.3 Selection of Oscilla t or Waiting Time after Exit from Software Standby Mode
Bits STS2 to STS0 in SYSCR, and its DIV1 and DIV0 in DIVCR should be set as follows.
Crystal Resonator
Set STS2 to STS0, and DIV1 and DIV0 so that the waiting time (for the clock to stabilize) is at
least 7 ms. Table 17.3 indicates the waiting times that are selected by STS2 to STS0, and DIV1
and DIV0 settings at various system clock frequencies.
External Clock
Any value may be set.
Table 17.3 Clock Frequency and Waiting Time for Cloc k to Settle
DIV1 DIV0 STS2 STS1 STS0 Waiting
Time 18 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz 1 MHz Unit
0 0 0 0 0 8192 states 0.46 0.51 0.65 0.8 1.0 1.3 2.0 4.1 8.2 ms
0 0 1 16384 states 0.91 1.0 1.3 1.6 2.0 2.7 4.1 8.2 16.4
0 1 0 32768 states 1.8 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8
0 1 1 65536 states 3.6 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5
1 0 0 131072 states 7.3 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1
1 0 1 1024 states 0.057 0.064 0.085 0.10 0.13 0.17 0.26 0.51 1.0
11—
0 1 0 0 0 8192 states 0.91 1.02 1.4 1.6 2.0 2.7 4.1 8.2 16.4 ms
0 0 1 16384 states 1.8 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8
0 1 0 32768 states 3.6 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5
0 1 1 65536 states 7.3 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1
1 0 0 131072 states 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1
1 0 1 1024 states 0.11 0.13 0.17 0.20 0.26 0.34 0.51 1.0 2.0
11—Illegal setting
Illegal setting
Illegal setting
Illegal setting
1 0 0 0 0 8192 states 1.8 2.0 2.7 3.3 4.1 5.5 8.2 16.4 32.8 ms
0 0 1 16384 states 3.6 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5
0 1 0 32768 states 7.3 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1
0 1 1 65536 states 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1
1 0 0 131072 states 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3
1 0 1 1024 states 0.23 0.26 0.34 0.41 0.51 0.68 1.02 2.0 4.1
11—
1 1 0 0 0 8192 states 3.6 4.1 5.5 6.6 8.2 10.9 16.4 32.8 65.5 ms
0 0 1 16384 states 7.3 8.2 10.9 13.1 16.4 21.8 32.8 65.5 131.1
0 1 0 32768 states 14.6 16.4 21.8 26.2 32.8 43.7 65.5 131.1 262.1
0 1 1 65536 states 29.1 32.8 43.7 52.4 65.5 87.4 131.1 262.1 524.3
1 0 0 131072 states 58.3 65.5 87.4 104.9 131.1 174.8 262.1 524.3 1048.6
1 0 1 1024 states 0.46 0.51 0.68 0.82 1.0 1.4 2.0 4.1 8.2
11—
: Recommended setting
Section 17 Power-Down State
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17.4.4 Sample Application of Software Standby Mode
Figure 17.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 ( selectin g the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG = 1
SSBY = 1
Software standby
mode (power-
down state)
Oscillator
settling time
(t
osc2
)
SLEEP
instruction
NMI exception
handling
Clock
oscillator
Figure 17.1 NMI Timing for So f tware Standby Mode (Example)
17.4.5 Usage Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output cu r rent is not reduced.
Section 17 Power-Down State
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17.5 Hardware Standby Mode
17.5.1 Transition to Hardware Sta ndby Mode
Regardless of its current state, the chip en ters hardware standby mode whenever the STBY pin
goes low. Hardware standby mode reduces power consumption drastically by halting all functions
of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As
long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the
high-impedance state.
Clear the RAME bit to 0 in SYSCR befo r e STBY goes low to retain on-chip RAM data.
The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode.
17.5.2 Exit from Hardware Standby Mode
Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when
STBY goes high, the clock oscillator starts running. RES should be held low long enough for the
clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a
transition to the program execution state.
Section 17 Power-Down State
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17.5.3 Timing for H ardware Standby Mode
Figure 17.2 shows the timing relationships for hardware standby mode. To enter hardware standby
mode, first drive RES low, then driv e STBY low. To exit hardware standby mode, first drive
STBY high , wait f or the clock to settle, then brin g RES f r om low to high.
RES
STBY
Clock
oscillator
Oscillator
settling time
Reset
exception
handling
Figure 17.2 Hardware Standby Mode Timing
Section 17 Power-Down State
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17.6 Module Standby Function
17.6.1 Module Standby Timing
The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0,
SCI1, and A/D converter) independently of the power-down state. This standby function is
controlled by b its MSTOP5 to MSTOP3 and MSTOP0 in MSTCR. When one of these bits is set
to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning
of the next bus cycle af ter the MSTCR write cycle.
17.6.2 Read/Write in Module Standby
When an on-chip supporting module is in module standby, read/write access to its registers is
disabled. Read access always results in H'FF data. Write access is ignored.
17.6.3 Usage Notes
When using the module standby function, note the following points.
Cancellation o f Interrupt Handling: When an on-chip supporting module is placed in standby
by the module standby function, its registers are initialized, including registers with interrupt
request flag s. Consequently, if an interr upt occurs just before the MSTOP bit is set to 1, the
interrupt will n ot be recognized. The interrupt source will not be held pending.
Pin States: Pins used by an on-chip supporting module lose their module functions when the
module is placed in module standby. What happens after that depends on the particular pin. For
details, see section 7, I/O Ports. Pins that change from the input to the output state require special
care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data
function and becomes a generic I/O pin. If its data direction bit is set to 1, the pin becomes a data
output pin, and its output may collide with external serial data. Data collisions should be prevented
by clearing the data direction bit to 0 or taking other appropriate action.
Register Resetting: When an on-chip supporting module is halted by the module standby
function , all its reg ister s ar e initialized. To restart th e module, after its MSTOP bit is cleared to 0,
its registers mu st be set up again . It is not possible to wr ite to the registers while the MSTOP bit is
set to 1.
Section 17 Power-Down State
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17.7 System Clock Output Disabling Function
Output of the system clock (φ) can be controlled by the PSTOP bit in MSTCR. When the PSTOP
bit is set to 1, output of the system clock halts and th e φ pin is placed in the high-impedance state.
Figure 17.3 shows the timing of the stopping and starting of system clock output. When the
PSTOP bit is cleared to 0, output of the system clock is enabled. Table 17 .4 indicates the state of
the φ pin in various operating states.
T1 T2
(PSTOP = 1)
T3 T1 T2
(PSTOP = 0)
MSTCR write cycle MSTCR write cycle
High impedance
φ pin
T3
Figure 17. 3 Starting and Stopping of System Clo c k Output
Table 17.4 φ
φφ
φ Pin State in Various Operating States
Operating State PSTOP = 0 PSTOP = 1
Hardware standby High impedance High impedance
Software standby Always high High impedance
Sleep mode System clo ck outp u t High impedance
Normal operatio n System clo ck outp ut High impedance
Section 18 Electrical Characteristics
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Section 18 Electrical Characteristics
18.1 Electrical Characteristics of Mask ROM Version
18.1.1 Absolute Maximum Ratings
Table 18.1 lists the ab solute maximum ratings.
Table 18.1 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage VCC –0.3 to +7.0 V
Input voltage (except port 7)*Vin –0.3 to VCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute ma ximum ratings are exceeded.
Note: *12 V must not be applied to any pin, as this will cause permanent damage to the chip.
Section 18 Electrical Characteristics
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18.1.2 DC Characteristics
Table 18.2 lists the DC characteristics. Table 18.3 lists the permissible output currents.
Table 18.2 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
Port A, VT–1.0 — — V
P80 to P81,V
T+——V
CC × 0.7 V
Schmitt
trigger input
voltages PB0 to PB3VT+ – VT–0.4 — — V
Input high
voltage RES, STBY,
NMI, MD2,
MD1, MD0
VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
Port 7 2.0 — AVCC +0.3 V
Ports 1, 2, 3, 5,
6, 9, PB4, PB5,
PB7
2.0 — VCC +0.3 V
Input low
voltage RES, STBY,
MD2, MD1, MD0
VIL –0.3 — 0.5 V
NMI, EXTAL,
ports 1, 2, 3, 5,
6, 7, 9, PB4,
PB5, PB7
–0.3 — 0.8 V
VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage All output pins
(except RESO)3.5 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL ——0.4VI
OL = 1.6 mA
Ports 1, 2, 5, B — — 1.0 V IOL = 10 mA
RESO ——0.4VI
OL = 2.6 mA
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 523 of 682
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Item Symbol Min Typ Max Unit Test Conditions
Input
leakage
current
STBY, NMI,
RES, MD2, MD1,
MD0
|Iin|——1.0µAV
in = 0.5 to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 to
AVCC –0.5 V
Ports 1, 2, 3, 5,
6, 8 to B |ITSI|— —1.0 µAV
in = 0.5 to
VCC –0.5 V
Three-state
leakage
current
(off state) RESO — — 10.0 µA
Input
pull-up MOS
current
Ports 2, 5 –Ip50 — 300 µA Vin = 0 V
NMI, RES Cin — — 50 pFInput
capacitance All input pins
except NMI and
RES
——20
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Normal
operation ICC — 50 70 mA f = 18 MHz
Sleep mode — 35 50 f = 18 MHz
Standby mode*3— 0.01 5.0 µA Ta ≤ 50°C
Current
dissipation*2
— — 20.0 50°C < Ta
During A/D
conversion AICC —1.72.8mAAnalog
power
supply
current Idle — 0.02 10.0 µA
RAM standby voltage VRAM 2.0 — — V
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 524 of 682
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Table 18.2 DC Characteristics (2)
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.2 — — V
VT+——V
CC × 0.7 V
Schmitt
trigger input
voltages
Port A,
P80 to P81,
PB0 to PB3VT+ – VT–VCC × 0.04 — — V
Input high
voltage RES, STBY,
NMI, MD2, MD1,
MD0
VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Ports 1, 2, 3, 5,
6, 9, PB4, PB5,
PB7
VCC × 0.7 — VCC +0.3 V
Input low
voltage RES, STBY,
MD2, MD1, MD0
VIL –0.3 — VCC × 0.1 V
–0.3 — VCC × 0.2 V VCC < 4.0 VNMI, EXTAL,
ports 1, 2, 3,
5, 6, 7, 9,
PB4, PB5, PB7
0.8 V VCC =
4.0 V to 5.5 V
VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage All output pins
(except RESO)VCC –1.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL ——0.4VI
OL = 1.0 mA
Ports 1, 2, 5, B — — 1.0 V VCC ≤ 4 V,
IOL = 5 mA,
4 V < VCC ≤ 5.5 V,
IOL = 10 mA
RESO ——0.4VI
OL = 1.6 mA
Input
leakage
current
STBY, NMI,
RES, MD2, MD1,
MD0
|Iin|— —1.0µAV
in = 0.5 V to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 V to
AVCC –0.5 V
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 525 of 682
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Item Symbol Min Typ Max Unit Test Conditions
Ports 1, 2, 3, 5,
6, 8, 9, A, B |ITSI|— —1.0 µAThree-state
leakage
current
(off state) RESO — — 10.0 µA
Vin = 0.5 V to
VCC –0.5 V
Input
pull-up MOS
current
Ports 2, 5 –Ip10 — 300 µA VCC =
2.7 V to 5.5 V,
Vin = 0 V
NMI, RES Cin — — 50 pFInput
capacitance All input pins
except NMI
and RES
——20
Vin = 0 V,
f = 1 MHz ,
Ta = 25°C
Current
dissipation*2Normal
operation ICC*4—12
(3.0 V) 33.8
(5.5 V) mA f = 8 MHz
Sleep mode — 8
(3.0 V) 25.0
(5.5 V) mA f = 8 MHz
Standby mode*3— 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
AICC —1.32.5mAAV
CC = 3.0 VDuring A/D
conversion —1.72.8mAAV
CC = 5.0 V
Analog
power
supply
current Idle — 0.02 10.0 µA
RAM standby voltage VRAM 2.0 — — V
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up MOS transistors in the off state.
3. The values are for VRAM ≤ VCC < 2.7 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
4. ICC depends on VCC and f as follows:
ICC max = 3.0 (mA) + 0.7 (mA/MHz · V) × VCC × f [normal mode]
ICC max = 3.0 (mA) + 0.5 (mA/MHz · V) × VCC × f [sleep mode]
Section 18 Electrical Characteristics
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Table 18.2 DC Characteristics (3)
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.2 — — V
VT+——V
CC × 0.7 V
Schmitt
trigger input
voltages
Port A,
P80 to P81,
PB0 to PB3VT+ – VT–VCC × 0.04 — — V
Input high
voltage RES, STBY,
NMI, MD2, MD1,
MD0
VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
Port 7 VCC × 0.7 — AVCC +0.3 V
Ports 1, 2, 3, 5,
6, 9, PB4, PB5,
PB7
VCC × 0.7 — VCC +0.3 V
Input low
voltage RES, STBY,
MD2, MD1, MD0
VIL –0.3 — VCC × 0.1 V
–0.3 — VCC × 0.2 V VCC < 4.0 VNMI, EXTAL,
ports 1, 2, 3, 5,
6, 7, 9, PB4,
PB5, PB7
0.8 V VCC = 4.0 V to
5.5 V
VOH VCC –0.5 — — V IOH = –200 µAOutput high
voltage All output pins
(except RESO)VCC –1.0 — — V IOH = –1 mA
Output low
voltage All output pins
(except RESO)VOL ——0.4VI
OL = 1.0 mA
Ports 1, 2, 5, B — — 1.0 V VCC ≤ 4 V,
IOL = 5 mA,
4 V < VCC ≤ 5.5 V,
IOL = 10 mA
RESO ——0.4VI
OL = 1.6 mA
Input
leakage
current
STBY, NMI,
RES, MD2, MD1,
MD0
|Iin|— —1.0µAV
in = 0.5 V to
VCC –0.5 V
Port 7 — — 1.0 µA Vin = 0.5 V to
AVCC –0.5 V
Section 18 Electrical Characteristics
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Item Symbol Min Typ Max Unit Test Conditions
Ports 1, 2, 3, 5,
6, 8 to B |ITSI|— —1.0 µAV
in = 0.5 V to
VCC –0.5 V
Three-state
leakage
current
(off state) RESO — — 10.0 µA
Input
pull-up MOS
current
Ports 2, 5 –Ip10 — 300 µA VCC =
3.0 V to 5.5 V,
Vin = 0 V
NMI, RES Cin — — 50 pFInput
capacitance All input pins
except NMI
and RES
——20
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Current
dissipation*2Normal
operation ICC*4—15
(3.0 V) 41.5
(5.5 V) mA f = 10 MHz
Sleep mode — 10
(3.0 V) 30.5
(5.5 V) mA f = 10 MHz
Standby mode*3— 0.01 5.0 µA Ta ≤ 50°C
— — 20.0 µA 50°C < Ta
AICC —1.32.5mAAV
CC = 3.0 VDuring A/D
conversion —1.7—mAAV
CC = 5.0 V
Analog
power
supply
current Idle — 0.02 10.0 µA
RAM standby voltage VRAM 2.0 — — V
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
4. ICC depends on VCC and f as follows:
ICC max = 3.0 (mA) + 0.7 (mA/MHz · V) × VCC × f [normal mode]
ICC max = 3.0 (mA) + 0.5 (mA/MHz · V) × VCC × f [sleep mode]
Section 18 Electrical Characteristics
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Table 18.3 Permissible Output Currents
Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Ports 1, 2, 5 and B — — 10 mA
Permissible output
low current (per pin) Other output pins
IOL ——2.0 mA
Total of 27 pins including
ports 1, 2, 5 and B ——80 mA
Total of 23 pins, including
ports 8, 9, A and B ——75*2/65*1mA
Permissible output
low current (total)
Total of all output pins,
including the above
ΣIOL
— — 120 mA
Permissible output
high current (per pin) All output pins IOH ——2.0 mA
Permissible output
high current (total) Total of all output pins ΣIOH ——40 mA
Notes: To protect chip reliability, do not exceed the output current values in table 18.3.
When driving a Darlington pair or LED, alwa ys ins ert a curr ent-limiting resistor in the output
line, as shown in figures 18.1 and 18.2.
1. The value is for conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V
2. The value is for conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V
Section 18 Electrical Characteristics
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LSI
Port 2 kΩ
Darlington pair
Figure 18.1 Darlington Pair Drive Circuit (Example)
LSI
Ports
LED
600 Ω
Figure 18.2 LED Drive Circuit (Example)
Section 18 Electrical Characteristics
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18.1.3 AC Characteristics
Bus timing parameters are listed in table 18.4. Control signal timing p arameters are listed in table
18.5. Timing parameters of the on-chip supporting modules are listed in table 18.6.
Table 18.4 Bus Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 125 500 100 500 55.5 500 ns
Clock low puls e wi dth tCL 40 —30 —17 —Figure 18.7,
Figure 18.8
Clock high pulse width tCH 40 —30 —17 —
Clock rise time tCr —20 —15 —10
Clock fall time tCf —20 —15 —10
Address delay tim e tAD —60 —50 —25
Address hold time tAH 25 —20 —10 —
Address strobe delay time tASD —60 —40 —25
Write strobe delay time tWSD —60 —50 —25
Strobe delay time tSD —60 —50 —25
Write data strobe pulse wi dt h 1 t WSW1*85 —60 —32 —
Write data strobe pulse wi dt h 2 t WSW2*150 —110 —62 —
Address setup time 1 tAS1 20 —15 —10 —
Address setup time 2 tAS2 80 —65 —38 —
Read data setup time tRDS 50 —35 —15 —
Read data hold time tRDH 0 — 0 — 0 —
Section 18 Electrical Characteristics
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Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
Write data delay time tWDD —75 —75 —55 ns
Write data setup time 1 tWDS1 60 —40 —10 —Figure 18.7,
Figure 18.8
Write data setup time 2 tWDS2 5—–10 —–10 —
Write data hold time tWDH 25 —20 —20 —
Read data access time 1 tACC1*—120 —100 —50
Read data access time 2 tACC2*—240 —200 —105
Read data access time 3 tACC3*—70 —50 —20
Read data access time 4 tACC4*—180 —150 —80
Precharge time tPCH*85 —60 —40 —
Wait setu p time tWTS 40 —40 —25 —Figure 18.9
Wait hold time tWTH 10 —10 — 5 —
Note: *For Condition A, the following times depend on the clock cycle time as shown below.
tACC1 = 1.5 × tcyc –68 (ns) tWSW1 = 1.0 × tcyc –40 (ns)
tACC2 = 2.5 × tcyc –73 (ns) tWSW2 = 1.5 × tcyc –38 (ns)
tACC3 = 1.0 × tcyc –55 (ns) tPCH = 1.0 × tcyc –40 (ns)
tACC4 = 2.0 × tcyc –70 (ns)
For Condition B, the following times depend on the clock cycle time as shown below.
tACC1 = 1.5 × tcyc –50 (ns) tWSW1 = 1.0 × tcyc –40 (ns)
tACC2 = 2.5 × tcyc –50 (ns) tWSW2 = 1.5 × tcyc –40 (ns)
tACC3 = 1.0 × tcyc –50 (ns) tPCH = 1.0 × tcyc –40 (ns)
tACC4 = 2.0 × tcyc –50 (ns)
For Condition C, the following times depend on the clock cycle time as shown below.
tACC1 = 1.5 × tcyc –34 (ns) tWSW1 = 1.0 × tcyc –24 (ns)
tACC2 = 2.5 × tcyc –34 (ns) tWSW2 = 1.5 × tcyc –22 (ns)
tACC3 = 1.0 × tcyc –36 (ns) tPCH = 1.0 × tcyc –21 (ns)
tACC4 = 2.0 × tcyc –31 (ns)
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 532 of 682
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Table 18.5 Control Signal Timing
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B Condition C
8 MHz 10 M Hz 18 MHz
Item Symbol M in Max Min Max Min Max Unit Test Conditions
RES setup time tRESS 200 —200 —200 —ns Fi gure 18. 10
RES pulse width t RESW 10 —10 —10 —tcyc
Mode programming
setup time (MD0, MD1,
MD2)
tMDS 200 —200 —200 —ns
RESO output delay
time tRESD —100 —100 —100 ns Figure 18.11
RESO output pulse
width tRESOW 132 —132 —132 —tcyc
NMI setu p time
(NMI, IRQ0, IRQ1,
IRQ4, IRQ5)
tNMIS 200 —200 —150 —ns Figure 18.12
NMI hold time
(NMI, IRQ0, IRQ1,
IRQ4, IRQ5)
tNMIH 10 —10 —10 —
Interrupt puls e wi dth
(NMI, IRQ1, IRQ0
when exiting soft ware
standby mode)
tNMIW 200 —200 —200 —
Clock osc i llator
settling tim e at reset
(crystal)
tOSC1 20 —20 —20 —ms Fi gure 18. 13
Clock osc i llator
settling time in
software standby
(crystal)
tOSC2 8 — 8 — 7 — m s Figure 17.1
Section 18 Electrical Characteristics
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Table 18. 6 Timing of On-C hip Supporting Modules
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
ITU Timer output delay
time tTOCD —100 —100 —100 ns Figure 18.15
Timer input setup
time tTICS 50 —50 —50 —
Timer clock input
setup time tTCKS 50 —50 —50 —Figure 18. 16
Single
edge tTCKWH 1.5 —1.5 —1.5 — tcyc
Timer
clock
pulse
width Both
edges tTCKWL 2.5 —2.5 —2.5 —
SCI Asynchro-
nous tScyc 4 — 4 — 4 — Figure 18.17Input
clock
cycle Synchro-
nous 6 — 6 — 6 —
Input clock rise time tSCKr —1.5 —1.5 —1.5
Input clock fall time tSCKf —1.5 —1.5 —1.5
Input clock pulse
width tSCKW 0.4 0.6 0.4 0.6 0.4 0.6 tScyc
Section 18 Electrical Characteristics
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Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Symbol Min Max Min Max Min Max Unit Test
Conditions
SCI T ransmit data delay
time tTXD —100 —100 —100 ns Figure 18.18
Receive data set up
time (sync hronous) tRXS 100 —100 —100 —
Receive data hold
time (sync hronous
clock input)
tRXH 100 —100 —100 —
Receive data hold
time (sync hronous
clock output)
0 — 0 — 0 —
Output data delay
time tPWD —100 —100 —100 ns Figure 18.14Ports
and
TPC Input data setup time tPRS 50 —50 —50 —
Input data hold time tPRH 50 —50 —50 —
CR
H
5 V
R
L
This LSI
output pin
C = 90 pF: ports 1, 2, 3, 5, 6, 8, φ
C = 30 pF: ports 9, A, B
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
R = 2.4 k
R = 12 k
L
H
Ω
Ω
Figure 18.3 Output Load Circuit
Section 18 Electrical Characteristics
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REJ09B0353-0300
18.1.4 A/D Conversion Characteristics
Table 18.7 lists the A/D conversion characteristics.
Table 18.7 A/D Converter Characteristics
Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
8 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition C: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B Condition C
8 MHz 10 MHz 18 MHz
Item Min Typ Max Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 10 10 10 bits
Conversion time ——16.8 ——13.4 ——7.5 µs
Analog input
capacitance ——20 ——20 ——20 pF
——10*1——10*1——10*4kΩPermissible signal-
source impedance ——5*2——5*3——5*5
Nonlinearity error ——±7.5 ——±7.5 ——±3.5 LSB
Offset error ——±7.5 ——±7.5 ——±3.5 LSB
Full-scale error ——±7.5 ——±7.5 ——±3.5 LSB
Quantization error ——±0.5 ——±0.5 ——±0.5 LSB
Absolute accuracy ——±8.0 ——±8.0 ——±4.0 LSB
Notes: 1. The value is for 4.0 V ≤ AVCC ≤ 5.5 V.
2. The value is for 2.7 V ≤ AVCC < 4.0 V.
3. The value is for 3.0 V ≤ AVCC < 4.0 V.
4. The value is for φ ≤ 12 MHz.
5. The value is for φ > 12 MHz.
Section 18 Electrical Characteristics
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18.2 Electrical Characteristics of Flash Memory Version
18.2.1 Absolute Maximum Ratings
Table 18.8 lists the ab solute maximum ratings.
Table 18.8 Absolute Maximum Ratings
Item Symbol Value Unit
Power supply voltage VCC –0.3 to +7.0 V
Input voltage (except port 7)*1Vin –0.3 to VCC +0.3 V
Input voltage (port 7) Vin –0.3 to AVCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifications: –20 to +75*2°C
Wide-range specifications: –40 to +85*2°C
Storage temperature Tstg –55 to +125 °C
Caution: Permanent damage to the chip may result if absolute ma ximum ratings are exceeded.
Notes: 1. 12 V must not be applied to any pin, as this will caus e permanent damage to the chip.
2. The operating temperature range when programming/erasing flash memory is Ta = 0 to
+75°C (regular specifications) or Ta = 0 to +85°C (wide-range specifications).
Section 18 Electrical Characteristics
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18.2.2 DC Characteristics
Table 18.9 lists the DC characteristics. Table 18.10 lists the permissible output currents.
Table 18.9 DC Characteristics (1)
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
(Programming/Erasing Conditions: Ta = 0°C to +75°C (regular specifications),
Ta = 0°C to +85°C (wide-range specifications))
Item Symbol Min Typ Max Unit Test Conditions
VT–1.0 —— V
VT+——VCC × 0.7 V
Schmitt
trigger input
voltages
Port A,
P80 to P81,
PB0 to PB3VT+ – VT–0.4 —— V
RES, STBY,
NMI, MD2, MD1,
MD0, FWE
VIH VCC –0.7 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
Port 7 2.0 —AVCC +0.3 V
Input high
voltage
Ports 1, 2, 3,
5, 6, 9,
PB4, PB5, PB7
2.0 — VCC +0.3 V
RES, STBY,
MD2, MD1, MD0,
FWE
VIL –0.3 —0.5 VInput low
voltage
NMI, EXTAL,
ports 1, 2, 3,
5, 6, 7, 9,
PB4, PB5, PB7
–0.3 —0.8 V
All output pins VOH VCC –0.5 —— VI
OH = –200 µAOutput high
voltage 3.5 —— VI
OH = –1 mA
All output pins VOL ——0.4 V IOL = 1.6 mAOutput low
voltage Ports 1, 2, 5, B ——1.0 V IOL = 10 mA
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 538 of 682
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Item Symbol Min Typ Max Unit Test Conditions
STBY, NMI,
RES, MD2, MD1,
MD0
|Iin|——1.0 µA Vin = 0.5 V to
VCC –0.5 V
Port 7 ——1.0 µA Vin = 0.5 V to
AVCC –0.5 V
Input
leakage
current
FWE ——10
Three-state
leakage
current
(off state)
Ports 1, 2, 3,
5, 6, 8, 9, A, B |ITSI|——1.0 µA Vin = 0.5 V to
VCC –0.5 V
Input
pull-up
current
Ports 2, 5 –Ip50 —300 µA Vin = 0 V
NMI, RES Cin ——50 pFInput
capacitance All input pins
except NMI
and RES
——20
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Normal
operation ICC —50 70 mA f = 18 MHz
Sleep mode —35 50 f = 18 MHz
—0.01 5.0 µA Ta ≤ 50°C
Current
dissipation
*2 *4
Standby mode*3
——20.0 50°C < Ta
During A/D
conversion AICC —1.7 2.8 mAAnalog
power
supply
current Idle —0.02 10.0 µA
RAM standby voltage VRAM 2.0 —— V
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
4. Power supply current value when programming/erasing in flash memory (Ta = 0°C to
+75°C (regular specifications), Ta = 0 °C to +85°C (wide-ra nge spe cif ic atio ns)) is 20 mA
(max) higher than the power sup ply curr ent val ue in norm al operat ion.
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 539 of 682
REJ09B0353-0300
Table 18.9 DC Characteristics (2)
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V*1, Ta = –20°C to
+75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications)
(Programming/Erasing Conditions: VCC = 3.0 V to 3.6 V, Ta = 0°C to +75°C (regular
specifications), Ta = 0°C to +85°C (wide-range specifications))
Item Symbol Min Typ Max Unit Test Conditions
VT–VCC × 0.2 —— V
VT+——VCC × 0.7 V
Schmitt
trigger input
voltages
Port A,
P80 to P81,
PB0 to PB3VT+ – VT–VCC × 0.04 —— V
Input high
voltage RES, STBY,
NMI, MD2 to
MD0, FWE
VIH VCC × 0.9 — VCC +0.3 V
EXTAL VCC × 0.7 — VCC +0.3 V
Port 7 VCC × 0.7 —AVCC +0.3 V
Ports 1 to 3, 5, 6,
9, PB4, PB5, PB7
VCC × 0.7 — VCC +0.3 V
Input low
voltage RES, STBY,
FWE, MD2 to
MD0, FWE
VIL –0.3 — VCC × 0.1 V
–0.3 — VCC × 0.2 V VCC < 4.0 VNMI, EXTAL,
ports 1 to 3,
5 to 7, 9, PB4,
PB5, PB70.8 VCC = 4.0 V to
5.5V
Output high
voltage All output pins VOH VCC –0.5
VCC –1.0
—
—
—
—
V
V
IOH = –200 µA
IOH = –1 mA
All output pins VOL ——0.4 V IOL = 1.0 mAOutput low
voltage Ports 1, 2, 5, B ——1.0 V VCC ≤ 4 V,
IOL = 5 mA,
4V < VCC ≤ 5.5 V,
IOL = 10 mA
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 540 of 682
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Item Symbol Min Typ Max Unit Test Conditions
STBY, NMI,
RES, MD2,
MD1, MD0
|Iin|——1.0 µA Vin = 0.5 V to
VCC –0.5 V
Input
leakage
current
Port 7 ——1.0 µA Vin = 0.5 V to
AVCC –0.5 V
FWE ——10 µA Vin = 0.5 V to
VCC –0.5 V
Three-state
leakage
current
(off state)
Ports 1, 2, 3, 5,
6, 8 to B |ITSI|——1.0 µA Vin = 0.5 V to
VCC –0.5 V
Input pull-up
current Ports 2 and 5 –Ip10 —300 µA VCC = 3.0 V to
5.5 V,
Vin = 0 V
NMI, RES Cin ——50 pFInput
capacitance All input pins
except NMI
and RES
——20 pF
Vin = 0 V,
f = 1 MHz,
Ta = 25°C
Normal
operation ICC *4—15
(3.0 V) 41.5
(5.5 V) mA f = 10 MHzCurrent
dissipation
*2 *5Sleep mode —10
(3.0 V) 30.5
(5.5 V) mA f = 10 MHz
Standby mode*3—0.01 5.0 µA Ta ≤ 50°C
——20.0 50°C < Ta
AICC —1.3 2.5 mA AVCC = 3.0 VDuring A/D
conversion —1.7 2.8 AVCC = 5.0 V
Analog
power
supply
current Idel —0.02 10.0 µA
RAM standby voltage VRAM 2.0 —— V
Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open.
Connect AVCC to VCC, and connect AVSS to VSS.
2. Current dissipation values are for VIH min = VCC –0.5 V and VIL max = 0.5 V with all
output pins unloaded and the on-chip pull-up transistors in the off state.
3. The values are for VRAM ≤ VCC < 3.0 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
4. ICC depends on VCC and f as follows:
ICC max = 3.0 (mA) + 0.7 (mA/MHz ⋅ V) × VCC × f [normal mode]
ICC max = 3.0 (mA) + 0.5 (mA/MHz ⋅ V) × VCC × f [sleep mode]
5. The current dissipation value when programming/erasing flash memory (Ta = 0°C to
+75°C (regular specifications), Ta = 0 °C to +85°C (wide-ra nge spe cif ic atio ns)) is 20 mA
(max) higher than the current dissipation va lue in normal operation.
Section 18 Electrical Characteristics
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Table 18.10 Permissible Output Currents
Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20°C to +75°C
(regular specifications), Ta = –40°C to +85°C (wide-range specifications)
Item Symbol Min Typ Max Unit
Permissible output
low current (per pin) Ports 1, 2, 5 and B IOL ——10 mA
Other output pi ns ——2.0 mA
Permissible output
low current (total) Total of 27 pins
including ports 1, 2, 5
and B
ΣIOL ——80 mA
Total of 23 pins,
including ports 8, 9, A
and B
——75*2/
65*1mA
Total of all output pins,
including the above ——120 mA
Permissible output
high current (per pin) All output pins IOH ——2.0 mA
Permissible output
high current (total) Total of all output pins ΣIOH ——40 mA
Notes: To protect chip reliability, do not exceed the output current values in table 18.10.
When driving a Darlingt on pair o r LED, alwa ys ins ert a current-limiting resistor in the output
line, as shown in figures 18.4 and 18.5.
1. Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V
2. Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 542 of 682
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LSI
Port 2 kΩ
Darlington pair
Figure 18.4 Darlington Pair Drive Circuit (Example)
LSI
Ports
LED
600 Ω
Figure 18.5 LED Drive Circuit (Example)
Section 18 Electrical Characteristics
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18.2.3 AC Characteristics
Bus timing parameters are listed in table 18.11. Contr ol signal timing p arameters are listed in table
18.12. Timing parameters of the on-chip supporting modules are listed in table 18.13.
Table 18.11 Bus Timing
Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 to 10 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B
10 MHz 18 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Clock cycle time tcyc 100 500 55.5 500 ns
Clock low pulse width tCL 30 —17 —
Figure 18.7,
Figure 18.8
Clock high pulse width tCH 30 —17 —
Clock rise time tCr —15 —10
Clock fall time tCf —15 —10
Address delay time tAD —50 —25
Address hold time tAH 20 —10 —
Address strobe delay time tASD —40 —25
Write strobe delay time tWSD —50 —25
Strobe delay time tSD —50 —25
Write data strobe pulse width 1 tWSW1*60 —32 —
Write data strobe pulse width 2 tWSW2*110 —62 —
Address setup time 1 tAS1 15 —10 —
Address setup time 2 tAS2 65 —38 —
Read data setup time tRDS 35 —15 —
Read data hold time tRDH 0 — 0 —
Section 18 Electrical Characteristics
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Condition A Condition B
10 MHz 18 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Write data delay time tWDD —75 —55 ns
Write data setup time 1 tWDS1 40 —10 —
Figure 18.7,
Figure 18.8
Write data setup time 2 tWDS2 –10 —–10 —
Write data hold time tWDH 20 —20 —
Read data access time 1 tACC1*—100 —50
Read data access time 2 tACC2*—200 —105
Read data access time 3 tACC3*—50 —20
Read data access time 4 tACC4*—150 —80
Precharge time tPCH*60 —40 —
Wait setup time tWTS 40 —25 —ns Figure 18.9
Wait hold time tWTH 10 — 5 —
Note: *For condition A, the following times depend on the clock cycle time as shown below.
tACC1 = 1.5 × tcyc –50 (ns) tWSW1 = 1.0 × tcyc –40 (ns)
tACC2 = 2.5 × tcyc –50 (ns) tWSW2 = 1.5 × tcyc –40 (ns)
tACC3 = 1.0 × tcyc –50 (ns) tPCH = 1.0 × tcyc –40 (ns)
tACC4 = 2.0 × tcyc –50 (ns)
For condition B, the following times depend on the clock cycle time as shown below.
tACC1 = 1.5 × tcyc –34 (ns) tWSW1 = 1.0 × tcyc –24 (ns)
tACC2 = 2.5 × tcyc –34 (ns) tWSW2 = 1.5 × tcyc –22 (ns)
tACC3 = 1.0 × tcyc –36 (ns) tPCH = 1.0 × tcyc –21 (ns)
tACC4 = 2.0 × tcyc –31 (ns)
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 545 of 682
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Table 18.12 Control Signal Timing
Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 to 10 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B
10 MHz 18 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
RES setup time tRESS 200 —200 —ns Figure 18.10
RES pulse width tRESW 20 —20 —tcyc
Mode programming setup time tMDS 200 —200 —ns
NMI setup time
(NMI, IRQ0, IRQ1, IRQ4, IRQ5)tNMIS 200 —150 —ns Figure 18.12
NMI hold time
(NMI, IRQ0, IRQ1, IRQ4, IRQ5)tNMIH 10 —10 —
Interrupt pulse width
(NMI, IRQ1, IRQ0 when ex iting
software standby mode)
tNMIW 200 —200 —
Clock oscillator settling time at
reset (crystal) tOSC1 20 —20 —ms Figure 18.13
Clock oscillator settling time in
software standby (crystal) tOSC2 8 — 7 — ms Figure 17.1
Section 18 Electrical Characteristics
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Table 18.13 Timing of On-Chip Supporting Modules
Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B
10 MHz 18 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
ITU Timer output delay time tTOCD —100 —100 ns Figure 18.15
Timer input setup time tTICS 50 —50 —
Timer clock input setup
time tTCKS 50 —50 —Figure 18.16
Single
edge tTCKWH 1.5 —1.5 — tcyc
Timer clock
pulse width
Both
edges tTCKWL 2.5 —2.5 —
SCI Asynchro-
nous tScyc 4 — 4 — Figure 18.17Input clock
cycle
Synchro-
nous 6 — 6 —
Input clock rise time tSCKr —1.5 —1.5
Input clock fall time tSCKf —1.5 —1.5
Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc
Transmit data delay time tTXD —100 —100 ns Figure 18.18
Receive data set up tim e
(synchronous) tRXS 100 —100 —
Receive data hol d time
(synchronous clock
input)
tRXH 100 —100 —
Receive data hol d time
(synchronous clock
output)
0 — 0 —
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 547 of 682
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Condition A Condition B
10 MHz 18 MHz
Item Symbol Min Max Min Max Unit Test
Conditions
Output data delay time tPWD —100 —100 ns Figure 18.14
Input data setup time tPRS 50 —50 —
Ports
and
TPC Input data hold time tPRH 50 —50 —
CR
H
5 V
RL
This LSI
output pin
C = 90 pF: ports 1, 2, 3, 5, 6, 8, φ
C = 30 pF: ports 9, A, B
Input/output timing measurement levels
• Low: 0.8 V
• High: 2.0 V
R = 2.4 k
R = 12 k
L
H
Ω
Ω
Figure 18.6 Output Load Circuit
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 548 of 682
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18.2.4 A/D Conversion Characteristics
Table 18.14 lists the A/D conversion characteristics.
Table 18.14 A/D Converter Characteristics
Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, φ = 2 MHz to
10 MHz, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-
range specifications)
Condition B: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 2 MHz to 18 MHz,
Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range
specifications)
Condition A Condition B
10 MHz 18 MHz
Item Min Typ Max Min Typ Max Unit
Resolution 10 10 10 10 10 10 bits
Conversion time ——13.4 ——7.5 µs
Analog input capacitance ——20 ——20 pF
——5*1——10*2kΩPermissible signal-
source impedance ——5*3
Nonlineari ty error ——±7.5 ——±3.5 LSB
Offset error ——±7.5 ——±3.5 LSB
Full-sca le error ——±7.5 ——±3.5 LSB
Quantization error ——±0.5 ——±0.5 LSB
Absolute ac curacy ——±8.0 ——±4.0 LSB
Notes: 1. The value is for φ = 10 MHz.
2. The value is for φ ≤ 12 MHz.
3. The value is for φ > 12 MHz.
Section 18 Electrical Characteristics
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18.2.5 Flash Memory Characteristics
Table 18.15 shows the flash memory characteristics.
Table 18.15 Flash Memory Characteristics (1)
Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V
Ta = 0°C to +75°C (program/erase operating temperature range: regular
specifications), Ta = 0°C to +85°C (program/erase operating temperature range:
wide-range specifications)
Item Symbol Min Typ Max Unit Test
condition
Programming time*1 *2 *4tP—10 200 ms/32 bytes
Erase time*1 *3 *5tE—100 300 ms/block
Reprogramming count NWEC ——100 Times
Programming Wai t time after SWE bit setting*1x10——µs
Wait time after PSU bit setting*1y50——µs
Wait time after P bit setting*1 *4z 150 —500 µs
Wait time after P bit clear*1α10 ——µs
Wait time after PSU bit clear*1β10 ——µs
Wait time after PV bit setting*1γ4——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after PV bit clear*1η4——µs
Maximum programming count*1 *4N——403 Times
Erase Wait time after SWE bit setting*1x10——µs
Wait time after ESU bit setting*1y 200 ——µs
Wait time after E bit setting*1 *5z5—10 ms
Wait time after E bit clear*1α10 ——µs
Wait time after ESU bit clear*1β10 ——µs
Wait time after EV bit setting*1γ20 ——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after EV bit clear*1η5——µs
Maximum erase count*1 *5N30—60 Times
Notes: 1. Set the times accord ing to the program /era se alg orithm s .
2. Programming time per 32 bytes (Shows the total time the flash memory control register
(FLMCR) is set. It does not include the programming verification time.)
Section 18 Electrical Characteristics
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3. Block erase time (Shows the period the E bit in FLMCR is set. It does not include the
erase verification time.)
4. To specify the maximum programming time (tP(max)) in the 32-byte programming
flowchart, set the max value (403) for the maximum programming count (N).
The wait time after P bit setting (z) should be changed as follows accord ing to the
programming cou nter va lue.
Programming counter value of 1 to 4: z = 150 µs
Programming counter value of 5 to 403: z = 500 µs
5. For the maximum erase time (tE(max)), the following relationship applies between the
wait time after E bit setting (z) and the maximum erase count (N):
tE(max) = Wait time after E bit setting (z) × maximum e rase c ount (N)
To set the maximum erase time, the values of z and N should be set so as to satisfy the
above formula.
Examples: When z = 5 [ms]: N = 60 times
When z = 10 [ms]: N = 30 times
Section 18 Electrical Characteristics
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Table 18.15 Flash Memory Characteristics (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V
Ta = 0°C to +75°C (Programming/erasing operating temperature range: regular
specification) Ta = 0°C to +85°C (Programming/erasing operating temperature range:
wide-range specification)
Item Symbol Min Typ Max Unit Test
condition
Programming time*1 *2 *4tP—10 200 ms/32 bytes
Erase time*1 *3 *5tE—100 300 ms/block
Reprogramming count NWEC ——100 Times
Programming Wai t time after SWE bit setting*1x10——µs
Wait time after PSU bit setting*1y50——µs
Wait time after P bit setting*1 *4z 150 —500 µs
Wait time after P bit clear*1α10 ——µs
Wait time after PSU bit clear*1β10 ——µs
Wait time after PV bit setting*1γ4——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after PV bit clear*1η4——µs
Maximum programming count*1,*4N——403 Times
Erase Wait time after SWE bit setting*1x10——µs
Wait time after ESU bit setting*1y 200 ——µs
Wait time after E bit setting*1 *5z5—10 ms
Wait time after E bit clear*1α10 ——µs
Wait time after ESU bit clear*1β10 ——µs
Wait time after EV bit setting*1γ20 ——µs
Wait time after H'FF dummy write*1ε2——µs
Wait time after EV bit clear*1η5——µs
Maximum erase count*1 *5N30—60 Times
Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or
erase/erase-verify flowchart.
2. Programming time per 32 bytes (Shows the total period for which the P-bit in the flash
memory control register (FLMCR) is set. It does not include the programming
verification time.)
3. Block erase time (Shows the total period for which the E-bit in FLMCR is set. It does not
include the erase verification time.)
Section 18 Electrical Characteristics
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4. To specify the maximum programming time (tP(max)) in the 32-byte programming
flowchart, set the maximum value (403) for the maximum programming count (N).
The wait time after P bit setting (z) should be changed as follows accord ing to the
programming cou nter va lue.
Programming counter value of 1 to 4: z = 150 µs
Programming counter value of 5 to 403: z = 500 µs
5. For the maximum erase time (tE(max)), the following relationshi p applies between the
wait time after E bit setting (z) and the maximum erase count (N):
tE(max) = Wait time after E bit setting (z) × maximum e rase c ount (N)
To set the maximum erase time, the values of z and N should be set so as to satisfy the
above formula.
Examples: When z = 5 [ms], N = 60 times
When z = 10 [ms], N = 30 times
18.3 Operational Timing
This section shows timing diagrams.
18.3.1 Bus Timing
Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 18.7 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 18.8 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 18.9 shows the timing of the external three-state access cycle with one wait state
inserted.
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 553 of 682
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T
1
T
2
t
cyc
t
CH
t
CL
t
AD
t
Cf
t
Cr
t
AS1
t
AS1
t
ASD
t
ACC3
t
ASD
t
ACC3
t
ACC1
t
ASD
t
AS1
t
WDD
t
WDS1
t
WSW1
t
SD
t
AH
t
PCH
t
SD
t
AH
t
PCH
t
RDH
t
RDS
t
PCH
t
SD
t
AH
t
WDH
φ
A
23
to A
0
AS
RD
(read)
D
7
to D
0
(read)
WR (write)
D
7
to D
0
(write)
Figure 18.7 Basic Bus Cycle: Two-State Access
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T
1
T
2
T
3
t
ACC4
t
ACC4
t
ACC2
t
WSW2
t
WSD
t
AS2
t
WDS2
φ
A
23
to A
0
AS
RD (read)
D
7
to D
0
(read)
WR (write)
D
7
to D
0
(write)
t
RDS
Figure 18.8 Basic Bus Cycle: Three-State Access
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T
1
T
2
T
W
T
3
t
WTS
t
WTS
t
WTH
φ
A
23
to A
0
AS
RD (read)
D
7
to D
0
(read)
WR (write)
D
7
to D
0
(write)
WAIT
t
WTH
Figure 18.9 Basic Bus Cycle: Three-State Access with One Wait State
Section 18 Electrical Characteristics
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18.3.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 18.10 shows the reset input timing.
• Reset output timing
Figure 18.11 shows the reset output timing.
• Interrupt input timing
Figure 18.12 shows the interrupt input timing for NMI and IRQ5, IRQ4, IRQ1, and IRQ0.
φ
RES
tRESS tRESS
tRESW
tMDS
MD2 to MD0
FWE*
Note: * The FWE input timing shown is for entering and exiting boot mode.
Figure 18. 10 Reset Input Timing
φ
RESO*
Note: * Flash version does not have RESO output pin
tRESD
tRESOW
tRESD
Figure 18.11 Reset Output Timing
Section 18 Electrical Characteristics
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φ
NMI
IRQ
IRQ
E
L
t
NMIS
t
NMIH
t
NMIS
t
NMIH
t
NMIS
t
NMIW
NMI
IRQ
j
IRQ : Edge-sensitive IRQ
: Level-sensitive IRQ (i = 0, 1, 4, and 5)
E
L
i
i
IRQ
(j = 0, 1)
Figure 18. 12 Interrupt Input Timing
Section 18 Electrical Characteristics
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18.3.3 Clock Timing
Clock timing is shown below.
• Oscillator settlin g timing
Figure 18.13 shows the oscillator settling timin g.
φ
V
CC
STBY
RES
t
OSC1
t
OSC1
Figure 18.13 Oscilla t or Settling Timing
18.3.4 TPC and I/O Port Timing
TPC and I/O port timing is shown below.
T1T2T3
φ
Ports 1 to 3,
5 to 9, A, and
B (read)
Ports 1 to 3,
5, 6, 8, 9, A,
and B (write)
tPRS tPRH
tPWD
Figure 18.14 TPC and I/O Port Input/Output Timing
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 559 of 682
REJ09B0353-0300
18.3.5 ITU Timing
ITU timing is shown as follows:
• ITU input/output timing
Figure 18.15 shows the ITU input/output timing.
• ITU external clo ck input timing
Figure 18.16 shows the ITU external clock input timing.
φ
Output
compare*1
Input
capture*2
tTOCD
tTICS
Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4
2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4
Figure 18 . 15 ITU Input/Output Timing
φ t
TCKS
t
TCKS
t
TCKWH
t
TCKWL
TCLKA to
TCLKD
Figure 18.16 ITU External Clock Input Timing
Section 18 Electrical Characteristics
Rev.3.00 Mar. 26, 2007 Page 560 of 682
REJ09B0353-0300
18.3 .6 SCI Input/Out put Timi ng
SCI timing is shown as follows:
• SCI input clock timing
Figure 18.17 shows the SCI input clock timing.
• SCI input/output timing (synchronous mode)
Figure 18.18 shows the SCI input/output timing in synchronous mode.
SCK
tSCKW
tScyc
tSCKr tSCKf
Figure 18. 17 SCK Input Clock Timing
tScyc
tTXD
tRXS tRXH
SCK
TxD
(transmit
data)
RxD
(receive
data)
Figure 18 . 18 SCI Input/Output Timing in Synchronou s Mode
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 561 of 682
REJ09B0353-0300
Appendi x A Instructi on Set
A.1 Instruction List
Operand Notation
Symbol Description
Rd General destination register*
Rs General source r egi ster *
Rn General register*
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (o verflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+Addition of the operands on both sides
– Subtraction of the operand on the right from the operand on the left
×Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧Logical AND of the operands on both sides
• Logical OR of the operands on both sides
⊕Exclusive logical OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
Note: *General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit
registers (R0 to R7 and E0 to E7).
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 562 of 682
REJ09B0353-0300
Condition Code Notatio n
Symbol Description
↔
Changed according to execution result
*Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆Varies depending on conditions, described in notes
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 563 of 682
REJ09B0353-0300
Table A.1 Instruction Set
1. Data transfer instru ctio ns
Condition Code
Mnemonic Operation I H N Z V C
MOV.B #xx:8, Rd B #xx:8 →Rd8 2 ——
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
0 — 2
MOV.B Rs, Rd B Rs8 →Rd8 2 —— 0 — 2
MOV.B @ERs, Rd B @ERs →Rd8 2 —— 0 — 4
MOV.B @(d:16, ERs),
B @(d:16, ERs) →Rd8 4 —— 0 — 6
Rd
MOV.B @(d:24, ERs),
B @(d:24, ERs) →Rd8 8 —— 0 — 10
Rd
MOV.B @ERs+, Rd B @ERs →RD8 2 —— 0 — 6
ERs32+1 →ERs32
MOV.B @aa:8, Rd B @aa:8 →Rd8 2 —— 0 — 4
MOV.B @aa:16, Rd B @aa:16 →Rd8 4 —— 0 — 6
MOV.B @aa:24, Rd B @aa:24 →Rd8 6 —— 0 — 8
MOV.B Rs, @ERd B Rs8 →@ERd 2 —— 0 — 4
MOV.B Rs, @(d:16, B Rd8 →@(d:16, ERd) 4 —— 0 — 6
ERd)
MOV.B Rs, @(d:24, B Rd8 →@(d:24, ERd) 8 —— 0 — 10
ERd)
MOV.B Rs, @–ERd B ERd32–1 →ERd32 2 —— 0 — 6
Rs8 →@ERd
MOV.B Rs, @aa:8 B Rs8 →@aa:8 2 —— 0 — 4
MOV.B Rs, @aa:16 B Rs8 →@aa:16 4 —— 0 — 6
MOV.B Rs, @aa:24 B Rs8 →@aa:24 6 —— 0 — 8
MOV.W #xx:16, Rd W #xx:16 →Rd16 4 —— 0 — 4
MOV.W Rs, Rd W Rs16 →Rd16 2 —— 0 — 2
MOV.W @ERs, Rd W @ERs →Rd16 2 —— 0 — 4
MOV.W @(d:16, ERs),
W @(d:16, ERs) →Rd16 4 —— 0 — 6
Rd
MOV.W @(d:24, ERs),
W @(d:24, ERs) →Rd16 8 —— 0 — 10
Rd
MOV.W @ERs+, Rd W @ERs →Rd16 2 —— 0 — 6
ERs32+2 →@ERd32
MOV.W @aa:16, Rd W @aa:16 →Rd16 4 —— 0 — 6
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 564 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
MOV.W @aa:24, Rd W @aa:24 →Rd16 6 —— 0 — 8
MOV.W Rs, @ERd W Rs16 →@ERd 2 —— 0 — 4
MOV.W Rs, @(d:16,
W Rs16 →@(d:16, ERd) 4 —— 0 — 6
ERd)
MOV.W Rs, @(d:24,
W Rs16 →@(d:24, ERd) 8 —— 0 — 8
ERd)
MOV.W Rs, @–ERd W ERd32–2 →ERd32 2 —— 0 — 6
Rs16 →@ERd
MOV.W Rs, @aa:16 W Rs16 →@aa:16 4 —— 0 — 6
MOV.W Rs, @aa:24 W Rs16 →@aa:24 6 —— 0 — 8
MOV.L #xx:32, Rd L #xx:32 →Rd32 6 —— 0 — 6
MOV.L ERs, ERd L ERs32 →ERd32 2 —— 0 — 2
MOV.L @ERs, ERd L @ERs →ERd32 4 —— 0 — 8
MOV.L @(d:16, ERs),
L @(d:16, ERs) →ERd32 6 —— 0 — 10
ERd
MOV.L @(d:24, ERs),
L @(d:24, ERs) →ERd32 10 —— 0 — 14
ERd
MOV.L @ERs+, ERd L @ERs →ERd32 4 ——0 — 10
ERs32+4 →ERs32
MOV.L @aa:16, ERd L @aa:16 →ERd32 6 —— 0 — 10
MOV.L @aa:24, ERd L @aa:24 →ERd32 8 ——0 — 12
MOV.L ERs, @ERd L ERs32 →@ERd 4 ——0 — 8
MOV.L ERs, @(d:16, L ERs32 →@(d:16, ERd) 6 —— 0 — 10
ERd)
MOV.L ERs, @(d:24, L ERs32 →@(d:24, ERd) 10 —— 0—14
ERd)
MOV.L ERs, @–ERd L ERd32–4 →ERd32 4—— 0—10
ERs32 →@ERd
MOV.L ERs, @aa:16 L ERs32 →@aa:16 6—— 0—10
MOV.L ERs, @aa:24 L ERs32 →@aa:24 8—— 0—12
POP.W Rn W @SP →Rn16 2—— 0— 6
SP+2 →SP
POP.L ERn L @SP →ERn32 4—— 0—10
SP+4 →SP
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 565 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
PUSH.W Rn W SP–2 →SP 2 —— 0 — 6
Rn16 →@SP
PUSH.L ERn L SP–4 →SP 4 —— 0 — 10
ERn32 →@SP
MOVFPE @aa:16, B Cannot be used in the 4 Cannot be used in the H8/3039
Rd H8/3039 Group Group
MOVTPE Rs, B Cannot be used in the 4 Cannot be used in the H8/3039
@aa:16 H8/3039 Group Group
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*
1
Advanced
Operand Size
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 566 of 682
REJ09B0353-0300
2. Arithmetic instructions
Condition Code
Mnemonic Operation I HNZVC
ADD.B #xx:8, Rd B Rd8+#xx:8 →Rd8 2 — 2
ADD.B Rs, Rd B Rd8+Rs8 →Rd8 2 — 2
ADD.W #xx:16, Rd W Rd16+#xx:16 →Rd16 4 —(1) 4
ADD.W Rs, Rd W Rd16+Rs16 →Rd16 2 —(1) 2
ADD.L #xx:32, ERd L ERd32+#xx:32 →6 — (2) 6
ERd32
ADD.L ERs, ERd L ERd32+ERs32 →2—(2) 2
ERd32
ADDX.B #xx:8, Rd B Rd8+#xx:8 +C →Rd8 2 — (3) 2
ADDX.B Rs, Rd B Rd8+Rs8 +C →Rd8 2 — (3) 2
ADDS.L #1, ERd L ERd32+1 →ERd32 2—————— 2
ADDS.L #2, ERd L ERd32+2 →ERd32 2—————— 2
ADDS.L #4, ERd L ERd32+4 →ERd32 2—————— 2
INC.B Rd B Rd8+1 →Rd8 2—— —2
INC.W #1, Rd W Rd16+1 →Rd16 2—— —2
INC.W #2, Rd W Rd16+2 →Rd16 2—— —2
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 567 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
INC.L #1, ERd L ERd32+1 →ERd32 2 —— — 2
INC.L #2, ERd L ERd32+2 →ERd32 2 —— — 2
DAA Rd B
Rd8 decimal adjust
2 — **— 2
→Rd8
SUB.B Rs, Rd B Rd8–Rs8 →Rd8 2 — 2
SUB.W #xx:16, Rd W Rd16–#xx:16 →Rd16 4 —(1) 4
SUB.W Rs, Rd W Rd16–Rs16 →Rd16 2 —(1) 2
SUB.L #xx:32, ERd L ERd32–#xx:32 6 —(2) 6
→ERd32
SUB.L ERs, ERd L ERd32–ERs32 2 —(2) 2
→ERd32
SUBX.B #xx:8, Rd B Rd8–#xx:8–C →Rd8 2 —(3) 2
SUBX.B Rs, Rd B Rd8–Rs8–C →Rd8 2 —(3) 2
SUBS.L #1, ERd L ERd32–1 →ERd32 2 —————— 2
SUBS.L #2, ERd L ERd32–2 →ERd32 2 —————— 2
SUBS.L #4, ERd L ERd32–4 →ERd32 2 —————— 2
DEC.B Rd B Rd8–1 →Rd8 2 ——— 2
DEC.W #1, Rd W Rd16–1 →Rd16 2 ——— 2
DEC.W #2, Rd W Rd16–2 →Rd16 2 ——— 2
DEC.L #1, ERd L ERd32–1 →ERd32 2 —— — 2
DEC.L #2, ERd L ERd32–2 →ERd32 2 ——— 2
DAS.Rd B
Rd8 decimal adjust
2 — **— 2
→Rd8
MULXU. B Rs, Rd B Rd8 × Rs8 →Rd16 2 —————— 14
(unsigned multiplication)
MULXU. W Rs, ERd W Rd16 × Rs16 →ERd32 2 —————— 22
(unsigned multiplication)
MULXS. B Rs, Rd B Rd8 × Rs8 →Rd16 4—— ——16
(signed multiplication)
MULXS. W Rs, ERd W Rd16 × Rs16 →ERd32 4—— ——24
(signed multiplication)
DIVXU. B Rs, Rd B Rd16 ÷ Rs8 →Rd16 2——(6) (7) —— 14
(RdH: remainder,
RdL: quotient)
(unsigned
division
)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 568 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
DIVXU. W Rs, ERd W ERd32 ÷ Rs16 →ERd32 2 ——(6) (7) —— 22
(Ed: remainder,
Rd: quotient)
(unsigned division)
DIVXS. B Rs, Rd B Rd16 ÷ Rs8 →Rd16 4 ——(8) (7) —— 16
(RdH: remainder,
RdL: quotient)
(signed division)
DIVXS. W Rs, ERd W ERd32 ÷ Rs16 →ERd32 4 ——(8) (7) —— 24
(Ed: remainder,
Rd: quotient)
(signed division)
CMP.B #xx:8, Rd B Rd8–#xx:8 2 — 2
CMP.B Rs, Rd B Rd8–Rs8 2 — 2
CMP.W #xx:16, Rd W Rd16–#xx:16 4 —(1) 4
CMP.W Rs, Rd W Rd16–Rs16 2 —(1) 2
CMP.L #xx:32, ERd L ERd32–#xx:32 6 —(2) 4
CMP.L ERs, ERd L ERd32–ERs32 2 —(2) 2
NEG.B Rd B 0–Rd8 →Rd8 2 — 2
NEG.W Rd W 0–Rd16 →Rd16 2 — 2
NEG.L ERd L 0–ERd32 →ERd32 2 — 2
EXTU.W Rd W 0 →(<bits 15 to 8> 2 —— 0 0 — 2
of Rd16)
EXTU.L ERd L 0 →(<bits 31 to 16> 2 —— 0 0 — 2
of Rd32)
EXTS.W Rd W (<bit 7> of Rd16) →2—— 0 — 2
(<bits 15 to 8> of Rd16)
EXTS.L ERd L (<bit 15> of Rd32) →2—— 0 — 2
(<bits 31 to 16> of
ERd32)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔↔↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 569 of 682
REJ09B0353-0300
3. Logic instructions
Condition Code
Mnemonic Operation I H N Z V C
AND.B #xx:8, Rd B Rd8∧#xx:8 →Rd8 2 —— 0 — 2
AND.B Rs, Rd B Rd8∧Rs8 →Rd8 2 —— 0 — 2
AND.W #xx:16, Rd W Rd16∧#xx:16 →Rd16 4 —— 0 — 4
AND.W Rs, Rd W Rd16∧Rs16 →Rd16 2 —— 0 — 2
AND.L #xx:32, ERd L
ERd32∧#xx:32 →ERd32
6—— 0 — 6
AND.L ERs, ERd L
ERd32∧ERs32 →ERd32
4—— 0 — 4
OR.B #xx:8, Rd B Rd8∨#xx:8 →Rd8 2 —— 0 — 2
OR.B Rs, Rd B Rd8∨Rs8 →Rd8 2 —— 0 — 2
OR.W #xx:16, Rd W Rd16∨#xx:16 →Rd16 4 —— 0 — 4
OR.W Rs, Rd W Rd16∨Rs16 →Rd16 2 —— 0 — 2
OR.L #xx:32, ERd L
ERd32∨#xx:32 →ERd32
6—— 0 — 6
OR.L ERs, ERd L
ERd32∨ERs32 →ERd32
4—— 0 — 4
XOR.B #xx:8, Rd B Rd8⊕#xx:8 →Rd8 2 —— 0 — 2
XOR.B Rs, Rd B Rd8⊕Rs8 →Rd8 2 ——0 — 2
XOR.W #xx:16, Rd W Rd16⊕#xx:16 →Rd16 4 ——0 — 4
XOR.W Rs, Rd W Rd16⊕Rs16 →Rd16 2 ——0 — 2
XOR.L #xx:32, ERd L
ERd32⊕#xx:32 →ERd32
6 — —0 — 6
XOR.L ERs, ERd L
ERd32⊕ERs32 →ERd32
4 — —0 — 4
NOT.B Rd B ¬ Rd8 →Rd8 2 —— 0 — 2
NOT.W Rd W ¬Rd16 →Rd16 2 ——0 — 2
NOT.L ERd L ¬Rd32 →Rd32 2 —— 0 — 2
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*
1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 570 of 682
REJ09B0353-0300
4. Shift in structions
Condition Code
Mnemonic Operation I H N Z V C
SHAL.B Rd B 2 —— 2
SHAL.W Rd W 2 —— 2
SHAL.L ERd L 2 —— 2
SHAR.B Rd B 2 —— 02
SHAR.W Rd W 2 —— 02
SHAR.L ERd L 2 —— 02
SHLL.B Rd B 2 —— 02
SHLL.W Rd W 2 —— 02
SHLL.L ERd L 2 —— 02
SHLR.B Rd B 2 —— 02
SHLR.W Rd W 2 —— 02
SHLR.L ERd L 2 —— 02
ROTXL.B Rd B 2 —— 02
ROTXL.W Rd W 2 —— 02
ROTXL.L ERd L 2 —— 02
ROTXR.B Rd B 2 —— 02
ROTXR.W Rd W 2 —— 02
ROTXR.L ERd L 2 —— 02
ROTL.B Rd B 2—— 02
ROTL.W Rd W 2 —— 02
ROTL.L ERd L 2 —— 02
ROTR.B Rd B2—— 02
ROTR.W Rd W2—— 02
ROTR.L ERd L 2 —— 02
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*
1
Advanced
Operand Size
MSB LSB
0
C
C
MSB LSB
MSB LSB
0
C
0
C
MSB LSB
CMSB LSB
C
MSB LSB
CMSB LSB
C
MSB LSB
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
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↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 571 of 682
REJ09B0353-0300
5. Bit manipulation instructions
Condition Code
Mnemonic Operation I H N Z V C
BSET #xx:3, Rd B (#xx:3 of Rd8) ←12 —————— 2
BSET #xx:3, @ERd B (#xx:3 of @ERd) ←14 —————— 8
BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ←14—————— 8
BSET Rn, Rd B (Rn8 of Rd8) ←12 —————— 2
BSET Rn, @ERd B (Rn8 of @ERd) ←14 —————— 8
BSET Rn, @aa:8 B (Rn8 of @aa:8) ←14—————— 8
BCLR #xx:3, Rd B (#xx:3 of Rd8) ←02 —————— 2
BCLR #xx:3, @ERd B (#xx:3 of @ERd) ←04 —————— 8
BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ←04—————— 8
BCLR Rn, Rd B (Rn8 of Rd8) ←02 —————— 2
BCLR Rn, @ERd B (Rn8 of @ERd) ←04 —————— 8
BCLR Rn, @aa:8 B (Rn8 of @aa:8) ←04—————— 8
BNOT #xx:3, Rd B (#xx:3 of Rd8) ←2—————— 2
¬(#xx:3 of Rd8)
BNOT #xx:3, @ERd B (#xx:3 of @ERd) ←4—————— 8
¬(#xx:3 of @ERd)
BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ←4 — ————— 8
¬(#xx:3 of @aa:8)
BNOT Rn, Rd B (Rn8 of Rd8) ←2 — ————— 2
¬(Rn8 of Rd8)
BNOT Rn, @ERd B (Rn8 of @ERd) ←4 — ————— 8
¬(Rn8 of @ERd)
BNOT Rn, @aa:8 B (Rn8 of @aa:8) ←4—————— 8
¬(Rn8 of @aa:8)
BTST #xx:3, Rd B ¬ (#xx:3 of Rd8) →Z2——— —— 2
BTST #xx:3, @ERd B ¬ (#xx:3 of @ERd) →Z4——— —— 6
BTST #xx:3, @aa:8 B ¬ (#xx:3 of @aa:8) →Z4——— —— 6
BTST Rn, Rd B ¬ (Rn8 of @Rd8) →Z2——— —— 2
BTST Rn, @ERd B ¬ (Rn8 of @ERd) →Z4——— —— 6
BTST Rn, @aa:8 B ¬ (Rn8 of @aa:8) →Z4——— —— 6
BLD #xx:3, Rd B (#xx:3 of Rd8) →C2————— 2
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔↔↔↔↔↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 572 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
BLD #xx:3, @ERd B (#xx:3 of @ERd) →C4 ————— 6
BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) →C4————— 6
BILD #xx:3, Rd B ¬(#xx:3 of Rd8) →C2 ————— 2
BILD #xx:3, @ERd B ¬(#xx:3 of @ERd) →C4 ————— 6
BILD #xx:3, @aa:8 B ¬(#xx:3 of @aa:8) →C4————— 6
BST #xx:3, Rd B C →(#xx:3 of Rd8) 2 —————— 2
BST #xx:3, @ERd B C →(#xx:3 of @ERd24) 4 —————— 8
BST #xx:3, @aa:8 B C →(#xx:3 of @aa:8) 4 —————— 8
BIST #xx:3, Rd B ¬C →(#xx:3 of Rd8) 2 —————— 2
BIST #xx:3, @ERd B ¬C →(#xx:3 of @ERd24) 4 —————— 8
BIST #xx:3, @aa:8 B ¬C →(#xx:3 of @aa:8) 4 —————— 8
BAND #xx:3, Rd B C∧(#xx:3 of Rd8) →C2 ————— 2
BAND #xx:3, @ERd B
C∧(#xx:3 of @ERd24) →C
4————— 6
BAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) →C4————— 6
BIAND #xx:3, Rd B C∧ ¬(#xx:3 of Rd8) →C2 ————— 2
BIAND #xx:3, @ERd B
C∧
¬
(#xx:3 of @ERd24) →C
4 — ———— 6
BIAND #xx:3, @aa:8 B
C∧ ¬ (#xx:3 of @aa:8) →C
4 — ———— 6
BOR #xx:3, Rd B C∨(#xx:3 of Rd8) →C2 ————— 2
BOR #xx:3, @ERd B
C
∨
(#xx:3 of @ERd24) →C
4 — ———— 6
BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) →C4
————— 6
BIOR #xx:3, Rd B C∨ ¬(#xx:3 of Rd8) →C2 ————— 2
BIOR #xx:3, @ERd B
C
∨
¬
(#xx:3 of @ERd24) →C
4————— 6
BIOR #xx:3, @aa:8 B
C
∨
¬(#xx:3 of @aa:8) →C
4————— 6
BXOR #xx:3, Rd BC
⊕ (#xx:3 of Rd8) →C2————— 2
BXOR #xx:3, @ERd B
C
⊕
(#xx:3 of @ERd24)
→C
4————— 6
BXOR #xx:3, @aa:8 BC
⊕(#xx:3 of @aa:8) →C4————— 6
BIXOR #xx:3, Rd BC
⊕ ¬(#xx:3 of Rd8) →C2————— 2
BIXOR #xx:3, @ERd B
C
⊕
¬
(#xx:3 of @ERd24)
→C
4————— 6
BIXOR #xx:3, @aa:8 B
C
⊕
¬
(#xx:3 of @aa:8)
→C
4————— 6
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 573 of 682
REJ09B0353-0300
6. Branching instructions
Condition Code
Mnemonic Operation I H N Z V C
BRA d:8 (BT d:8) —Always 2 —————— 4
BRA d:16 (BT d:16) — 4 —————— 6
BRN d:8 (BF d:8) —Never 2 —————— 4
BRN d:16 (BF d:16) — 4 —————— 6
BHI d:8 —C ∨Z = 0 2 —————— 4
BHI d:16 — 4 —————— 6
BLS d:8 —C ∨Z = 1 2 —————— 4
BLS d:16 — 4 —————— 6
BCC d:8 (BHS d:8) —C = 0 2 —————— 4
BCC d:16 (BHS d:16) — 4 —————— 6
BCS d:8 (BLO d:8) —C = 1 2 —————— 4
BCS d:16 (BLO d:16) — 4 —————— 6
BNE d:8 —Z = 0 2 —————— 4
BNE d:16 — 4 —————— 6
BEQ d:8 —Z = 1 2—————— 4
BEQ d:16 — 4 —————— 6
BVC d:8 —V = 0 2—————— 4
BVC d:16 — 4 —————— 6
BVS d:8 —V = 1 2 —————— 4
BVS d:16 — 4 —————— 6
BPL d:8 —N = 0 2 —————— 4
BPL d:16 — 4 —————— 6
BMI d:8 —N = 1 2 —————— 4
BMI d:16 — 4 —————— 6
BGE d:8 — N ⊕ V = 0 2—————— 4
BGE d:16 — 4 —————— 6
BLT d:8 — N ⊕ V = 1 2—————— 4
BLT d:16 — 4 —————— 6
BGT d:8 — 2 —————— 4
BGT d:16 — 4 —————— 6
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
Z
∨
(N
⊕
V)
= 0
If condition
is true then
PC ←
PC+d else
next;
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 574 of 682
REJ09B0353-0300
Condition Code
Mnemonic Operation I H N Z V C
BLE d:8 — 2 —————— 4
BLE d:16 — 4 —————— 6
JMP @ERn —PC ←ERn 2 —————— 4
JMP @aa:24 —PC ←aa:24 4 —————— 6
JMP @@aa:8 —PC ←@aa:8 2 —————— 810
BSR d:8 —PC →@–SP 2 —————— 68
PC ←PC+d:8
BSR d:16 —PC →@–SP 4 —————— 810
PC ←PC+d:16
JSR @ERn —PC →@–SP 2 —————— 68
PC ←@ERn
JSR @aa:24 —PC →@–SP 4 —————— 810
PC ←@aa:24
JSR @@aa:8 —PC →@–SP 2 —————— 812
PC ←@aa:8
RTS —PC ←@SP+ 2 —————— 810
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
Z
∨
(N
⊕
V)
= 1
If condition
is true then
PC ←
PC+d else
next;
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 575 of 682
REJ09B0353-0300
7. System control instructions
Condition Code
Mnemonic Operation I H N Z V C
TRAPA #x:2 —PC →@–SP 2 1 ————— 14 16
CCR →@–SP
<vector> →PC
RTE —CCR ←@SP+ 10
PC ←@SP+
SLEEP —Transition to power- —————— 2
down state
LDC #xx:8, CCR B #xx:8 →CCR 2 2
LDC Rs, CCR B Rs8 →CCR 2 2
LDC @ERs, CCR W @ERs → CCR 4 6
LDC @(d:16, ERs), W @(d:16, ERs) → CCR 6 8
CCR
LDC @(d:24, ERs), W @(d:24, ERs) → CCR 10 12
CCR
LDC @ERs+, CCR W @ERs → CCR 4 8
ERs32+2 → ERs32
LDC @aa:16, CCR W @aa:16 → CCR 6 8
LDC @aa:24, CCR W @aa:24 → CCR 8 10
STC CCR, Rd B CCR →Rd8 2 —————— 2
STC CCR, @ERd W CCR →@ERd 4 —————— 6
STC CCR, @(d:16, W CCR →@(d:16, ERd) 6 —————— 8
ERd)
STC CCR, @(d:24, W CCR →@(d:24, ERd) 10 —————— 12
ERd)
STC CCR, @–ERd W ERd32–2 →ERd32 4—————— 8
CCR →@ERd
STC CCR, @aa:16 W CCR →@aa:16 6—————— 8
STC CCR, @aa:24 W CCR →@aa:24 8—————— 10
ANDC #xx:8, CCR B CCR∧#xx:8 →CCR 22
ORC #xx:8, CCR B CCR∨#xx:8 →CCR 22
XORC #xx:8, CCR B CCR⊕#xx:8 →CCR 22
NOP —PC ←PC+2 2—————— 2
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*1
Advanced
Operand Size
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 576 of 682
REJ09B0353-0300
8. Block transfer instructions
Condition Code
Mnemonic Operation I H N Z V C
EEPMOV. B —if R4L ≠0 then 4 —————— 8+4n*
2
repeat @R5 →@R6
R5+1 →R5
R6+1 →R6
R4L−1 →R4L
until R4L=0
else next
EEPMOV. W —if R4 ≠0 then 4 —————— 8+4n*
2
repeat @R5 →@R6
R5+1 →R5
R6+1 →R6
R4−1 →R4
until R4=0
else next
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
Implied
Addressing Mode and
Instruction Length (bytes)
Normal
No. of
States*
1
Advanced
Operand Size
Notes: 1. The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases see section
A.3, Number of States Required for Execution.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 577 of 682
REJ09B0353-0300
A.2 Operation Code Maps
Table A.2 Operation Code Map (1)
Instruction code:
AH AL 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
BRN
DIVXU
BNOT
STC
BHI
MULXU
BCLR
LDC
BLS
DIVXU
BTST
ORC
OR.B
BCC
RTS
OR
XORC
XOR.B
BCS
BSR
XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND.B
BNE
RTE
AND
LDC
BEQ
TRAPA
BLD
BILD
BST
BIST
BVC
MOV
BPL
JMP
BMI
EEPMOV
ADDX
SUBX
BGT
JSR
BLE
MOV
MOV.B
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2) Table A.2
(2)
BVS BLTBGE
BSR
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2)
Table A.2
(2) Table A.2
(2) Table A.2
(3)
1st byte 2nd byte
AH BHAL BL
ADD
SUB
MOV
CMP
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 578 of 682
REJ09B0353-0300
Table A.2 Operation Code Map (2)
AH ALBH 0123456789ABCDEF
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
BHI
CMP
CMP
LDC/STC
BCC
OR
OR
BPL BGT
Instruction code:
BVS
SLEEP
BVC BGE
Table A.2
(3)
Table A.2
(3) Table A.2
(3)
ADD
MOV
SUB
CMP
BNE
AND
AND
INC
EXTU
DEC
BEQ
INC
EXTU
DEC
BCS
XOR
XOR
SHLL
SHLR
ROTXL
ROTXR
NOT
BLS
SUB
SUB
BRN
ADD
ADD
INC
EXTS
DEC
BLT
INC
EXTS
DEC
BLE
SHAL
SHAR
ROTL
ROTR
NEG
BMI
1st byte 2nd byte
AH BHAL BL
SUB
ADDS
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHAR
ROTL
ROTR
NEG
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 579 of 682
REJ09B0353-0300
Table A.2 Operation Code Map (3)
AH
ALBH
BLCH
CL
0123456789ABCDEF
01406
01C05
01D05
01F06
7Cr06*1
7Cr07*1
7Dr06*1
7Dr07*1
7Eaa6*2
7Eaa7*2
7Faa6*2
7Faa7*2
MULXS
BSET
BSET
BSET
BSET
DIVXS
BNOT
BNOT
BNOT
BNOT
MULXS
BCLR
BCLR
BCLR
BCLR
DIVXS
BTST
BTST
BTST
BTST
OR XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
AND
BLD
BILD
BST
BIST
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Instruction code:
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1.
2. r is the register designation field.
aa is the absolute address field.
1st byte 2nd byte
AH BHAL BL 3rd byte
CH DHCL DL
4th byte
LDCSTC LDC LDC LDC
STC STC STC
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 580 of 682
REJ09B0353-0300
A.3 Number of States Required for Execution
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.3 indicates the number of states required per cycle
according to the bus size. Table A.4 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0 , @FFFFC7:8
From table A.3, SI = 4 and SL = 3
From table A.4, I = L = 2 and J = K = M = N = 0
Number of states = 2 × 4 + 2 × 3 = 14
JSR @@30
From table A.3, SI = SJ = SK = 4
From table A.4, I = J = K = 2 and L = M = N = 0
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 581 of 682
REJ09B0353-0300
Table A.3 Number of States per Cycle
Access Conditions
External Device
On-Chip
Supporting
Module 8-Bit Bus 16-Bit Bus
Cycle On-Chip
Memory 8-Bit
Bus 16-Bit
Bus 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI2 6 3 4 6 + 2m 2 3 + m
Branch address read SJ
Stack operation SK
Byte data access SL323 + m
Word data access SM6 4 6 + 2m
Internal operation SN1111111
Legend:
m: Number of wait states inserted in external device access
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 582 of 682
REJ09B0353-0300
Table A.4 Number of Cycles per Instruction
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd 1
ADD.B Rs, Rd 1
ADD.W #xx:16, Rd 2
ADD.W Rs, Rd 1
ADD.L #xx:32, ERd 3
ADD.L ERs, ERd 1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx:8, Rd 1
ADDX Rs, Rd 1
AND AND.B #xx:8, Rd 1
AND.B Rs, Rd 1
AND.W #xx:16, Rd 2
AND.W Rs, Rd 1
AND.L #xx:32, ERd 3
AND.L ERs, ERd 2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd 1
BAND #xx:3, @ERd 2 1
BAND #xx:3, @aa:8 2 1
Bcc BRA d:8 (BT d:8) 2
BRN d:8 (BF d:8) 2
BHI d:8 2
BLS d:8 2
BCC d:8 (BHS d:8) 2
BCS d:8 (BLO d:8) 2
BNE d:8 2
BEQ d:8 2
BVC d:8 2
BVS d:8 2
BPL d:8 2
BMI d:8 2
BGE d:8 2
BLT d:8 2
BGT d:8 2
BLE d:8 2
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 583 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc BRA d:16 (BT d:16) 2 2
BRN d:16 (BF d:16) 2 2
BHI d:16 2 2
BLS d:16 2 2
BCC d:16 (BHS d:16) 2 2
BCS d:16 (BLO d:16) 2 2
BNE d:16 2 2
BEQ d:16 2 2
BVC d:16 2 2
BVS d:16 2 2
BPL d:16 2 2
BMI d:16 2 2
BGE d:16 2 2
BLT d:16 2 2
BGT d:16 2 2
BLE d:16 2 2
BCLR BCLR #xx:3, Rd 1
BCLR #xx:3, @ERd 2 2
BCLR #xx:3, @aa:8 2 2
BCLR Rn, Rd 1
BCLR Rn, @ERd 2 2
BCLR Rn, @aa:8 2 2
BIAND BIAND #xx:3, Rd 1
BIAND #xx:3, @ERd 2 1
BIAND #xx:3, @aa:8 2 1
BILD BILD #xx:3, Rd 1
BILD #xx:3, @ERd 2 1
BILD #xx:3, @aa:8 2 1
BIOR BIOR #xx:8, Rd 1
BIOR #xx:8, @ERd 2 1
BIOR #xx:8, @aa:8 2 1
BIST BIST #xx:3, Rd 1
BIST #xx:3, @ERd 2 2
BIST #xx:3, @aa:8 2 2
BIXOR BIXOR #xx:3, Rd 1
BIXOR #xx:3, @ERd 2 1
BIXOR #xx:3, @aa:8 2 1
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 584 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BLD BLD #xx:3, Rd 1
BLD #xx:3, @ERd 2 1
BLD #xx:3, @aa:8 2 1
BNOT BNOT #xx: 3, Rd 1
BNOT #xx:3, @ERd 2 2
BNOT #xx:3, @ aa: 8 2 2
BNOT Rn, Rd 1
BNOT Rn, @ERd 2 2
BNOT Rn, @aa:8 2 2
BOR BOR #xx:3, Rd 1
BOR #xx:3, @ERd 2 1
BOR #xx:3, @aa:8 2 1
BSET BSET #xx:3, Rd 1
BSET #xx:3, @ERd 2 2
BSET #xx:3, @aa:8 2 2
BSET Rn, Rd 1
BSET Rn, @ERd 2 2
BSET Rn, @aa:8 2 2
BSR BSR d:8 Normal 2 1
Advanced 2 2
BSR d:16 Normal 2 1 2
Advanced 2 2 2
BST BST #xx:3, Rd 1
BST #xx:3, @ERd 2 2
BST #xx:3, @aa:8 2 2
BTST BTST #xx:3, Rd 1
BTST #xx:3, @ERd 2 1
BTST #xx:3, @aa: 8 2 1
BTST Rn, Rd 1
BTST Rn, @ERd 2 1
BTST Rn, @aa:8 2 1
BXOR BXOR #x x:3 , Rd 1
BXOR #xx:3, @ERd 2 1
BXOR #xx:3, @aa:8 2 1
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 585 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
CMP CMP.B #xx:8, Rd 1
CMP.B Rs, Rd 1
CMP.W #xx:16, R d 2
CMP.W Rs, Rd 1
CMP.L #xx:32 , ERd 3
CMP.L ERs, ERd 1
DAA DAA Rd 1
DAS DAS Rd 1
DEC DEC.B Rd 1
DEC.W #1/2, Rd 1
DEC.L #1/2, ERd 1
DIVXS DIVXS.B Rs, Rd 2 12
DIVXS.W Rs, ERd 2 20
DIVXU DIVXU.B Rs, Rd 1 12
DIVXU.W Rs, ERd 1 20
EEPMOV EEPMOV.B 2 2 n + 2 *1
EEPMOV.W 2 2 n + 2 *1
EXTS EXTS.W Rd 1
EXTS.L ERd 1
EXTU EXTU.W Rd 1
EXTU.L ERd 1
INC INC.B Rd 1
INC.W #1/2, Rd 1
INC.L #1/2, ER d 1
JMP JMP @ERn 2
JMP @aa:24 2 2
JMP @@aa:8 Normal 2 1 2
Advanced 2 2 2
JSR JSR @ERn Normal 2 1
Advanced 2 2
JSR @aa:24 Normal 2 1 2
Advanced 2 2 2
JSR @@aa:8 Normal 2 1 1
Advanced 2 2 2
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 586 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
LDC LDC #xx:8, CCR 1
LDC Rs, CCR 1
LDC @ERs, CCR 2 1
LDC @(d:16, ERs), CCR 3 1
LDC @(d:24, ERs), CCR 5 1
LDC @ERs+, CCR 2 1 2
LDC @aa:16, CCR 3 1
LDC @aa:24, CCR 4 1
MOV MOV.B #xx: 8, Rd 1
MOV.B Rs, Rd 1
MOV.B @ERs, Rd 1 1
MOV.B @(d:16, ERs), Rd 2 1
MOV.B @(d:24, ERs), Rd 4 1
MOV.B @ERs+, Rd 1 1 2
MOV.B @aa:8, Rd 1 1
MOV.B @aa:16, Rd 2 1
MOV.B @aa:24, Rd 3 1
MOV.B Rs, @ERd 1 1
MOV.B Rs, @(d:16, ERd) 2 1
MOV.B Rs, @(d:24, ERd) 4 1
MOV.B Rs, @–ERd 1 1 2
MOV.B Rs, @aa:8 1 1
MOV.B Rs, @aa:16 2 1
MOV.B Rs, @aa:24 3 1
MOV.W #xx:16, Rd 2
MOV.W Rs, Rd 1
MOV.W @ERs , Rd 1 1
MO V.W @(d:16, ERs), Rd 2 1
MO V.W @(d:24, ERs), Rd 4 1
MOV.W @ERs+, Rd 1 1 2
MOV.W @aa:16, Rd 2 1
MOV.W @aa:24, Rd 3 1
MOV.W Rs, @ER d 1 1
MOV.W Rs, @(d:16, ERd) 2 1
MOV.W Rs, @(d:24, ERd) 4 1
MOV.W Rs, @–ERd 1 1 2
MOV.W Rs, @aa:16 2 1
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 587 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.W Rs, @aa: 24 3 1
MOV.L #xx:32, ERd 3
MOV.L ERs, ERd 1
MOV.L @ERs, ERd 2 2
MOV.L @(d:16, ERs), ERd 3 2
MOV.L @(d:24, ERs), ERd 5 2
MOV.L @ERs+, ERd 2 2 2
MOV.L @aa:16, ERd 3 2
MOV.L @aa:24, ERd 4 2
MOV.L ERs, @ERd 2 2
MOV.L ERs, @(d:16, ERd) 3 2
MOV.L ERs, @(d:24, ERd) 5 2
MOV.L ERs, @–ERd 2 2 2
MOV.L ERs, @aa:16 3 2
MOV.L ERs, @aa:24 4 2
MOVFPE MOVFPE @aa:16, Rd*221
MOVTPE MOVTPE Rs, @aa:16*221
MULXS MULXS.B Rs, Rd 2 12
MULXS.W Rs, ERd 2 20
MULXU MULXU.B Rs, Rd 1 12
MULXU.W Rs, ERd 1 20
NEG NEG.B Rd 1
NEG.W Rd 1
NEG.L ERd 1
NOP NOP 1
NOT NOT.B Rd 1
NOT.W Rd 1
NOT.L ERd 1
OR OR.B #xx:8, Rd 1
OR.B Rs, Rd 1
OR.W #xx:16, Rd 2
OR.W Rs, Rd 1
OR.L #xx:32, ERd 3
OR.L ERs, ERd 2
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 588 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ORC ORC #xx:8, CCR 1
POP POP.W Rn 1 1 2
POP.L ERn 2 2 2
PUSH PUSH.W Rn 1 1 2
PUSH.L ERn 2 2 2
ROTL ROTL.B Rd 1
ROTL.W Rd 1
ROTL.L ERd 1
ROTR ROTR.B Rd 1
ROTR.W Rd 1
ROTR.L ERd 1
ROTXL ROTXL.B Rd 1
ROTXL.W Rd 1
ROTXL.L ERd 1
ROTXR ROTXR.B Rd 1
ROTXR.W Rd 1
ROTXR.L ERd 1
RTE RTE 2 2 2
RTS RTS Normal 2 1 2
Advanced 2 2 2
SHAL SHAL.B Rd 1
SHAL.W Rd 1
SHAL.L ERd 1
SHAR SHAR.B Rd 1
SHAR.W Rd 1
SHAR.L ERd 1
SHLL SHLL.B Rd 1
SHLL.W Rd 1
SHLL.L ERd 1
SHLR SHLR.B Rd 1
SHLR.W Rd 1
SHLR.L ERd 1
SLEEP SLEEP 1
Appendix A Instruction Set
Rev.3.00 Mar. 26, 2007 Page 589 of 682
REJ09B0353-0300
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
STC STC CCR, Rd 1
STC CCR, @ERd 2 1
STC CCR, @(d:16, ERd) 3 1
STC CCR, @(d:24, ERd) 5 1
STC CCR, @–ERd 2 1 2
STC CCR, @aa:16 3 1
STC CCR, @aa:24 4 1
SUB SUB.B Rs, Rd 1
SUB.W #xx:16, Rd 2
SUB.W Rs, Rd 1
SUB.L #xx:32, ERd 3
SUB.L ERs, ERd 1
SUBS SUBS #1/2/4, ERd 1
SUBX SUBX #xx:8, Rd 1
SUBX Rs, Rd 1
TRAPA TRAPA #x:2 Normal 2 1 2 4
Advanced 2 2 2 4
XOR XOR.B #xx:8, Rd 1
XOR.B Rs, Rd 1
XOR.W #xx:16, Rd 2
XOR.W Rs, Rd 1
XOR.L #xx:32, ERd 3
XOR.L ERs, ERd 2
XORC XORC #xx:8, CCR 1
Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n+1
times each.
2. Not used with this LSI.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 590 of 682
REJ09B0353-0300
Appendix B Internal I/O Register Field
B.1 Addresses
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'1C
H'1D
H'1E
H'1F
H'20— ————————
H'21— ————————
H'22— ————————
H'23— ————————
H'24— ————————
H'25— ————————
H'26— ————————
H'27— ————————
H'28— ————————
H'29— ————————
H'2A— ————————
H'2B— ————————
H'2C— ————————
H'2D— ————————
H'2E— ————————
H'2F— ————————
H'30— ————————
H'31— ————————
H'32— ————————
H'33— ————————
H'34— ————————
H'35— ————————
H'36— ————————
H'37— ————————
H'38— ————————
H'39— ————————
H'3A— ————————
H'3B— ————————
H'3C— ————————
H'3D— ————————
H'3E— ————————
H'3F— ————————
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 591 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'40 FLMCR 8 FWE SWE ESU PSU EV PV E P Flash memory
H'41— ————————
H'42 EBR 8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
H'43— ————————
H'44— ————————
H'45— ————————
H'46— ————————
H'47 RAMCR 8 — — — — RAMS RAM2 RAM1 —
H'48— ————————
H'49— ————————
H'4A— ————————
H'4B— ————————
H'4C— ————————
H'4DFLMSR8FLER———————
H'4E— ————————
H'4F— ————————
H'50— ————————
H'51— ————————
H'52— ————————
H'53— ————————
H'54— ————————
H'55— ————————
H'56— ————————
H'57— ————————
H'58— ————————
H'59— ————————
H'5A— ————————
H'5B— ————————
H'5C— ————————
H'5DDIVCR8——————DIV1DIV0System control
H'5E MSTCR 8 PSTOP — MSTOP5 MSTOP4 MSTOP3 — — MSTOP0
H'5F— ————————
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 592 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'60 TSTR 8 — — — STR4 STR3 STR2 STR1 STR0
H'61 TSNC 8 — — — SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 ITU
(all channels)
H'62 TMDR 8 MDF FDIR PWM4 PWM3 PWM2 PWM1 PWM0
H'63 TFCR 8 — — CMD1 CMD0 BFB4 BFA4 BFB3 BFA3
H'64 TCR0 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
H'65 TIOR0 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 ITU
channel 0
H'66 TIER0 8 — — — — — OVIE IMIEB IMIEA
H'67 TSR0 8 — — — — — OVF IMFB IMFA
H'68 TCNT0H 16
H'69 TCNT0L
H'6A GRA0H 16
H'6B GRA0L
H'6C GRB0H 16
H'6D GRB0L
H'6E TCR1 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
H'6F TIOR1 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0 ITU
channel 1
H'70 TIER1 8 — — — — — OVIE IMIEB IMIEA
H'71 TSR1 8 — — — — — OVF IMFB IMFA
H'72 TCNT1H 16
H'73 TCNT1L
H'74 GRA1H 16
H'75 GRA1L
H'76 GRB1H 16
H'77 GRB1L
H'78 TCR2 8 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ITU
channel 2
H'79 TIOR2 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0
H'7A TIER2 8 — — — — — OVIE IMIEB IMIEA
H'7B TSR2 8 — — — — — OVF IMFB IMFA
H'7C TCNT2H 16
H'7D TCNT2L
H'7E GRA2H 16
H'7F GRA2L
H'80 GRB2H 16
H'81 GRB2L
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 593 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'82 TCR3 8 — CCLR1 CCLR0 CKEG1 CKEG0 T PSC2 TPSC1 TPSC0 ITU channel 3
H'83 TIOR3 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0
H'84 TIER3 8 — — — — — OVIE IMIEB IMIEA
H'85TSR38—————OVFIMFBIMFA
H'86 TCNT3H 16
H'87 TCNT3L
H'88 GRA3H 16
H'89 GRA3L
H'8A GRB3H 16
H'8B GRB3L
H'8C BRA3H 16
H'8D BRA3L
H'8E BRB3H 16
H'8F BRB3L
H'90 TOER 8 — — EXB4 EXA4 EB3 EB4 EA4 EA3
H'91TOCR8———XTGD——OLS4OLS3
ITU
(all channel)
H'92 TCR4 8 — CCLR1 CCLR0 CKEG1 CKEG0 T PSC2 TPSC1 TPSC0 ITU channel 4
H'93 TIOR4 8 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0
H'94 TIER4 8 — — — — — OVIE IMIEB IMIEA
H'95TSR48—————OVFIMFBIMFA
H'96 TCNT4H 16
H'97 TCNT4L
H'98 GRA4H 16
H'99 GRA4L
H'9A GRB4H 16
H'9B GRB4L
H'9C BRA4H 16
H'9D BRA4L
H'9E BRB4H 16
H'9F BRB4L
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 594 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'A0 TPMR 8 — — — — G3NOV G2NOV G1NOV G0NOV TPC
H'A1 TPCR 8 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
H'A2 NDERB 8 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
H'A3 NDERA 8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
H'A4 NDRB*18 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8
8 NDR15 NDR14 NDR13 NDR12 — — — —
H'A5 NDRA*18 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0
8 NDR7 NDR6 NDR5 NDR4 — — — —
H'A6 NDRB*18————————
8 — — — — NDR11 NDR10 NDR9 NDR8
H'A7 NDRA*18————————
8 — — — — NDR3 NDR2 NDR1 NDR0
H'A8 TCSR*28OVFWT/IT TME — — CKS2 CKS1 CKS0 WDT
H'A9 TCNT*28
H'AA— ————————
H'AB RSTCSR*
2
8WRSTRSTOE——————
H'AC— ————————
H'AD— ————————
H'AE— ————————
H'AF— ————————
H'B0 SMR 8 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI0
H'B1 BRR 8
H'B2 SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'B3 TDR 8
H'B4 SSR 8 TDRE RDRF ORER FER PER TEND MPB MPBT
H'B5 RDR 8
H'B6 SCMR 8 — — — — SDIR SINV — SMIF Smart card
interface
H'B7
H'B8 SMR 8 C/ACHR PE O/ESTOP MP CKS1 CKS0 SCI1
H'B9BRR8————————
H'BA SCR 8 TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'BBTDR8————————
H'BC SSR 8 TDRE RDRF ORER FER PER TEND MPB MPBT
H'BDRDR8————————
H'BE— ————————
H'BF— ————————
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 595 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'C0 P1DDR 8 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1
H'C1 P2DDR 8 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2
H'C2 P1DR 8 P17P16P15P14P13P12P11P10Port 1
H'C3 P2DR 8 P27P26P25P24P23P22P21P20Port 2
H'C4 P3DDR 8 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3
H'C5— ————————
H'C6 P3DR 8 P37P36P35P34P33P32P31P30Port 3
H'C7— ————————
H'C8 P5DDR 8 — — — — P53DDR P52DDR P51DDR P50DDR Port 5
H'C9 P6DDR 8 — — P65DDR P64DDR P63DDR — — P60DDR Port 6
H'CA P5DR 8 — — — — P53P52P51P50Port 5
H'CB P6DR 8 — — P65P64P63——P6
0Port 6
H'CC— ————————
H'CD P8DDR 8 — — — — — — P81DDR P80DDR Port 8
H'CE P7DR 8 P77P76P75P74P73P72P71P70Port 7
H'CF P8DR 8 — — — — — — P81P80Port 8
H'D0 P9DDR 8 — — P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9
H'D1 PADDR 8 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A
H'D2 P9DR 8 — — P95P94P93P92P91P90Port 9
H'D3 PADR 8 PA7PA6PA5PA4PA3PA2PA1PA0Port A
H'D4 PBDDR 8 PB7DDR — PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B
H'D5— ————————
H'D6 PBDR 8 PB7—PB
5PB4PB3PB2PB1PB0Port B
H'D7— ————————
H'D8 P2PCR 8 P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'D9— ————————
H'DA— ————————
H'DB P5PCR 8 — — — — P53PCR P52PCR P51PCR P50PCR P ort 5
H'DC— ————————
H'DD— ————————
H'DE— ————————
H'DF— ————————
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 596 of 682
REJ09B0353-0300
Bit Names
Address
(low) Register
Name
Data
Bus
Width Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name
H'E0 ADDRAH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
H'E1 ADDRAL 8 AD1 AD0 — — — — — —
H'E2 ADDRBH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E3 ADDRBL 8 AD1 AD0 — — — — — —
H'E4 ADDRCH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E5 ADDRCL 8 AD1 AD0 — — — — — —
H'E6 ADDRDH 8 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E7 ADDRDL 8 AD1 AD0 — — — — — —
H'E8 ADCSR 8 ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'E9 ADCR 8 TRGE — — — — — — —
H'EA— ————————
H'EB— ————————
H'EC— ————————Bus controller
H'ED ASTCR 8 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
H'EE WCR 8 — — — — WMS1 WMS0 WC1 WC0
H'EF WCER 8 WCE7 WCE6 WCE5 WCE4 WCE3 WCE2 WCE1 WCE0
H'F0— ————————
H'F1 MDCR 8 — — — — — MDS2 MDS1 MDS0 System control
H'F2 SYSCR 8 SSBY STS2 STS1 STS0 UE NMIEG — RAME
H'F3 ADRCR 8 A23EA
22EA
21E—————Bus controller
H'F4 ISCR 8 — — IRQ5SC IRQ4SC — — IRQ1SC IRQ0SC Interrupt
controller
H'F5 IER 8 — — IRQ5E IRQ4E — — IRQ1E IRQ0E
H'F6 ISR 8 — — IRQ5F IRQ4F — — IRQ1F IRQ0F
H'F7— ————————
H'F8 IPRA 8 IPRA7 IPRA6 — IPRA4 IPRA3 IPRA2 IPRA1 IPRA0
H'F9 IPRB 8 IPRB7 IPRB6 — — IPRB3 IPRB2 IPRB1 —
H'FA— ————————
H'FB— ————————
H'FC
H'FD— ————————
H'FE— ————————
H'FF— ————————
Legend:
ITU: 16-bit integrated timer unit
TPC: Programmable timing pattern controller
WDT: Watchdog timer
SCI: Serial communication interface
A/D: A/D converter
Notes: 1. The address depends on the output trigger setting.
2. For write access to TCSR, TCNT, and RSTCSR, see section 10.2.4, Notes on Register Access.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 597 of 682
REJ09B0353-0300
B.2 Function
TSTR Timer Start Register H'60 ITU (all channels)
Register
name Address to which
the register is mapped Name of on-chip
supporting
module
Register
acronym
Bit
numbers
Initial bit
values Names of the
bits. Dashes
(—) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
Read only
Write only
Read and write
R
W
R/W
Possible types of access
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
STR4
0
R/W
3
STR3
0
R/W
0
STR0
0
R/W
2
STR2
0
R/W
1
STR1
0
R/W
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 598 of 682
REJ09B0353-0300
FLMCR—Flash Memory Control Register H'40 Flash memory
Bit
Initial value
Read/Write 1/0
R
7
FWE
0
R/W
6
SWE
0
R/W
5
ESU
0
R/W
4
PSU
0
R/W
3
EV
0
R/W
2
PV
0
R/W
1
E
0
R/W
Initial value
Read/Write
Modes
5 and 7
Modes
1 to 4,
and 6 0
R0
R0
R0
R0
R0
R0
R0
R
0
P
0
1
Program mode cleared (Initial value)
Transition to program mode
[Setting condition]
When FWE = 1, SWE = 1, and PSU = 1
Program mode
0
1Erase mode cleared (Initial value)
Transition to erase mode
[Setting condition]
When FWE = 1, SWE = 1, and ESU = 1
Erase mode
0
1Program-verify mode cleared (Initial value)
Transition to program-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
Program-verify mode
0
1Erase-verify mode cleared (Initial value)
Transition to erase-verify mode
[Setting condition]
When FWE = 1 and SWE = 1
Erase-verify mode
0
1
Program setup cleared (Initial value)
Program setup
[Setting condition]
When FWE = 1 and SWE = 1
Program setup
0
1Erase setup cleared (Initial value)
Erase setup
[Setting condition]
When FWE = 1 and SWE = 1
Erase setup
0
1
Program/erase disabled (Initial value)
Program/erase enabled
[Setting condition]
When FWE = 1
Software write enable bit
0
1
When a low level is input to the FWE pin (hardware protection state)
When a high level is input to the FWE pin
Flash write enable bit
Note: This register is used only in the flash memory versions.
Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled.
Fix the FWE pin low in mode 6.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 599 of 682
REJ09B0353-0300
EBR—Erase Block Register H'42 Flash memory
Bit 7
EB7
6
EB6
5
EB5
4
EB4
3
EB3
2
EB2
1
EB1
0
EB0
0
1
Block EB7 to EB0 is not selected (Initial value)
Block EB7 to EB0 is selected
Block 7 to 0
Note: When not erasing flash memory, EBR should be cleared to H'00.
This register is used only in the flash memory versions. Reading the corresponding address
in a mask ROM version will always return 1s, and writes to this address are disabled.
1s cannot be set in this register in mode 6.
Initial value
Read/Write 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W
Initial value
Read/Write
Modes
5 to 7
Modes
1 to 4,
and 6 0
R0
R0
R0
R0
R0
R0
R0
R
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 600 of 682
REJ09B0353-0300
RAMCR—RAM Control Register H'47 Flash Memory
Bit 3 Bit 2 Bit 1
RAMS RAM2 RAM1 RAM Area
0
1
0/1
0
1
0/1
0
1
0
1
RAM Emulation Status
H'FFF000 to H'FFF3FF
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
No emulation
Mapping RAM
RAM select, RAM2, RAM1
Note:
Bit 7
—RAMS
6543210
——— RAM2 RAM1 —
Reserved bits
Modes
1 to 4 1
—1
—1
—1
—0
R0
R0
R1
—
Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7 1
—1
—1
—1
—0
R/W*0
R/W*0
R/W*1
—
This register is used only in the flash memory versions. Reading the corresponding address in
a mask ROM version will always return 1s, and writes to this address are disabled.
* In mode 6 (single-chip normal mode), flash memory emulation by RAM is not supported;
these bits can be modified, but must not be set to 1.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 601 of 682
REJ09B0353-0300
FLMSR—Flash Memory Status Register H'4D Flash memory
Bit 76543210
FLER ————— —
Initial value 0 1 1 1 1 1 1 1
Read/Write R ———————
—
Flash memory error
0
1
Flash memory write/erase protection is disabled (Initial value)
An error has occurred during flash memory writing/erasing
Flash memory error protection is enabled
DIVCR—Division Control Register H'5D System control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
3
—
1
—
0
DIV0
0
R/W
2
—
1
—
1
DIV1
0
R/W
Divide bits 1 and 0
DIV1 Frequency
Division Ratio
DIV0
Bit 0
Bit 1
0
1
1/1initial value
1/2
1/4
1/8
0
0
1
1
7
—
1
—
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 602 of 682
REJ09B0353-0300
MSTCR—Module Standby Control Reg ister H'5E System control
Bit
Initial value
Read/Write
7
PSTOP
0
R/W
6
—
1
—
5
MSTOP5
0
R/W
4
MSTOP4
0
R/W
3
MSTOP3
0
R/W
0
MSTOP0
0
R/W
2
—
0
R/W
1
—
0
R/W
Module standby 0
0 A/D converter operates normally
1 A/D converter is in standby state
Module standby 3
0 SCI1 operates normally
1 SCI1 is in standby state
Module standby 4
0 SCI0 operates normally
1 SCI0 is in standby state
Module standby 5
0 ITU operates normally
1 ITU is in standby state
φ clock stop
0φ clock output is enabled
1φ clock output is disabled
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 603 of 682
REJ09B0353-0300
TSTR—Timer Start Register H'60 ITU (all channels)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
STR4
0
R/W
3
STR3
0
R/W
0
STR0
0
R/W
2
STR2
0
R/W
1
STR1
0
R/W
Counter start 0
0 TCNT0 is halted
1 TCNT0 is counting
Counter start 3
0 TCNT3 is halted
1 TCNT3 is counting
Counter start 1
0 TCNT1 is halted
1 TCNT1 is counting
Counter start 2
0 TCNT2 is halted
1 TCNT2 is counting
Counter start 4
0 TCNT4 is halted
1 TCNT4 is counting
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 604 of 682
REJ09B0353-0300
TSNC—Timer Synchro Register H'61 ITU (all channel s)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
SYNC4
0
R/W
3
SYNC3
0
R/W
0
SYNC0
0
R/W
2
SYNC2
0
R/W
1
SYNC1
0
R/W
Timer sync 0
0 TCNT0 operates independently
1 TCNT0 is synchronized
Timer sync 3
0 TCNT3 operates independently
1 TCNT3 is synchronized
Timer sync 1
0 TCNT1 operates independently
1 TCNT1 is synchronized
Timer sync 2
0 TCNT2 operates independently
1 TCNT2 is synchronized
Timer sync 4
0 TCNT4 operates independently
1 TCNT4 is synchronized
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 605 of 682
REJ09B0353-0300
TMDR—Timer Mode Register H'62 ITU (all channels)
Bit
Initial value
Read/Write
7
—
1
—
6
MDF
0
R/W
5
FDIR
0
R/W
4
PWM4
0
R/W
3
PWM3
0
R/W
0
PWM0
0
R/W
2
PWM2
0
R/W
1
PWM1
0
R/W
PWM mode 0
0 Channel 0 operates normally
1 Channel 0 operates in PWM mode
PWM mode 3
0 Channel 3 operates normally
1 Channel 3 operates in PWM mode
PWM mode 1
0 Channel 1 operates normally
1 Channel 1 operates in PWM mode
PWM mode 2
0 Channel 2 operates normally
1 Channel 2 operates in PWM mode
PWM mode 4
0 Channel 4 operates normally
1 Channel 4 operates in PWM mode
Flag direction
0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows
1 OVF is set to 1 in TSR2 when TCNT2 overflows
Phase counting mode flag
0 Channel 2 operates normally
1 Channel 2 operates in phase counting mode
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 606 of 682
REJ09B0353-0300
TFCR—Timer Function Control Register H'63 ITU (all channels)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
CMD1
0
R/W
4
CMD0
0
R/W
3
BFB4
0
R/W
0
BFA3
0
R/W
2
BFA4
0
R/W
1
BFB3
0
R/W
Buffer mode A3
0 GRA3 operates normally
1 GRA3 is buffered by BRA3
Buffer mode B4
0 GRB4 operates normally
1 GRB4 is buffered by BRB4
Buffer mode B3
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Buffer mode A4
0 GRA4 operates normally
1 GRA4 is buffered by BRA4
Combination mode 1 and 0
Channels 3 and 4 operate normally
Channels 3 and 4 operate together in complementary PWM mode
Channels 3 and 4 operate together in reset-synchronized PWM mode
Bit 5
0
1
Bit 4
0
1
0
1
Operating Mode of Channels 3 and 4
CMD1 CMD0
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 607 of 682
REJ09B0353-0300
TCR0—Timer Control Register 0 H'64 ITU0
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Timer prescaler 2 to 0
Clock edge 1 and 0
Counter clear 1 and 0
TCNT is not cleared
TCNT is cleared by GRB compare match or input capture
Synchronous clear:
Bit 6
0
1
Bit 5
0
0
1
TCNT Clear Source
CCLR1 CCLR0
TCNT is cleared by GRA compare match or input capture1
Rising edges counted
Both edges counted
Bit 4
0
1
Bit 3
0
—
Counted Edges of External Clock
CKEG1CKEG0
Falling edges counted1
TPSC2
1
TCNT Clock Source
Internal clock: φ
Internal clock: φ/2
Internal clock: φ/4
Internal clock: φ/8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
Bit 2 TPSC1
0
1
0
1
Bit 1 TPSC0
0
1
0
1
0
1
Bit 0
0External clock D: TCLKD input1
0
TCNT is cleared in synchronization
with other synchronized timers
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 608 of 682
REJ09B0353-0300
TIOR0—Timer I/O Control Register 0 H'65 ITU0
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
I/O control A2 to A0
IOA2
1
GRA Function
GRA is an output
compare register
GRA is an input
capture register
IOA1
0
1
0
1
Bit 1 IOA0
0
1
0
1
0
1
Bit 0
0
1
0
Bit 2
No output at compare match
0 output at GRA compare match
1 output at GRA compare match
Output toggles at GRA compare match
GRA captures rising edge of input
GRA captures falling edge of input
GRA captures both edges of input
I/O control B2 to B0
IOB2
1
GRB Function
GRB is an output
compare register
GRB is an input
capture register
IOB1
0
1
0
1
Bit 5 IOB0
0
1
0
1
0
1
Bit 4
0
1
0
Bit 6
No output at compare match
0 output at GRB compare match
1 output at GRB compare match
Output toggles at GRB compare match
GRB captures rising edge of input
GRB captures falling edge of input
GRB captures both edges of input
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 609 of 682
REJ09B0353-0300
TIER0—Timer Interrupt Enable Register 0 H'66 ITU0
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMIEA
0
R/W
2
OVIE
0
R/W
1
IMIEB
0
R/W
Input capture/compare match interrupt enable A
0 IMIA interrupt requested by IMFA is disabled
1 IMIA interrupt requested by IMFA is enabled
Input capture/compare match interrupt enable B
0 IMIB interrupt requested by IMFB is disabled
1 IMIB interrupt requested by IMFB is enabled
Overflow interrupt enable
0 OVI interrupt requested by OVF is disabled
1 OVI interrupt requested by OVF is enabled
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 610 of 682
REJ09B0353-0300
TSR0—Timer Status Register 0 H'67 ITU0
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMFA
0
R/(W)
2
OVF
0
R/(W)
1
IMFB
0
R/(W)
Input capture/compare match flag A
0 [Clearing condition]
Overflow flag
***
Read IMFA when IMFA = 1, then write 0 in IMFA
1 [Setting conditions]
• TCNT = GRA when GRA functions as a compare
match register.
• TCNT value is transferred to GRA by an input capture
signal, when GRA functions as an input capture register.
Input capture/compare match flag B
0 [Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
1 [Setting conditions]
• TCNT = GRB when GRB functions as a compare
match register.
• TCNT value is transferred to GRB by an input capture
signal, when GRB functions as an input capture register.
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000
Note: * Only 0 can be written to clear the flag.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 611 of 682
REJ09B0353-0300
TCNT0 H/L—Timer Counter 0 H/L H'68, H'69 ITU0
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
Up-counter
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
GRA0 H/L—General Register A0 H/L H'6A, H'6B ITU0
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Output compare or input capture register
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
GRB0 H/L—General Register B0 H/L H'6C, H'6D ITU0
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Output compare or input capture register
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
TCR1—Timer Control Register 1 H'6E ITU1
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Note: Bit functions are the same as for ITU0.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 612 of 682
REJ09B0353-0300
TIOR1—Timer I/O Control Register 1 H'6F ITU1
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Note: Bit functions are the same as for ITU0.
TIER1—Timer Interrupt Enable Register 1 H'70 ITU1
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMIEA
0
R/W
2
OVIE
0
R/W
1
IMIEB
0
R/W
Note: Bit functions are the same as for ITU0.
TSR1—Timer Status Register 1 H'71 ITU1
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMFA
0
R/(W)
2
OVF
0
R/(W)
1
IMFB
0
R/(W)
Notes:
***
Bit functions are the same as for ITU0.
* Only 0 can be written to clear the flag.
TCNT1 H/L—Timer Counter 1 H/L H'72, H'73 ITU1
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
Note: Bit functions are the same as for ITU0.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 613 of 682
REJ09B0353-0300
GRA1 H/L—General Register A1 H/L H'74, H'75 ITU1
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU0.
GRB1 H/L—General Register B1 H/L H'76, H'77 ITU1
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU0.
TCR2—Timer Control Register 2 H'78 ITU2
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Notes: 1. Bit functions are the same as for ITU0.
2. When channel 2 is used in phase counting mode, the counter clock source selection by
bits CKEG1, CKEG0 and TPSC2 to TPSC0 is ignored.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 614 of 682
REJ09B0353-0300
TIOR2—Timer I/O Control Register 2 H'79 ITU2
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Notes: 1. Bit functions are the same as for ITU0.
2. Channel 2 does not have a compare match toggle output function. If this setting is
used, 1 output will be selected automatically.
TIER2—Timer Interrupt Enable Register 2 H'7A ITU2
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMIEA
0
R/W
2
OVIE
0
R/W
1
IMIEB
0
R/W
Note: Bit functions are the same as for ITU0.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 615 of 682
REJ09B0353-0300
TSR2—Timer Status Register 2 H'7B ITU2
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMFA
0
R/(W)
2
OVF
0
R/(W)
1
IMFB
0
R/(W)
Overflow flag
0 [Clearing condition]
***
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Bit functions are the
same as for ITU0
Note: * Only 0 can be written to clear the flag.
TCNT2 H/L—Timer Counter 2 H/L H'7C, H'7D ITU2
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
Phase counting mode:
Other modes: up-counter
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
up/down-counter
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 616 of 682
REJ09B0353-0300
GRA2 H/L—General Register A2 H/L H'7E, H'7F ITU2
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU0.
GRB2 H/L—General Register B2 H/L H'80, H'81 ITU2
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU0.
TCR3—Timer Control Register 3 H'82 ITU3
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CLEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Note: Bit functions are the same as for ITU0.
TIOR3—Timer I/O Control Register 3 H'83 ITU3
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Note: Bit functions are the same as for ITU0.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 617 of 682
REJ09B0353-0300
TIER3—Timer Interrupt Enable Register 3 H'84 ITU3
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMIEA
0
R/W
2
OVIE
0
R/W
1
IMIEB
0
R/W
Note: Bit functions are the same as for ITU0.
TSR3—Timer Status Register 3 H'85 ITU3
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMFA
0
R/(W)
2
OVF
0
R/(W)
1
IMFB
0
R/(W)
***
Overflow flag
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT overflowed from H'FFFF to H'0000 or underflowed from
H'0000 to H'FFFF
Bit functions are the
same as for ITU0
Note: * Only 0 can be written to clear the flag.
TCNT3 H/L—Timer Counter 3 H/L H'86, H'87 ITU3
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
Complementary PWM mode:
Other modes: up-counter
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
up/down counter
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 618 of 682
REJ09B0353-0300
GRA3 H/L—General Register A3 H/L H'88, H'89 ITU3
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Output compare or input capture register (can be buffered)
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
GRB3 H/L—General Register B3 H/L H'8A, H'8B ITU3
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Output compare or input capture register (can be buffered)
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
BRA3 H/L—Buffer Register A3 H/L H'8C, H'8D ITU3
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Used to buffer GRA
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
BRB3 H/L—Buffer Register B3 H/L H'8E, H'8F ITU3
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
Used to buffer GRB
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 619 of 682
REJ09B0353-0300
TOER—Timer Output Enable Register H'90 ITU (all channels)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
EXB4
1
R/W
4
EXA4
1
R/W
3
EB3
1
R/W
0
EA3
1
R/W
2
EB4
1
R/W
1
EA4
1
R/W
Master enable TIOCA3
0 TIOCA output is disabled regardless of TIOR3, TMDR, and TFCR settings
1 TIOCA is enabled for output according to TIOR3, TMDR, and TFCR settings
Master enable TIOCB3
0 TIOCB output is disabled regardless of TIOR3 and TFCR settings
1 TIOCB is enabled for output according to TIOR3 and TFCR settings
Master enable TIOCA4
0 TIOCA output is disabled regardless of TIOR4, TMDR, and TFCR settings
1 TIOCA is enabled for output according to TIOR4, TMDR, and TFCR settings
Master enable TIOCB4
0 TIOCB output is disabled regardless of TIOR4 and TFCR settings
1 TIOCB is enabled for output according to TIOR4 and TFCR settings
Master enable TOCXA4
0 TOCXA output is disabled regardless of TFCR settings
1 TOCXA is enabled for output according to TFCR settings
Master enable TOCXB4
0 TOCXB output is disabled regardless of TFCR settings
1 TOCXB is enabled for output according to TFCR settings
4
4
4
4
3
3
4
4
4
4
3
3
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 620 of 682
REJ09B0353-0300
TOCR—Timer Output Control Reg ister H'91 ITU (all cha nnels)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
1
R/W
3
—
1
—
0
OLS3
1
R/W
2
—
1
—
1
OLS4
1
R/W
Output level select 3
0 TIOCB , TOCXA , and TOCXB outputs are inverted
1 TIOCB , TOCXA , and TOCXB outputs are not inverted
Output level select 4
0 TIOCA , TIOCA , and TIOCB outputs are inverted
1 TIOCA , TIOCA , and TIOCB outputs are not inverted
External trigger disable
0 Input capture A in channel 1 is used as an external trigger signal in
reset-synchronized PWM mode and complementary PWM mode*
1 External triggering is disabled
XTGD
Note: *When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0,
disabling ITU output.
3
3
3
3
4
4
4
4
4
4
4
4
TCR4—Timer Control Register 4 H'92 ITU4
Bit
Initial value
Read/Write
7
—
1
—
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
CKEG1
0
R/W
3
CKEG0
0
R/W
0
TPSC0
0
R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
Note: Bit functions are the same as for ITU0.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 621 of 682
REJ09B0353-0300
TIOR4—Timer I/O Control Register 4 H'93 ITU4
Bit
Initial value
Read/Write
7
—
1
—
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
—
1
—
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Note: Bit functions are the same as for ITU0.
TIER4—Timer Interrupt Enable Register 4 H'94 ITU4
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMIEA
0
R/W
2
OVIE
0
R/W
1
IMIEB
0
R/W
Note: Bit functions are the same as for ITU0.
TSR4—Timer Status Register 4 H'95 ITU4
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IMFA
0
R/(W)
2
OVF
0
R/(W)
1
IMFB
0
R/(W)
***
Notes: Bit functions are the same as for ITU0.
* Only 0 can be written to clear the flag.
TCNT4 H/L—Timer Counter 4 H/L H'96, H'97 ITU4
Bit
Initial value
Read/Write
14
0
R/W
12
0
R/W
10
0
R/W
8
0
R/W
6
0
R/W
0
0
R/W
4
0
R/W
2
0
R/W
15
0
R/W
13
0
R/W
11
0
R/W
9
0
R/W
7
0
R/W
1
0
R/W
5
0
R/W
3
0
R/W
Note: Bit functions are the same as for ITU3.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 622 of 682
REJ09B0353-0300
GRA4 H/L—General Register A4 H/L H'98, H'99 ITU4
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU3.
GRB4 H/L—General Register B4 H/L H'9A, H'9B ITU4
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU3.
BRA4 H/L—Buffer Register A4 H/L H'9C, H'9D ITU4
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU3.
BRB4 H/L—Buffer Register B4 H/L H'9E, H'9F ITU4
Bit
Initial value
Read/Write
14
1
R/W
12
1
R/W
10
1
R/W
8
1
R/W
6
1
R/W
0
1
R/W
4
1
R/W
2
1
R/W
15
1
R/W
13
1
R/W
11
1
R/W
9
1
R/W
7
1
R/W
1
1
R/W
5
1
R/W
3
1
R/W
Note: Bit functions are the same as for ITU3.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 623 of 682
REJ09B0353-0300
TPMR—TPC Output Mode Register H'A0 TPC
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
G3NOV
0
R/W
0
G0NOV
0
R/W
2
G2NOV
0
R/W
1
G1NOV
0
R/W
Group 3 non-overlap
0 Normal TPC output in group 3
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 3, controlled by compare match
A and B in the selected ITU channel
Group 2 non-overlap
0 Normal TPC output in group 2
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 2, controlled by compare match
A and B in the selected ITU channel
Group 1 non-overlap
0 Normal TPC output in group 1
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 1, controlled by compare match
A and B in the selected ITU channel
Group 0 non-overlap
0 Normal TPC output in group 0
Output values change at compare match A in the selected ITU channel
1 Non-overlapping TPC output in group 0, controlled by compare match
A and B in the selected ITU channel
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 624 of 682
REJ09B0353-0300
TPCR—TPC Output Control Register H'A1 TPC
Bit
Initial value
Read/Write
7
G3CMS1
1
R/W
6
G3CMS0
1
R/W
5
G2CMS1
1
R/W
4
G2CMS0
1
R/W
3
G1CMS1
1
R/W
0
G0CMS0
1
R/W
2
G1CMS0
1
R/W
1
G0CMS1
1
R/W
Group 3 compare match select 1 and 0
TPC output group 3 (TP
15
to TP
12
)* is triggered by compare match in ITU channel 0
TPC output group 3 (TP
15
to TP
12
)* is triggered by compare match in ITU channel 2
TPC output group 3 (TP
15
to TP
12
)* is triggered by compare match in ITU channel 3
Bit 7
0
1
Bit 6
0
0
1
ITU Channel Selected as Output Trigger
G3CMS1 G3CMS0
TPC output group 3 (TP
15
to TP
12
)* is triggered by compare match in ITU channel 11
Group 2 compare match select 1 and 0
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in ITU channel 0
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in ITU channel 2
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in ITU channel 3
Bit 5
0
1
Bit 4
0
0
1
ITU Channel Selected as Output Trigger
G2CMS1 G2CMS0
TPC output group 2 (TP
11
to TP
8
) is triggered by compare match in ITU channel 11
Group 1 compare match select 1 and 0
TPC output group 1 (TP
7
to TP
4
) is triggered by compare match in ITU channel 0
TPC output group 1 (TP
7
to TP
4
) is triggered by compare match in ITU channel 2
TPC output group 1 (TP
7
to TP
4
) is triggered by compare match in ITU channel 3
Bit 3
0
1
Bit 2
0
0
1
ITU Channel Selected as Output Trigger
G1CMS1 G1CMS0
TPC output group 1 (TP
7
to TP
4
) is triggered by compare match in ITU channel 11
Group 0 compare match select 1 and 0
TPC output group 0 (TP
3
to TP
0
) is triggered by compare match in ITU channel 0
TPC output group 0 (TP
3
to TP
0
) is triggered by compare match in ITU channel 2
TPC output group 0 (TP
3
to TP
0
) is triggered by compare match in ITU channel 3
Bit 1
0
1
Bit 0
0
0
1
ITU Channel Selected as Output Trigger
G0CMS1 G0CMS0
TPC output group 0 (TP
3
to TP
0
) is triggered by compare match in ITU channel 11
Note: * Since this LSI does not have a TP
14
pin, the TP
14
signal cannot be output off-chip.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 625 of 682
REJ09B0353-0300
NDERB—Next Data Enable Register B H'A2 TPC
Bit
Initial value
Read/Write
7
NDER15
0
R/W
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
0
NDER8
0
R/W
2
NDER10
0
R/W
1
NDER9
0
R/W
Next data enable 15 to 8
TPC outputs TP to TP * are disabled
(NDR15 to NDR8 are not transferred to PB to PB )
TPC outputs TP to TP * are enabled
(NDR15 to NDR8 are transferred to PB to PB )
Bits 7 to 0
0
1
Description
Note: * Since this LSI does not have a TP
14
pin, the TP
14
signal cannot be
output off-chip.
NDER15 to NDER8
15
15
8
8
7
7
0
0
NDERA—Next Data Enable Register A H'A3 TPC
Bit
Initial value
Read/Write
7
NDER7
0
R/W
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
0
NDER0
0
R/W
2
NDER2
0
R/W
1
NDER1
0
R/W
Next data enable 7 to 0
TPC outputs TP to TP are disabled
(NDR7 to NDR0 are not transferred to PA to PA )
TPC outputs TP to TP are enabled
(NDR7 to NDR0 are transferred to PA to PA )
Bits 7 to 0
0
1
Description
NDER7 to NDER0
7
7
0
0
7
7
0
0
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 626 of 682
REJ09B0353-0300
NDRB—Next Data Register B H'A4/H'A6 TPC
• Same output trigger for TPC output groups 2 and 3
Address H'FFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
NDR11
0
R/W
0
NDR8
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
Next output data for
TPC output group 3*Next output data for
TPC output group 2
Address H'FFA6
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
• Different output triggers for TPC output groups 2 and 3
Address H'FFA4
Bit
Initial value
Read/Write
7
NDR15
0
R/W
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Next output data for
TPC output group 3*
Address H'FFA6
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR11
0
R/W
0
NDR8
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
Next output data for
TPC output group 2
Note: *Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 627 of 682
REJ09B0353-0300
NDRA—Next Data Register A H'A5/H'A7 TPC
• Same output trigger for TPC output groups 0 and 1
Address H'FFA5
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
NDR3
0
R/W
0
NDR0
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
Next output data for
TPC output group 1 Next output data for
TPC output group 0
Address H'FFA7
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
• Different output triggers for TPC output groups 0 and 1
Address H'FFA5
Bit
Initial value
Read/Write
7
NDR7
0
R/W
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Next output data for
TPC output group 1
Address H'FFA7
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
NDR3
0
R/W
0
NDR0
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
Next output data for
TPC output group 0
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 628 of 682
REJ09B0353-0300
TCSR—Timer Control/Status Register H'A8 WDT
Bit
Initial value
Read/Write
7
OVF
0
R/(W)
6
WT/
0
R/W
5
TME
0
R/W
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Overflow flag
Timer mode select
IT
0 [Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
1 [Setting condition]
TCNT changes from H'FF to H'00
0 Interval timer: requests interval timer interrupts
1 Watchdog timer: generates a reset signal
Clock select 2 to 0
0
1
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
0
1
0
1
0
1
0
1
0
1
0φ/40961
Timer enable
0
1TCNT is initialized to H'00 and halted
TCNT is counting
Note: * Only 0 can be written to clear the flag.
*
CKS2 CKS1 CKS0 Description
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 629 of 682
REJ09B0353-0300
TCNT—Timer Counter H'A9 (read), WDT
H'A8 (write)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
RSTCSR—Reset Control/Status Register H'AB (read), WDT
H'AA (write)
Bit
Initial value
Read/Write
7
WRST
0
R/(W)
6
RSTOE
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Reset output enable
0 Reset signal is not output externally
1 Reset signal is output externally
Watchdog timer reset
0 [Clearing condition]
Reset signal input at RES pin, or 0 written by software
1 [Setting condition]
TCNT overflow generates a reset signal
Note: * Only 0 can be written in bit 7 to clear the flag.
*
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 630 of 682
REJ09B0353-0300
SMR—Serial Mode Register H'B0 SCI0
Bit
Initial value
Read/Write
7
C/
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Parity enable
Clock select 1 and 0
CKS1 Clock Source
CKS0
Bit 0
Bit 1
0
1
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
0
0
1
1
A
7
O/
0
R/W
E
0 Parity bit is not added or checked
1 Parity bit is added and checked
Parity mode
0 Even parity
1 Odd parity
Stop bit length
Multiprocessor mode
0 Multiprocessor function disabled
1 Multiprocessor format selected
0 One stop bit
1Two stop bits
Character length
0 8-bit data
1 7-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 631 of 682
REJ09B0353-0300
BRR—Bit Rate Register H'B1 SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Serial communication bit rate setting
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 632 of 682
REJ09B0353-0300
SCR—Serial Contro l Register H'B2 SCI0
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Transmit interrupt enable
0 Transmit-data-empty interrupt request (TXI) is disabled
1 Transmit-data-empty interrupt request (TXI) is enabled
Receive interrupt enable
0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled
1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled
Transmit enable
Clock enable 1 and 0
CKE1
Multiprocessor interrupt enable
0
1
Clock Selection and Output
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Synchronous mode
Asynchronous mode
Bit 1 CKE2
0
1
0
1
Bit 2
Receive enable
Synchronous mode
0 Multiprocessor interrupts are disabled (normal receive operation)
1 Multiprocessor interrupts are enabled
0 Receiving is disabled
1 Receiving is enabled
Transmit-end interrupt enable
0 Transmitting is disabled
1 Transmitting is enabled
0 Transmit-end interrupt requests (TEI) are disabled
1 Transmit-end interrupt requests (TEI) are enabled
Internal clock, SCK pin available for generic input/output
Internal clock, SCK pin used for serial clock output
Internal clock, SCK pin used for clock output
Internal clock, SCK pin used for serial clock output
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
External clock, SCK pin used for clock input
External clock, SCK pin used for serial clock input
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 633 of 682
REJ09B0353-0300
TDR—Transmit Data Register H'B3 SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Serial transmit data
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 634 of 682
REJ09B0353-0300
SSR—Serial Status Register H'B4 SCI0
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Transmit end
0 [Clearing conditions]
1 [Setting conditions]
Reset or transition to standby mode.
TE is cleared to 0 in SCR.
TDRE is 1 when last bit of serial character is transmitted.
*****
Multiprocessor bit transfer
Read TDRE when TDRE = 1, then write 0 in TDRE.
Multiprocessor bit
Parity error
0 [Clearing conditions]
1 [Setting condition]
Parity error: (parity of receive data does not
match parity setting of O/ in SMR)
Reset or transition to standby mode.
Read PER when PER = 1, then write 0 in
PER.
E
Framing error
0 [Clearing conditions]
1 [Setting condition]
Framing error (stop bit is 0)
Reset or transition to standby mode.
Read FER when FER = 1, then write 0
in FER.
Overrun error
0 [Clearing conditions]
1 [Setting condition]
Overrun error (reception of next serial data
ends when RDRF = 1)
Reset or transition to standby mode.
Read ORER when ORER = 1, then write 0 in
ORER.
Receive data register full
0 [Clearing conditions]
1 [Setting condition]
Serial data is received normally and transferred
from RSR to RDR
Reset or transition to standby mode.
Read RDRF when RDRF = 1, then write 0 in
RDRF.
Transmit data register empty
0 [Clearing conditions]
1 [Setting conditions]
Reset or transition to standby mode.
TE is 0 in SCR
Data is transferred from TDR to TSR, enabling new
data to be written in TDR.
Read TDRE when TDRE = 1, then write 0 in TDRE.
0 Multiprocessor bit value in
receive data is 0
1 Multiprocessor bit value in
receive data is 1
0 Multiprocessor bit value in
transmit data is 0
1 Multiprocessor bit value in
transmit data is 1
Note: * Only 0 can be written to clear the flag.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 635 of 682
REJ09B0353-0300
RDR—Receive Data Register H'B5 SCI0
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Serial receive data
SCMR—Smart Card Mode Register H'B6 SCI0
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
SDIR
0
R/W
0
SMIF
0
R/W
2
SINV
0
R/W
1
—
1
—
Smart card interface mode select
0 Smart card interface function is disabled
1 Smart card interface function is enabled
Smart card data invert
0 Unmodified TDR contents are transmitted
Received data is stored unmodified in RDR
1 Inverted 1/0 logic levels of TDR contents are transmitted
1/0 logic levels of received data are inverted before storage in RDR
Smart card data transfer direction
0 TDR contents are transmitted LSB-first
Received data is stored LSB-first in RDR
1 TDR contents are transmitted MSB-first
Received data is stored MSB-first in RDR
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 636 of 682
REJ09B0353-0300
SMR—Serial Mode Register H'B8 SCI1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
7
C/
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
A
7
O/
0
R/W
E
BRR—Bit Rate Register H'B9 SCI1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
SCR—Serial Contro l Register H'BA SCI1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
TDR—Transmit Data Register H'BB SCI1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 637 of 682
REJ09B0353-0300
SSR—Serial Status Register H'BC SCI1
Bit
Initial value
Read/Write
Notes: Bit functions are the same as for SCI0.
* Only 0 can be written to clear the flag.
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
* * * * *
RDR—Receive Data Register H'BD SCI1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI0.
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
P1DDR—Port 1 Data Direction Register H'C0 Port 1
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
P1 DDR
1
—
0
W
7
6
P1 DDR
1
—
0
W
6
5
P1 DDR
1
—
0
W
5
4
P1 DDR
1
—
0
W
4
3
P1 DDR
1
—
0
W
3
2
P1 DDR
1
—
0
W
2
1
P1 DDR
1
—
0
W
1
0
P1 DDR
1
—
0
W
0
Port 1 input/output select
0 Generic input pin
1 Generic output pin
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 638 of 682
REJ09B0353-0300
P2DDR—Port 2 Data Direction Register H'C1 Port 2
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
P2 DDR
1
—
0
W
7
6
P2 DDR
1
—
0
W
6
5
P2 DDR
1
—
0
W
5
4
P2 DDR
1
—
0
W
4
3
P2 DDR
1
—
0
W
3
2
P2 DDR
1
—
0
W
2
1
P2 DDR
1
—
0
W
1
0
P2 DDR
1
—
0
W
0
Port 2 input/output select
0 Generic input pin
1 Generic output pin
P1DR—Port 1 Data Register H'C2 Port 1
Bit
Initial value
Read/Write
7
P17
0
R/W
6
P16
0
R/W
5
P15
0
R/W
4
P14
0
R/W
3
P13
0
R/W
0
P10
0
R/W
2
P12
0
R/W
1
P11
0
R/W
Data for port 1 pins
P2DR—Port 2 Data Register H'C3 Port 2
Bit
Initial value
Read/Write
7
P27
0
R/W
6
P26
0
R/W
5
P25
0
R/W
4
P24
0
R/W
3
P23
0
R/W
0
P20
0
R/W
2
P22
0
R/W
1
P21
0
R/W
Data for port 2 pins
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 639 of 682
REJ09B0353-0300
P3DDR—Port 3 Data Direction Register H'C4 Port 3
Bit
Initial value
Read/Write
7
P3 DDR
0
W
7
6
P3 DDR
0
W
6
5
P3 DDR
0
W
5
4
P3 DDR
0
W
4
3
P3 DDR
0
W
3
2
P3 DDR
0
W
2
1
P3 DDR
0
W
1
0
P3 DDR
0
W
0
Port 3 input/output select
0 Generic input pin
1 Generic output pin
P3DR—Port 3 Data Register H'C6 Port 3
Bit
Initial value
Read/Write
7
P3
0
R/W
7
6
P3
0
R/W
6
5
P3
0
R/W
5
4
P3
0
R/W
4
3
P3
0
R/W
3
2
P3
0
R/W
2
1
P3
0
R/W
1
0
P3
0
R/W
0
Data for port 3 pins
P5DDR—Port 5 Data Direction Register H'C8 Port 5
Bit
Modes
1 and 3 Initial value
Read/Write
Initial value
Read/Write
Modes
5 to 7
7
—
1
—
1
—
6
—
1
—
1
—
5
—
1
—
1
—
4
—
1
—
1
—
3
P5 DDR
1
—
0
W
3
2
P5 DDR
1
—
0
W
2
1
P5 DDR
1
—
0
W
1
0
P5 DDR
1
—
0
W
0
Port 5 input/output select
0 Generic input
1 Generic output
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 640 of 682
REJ09B0353-0300
P6DDR—Port 6 Data Direction Register H'C9 Port 6
Bit
Initial value
Read/Write
7
—
1
—
6
—
0
W
5
P6 DDR
0
W
5
4
P6 DDR
0
W
4
3
P6 DDR
0
W
3
2
—
0
W
1
—
0
W
0
P6 DDR
0
W
0
Port 6 input/output select
0 Generic input
1 Generic output
P5DR—Port 5 Data Register H'CA Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
P5
3
0
R/W
2
P5
2
0
R/W
1
P5
1
0
R/W
0
P5
0
0
R/W
Data for port 5 pins
P6DR—Port 6 Data Register H'CB Port 6
Bit
Initial value
Read/Write
7
—
1
—
6
—
0
R/W
5
P6
0
R/W
5
4
P6
0
R/W
4
3
P6
0
R/W
3
2
—
0
R/W
1
—
0
R/W
0
P6
0
R/W
0
Data for port 6 pins
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 641 of 682
REJ09B0353-0300
P8DDR—Port 8 Data Direction Register H'CD Port 8
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
W
3
—
0
W
2
—
0
W
1
P8 DDR
0
W
1
0
P8 DDR
0
W
0
Port 8 input/output select
0 Generic input
1 Generic output
P7DR—Port 7 Data Register H'CE Port 7
Bit
Initial value
Read/Write
0
P7
—
R
*
Note: * Determined by pins P77 to P70.
0
1
P7
—
R
*
1
2
P7
—
R
*
2
3
P7
—
R
*
3
4
P7
—
R
*
4
5
P7
—
R
*
5
6
P7
—
R
*
6
7
P7
—
R
*
7
Data for port 7 pins
P8DR—Port 8 Data Register H'CF Port 8
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
R/W
3
—
0
R/W
2
—
0
R/W
1
P8
0
R/W
1
0
P8
0
R/W
0
Data for port 8 pins
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 642 of 682
REJ09B0353-0300
P9DDR—Port 9 Data Direction Register H'D0 Port 9
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P95DDR
0
W
4
P9 DDR
0
W
4
3
P93DDR
0
W
2
P9 DDR
0
W
2
1
P91DDR
0
W
0
P9 DDR
0
W
0
Port 9 input/output select
0 Generic input
1 Generic output
PADDR—Port A Data Direction Register H'D1 Port A
Bit
Initial value
Read/Write
Initial value
Read/Write
7
PA DDR
1
—
0
W
7
6
PA DDR
0
W
0
W
6
5
PA DDR
0
W
0
W
5
4
PA DDR
0
W
0
W
4
3
PA DDR
0
W
0
W
3
2
PA DDR
0
W
0
W
2
1
PA DDR
0
W
0
W
1
0
PA DDR
0
W
0
W
0
Port A input/output select
0 Generic input
1 Generic output
Mode 3
Modes
1 and 5
to 7
P9DR—Port 9 Data Register H'D2 Port 9
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
P95
0
R/W
4
P94
0
R/W
3
P93
0
R/W
2
P92
0
R/W
1
P91
0
R/W
0
P90
0
R/W
Data for port 9 pins
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 643 of 682
REJ09B0353-0300
PADR—Port A Data Register H'D3 Port A
Bit
Initial value
Read/Write
0
PA
0
R/W
0
1
PA
0
R/W
1
2
PA
0
R/W
2
3
PA
0
R/W
3
4
PA
0
R/W
4
5
PA
0
R/W
5
6
PA
0
R/W
6
7
PA
0
R/W
7
Data for port A pins
PBDDR—Port B Data Direction Register H'D4 Port B
Bit
Initial value
Read/Write
7
PB DDR
0
W
7
6
—
0
W
5
PB DDR
0
W
5
4
PB DDR
0
W
4
3
PB DDR
0
W
3
2
PB DDR
0
W
2
1
PB DDR
0
W
1
0
PB DDR
0
W
0
Port B input/output select
0 Generic input
1 Generic output
PBDR—Port B Data Register H'D6 Port B
Bit
Initial value
Read/Write
0
PB
0
R/W
0
1
PB
0
R/W
1
2
PB
0
R/W
2
3
PB
0
R/W
3
4
PB
0
R/W
4
5
PB
0
R/W
5
6
—
0
R/W
7
PB
0
R/W
7
Data for port B pins
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 644 of 682
REJ09B0353-0300
P2PCR—Port 2 Input Pull-Up Control Register H 'D8 Port 2
Bit
Initial value
Read/Write
7
P2 PCR
0
R/W
7
6
P2 PCR
0
R/W
6
5
P2 PCR
0
R/W
5
4
P2 PCR
0
R/W
4
3
P2 PCR
0
R/W
3
2
P2 PCR
0
R/W
2
1
P2 PCR
0
R/W
1
0
P2 PCR
0
R/W
0
Port 2 input pull-up control 7 to 0
0 Input pull-up transistor is off
1 Input pull-up transistor is on
Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input).
P5PCR—Port 5 Input Pull-Up Control Register H 'DB Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
P5 PCR
0
R/W
3
2
P5 PCR
0
R/W
2
1
P5 PCR
0
R/W
1
0
P5 PCR
0
R/W
0
Port 5 input pull-up control 3 to 0
0 Input pull-up transistor is off
1 Input pull-up transistor is on
Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input).
ADDRA H/L—A/D Data Register A H/L H'E0, H'E1 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRAH ADDRAL
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 645 of 682
REJ09B0353-0300
ADDRB H/L—A/D Data Register B H/L H'E2, H'E3 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRBH ADDRBL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRC H/L—A/D Data Register C H/L H'E4, H'E5 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRCH ADDRCL
A/D conversion data
10-bit data giving an
A/D conversion result
ADDRD H/L—A/D Data Register D H/L H'E6, H'E7 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRDH ADDRDL
A/D conversion data
10-bit data giving an
A/D conversion result
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 646 of 682
REJ09B0353-0300
ADCR—A/D Control Reg ister H'E9 A/D
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Trigger enable
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the fall of the external trigger signal ( )ADTRG
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 647 of 682
REJ09B0353-0300
ADCSR—A/D Control/Sta tus Register H'E8 A/D
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W*
Note: * Only 0 can be written to clear flag.
Channel select 2 to 0
CH2
1
Single Mode
AN
AN
AN
AN
AN
AN
AN
CH1
0
1
0
1
Channel
Selection
CH0
0
1
0
1
0
1
0
1
00
1
2
3
4
5
6
AN7
Scan Mode
AN
AN , AN
AN to AN
AN to AN
AN
AN , AN
AN to AN
0
0
0
0
4
4
4
AN to AN
4
1
5
2
3
6
7
Description
Group
Selection
A/D end flag
A/D interrupt enable
A/D start
Clock select
Scan mode
0 [Clearing condition]
Read ADF while ADF = 1, then write 0 in ADF
1 [Setting conditions]
Single mode:
Scan mode:
0 A/D end interrupt request is disabled
1 A/D end interrupt request is enabled
0 A/D conversion is stopped
1 Single mode:
Scan mode:
0 Single mode
1 Scan mode
0 Conversion time = 266 states (maximum)
1 Conversion time = 134 states (maximum)
A/D conversion ends
A/D conversion ends in all selected channels
A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a
transition to standby mode
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 648 of 682
REJ09B0353-0300
ASTCR—Access State Control Register H'ED Bus controller
Bit
Initial value
Read/Write
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
0
AST0
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
Area 7 to 0 access state control
Areas 7 to 0 are two-state access areas
Areas 7 to 0 are three-state access areas
Bits 7 to 0
0
1
Number of States in Access Cycle
AST7 to AST0
WCR—Wait Control Register H'EE Bus controller
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
WMS1
0
R/W
0
WC0
1
R/W
2
WMS0
0
R/W
1
WC1
1
R/W
Wait count 1 and 0
WC1 Number of Wait States
WC0
Bit 0
Bit 1
0
1
No wait states inserted by
wait-state controller
1 state inserted
2 states inserted
3 states inserted
0
0
1
1
Wait mode select 1 and 0
WMS1 Wait Mode
WMS0
Bit 2
Bit 3
0
1
Programmable wait mode
No wait states inserted by
wait-state controller
Pin wait mode 1
Pin auto-wait mode
0
0
1
1
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 649 of 682
REJ09B0353-0300
WCER—Wait Controller Enable Register H'EF Bus controller
Bit
Initial value
Read/Write
7
WCE7
1
R/W
6
WCE6
1
R/W
5
WCE5
1
R/W
4
WCE4
1
R/W
3
WCE3
1
R/W
0
WCE0
1
R/W
2
WCE2
1
R/W
1
WCE1
1
R/W
Wait state controller enable 7 to 0
0 Wait-state control is disabled (pin wait mode 0)
1 Wait-state control is enabled
MDCR—Mode Control Register H'F1 System control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—
R
2
MDS2
—*
R
1
MDS1
—
R
**
Note: * Determined by the state of the mode pins (MD
2
to MD
0
).
Mode select 2 to 0
Operating mode
—
Mode 1
—
Mode 3
MD
1
0
1
Bit 1 MD
0
0
1
0
1
Bit 0
Bit 2
MD
2
0
—
Mode 7
Mode 5
0
10
1
0
1
1Mode 6
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 650 of 682
REJ09B0353-0300
SYSCR—System Control Register H'F 2 System control
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
UE
1
R/W
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Software standby
0 SLEEP instruction causes transition to sleep mode
1 SLEEP instruction causes transition to software standby mode
Standby timer select 2 to 0
STS2
0
1
Standby Timer
Waiting time = 8192 states
Waiting time = 16384 states
Waiting time = 32768 states
Waiting time = 65536 states
Waiting time = 131072 states
Illegal setting
Bit 6 STS1
0
1
0
1
Bit 5 STS0
0
1
0
1
—
Bit 4
RAM enable
0 On-chip RAM is disabled
1 On-chip RAM is enabled
NMI edge select
0 An interrupt is requested at the falling edge of NMI
1 An interrupt is requested at the rising edge of NMI
User bit enable
0 CCR bit 6 (UI) is used as an interrupt mask bit
1 CCR bit 6 (UI) is used as a user bit
—
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 651 of 682
REJ09B0353-0300
ADRCR—Address Co ntro l Register H'F3 Bus controller
Bit
Initial value
Read/Write
Initial value
Read/Write
Modes
1 and
5 to 7
Mode 3
7
A
23
E
1
—
1
R/W
6
A
22
E
1
—
1
R/W
5
A
21
E
1
—
1
R/W
4
—
1
—
1
—
3
—
1
—
1
—
0
—
0
R/W
0
R/W
2
—
1
—
1
—
1
—
1
—
1
—
Address 23 to 21 enable
0 Address output
1 I/O pins other than the above
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 652 of 682
REJ09B0353-0300
ISCR—IRQ Sense Control Register H'F4 Interrupt controller
Bit
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
—
0
R/W
2
—
0
R/W
1
IRQ1SC
0
R/W
0
IRQ0SC
0
R/W
IRQ
5
, IRQ
4
, IRQ
1
and IRQ
0
sense control
0 Interrupts are requested when IRQ
5
, IRQ
4
, IRQ
1
, and IRQ
0
inputs are low
1 Interrupts are requested by falling-edge input at IRQ
5
, IRQ
4
,
IRQ
1
and IRQ
0
IER—IRQ Enable Register H'F5 Interrupt controller
Bit
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
—
0
R/W
2
—
0
R/W
1
IRQ1E
0
R/W
0
IRQ0E
0
R/W
IRQ
5
, IRQ
4
, IRQ
1
, IRQ
0
enable
0 IRQ
5
, IRQ
4
, IRQ
1
and IRQ
0
interrupts are disabled
1 IRQ
5
, IRQ
4
, IRQ
1
and IRQ
0
interrupts are enabled
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 653 of 682
REJ09B0353-0300
ISR—IRQ Status Register H'F6 Interrupt controller
Bit
Initial value
Read/Write
7
—
0
—
6
—
0
—
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
R/(W) *
3
—
0
—
2
—
0
—
1
IRQ1F
0
R/(W) *
0
IRQ0F
0
R/(W) *
IRQ5, IRQ4, IRQ1 and IRQ0 flags
Bits 5, 4, 1 and 0
0
1
Setting and Clearing Conditions
IRQ5F
IRQ4F
IRQ1F
IRQ0F [Clearing conditions]
• Read IRQnF when IRQnF = 1, then write 0 in IRQnF.
• IRQnSC = 0, IRQn input is high, and interrupt exception
handling is carried out.
• IRQnSC = 1 and IRQn interrupt exception handling is
carried out.
[Setting conditions]
• IRQnSC = 0 and IRQn input is low.
• IRQnSC = 1 and IRQn input changes from high to low.
Note: n = 5, 4, 1 and 0
Note: * Only 0 can be written to clear the flag.
Appendix B Internal I/O Register Field
Rev.3.00 Mar. 26, 2007 Page 654 of 682
REJ09B0353-0300
IPRA—Interrupt Priority Register A H'F8 Interrupt controller
Bit
Initial value
Read/Write
7
IPRA7
0
R/W
6
IPRA6
0
R/W
5
—
0
R/W
4
IPRA4
0
R/W
3
IPRA3
0
R/W
0
IPRA0
0
R/W
2
IPRA2
0
R/W
1
IPRA1
0
R/W
Priority level A7, A6, A4 to A0
0 Priority level 0 (low priority)
1 Priority level 1 (high priority)
• Interrupt sources controlled by each bit
Bit 7
IPRA7 Bit 6
IPRA6 Bit 5
—Bit 4
IPRA4 Bit 3
IPRA3 Bit 2
IPRA2 Bit 1
IPRA1 Bit 0
IPRA0
Interrupt
source IRQ0IRQ1— IRQ4,
IRQ5
WDT ITU
channel
0
ITU
channel
1
ITU
channel 2
IPRB—Interrupt Priority Register B H'F9 Interrupt controller
Bit
Initial value
Read/Write
7
IPRB7
0
R/W
6
IPRB6
0
R/W
5
—
0
R/W
4
—
0
R/W
3
IPRB3
0
R/W
0
—
0
R/W
2
IPRB2
0
R/W
1
IPRB1
0
R/W
Priority level B7, B6, B3 to B1
0 Priority level 0 (low priority)
1 Priority level 1 (high priority)
• Interrupt sources controlled by each bit
Bit 7
IPRB7 Bit 6
IPRB6 Bit 5
—Bit 4
—Bit 3
IPRB3 Bit 2
IPRB2 Bit 1
IPRB1 Bit 0
—
Interrupt
source ITU
channel
3
ITU
channel
4
——SCI
channel
0
SCI
channel
1
A/D
converter —
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 655 of 682
REJ09B0353-0300
Appendix C I/O Block Diagrams
C.1 Port 1 Block Diagram
Modes 1, 3, and 5
Internal data bus (upper)
Internal address bus
P1
n
DDR
Reset
RS
QD
C
Reset
R
QD
P1
n
DR
WP1D
WP1
C
RP1
Modes 1, 3, and 5
Modes 6 and 7
Modes 6 and 7
P1
n
*
Software standby
Hardware standby
WP1D:
WP1:
RP1:
Notes: n = 0 to 7
* Set priority
Legend:Write to P1DDR
Write to port 1
Read port 1
Figure C.1 Port 1 Block Diagram
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 656 of 682
REJ09B0353-0300
C.2 Port 2 Block Diagram
Modes 1, 3, and 5
Internal data bus (upper)
Internal address bus
P2
n
DDR
Reset
RS
QD
C
Reset
R
QD
P2
n
DR
WP2D
WP2
C
RP2
Modes
1, 3, and 5
Modes 6 and 7
Modes
6 and 7
P2
n
*
Software standby
Hardware standby
WP2P:
RP2P:
WP2D:
WP2:
RP2:
Notes: n = 0 to 7
* Set priority
Write to P2PCR
Read P2PCR
Write to P2DDR
Write to port 2
Read port 2
Reset
R
QD
P2
n
PCR
WP2P
C
RP2P
Legend:
Figure C.2 Port 2 Block Diagram
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 657 of 682
REJ09B0353-0300
C.3 Port 3 Block Diagram
Internal data bus (upper)
Internal data bus (lower)
P3
n
DDR
Reset
Modes 6 and 7 R
QD
C
Reset
R
QD
P3
n
DR
WP3D
WP3
C
RP3
Modes
1, 3, and 5
Modes 6 and 7
P3
n
WP3D:
WP3:
RP3:
Note: n = 0 to 7
Write to P3DDR
Write to port 3
Read port 3
Write to external
address
Hardware
standby
Read external
address
Legend:
Figure C.3 Port 3 Block Diagram
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 658 of 682
REJ09B0353-0300
C.4 Port 5 Block Diagram
Internal data bus (upper)
Internal address bus
P5
n
DDR
Reset
RS
QD
C
Reset
R
QD
P5
n
DR
WP5D
WP5
C
RP5
Modes
1, 3, and 5
Modes 6 and 7
Modes
6 and 7
P5
n
*
Software standby
Hardware standby
WP5P:
RP5P:
WP5D:
WP5:
RP5:
Notes: n = 0 to 3
* Set priority
Write to P5PCR
Read P5PCR
Write to P5DDR
Write to port 5
Read port 5
Reset
R
QD
P5
n
PCR
WP5P
C
RP5P
Modes 1, 3
Legend:
Figure C.4 Port 5 Block Diagram
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 659 of 682
REJ09B0353-0300
C.5 Port 6 Block Diagram
P60DDR
Reset
R
QD
C
Reset
R
QD
P60DR
WP6D
WP6
C
RP6
P60
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
Internal data bus
Bus controller
WAIT
input
enable
Bus controller
WAIT
output
Modes
6 and 7
Legend:
Figure C.5 (a) Port 6 Block Diagram (Pin P60)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 660 of 682
REJ09B0353-0300
Internal data bus
P6
n
DDR
Reset
R
QD
C
Reset
R
QD
P6
n
DR
WP6D
WP6
C
RP6
Modes 6 and 7
Modes 6 and 7
P6
n
Software standby
Hardware standby
WP6D:
WP6:
RP6:
Note: n = 3 to 5
Write to P6DDR
Write to port 6
Read port 6
AS output
RD output
WR output
Modes
1, 3,
and 5
Legend:
Figure C.5 (b) Po rt 6 Block Diagram (Pins P63 to P65)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 661 of 682
REJ09B0353-0300
C.6 Port 7 Block Diagram
Internal data bus
P7
n
RP7: Read port 7
Note: n = 0 to 7
A/D converter
Analog input
RP7
Input enable
Legend:
Figure C.6 Port 7 Block Diagram
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 662 of 682
REJ09B0353-0300
C.7 Port 8 Block Diagram
Internal data bus
P8
0
DDR
Reset
R
QD
C
Reset
R
QD
P8
0
DR
WP8D
WP8
C
RP8
P8
0
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
Interrupt
controller
IRQ
0
input
Legend:
Figure C.7(a) Port 8 Block Diagram (Pin P80)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 663 of 682
REJ09B0353-0300
Internal data bus
P8
1
DDR
Reset
R
QD
C
Reset
R
QD
P8
1
DR
WP8D
WP8
C
RP8
Modes
6 and 7
Modes
1, 3, and 5
P8
1
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
Interrupt
controller
IRQ
1
input
Legend:
Figure C.7 (b) Po rt 8 Block Diagram (Pin P81)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 664 of 682
REJ09B0353-0300
C.8 Port 9 Block Diagram
Internal data bus
P9
0
DDR
Reset
QD
C
Reset
R
QD
P9
0
DR
WP9D
WP9
C
RP9
P9
0
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
SCI0
R
Output enable
Guard time
Serial transmit
data
Legend:
Figure C.8 (a) Port 9 Block Diagram (Pin P90)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 665 of 682
REJ09B0353-0300
Internal data bus
P9
1
DDR
Reset
QD
C
Reset
R
QD
P9
1
DR
WP9D
WP9
C
RP9
P9
1
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
SCI1
R
Output enable
Serial transmit
data
Legend:
Figure C.8 (b) Po rt 9 Block Diagram (Pin P91)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 666 of 682
REJ09B0353-0300
Internal data bus
P9
n
DDR
Reset
QD
C
Reset
R
QD
P9
n
DR
WP9D
WP9
C
RP9
P9
n
WP9D:
WP9:
RP9:
Note: n = 2, 3
Write to P9DDR
Write to port 9
Read port 9
SCI
R
Input
enable
Serial receive
data
Legend:
Figure C.8 (c) Port 9 Block Diagram (Pin P92, P9 3)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 667 of 682
REJ09B0353-0300
Internal data bus
P9
n
DDR
Reset
QD
C
Reset
R
QD
P9
n
DR
WP9D
WP9
C
RP9
P9
n
WP9D:
WP9:
RP9:
Note: n = 4 and 5
Write to P9DDR
Write to port 9
Read port 9
SCI
R
Clock input
enable
Clock output
Clock output
enable
Clock input
Interrupt controller
IRQ
4,
IRQ
5
input
Legend:
Figure C.8 (d) Po rt 9 Block Diagram (Pin P94, P95)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 668 of 682
REJ09B0353-0300
C.9 Port A Block Diagram
Internal data bus
PA
n
DDR
Reset
QD
C
Reset
R
QD
PA
n
DR
WPAD
C
PA
n
WPAD:
WPA:
RPA:
Note: n = 0 or 1
Write to PADDR
Write to port A
Read port A
TPC
R
TPC output
enable
Output trigger
Next data
Counter
input
clock
RPA
WPA
ITU
Legend:
Figure C.9 (a) Port A Block Diagram (Pins PA0, PA1)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 669 of 682
REJ09B0353-0300
Internal data bus
PA
n
DDR
Reset
QD
C
Reset
R
QD
PA
n
DR
WPAD
C
PA
n
WPAD:
WPA:
RPA:
Note: n = 2 or 3
Write to PADDR
Write to port A
Read port A
TPC
R
TPC output
enable
Output trigger
Next data
Input capture
input
RPA
WPA
ITU
Output enable
Compare
match output
Counter input
clock
Legend:
Figure C.9 (b) Po rt A Block Diagram (Pins PA2, PA3)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 670 of 682
REJ09B0353-0300
PA
n
DDR
Reset
Software standby
Address output enable
Mode 3
QD
C
Reset
R
QD
PA
n
DR
WPAD
C
PA
n
WPAD:
WPA:
RPA:
Notes: n = 4 to 7
PA
7
address output enable is fixed at 1 in mode 3.
Write to PADDR
Write to port A
Read port A
R
RPA
WPA
Internal data bus
Internal address bus
TPC
TPC output
enable
Output trigger
Next data
ITU
Output enable
Compare
match output
Input capture
input
Legend:
Figure C.9 (c) Port A Block Diagram (Pins PA4 to PA7)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 671 of 682
REJ09B0353-0300
C.10 Port B Block Diagram
Internal data bus
PB
n
DDR
Reset
QD
C
Reset
R
QD
PB
n
DR
WPBD
C
PB
n
WPBD:
WPB:
RPB:
Note: n = 0 to 3
Write to PBDDR
Write to port B
Read port B
TPC
R
TPC output
enable
Output trigger
Next data
RPB
WPB
ITU
Compare
match output
Input capture
input
Output enable
Legend:
Figure C.10 (a) Port B Block Diagram (Pins PB0 to PB3)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 672 of 682
REJ09B0353-0300
Internal data bus
PB
n
DDR
Reset
QD
C
Reset
R
QD
PB
n
DR
WPBD
C
PB
n
WPBD:
WPB:
RPB:
Note: n = 4 or 5
Write to PBDDR
Write to port B
Read port B
TPC
R
TPC output
enable
Output trigger
Next data
RPB
WPB
ITU
Output enable
Compare
match output
Legend:
Figure C.10 (b) Port B Block Diagram (Pins PB4, PB5)
Appendix C I/O Block Diagrams
Rev.3.00 Mar. 26, 2007 Page 673 of 682
REJ09B0353-0300
PB
7
DDR
Reset
QD
C
Reset
R
QD
PB
7
DR
WPBD
C
PB
7
WPBD:
WPB:
RPB:
Write to PBDDR
Write to port B
Read port B
TPC
R
TPC output
enable
Output trigger
Next data
RPB
WPB
Internal data bus
A/D converter
ADTRG
input
Legend:
Figure C.10 (c) Port B Block Diagram (Pin PB7)
Appendix D Pin States
Rev.3.00 Mar. 26, 2007 Page 674 of 682
REJ09B0353-0300
Appendix D Pin States
D.1 Port States in Each Mode
Table D.1 Port St ates
Pin Name Mode Reset
State Hardware
Standby Mode Software
Standby Mode Program Execution
State Sleep Mode
φ—Clock
output T H Clock output
RESO*1—T*2TTRESO
P17 to P101, 3 L T T A7 to A0
5 T T keep Input port (DDR = 0)
TA
7 to A0 (DDR = 1)
6, 7 T T keep I/O port
P27 to P201, 3 L T T A15 to A8
5 T T keep Input port (DDR = 0)
TA
15 to A8 (DDR = 1)
6, 7 T T keep I/O port
P37 to P301, 3, 5 T T T D7 to D0
6, 7 T T keep I/O port
P53 to P501, 3 L T T A19 to A16
5 T T keep Input port (DDR = 0)
TA
19 to A16 (DDR = 1)
6, 7 T T keep I/O port
P601, 3, 5 T T keep I/O port, WAIT
6, 7 T T keep I/O port
P65 to P631, 3, 5 H T T WR, RD, AS
6, 7 T T keep I/O port
P77 to P701, 3, 5 to 7 T T T Input port
P801, 3, 5 T T keep I/O port
6, 7 T T keep I/O port
Appendix D Pin States
Rev.3.00 Mar. 26, 2007 Page 675 of 682
REJ09B0353-0300
Pin Name Mode Reset
State Hardware
Standby Mode Software
Standby Mode Program Execution
State Sleep Mode
P811, 3, 5 T T T [DDR = 0] Input port [DDR = 0]
H [DDR = 1] H [DDR = 1]
6, 7 T T keep I/O port
P95 to P901, 3, 5 to 7 T T keep I/O port
PA 3 to PA 01, 3, 5 to 7 T T keep I/O port
PA6 to PA43 T T [ADRCR = 0]
T
[ADRCR = 1]
keep
(ADRCR = 0)
A21 to A23
(ADRCR = 1)
I/O port
1, 5, 6, 7 T T keep I/O port
PA73LT T A
20
1, 5, 6, 7 T T keep I/O port
PB7, PB5 to
PB0
1, 3, 5 to 7 T T keep I/O port
Legend:
H: High
L: Low
T: High-impedance stat e
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
ADRCR: Address control register
Notes: 1 Mask ROM version. Dedicated FWE input pin for the F-ZTAT version.
2 Low output only when WDT overflows causes a reset.
Appendix D Pin States
Rev.3.00 Mar. 26, 2007 Page 676 of 682
REJ09B0353-0300
D.2 Pin States at Reset
Reset in T1 State
Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an
external memory access cycle. As soon as RES goes low, all ports are in itialized to the input state.
AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is
initialized to the low output level 0.5 state after the low level of RES is sam pled. Sampling of RES
takes place at the fall of the system clock (φ).
Access to external address
φ
RES
H'000000
High impedance
High impedance
High
High
High
Internal
reset signal
T
1
T
2
T
3
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
Figure D.1 Reset during Memory Access (Reset during T1 State)
Appendix D Pin States
Rev.3.00 Mar. 26, 2007 Page 677 of 682
REJ09B0353-0300
Reset in T2 State
Figure D.2 is a timing diagram for the case in which RES goes low during the T2 state of an
external memory access cycle. As soon as RES goes low, all ports are in itialized to the input state.
AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is
initialized to the low output level 0.5 state after the low level of RES is samp led. The same timin g
applies when a reset occurs during a wait state (TW).
φ
RES
H'000000
High impedance
High impedance
Internal
reset signal
Access to external address
T1T2T3
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
Figure D.2 Reset during Memory Access (Reset during T2 State)
Appendix D Pin States
Rev.3.00 Mar. 26, 2007 Page 678 of 682
REJ09B0353-0300
Reset in T3 State
Figure D.3 is a timing diagram for the case in which RES goes lo w duri ng the T3 state of an
external memory access cycle. As soon as RES goes low, all ports are in itialized to the input state.
AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus
outputs are held during the T3 state.The same timing applies when a reset occurs in the T2 state of
an access cycle to a two-state-access area.
φ
RES
High impedance
High impedance
Internal
reset signal
Access to external address
T
1
T
2
T
3
H'000000
RD (read access)
(modes 1, 3, 5)
WR (write access)
(modes 1, 3, 5)
Data bus
(write access)
(modes 1, 3, 5)
I/O port
(modes 1, 3, 5 to 7)
Address bus
(modes 1, 3, 5)
AS (modes 1, 3, 5)
Figure D.3 Reset during Memory Access (Reset during T3 State)
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Rev.3.00 Mar. 26, 2007 Page 679 of 682
REJ09B0353-0300
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Sta ndby Mode
(1) To re tain RAM contents with the RAME bit set to 1 in SYSCR, d rive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must remain low
until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
t1≥ 10tcyc t2≥ 0 ns
STBY
RES
(2) To re tain RAM contents with th e RAME bit cleared to 0 in SYSCR, RES does not have to be
driven lo w as in (1).
Timing of Recovery fro m H ardware Standby Mode
Drive the RES signal low approximately 100 ns before STBY goes high.
STBY
RES
t≥100 ns tOSC
Appendix F Product Lineup
Rev.3.00 Mar. 26, 2007 Page 680 of 682
REJ09B0353-0300
Appendix F Product Lineup
Table F.1 H8/3039 Group Pro duct Lineup
Product Type Part Number Mark Code Package
(Package Code)
H8/3039 HD64F3039F HD64F3039F 80-pin QFP (FP-80A)
5 V
version HD64F3039TE HD64F3039TE 80-pin TQFP (TFP-80C)
HD64F3039VF HD64F3039VF 80-pin QFP (FP-80A)
Flash memory
version
3 V
version HD64F3039VTE HD64F3039VTE 80-pin TQFP (TFP-80C)
HD6433039F HD6433039(***)F 80-pin QFP (FP-80A)
5 V
version HD6433039TE HD6433039(***)TE 80-pin TQFP (TFP-80C)
HD6433039VF HD6433039(***)VF 80-pin QFP (FP-80A)
Mask ROM
version
3 V
version HD6433039VTE HD6433039(***)VTE 80-pin TQFP (TFP-80C)
H8/3038 HD6433038F HD6433038(***)F 80-pin QFP (FP-80A)
5 V
version HD6433038TE HD6433038(***)TE 80-pin TQFP (TFP-80C)
HD6433038VF HD6433038(***)VF 80-pin QFP (FP-80A)
Mask ROM
version
3 V
version HD6433038VTE HD6433038(***)VTE 80-pin TQFP (TFP-80C)
H8/3037 HD6433037F HD6433037(***)F 80-pin QFP (FP-80A)
5 V
version HD6433037TE HD6433037(***)TE 80-pin TQFP (TFP-80C)
HD6433037VF HD6433037(***)VF 80-pin QFP (FP-80A)
Mask ROM
version
3 V
version HD6433037VTE HD6433037(***)VTE 80-pin TQFP (TFP-80C)
H8/3036 HD6433036F HD6433036(***)F 80-pin QFP (FP-80A)
Mask ROM
version 5 V
version HD6433036TE HD6433036(***)TE 80-pin TQFP (TFP-80C)
HD6433036VF HD6433036(***)VF 80-pin QFP (FP-80A)
3 V
version HD6433036VTE HD6433036(***)VTE 80-pin TQFP (TFP-80C)
Note: (***) in mask ROM versions is the ROM code.
Appendix G Package Dimensions
Rev.3.00 Mar. 26, 2007 Page 681 of 682
REJ09B0353-0300
Appendix G Package Dimensions
The package dimension that is shown in the Renesas Semiconductor Package Data Book has
priority.
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
*1
*2
*3p
E
D
E
D
80
1
F
20
21
61
60 41
40
yxM
Z
Z
E
H
D
H
b
2
1
1
Detail F
c
AA
L
A
L
Terminal cross section
p
1
1
c
b
c
b
0.83
0.83
0.10
0.12
0.65
0° 8°
3.05
0.12 0.17 0.22
0.24 0.32 0.40
0.00
0.30
0.15
0.10 0.25
17.517.216.9
L
1
Z
E
Z
D
y
x
c
b
1
b
p
A
H
D
A
2
E
D
A
1
c
1
e
e
L
H
E
1.6
16.9 17.2 17.5
2.70
14
Reference
Symbol
Dimension in Millimeters
Min Nom Max
0.5 0.8 1.1
14
θ
θ
P-QFP80-14x14-0.65 1.2g
MASS[Typ.]
FP-80A/FP-80AVPRQP0080JB-A
RENESAS CodeJEITA Package Code Previous Code
Figure G.1 Package Dimensions (FP-80A)
Appendix G Package Dimensions
Rev.3.00 Mar. 26, 2007 Page 682 of 682
REJ09B0353-0300
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
12
0.60.50.4
MaxNom
Min
Dimension in Millimeters
Symbol
Reference
12
1.00
14.214.013.8
1.0
H
1
L
e
e
c
1
A
1
E
A
2
H
D
A
b
p
b
1
c
x
y
Z
D
Z
E
L
1
D
13.8 14.0 14.2
1.20
0.00 0.10 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
0°8°
0.5
0.10
0.10
1.25
1.25
Index mark
*1
*2
*3
y
F
80
1
Mx
20
21
61
60 41
40
D
E
D
E
p
b
H
E
H
D
Z
Z
Detail F
1
12
c
L
A
A A
L
1
1
p
Terminal cross section
b
c
c
b
θ
θ
P-TQFP80-12x12-0.50 0.4g
MASS[Typ.]
TFP-80C/TFP-80CVPTQP0080KC-A
RENESAS CodeJEITA Package Code Previous Code
Figure G.2 Package Dimensions (TFP-80C)
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/3039 Group, H8/3039F-ZTAT™
Publication Date: 1st Edition, December 1997
Rev.3.00, March 26, 2007
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
Colophon 6.0
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
H8/3039 Group, H8/3039F-ZTAT™
REJ09B0353-0300
Hardware Manual
