IS61LV256 ISST 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEATURES High-speed access times: -- 7, 8, 10, 12, 15, 20, 25 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby TTL compatible interface levels Single 3.3V power supply Fully static operation: no clock or refresh required Three-state outputs MARCH 1999 DESCRIPTION The JSSI 1S61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using /SSI's high-performance CMOS technology. This highly reliable pro- cess coupled with innovative circuit design techniques, yields access times as fast as 7 ns maximum. When CEis HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 wW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil SOU and the 450-mil TSOP package. FUNCTIONAL BLOCK DIAGRAM A0-A14 vcc > GND > 1/00-1/07 CE OE WE DECODER VO DATA CIRCUIT CONTROL CIRCUIT 256 X 1024 MEMORY ARRAY COLUMN I/O ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. Copyright 1999, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 ISSP PIN CONFIGURATION PIN CONFIGURATION 28-Pin SOJ 28-Pin TSOP OU Ai4 [1 28[] vec _ At2 [2 27] WE OE LJ 2 21f] A10 Ai1 [7] 23 20[-] CE A7 H 3 a A13 ao E424 19[] 07 AG L 4 2511 A8 As ] 25 18] 08 A5 [5 241] Ag A13 [1] 26 17[) 05 A4 6 23] Att WE [] 27 16{_] 1/04 A3 7 221] OE vec LJ 15{_] 1/03 A2 [8 21[] A1o A14 (1 14[-] GND ai 9 oof] CE A1i2 L]2 13[] 02 ao 10 19f] 07 A7 C43 1217] ot As CL} 4 11{-] oo voo (11 181] 06 as E15 10f ao vo1 (12 171] 05 A4 C16 of At yo2 ] 13 16[] 04 A3 (17 8] A2 GND [] 14 15[] 03 PIN DESCRIPTIONS TRUTH TABLE AO-A14 Address Inputs Mode WE CE OE _ 1/O Operation Vcc Current CE Chip Enable Input Not Selected Xx H Xx High-Z IsB1, IsB2 OE Output Enable Input (Power-down) aes Output Disabled HL 4H High-Z Ioct, loc WE Write Enable Input Read HLL Dout Icct, Ioce 1/00-1/O7 Input/Output Write L L xX Din Icct, Icce2 Vcc Power GND Ground ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vcc Power Supply Voltage Relative to GND -0.5t0+46 V VTERM Terminal Voltage with Respect to GND -0.5t0+46 V TBIAS Temperature Under Bias Com. 10 to +85 C Ind. 45 to +90 TsTG Storage Temperature -65to+150 C Pb Power Dissipation 1 Ww lout DC Output Current +20 mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 [SSP OPERATING RANGE Range Ambient Temperature Speed Vcc Commercial 0C to +70C 7,8 3.3V, +300 mV, 150 mV 10-25 3.3V + 300 mV Industrial 40C to +85C All 3.3V + 300 mV DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VoH Output HIGH Voltage Vcc = Min., loH = -2.0 mA 2.4 _ Vv VoL Output LOW Voltage Vcc = Min., lo. = 4.0 mA _ 0.4 Vv VIH Input HIGH Voltage 2.2 Vcc + 0.3 Vv VIL Input LOW Voltage -0.3 0.8 Vv Iu Input Leakage GND < Vin Vec Com. -1 1 LA Ind. -5 5 ILo Output Leakage GND < Vout < Vcc, Outputs Disabled Com. 1 1 LA Ind. -5 5 Notes: 1. Vit (min.) = 0.3V (DC); Vi_ (min.) = 2.0V (pulse width < 2.0 ns). Vin (max.) = Vec + 0.5V (DC); ViH (max.) = Vec + 2.0V (pulse width < 2.0 ns). 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. POWER SUPPLY CHARACTERISTICS (Over Operating Range) -7ns) -Bns@) = -10ns@ | -12ns -15ns = -20ns_s -25ns Sym. Parameter Test Conditions Min. Max. Min.Max. Min. Max. | Min.Max. Min.Max. Min.Max. Min.Max. Unit lec Vec Dynamic Operating + Vcc=Max.,CE=Vi Com.| 140 120 100 | 100 - 9 80 70 mA Supply Current lout = 0 mA, f= fuax Inc.| 160 140 120 |- 110 - 100 - 9 - 8 Isat = TTL Standby Current Vcc = Max., Com.| 3 8% --86 )})-8 -2%8) -28b & mA (TTL Inputs) Vin = Vin or Vit Ind. | 40 3 30 |- 30 --3 --3 9 CE2 Vin, f=0 Iss2 CMOS Standby Vc = Max., Com.| 2 2 2 2 2 2 2 mA Current (CMOS Inputs) CE< Vcc -0.2V, Ind} 5 = 5 =~ 56 |- 5 - 5 -~ 5 Vin > Voc - 0.2V, or Vin < 0.2V, f=0 Notes: 1. At f =fmax, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Shaded area = ADVANCE INFORMATION DATA. CAPACITANCE) Symbol Parameter Conditions Max. Unit CIN Input Capacitance Vin = OV 6 pF Court Output Capacitance Vout = OV 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25C, f = 1 MHz, Vee = 3.3V. Integrated Silicon Solution, Inc. 1-800-379-4774 3 SRO63-1G 04/16/99IS61LV256 ISSP READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range) -7ns@) 8 ns() -10 ns?) -12ns -15ns -20 ns -25 ns Symbol Parameter Min. Max. Min. Max. 9 Min. Max. | Min. Max. Min. Max. = Min. Max. = Min. Max Unit tre Read Cycle Time 7 o- & = 10 12 15 20 2 ns faa Address Access Time 7 8 10 12 15 20 25 ns toHa Output Hold Time 20 20 20 2 - 2 - 2 - 2 ns tace CE Access Time 7 8&8 0] 12 -- 15 2 2 ns tooe OE Access Time 95 - 4 6 7 8 8 ns tzoe OE to Low-Z Output 0 0 oO - 0 0 0 0 ns tyzoe OE to High-Z Output 35 4 5 6 6 7 os tzce CE to Low-Z Output 3 3 3 - 3 3 3 3 ns tuzce CE to High-Z Output 35 4 5 6 7 7 8 ns teu) CE to Power-Up 0 0 - 0 - 0 0 0 0 ns tro CE to Power-Down ~ 7 8 0} 12 - 15 20 2 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Shaded area = ADVANCE INFORMATION DATA. 3. Tested with the load in Figure 2. Transition is measured +200 mV from steady-state voltage. Not 100% tested. 4. Not 100% tested. AC TEST CONDITIONS Parameter Unit Input Pulse Level OV to 3.0V Input Rise and Fall Times 3ns Input and Output Timing 1.5V and Reference Levels Output Load See Figures 1 and 2 AC TEST LOADS 317 Q 3170 3.3V 3.3V OUTPUT OUTPUT 351 30 pF 351 Q 5 pF Including Including jig and jig and scope = scope = = Figure 1. Figure 2. 4 Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 AC WAVEFORMS READ CYCLE NO. 1.?) [SSP ADDRESS DOUT ait trc < x ag TOHA PREVIOUS DATA VALID eg TAA _ > - x <t TOHA>} DATA VALID READ CYCLE NO. 2) < trc > ADDRESS mM mK gt AA <i> TOHA OE N 4 . 7 -t poE >] << wt THZ0E CE \ tpl TLZ0E H NX ~t tACE> tizce t~ > eg THZCE > DOUT I ___< K DATA VALID _ Notes: 1. WE is HIGH for a Read Cycle. _ 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 ISSP WRITE CYCLE SWITCHING CHARACTERISTICS) (Over Operating Range) -7ns) = -8ns) ~ -10 ns) -12 ns -15ns -20 ns -25 ns Symbol Parameter Min. Max. Min. Max. 9 Min. Max. | Min. Max. Min. Max. Min. Max. = Min. Max Unit twe Write Cycle Time 7 = 8 = 10 12 15 20 2 ns tsce CE to Write End 6 = 65 8 = 8 10 12 15 ns taw Address Setup Time 6 65 8 8 10 12 15 ns to Write End tHA Address Hold 0 | 0 0 0 0 0 0 ns from Write End tsa Address Setup Time QO = 0 = 0 = Oo Oo Oo 0 ns tewet WEPulse Width(OELOW) | 7) 8 10 } 12 14 20 2 ns tewe2 WEPulseWidth(OEHIGH) | 6 65 7 - 8 10 12 15 ns tsp Data Setup to Write End 45 5 = 5 = 6 7 = 10 11 ns tHD Data Hold from Write End G0 0 | 0 Oo oO oO 0 ns tuzwe WELOWtoHigh-Z Output | 35 35 4 6 7 7 7 os tzwe" WEHIGH to Low-Z Output 0 0 - 0 - oO oO oO 0 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. __ __ 2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 3. Shaded area = ADVANCE INFORMATION DATA. 4. Tested with the load in Figure 2. Transition is measured +500 mV from steady-state voltage. Not 100% tested. AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) ) ~t twe > ADDRESS x VALID ADDRESS mK tSA -~<$>|-~ tsce te THA CE SS ZO ~t taw > _ wv 1 PWE1 > WE XR / | ee THZWE>] < TLZ2we> HIGH-Z / DOUT DATA UNDEFINED No < tsp } typ DIN DATAIN VALID 6 Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 [SSP WRITE CYCLE NO. 2(OEis HIGH During Write Cycle) 1.2) two __________ | ADDRESS x VALID ADDRESS mx A >- THA oc YY i __TtSceE CE SS A. < taw > tpwet > _ NX IN YS WE NOX, /) tsat > Let THZWEr g TLZWE> DouT DATA UNDEFINED an < t sp >< Tt HD > DIN DATAIN VALID WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) < twe > ADDRESS XK VALID ADDRESS mx __ A$ THA OE Low tsa+~ | tsce CE Ss. A taw _ __- .\-_ PWE2 >] WE IN S| Leg T HZWE > - TLZWE >} DOouT DATA UNDEFINED ee < @ t sp |<e_ THD > DIN DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. |/O will assume the High-Z state if OE > Vin. Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99IS61LV256 ISSP ORDERING INFORMATION Commercial Range: 0C to +70C ORDERING INFORMATION Industrial Range: 40C to +85C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 7 IS61LV256-7T TSOP - 450 mil 7 IS61LV256-7T| TSOP - 450 mil IS61LV256-7J 300-mil Plastic SOJ IS61LV256-7Jl 300-mil Plastic SOJ 8 IS61LV256-8T TSOP - 450 mil 8 1S61LV256-8T TSOP - 450 mil IS61LV256-8J 300-mil Plastic SOJ IS61LV256-8J| 300-mil Plastic SOJ 10 IS61LV256-10T TSOP - 450 mil 10 IS61LV256-10Tl = TSOP - 450 mil IS61LV256-10J 300-mil Plastic SOJ IS61LV256-10JI 300-mil Plastic SOJ 12 IS61LV256-12T TSOP - 450 mil 12 IS61LV256-12Tl = TSOP - 450 mil IS61LV256-12J 300-mil Plastic SOJ IS61LV256-12JI 300-mil Plastic SOJ 15 IS61LV256-15T 450-mil TSOP 15 IS61LV256-15TI 450-mil TSOP IS61LV256-15J 300-mil Plastic SOJ IS61LV256-15Jl 300-mil Plastic SOJ 20 IS61LV256-20T 450-mil TSOP 20 IS61LV256-20T| 450-mil TSOP IS61LV256-20J 300-mil Plastic SOJ IS61LV256-20JI 300-mil Plastic SOJ 25 IS61LV256-25T 450-mil TSOP 25 IS61LV256-25T| 450-mil TSOP IS61LV256-25J 300-mil Plastic SOJ IS61LV256-25J| 300-mil Plastic SOJ Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com 8 Integrated Silicon Solution, Inc. 1-800-379-4774 SR063-1G 04/16/99