HV7131R Confidential CMOS Image Sensor HV7131R MagnaChip Semiconductor Ltd Version 1.7 This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -12004 MagnaChip Semiconductor Ltd. HV7131R Confidential Revision History Revision 1.0 1.2 1.3 1.4 2002-December-24 2002-December-30 2003-March-12 Comments Initial Creation Replaced ADC to 10-bit resolution Changed Package Specification Changed Pin Configuration Review datasheet & release Add I/R Reflow Condition added 40 pin PKG. Drawing Revision 1.5 2003.May-29 Register Revision 1.6 2004 March-26 Electro-Optical Characteristic Revision 1.7 2004 June-18 Add Spectral Characteristics 1.1 Issue Date 2001-November-6 2002-April-12 (c) Copyright 2004, MagnaChip Semiconductor Ltd. All right reserved. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -22004 MagnaChip Semiconductor Ltd. HV7131R Confidential CONTENTS General Description .................................................................................................................... 4 Features........................................................................................................................................ 4 Block Diagram ............................................................................................................................. 5 Pin Diagram.................................................................................................................................. 6 Pixel Array Structure ............................................................................................................... 7 Pin Description ............................................................................................................................ 8 Functional Description ............................................................................................................... 9 Register Description ................................................................................................................. 11 Frame Timing ............................................................................................................................. 21 I2C Chip Interface...................................................................................................................... 24 AC/DC Characteristics .............................................................................................................. 26 MCLK Duty Cycle......................................................................................................... 27 ENB Timing .................................................................................................................. 27 RESETB Timing ........................................................................................................... 27 Electro-Optical Characteristics................................................................................................ 30 Electro-Optical Test Condition ............................................................................................. 30 Soldering.............................................................................................................................. 30 Package Specification .............................................................................................................. 32 MEMO.................................................................................................................................. 33 This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -32004 MagnaChip Semiconductor Ltd. Confidential HV7131R General Description HV7131R is a highly integrated single chip CMOS color image sensor implemented by proprietary MagnaChip 0.30um CMOS sensor process realizing high sensitivity and wide dynamic range. Total pixel array size is 656x502, and 640x480 pixels are active. Each active pixel composed of 4 transistors, it has a micro-lens to enhance sensitivity. and it converts photon energy to analog pixel voltage. On-chip 10-bit Analog to Digital Converter (ADC) are configured to digitize analog pixel voltage, and on-chip Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. Auto Black Level Compensation (ABLC) is using light blocking shield pixels which is placed top and bottom at core pixel to measure the black level and compensation. Features z VGA resolution z 5.04m x 5.04m active square pixel z 1/4.5 inch optical format z Total Pixel Array : 656x502 / Active Pixel Array : 640x480 z Bayer RGB color filter array z Micro-lens for high sensitivity z Low Power Operation : Voltage Range : 2.6V - 3.0V z Max Frame rate : 30 frame/s at 25Mhz Master Clock (VGA) z Package Types : CLCC 40LD, COB(Chip-on-Board), COF(Chip-on-Flex) z 10-bit Digital Image Signal Data Bus z Low Fixed Pattern Noise by Correlated Double Sampling z Controllable full function through standard IIC bus z External Power Down z Programmable Power Down mode z Auto Black level compensation z Flexible exposure time control z Strobe Control Signal generation for frame capture mode z Programmable Video Windowing z Integrated 10bit Analog to Digital Conversion z Programmable Frame Rate up to 30frame/sec This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -42004 MagnaChip Semiconductor Ltd. Confidential HV7131R Block Diagram 1. PGA : Programmable Gain Amplifier. 2. ADC : Analog to Digital Converter. 3. CDS : Correlated Double Sampling. 4. SNR : Sensor Control Digital Logic. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -52004 MagnaChip Semiconductor Ltd. HV7131R Confidential Pin Diagram STROB DGNDI 1 VSYNC SCK 2 HSYNC DGNDI 3 DGNDI ENB 4 SDA DGNDI 5 40 39 38 37 36 NC 6 35 NC NC 7 34 RESETB MCLK 8 33 DVDDI VCLK 9 32 DVDDC 31 DGNDC 30 DGNDI 29 DATA[0] AVDD 13 28 DATA[1] NC 14 27 NC NC 15 26 NC HV7131R AGND 10 CLCC 40 PIN AGND 11 Top View AVDD 12 16 17 18 19 20 21 22 23 24 25 DATA[2] DATA[3] DGNDI DATA[4] DATA[5] DATA[6] DATA[7] DGNDI DATA[8] DATA[9] This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -62004 MagnaChip Semiconductor Ltd. HV7131R Confidential Pixel Array Structure Metal Shielded Black Level Array[2 line] G R G R ...... G R G R B G B G ...... B G B G G R G R ...... G R G R B G B G ...... B G B G Metal Shielded Black Level Array[2 line] This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -72004 MagnaChip Semiconductor Ltd. Confidential HV7131R Pin Description Pin 1 2 3 Type G I G Symbol DGNDI SCK DGNDI 4 I ENB 5 6~7 8 9 10~11 12~13 14~15 16 17 18 19 20 21 22 23 24 25 26~27 28 29 30 31 32 33 34 35 36 37 G N I O G P N O O G O O O O G O O N O O G G P P I N O O DGNDI NC MCLK VCLK AGND AVDD NC DATA[9] DATA[8] DGNDI DATA[7] DATA[6] DATA[5] DATA[4] DGNDI DATA[3] DATA[2] NC DATA[1] DATA[0] DGNDI DGNDC DVDDC DVDDI RESETB NC STROBE VSYNC 38 O HSYNC 39 40 G B DGNDI SDA Description Ground for I/O Buffer. I2C Clock Input. Ground for I/O Buffer. ENB signal enables Sensor : High(Sensor Enabled), Low(Sensor Disabled, External Power Down) Ground for I/O Buffer. No Connection. Master Input Clock. Video Output Clock. Ground for Analog Block. Power for Analog Block. No Connection. Image Output Data Bit 9. Image Output Data Bit 8. Ground for I/O Buffer. Image Output Data Bit 7. Image Output Data Bit 6. Image Output Data Bit 5. Image Output Data Bit 4. Ground for I/O Buffer. Image Output Data Bit 3. Image Output Data Bit 2. No Connection. Image Output Data Bit 1. Image Output Data Bit 0. Ground for I/O Buffer. Ground for Internal Digital Block. Power for Internal Digital Block. Power for I/O Buffer. Sensor Reset, Low Active. No Connection. Strobe Signal Output. Video Frame Synchronization signal. / Frame Start output VSYNC is active at start of image data frame. Video Horizontal Line Synchronization signal. / Data is valid, when HSYNC is High. Ground for I/O Buffer. I2C Standard data I/O port. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -82004 MagnaChip Semiconductor Ltd. HV7131R Confidential Functional Description Pixel Architecture Pixel architecture is a 4-transistor NMOS pixel design. The additional use of a dedicated transfer transistor in the architecture reduces most of reset level noise so that fixed pattern noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill factor so that high pixel sensitivity is achieved. Sensor Imaging Operation Imaging operation is implemented by the offset mechanism of integration domain and scan domain(rolling shutter scheme). First integration plane is initiated, and after the programmed integration time is elapsed, scan plane is initiated, then image data start being produced. Time Integration Integration Plane Time Frame 0 Scan Integration Plane Frame 0 Plane Frame 0 Time Frame 1 Scan Plane Frame 1 Frame 1 Time This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. -92004 MagnaChip Semiconductor Ltd. HV7131R Confidential Spectral Characteristics HV7131G Spectral Response 1.2 1 0.8 B G 0.6 R 0.4 0.2 0 400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700 (nm) This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 10 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Register Description Register Device ID Symbol DEVID Sensor Control A SCTRA Sensor Control B SCTRB Output Inversion OUTIV Row Start Add Upper Row Start Add Lower Col. Start Add Upper Col. Start Add Lower Window Height Upper Window Height Lower Window Width Upper Window Width Lower HBLANK Time Upper HBLANK Time Lower VBLANK Time Upper VBLANK Time Lower Integration Time High Integration Time Middle Integration Time Low RSAU RSAL CSAU CSAL WIHU WIHL WIWU WIWL HBLU HBLL VBLU VBLL INTH Address Default Description 00h 02h Product Identification, Revision Number. ClkDiv[6:4], ABLCEn[3], PxlVs[2], 01h 09h XFlip[1], YFlip[0] VCLK Disable[6], ADCPwDn[5], Black 02h 01h Mode[4], Sleep[3], VsHsEn[2], BLDataEn[1], StrobeEn[0] ByrDpcEn[6], ByrDpcTh[5:4], 03h 00h ClkHSC[3], InvVSC[2], InvHSC[1], InvVCLK[0] 10h 00h Row Start Address Upper Byte[8] 11h 02h Row Start Address Lower Byte[7:0] 12h 00h Column Start Address Upper Byte[9:8] 13h 02h Column Start Address Lower Byte[7:0] 14h 01h Window Height Upper Byte[8] 15h e2h Window Height Lower Byte[7:0] 16h 02h Window Width Upper Byte[9:8] 17h 82h Window Width Lower Byte[7:0] 20h 00h HBLANK Time Upper Byte[15:8]. 21h d0h HBLANK Time Lower Byte[7:0]. 22h 00h VBLANK Time Upper Byte[15:8]. 23h 08h VBLANK Time Lower Byte[7:0]. 25h 06h Integration Time [23:16] INTM 26h 5Bh Integration Time [15:8] INTL 27h 9ah Pre-amp Gain PAG 30h 10h Red Color Gain RCG 31h 10h Green Color Gain GCG 32h 10h Blue Color Gain BCG 33h 10h Integration Time [7:0] Gain for Pre-amp (0.5~16.5 times with 8bit resolution) [7:0] Gain for Red Pixel Read-out (0.5~2 times with 6bit resolution) [5:0] Gain for Green Pixel Read-out (0.5~2 times with 6bit resolution [5:0] Gain for Blue Pixel Read-out (0.5~2 times with 6bit resolution [5:0] Analog Bias Control A ACTRA 34h 17h CDS Bias [6:4], PGA Bias [3:0] Analog Bias Control B ACTRB 35h 7fh Black Level Threshold BLCTH 40h ffh Initial ADC Offset Red Initial ADC Offset Green Initial ADC Offset Blue ORedI 41h 7fh Reset Clamp [7:4], ADC Bias [3:0] Auto Black Level Pixel Threshold Value Initial ADC Offset Red OGrnI 42h 7fh Initial ADC Offset Green OBluI 43h 7fh Initial ADC Offset Blue This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 11 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Device ID [DEVID : 00h : 02h] 7 6 5 4 3 2 Product ID 0 0 1 0 Revision Number 0 0 0 0 1 0 High nibble represents Sensor Array Resolution, Low nibble represents Revision Number. Sensor Control A [SCTRA : 01h : 09h] 7 6 Reserved - 5 4 ClkDiv 0 0 3 2 1 0 ABLC En PxlVs X Flip Y Flip 1 0 0 1 0 Clock Division Device Input Master Clock(IMC) for internal use. Internal Divided Clock Frequency(DCF) is defined as Master Clock Frequency(MCF) divided by specified clock divisor. DCF is as follows 000 : DCF = MCLK, 001 : DCF = MCLK/2, 010 : DCF = MCLK/4 011 : DCF = MCLK/8, 100 : DCF = MCLK/16, 101 : DCF = MCLK/32 110 : DCF = MCLK/64, 111 : DCF = MCLK/128, ABLC En 0 : Auto Black Level Compensation Disable 1 : Auto Black Level Compensation Enable PxlVs VBLANK unit : VBLANK Time value 0 : LCF unit 1 : SCF unit X-Flip 0 : Normal. 1 : Image is horizontally flipped. Y-Flip 0 : Normal. 1 : Image is vertically flipped. Sensor Control B [SCTRB : 02h : 01h] This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 12 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential 7 6 5 4 3 2 1 0 Reserved VCLK ADC Black Sleep VsHsEn BLDataEn StrobeEn PwDn Mode Mode 0 0 0 0 0 1 - 0 VCLK When this bit is high Video Output Clock(VCLK) Disable ADCPwDn When this bit is high ADC Block goes to Power Down Black Mode Black and White Mode : Red and Blue gain use the Green gain when this bit is set to high. 0 : Color Mode 1 : Black and White Mode Sleep Mode Software Power Down 0 : Software power down mode off. 1 : Software power down mode on. All internal digital block goes to sleep mode with this bit set to high VsHsEn HSYNC in VBLANK : VBLANK is equivalent to VSYNC, and HSYNC is the inversion of HBLANK, and this signal control whether HSYNC is active or not when VBLANK unit is LCF. 0 : There are no valid HSYNC signals during valid VSYNC signal. 1 : There are valid HSYNC signals during valid VSYNC signal. Number of valid HSYNC is same as number of VBLANK register when VSYNC unit is line unit. Do not use this mode when VSYNC unit is pixel unit VSYNC (VBLANK) HSYNC BLDataEn Black Level Data Enable : HSYNC is generated for light-shielded pixels in 4 lines. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 13 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential StrobeEn Strobe Enable : When StrobEn is high STROBE pin will indicates when strobe light should be splashed in dark environment to get adequate lighted image Output Inversion [OUTIV : 03h : X0h] 7 6 5 4 Reserved - - - - 3 2 1 0 Clocked VSYNC HSYNC VCLK HSYNC Inversion Inversion Inversion 0 0 0 0 Clocked HSYNC In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNV time VSYNC Inversion VSYNC output polarity is inverted HSYNC Inversion HSYNC output polarity is inverted VCLK Inversion HSYNC output polarity is inverted Row Start Address Upper [RSAU : 10h : X0h] 7 6 5 4 3 2 1 0 This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 14 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Reserved - - - - RSA[8] - - - 0 3 2 1 0 0 0 1 0 Row Start Address Low [RSAL : 11h : 02h] 7 6 5 4 RSA[7:0] 0 0 0 0 Row Start Address register defines the row start address of image read out operation. Column Start Address Upper [CSAU : 12h : X0h] 7 6 5 4 3 2 1 Reserved - - - 0 CSA[9:8] - - - 0 0 3 2 1 0 0 0 1 0 Column Start Address Low [CSAL : 13h : 02h] 7 6 5 4 CSA[7:0] 0 0 0 0 Column Start Address register defines the column start address of image read out operation. Window Height Upper [WIHU : 14h : X1h] 7 6 5 4 3 2 1 Reserved - - - 0 WIH[8] - - - - 1 4 3 2 1 0 0 0 1 0 Window Height Low [WIHL : 15h : e2h] 7 6 5 WIH[7:0] 1 1 1 0 This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 15 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Window Height register defines the height of image read out operation. Window Width Upper [WIWU : 16h : X2h] 7 6 5 4 3 2 1 Reserved - - - 0 WIW[9:8] - - - 1 0 4 3 2 1 0 0 0 1 0 2 1 0 0 0 0 0 3 2 1 0 0 0 0 Window Width Low [WIWL : 17h : 82h] 7 6 5 WIW[7:0] 1 0 0 0 Window Width register defines the width of image read out operation. Horizontal Blanking Time Upper [HBLU : 20h : 00h] 7 6 5 4 3 HBLANK Time [15:8] 0 0 0 0 Horizontal Blanking Time Low [HBLL : 21h : d0h] 7 6 5 4 HBLANK Time [7:0] 1 1 0 1 0 HBLANK Time register defines data blank time between current line and next line by using Sensor Clock Period unit (1/SCF), and should larger then 208(d0h) Vertical Blanking Time High [VBLU : 22h : 00h] 7 6 5 4 3 2 1 0 0 0 0 VBLANK Time[15:8] 0 0 0 0 0 This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 16 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Vertical Blanking Time Low [VBLL : 23h : 08h] 7 6 5 4 3 2 1 0 0 0 0 VBLANK Time[7:0] 0 0 0 0 1 VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC indicates frame boundary between continuous frames For VSYNC-HSYNC timing relation in the frame transition, please refer to Frame Timing section Integration Time High [INTH: 25h : 06h] 7 6 5 4 3 2 1 0 0 1 1 0 3 2 1 0 Integration Time [23:16] 0 0 0 0 Integration Time Middle [INTM: 26h: 5bh] 7 6 5 4 Integration Time [15:8] 0 1 0 1 1 0 1 1 4 3 2 1 0 0 1 0 Integration Time Low [INTL: 27h: 9ah] 7 6 5 Integration Time [7:0] 1 0 0 1 1 Integration time value register defines the time during which active pixel element evaluates photon energy that is converted to digital data output by internal ADC processing. Integration time is equivalent to exposure time of general camera. So that integration time need to be increased in dark environment and decreased in bright environment. Maximum value of integration time is (224-1) x sensor clock period (80ns, SCF 12.5MHz @ DCF 25MHz) = 1.34sec This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 17 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Preamp Gain [PAG : 30h : 10h] 7 6 5 4 3 2 1 0 0 0 0 Preamp Gain 0 0 0 1 0 Preamp Gain is common gain for R, G, B channel and used for auto exposure control. Programmable range is from 0.5X ~ 16.5X. Default gain is 1.5X. Gain = 0.5 + B<7:0>/16 Red Color Gain [RCG : 31h : 10h] 7 6 5 4 Reserved - 3 2 1 0 Red Color Gain - 0 1 0 0 0 0 4 3 2 1 0 Green Color Gain [GCG : 32h : 10h] 7 6 5 Reserved - Green Color Gain - 0 1 0 0 0 0 4 3 2 1 0 0 0 Blue Color Gain [BCG : 33h : 10h] 7 6 5 Reserved - Blue Color Gain - 0 1 0 0 There are three color gain registers for R, G, B pixels, respectively. R, G, B color gain are used to amplify R, G, B channel. Programmable range is from 0.5X ~ 2.5X. Default gain is 1X. Gain = 0.5 + B<5:0>/32 Analog Bias Control A [ACTRA : 34h : 17h] 7 6 Reserved - 5 4 3 2 CDS Bias 0 0 1 0 1 1 PGA Bias 1 0 1 PGA Bias This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 18 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Controls the amount of current in internal amplifier bias circuit to amplify pixel output effectively. The larger register value increases the amount of current CDS Bias Controls the amount of current in internal CDS bias circuit to amplify pixel output effectively. The larger register value increases the amount of current Analog Bias Control B [ACTRB : 35h : 7fh] 7 6 5 4 3 2 Reset Clamp 0 1 1 1 0 1 1 ADC Bias 1 1 1 Reset Level Clamp Because extremely bright image like sun affects reset data voltage of pixel to lower, bright image is captured as black image in image sensor regardless of correlated double sampling. To solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The larger register value clamps the reset data level at highest voltage level. Default value is 7 to clamp the reset data level at appropriate voltage level. ADC Bias ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. The larger register value increase the amount of current Black Level Threshold [BLCTH : 40h : ffh] 7 6 5 4 3 2 1 0 1 1 1 Black Level Threshold 1 1 1 1 1 The register specifies the maximum value, which determines whether light shielded pixel output, is valid. When light shielded pixel output exceeds this limit, the pixel is not accounted for black level calculation. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 19 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Initial ADC Offset Red [ORedI : 41h : 7fh] 7 6 5 4 3 2 1 0 1 1 1 1 3 2 1 0 1 1 1 1 3 2 1 0 1 1 1 Initial ADC Offset Red 0 1 1 1 Initial ADC Offset Green [OGrnI : 42h : 7fh] 7 6 5 4 Initial ADC Offset Green 0 1 1 1 Initial ADC Offset Blue [OBluI : 43h : 7fh] 7 6 5 4 Initial ADC Offset Blue 0 1 1 1 1 * Update ADC Offset = - (Average - Initial ADC Offset) These values are using black level compensation in active pixel. Average value is measured and calculated at light shielded pixel with ABLCEn is active. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 20 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Frame Timing For clear description of frame timing, clocks' acronym and relation are reminded in here again. < Clock Acronym Definition > MCF(Master Clock Frequency) : MCLK SCF(Sensor Clock Frequency) : DCF/2 VCF( Video Clock Frequency) : SCF DCF(Divided Clock Frequency) : MCF/Clock Division LCF(Line Clock Frequency) : 1/(HBLANJ Period + HSYNC Period (HBLANK Time + Video Width Time) SCP(Sensor Clock Period) = 1/SCF, LCP(Line Clock Period) = 1/LCF < Frame Time Calculation > ABLC Time = 4LCP * (HBLANK + 512 SCP) Core Frame Time = IDLE Slot + Video Height * LCP Real Frame Time = Integration Time + VBLANK * LCP for Integration Time > Core Frame Time = Core Frame Time + VBLANK * LCP for Integration Time <= Core Frame Time HOLD Slot Time = Integration Time - Core Frame Time for Integration Time > Core Frame Time = 0 for Integration Time <= Core Frame Time where IDLE Slot is 1LCP. This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 21 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential 1. VGA size when Programmable Window is disabled and ABLC enable VGA Frame Timing Related Parameters Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) HBLANK Value VSYNC Mode ABLC 25Mhz DCF/2 =12.5Mhz 208 Line Mode Enable Clock Division Sensor Clock Period(SCP) VBLANK Value Line Clock Period(LCP) Programmable Window MCF/1 = 25Mhz 1/12.5Mhz = 80ns 8 848 SCPs OFF If Integration Time < Core Frame Time, Real Frame Time is 2(208 + 640)SCPs + 4(208 + 512)SCPs + 480(208 + 640)SCPs + 8(208 + 640)SCPs = 418400 SCPs =418400 X 80ns = 33.47msec = 29.87fps else Real Frame Time is Integration Time * SCPs + 8 * (208 +640) SCPs. HOLD SLOT in frame timing appears only if integration time is larger then core frame time LCP(848SCPs) Video Width(640SCP) IDLE SLOT(2LCP) Core Frame Time 0~3 Line Data Flow for ABLC ABLC Time 4th Line Data Flow 5th Line Data Flow HBLANK 480 LCPs Video Height (208 SCPs) HSYNC(640 SCPs) Active Data : 640 EA 482th Line Data Flow 483th Line Data Flow HOLD SLOT Integration time - Core Frame Time Real Frame Time VBLANK[VSYNC] (8LCP) HBLANK (208 SCPs) HSYNC(640 SCPs) LCP = 848 SCPs VCLK=12.5[Mhz] DATA[9:0] Hi - Z Valid Data 2. VGA size when Programmable Window is disabled and ABLC disable This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 22 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential VGA Frame Timing Related Parameters Master Clock Frequency(MCF) Sensor Clock Frequency(SCF) HBLANK Value VSYNC Mode ABLC 25Mhz DCF/2 =12.5Mhz 208 Line Mode Disable Clock Division Sensor Clock Period(SCP) VBLANK Value Line Clock Period(LCP) Programmable Window MCF/1 = 25Mhz 1/12.5Mhz = 80ns 8 848 SCPs OFF If Integration Time < Core Frame Time, Real Frame Time is 2(208 + 640)SCPs + 480(208 + 640)SCPs + 8(208 + 640)SCPs = 415520 SCPs =415520 X 80ns = 33.24msec = 30fps else Real Frame Time is Integration Time * SCPs + 8 * (208 +640) SCPs. HOLD SLOT in frame timing appears only if integration time is larger then core frame time LCP(848SCPs) Video Width(640SCP) Core Frame Time IDLE SLOT(2LCP) 4th Line Data Flow 5th Line Data Flow HBLANK 480 LCPs Video Height (208 SCPs) HSYNC(640 SCPs) Active Data : 640 EA 482th Line Data Flow 483th Line Data Flow HOLD SLOT Integration time - Core Frame Time Real Frame Time VBLANK[VSYNC] (8LCP) HBLANK (208 SCPs) HSYNC(640 SCPs) LCP = 848 SCPs VCLK=12.5[Mhz] DATA[9:0] Hi - Z Valid Data I2C Chip Interface This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 23 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential The serial bus interface consists of the SDA(serial data) and SCK(serial clock) pins. HV7131GR sensor can operate only as a slave. The SCK only controls the serial interface. However, MCLK should be supplied and RESET should be high signal during controlling the serial interface. The Start condition is that logic transition (High to Low) on the SDA pin while the SCK pin is at high. The Stop condition is that logic transition (Low to High) on the SDA pin while the SCK pin is at high. To generate Acknowledge signal, the Sensor drives the SDA low when the SCK is high. Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an Acknowledge. The most significant bit of the byte should always be transmitted first. MSB SDA SCK 1 LSB 2 8 START 9 ACK 1 2 8 9 ACK STOP Register Write Sequences One Byte Write S 22H A 01H A 03H A P *1 *2 *3 *4 *5 *6 *7 *8 Set "Sensor Control A" register into Window mode *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 03H [Video Mode : CIF] *7. Read: acknowledge from sensor *8. Drive: I2C stop condition This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 24 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Multiple Byte Write using Auto Address Increment S 22H A 10H A 00H A 64H A P *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 Set "HSYNC Blanking High/Low" register as 0064H with auto address increment *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit] *3. Read: acknowledge from sensor *4. Drive: 10H [sub-address] *5. Read: acknowledge from sensor *6. Drive: 00H [HSYNC Blanking High] *7. Read: acknowledge from sensor *8. Drive: 64H [HSYNC Blanking Low] *9. Read: acknowledge from sensor *10. Drive: I2C stop condition Register Read Sequence S 22H A 01H *1 *2 *3 *4 A S *5 *6 23H A 13H *7 *8 *9 A P *1 *11 0 Read "Sensor Control A" register from HV7131GR *1. Drive: I2C start condition *2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)] *3. Read: acknowledge from sensor *4. Drive: 01H [sub-address] *5. Read: acknowledge from sensor *6. Drive: I2C start condition *7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)] *8. Read: acknowledge from sensor *9. Read: Read "13H(Value of Sensor Control A) " from sensor *10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to high to prepare for the read transaction end. *11. Drive: I2C stop condition AC/DC Characteristics This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 25 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Absolute Maximum Ratings Symbol Parameter Units Min. Max. Vdpp Digital supply voltage Volts -0.3 7.0 Vapp Analog supply voltage Volts -0.3 7.0 Vipp Input signal voltage Volts -0.3 7.0 Top Operating Temperature C -10 50 Tst Storage Temperature C -30 80 Caution: Stresses exceeding the absolute maximum ratings may induce failure. DC Operating Conditions Symbol Parameter Units Min. Max. Vdd Internal operation supply voltage Volt 2.6 3.0 Vih Input voltage logic "1" Volt 2.0 3.0 6.5 Vil Input voltage logic "0" Volt 0 0.8 6.5 Voh Output voltage logic "1" Volt 2.15 Vol Output voltage logic "0" Volt 0.4 60 Ioh Output High Current mA -4 60 Iol Output Low Current mA 4 60 Ta Ambient operating temperature Celsius -10 Load[pF] 60 Notes at Ioh = -1mA 50 AC Operating Conditions Symbol Parameter Max Operation Frequency Units Notes MCLK Main clock frequency 25 MHz 1 400 KHz 2 30.953 @ 30fps, 25MHz mA 0.095 @ 25MHz uA 208.815 @ 25MHz uA SCK INORMAL IDOWN_HARD IDOWN_SOFT 2 I C clock frequency Power Consumption in Normal mode Power Consumption in Hard Power Down mode Power Consumption in Soft Power Down mode 1. MCLK may be divided by internal clock division logic for easy integration with high speed video codec. 2. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface section Input AC Characteristics This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 26 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential MCLK Duty Cycle TMCLK TB VDD / 2 MCLK TA TA = 40% ~ 60% of TMCLK, TB = 40% ~ 60% of TMCLK , TA + TB = TMCLK ENB Timing ENB pin enables sensor. If you set ENB pin to low, sensor goes to power down. Though sensor remains power down, you can program the registers by above IIC protocol. After ENB is changed to high, the registers that you set in power down are newly updated. If you want software power down with ENB pin high, set sleep mode in SCTRB(02H)register. ENB VSYNC HSYNC DATA[9:0] VCLK RESETB Timing RESETB pin initializes the registers to default value. When RESETB pin is low, initialization is done. HV7131GR is automatically reset the chip when power on. We recommend to initialize the registers by using RESETB pin. TR: RESETB valid minimum time: 10 MCLK periods. MCLK RESETB TR Sensor Ready to Operate Output AC Characteristics All output timing delays are measured with output load 60[pF]. Output delay includes the internal This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 27 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential clock path delay and output driving delay that changes in respect to the output load, the operating environment, and a board design. Due to the variable valid time delay of the output, RGB output signals DATA[9:0], HSYNC, and VSYNC may be latched in the negative edge of VCLK for the stable data transfer between the image sensor and video codec. V C LK (N on Inverted) HSYNC D ATA [9:0] X D ata 0 D ata 1 D ata 2 D ata 3 M inim um delay : 0.5X M aster C lock P eriod I2C Bus Timing stop start start stop SDA tr tbuf thd;sta tf tlow SCK thd;sta thd;dat thigh tsu;dat tsu;sta tsu;sto This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 28 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Parameter Symbol Min. Max. Unit SCK clock frequency fsck 0 400 KHz Time that I2C bus must be free before a new transmission can start tbuf 1.2 - us Hold time for a START thd;sta 1.0 - us LOW period of SCK tlow 1.2 - us HIGH period of SCK thigh 1.0 - us Setup time for START tsu;sta 1.2 - us Data hold time thd;dat 1.3 - us Data setup time tsu;dat 250 - ns Rise time of both SDA and SCK tr - 250 ns tf - 300 ns Setup time for STOP tsu;sto 1.2 - us Capacitive load of SCK/SDA Cb - - pf Fall time of both SDA and SCK This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 29 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Electro-Optical Characteristics Parameter Units Min. Typical Max. Sensitivity mV / luxxsec 2053.9 1356 1362.3 2480.482 1657.460 1656.700 10.728 1023.000 1023.000 1023.000 6.627 24.326 0.005 0.090 208.806 0.009 3121.600 2093.500 2074.100 31.990 1023.000 1023.000 1023.000 11.861 30.009 27.130 29.610 259.660 17.580 Dark Signal Output Saturation Signal Power Consumption Power Consumption Power Consumption code mV mA uA uA 0.000 1022.980 1022.990 1023.000 4.428 19.572 0.000 0.000 182.160 0.00 Note Green Red Blue Green Red Blue Dynamic DVDD Dynamic AVDD Static DVDD Static AVDD Sleep DVDD Sleep AVDD - Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used. Soldering Infrared(IR) / Convection solder reflow condition Parameter Average ramp-up rate(183C to Peak) Convection or IR/Convection 3 C / second max. Preheat temperature 125(25) C 120 second max. Temperature maintained above 183C 60 - 150 second Time within 235C of actual peak temperature 10 - 20 second Peak temperature range Ramp-down rat Time 25C to peak temperature (220 +5/-0) C or (235 +5/-0) C 6C / second max. 6 minute This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 30 2004 MagnaChip Semiconductor Ltd. HV7131R Confidential Temp.( C) 10 ~ 20 sec. 235 180 125 60 ~ 150 sec. max 120 sec. max 30 60 90 120 150 180 210 240 270 300 330 360 Time(seconds) This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 31 2004 MagnaChip Semiconductor Ltd. Confidential HV7131R Package Specification - 40 PIN CLCC - - This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 32 2004 MagnaChip Semiconductor Ltd. Confidential HV7131R MEMO MagnaChip Semiconductor Ltd. * Contact Point * CIS Marketing Team 15Floor, MagnaChip Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea Tel: 82-2-3459-3374 Fax: 82-2-3459-5580 E-mail : hanho.lee@MagnaChip.com This document is a general product description and is subject to change without notice. MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent licenses are implied. - 33 2004 MagnaChip Semiconductor Ltd.