HV7131R - MagnaChip Semiconductor

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CMOS Image Sensor

HV7131R

MagnaChip Semiconductor Lt d

Version 1.7

Confidential HV7131R

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Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent

licenses are implied.

- 2 - 2004 MagnaChip Semiconductor Ltd.

Revision History

Revision Issue Date Comments

1.0 2001-November-6 Initial Creation

1.1 2002-April-12 Replaced ADC to 10-bit resolution

Changed Package Specification

Changed Pin Configuration

1.2 2002-December-24 Review datasheet & release

1.3 2002-December-30 Add I/R Reflow Condition added

1.4 2003-March-12 40 pin PKG. Drawing Revision

1.5 2003.May-29 Register Revision

1.6 2004 March-26 Electro-Optical Characteristic Revision

1.7 2004 June-18 Add Spectral Characteristics

Confidential HV7131R

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CONTENTS

General Description....................................................................................................................4

Features........................................................................................................................................4

Block Diagram .............................................................................................................................5

Pin Diagram..................................................................................................................................6

Pixel Array Structure...............................................................................................................7

Pin Description............................................................................................................................8

Functional Description ...............................................................................................................9

Register Description................................................................................................................. 11

Frame Timing.............................................................................................................................21

I2C Chip Interface......................................................................................................................24

AC/DC Characteristic s..............................................................................................................26

MCLK Duty Cycle.........................................................................................................27

ENB T iming..................................................................................................................27

RESETB T iming...........................................................................................................27

Electro-Optical Characteristics................................................................................................30

Electro-Optical Test Condition .............................................................................................30

Soldering..............................................................................................................................30

Package S pecification ..............................................................................................................32

MEMO..................................................................................................................................33

Confidential HV7131R

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General Description

HV7131R is a highly integrated single chip CMOS color image sensor implemented by proprietary

MagnaChip 0.30um CMOS sensor process realizing high sensitivity and wide dynamic rang e. Total pixel

array size is 656x502, an d 640x480 pixels ar e active. Each active pixel composed of 4 transistors, it has a

micro-lens to enhance sensitivity. and it converts photon energy to analog pixel voltage. On-chip 10-bit

Analog to Digital Converter (ADC) are configured to digitize analog pixel voltage, and on-chip

Correlated Double Sampling (CDS) scheme reduces Fixed Pattern Noise (FPN) dramatically. Auto Black

Level Compensation (ABLC) is using light blocking shield pixels which is placed top and botto m at core

pixel to measure the black level and compensation.

Features

z VGA resolution

z 5.04µm x 5.04µm active square pixel

z 1/4.5 inch optical format

z Total Pixel Array : 656x502 / Active Pixel Array : 640x480

z Bayer RGB color filter array

z Micro-lens for high sensitivity

z Low Power Operation : Voltage Range : 2.6V - 3.0V

z Max Frame rate : 30 frame/s at 25Mhz Master Cloc k (VGA)

z Package Types : CLCC 40LD, COB(Chip-on-Bo ard), COF(Chip-on-Flex)

z 10-bit Digital Image Sign al Data Bus

z Low Fixed Pattern Noise by Correlated Double Sampling

z Controllable full function throu gh standard IIC bus

z External Power Down

z Programmable Powe r Down mode

z Auto Black level compensation

z Flexible exposure time control

z St robe Control Signal generation for frame capture mode

z Programmable Video Windowing

z Integrated 10bit Analog to Digital Conversion

z Programmable Fram e Rate up to 30frame/sec

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Block Diagram

1. PGA : Programmable Gain Amplifier.

2. ADC : Analog to Digital Conve rte r.

3. CDS : Correlated Double Sampling.

4. SNR : Sensor Control Digital Logic.

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Pin Diagram

16 17 18 19 20 21 22 23 24 25

5 4 3 2 1

35

34

33

32

31

30

29

28

27

26

6

7

8

9

10

11

12

13

14

15

HV7131R

CLCC 40 PIN

Top View

NC

MCLK

VCLK

AGND

AVDD

NC

STROB

VSYNC

HSYNC

DGNDI

SDA

DGNDI

SCK

DGNDI

ENB

DGNDI

NC

RESETB

DVDDI

DVDDC

DGNDC

DGNDI

DAT A [0]

DAT A [1]

NC

DATA[2]

DATA[3]

DGNDI

DATA[4]

DATA[5]

DATA[6]

DATA[7]

DGNDI

DATA[8]

DATA[9]

40 39 38 37 36

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Pixel Array Structure

R

B G B G

G RG R

B GB G

GR G

……

R

B G B G

G RG R

B GB G

GR G

……

Metal Shielded B lack Level Array[2 line]

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Pin Description

Pin Type Symbol Description

1 G DGNDI Ground for I/O Buf f er.

2 I SCK I2C Clock Input.

3 G DGNDI Ground for I/O Buf f er.

4 I ENB

ENB signal enables Sensor : High(S ensor Enabled),

Low(Sensor Disabled, External Powe r Down)

5 G DGNDI Ground for I/O Buf f er.

6~7 N NC No Connection.

8 I MCLK Master Input Clock.

9 O VCLK Video Outp ut Clock.

10~11 G AGND Ground for Analog Block.

12~13 P AVDD Power for Analog Block.

14~15 N NC No Connection.

16 O DATA[9] Image Output Data Bit 9.

17 O DATA[8] Image Output Data Bit 8.

18 G DGNDI Ground for I/O Buf f er.

19 O DATA[7] Image Output Data Bit 7.

20 O DATA[6] Image Output Data Bit 6.

21 O DATA[5] Image Output Data Bit 5.

22 O DATA[4] Image Output Data Bit 4.

23 G DGNDI Ground for I/O Buf f er.

24 O DATA[3] Image Output Data Bit 3.

25 O DATA[2] Image Output Data Bit 2.

26~27 N NC No Connection.

28 O DATA[1] Image Output Data Bit 1.

29 O DATA[0] Image Output Data Bit 0.

30 G DGNDI Ground for I/O Buf f er.

31 G DGNDC Ground for Internal Digital Block.

32 P DVDDC Power for Internal Digital Block.

33 P DVDDI Power for I/O Buffer.

34 I RESETB Sensor Reset, Low Active.

35 N NC No Connection.

36 O STROBE Strobe Signal Output.

37 O VSYNC Video Frame Synchronization signal. / Frame Start output

VSYNC is active at start of image data frame.

38 O HSYNC Video Horizontal Line Synchronization signal. / Data is valid,

when HSYNC is High.

39 G DGNDI Ground for I/O Buf f er.

40 B SDA I2C Standard data I/O port.

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Functional Description

Pixel Architecture

Pixel architecture is a 4-transistor NMOS pixel design. The additional use of a dedicated

transfer transistor in the architecture reduces most of reset level noise so that fixed pattern

noise is not visible. Furthermore, micro-lens is placed upon each pixel in order to increase fill

factor so that high pixel sensitivity is achieved.

Sensor Imaging Operation

Imaging operation is implemented by the offset mechanism of integration domain and scan

domain(rolling shutter scheme). First integration plane is initiated, and after the programmed

integration time is elapsed, scan plane is initiated, then image data start being produced.

Integration

Time

Frame 0

Time

Time Integration

Plane

Frame 0

Integration

Plane

Frame 1

Scan

Plane

Frame 0

Scan

Plane

Frame 1

Time

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Spectral Characteristics

HV7131G Spectral Response

0

0.2

0.4

0.6

0.8

1

1.2

400 420 440 460 480 500 520 540 560 580 600 620 640 660 680 700

파장 (nm)

상대감도

B

G

R

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Register Description

Register Symbol Address Default Description

Device ID DEVID 00h 02h Product Identification, Revision

Number.

Sensor Control A SCTRA 01h 09h ClkDiv[6:4], ABLCEn[3], PxlVs[2],

XFlip[1], YFlip[0]

Sensor Control B SCTRB 02h 01h VCLK Disable[6], ADCPwDn[5], Black

Mode[4], Sleep[3], VsHsEn[2],

BLDataEn[1], StrobeEn[0]

Output Inversion OUTIV 03h 00h ByrDpcEn[6], ByrDpcTh[5:4],

ClkHSC[3], InvVSC[2], InvHSC[1],

InvVCLK[0]

Row Start Add Upper RSAU 10h 00h Row Start Address Upper Byte[8]

Row Start Add Lower RSAL 11h 02h Row Start Address Lower Byte[7:0]

Col. Start Add Upper CSAU 12h 00h Column Start Address Upper Byte[9:8]

Col. Start Add Lower CSAL 13h 02h Column Start Address Lower Byte[7:0]

Window Height Upper WIHU 14h 01h Window Height Upper Byte[8]

Window Height Lower WIHL 15h e2h Window Height Lower Byte[7:0]

Window Width Upper WIWU 16h 02h Window Width Upper Byte[9:8]

Window Width Lower WIWL 17h 82h Wind ow Width Lower Byte[7:0]

HBLANK T ime Upper HBLU 20h 00h HBLANK Time Upper Byte[15:8].

HBLANK T ime Lower HBLL 21h d0h HBLANK Time Lower Byte[7:0].

VBLANK Time Upper VBLU 22h 00h VBLANK Time Upper Byte[15:8].

VBLANK Time Lower VBLL 23h 08h VBLANK Time Lower Byte[7:0].

Integration T i me High INTH 25h 06h Integration T i me [23:16]

Integration Time

Middle INTM 26h 5Bh Integration Time [15:8]

Integration T i me Low INTL 27h 9ah Integration T i me [7:0]

Pre-amp Gain PAG 30h 10h Gain for Pre-amp (0.5~16.5 times with

8bit resolution) [7:0]

Red Color Gain RCG 31h 10h Gain for Red Pixel Read-out (0.5~2

times with 6bit resolution) [5:0]

Green Color Gain GCG 32h 10h Gain for Green Pixel Read-out (0.5~2

times with 6bit resolution [5:0]

Blue Color Gain BCG 33h 10h Gain for Blue Pixel Read-out (0.5~2

times with 6bit resolution [5:0]

Analog Bias Control A ACTRA 34h 17h CDS Bias [6:4], PGA Bias [3:0]

Analog Bias Control B ACTRB 35h 7fh Reset Clamp [7:4], ADC Bias [3:0]

Black Level Threshold BLCTH 40h ffh Auto Black Level Pixel Threshold

Value

Initial ADC Offset Red ORedI 41h 7fh Initial ADC Offset Red

Initial ADC Offset

Green OGrnI 42h 7fh Initial ADC Offset Green

Initial ADC Offset Blue OBluI 43h 7fh Initial ADC Offset Blue

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Device ID [DEVID : 00h : 02h]

7 6 5 4 3 2 1 0

Product ID Revision Number

0 0 0 0 0 0 1 0

High nibble represents Sensor Array Resol ution, Low nibble represents Revision Nu mber.

Sensor Control A [SCTRA : 01h : 09h]

7 6 5 4 3 2 1 0

Reserved ClkDiv ABLC En PxlVs X Flip Y Flip

- 0 0 0 1 0 0 1

Clock Division

Device Input Master Clock(IMC) for internal use. Internal Divided Clock Frequency(DCF) is

defined as Master Clock Frequency(MCF) divided by specified clock divisor. DCF is as follows

000 : DCF = MCLK, 001 : DCF = MCLK/2, 010 : DCF = MCLK/4

011 : DCF = MCLK/8, 100 : DCF = MCLK/16, 101 : DCF = MCLK/32

110 : DCF = MCLK/64, 111 : DCF = MCLK/128,

ABLC En

0 : Auto Black Level Compensation Disable

1 : Auto Black Level Compensation Enable

PxlVs

VBLANK unit : VBLANK Time value

0 : LCF unit

1 : SCF unit

X-Flip

0 : Normal.

1 : Image is horizontally flipped.

Y-Flip

0 : Normal.

1 : Image is vertically flipped.

Sensor Control B [SCTRB : 02h : 01h]

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7 6 5 4 3 2 1 0

Reserved VCLK ADC

PwDn

Black

Mode

Sleep

Mode

VsHsEn BLDataEn StrobeEn

- 0 0 0 0 0 0 1

VCLK

When this bit is high Vi deo Output Clock(VCLK) Disable

ADCPwDn

When this bit is high ADC Block goes to Power Down

Black Mode

Black and White Mode : Red and Blue gain use the Green gain when this bit is set to high.

0 : Color Mode

1 : Black and White Mode

Sleep Mode

Software Power Down

0 : Software power down mode off.

1 : Software power down mode on.

All internal digital blo ck goes to sleep mode with this bit set to high

VsHsEn

HSYNC in VBLANK : VBLANK is equivalent to VSYNC, and HSYNC is the inversion of

HBLANK, and this signal control whethe r HSYNC is active or not when VBLANK unit is LCF.

0 : There are no valid HSYNC signals during valid VSYNC signal.

1 : There are valid HSYNC signals during valid VSYNC signal. Number of valid HSYNC is

same as number of VBLANK register when VSYNC unit is line unit. Do not use this mode

when VSYNC unit is pixel unit

VSYNC

(VBLANK)

HSYNC

BLDataEn

Black Level Data Enable : HSYNC is generat ed for light-shielded pixels in 4 lines.

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StrobeEn

Strobe Enable : When StrobEn is high STROBE pin will indicates when strobe light should be

splashed in dark environm ent to get adequate lighted image

Output Inversion [OUTIV : 03h : X0h]

7 6 5 4 3 2 1 0

Reserved Clocked

HSYNC

VSYNC

Inversion

HSYNC

Inversion

VCLK

Inversion

- - - - 0 0 0 0

Clocked HSYNC

In HSYNC, VCLK is embedded, that is, HSYNC is toggling at VCLK rate during normal HSYNV

time

VSYNC Inversion

VSYNC output polarity is inverted

HSYNC Inversion

HSYNC output polarity is inverted

VCLK Inversion

HSYNC output polarity is inverted

Row Start Address Upper [RSAU : 10h : X0h]

7 6 5 4 3 2 1 0

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Reserved RSA[8]

- - - - - - - 0

Row Start Address Low [RSAL : 11h : 02h]

7 6 5 4 3 2 1 0

RSA[7:0]

0 0 0 0 0 0 1 0

Row Start Address register defines the row start address of image read out operation.

Column Start Address Upper [CSAU : 12h : X0h]

7 6 5 4 3 2 1 0

Reserved CSA[9:8]

- - - - - - 0 0

Column Start Address Low [CSAL : 13 h : 02h]

7 6 5 4 3 2 1 0

CSA[7:0]

0 0 0 0 0 0 1 0

Column Start Address register defines th e column start address of image read out operation.

Window Height Upper [WIHU : 14h : X1h]

7 6 5 4 3 2 1 0

Reserved WIH[8]

- - - - - - - 1

Window Height Lo w [WIHL : 15h : e2h]

7 6 5 4 3 2 1 0

WIH[7:0]

1 1 1 0 0 0 1 0

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Window Height register defines the height of image read out operation.

Window Width Upper [WIWU : 16h : X2h]

7 6 5 4 3 2 1 0

Reserved WIW[9:8]

- - - - - - 1 0

Window Width Low [WIWL : 17h : 82h]

7 6 5 4 3 2 1 0

WIW[7:0]

1 0 0 0 0 0 1 0

Window Width regi ster defines the width of image read out operation.

Horizontal Blanking Time Upper [HBLU : 20h : 00h]

7 6 5 4 3 2 1 0

HBLANK Time [15:8]

0 0 0 0 0 0 0 0

Horizontal Blanking Time Low [HBLL : 21h : d0h]

7 6 5 4 3 2 1 0

HBLANK Time [7:0]

1 1 0 1 0 0 0 0

HBLANK Time register defines data blank time between current line and next line by using

Sensor Clock Period unit (1/SCF), and should large r then 208(d0h)

Vertical Blanking Time High [VBLU : 22h : 00h]

7 6 5 4 3 2 1 0

VBLANK Time[15:8]

0 0 0 0 0 0 0 0

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Vertical Blanking Time Low [VBLL : 23h : 08h]

7 6 5 4 3 2 1 0

VBLANK Time[7:0]

0 0 0 0 1 0 0 0

VBLANK Time register defines active high duration of VSYNC output. Active high VSYNC

indicates frame boundary between continuous frames For VSYNC-HSYNC timing relation in the

frame transition, please refer to Frame T iming section

Integration Time High [INTH: 25h : 06h]

7 6 5 4 3 2 1 0

Integration Time [23:16]

0 0 0 0 0 1 1 0

Integration Time Middle [INTM: 26h: 5 bh]

7 6 5 4 3 2 1 0

Integration Time [15:8]

0 1 0 1 1 0 1 1

Integration Time Low [INTL: 27h: 9ah ]

7 6 5 4 3 2 1 0

Integration Time [7:0]

1 0 0 1 1 0 1 0

Integration time value register defines the time during which active pixel element evaluates

photon energy that is converted to digital data output by internal ADC processing. Integration

time is equivalent to exposure time of general camera. So that integration time need to be

increased in dark environment and decreased in bright environment. Maximum value of

integration time is (224-1) x sensor clock period (80ns, SCF 12.5MHz @ DCF 25MHz) = 1.34sec

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Preamp Gain [PAG : 30h : 10h]

7 6 5 4 3 2 1 0

Preamp Gain

0 0 0 1 0 0 0 0

Preamp Gain is common gain for R, G, B channel and used for auto exposure control.

Programmable range is from 0.5X ~ 16.5X. Default gain is 1.5X.

Gain = 0.5 + B<7:0>/16

Red Color Gain [RCG : 31h : 10h]

7 6 5 4 3 2 1 0

Reserved Red Color Gain

- - 0 1 0 0 0 0

Green Color Gain [GCG : 32h : 10h]

7 6 5 4 3 2 1 0

Reserved Green Color Gain

- - 0 1 0 0 0 0

Blue Color Gain [BCG : 33h : 10h]

7 6 5 4 3 2 1 0

Reserved Blue Color Gain

- - 0 1 0 0 0 0

There are three color gain registers for R, G, B pixels, respectively.

R, G, B color gain are used to amplify R, G, B channel. Programmabl e range is from 0.5X ~ 2.5X.

Default gain is 1X.

Gain = 0.5 + B<5:0>/32

Analog Bias Control A [A CTRA : 34h : 17h]

7 6 5 4 3 2 1 0

Reserved CDS Bias PGA Bias

- 0 0 1 0 1 1 1

PGA Bias

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Controls the amount of current in internal amplifier bias circuit to amplify pixel output effectively.

The larger register value increases the amount of current

CDS Bias

Controls the amount of current in internal CDS bias circuit to amplify pixel output effectively. The

larger register value incre ases the amount of current

Analog Bias Control B [A CTRB : 35h : 7fh]

7 6 5 4 3 2 1 0

Reset Clamp ADC Bias

0 1 1 1 1 1 1 1

Reset Level Clamp

Because extremely bright image like sun affects reset data voltage of pixel to lower, bright

image is captured as black image in image sensor regardless of correlated double sampling. To

solve this extraordinary phenomenon, we adopt the method to clamp reset data voltage. Reset

Level Clamp controls the reset data voltage to prevent inversion of extremely bright image. The

larger register value clamps the reset data level at highest voltage level. Default value is 7 to

clamp the reset dat a level at appropriate voltage lev el.

ADC Bias

ADC Bias controls the amount of current in ADC bias circuit to operate ADC effectively. The

larger register value incre ase the amount of current

Black Level Threshold [BLCTH : 40h : ffh]

7 6 5 4 3 2 1 0

Black Level Threshold

1 1 1 1 1 1 1 1

The register specifies the maximum value, which determines whether light shielded pixel output,

is valid. When light shielded pixel output exceeds this limit, the pixel is not accounted for black

level calculation.

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Initial ADC Offset Red [ORedI : 41h : 7fh]

7 6 5 4 3 2 1 0

Initial ADC Offset Red

0 1 1 1 1 1 1 1

Initial ADC Offset Green [OGrnI : 42h : 7fh]

7 6 5 4 3 2 1 0

Initial ADC Offset Green

0 1 1 1 1 1 1 1

Initial ADC Offset Blue [OBluI : 43h : 7fh]

7 6 5 4 3 2 1 0

Initial ADC Offset Blue

0 1 1 1 1 1 1 1

* Update ADC Offset = - (Average – Initial ADC Offset)

These values are using black level compensation in active pixel.

Average value is measured and calculated at light shielded pixel with ABLCEn is active.

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Frame Timing

For clear descri ption of frame timing, clocks’ acronym and relation are reminded in here again.

< Clock Acronym Definition >

MCF(Master Clock Freque ncy)

: MCLK DCF(Divided Clock Frequency)

: MCF/Clock Division

SCF(Sensor Clock Frequency)

: DCF/2

VCF( Video Clock Freque ncy)

: SCF LCF(Line Clock Frequency)

: 1/(HBLANJ Period + HSYNC Period

(HBLANK Time + Video Width Time)

SCP(Sensor Clock Period) = 1/SCF, LCP(Line Clock Period) = 1/LCF

< Frame Time Calculation >

ABLC Time = 4LCP * (HBLANK + 512 SCP)

Core Frame Time = IDLE Slot + Video Height * LCP

Real Frame Time = Integration Time + VBLANK * LCP for Integration Time > Core Frame Time

= Core Frame Time + VBLANK * LCP for Integration Time <= Core Frame Time

HOLD Slot Time = Integration Time - Core Frame Time for Integration Time > Core Frame Time

= 0 for Integration Time <= Core Frame Time

where IDLE Slot is 1LCP.

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1. VGA size when Programmable Window is disabled and ABLC enable

VGA Frame Timing Related Parameters

Master Clock Frequency(MCF) 25Mhz Clock Division MCF/1 = 25Mhz

Sensor Clock Frequency(SCF) DCF/2 =12.5Mhz Sensor Clock Period(SCP) 1/12.5Mhz = 80ns

HBLANK Value 208 VBLANK Value 8

VSYNC Mode Line Mode Line Clock Period(LCP) 848 SCPs

ABLC Enable Programmable Window OFF

If Integration Time < Core Frame Time, Real Frame Time is

2(208 + 640)SCPs + 4(208 + 512)SCPs + 480(208 + 640)SCPs + 8(208 + 640)SCPs

= 418400 SCPs =418400 X 80ns = 33.47msec = 29.87fps

else Real Frame Time is

Integration Time * SCPs + 8 * (208 +640) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger then core frame time

2. VGA size when Programmable Window is disabled and ABLC disable

LCP

(

848SCPs

)

IDLE SLOT

(

2LCP

)

HOLD SLOT

Integration time – Core Frame Time

VBLANK[VSYNC] (8LCP)

HBLANK

(208 SCPs) HSYNC(640 SCPs)

Active Data : 640 EA

Real Frame Time

Core Frame Time

480 LCPs

Video Height

4th Line Data Flow

HBLANK

(208 SCPs) HSYNC

(

640 SCPs

)

VCLK=12.5[Mhz]

LCP = 848 SCPs

5th Line Data Flow

482th Line Data Flow

483th Line Data Flow

Video Width

(

640SCP

)

0~3 Line Data Flow for ABLC

A

BLC T ime

Hi

-

Z

Valid Data

DATA[9:0]

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VGA Frame Timing Related Parameters

Master Clock Frequency(MCF) 25Mhz Clock Division MCF/1 = 25Mhz

Sensor Clock Frequency(SCF) DCF/2 =12.5Mhz Sensor Clock Period(SCP) 1/12.5Mhz = 80ns

HBLANK Value 208 VBLANK Value 8

VSYNC Mode Line Mode Line Clock Period(LCP) 848 SCPs

ABLC Disable Programmable Window OFF

If Integration Time < Core Frame Time, Real Frame Time is

2(208 + 640)SCPs + 480(208 + 640)SCPs + 8(208 + 640)SCPs

= 415520 SCPs =415520 X 80ns = 33.24msec = 30fps

else Real Frame Time is

Integration Time * SCPs + 8 * (208 +640) SCPs.

HOLD SLOT in frame timing appears only if integration time is larger then core frame time

I2C Chip Interface

LCP

(

848SCPs

)

IDLE SLOT

(

2LCP

)

HOLD SLOT

Integration time – Core Frame Time

VBLANK[VSYNC] (8LCP)

HBLANK

(208 SCPs) HSYNC(640 SCPs)

Active Data : 640 EA

Real Frame Time

Core Frame Time

480 LCPs

Video Height

4th Line Data Flow

HBLANK

(208 SCPs) HSYNC

(

640 SCPs

)

VCLK=12.5[Mhz]

LCP = 848 SCPs

5th Line Data Flow

482th Line Data Flow

483th Line Data Flow

Video Width

(

640SCP

)

Hi

-

Z

Valid Data

DATA[9:0]

Confidential HV7131R

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The serial bus interface consists of the SDA(serial data) and SCK(serial clock) pins. HV7131GR

sensor can operate only as a slave. The SCK only controls the serial interface. However, MCLK

should be supplied and RESET should be high signal during controlling the serial interface. The

Start condition is that logic transition (High to Low) on the SDA pin while the SCK pin is at high.

The Stop condition is that logic transition (Low to High) on the SDA pin while the SCK pin is at

high. To generate Acknowledge signal, the Sensor drives the SDA low when the SCK is high.

Every byte consists of 8 bits. Each byte transferred on the bus must be followed by an

Acknowledge. The most significant bit of the byte should always be transmitted first.

Register Write Sequences

One Byte Write

S 22H A 01H A 03H A P

*1 *2 *3 *4 *5 *6 *7 *8

Set "Sensor Control A" registe r into Window mode

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device a ddress + R/W bit]

*3. Read: acknowledge from sen so r

*4. Drive: 01H [sub-address]

*5. Read: acknowledge from sen so r

*6. Drive: 03H [Video Mode : CIF]

*7. Read: acknowledge from sen so r

*8. Drive: I2C stop condition

1 2 8 9

A

CK

MSB LSB

SD

A

SCK

START 12 89

A

CK STOP

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Multiple Byte Write using Auto Addr ess Increment

S 22H A 10H A 00H A 64H A P

*1 *2 *3 *4 *5 *6 *7 *8 *9 *10

Set "HSYNC Blanking High/Low" register as 0064H with auto address increment

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device a ddress + R/W bit]

*3. Read: acknowledge from sen so r

*4. Drive: 10H [sub-address]

*5. Read: acknowledge from sen so r

*6. Drive: 00H [HSYNC Blanking High]

*7. Read: acknowledge from sen so r

*8. Drive: 64H [HSYNC Blanking Low]

*9. Read: acknowledge from sen so r

*10. Drive: I2C stop condition

Register Read Sequence

S 22H A 01H A S 23H A 13H A P

*1 *2 *3 *4 *5 *6 *7 *8 *9 *1

0 *11

Read "Sensor Control A" register from HV71 31GR

*1. Drive: I2C start condition

*2. Drive: 22H(001_0001 + 0) [device address + R/W bit(be careful. R/W=0)]

*3. Read: acknowledge from sen so r

*4. Drive: 01H [sub-address]

*5. Read: acknowledge from sen so r

*6. Drive: I2C start condition

*7. Drive: 23H(001_0001 + 1) [device address + R/W bit(be careful. R/W=1)]

*8. Read: acknowledge from sen so r

*9. Read: Read “13H(Value of Sensor Control A) ” from sensor

*10. Drive: acknowledge to sensor. If there is more data bytes to read, SDA should be driven to

low and data read states(*9, *10) is repeated. Otherwise SDA should be driven to

high to prepare for the read transaction end.

*11. Drive: I2C stop condition

AC/DC Characteristics

Confidential HV7131R

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licenses are implied.

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Absolute Maximum Ratings

Symbol Parameter Units Min. Max.

Vdpp Digital supply voltage Volts -0.3 7.0

Vapp Analog supply voltage Volts -0.3 7.0

Vipp Input signal voltage Volts -0.3 7.0

Top Operating Temperature °C -10 50

Tst Storage Temperature °C -30 80

Caution: Stresses exceeding the absolute maximum ratings may induce failure.

DC Operating Conditions

Symbol Parameter Units Min. Max. Load[pF] Notes

Vdd Internal operation supply voltage Volt 2.6 3.0

Vih Input voltage logic "1" Volt 2.0 3.0 6.5

Vil Input voltage logic "0" Volt 0 0.8 6.5

Voh Output voltage logic "1" Volt 2.15 60 at Ioh =

-1mA

Vol Output voltage logic "0" Volt 0.4 60

Ioh Output High Current mA -4 60

Iol Output Low Current mA 4 60

Ta Ambient operating temperature Celsius -10 50

AC Operating Conditions

Symbol Parameter Max Operation Frequency Unit s Notes

MCLK Main clock frequency 25 MHz 1

SCK I2C clock frequency 400 KHz 2

INORMAL Power Consumption in

Normal mode 30.953 @ 30fps, 25MHz mA

IDOWN_HARD Power Consumption in

Hard Power Down mode 0.095 @ 25MHz uA

IDOWN_SOFT Power Consumption in

Soft Power Down mode 208.815 @ 25MHz uA

1. MCLK may be divided by internal clock division logic for easy integration with high speed

video codec.

2. SCK is driven by host processor. For the detail serial bus timing, refer to I2C chip interface

section

Input AC Characteristics

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MCLK Duty Cy cle

TA = 40% ~ 60% of TMCLK, TB = 40% ~ 60% of TMCLK , TA + TB = TMCLK

ENB Tim i ng

ENB pin enables sensor. If you set ENB pin to low, sensor goes to power down. Though sensor

remains power down, you can program the registers by above IIC protocol. After ENB is

changed to high, the regist ers that you set in power down are newly updated.

If you want software power down with ENB pin high, set sleep mode in SCTRB(02H)re gister.

RESETB Timing

RESETB pin initializes the registers to default value. When RESETB pin is low, initialization is

done. HV7131GR is automatically reset the chip when powe r on.

We recommend to initialize the registers by using RESETB pin. TR: RESETB valid minimum

time: 10 MCLK periods.

Output AC Characteristics

All output timing delays are measured with output load 60[pF]. Output delay includes the internal

MCLK

TMCLK

TB

TA

VDD / 2

TR

RESETB

MCLK

Sensor Ready to Operate

ENB

VSYNC

HSYNC

DATA[9:0]

VCLK

Confidential HV7131R

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clock path delay and output driving delay that changes in respect to the output load, the

operating environment, and a board design. Due to the variable valid time delay of the output,

RGB output signals DATA[9:0], HSYNC, and VSYNC may be latched in the negative edge of

VCLK for the stable data transfer between the image sensor and video code c.

D ATA [9 :0 ]

VCLK

(N o n In ve rte d )

X Data 0 Data 1 Data 2

HSYNC

Data 3

M inimum delay : 0.5XMaster Clock Period

I2C Bus Timing

SDA

SCK

stop start

tbuf tlow tr

thd;sta thd;dat thigh tsu;dat tsu;sta tsu;sto

stop start

tfthd;sta

Confidential HV7131R

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Parameter Symbol Min. Max. Unit

SCK clock frequency fsck 0 400 KHz

Time that I2C bus must be free before a

new transmission can start t

buf 1.2 - us

Hold time for a START thd;sta 1.0 - us

LOW period of SCK tlow 1.2 - us

HIGH period of SCK thigh 1.0 - us

Setup time for START tsu;sta 1.2 - us

Data hold time thd;dat 1.3 - us

Data setup time tsu;dat 250 - ns

Rise time of both SDA and SCK tr - 250 ns

Fall time of both SDA and SCK tf - 300 ns

Setup time for STOP tsu;sto 1.2 - us

Capacitive load of SCK/SDA Cb - - pf

Confidential HV7131R

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licenses are implied.

- 30 - 2004 MagnaCh ip Semiconductor Ltd.

Electro-Optical Characteristics

Parameter Units Min. Typical Max. Note

2053.9 2480.482 3121.600 Green

1356 1657.460 2093.500 Red

Sensitivity mV /

luxxsec 1362.3 1656.700 2074.100 Blue

Dark Signal code 0.000 10.728 31.990

1022.980 1023.000 1023.000 Green

1022.990 1023.000 1023.000 Red

Output

Saturation

Signal mV 1023.000 1023.000 1023.000 Blue

4.428 6.627 11.861 Dynamic DVDD Power

Consumption mA 19.572 24.326 30.009 Dynamic AVDD

0.000 0.005 27.130 Static DVDD

Power

Consumption uA 0.000 0.090 29.610 Static AVDD

182.160 208.806 259.660 Sleep DVDD Power

Consumption uA 0.00 0.009 17.580 Sleep AVDD

- Color temperature of light source: 3200K / IR cut-off filter (CM-500S, 1mm thickness) is used.

Soldering

Infrared(IR) / Convection solde r reflo w condition

Parameter Convection or IR/Convection

Av erage ramp-u p rate(18 3°C to Peak) 3 °C / second max.

Preheat temperature 125(±25) °C 120 second max.

Temperature maintained above 183°C 60 – 150 second

Time within 235°C of actual peak temperature 10 – 20 second

Peak temperature range (220 +5/-0) °C or (235 +5/-0) °C

Ramp-down rat 6°C / second max.

Time 25°C to peak temperature 6 minute

Confidential HV7131R

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30 60 90 120 180 210 240 270 300 330 360150

125

180

235

Temp.( °C)

Time(seconds)

120 sec. max

60 ~ 150 sec. max

10 ~ 20 sec.

Confidential HV7131R

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Semiconductor Ltd. does not assume any responsibility for use of circuits described and no patent

licenses are implied.

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Package Specification

- 40 PIN CLCC

-

Confidential HV7131R

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licenses are implied.

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MEMO

MagnaChip Semiconductor Ltd.

* Contact Point *

CIS Marketing Team

15Floor, MagnaChip Youngdong Bldg. 891 Daechi-Dong Kangnam-Gu Seoul 135-738 Republic of Korea

Tel: 82-2-3459-3374

Fax: 82-2-34 5 9- 5 580

E-mail : hanho.lee@MagnaChip.com