SDRAM
AS4SD16M16
Preliminary
Austin Semiconductor, Inc.
AS4SD16M16
Rev. 1.0 4/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
• Configuration: 16 Meg x 16 (4 Meg x 16 x 4 banks)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can be
changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE and Auto Refresh Modes
• Self Refresh Mode
• 64ms, 8,192-cycle refresh
• WRITE Recovery (tWR = “2 CLK”)
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS MARKING
• Plastic Package - OCPL*
54-pin TSOP (400 mil) DG No. 901
•Timing (Cycle Time)
7.5ns @ CL = 3 (PC133) or -75
7.5ns @ CL = 2 (PC100)
•Operating Temperature Ranges
-Industrial Temp (-40°C to 85° C) IT
-Industrial Plus Temp (-40°C to +110°C) IT+
-Military Temp (-55°C to 125°C) XT***
*Off-center parting line
**CL = CAS (READ) latency
***Consult Factory
PIN ASSIGNMENT
(Top View)
54-Pin TSOP
Note: “\” indicates an active low.
256 MB: 16 Meg x 16 SDRAM
Synchronous DRAM Memory
For more products and information
please visit our web site at
www.austinsemiconductor.com
KEY TIMING PARAMETERS
SPEED CLOCK SETUP HOLD
GRADE FREQUENCY CL = 2** CL = 3** TIME TIME
-75 133 MHz – 5.4ns 1.5ns 0.8ns
-75 100 MHz 6ns – 1.5ns 0.8ns
ACCESS TIME
A12
Configuration 4 Meg x 16 x 4 banks
Refresh Count 8K
Row Addressing 8K (A0-A12)
Bank Addressing 4 (BA0, BA1)
Column Addressing 512 (A0-A8)
16 Meg x 16