8K x 8 Registered PROM
CY7C265
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
April 1988 – Revised April 1995
1CY7C26 5
Features
• CMOS for optimum speed/power
• High speed (commercial and military)
—15 ns address set-up
—12 ns clock to output
• Low power
—660 mW (commercial)
—7 70 mW (mi litary)
• On-chip edge-triggered re gisters
—Ideal for pipelined micro programme d system s
• EPROM technology
—100% programmable
—Reprogrammable (7C265W)
• 5V ±10% VCC, commercial and military
• Capable of withsta nding >2001V static discharge
• Slim 28-pin, 300-mil plastic or hermet ic DIP
Functio nal D escription
The CY7C265 is a 8192 x 8 registered PROM. It is organized
as 8,192 word s by 8 bits wid e, and has a pipeline output reg-
ister . In addition, the device features a programmable initialize
byte that may be loaded into the pipelin e register with the ini-
tiali ze signal. The programmable initiali ze byte is the 8,193rd
byte in the PROM and its value is programmed at the time of
use.
Packaged in 28 pins, the PROM has 13 address signals (A0
through A12), 8 data out signals (O0 through O 7), E/I (enable
or initialize), and CLOCK.
CLOCK functions as a pipeline clock, loading the c ontents of
the addressed memory location into the pipeline register on
each rising edge. The data will appear on the outputs if th ey
are enabled. One pin on the CY7C265 is programmed to per-
form either the enable or the initialize function.
If the asynch ronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (ES) is being us ed, the outputs will
go to the OFF or high-imped ance s tate up on the next positive
clock edge after the synchronous enabl e input is switched to
a HIGH level. I f the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive cloc k edge, the
address a nd synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIG H tran sition of the clock. Thi s unique feature al-
lows the CY7C265 decoders and sense amplifiers to access
the next location while previously a ddressed data remains sta-
ble on the outputs.
If the E/I pi n is used for INIT (asynchronous), then the outputs
are permanently enabled. The init ialize function is useful dur-
ing power-up and time-out sequences, and can facilitate im-
plementation of other sop histicated functions such as a b ui lt -in
“jump start” address. When activated, the i nitialize control in-
put causes the contents of a user programmed 8193rd 8-bit
word to be loaded into the on-chip register. Each bit is pro-
gr ammable and the ini tialize function can be used to load any
desired combination of 1’s a nd 0’s into the register. In the un-
programmed state, activating INIT will generate a register
clear (all outputs LOW). If all the bits of the initialize word are
programmed to be a 1, activating INIT performs a register pre-
set (all outputs HIGH).
Applying a LOW to the INIT i nput causes an immediate load
of the programmed initialize word into the pipeline register and
onto the outputs. The INIT LOW disables cl ock and m ust re-
turn HIGH to enable clock independent of all other inputs, in-
cluding the clock.
CY7C265
2
F
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature wi th
Power Applied.............................................–55°C to +125°C
Supply Voltage to Gro und Pot ential..... .......... –0.5V to +7.0V
DC Voltage Applied to Output s
in High Z State............................................... –0.5V to +7.0V
DC Input Voltage............................................ –3.0V to +7.0V
DC Program Voltage.....................................................13.0V
UV Exposure.................................................7258 Wsec/cm 2
Static Discharge Voltage...........................................>2001V
(pe r MIL-STD-883, Method 3015)
Latch-Up Current....... ..............................................>200 mA
Logic Block Diagram Pin Configurations
C265–1
C265–2
Top View
LCC/PLCC (Opaque Only)
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
Top View
DIP/Flatpack
15
7C265
A7
A6
A5
A4
A3
A2
GND
CLK
A1
A0
O0
O1
O2
GND
VCC
A8
A9
A10
A11
A12
E/ES,I
GND
GND
O7
O6
O4
O5
O3
C265–3
O7
O6
O5
O4
O3
O2
O1
O0
A12
A11
A10
A9
A8
A7
A6
A5
COLUMN
MULTIPLEXER
A4
A3
A2
A1
PROGRAMMABLE
MULTIPLEXER
ADDRESS
DECODER
PROGRAMMABLE
ARRAY
8-BIT
EDGE-
TRIGGERED
REGISTER
CLK
INIT/E/ES
CLK
D
C
O
28
4
5
6
7
8
9
10
321 27
13 14 15 16 17
26
25
24
23
22
21
20
1112 19
O018
A0
A1
A3
A2
A10
GND
A11
A12
GND
O7
GND
CLK E/ES,I
A4A5A6A7VCC A8A9
O1O2GND O3O4O5O6
A5
A0
ROW
ADDRESS
COLUMN
ADDRESS
Selection Gu ides
7C265–15 7C265–25 7C265–40 7C265–50
M inimum Addre ss Set -Up Time (ns) 15 25 40 50
M aximum Clock to Output (ns) 12 15 20 25
M aximum Operating Curr ent (mA) Com’l 120 120 100 80
Mil 140 140 120
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Industrial[1] –40°C to +85°C 5V ±10%
Military[2] –55°C to +125°C 5V ±10%
Notes:
1. Contact a Cypress representative for industrial t emperature range spec-
ifications.
2. TA is the “instant on” case temperature.
CY7C265
3
Electrical Characteristics Over the Operating Range[3]
7C265–15,
25 7C265–40 7C265–50
Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 V
VCC = Min., IOH = –4.0 mA 2.4 2.4
VOL Output LOW Vol tage VCC = Min. , IOL = 8.0 mA Com’l 0.4 V
VCC = Min., IOL = 12.0 mA 0.4 0.4
VCC = Min., IOL = 6.0 mA Mil 0.4
VCC = Min., IOL = 8.0 mA 0.4
VIH Input HIGH Voltage 2.0 2.0 2.0 V
VIL Input LOW Voltage 0.8 0.8 0.8 V
IIX In put Lo ad Current GND < VIN < VCC –10 +10 –10 +10 –10 +10 µA
IOZ Output Leakage Current GND < VOUT < VCC,
Output Disabled –40 +40 –40 +40 –40 +40 µA
IOS[4] Output Short Circ uit Current VCC = Max., VOUT = GND 90 90 90 mA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA Com’l 120 100 80 mA
Mil 140 120
VPP Programming Supply Voltage 12 13 12 13 12 13 V
IPP Programming Supply Current 50 50 50 mA
VIHP Input HIGH Programming
Voltage 3.0 3.0 3.0 V
VILP Input LOW Programming
Voltage 0.4 0.4 0.4 V
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output C apacitance 10 pF
Notes:
3. See the last page of this specification for Group A subgroup testing information.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
5. See Introduction to CMOS PROMs in this Data Book for general information on testing.
CY7C265
4
AC Test Loads and Waveforms
R2 333Ω
(403ΩMIL)
3.0V
5V
OUTPUT
R1500
(658ΩMIL)
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤5ns ≤5ns
5V
OUTPUT
5pF
INCLUDING
JIG AN D
SCOPE
(a) NormalLoad (b) High Z Load C269–4 C269–5
OUTPUT RTH 200Ω
5V
OUTPUT 5V
OUTPUT
R1 250Ω
30 pF
INCLUDING
JIG AND
SCOPE
5pF
INCLUDING
JIG AN D
SCOPE
(c) Normal Load (d) High Z Load
C269–6
OUTPUT 2.0V
RTH 100Ω
R1 250Ω
R1500Ω
(658ΩMIL)
R2333Ω
(403ΩMIL)
R2 167ΩR2 167Ω
250ΩMIL
Test Load for –15 through –25 speeds
Test Load for – 40 through –50 speeds
Equivalent to: THÉ VENIN EQUIVALENT
Equivalent to: THÉ VENIN EQUIVALENT
Switching Characteristics Ove r the Operating Range[3, 5]
7C265–15 7C265–25 7C265–40 7C265–50
Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit
tAS Address Set-Up to Clo ck 15 25 40 50 ns
tHA Address Hold from Clock 0 0 0 0 ns
tCO Clock to Output Valid 12 15 20 25 ns
tPWC Clock Pulse Width 12 15 15 20 ns
tSES ES Set-Up to Clock
(Sync. Enable Only) 12 15 15 15 ns
tHES ES Hold from Clock 5 5 5 5 ns
tDI INIT to Output Valid 15 18 25 35 ns
tRI INIT Recovery to Clo ck 12 15 20 25 ns
tPWI INIT Pulse Width 12 15 25 35 ns
tCOS Output Valid from Clock
(Sync. Mode) 12 15 20 25 ns
tHZC Output Inactive from Clock
(Sync. Mode) 12 15 20 25 ns
tDOE Output Val id from E LOW
(Async. Mode) 12 15 20 25 ns
tHZE Output Inactive from E HIGH
(Async. Mode) 12 15 20 25 ns
CY7C265
5
Erasure Characteristics
Wavelengths of light less th an 4000 angstroms begin to eras e
the 7C265 in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlig ht or fluorescent lighting for extended pe-
riods of time.
The recommended dose of ultraviolet light for erasure is a
wavelength of 25 37 a ngstroms for a minimum dose (UV inten-
sity • exposure time) of 25 Wsec/cm2. For an ultraviolet lamp
with a 12 mW/cm2 power rating the exposure time would be
approximately 45 minutes. The 7C265 needs to be within one
inch of the lamp during erasure. Permanent damage may re-
sult if the PROM is exposed to high-intensity UV light for an
extended period of time. 7258 Wsec/cm 2 is the recommended
maximum dosage.
Control Byte
00 Asynchronous output enable (default condition)
01 Synchronous output enable
02 Asynchronous initialize
Programming Modes
The 7C265 offers a limited selection of programmed architec-
tures. Programming these features should be done with a sin-
gle 10-ms-wide pulse in place of the intelligent algorithm,
mainly because these features are verified operationally, not
with the VFY pin. Architecture programming is implemented by
applying the supervoltage to two additional pins during pro-
gramming. In programming the 7C265 architecture, VPP is
applied to pins 3, 9, and 22. The c hoi ce of a particular mode
depends on the stat e s of th e other pin s during program ming,
so it is important that the condition of the other pins be met as
set forth in the mode table. The considerations that apply with
respect to power-up and power-down during intelligent pro-
gram ming also ap ply during architecture programm ing. Once
the supervoltages have bee n e s tab lished a nd the co rrect logic
states exist on the o the r device pins, p rogramming may be gin.
Pro gramming i s a ccompli shed by pulli ng PGM from HIGH to
LOW and then back to HIGH with a pulse width equal to 10 ms.
Switching Waveform
tHZC
tPWC
C265–7
tHES
VALID DATA
tCOS tCO
tPWI
tDI
ADDRESS
CLOCK
SYNCHRONOUS
ENABLE
(PROGRAMMABLE)
ASYNCHRONOUS INIT
(PROGRAMMABLE)
OUTPUT
ASYNCHRONOUS
ENABLE
tHZE
tSES
tAH
tAS
tDOE
tRI
Bit Ma p Data
Programmer A ddres s (Hex.) RAM Data
Decimal Hex Contents
0
.
.
8191
8192
8193
0
.
.
1FFF
2000
2001
Data
.
.
Data
INIT Byte
Control Byte
CY7C265
6
Prog ramming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section . Prog ramming algori thms can be ob-
tained fr om any Cypress r epresentative.
Table 1. Mode Selectio n
Pin Functi on
Read or Output Disable A12 A11 A10 – A7A6A5A4 – A3A2
Mode Other A12 A11 A10 – A7A6A5A4 – A3A2
Asynchr onous Enable Read A12 A11 A10 – A7A6A5A4 – A3A2
Synchr o n ous Enable Read A12 A11 A10 – A7A6A5A4 – A3A2
Asynchronous Initiali zation Read A12 A11 A10 – A7A6A5A4 – A3A2
Program Memory A12 A11 A10 – A7A6A5A4 – A3A2
Pro gram Verify A12 A11 A10 – A7A6A5A4 – A3A2
Program Inhibit A12 A11 A10 – A7A6A5A4 – A3A2
Program Synchr o n ous Enable VIHP VIHP A10 – A7VIHP VPP A4 – A3VIHP
Program Initialize VILP VIHP A10 – A7VIHP VPP A4 – A3VILP
Program Initi al Byte A12 VILP A10 – A7VIHP VPP A4 – A3VILP
Pin Function
Read or Output Disable A1A0GND CLK GND E, I O7 – O0
Mode Other A1A0PGM CLK VFY VPP D7 – D0
Asynchr onous Enable Read A1A0GND VIL GND VIL O7 – O0
Synchr o n ous Enable Read A1A0GND VIL/VIH GND VIL O7 – O0
Asynchronous Initiali zation Read A1A0GND VIL GND VIL O7 – O0
Program Memory A1A0VILP VILP VIHP VPP D7 – D0
Pro gram Verify A1A0VIHP VILP VILP VPP O7 – O0
Program Inhibit A1A0VIHP VILP VIHP VPP High Z
Program Synchr o n ous Enable VPP VILP VILP VILP VIHP VPP D7 – D0
Program Initialize VPP VILP VILP VILP VIHP VPP D7 – D0
Program Initi al Byte VPP VIHP VILP VILP VIHP VPP D7 – D0
Figure 1. Programming Pinout
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A7
A6
A5
A4
A3
A2
PGM
CLK
A1
A0
D0
D1
D2
GND
VCC
A8
A9
A10
A11
A12
VPP
NA
VFY
D7
D6
D4
D5
D3
C265–8
C265–9
15
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19D018
A0
A1
A3
A2
D7
PGM
CLK
A10
VPP
VFY
A12
NA
A11
LCC/PLCC (Opaque Only)DIP/Flatpack
CY7C265
7
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0
1.6
1.4
1.2
1.0
0.8
–55 25 125
–55 25 125
1.2
1.1
60
40
30
20
10
0.0 1.0 2.0 3.0 4.0
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.6
1.2
150
175
125
75
50
25
0.0 1.0 2.0 3.0 4.0
0
100
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
ICC
ICC
VCC =5.0V
TA=25°C
0.6
0
30
25
20
15
10
5
0 200 400 600 800
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
01000
VCC =4.5V
TA=25°C
AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V)
TA=25°C
f=MAX.
50
35
1.00
1.05
0.95
0.85
0.80
0.75
025 5075
100
0.70
0.90
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
CLOCK PERIOD (ns)
VCC =5.5V
TA=25°C
CY7C265
8
MIL ITARY SPEC IFICATIONS
Group A Subgroup Testing
Document #: 38–00084–E
Orde rin g Inf orm a tio n[6]
Speed
(ns) ICC
(mA) Ordering Code Package
Name Package Ty pe Operating
Range
15 120 CY7C265–15JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C265–15PC P21 28-Lead (300-Mil) Molded DIP
CY7C265–15WC W22 28-Lead (300-Mil) Windowed CerDI P
140 CY7C265–15DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C265–15LMB L64 28-Square Leadless Chip Carrier
CY7C265–15QMB Q64 28-Pin Windowed Leadless Chip Car rier
CY7C265–15WMB W22 28-Lead (300-Mil) Windowed CerDIP
25 120 CY7C265–25JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C265–25PC P21 28-Lead (300-Mil) Molded DIP
CY7C265–25WC W22 28-Lead (300-Mil) Windowed CerDI P
140 CY7C265–25DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C265–25LMB L64 28-Square Leadless Chip Carrier
CY7C265–25QMB Q64 28-Pin Windowed Leadless Chip Car rier
CY7C265–25WMB W22 28-Lead (300-Mil) Windowed CerDIP
40 100 CY7C265–40JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C265–40PC P21 28-Lead (300-Mil) Molded DIP
CY7C265–40WC W22 28-Lead (300-Mil) Windowed CerDI P
50 80 CY7C265–50JC J64 28-Lead Plastic Leaded Chip Carrier Commercial
CY7C265–50PC P21 28-Lead (300-Mil) Molded DIP
CY7C265–50WC W22 28-Lead (300-Mil) Windowed CerDI P
120 CY7C265–50DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C265–50LMB L64 28-Square Leadless Chip Carrier
CY7C265–50QMB Q64 28-Pin Windowed Leadless Chip Car rier
CY7C265–50WMB W22 28-Lead (300-Mil) Windowed CerDIP
Note:
6. Most of these products are available in industrial temperature range. Contact a Cypress representative for specifica t ions and product
availability.
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tAS 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
tPW 7, 8, 9, 10, 11
tSES 7, 8, 9, 10, 11
tHES 7, 8, 9, 10, 11
tCOS 7, 8, 9, 10, 11
CY7C265
9
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL–STD–1835 D–15 Config. A 28-Lead Plastic Leaded Chip Carrier J64
28-Square Leadless Chip Carrier L64
MIL–STD–1835 C–4 28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
CY7C265
© Cypress Semiconductor Corporation, 1995. The informatio n contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cy press Semi conductor p roduct. Nor does it convey or im ply any li cense under patent or other rights. Cypress Semicondu ctor does not authori ze
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
28-Lead (300-Mil) Molded DIP P21
28-Lead (300-Mil) Windowed CerDIP W22
MIL–STD–1835 D–15 Config. A
