NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals Field-programmable microcontroller peripheral bLE D M@@ 6653924 0071907 714 MBSIC3 Preliminary specification PSD313 a Key Features May, 1993 {4 Single Chip Programmable Peripheral for Microcontroller-based Applications 19 Individually Configurable I/O pins that can be used as: Microcontroller /O port expansion Programmable Address Decoder (PAD) O Latched address output Open drain or CMOS J Two Programmable Arrays (PAD A & PAD B) Total of 40 Product Terms and up to 16 Inputs and 24 Outputs Direct Address Decoding up to 1 Meg address space and up to 16 Meg with paging Logic replacement {J No Glue Microcontroller Chip-Set Built-in address latches for multiplexed address/data bus Non-multtiplexed address/data bus mode 8-bit data bus width ALE and Reset polarity programmable Selectable modes for read _and write control bus as RD/WR, R/W/E, or RW/DS PSEN pin for 8051 users QO Built-In Page Logic To Expand the Address Space of Microcontrollers with Limited Address Space Capabilities Upto 16 pages 133 Cc T4I-17-6 5 1M bit of UV EPROM Configurable as 128K x 8 Divides into 8 equal mappable blocks for optimized mapping Block resolution is 16K x 8 120 ns EPROM access time, including input latches and PAD address decoding. 16 Kbit Static RAM Configurable as 2K x 8 120 ns SRAM access time, including input latches and PAD address decoding Address/Data Track Mode Enables easy Interface to Shared Resources (e.g., Mail Box SRAM) with other Microcontrollers or a Host Processor Built-In Security Locks the PSD313 and PAD Decoding Configuration Available in a Choice of Packages 44 Pin PLDCC and CLDCC Simple Menu-Driven Software: Configure the PSD313 on an IBM PC Pin Compatible with the PSD311 and PSD312NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals Field-programmabie microcontroller peripheral BLE D MM 6653924 0071908 bS4 MBSIC3 Preliminary specification PSD313 May, 1993 Security Security Mode in the PSD3XxX locks the software. In window packages, the mode is Mode contents of the PAD A , PAD B and all the erasable through UV full part erasure. In configuration bits. The EPROM, SRAM, the security mode, the PSD3XxX contents and I/O contents can be accessed only cannot be copied on a programmer. through the PAD. The Security Mode can be set by the MAPLE or Programming CMiser-Bit The CMiser-Bit provides a programmable In the default mode, or if the PSD3XxX< is option for power-sensitive applications that configured without programming the require further reduction in power CMiser-Bit (CMiser = 0), the device consumption. The CMiser-Bit (CMiser = 1) operates at specified speed and power in the Maple portion of the PSD3XX sytem rating as specified in the A.C. and D.C. development software can be used to Characteristics. reduce power consumption. The CMiser-Bit However, if the CMiser-Bit is programmed turns off the EPROM blocks in the PSD3XX (CMiser ~ 1), the device consumes even whenever the EPROM is not accessed, ce : : . : lower current, and is reflected in the data thereby reducing the active current heet. Thi deh dder i consumed by the PSD3XX. Sheet. This mode has an adder in propagation delay in T5, T6, and T7 parameters in the A.C. Characteristics, and should be added to compute worst-case timing requirements in the application. Absolute Symbol Parameter Condition Min | Max | Unit pacimum T. Storage Temperature GERDIP = 85 + 150 c alings ste ge temp PLASTIC -e5 | +125] Voltage on any Pin With Respect to GND | -0.6 +7 Vv Programming . Vpp Supply Voltage With Respectto GND | 0.6 +14 Vv Voc Supply Voltage With Respect to GND | -0.6 +7 Vv ESD Protection >2000 Vv NOTE: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at theses or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure ta Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Operating Vec Tolerance Range Temperature Vec o Range 12 15 -20 Commercial 0 C to +70C +5V + 10% + 10% +10% Industrial A0 C to +80C +5V +10% | +10% Military ~55 C to +125C +5V + 10% Recommended Symbol! Parameter Conditions Min | Typ | Max | Unit Conditions Veco Supply Voltage All Speeds 45 5 5 | V Vin High-level Input Voltage |} Vec =4.5Vto5.5V 2 Vv Vit Low-level Input Voltage Veco =45Vto55V 0 0.8 Vv 134NAPC/PHILIPS SEMICOND bLE D> MM 6653924 0071909 590 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 DC CMiser = 1 Characteristics | Symbol| _ Parameter Conditions Subtract: Min | Typ | Max| Min; Typ | Max | Unit lo. = 20 pA 0.01] 0.1 Vv Vo Output Low Voc =4.5V Voltage lol =8 MA Veo =4.5V 0.15 | 0.45 lon = -20 PA 4.4 | 4.49 Vv Vou Output High Veo =4.5V Voltage low = -2 MA Veo =45V 2.4 | 3.9 V Voo Standby Comm'l 50 | 100 HA Ispi Current (CMOS) - (Notes 2 and 4) ind/Mil 75 | 150 pA Comm'l (Note 6) 16 | 35 7 10 | mA Active Current Comm' (CMOS) (No (Note 7) 28 | 50 7 10 | mA lect internal Memory ind Mil Block Selected) (Note. 6) 16 | 45 7 | 10 | ma (Notes 2 and 5) Ind/Mil (Note 7) 28 60 7 10 | mA Comm' (Note 6) 16 | 35 0 O | mA Active Current Comm'l 28 |} 50 0 0 | mA loce (CMOS) (EPROM | (Note 7) Block Selected) Ind/Mil (Notes 2 and5) | (Note 6) 16 | 45 Oo | 0 | ma Ind/Mit (Note 7) 28 | 60 0 QO | mA Comm (Note 6) 47 | 80 7 10 | mA Active Current Comm'l 59 95 7 10 mA lees | (CMOS) (SRAM | (Note 7) Block Selected Ind/Mil (Notes 2and5) _| (Note 6) 47 | 100 7 | 10 | mA Ind/Mil (Note 7) 59 | 115 7 10 | mA | Input Leakage Vin = 5.5 V 7 uu Current or GND 1 |;4+01) 1 pA I Output Leakage VouT =5.5V 1} _. LO Current or GND 10] +5 | 10 pA NOTES: 2. CMOS inputs: GND + 0.3 V or Vcc + 0.3V. 3. TTL inputs: Vy < 0.8 V, Vix > 2.0 V. 4. CSI/A19 is high and the part is in a power-down configuration mode. 5. Add 3.0 mA/MHz for AC power component (power = AC + DC). 6. Ten (10) PAD product terms active. (Add 380 LA per product term, typical, or 480 1A per product term maximum 7. Forty-one (41) PAD praduct terms active. May, 1993 135NAPC/PHILIPS SEMNICOND Philips Semiconductors Microcontroller Peripherals BLE D MM 6653924 0073910 20e MESIC3 Preliminary specification Field-programmable microcontroller peripheral PSD313 AC Characteristics -90 12 15 -20 . Symbol Parameter - - - CMiser=1) unit Min | Max | Min | Max | Min | Max| Min | Max| Add: Tt ALE or AS Pulse Width 20 30 40 50 ns T2 Address Set-up Time 12 15 ns T3 Address Hold Time 9 12 15 ns Leading Edge of Read 74 | to Data Active 0 0 0 0 0 ns T5 ALE Valid to Data Valid 100 130 160 200 10 ns T6 Address Valid to Data Valid 90 120 150 200 10 ns T7 | CSI Active to Data Valid 100 130 160 200 15 ns Leading Edge of Read T8 to Data Valid 32 38 55 60 0 ns T9 Read Data Hold Time 0 0 0 0 0 ns T10 Trailing Edge of Read to Data High-Z 32 32 35 40 0 ns T11 Trailing Edge of ALE or AS to Leading Edge of Write | 0 0 0 0 ns RO, E, PSEN, or DS T12 Pulse Width 40 45 60 75 0 ns T12A | WR Pulse Width 20 25 35 45 0 ns Trailing Edge of Write or T13 Read to Leading Edge 0 0 0 0 0 ns of ALE or AS Address Valid to Trailing 714 Edge of Write 30 120 150 200 0 ns CSI Active to Trailing Edge T15 of Write 100 130 160 200 0 ns T16 Write Data Set-up Time 20 25 30 40 ns T17 Write Data Hold Time 5 5 10 15 ns Port to Data Out Valid T18 Propagation Delay 30 30 35 45 0 ns T19 Port Input Hold Time 0 0 0 0 0 ns Trailing Edge of Write T20 | to Port Output Valid 40 40 50 60 0 ns T21 | ADior Control to CSOi 6 |25|6]|30| 6/35] 5 | 45 0 ns Valid ADi or Control to CSOi T22 Invalid 5 25 5 30 4 35 4 45 0 ns May, 1993 136NAPC/PHILIPS SEMICOND bLE D MM 66539924 0071911 149 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 A Characteristics (Cont.) -90 12 15 -20 CMiser =1 Symbol Parameter - - - - sr=1) Unit Min | Max | Min | Max | Min | Max | Min | Max Add: Track Mode Address Te3 Propagation Delay: 22 22 28 28 0 ns CSADOUT1 Already True | Track Mode Address | Propagation Delay: | T23A CSADOUT1 Becomes 33 33 50 50 0 ns True During ALE or AS | Track Mode Trailing Edge | T24 | of ALEor AS to Address 32 32 35 40 0 ns High-Z Track Mode Read T25 Propagation Delay 29 29 35 35 0 ns Track Mode Read T26 Hold Time 11 29 W 29 10 29 10 35 0 ns Track Mode Write Cycle, 127 Data Propagation Delay 20 20 30 30 0 ns Track Mode Write | T28 Cycle, Write to Data 8 30 8 30 7 40 7 55 0 ns | Propagation Delay | Hold Time of Port A T29 Valid During Write 2 2 2 2 0 ns CSOi Trailing Edge : T30 | CSI Active to CSOi Active | 9 | 40 | 9 | 45 | 9 | 50 | 8 | 60 0 ns | xl . nari CSI Inactive to CSOi T31 Inactive 9 40 9 45 9 50 8 60 0 ns Direct PAD Input as 32 Hold Time 10 10 12 15 0 ns 733 | R/W Active to Eor DS Start | 20 20 30 40 0 ns : 134 | Eor DS Endto RW 20 20 30 40 0 ns 735 | AS Inactive to E high 0 0 Oo 0 0 ns | Address to Leading | T36 Edge of Write 20 20 25 30 0 ns NOTES: 8. ADi = any address lino. 9. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port C (CS8-CS10). __ 10. Direct PAD input = any of the following direct PAD input lines: CSI/A19 as transparent A19, RD/E/DS, WR or RW, transparent PCO-PC2, ALE (or AS). 11. Control signals RD/E/DS or WR or R/W. May, 1993 137NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals bLE D MB 66539924 0071912 085 MBSICI Preliminary specification Field-programmable microcontroller peripheral PSD313 Figure 1. Timing of 8-Bit Multiplexed Address/DataBus, CRRWR = 0 CSVA19 as CSI Direct (12) PAD Input Multiplexed (13) Inputs A0/ADO- A7/AD7 Active High ALE Active Low ALE RD/E/DS as RD BHE/PSEN as PSEN WAWVpp or RW as WR Any of PAO-PA7 as I/O Pin Any of PBO-PB7 as /O Pin Any of PAO-PA7 Pins as Address Outputs See referenced notes on page 144. May, 1993 ADDRESS A READ CYCLE STABLE INPUT 6 ADDRESS A DATA VALID WRITE CYCLE 32 15 32 STABLE INPUT 14 14 ADDRESS B 3 ADDRESS BNAPC/PHILIPS SEMICOND bB1E D MM 66539e4 0071913 T11 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 | Figure 2. | Timing of 8-Bit Multiplexed Address/DataBus, CRRWR =1 READ CYCLE WRITE CYCLE 32 CSVA19 as CSI 15 32 H 42) PAD Input 2) STABLE INPUT STABLE INPUT 6 14 Multiplexed (13) Inputs 14 AO/ADO- AT/AD7 ADDRESS A DATA VALID ADDRESS B 9 3 Active High AS Active Low AS RD/E/DS as E RD/E/DS as DS WRWV pp or R/W as R/V Any of PAO-PA7 as V/O Pin Any of PBO-PB7 as I/O Pin Any of PAO-PA7 Pins as Address Outputs ADDRESS A ADDRESS B See referenced notes on page 144. May, 1993 139NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals bLE D MM 66539924 0071914 958 MESIC3 Preliminary specification Field-programmable microcontroller peripheral PSD313 Figure 3. Timing of 8-Bit Data, Non-Multiplexed Address/DataBus, CRRWR = 0 CSVA19 as CSI Direct (12) PAD Input A0/ADO- A15/AD15 as AO-A15 Multiptexed (13) Inputs PAO-PA7 Active High ALE Active Low ALE RDVE/DS as RD WR pp_or RW as WR Any of PBO-PB7 as V/O Pin READ CYCLE STABLE INPUT 6 STABLE INPUT See referenced notes on page 144. May, 1993 WRITE CYCLE 32 STABLE INPUT STABLE INPUT 32NAPC/PHILIPS SEMICOND BLE D MM 665394 0071915 494 MBSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Figure 4. Timing of 8-Bit Data, Non-Multiplexed Address/DataBus, CRRWR = 1 READ CYCLE WRITE CYCLE 32 CSI/A19 as CSI i 12) P AD heat. ) STABLE INPUT STABLE INPUT 6 14 AQ/ADO- A15/AD15 STABLE INPUT STABLE INPUT as AQ-A15 32 Multiplexed (13) Inputs 10 PAO-PA7 DATA VALID 9 Active High ALE Active Low ALE RD/E/DS as E RD/E/DS as DS WRWVpp or RW as R/W Any of | PBO-PB7 OUTPUT as VO Pin See referenced notes on page 144. May, 1993 141NAPC/PHILIPS SEMICOND BLE D MM 6653924 0071916 720 MESIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Figure 5. Chip-Select Output Timing 30 31 siaig ~ \ / as CSI Direct PAD ? INPUT STABLE x Input Multiplexed (8) PAD Inputs RXXXX 2. _ 3 _ ALE | - (Multiplexed TY Mode Only) > orALE \ "4 (Multiplexed \ | A Mode Only) 21 22 et > > soi (14-19) \ ff ey, See referenced notes on page 144. May, 1993 142NAPC/PHILIPS SEMICOND b1E D WM 6653924 0071917 bb? MBSICS Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Figure 6. Port A as ADO-AD7 Timing (Track Mode), CRRWR=0 READ CYCLE WRITE CYCLE Direct PAD Input STABLE INPUT STABLE INPUT (12,15) 2 Multiplexed PAD Inputs STABLE INPUT STABLE INPUT (16,18) 2 3 26 2 3 AO/ADO- A7/AD7 ADDRESS DATA VALID ADDRESS ALE or ALE RD/E/DS as RD g WAVrp RW as | PAO-PA7 ADR OUT DATA IN ADR OUT csoi (14,17} See referenced notes on page 144. May, 1993 143NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals Field-programmable microcontroller peripheral Preliminary specification PSD313 Figure 7. Port A as ADO-AD7 Timing (Track Mode), CRRWR = 1 Direct PAD Input (12,18) Multiplexed PAD Inputs (16,18) AQ/ADO- A7/AD7 AS or AS ROV/E/DS as E RD/E/DS as DS WAV oF RW as RW PAO-PA7 csal (14,17) READ CYCLE WRITE CYCLE STABLE INPUT STABLE INPUT STABLE INPUT STABLE INPUT 2 3 26 3 ADDRESS DATA VALID ADDRESS 24 DATA IN ADR OUT Notes for Timing Diagrams May, 1993 12. Direct PAD input = any of the following direct PAD input lines: CSV/A19 as transparent A19, RD/E, WR or R/W, transparent PCO-PC2, ALE in non-multiplexed modes. 13. Multiplexed inputs: any of the following inputs that are latched by the ALE (or AS): AO/ADO-A15/AD15, CSI/A19 as ALE dependent A19, ALE dependent PCO-PC2. 14. CSOi = any of the chip-select output signals coming through Port B (CS0-CS7) or through Port G (CS8-CS10). 15. CSADOUT1, which internally enables the address transfer to Port A, should be derived only from direct PAD input signals, otherwise the address propagation delay is slowed down. 16. CSADIN and CSADOUT2, which internally enable the data-in or data-out transfers, respectively, can be derived from any combination of direct PAD inputs and multiplexed PAD inputs. 17. The write operation signals are included in the GSOi expression. 18. Multiplexed PAD inputs: any of the following PAD inputs that are latched by the ALE (or AS) in the multiplexed modes: A11/AD11-A15/AD15, CSVA19 as ALE dependent A19, ALE dependent PCO-PC2. 19. GSOi product terms can include any of the PAD input signals except for reset and Csi. 144 b1E D MB 6653924 0071918 5T3 MBSIC3NAPC/PHILIPS SEMICOND Philips Semiconductors Microcontroller Peripherals b1E D MM 6653924 0071919 43T MBSIC3 Preliminary specification Field-programmable microcontroller peripheral PSD313 Pin Symbol Parameter Conditions | Typical?"| Max | Unit Capacitance : Cin Capacitance (for input pins only) Vin=OV 4 6 pF Court | Capacitance (for input/output pins) Vout=0V 8 12 pF Cypp | Capacitance (for WR/Vpp or R/W/V/pp) | Vpp=0V 18 25 pF NOTES: 20. This paramter is only sampled and is not 100% tested. 21. Typical values are for Ta = 25C and nominal supply voltages. Figure 8. AC Testing Input/Output a0V Waveform x , TEST POINT 1.5V ov Figure 9. 2.01 V AC Testing Load Circult 195.Q DEVICE UNDER TEST C= 30 pF L (INCLUDING mi= SCOPE ANDJIG = CAPACITANCE) Erasure and To clear all locations of their programmed sources at 2537 A, exposure to fluorescent Programming contents, expose the device to ultra-violet light and sunlight eventually erases the May, 1993 light source. A dosage of 15 W second/cm? is required. This dosage can be obtained with exposure to a wavelength of 2537 A and intensity of 12000 pW/cm? for 15 to 20 minutes. The device should be about 1 inch from the source, and all filters should be rernoved from the UV light source prior to erasure. The PSD3XX and similar devices will erase with light sources having wavelengths shorter than 4000 A. Although the erasure times will be much longer than with UV 145 device. For maximum system reliability, these sources should be avoided. If used in such an environment, the package windows should be covered by an opaque substance. Upon delivery, or after each erasure, the PSD3XX device has all bits in the PAD and EPROM in the 1 or high state. The configuration bits are in the O or low state. The code, configuration, and PAD MAP data are loaded through the procedure of programming.NAPC/PHILIPS SEMICOND blE D MM 6653924 0071920 151 MMSIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Pin 44-Pin Assignments Pin Name PLOC/CLEC Package PSEN 1 WRVpp or RW 2 RESET 3 PB7 4 PB6 5 PBS 6 PB4 7 PB3 8 PB2 9 PB1 40 PBO 1 GND 12 ALE or AS 13 PA7 14 PAG 15 PAS 16 PA4 17 PA3 18 PA2 19 PAI 20 PAO 21 RD/E/DS 22 ADO/AO 23 AD1/A1 24 AD2/A2 25 AD3/A3 26 AD4/A4 27 ADS5/A5 28 AD6/AG 29 AD7/A7 30 AS 31 Ag 32 A10 33 GND 34 Al1 35 Al2 36 A13 37 Al4 38 A15 39 PCO 40 PC1 41 PC2 42 A19/CSI 43 Vee 44 May, 1993 146NAPC/PHILIPS SEMICOND b1E D MM 6653924 0071521 098 MESIC3 Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Package lz Information - a gure 10. een @ BE298 Drawing L4 eee ee ess 44 Pin Ceramic RRR Leaded Chip foeeg tt PhP i LEGELE LE LE oo} Carrler (CLEC) res oes oe ata with Window pe2 9 fi i 37 A13 (Package Type L) PBI 10 (7 Tp 36 at2 PBO 11 [f"7? SU 95 att GND 12 (77: 7] 34 GND ALE or AS 13 (777! C7 33 ato PAT 14 7) COM] 32. a9 PAs 15 (173 C771 31 a8 PAS 16 [[-: 7] 30 AD7/A7 PA4 17 73 CT) 20 ADG/AG g2 328228233 (TOP VIEW) 8 g28838 Figure 11. Drawing J2 g 44 Pin Plastic H i Leaded Chip bSz Sarre Carrier (PLCC) SEHR SERRE with Window (Package Type J) Conon Too oS ppa 7 Wo: 0 39 A15 PBs 8 Or: ip 39 Ai4 pp2 9 (3 ETD 37 A13 Pei 10 7D 36 A12 PBo 11 D735 aw GND 12 (3 iy] 34 GND ALE or aS 13 (7! ENT] 33 A10 Pa7 14 0 iT 32 ao Pas 15 O73 HD 31 As Pas 16 [D-3 iD 30 AD7/A7 Pad 17 EG HU 29 ADe/AG anrereowoorn sz (TOP VIEW) ge FFG 825533 @ qadateadte May, 1993 147NAPC/PHILIPS SEMICOND BLE D MM 66539924 0071922 T24 MESICI Philips Semiconductors Microcontroller Peripherals Preliminary specification Field-programmable microcontroller peripheral PSD313 Ordering Operati Spd.| Package Package| ,Peraung | Manufacturi Information Part Number (ns) Te. Brawing Teperatare Procedure ge PSD313-90 A 90 | 44-pin PLCC J2 Commercial Standard PSD313-90 KA 90 | 44-pin CLCC L4 Commercial Standard PSD313-12 A 120 | 44-pin PLCC J2 Commercial Standard PSD313-12 KA | 120 | 44-pin CLCC L4 Commercial Standard PSD313-15 A 150 | 44-pin PLCC J2 Commercial Standard PSD313-151A 150 | 44-pin PLCC J2 Industrial Standard PSD313-15 KA | 150 | 44-pin CLCC L4 Commercial Standard PSD313-151 KA | 150 | 44-pin CLCC L4 Industrial Standard PSD313-20 A 200 | 44-pin PLCC J2 Commercial Standard PSD313-201 A 200 | 44-pin PLCC J2 Industrial Standard PSD313-20 KA | 200 | 44-pin CLCC L4 Commercial Standard PSD313-201KA | 200 | 44-pin CLCC L4 Industrial Standard May, 1993 148