To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
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Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
* Typical parameter indicates the value for the center
of distribution, and is not 100% tested.
1
DESCRIPTION
The M5M5W816 is a family of low voltage 8-Mbit static RAMs
organized as 524288-words by 16-bit, fabricated by Mitsubishi's
high-performance 0.18µm CMOS technology.
The M5M5W816 is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
M5M5W816WG is packaged in a CSP (chip scale package),
with the outline of 7.5mm x 8.5mm, ball matrix of 6 x 8 (48ball)
and ball pitch of 0.75mm. It gives the best solution for a
compaction of mounting area as well as flexibility of wiring pattern
of printed circuit boards.
FEATURES
- Single 2.7~3.6V power supply
- Small stand-by current: 0.1µA (2V, typ.)
- No clocks, No refresh
- Data retention supply voltage =2.0V
- All inputs and outputs are TTL compatible.
- Easy memory expansion by S1#, S2, BC1# and BC2#
- Common Data I/O
- Three-state outputs: OR-tie capability
- OE prevents data contention in the I/O bus
- Process technology: 0.18µm CMOS
- Package: 48ball 7.5mm x 8.5mm CSP
PIN CONFIGURATION
A0 ~ A18
DQ1 ~ DQ16
S1#
W#
OE#
BC1#
Address input
Data input / output
Chip select input 1
Write control input
Output enable input
Lower Byte (DQ1 ~ 8)
Pin Function
Vcc
GND Power supply
Ground supply
BC2# Upper Byte (DQ9 ~ 16)
S2 Chip select input 2
(TOP VIEW)
30mA
(10MHz)
5mA
(1MHz)
Version,
Operating
temperature Part name Power
Supply Access time
max.
Stand-by current
Ratings (max.@ Vcc=3.6V)
Active
current
*(3.0V, typ.)
Icc1
70°C 85°C25°C
85ns
2.7 ~ 3.6V
I-version
-40 ~ +85°C M5M5W816WG -70HI
* Typical(3.0V) 40°C
25°C 40°C
408.0 205.01.00.5
NC : No Connection
1 2 3 4 5 6
A
B
C
D
E
F
G
DQ3
A7
DQ1
S2
VCC
GND
DQ6
A2
S1#
DQ2
DQ4
DQ5
DQ7
A1
A4
A6
A5
A17
A16
A15
A0
A3
A14
OE#
BC2#
DQ15
DQ13
DQ12
DQ10
BC1#
DQ16
DQ14
GND
VCC
DQ11
DQ8
W#
A13
A12
N.C.
DQ9
N.C.
A11
A10
A9
A8
HA18
NC or
GND
Outline : 48F7Q
(µA)
M5M5W816WG -85HI
55nsM5M5W816WG -55HI 70ns
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
2
FUNCTION
The M5M5W816WG is organized as 524288-words by 16-bit.
These devices operate on a single +2.7~3.6V power supply,
and are directly TTL compatible to both input and output. Its
fully static circuit needs no clocks and no refresh, and
makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1# , BC2# , S1#, S2 , W# and
OE#. Each mode is summarized in the function table.
A write operation is executed whenever the low level W#
overlaps with the low level BC1# and/or BC2# and the low
level S1# and the high level S2. The address(A0~A18) must
be set up before the write cycle and must be stable during
the entire cycle.
A read operation is executed by setting W# at a high level
and OE# at a low level while BC1# and/or BC2# and S1# and
S2 are in an active state(S1#=L,S2=H).
When setting BC1# at the high level and other pins are in
an active stage , upper-byte are in a selectable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2# at a
high level and other pins are in an active stage, lower-byte
are in a selectable mode and upper-byte are in a non-
selectable mode.
When setting BC1# and BC2# at a high level or S1# at a high
level or S2 at a low level, the chips are in a non-selectable
mode in which both reading and writing are disabled. In this
mode, the output stage is in a high-impedance state, allowing
OR-tie with other chips and memory expansion by BC1#,
BC2# and S1#, S2.
The power supply current is reduced as low as 0.1µA(25°C,
typical), and the memory data can be held at +2.0V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
BLOCK DIAGRAM
MEMORY ARRAY
524288 WORDS
x 16 BITS
CLOCK
GENERATOR
A0
A1
A17
A18
S2
BC1
#
BC2
#
W#
OE
#
DQ
8
DQ
1
DQ
16
DQ
9
-
Vcc
GND
S1
#
FUNCTION TABLE
Mode
S2
W#
HX X High-Z
BC1#BC2# OE# DQ1~8
X X
Non selection
DQ9~16 Icc
High-Z Standby
High-Z High-Z
HXLL HDin High-Z Active
H HLHRead High-ZDout ActiveL
H HLActive
H H LActive
HL
High-Z
High-Z ActiveHL
H
HHigh-Z
HLDoutHL L Read Dout Active
HLDinLL XWrite Din Active
HHigh-Z
H H High-Z High-Z
Non selection
XH H X X Standby
Write
H H L L Write Din ActiveX
HLHRead High-Z ActiveLDoutHHigh-Z
S1
#
H
L
L
L
L
L
L
L
X
L
L
LX X High-Z
X X
Non selection
High-Z Standby
LLX X High-Z
X X Non selection High-Z Standby
H
(note1) "H" and "L" in this table mean VIH and VIL, respectively .
(note2) "X" in this table should be "H" or "L".
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
3
ABSOLUTE MAXIMUM RATINGS
pF
10
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
CO
Symbol Parameter Limits
Conditions Units
µA
mA
mA
V
Icc1
Icc2
Icc4
VIH
VIL
IO
Icc3
VOH IOH= -0.5mA
VOL IOL=2mA
IIVI =0 ~ Vcc
BC1# and BC2# =VIH or S1# =VIH or S2=VIL or OE# =VIH, VI/O=0 ~ Vcc
Vcc+0.2V
0.6
2.2
-0.2 *
2.4
2
0.4
±1
5030 ±1
15
MaxTypMin
DC ELECTRICAL CHARACTERISTICS
f= 10MHz
f= 1MHz
-
-
-
-
-
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating
temperature
Storage temperature
V
mW
Conditions
Ta= 700
- 65 ~ +150
Ratings
Vcc
VI
VO
Pd
Ta
Tstg
-0.3* ~ +4.6
-0.3* ~ Vcc + 0.3 (max. 4.6V)
0 ~ Vcc
Symbol Parameter Units
- 40 ~ +85
With respect to GND
f= 10MHz
f= 1MHz
55030 155
-
With respect to GND
With respect to GND
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input leakage current
Output leakage current
Active supply current
( AC,MOS level )
( AC,TTL level )
Active supply current
Stand by supply current
( AC,MOS level )
( AC,TTL level )
Stand by supply current
Other inputs= 0 ~ Vcc
Note 1: Direction for current flowing into IC is indicated as positive (no mark).
Note 2: Typical parameter indicates the value for the center of distribution at 3.0V, and is not 100% tested.
CAPACITANCE
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Symbol Parameter Conditions Limits Max
Typ
Min Units
Input capacitance
Output capacitance
BC1# and BC2# < 0.2V, S1# < 0.2V, S2 > Vcc-0.2V
other inputs < 0.2V or > Vcc-0.2V
Output - open (duty 100%)
BC1# and BC2#=VIL , S1#=VIL ,S2=VIH
other pins =VIH or VIL
Output - open (duty 100%)
BC1# and BC2# =VIH or S1# =VIH or S2 =VIL
* -1.0V in case of AC (Pulse width < 30ns)
* -3.0V in case of AC (Pulse width < 30ns)
10
°C
°C
µA
20
~ +70°C
~ +40°C
0.5
-
-
-
~ +85°C
~ +25°C -
1.0
5
8
-
-
40
(1)
S1# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 < 0.2V,
(2)
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
(3)
other inputs = 0 ~ Vcc
25°C
S2 > Vcc - 0.2V,
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
AC ELECTRICAL CHARACTERISTICS
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
Input rise time and fall time
Reference level
Output loads
2.7~3.6V
VIH=2.4V, VIL=0.4V
Transition is measured ±200mV from
steady state voltage.(for ten,tdis)
5ns
Fig.1,CL=30pF
CL=5pF (for ten,tdis)
(1) TEST CONDITIONS
Supply voltage
Input pulse
1TTL
CL
DQ
Fig.1 Output load
Including scope and
jig capacitance
tCR ns
ta(S1)
ta(OE)
tdis(S1)
tdis(OE)
ten(S1)
ten(OE)
tV(A)
ta(A) ns
ns
ns
ns
ns
ns
ns
ns
ta(BC1)
ta(BC2)
tdis(BC1)
tdis(BC2)
ten(BC1)
ten(BC2)
ns
ns
ns
ns
ns
ns
85
10
45
85
85
85
85
30
30
30
30
5
5
5
10
ta(S2) ns
85
ten(S2) ns
10
tdis(S2) ns
30
4
tsu(A-WH)
tCW
tw(W)
tsu(A)
tsu(S1)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(BC1)
tsu(BC2)
30
30
tsu(S2) ns
85
60
0
70
70
70
70
45
0
0
70
5
5
Symbol Parameter
Read cycle time
Limits
Address access time
Chip select 1 access time
Chip select 2 access time
Byte control 1 access time
Byte control 2 access time
Output enable access time
Output disable time after S2 low
Output disable time after S1# high
Output disable time after BC1# high
Max
Min Units
(2) READ CYCLE
Output disable time after BC2# high
Output disable time after OE# high
Output enable time after S1# low
Output enable time after S2 high
Output enable time after BC1# low
Output enable time after BC2# low
Output enable time after OE# low
Data valid time after address
(3) WRITE CYCLE
Units
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to W#
Byte control 1 setup time
Byte control 2 setup time
Chip select 1 setup time
Chip select 2 setup time
Data setup time
Data hold time
Write recovery time
Output disable time from W# low
Output disable time from OE# high
Output enable time from W# high
Output enable time from OE# low
Symbol Parameter
VOH=VOL=1.5V
85HI
70
10
35
70
70
70
70
25
25
25
25
5
5
5
10
70
10
25
Max
Min 70HI
Limits
Max
Min 85HI
Max
Min 70HI
25
25
70
55
0
65
65
65
65
35
0
0
65
5
5
55
10
30
55
55
55
55
20
20
20
20
5
5
5
10
55
10
20
Max
Min 55HI
50
45
0
50
50
50
0
020
5
50
5
30
Max
Min 55HI
20
55
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
S2
(Note3) (Note3)
tsu (S2)
ten (W)
5
ta(A)
t
a(BC1)
tv (A)
tdis (BC1) or tdis (BC1)
ta (OE)
t
en (OE) tdis (OE)
tCR
th (D)tsu (D)
DQ1~16
tsu (BC1) or tsu(BC2)
ten
(OE)
tdis(OE)
tw
(W)
trec (W)
tsu
(A)
tdis (W)
tCW
t
en
(S1)
W# = "H" level
A
0~18
DQ1~16
A0~18
OE#
OE#
W#
(4)TIMING DIAGRAMS
Read cycle
(Note3)
(Note3)
(Note3)
(Note3)
VALID DATA
Write cycle ( W# control mode )
DATA IN
STABLE
(Note3) (Note3)
ta(S1)
tdis (S1)
S1#
(Note3) (Note3)
BC1#,BC2#
t
a(BC2)
or
ten (BC2)
ten (BC1)
t
su (A-WH)
S1#
(Note3) (Note3)
tsu (S1)
BC1#,BC2#
ta(S2)
tdis (S2)
S2
(Note3) (Note3)
t
en
(S2)
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
6
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S1# low, S2 high overlaps BC1# and/or BC2# low and W# low.
Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.
Note 5: When the falling edge of W# is simultaneously or prior to the falling edge of BC1# and/or BC2# or the falling edge of S1#
th (D)tsu (D)
DQ1~16
tsu (BC1) or
tsu (BC2) trec (W)
tsu
(A)
tCW
A
0~18
W#
Write cycle (BC# control mode)
DATA IN
STABLE
(Note3)(Note3)
(Note4)
(Note5)
(Note3)(Note3)
S1#
or rising edge of S2, the outputs are maintained in the high impedance state.
BC1#,BC2#
(Note3)(Note3)
S2
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
th (D)tsu (D)
DQ1~16
tsu (S1) trec (W)
tsu
(A)
tCW
A
0~18
W#
S1#
Write cycle (S1# control mode)
DATA IN
STABLE
(Note3)
(Note3)
(Note4)
(Note5)
(Note3)
(Note3)
BC1#,BC2#
(Note3)
(Note3)
S2
th (D)tsu (D)
DQ1~16
tsu (S2) trec (W)
tsu
(A)
tCW
A
0~18
W#
S1#
Write cycle (S2 control mode)
DATA IN
STABLE
(Note3)
(Note3)
(Note4)
(Note5)
(Note3)
(Note3)
BC1#,BC2#
(Note3)
(Note3)
S2
7
M5M5W816WG - 55HI, 70HI, 85HI
2002.04.18 Ver. 6.0
8388608
-BIT (524288-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
8
tsu (PD)
trec (PD) ns
ms
2.2V
tsu (PD) 2.7V2.7Vtrec (PD)
BC1# , BC2# > Vcc-0.2V
Vcc
V
2.0
Vcc (PD)
VI (S1)
Icc (PD)
2.2
BC1#
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
Power down supply voltage
Chip select input S1#
Power down
supply current
(2) TIMING REQUIREMENTS
Symbol Parameter Test conditions Limits
Min
Typ
Max Units
Power down set up time
Power down recovery time
(3) TIMING DIAGRAM
BC# control mode On the BC# control mode, the level of S1# and S2 must be fixed at S1#, S2 > Vcc-0.2V or S2 < 0.2V.
VI (BC)
Byte control input BC1# &
BC2#
V
BC2#
tsu (PD) 2.7V2.7Vtrec (PD)
Vcc
S1#
S1# control mode On the S1# control mode, the level of S2 must be fixed at S2 > Vcc-0.2V or S2 < 0.2V.
S1# > Vcc-0.2V
0
5
VI (S2) Chip select input S2 0.2
0.2V tsu (PD)
2.7V2.7Vtrec (PD)
Vcc
S2
S2 control mode
S2 < 0.2V
µA
15
~ +70°C
~ +40°C
0.1
-
-
-
~ +85°C
~ +25°C -0.2 1.5
3
-
-30
(1)
S1# > Vcc - 0.2V,
other inputs = 0 ~ Vcc
S2 < 0.2V,
(2)
other inputs = 0 ~ Vcc
BC1# and BC2# > Vcc - 0.2V
S1# < 0.2V, S2 > Vcc - 0.2V
(3)
other inputs = 0 ~ Vcc
Vcc=2.0V
2.2V
2.2V 2.2V
2.2V < Vcc(PD)
2.0V < Vcc(PD) < 2.2V Vcc(PD)
2.2 Vcc(PD) V
0.2V
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution, and is not 100% tested.
2.2V < Vcc(PD)
2.0V < Vcc(PD) < 2.2V
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