Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop REJ03D0277–0200Z
(Previous ADE-205-3 61 (Z))
Rev.2.00
Jul.16.2004
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse a nd is not directly related to the transition time of the positive-going pulse. After the
Clock Pulse input thre shold voltage has been passed, the Data input is locked o ut and i nformation present will not b e
transferred to the outputs until the next rising edge of the Clock Pulse input.
Features
Asynchronous Inputs:
Low input to SD (Set) sets Q to High level
Low input to CD (Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneou s Low on CD and SD makes both Q and Q High
• Outputs Source/Sink 24 mA
• Ordering Information
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity)
HD74AC74P DIP-14 pin DP-14, -14AV P —
HD74AC74FPEL SOP-14 pin (JEITA) FP-14DAV FP EL (2,000 pcs/reel)
HD74AC74RPEL SOP-14 pin (JEDEC) FP-14DNV RP EL (2,500 pcs/reel)
HD74AC74TELL TSSOP-14 pin TTP-14DV T ELL (2,000 pcs/reel)
Notes: 1. Please consult the sales office for the above package availability.
2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of
the package code.
Pin Arrangement
1
2
3
4
5
6
7
CD1
D1
CP1
SD1
Q1
Q1
GND
VCC
CD2
D2
CP2
SD2
Q2
Q2
14
13
12
11
10
9
8
CP1
CP2
SD1
CD2 SD2
CD1
D1
D2
Q1
Q2
(Top view)
Q2
Q1
HD74AC74
Rev.2.00, Jul.16.2004, page 2 of 7
Logic Symbol
D
1
Q
1
Q
1
CP
1
C
D1
S
D1
S
D2
D
2
Q
2
Q
2
CP
2
C
D2
Pin Names
D1, D2Data Inputs
CP1, CP2Clock Pulse Inputs
CD1, CD2 Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q1, Q2, Q 2 Outputs
Truth Table (Each Half)
Inputs Outputs
S
SS
SDC
CC
CDCP D Q Q
QQ
Q
LHXXHL
HLXXLH
LLXXHH
HH HHL
HH LLH
HHLXQ
0Q0
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Clock Transition
Q0 (Q0) : Previous Q (Q) before Low-to-High Transition of Clock
Logic Diagram
SD
CD
D
Q
Q
CP
Please note that this diagram is provised only for the understanding of logic operations and should not be
used to estimate propagation delays.
HD74AC74
Rev.2.00, Jul.16.2004, page 3 of 7
Absolute Maximum Ratings
Item Symbol Ratings Unit Condition
Supply voltage VCC –0.5 to 7 V
–20 mA VI = –0.5VDC input diode current IIK 20 mA VI = Vcc+0.5V
DC input voltage VI–0.5 to Vcc+0.5 V
–50 mA VO = –0.5VDC output diode current IOK 50 mA VO = Vcc+0.5V
DC output voltage VO–0.5 to Vcc+0.5 V
DC output source or sink current IO±50 mA
DC VCC or ground current per output pin ICC, IGND ±50 mA
Storage temperature Tstg –65 to +150 °C
Recommended Operating Conditions
Item Symbol Ratings Unit Condition
Supply voltage VCC 2 to 6 V
Input and output voltage VI, VO0 to VCC V
Operating temperature Ta –40 to +85 °CVCC = 3.0V
VCC = 4.5 V
Input rise and fall time
(except Schmitt inputs)
VIN 30% to 70% VCC
tr, tf 8 ns/V
VCC = 5.5 V
DC Characteristics
Ta = 25°
°°
°C Ta = –40 to
+85°
°°
°C
Item Sym-
bol Vcc
(V) min. typ. max. min. max.
Unit Condition
3.0 2.1 1.5 — 2.1 —
4.5 3.15 2.25 — 3.15 —
VIH
5.5 3.85 2.75 — 3.85 —
VOUT = 0.1 V or VCC –0.1 V
3.0 — 1.50 0.9 — 0.9
4.5 — 2.25 1.35 — 1.35
Input Voltage
VIL
5.5 — 2.75 1.65 — 1.65
V
VOUT = 0.1 V or VCC –0.1 V
3.0 2.9 2.99 — 2.9 —
4.5 4.4 4.49 — 4.4 —
5.5 5.4 5.49 — 5.4 —
VIN = VIL or VIH
IOUT = –50 µA
3.0 2.58 — — 2.48 — IOH = –12 mA
4.5 3.94 — — 3.80 — IOH = –24 mA
VOH
5.5 4.94 — — 4.80 —
VIN = VIL or VIH
IOH = –24 mA
3.0 — 0.002 0.1 — 0.1
4.5 — 0.001 0.1 — 0.1
5.5 — 0.001 0.1 — 0.1
VIN = VIL or VIH
IOUT = 50 µA
3.0 — — 0.32 — 0.37 IOL = 12 mA
4.5 — — 0.32 — 0.37 IOL = 24 mA
Output voltage
VOL
5.5 — — 0.32 — 0.37
V
VIN = VIL or VIH
IOL = 24 mA
Input leakage
current IIN 5.5 — — ±0.1 — ±1.0 µAV
IN = VCC or GND
IOLD 5.5———86—mAV
OLD = 1.1 V
Dynamic outp ut
current*IOHD 5.5 — — — –75 — mA VOHD = 3.85 V
Quiescent su pply
current ICC 5.5 — — 4.0 — 40 µAV
IN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
HD74AC74
Rev.2.00, Jul.16.2004, page 4 of 7
AC Characteristics
Ta = +25°C
CL = 50 pF Ta = –40°C to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Min Typ Max Min Max Unit
Maximum clock fmax 3.3 100 125 — 95 — MHz
frequency 5.0 140 160 — 125 —
Propagation delay tPLH 3.3 1.0 8.0 12.0 1.0 13.0 ns
CDn or SDn to Qn or Qn5.0 1.0 6.0 9.0 1.0 10.0
Propagation delay tPHL 3.3 1.0 10.5 12.0 1.0 13.5 ns
CDn or SDn to Qn or Qn5.0 1.0 8.0 9.5 1.0 10.5
Propagation delay tPLH 3.3 1.0 8.0 13.5 1.0 16.0 ns
CPn to Qn or Qn5.0 1.0 6.0 10.0 1.0 10.5
Propagation delay tPHL 3.3 1.0 8.0 14.0 1.0 14.5 ns
CPn to Qn or Qn5.0 1.0 6.0 10.0 1.0 10.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements
Ta = +25°C
CL = 50 pF
Ta = –40°C
to +85°C
CL = 50 pF
Item Symbol VCC (V)*1Ty p Guaranteed Minimum Unit
Set-up time, HIGH or LOW tsu 3.3 1.5 4.0 4.5 ns
Dn to CPn5.0 1.0 3.0 3.0
Hold time, HIGH or LOW th3.3 –2.0 0 0 ns
Dn to CPn5.0 –1.5 0 0
CPn or CDn or SDn tw3.3 3.0 5.5 7.0 ns
Pulse width 5.0 2.5 4.5 5.0
Recovery time trec 3.3 –2.5 0 0 ns
CDn or SDn to CP 5.0 –2.0 0 0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Capacitance
Item Symbol Typ Unit Condition
Input capacitan ce CIN 4.5 pF VCC = 5.5 V
Power dissipation capacitance CPD 35.0 pF VCC = 5.0 V
HD74AC74
Rev.2.00, Jul.16.2004, page 5 of 7
Package Dime nsions
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-14
Conforms
Conforms
0.97 g
As of January, 2003
Unit: mm
7.62
0.25
0˚ – 15˚
19.20
20.32 Max
1
814
7
1.30
2.54 ± 0.25 0.48 ± 0.10
6.30
7.40 Max
0.51 Min
2.54 Min 5.06 Max
+ 0.10
– 0.05
2.39 Max
Package Code
JEDEC
JEITA
Mass
(reference value)
DP-14AV
Conforms
Conforms
0.97 g
Unit: mm
7.62
*0.25 ± 0.06
0˚ – 15˚
19.20
20.32 Max
1
814
7
1.30
2.54 ± 0.25
*NI/Pd/AU Plating
*0.48 ± 0.08
6.30
7.40 Max
0.51 Min
2.54 Min 5.06 Max
2.39 Max
HD74AC74
Rev.2.00, Jul.16.2004, page 6 of 7
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-14DAV
—
Conforms
0.23 g
*Ni/Pd/Au plating
*0.20 ± 0.05
*0.40 ± 0.06
0.70 ± 0.20
0.12
0.15
0˚ – 8˚
M
0.10 ± 0.10
2.20 Max
5.5
10.06
1.42 Max
14 8
17
10.5 Max
+ 0.20
– 0.30
7.80
1.15
1.27
As of January, 2003
Unit: mm
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-14DNV
Conforms
Conforms
0.13 g
0
˚
– 8
˚
1.27
14 8
17
0.15
0.25
M
1.75 Max 3.95
*0.20 ± 0.05
8.65
9.05 Max
*0.40 ± 0.06
0.14
+ 0.11
– 0.04
0.635 Max 6.10
+ 0.10
– 0.30
0.60
+ 0.67
– 0.20
1.08
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
HD74AC74
Rev.2.00, Jul.16.2004, page 7 of 7
Package Code
JEDEC
JEITA
Mass
(reference value)
TTP-14DV
—
—
0.05 g
*Ni/Pd/Au plating
0.50 ± 0.10
0˚ – 8˚
*0.15 ± 0.05
6.40 ± 0.20
0.10
1.10 Max
0.13 M
0.65
17
14 8
4.40
5.00
5.30 Max
0.83 Max
*0.20 ± 0.05
0.07+0.03
–0.04
1.0
As of January, 2003
Unit: mm
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