W681360RG TR - Nuvoton Technology

- 1 -

W681360

3V SINGLE-CHANNEL

13-BIT LINEAR

VOICE-BAND CODEC

Data Sheet

Revision A.4

W681360

Publication Release Date: January 2009

- 2 - Revision A.4

1. GENERAL DESCRIPTION

The W681360 is a general-purpose single channel 13–bit linear PCM CODEC with 2s complement

data format. It operates from a single +3V power supply and is available in 20-pin SOG(SOP), SSOP

and TSSOP package options. The primary function of the device is the digitization and reconstruction

of voice signals, including the band limiting and smoothing required for PCM systems. The W681360

performance is specified over the industrial temperature range of –40°C to +85°C.

The W681360 includes an on-chip precision voltage reference. The analog section is fully differential,

reducing noise and improving the power supply rejection ratio. The VAG reference pin allows for

decoupling of the internal circuitry that generates the reference voltage to the VSS power supply ground,

minimizing clock noise on the analog circuitry when external analog signals are referenced to VSS.

The data transfer protocol supports both long-frame and short-frame, synchronous and asynchronous

communications for PCM applications. The W681360 accepts eight master clock rates between

256kHz and 4.800MHz, and an on-chip pre-scaler automatically determines the division ratio for the

required internal clock. An additional on-chip power amplifier is capable of driving 300Ω loads

differentially up to a level of 3.544V peak-to-peak.

For fast evaluation a development kit (W681360DK) is available.

For fast prototyping purposes a low-cost evaluation board (W681360ES) is also available.

2. FEATURES

• Single +3V power supply (2.7V to 5.25V)

• Typical power dissipation: 9.8mW

Standby power dissipation: 3µW

Power-Down dissipation: 0.09µW

• Fully-differential analog circuit design for

low noise

• 13-bit linear A/D & D/A conversions with 2s

complement data format

• CODEC A/D and D/A filtering compliant

with ITU G.712

• Eight master clock rates of 256kHz to

4.800 MHz

• 256KHz – 4.8MHz bit clock rates on the

serial PCM port

• On-chip precision reference of 0.886 V for

a -5 dBm TLP at 600 Ω (436mVRMS)

• Programmable receive gain: 0 to –21dB in

3dB steps

• Industrial temp. range (–40°C to +85°C)

• 20-pin SOG (SOP), SSOP and TSSOP as

well as a QFN-32L package

• Pb-Free / RoHS package options available

Applications

• VoIP, Voice over Networks equipment

• Digital telephone and communication

systems

• Wireless Voice devices

• DECT/Digital Cordless phones

• Broadband Access Equipment

• Bluetooth Headsets

• Fiber-to-curb equipment

• Enterprise phones

• Digital Voice Recorders

W681360

Publication Release Date: January 2009

- 3 - Revision A.4

3. BLOCK DIAGRAM

256 kHz

512 kHz

1536 kHz

1544 kHz

2048 kHz

2560 kHz

4096 kHz

4800 kHz

MCLK

256 kHz

8 kHz

Pre-scaler

VDD

VSS

Power Conditioning

Voltage reference VAG

PUI

G.712 CODEC

PAO+

PAO-

PAI

RO-

AI+

AI-

Transmit

PCM

Interface

Receive

PCM

Interface

FST

BCLKT

PCMT

FSR

BCLKR

PCMR

VAGREF

256 kHz

512 kHz

1536 kHz

1544 kHz

2048 kHz

2560 kHz

4096 kHz

4800 kHz

MCLK

256 kHz

8 kHz

Pre-scaler

VDD

VSS

Power Conditioning

Voltage reference VAG

PUI

G.712 CODEC

PAO+

PAO-

PAI

RO-

AI+

AI-

Transmit

PCM

Interface

Receive

PCM

Interface

FST

BCLKT

PCMT

FSR

BCLKR

PCMR

VAGREF

W681360

Publication Release Date: January 2009

- 4 - Revision A.4

4. TABLE OF CONTENTS

1. GENERAL DESCRIPTION .................................................................................................................. 2

2. FEATURES ......................................................................................................................................... 2

3. BLOCK DIAGRAM ............................................................................................................................... 3

4. TABLE OF CONTENTS ...................................................................................................................... 4

5. PIN CONFIGURATION ....................................................................................................................... 6

6. PIN DESCRIPTION ............................................................................................................................. 7

7. FUNCTIONAL DESCRIPTION ............................................................................................................ 9

7.1. Transmit Path................................................................................................................................ 9

7.1.1 Input Operational Amplifier Gain ........................................................................................... 10

7.2. Receive Path............................................................................................................................... 11

7.2.1. Receive Gain Adjust Mode ................................................................................................... 12

7.3. POWER MANAGEMENT ........................................................................................................... 12

7.3.1. Analog and Digital Supply .................................................................................................... 12

7.3.2. Analog Ground Reference Bypass ...................................................................................... 12

7.3.3. Analog Ground Reference Voltage Output .......................................................................... 12

7.4. PCM INTERFACE ...................................................................................................................... 13

7.4.1. Long frame sync ................................................................................................................... 13

7.4.2. Short frame sync .................................................................................................................. 13

7.4.3. Special 16-bit Receive Modes.............................................................................................. 14

7.4.3.1. Sign-Extended Mode Timing ............................................................................................. 14

7.4.3.2. Receive Gain Adjust Mode Timing .................................................................................... 15

7.4.4. System Timing ..................................................................................................................... 15

7.5. On-Chip Power Amplifier ............................................................................................................ 15

8. TIMING DIAGRAMS .......................................................................................................................... 16

9. ABSOLUTE MAXIMUM RATINGS .................................................................................................... 21

9.1. Absolute Maximum Ratings ........................................................................................................ 21

9.2. Operating Conditions .................................................................................................................. 21

10. ELECTRICAL CHARACTERISTICS ............................................................................................... 22

10.1. General Parameters ................................................................................................................. 22

10.2. Analog Signal Level and Gain Parameters ............................................................................... 23

10.3. Analog Distortion and Noise Parameters ................................................................................. 24

W681360

Publication Release Date: January 2009

- 5 - Revision A.4

10.4. Analog Input and Output Amplifier Parameters ........................................................................ 25

10.5.1. PCM Codes for Zero and Full Scale .................................................................................. 27

10.5.2. PCM Codes for 1kHz Digital Milliwatt ................................................................................ 27

11. TYPICAL APPLICATION CIRCUIT ................................................................................................. 28

12. PACKAGE DRAWING AND DIMENSIONS .................................................................................... 29

12.1. 20L SOG (SOP)-300mil ............................................................................................................ 29

12.2. 20L SSOP-209 mil .................................................................................................................... 30

12.3. 20L TSSOP - 4.4X6.5mm ......................................................................................................... 31

12.3. QFN-32L ................................................................................................................................... 32

13. ORDERING INFORMATION ........................................................................................................... 33

14. VERSION HISTORY ....................................................................................................................... 34

W681360

Publication Release Date: January 2009

- 6 - Revision A.4

5. PIN CONFIGURATION

W681360

SINGLE

CHANNEL

CODEC

SOG, SSOP, TSS OP

VREF

RO-

PAI

PAO-

PAO+

VDD

FSR

PCMR

BCLKR

PUI

VAG

AI+

AI-

VSS

FST

PCMT

BCLKT

MCLK

W681360

SINGLE

CHANNEL

CODEC

SOG, SSOP, TSS OP

VREF

RO-

PAI

PAO-

PAO+

VDD

FSR

PCMR

BCLKR

PUI

VAG

AI+

AI-

VSS

FST

PCMT

BCLKT

MCLK

10 11 12 13 14 15 16

26272829303132

RO-

PAI

PAO-

PAO+

FSR

PCMR

BCLKR

AI-

FST

PCMT

PUI

MCLK

BCLKT

REF

AI+

QFN-32L

10 11 12 13 14 15 16

26272829303132

RO-

PAI

PAO-

PAO+

FSR

PCMR

BCLKR

AI-

FST

PCMT

AI-

FST

PCMT

PUI

MCLK

BCLKT

PUI

MCLK

BCLKT

REF

AI+

QFN-32L

W681360

Publication Release Date: January 2009

- 7 - Revision A.4

6. PIN DESCRIPTION

Name Pin No. Functionality

non-

QFN QFN

VREF 1 30

This pin is used to bypass the on–chip VDD/2 voltage reference for the VAG output pin. This pin

should be bypassed to VSS with a 0.1μF ceramic capacitor using short, low inductance traces. The

VREF pin is only used for generating the reference voltage for the VAG pin. Nothing is to be

connected to this pin except the bypass capacitor.

RO- 2 1

Inverting output of the receive smoothing filter. This pin can typically drive a 2kΩ load to 0.886VPEAK

referenced to analog ground.

PAI 3 2 Inverting input to the power amplifier. The non-inverting input is tied internally to VAG voltage.

PAO- 4 3

Inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to

1.772VPEAK.

PAO+ 5 5

Non-inverting power amplifier output. The PAO- and PAO+ can drive a 300Ω load differentially to

1.772VPEAK.

VDD 6 6

Power supply. Should be decoupled to VSS with a 0.1μF ceramic capacitor.

FSR 7 7

8kHz Frame Sync input for the PCM receive section. FSR can be asynchronous to FST in either

Long Frame Sync or Short Frame Sync mode.

PCMR 8 8 PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.

BCLKR 9 9

PCM receive bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz. When

not clocked it can be used to select the 16 sign-bit extended synchronous mode (BCLKR=0) or the

receive gain adjust synchronous mode (BCLKR=1)

PUI 10 12

Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS, the

part is powered down.

MCLK 11 13

System master clock input. Possible input frequencies are 256kHz, 512kHz, 1536kHz, 1544kHz,

2048kHz, 2560kHz, 4096kHz & 4800kHz. For performance reasons, it is recommended that MCLK

be synchronous and aligned to the FST signal. This is a requirement in the case of 256 and

512kHz frequencies.

BCLKT 12 16 PCM transmit bit clock input pin. Can accept any bit clock frequency from 256 to 4800kHz.

PCMT 13 17 PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.

FST 14 19 8kHz transmit frame sync input. This pin synchronizes the transmit data bytes.

VSS 15 20 This is the supply ground. This pin should be connected to 0V.

W681360

Publication Release Date: January 2009

- 8 - Revision A.4

Name Pin No. Functionality

non-

QFN QFN

HB 16 22

High-pass Bypass. Determines if the transmit high-pass filter is used (HB=’0’) or bypassed

(HB=’1’). When the high pass is bypassed the frequency response extends to DC.

AO 17 23 Analog output of the first gain stage in the transmit path.

AI- 18 24 Inverting input of the first gain stage in the transmit path.

AI+ 19 26 Non-inverting input of the first gain stage in the transmit path.

VAG 20 29

Mid-Supply analog ground pin, which supplies a VDD/2 volt reference voltage for all-analog signal

processing. This pin should be decoupled to VSS with a 0.01μF capacitor. This pin becomes high

impedance when the chip is powered down.

W681360

Publication Release Date: January 2009

- 9 - Revision A.4

7. FUNCTIONAL DESCRIPTION

W681360 is a single-rail, single channel PCM CODEC for voiceband applications. The CODEC

complies with the specifications of the ITU-T G.712 recommendation. The CODEC block diagram in

Section 3 illustrates the main components of the W681360. The chip consists of a PCM interface,

which can process long and short frame sync formats. The pre-scaler of the chip provides the internal

clock signals and synchronizes the CODEC sample rate with the external frame sync frequency. The

power conditioning block provides the internal power supply for the digital and the analog section,

while the voltage reference block provides a precision analog ground voltage for the analog signal

processing.

The calibration level for both the Analog to Digital Converter (ADC) and the Digital to Analog

Converter (DAC) is referenced to μ-Law with the same bit voltage weighing about the zero crossing,

resulting in the 0dBm0 calibration level 3.2dB below the peak sinusoidal level before clipping, Based

on the reference voltage of 0.886V the calibration level is 0.436 Vrms or –5dBm at 600Ω.

FIGURE 7.1: THE W681360 SIGNAL PATH

7.1. Transmit Path

The first stage of the A-to-D path of the CODEC is an analog input operational amplifier with externally

configurable gain settings. A differential analog input may be applied to the Inputs AI+ and AI-.

Alternately the input amplifier may be powered down and a single-ended input signal can be applied to

either the AO pin or the AI- pin. The input amplifier can be powered down by connecting the AI+ pin to

High Pass

Bypass

13 bit linear

DAC

Smoothing

Filter b

fC= 3400 Hz

Smoothing

Filter a

Buffer1

Av=1

DATA

Receive RO-

13 AI-

Anti-Aliasing

Filter b

fC= 3400 Hz

Anti-Aliasing

Filter a

fC= 200 Hz

High Pass

Filter

13 bit linear

ADC

DATA

Transmit AI+

PAI

PAO+

-PAO-

VAG

High Pass

Bypass

13 bit linear

DAC

Smoothing

Filter b

fC= 3400 Hz

Smoothing

Filter a

Buffer1

Av=1

DATA

Receive RO-

13 AI-AI-

Anti-Aliasing

Filter b

fC= 3400 Hz

Anti-Aliasing

Filter a

fC= 200 Hz

High Pass

Filter

13 bit linear

ADC

DATA

Transmit AI+AI+

PAI

PAO+

-PAO-

VAG

W681360

Publication Release Date: January 2009

- 10 - Revision A.4

either VDD or VSS which also determines whether AO or AI+ is selected as input according to Table 7.1.

When the input operational amplifier is powered down the AO pin becomes high input impedance.

TABLE 7.1: INPUT AMPLIFIER MODES OF OPERATION

AI+ (Pin 19) Input Amplifier Input

VDD Powered Down AO (Pin 17)

1.2 to VDD-1.2 Powered Up AI+, AI- (Pins 19, 18)

VSS Powered Down AI- (Pin 18)

When the input amplifier is powered down, the input signal at AO or AI- should be referenced to the

analog ground voltage VAG.

The output of the input operational amplifier is first fed through a low-pass filter to prevent aliasing at

the switched capacitor 3.4kHz low pass filter. Subsequently the 3.4kHz switched capacitor low pass

filter bandlimits the input signals well below 4kHz. Signals above 4kHz would be aliased at the

sampling rate of 8kHz. A high pass filter with a 200Hz cut-off frequency prevents DC coupling. All

filters are designed according to the G.712 ITU-T specification. The high-pass filter may be bypassed

depending on the logic level on the HB pin. If the high pass is removed the frequency response of the

device extends down to DC.

After filtering the signal is digitized as a 13-bit linear PCM code and fed to the PCM interface for serial

transmission at the sample rate supplied by the external frame sync FST.

7.1.1 Input Operational Amplifier Gain

The gain of the input operational amplifier can be adjusted using external resistors. For single-ended

input operation the gain is given by a simple resistive ratio.

FIGURE 7.2: INPUT OPERATIONAL AMPLIFIER GAIN – SINGLE-ENDED INPUT

For differential input operation the external resistor network is more complex but the gain is expressed

in the same way. Of course, a differential input also has an inherent 6dB advantage over a

corresponding single-ended input.

Gin = Ro/Ri

Vin

VAG

AI+

AI-

W681360

Publication Release Date: January 2009

- 11 - Revision A.4

FIGURE 7.3: INPUT OPERATIONAL AMPLIFIER GAIN – DIFFERENTI AL INPUT

The gain of the operational amplifier will be typically be set to 30dB for microphone interface circuits.

However the gain may be used for more than 30dB but this will require a compact layout with minimal

trace lengths and good isolation from noise sources. It is also recommended that the layout be as

symmetrical as possible as imbalances work against the noise canceling advantages of the differential

design.

7.2. Receive Path

The 13-bit digital input samples for the D-to-A path are serially shifted in by the PCM interface and

converted to parallel data bits. During every cycle of the frame sync FSR, the parallel data bits are fed

through the 13-bit linear DAC and converted to analog samples. The analog samples are filtered by a

low-pass smoothing filter with a 3.4kHz cut-off frequency, according to the ITU-T G.712 specification.

A sin(x)/x compensation is integrated with the low pass smoothing filter. The output of this filter is

buffered to provide the receive output signal RO-. The output may be also be attenuated when the

device is in the receive path adjust mode. If the device is operated half–channel with the FST pin

clocking and FSR pin held LOW, the receive filter input will be connected to the VAG voltage. This

minimizes transients at the RO– pin when full–channel operation is resumed by clocking the FSR pin.

The RO- output can be externally connected to the PAI pin to provide a differential output with high

driving capability at the PAO+ and PAO- pins. By using external resistors various gain settings of this

output amplifier can be achieved. If the transmit power amplifier is not in use, it can be powered down

by connecting PAI to VDD. The bias voltage and signal reference of the PAO+ & PAO– outputs is the

VAG pin. The VAG pin cannot source or sink as much current as these pins, and therefore low

impedance loads must be placed between PAO+ and PAO–. The PAO+ and PAO– differential drivers

are also capable of driving a 100Ω resistive load or a 100nF piezoelectric transducer in series with a

20Ω resister with a small increase in distortion. These drivers may be used to drive resistive loads of

32Ω when the gain of PAO– is set to 1/4 or less.

AI+

AI-

Vin+

Vin-

VAG

Gin = Ro/Ri

W681360

Publication Release Date: January 2009

- 12 - Revision A.4

7.2.1. Receive Gain Adjust Mode

The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin

while all other clocks are clocked normally. The device is then in a position to read 16-bits of data,

with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients

are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated

according to the values in the following table. If the feature is not used the default value is 0dB.

Coefficient Attenuation (dB)

000 0

001 3

010 6

011 9

100 12

101 15

110 18

111 21

TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE

7.3. POWER MANAGEMENT

7.3.1. Analog and Digital Supply

The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply

voltage is connected to the VDD pin. The VDD pin needs to be decoupled to ground through a 0.1 μF

ceramic capacitor.

7.3.2. Analog Ground Reference Bypass

The system has an internal precision voltage reference which generates the VDD/2 mid-supply analog

ground voltage. This voltage needs to be decoupled to VSS at the VREF pin through a 0.1 μF ceramic

capacitor.

7.3.3. Analog Ground Reference Voltage Output

The analog ground reference voltage is available for external reference at the VAG pin. This voltage

needs to be decoupled to VSS through a 0.01 μF ceramic capacitor. The analog ground reference

voltage is generated from the voltage on the VREF pin and is also used for the internal signal

processing.

W681360

Publication Release Date: January 2009

- 13 - Revision A.4

7.4. PCM INTERFACE

The PCM interface is controlled by pins BCLKR, FSR, BCLKT & FST. The input data is received

through the PCMR pin and the output data is transmitted through the PCMT pin.

The Long Frame Sync or Short Frame Sync interface mode can be selected by connecting the BCLKR

or BCLKT pin to a 256kHz to 4.800 MHz clock and connecting the FSR or FST pin to the 8kHz frame

sync. The device synchronizes the data word for the PCM interface and the CODEC sample rate on

the positive edge of the Frame Sync signal. Long Frame Sync is recognized when the FST pin is held

HIGH for two consecutive falling edges of the bit-clock at the BCLKT pin. Short Frame Sync Mode is

recognized when the Frame Sync signal at pin FST is HIGH for one and only one falling edge of the

bit-clock at the BCLKT pin.

7.4.1. Long frame sync

The device recognizes a Long Frame Sync when the FST pin is held HIGH for two consecutive falling

edges of the bit-clock at the BCLKT pin. The length of the Frame Sync pulse can vary from frame to

frame, as long as the positive frame sync edge occurs every 125 μsec. During data transmission in the

Long Frame Sync mode, the transmit data pin PCMT will become low impedance when the Frame

Sync signal FST is HIGH or when the 13-bit data word is being transmitted. The transmit data pin

PCMT will become high impedance when the Frame Sync signal FST becomes LOW while the data is

transmitted or when half of the LSB is transmitted. The internal decision logic will determine whether

the next frame sync is a long or a short frame sync, based on the previous frame sync pulse. To avoid

bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every power down

state. Long Frame Sync mode is illustrated below. More detailed timing information can be found in

the interface timing section.

Long Frame Sync (Transmit and Receive Have Individual Clocking)

FST

(FSR)

PCMT 7654321

BCLKT

(BCLKR)

12111098 13

PCMR 7654321 12111098 13don't care don't care

FIGURE 7.4: LONG FRAME SYNC PC M MODE

7.4.2. Short frame sync

The W681360 operates in the Short Frame Sync Mode when the Frame Sync signal at pin FST is

HIGH for one and only one falling edge of the bit-clock at the BCLKT pin. On the following rising edge

of the bit-clock, the W681360 starts clocking out the data on the PCMT pin, which will also change

from high to low impedance state. The data transmit pin PCMT will go back to the high impedance

state halfway through the LSB. The Short Frame Sync operation of the W681360 is based on a 13-bit

data word. When receiving data on the PCMR pin, the data is clocked in on the first falling edge after

W681360

Publication Release Date: January 2009

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the falling edge that coincides with the Frame Sync signal. The internal decision logic will determine

whether the next frame sync is a long or a short frame sync, based on the previous frame sync pulse.

To avoid bus collisions, the PCMT pin will be high impedance for two frame sync cycles after every

power down state. Short Frame Sync mode is illustrated below. More detailed timing information can

be found in the interface timing section.

Short Frame Sync (Transmit and Receive Have Individual Clocking)

FST

(FSR)

PCMT 7654321

BCLKT

(BCLKR)

12111098 13

PCMR 7654321 12111098 13don't care don't care

FIGURE 7.5: SHORT FRAME SYNC PCM MODE

7.4.3. Special 16-bit Receive Modes

7.4.3.1. Sign-Extended Mode Timing

The Sign-bit extended mode is entered by applying a logic “0” to the BCLKR pin while all other clocks

are clocked normally. In standard 13-bit mode the first bit is the sign bit. In this mode the device

transmits and receives 16-bit data where the sign bit is extended to the first four data bits. The PCM

timing for this mode is illustrated below.

Sign-Extended (BCLKR=0)

Transmit and Receive both use BCLKT, and the first four data bits are the sign bit.

FST may occur at a different time than FSR

FST (FSR)

SHORT OR

LONG FRAME

SYNC

PCMT 7654321

BCLKT

(BCLKR)

12111098 13

PCMR 7654321 12111098 13don't care don't care

1514 16

1514 16 don't care

FIGURE 7.6: SIGN EXTENDED MODE

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7.4.3.2. Receive Gain Adjust Mode Timing

The Receive Path Adjust Mode is entered by applying a logic “1” to the BCLKR pin while all other

clocks are clocked normally. In this mode the device receives 16-bit data where the last three bits are

coefficients to program the Receive Gain Adjust Attenuation described above. The PCM timing for

this mode is illustrated below.

FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE

7.4.4. System Timing

The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz &

4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and

can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz

and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency

versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are

LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the

W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to

LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the

transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the

pin PCMT becomes low impedance.

7.5. ON-CHIP POWER AMPLIFIER

The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to

the power amplifier is available at pin PAI. The non-inverting input is tied internally to VAG. The

inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power

amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to

1.772 VPEAK.

Connecting PAI to VDD will power down the power driver amplifiers and the PAO+ and PAO– outputs

will be high impedance.

Receive Gain Adjust (BCLKR=1)

Transmit and Receive both use BCLKT. FST may occur at a different time than FSR.

Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the

receive analog output.

FST (FSR)

SHO RT O R

LONG FRAME

SYNC

PCMT 7654321

BCLKT

(BCLKR)

12111098

PCMR 7654321 12111098 13don't care don't care

1514 16 don't care

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8. TIMING DIAGRAMS

FIGURE 8.1: LONG FRAME SYNC PC M TIMING

NOTE: The Data is clocked out on the rising edge of BCLK.

The Data is clocked in on the falling edge of BCLK.

TFTRH

TFTRS TFTFH

TFDTD

TBDTD

TBCKH TBCKL

TBCK

THID THID

TRISE TFALL

TMCK

TMCKH

TFTRHM TFTRSM

TMCKL

TFS

TFSL

TFRRH

TFRRS TFRFH

TBCKH TBCKL

TDRS

TDRH

MCLK

BCLKT

FST

PCMT

BCLKR

(BCLKT)

FSR

PCMR

TBCK

MSB LSB

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TABLE 8.1: LONG FRAME SYNC PCM TIMING PARAMETERS

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

TFSL FST / FSR Minimum LOW Width 1 T

BCK sec

1/TBCK BCLKT, BCLKR Frequency 1 256 --- 4800 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT Falling Edge to FST Rising

Edge Hold Time 20 --- --- ns

TFTRS FST Rising Edge to BCLKT Falling

edge Setup Time 80 --- --- ns

TFTFH BCLKT Falling Edge to FST Falling

Edge Hold Time 50 --- --- ns

TFDTD

The later of BCLKT rising edge, or FST

rising edge to first valid PCMT Bit Delay

Time

--- --- 60 ns

TBDTD BCLKT Rising Edge to Valid PCMT

Delay Time --- --- 60 ns

THID

Delay Time from the Later of FST

Falling Edge, or

BCLKT Falling Edge of last PCMT Bit to

PCMT Output High Impedance

10 --- 60 ns

TFRRH BCLKR Falling Edge to FSR Rising

Edge Hold Time 20 --- --- ns

TFRRS FSR Rising Edge to BCLKR Falling

edge Setup Time 80 --- --- ns

TFRFH BCLKR Falling Edge to FSR Falling

Edge Hold Time 50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge

Setup Time 1 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling

Edge 50 --- --- ns

1 TFSL must be at least ≥ TBCK

W681360

Publication Release Date: January 2009

- 18 - Revision A.4

FIGURE 8.2: SHORT FRAME SYNC PCM TIMING

TFTRH

TFTRS

TFTFH

TBDTD

TBCKH TBCKL

TBCK

THID

TRISE TFALL

TMCK

TMCKH

TFTRHM TFTRSM

TMCKL

TFS

TFRRH

TFRRS

TFRFH

TBCKH TBCKL

TDRS

TDRH

MCLK

BCLKT

FST

PCMT

BCLKR

(BCLKT)

FSR

PCMR

TBDTD

TBCK

TFTFS

TFRFS

MSB LSB

W681360

Publication Release Date: January 2009

- 19 - Revision A.4

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TFS FST, FSR Frequency --- 8 --- kHz

1/TBCK BCLKT, BCLKR Frequency 256 --- 4800 kHz

TBCKH BCLKT, BCLKR HIGH Pulse Width 50 --- --- ns

TBCKL BCLKT, BCLKR LOW Pulse Width 50 --- --- ns

TFTRH BCLKT Falling Edge to FST Rising Edge Hold Time 20 --- --- ns

TFTRS FST Rising Edge to BCLKT Falling edge Setup Time 80 --- --- ns

TFTFH BCLKT Falling Edge to FST Falling Edge Hold Time 50 --- --- ns

TFTFS FST Falling Edge to BCLKT Falling Edge Setup Time 50 --- --- ns

TBDTD BCLKT Rising Edge to Valid PCMT Delay Time 10 --- 60 ns

THID Delay Time from BCLKT Falling Edge at last PCMT bit

(LSB) to PCMT Output High Impedance 10 --- 60 ns

TFRRH BCLKR Falling Edge to FSR Rising Edge Hold Time 20 --- --- ns

TFRRS FSR Rising Edge to BCLKR Falling edge Setup Time 80 --- --- ns

TFRFH BCLKR Falling Edge to FSR Falling Edge Hold Time 50 --- --- ns

TFRFS FSR Falling Edge to BCLKR Falling Edge Setup Time 50 --- --- ns

TDRS Valid PCMR to BCLKR Falling Edge Setup Time 1 --- --- ns

TDRH PCMR Hold Time from BCLKR Falling Edge 50 --- --- ns

TABLE 8.2: SHORT FRAME SYNC PCM TIMING PARAMETERS

W681360

Publication Release Date: January 2009

- 20 - Revision A.4

SYMBOL DESCRIPTION MIN TYP MAX UNIT

1/TMCK Master Clock Frequency ---

256

512

1536

1544

2048

2560

4096

4800

--- kHz

TMCKH /

TMCK MCLK Duty Cycle for 256kHz Operation 45% 55%

TMCKH Minimum Pulse Width HIGH for

MCLK(512kHz or Higher) 50 --- --- ns

TMCKL Minimum Pulse Width LOW for MCLK

(512kHz or Higher) 50 --- --- ns

TFTRHM MCLK falling Edge to FST Rising Edge

Hold Time 50 --- --- ns

TFTRSM FST Rising Edge to MCLK Falling edge

Setup Time 50 --- --- ns

TRISE Rise Time for All Digital Signals --- --- 50 ns

TFALL Fall Time for All Digital Signals --- --- 50 ns

Table 8.3: General PCM Timing Parameters

W681360

Publication Release Date: January 2009

- 21 - Revision A.4

9. ABSOLUTE MAXIMUM RATINGS

9.1. ABSOLUTE MAXIMUM RATINGS

Condition Value

Junction temperature 1500C

Storage temperature range -650C to +1500C

Voltage applied to any pin (VSS - 0.3V) to (VDD + 0.3V)

Voltage applied to any pin (Input current limited to +/-20 mA) (VSS – 1.0V) to (VDD + 1.0V)

VDD - VSS -0.5V to +6V

1. Stresses above those listed may cause permanent damage to the device. Exposure to the absolute

maximum ratings may affect device reliability. Functional operation is not implied at these conditions.

9.2. OPERATING CONDITIONS

Condition Value

Industrial operating temperature -400C to +850C

Supply voltage (VDD) +2.7V to +5.25V

Ground voltage (VSS) 0V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely

affect the life and reliability of the device.

W681360

Publication Release Date: January 2009

- 22 - Revision A.4

10. ELECTRICAL CHARACTERISTICS

10.1. GENERAL PARAMETERS

VDD=2.7V – 3.6V; VSS=0V; TA=-40°C to +85°C;

Symbol Parameters Conditions Min (2) Typ

(1) Max

(2) Units

VIL Input LOW Voltage 0.6 V

VIH Input HIGH Voltage 2.2 V

VOL PCMT Output LOW Voltage IOL = 1.6 mA 0.4 V

VOH PCMT Output HIGH Voltage IOL = -1.6 mA VDD–0.5 V

IDD VDD Current (Operating) - ADC

+ DAC No Load 3.25 4.7 mA

ISB V

DD Current (Standby) FST&FSR =Vss ; PUI=VDD (3) 1 100

μA

IPD V

DD Current (Power Down) PUI= Vss (3) 0.03 10

μA

IIL Input Leakage Current VSS<VIN<VDD -10 +10

μA

IOL PCMT Output Leakage Current VSS<PCMT<VDD

High Z State -10 +10

μA

CIN Digital Input Capacitance 10 pF

COUT PCMT Output Capacitance PCMT High Z 15 pF

1. Typical values: TA = 25°C , VDD = 3.0 V

2. All min/max limits are guaranteed by Nuvoton via electrical testing or characterization. Not all

specifications are 100 perc en t tested.

3. No DC load from VREF & VAG to Vss

W681360

Publication Release Date: January 2009

- 23 - Revision A.4

10.2. ANALOG SIGNAL LEVEL AND GAIN PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; 0dBm0 = 0.436

Vrms = -5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz

PARAMETER SYM. CONDITION TYP.

TRANSMIT

(A/D) RECEIVE

(D/A) UNIT

MIN. MAX. MIN. MAX.

Absolute Level LABS 0 dBm0 = -5dBm @ 600Ω0.616

0.436 --- --- --- ---

VPK

VRMS

Max. Transmit

Level TXMAX 3.2

0.886 --- --- --- ---

dBm0

VPK

Absolute Gain (0

dBm0 @ 1020Hz;

TA=+25°C)

GABS 0 dBm0 @ 1020Hz;

TA=+25°C 0 -0.20 +0.20 -0.20 +0.20 dB

Absolute Gain

variation with

Temperature

GABST TA=0°C to TA=+70°C

TA=-40°C to TA=+85°C 0 -0.05

-0.10

+0.05

+0.10

-0.05

-0.10

+0.05

+0.10 dB

Frequency

Response,

Relative to 0dBm0

@ 1020Hz

(HB=0)

GRTV

15Hz

50Hz

60Hz

200Hz

300 to 1600Hz

1600 to 2400Hz

2400 to 3000Hz

3300Hz

3400Hz

3600Hz

4000Hz

4600Hz to 100kHz

---

-1.4

-0.2

-0.7

---

-45

-30

-26

-0.4

+0.2

+0.15

-12.5

-32

-0.5

-0.2

-0.25

-0.4

-0.8

---

+0.2

+0.25

+0.2

+0.15

-12.5

-30

W681360

Publication Release Date: January 2009

- 24 - Revision A.4

10.3. ANALOG DISTORTION AND NOISE PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG; 0dBm0 = 0.436

Vrms = -5dBm @ 600 Ohm; FST =FSR = 8kHz;MCLK=BCLK= 2.048 MHz

PARAMETER SYM. CONDITION TRANSMIT (A/D) RECEIVE (D/A) UNIT

MIN. TYP. MAX. MIN. TYP. MAX.

Total Distortion

vs. Level Tone

(1020Hz, C-

Message

Weighted)

DLT

+3 dBm0

0 dBm0

-10 dBm0

-20 dBm0

-30 dBm0

-40 dBm0

-50 dBm0

-60 dBm0

---

dBC

Spurious Out-Of-

Band at RO-

(300Hz to 3400Hz

@ 0dBm0)

DSPO

4600Hz to 7600Hz

7600Hz to 8400Hz

8400Hz to 100000Hz

---

-30

-40

-30

Crosstalk

(1020Hz @

0dBm0)

DXT --- --- -75 --- --- -75 dB

Absolute Group

Delay τABS 1200Hz (HB=0) --- --- 360 --- --- 240 μsec

Group Delay

Distortion (relative

to group delay @

1200Hz)

τD

500Hz

600Hz

1000Hz

2600Hz

2800Hz

---

750

380

130

750

---

750

370

120

750

μsec

Idle Channel

Noise NIDL C-message weighted

Psophometric weighted

---

-72

---

-74

dBrnc0

dBm0p

W681360

Publication Release Date: January 2009

- 25 - Revision A.4

10.4. ANALOG INPUT AND OUTPUT AMPLIFIER PARAMETERS

VDD=2.7V to 3.6V; VSS=0V; TA=-40°C to +85°C; all analog signals referred to VAG;

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

AI Input Offset Voltage VOFF,AI AI+, AI- --- --- ±25 mV

AI Input Current IIN,AI AI+, AI- --- ±0.1 ±1.0 μA

AI Input Resistance RIN,AI AI+, AI- to VAG 10 --- --- MΩ

AI Input Capacitance CIN,AI AI+, AI- --- --- 10 pF

AI Common Mode Input Voltage

Range VCM,AI AI+, AI- 1.2 --- VDD-1.2 V

AI Common Mode Rejection Ratio CMRRTI AI+, AI- --- 60 --- dB

AI Amp Gain Bandwidth Product GBWTI AO, RLD≥10kΩ --- 2500 --- kHz

AI Amp DC Open Loop Gain GTI AO, RLD≥10kΩ --- 95 --- dB

AI Amp Equivalent Input Noise NTI C-Message Weighted --- -24 --- dBrnC

AO Output Voltage Range VTG RLD=2kΩ to VAG 0.4 --- VDD-0.4 V

Load Resistance RLDTGRO AO, RO to VAG 2 --- --- kΩ

Load Capacitance CLDTGAO AO --- --- 100 pF

Load Capacitance CLDTGRO RO --- --- 200 pF

AO & RO Output Current IOUT1 0.5 ≤AO,RO-≤ VDD-0.5 ±1.0 --- --- mA

RO- Output Resistance RRO- RO-, 0 to 3400Hz --- 1 --- Ω

RO- Output Offset Voltage VOFF,RO- RO- to VAG --- ---

±25 mV

Analog Ground Voltage VAG Relative to VSS (no

load) VDD/2-0.1 VDD/2 VDD/2+0.1 V

W681360

Publication Release Date: January 2009

- 26 - Revision A.4

PARAMETER SYM. CONDITION MIN. TYP. MAX. UNIT.

VAG Output Resistance RVAG Within ±25mV change --- 12.5 25 Ω

Power Supply Rejection Ratio (0 to

100kHz to VDD, C-message. All

signals referenced to VAG)

PSRR Transmit

Receive

---

--- dBC

PAI Input Offset Voltage VOFF,PAI PAI --- --- ±25 mV

PAI Input Current IIN,PAI PAI --- ±0.05 ±1.0 μA

PAI Input Resistance RIN,PAI PAI to VAG 10 --- ---

MΩ

PAI Amp Gain Bandwidth Product GBWPI PAO- no load

(@10kHz) --- 1000 --- kHz

Output Offset Voltage VOFF,PO PAO+ to PAO- --- --- ±50 mV

Load Capacitance CLDPO

PAO+, PAO-

differentially or PAO+,

PAO to VAG

--- --- 1000 pF

PAO Output Current IOUTPAO 0.4 ≤ PAO+,PAO--≤

VDD-0.4 ±10.0 --- --- mA

PAO Output Resistance RPAO PAO+ to PAO- --- 1 --- Ω

PAO Differential Gain GPAO RLD=300Ω, +3dBm0,

1kHz, PAO+ to PAO- -0.2 0 +0.2 dB

PAO Differential Signal to Distortion

C-Message weighted DPAO

ZLD=300

ZLD=100nF + 20Ω

ZLD=100Ω (10mA

limit)

---

dBC

PAO Power Supply Rejection Ratio

(0 to 25kHz to VDD, Differential out)

PSRRPA

0 to 4kHz

4 to 25kHz

---

--- dB

W681360

Publication Release Date: January 2009

- 27 - Revision A.4

10.5. Digital I/O

10.5.1. PCM Codes for Zero and Full Scale

Level Sign bit Magnitude Bits

+ Full Scale 0 1111 1111 1111

+ One Step 0 0000 0000 0001

Zero 0 0000 0000 0000

- One Step 1 1111 1111 1111

- Full Scale 1 0000 0000 0000

10.5.2. PCM Codes for 1kHz Digital Milliwatt

Phase Sign bit Magnitude Bits

π / 8 0 0100 0011 1100

3π / 8 0 1010 0011 1001

5π / 8 0 1010 0011 1001

7π / 8 0 0100 0011 1100

9π / 8 1 1011 1100 0100

11π / 8 1 0101 1100 0111

13π / 8 1 0101 1100 0111

15π / 8 1 1011 1100 0100

W681360

Publication Release Date: January 2009

- 28 - Revision A.4

11. TYPICAL APPLICATION CIRCUIT

1.0 uF

100pF

POWER CONTROL

0.1 uF

8 KHz Frame Sy nc

22 uF

PCM IN

VDD

3.9K+

62K

2.048 MHz

Bit Clock

1.5K

100pF

27K

MICROPHONE

0.1 uF

27K

3.9K

ELECTRET

27K

0.01 uF

62K

1.5K

W681360

615

VDDVSS

PUI

FST

BCLKT

PCMT

MCLK

PCMR

BCLKR

FSR

AI-

AI+

VAG

VREF

RO-

PAO+

PAI

PAO-

SPEAKER

PCM OUT

HP FILTER SELECT

FIGURE 11.1: TYPICAL HANDSET INTERFACE

W681360

Publication Release Date: January 2009

- 29 - Revision A.4

12. PACKAGE DRAWING AND DIMENSIONS

12.1. 20L SOG (SOP)-300MIL

SMALL OUTLINE PACKAGE (SAME AS SOG & SOIC) DIMENSIONS

SYMBOL

DIMENSION (MM) DIMENSION (INCH)

MIN. MAX. MIN. MAX.

A 2.35 2.65 0.093 0.104

A1 0.10 0.30 0.004 0.012

b 0.33 0.51 0.013 0.020

c 0.23 0.32 0.009 0.013

E 7.40 7.60 0.291 0.299

D 12.60 13.00 0.496 0.512

e 1.27 BSC 0.050 BSC

HE 10.00 10.65 0.394 0.419

Y - 0.10 - 0.004

L 0.40 1.27 0.016 0.050

0 0º 8º 0º 8º

SEATING

0.2

GAUGE

20 11

W681360

Publication Release Date: January 2009

- 30 - Revision A.4

12.2. 20L SSOP-209 MIL

SHRINK SMALL OUTLINE PACKAGE DIMENSIONS

SYMBOL

DIMENSION (MM) DIMENSION (INCH)

MIN. NOM. MAX. MIN. NOM. MAX.

A - - 2.00 - - 0.079

A1 0.05 - - 0.002 - -

A2 1.65 1.75 1.85 0.065 0.069 -

b 0.22 - 0.38 0.009 - 0.015

c 0.09 - 0.25 0.004 - 0.010

D 6.90 7.20 7.50 0.272 0.283 0.295

E 5.00 5.30 5.60 0.197 0.209 0.220

HE 7.40 7.80 8.20 0.291 0.307 0.323

e - 0.65 - - 0.0256 -

L 0.55 0.75 0.95 0.021 0.030 0.037

L1 - 1.25 - - 0.050 -

Y - - 0.10 - - 0.004

0 0º - 8º 0 - 8º

SEATING

DTEAIL

DETAIL

SEATING

W681360

Publication Release Date: January 2009

- 31 - Revision A.4

12.3. 20L TSSOP - 4.4X6.5MM

PLASTIC THIN SHRINK S M ALL OUTLINE PACKAGE (TSSOP) DI MENSIONS

SYMBOL

DIMENSION (MM) DIMENSION (INCH)

MIN. NOM. MAX. MIN. NOM. MAX.

A - - 1.20 - - 0.047

A1 0.05 - 0.15 0.002 - 0.006

A2 0.80 0.90 1.05 0.031 0.035 0.041

E 4.30 4.40 4.50 0.169 0.173 0.177

HE 6.40 BSC .252 BSC

D 6.40 6.50 6.60 0.252 0.256 0.260

L 0.50 0.60 0.75 0.020 0.024 0.030

L1 1.00 REF 0.039 REF

b 0.19 - 0.30 0.007 - 0.012

e 0.65 BSC 0.026 BSC

c 0.09 - 0.20 0.004 - 0.008

0 0º - 8º 0º - 8º

Y 0.10 BASIC 0.004 BASIC

W681360

Publication Release Date: January 2009

- 32 - Revision A.4

12.3. QFN-32L

QUAD FLAT PACK NO LE ADS PACKAGE (QFN) DIMENSIONS

W681360

Publication Release Date: January 2009

- 33 - Revision A.4

13. ORDERING INFORMATION

Nuvoton Part Number Description

When ordering W681360 series devices, please refer to the following part numbers.

Part Number

W681360SG

W681360RG

W681360WG

W681360YG

Package Type:

S = 20-Lead Plastic Small Outline Package (SOG/SOP)

R = 20-Lead Plastic Shrink Small Outline Package (SSOP)

W = 20-Lead Plastic Thin Shrink Small Outline Package (TSSOP)

Y = 32-Quad Flat No leads Package (QFN)

Product Family

W681360

W681360_ _

Package Material:

G = Pb-free (RoHS) Package

W681360

Publication Release Date: January 2009

- 34 - Revision A.4

14. VERSION HISTORY

VERSION DATE PAGE DESCRIPTION

A.1 April 2004 All Preliminary Specification

A.15 April 2005 32 Add Important Note

A.16 September,

2005

6, 7

10, 12

Added reference to Pb-free RoHS packaging and to VRMS

Added reference to QFN-32L package

Added QFN-32L Pinout

Added Pin numbers to Tables

Capitalized logic HIGH/LOW

Added Reference to VRMS

Improved Application Diagram

Added QFN-32L Mechanical Dimensions

Added Y and G package ordering code

A.3 January

2009

24 Idle Channel Noise (C-message weighted) receive maximum

parameter updated

A.4 January

2009

33 Leaded packages no longer supported

Important Notice

Nuvoton products are not designed, intended, authorized or warranted for use as components

in systems or equipment intended for surgical implantation, atomic energy control instruments,

airplane or spaceship instruments, transportation instruments, traffic signal instruments,

combustion control instruments, or for other applications intended to support or sustain life.

Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton

products could result or lead to a situation wherein personal injury, death or severe property

or environmental damage could occur.

Nuvoton customers using or selling these products for use in such applications do so at their

own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper

use or sales.

The information contained in this datasheet may be subject to change without

notice. It is the responsibility of the customer to check the Nuvoton USA website

(www.nuvoton-usa.com) periodically for the latest version of this document, and

any Errata Sheets that may be generated between datasheet revisions.