Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializer ADN2855 Data Sheet FEATURES GENERAL DESCRIPTION Serial data input 155.52 Mbps/622.08 Mbps/1244.16 Mbps/1250.00 Mbps 12-bit acquisition time 4-bit parallel LVDS output interface Patented dual-loop clock recovery architecture Integrated PRBS generator Byte rate reference clock Loss-of-lock indicator Supports double data rate (DDR)-compatible FPGA I2C interface to access optional features Single-supply operation: 3.3 V Power 670 mW typical in serial output mode 825 mW typical in deserializer mode 5 mm x 5 mm, 32-lead LFCSP The ADN2855 is a burst mode clock and data recovery IC designed for GPON/BPON/GEPON optical line terminal (OLT) receiver applications. The part can operate at 155.52 Mbps, 622.08 Mbps, 1244.16 Mbps, or 1250.00 Mbps data rates, selectable via the I2C interface. The ADN2855 frequency locks to the OLT reference clock and aligns to the input data within 12 bits of the start of the preamble. The device provides a full rate or an optional half rate output clock for a double data rate (DDR) interface to an FPGA or digital ASIC. All specifications are quoted for -40C to +85C ambient temperature, unless otherwise noted. The ADN2855 is available in a compact 5 mm x 5 mm, 32-lead chip scale package. APPLICATIONS Passive optical networks GPON/BPON/GEPON OLT receivers FUNCTIONAL BLOCK DIAGRAM REFCLKP, REFCLKN DATAV CF1 CF2 VCC VEE ADN2855 RESET FREQUENCY/ LOCK DETECT LOOP FILTER PHASE DETECT LOOP FILTER PIN NIN CML INPUT BUFFER PHASE SHIFTER VCO DATA RE-TIMING 2 I2C DIVIDER DESERIALIZER SDA SCK SQUELCH 4x2 CLKOUTP, CLKOUTN 06660-001 DATxP, DATxN 2 Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2009-2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADN2855 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C Interface Timing and Internal Register Description ..............9 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 11 General Description ......................................................................... 1 Functional Description .................................................................. 12 Functional Block Diagram .............................................................. 1 Frequency Acquisition ............................................................... 12 Revision History ............................................................................... 2 Squelch Mode ............................................................................. 12 Specifications..................................................................................... 3 I2C Interface ................................................................................ 12 Jitter Specifications ....................................................................... 3 Reference Clock .......................................................................... 13 Output and Timing Specifications ............................................. 4 Output Modes ............................................................................. 14 Timing Characteristcs .................................................................. 5 Disable Output Buffers .............................................................. 14 Reset Timing Options .................................................................. 6 Applications Information .............................................................. 15 Absolute Maximum Ratings............................................................ 7 PCB Design Guidelines ............................................................. 15 Thermal Resistance ...................................................................... 7 Outline Dimensions ....................................................................... 17 ESD Caution .................................................................................. 7 Ordering Guide .......................................................................... 17 Pin Configuration and Function Descriptions ............................. 8 REVISION HISTORY 4/2017--Rev. A to Rev. B Changed CP-32-13 to CP-32-20 .................................. Throughout Changes to Soldering Guidelines for Chip Scale Package Section........................................................................................................ 16 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 2/2013--Rev. 0 to Rev. A Change to Table 5 ............................................................................. 7 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 1/2009--Revision 0: Initial Version Rev. B | Page 2 of 20 Data Sheet ADN2855 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 F, input data pattern: PRBS 223 - 1, unless otherwise noted. Table 1. Parameter INPUT BUFFER--DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input ACQUISITION TIME (BDR Mode 1) Lock to Preamble Data POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT Conditions Min @ PIN or NIN, dc-coupled PIN - NIN VCC - 0.6 0.2 1250.00 Mbps 1244.16 Mbps 622.08 Mbps 155.52 Mbps 3.0 Serial output mode Deserializer mode OPERATING TEMPERATURE RANGE 1 Typ 12 12 12 6 3.3 204 250 -40 Max Unit VCC - 0.1 1.2 V V 3.6 +85 Bits Bits Bits Bits V mA mA C BDR mode = burst clock and data recovery mode, whereas CDR = continuous clock and data recovery mode. JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 F, input data pattern: PRBS 223 - 1, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Tolerance Conditions Min 1250.00 Mbps, 223 - 1 PRBS 50 kHz 500 kHz 10 MHz 1244.16 Mbps, 223 - 1 PRBS 50 kHz 500 kHz 10 MHz 622.08 Mbps, 223 - 1 PRBS 25 kHz 250 kHz 155.52 Mbps, 223 - 1 PRBS 6.5 kHz 65 kHz Rev. B | Page 3 of 20 Typ Max Unit 3.0 1.0 0.5 UI p-p UI p-p UI p-p 3.0 1.0 0.5 UI p-p UI p-p UI p-p 2.5 1.0 UI p-p UI p-p 3.5 1.0 UI p-p UI p-p ADN2855 Data Sheet OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter Symbol Conditions Min Typ Max Unit LVDS OUPUT CHARACTERISTICS CLKOUTP/CLKOUTN, DATxP/DATxN Differential Output Swing VDIFF See Figure 3 260 320 400 mV 1475 mV mV mV Output High Voltage Output Low Voltage Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time I2C INTERFACE DC CHARACTERISTICS (SCK, SDA) Input High Voltage Input Low Voltage Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK and SDA Rise/Fall Time Stop Condition Setup Time Bus Free Time between a Stop and a Start REFCLK CHARACTERISTICS Input Voltage Range Minimum Differential Input Drive Reference Frequency Required Accuracy LVTTL DC INPUT CHARACTERISTICS (SQUELCH, SADDR[2:1], RESET) Input High Voltage Input Low Voltage Input High Current Input Low Current VOH VOL VOS 925 1125 Differential 20% to 80% 80% to 20% tS tH 0.5 - 20% 0.5 - 20% 1200 100 1275 115 115 0.5 0.5 220 220 ps ps UI UI LVCMOS VIH VIL VOL 0.7 VCC VIN = 0.1 VCC or VIN = 0.9 VCC IOL = 3.0 mA 0.3 VCC +10.0 0.4 -10.0 400 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tR/tF tSU;STO tBUF 600 1300 600 600 100 300 20 + 0.1 Cb 1 600 1300 300 V V A V kHz ns ns ns ns ns ns ns ns ns At REFCLKP or REFCLKN VIL VIH 10 VIH VIL IIH IIL VIN = 2.4 V VIN = 0.4 V VOH VOL IOH = -2.0 mA IOL = 2.0 mA 0 VCC 100 155.52 0 200 2.0 0.8 5 -5 V V mV p-p MHz ppm V V A A LVTTL DC OUTPUT CHARACTERISTICS (DATAV) Output High Voltage Output Low Voltage 1 2.4 Cb = total board capacitance of one bus line in picofarads (pF). If mixed with high speed class of I2C devices, faster fall times are allowed. Rev. B | Page 4 of 20 0.4 V V Data Sheet ADN2855 TIMING CHARACTERISTCS CLKOUTP tH 06660-102 tS DATxP/ DATxN Figure 2. Output Timing OUTP VLVDS VSE OUTN OUTP - OUTN VSE 06660-103 VDIFF 0V Figure 3. Single-Ended vs. Differential Output Specifications CLKOUTP tH 06660-003 tS DAT0P/ DAT0N Figure 4. Serial Output Mode (Full Rate Clock) CLKOUTP tH 06660-004 tS DAT0P/ DAT0N Figure 5. Serial Output Mode (Half Rate Clock, DDR Mode) CLKOUTP tS 06660-005 tH DATxP/ DATxN Figure 6. Nibble Output Mode (Full Rate Clock) CLKOUTP tH 06660-006 tS DATxP/ DATxN Figure 7. Nibble Output Mode (Half Rate Clock, DDR Mode) Rev. B | Page 5 of 20 ADN2855 Data Sheet RESET TIMING OPTIONS OPTION 1 RESET PULSE (2 BYTES) END OF PACKET GUARD TIME (4 BYTES) OPTION 2 RESET PULSE (2 BYTES) 0 BYTES TO 8 BYTES END OF PACKET 200s BETWEEN BURSTS THIS ASSUMES NO NOISE IS PRESENT ON THE INPUTS TO THE ADN2855 OPTION 3 RESET PULSE 0 BYTES TO 8 BYTES 200s BETWEEN BURSTS THIS ASSUMES NO NOISE IS PRESENT AT THE INPUTS TO THE ADN2855 BETWEEN BURSTS. IF THIS IS THE CASE, THE RESET PULSE MUST BEASSERTED UNTIL THE TIME THAT THE INPUT DATA TO THE ADN2855 BECOMES VALID, IDEALLY JUST PRIOR TO THE START OF THE PREAMBLE. THERE IS NO REQUIREMENT THAT FOLLOWING THE DEASSERTION OF THE RESET SIGNAL THE ADN2855 MUST SEE AT LEAST 13 BITS OF THE PREAMBLE. Figure 8. Reset Timing Options Rev. B | Page 6 of 20 06660-007 END OF PACKET Data Sheet ADN2855 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 F, unless otherwise noted. THERMAL RESISTANCE JA is specified for 4-layer board with exposed paddle soldered to VEE. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE - 0.4 V VCC + 0.4 V 125C -65C to +150C Table 5. Thermal Resistance Package Type 32-Lead LFCSP (CP-32-20) ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 7 of 20 JA 35.1 JC 2.4 Unit C/W ADN2855 Data Sheet VCC VEE SQUELCH CLKOUTN CLKOUTP VCC DAT0P DAT0N PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADN2855 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VCC VEE DAT1P DAT1N DAT2P DAT2N DAT3P DAT3N NOTES 1. THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO VEE (GND). 06660-002 SCK REFCLKP REFCLKN VCC VEE CF2 CF1 DATAV 9 10 11 12 13 14 15 16 SADDR[2] RESET SADDR[1] NIN PIN VCC VEE SDA 32 31 30 29 28 27 26 25 PIN 1 INDICATOR Figure 9. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (EPAD) 1 Mnemonic SADDR[2] RESET SADDR[1] NIN PIN VCC VEE SDA SCK REFCLKP REFCLKN VCC VEE CF2 CF1 DATAV DAT3N DAT3P DAT2N DAT2P DAT1N DAT1P VEE VCC DAT0N DAT0P VCC CLKOUTP CLKOUTN SQUELCH VEE VCC Exposed Pad (EPAD) Type1 DI DI DI AI AI P P IO DI DI DI P P AO AO DO DO DO DO DO DO DO P P DO DO P DO DO DI P P P Description Slave Address Bit 2. RESET Pulse to be Asserted Prior to Incoming Burst. Active high. Slave Address Bit 1. Differential Data Input. CML. Differential Data Input. CML. 3.3 V Power. GND. I2C Data I/O. I2C Clock. Differential REFCLK Input. Differential REFCLK Input. 3.3 V Power. GND. Frequency Loop Capacitor. Frequency Loop Capacitor. Output Data Valid. LVTTL active low. Differential Deserialized Output MSB, LVDS. Differential Deserialized Output MSB, LVDS. Differential Deserialized Output Bit 2, LVDS. Differential Deserialized Output Bit 2, LVDS. Differential Deserialized Output Bit 1, LVDS. Differential Deserialized Output Bit 1, LVDS. GND. 3.3 V Power. Differential Deserialized Output LSB, LVDS Differential Deserialized Output LSB, LVDS 3.3 V Power Differential Recovered Clock Output, LVDS. Differential Recovered Clock Output, LVDS. Squelch Data and/or Clock Outputs. Active high. GND 3.3 V Power. There is an exposed pad on the bottom of the package that must be connected to VEE (GND). P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output, IO = digital input/output. Rev. B | Page 8 of 20 Data Sheet ADN2855 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 0 0 0 0 PIN 1 PIN 3 X 0=W 1=R 06660-008 R/W CTRL SADDR[7:1] S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 06660-009 Figure 10. Slave Address Configuration Figure 11. I2C Write Data Transfer SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER 06660-010 S S = START BIT A(S) = ACKNOWLEDGE BY SLAVE Figure 12. I2C Read Data Transfer SDA SLAVE ADDRESS A6 SUB ADDRESS A5 STOP BIT DATA A7 A0 D7 D0 SCK S WR ACK ACK SADDR[4:0] ACK SUB ADDR[6:1] DATA[6:1] Figure 13. I2C Data Transfer Timing tF tSU;DAT tHD;STA tBUF SDA tR tR tSU;STO tF tLOW tHIGH tHD;STA S tSU;STA tHD;DAT 2 S Figure 14. I C Port Timing Diagram Rev. B | Page 9 of 20 P S 06660-012 SCK P 06660-011 START BIT ADN2855 Data Sheet Table 7. Internal Register Map 1 Reg. Name CTRLA CTRLA_RD CTRLB R/W W R W Address 0x08 0x05 0x09 CTRLB_RD CTRLC R W 0x06 0x11 CTRLD W 0x22 1 D7 D6 FREF range 0 0 D5 Initiate acquisition 0 0 Bus swap Output mode Disable data buffer Disable clock buffer D4 D3 Data rate/DIV_FREF ratio Readback CTRLA 0 0 D2 D1 0 D0 Lock to REFCLK 0 0 0 0 Output boost 0 Serial CLKOUT mode Readback CTRLB Parallel RxCLK phase CLKOUT mode adjust 0 0 0 All writeable registers default to 0x00. Table 8. Control Register, CTRLA1 Table 10. Control Register, CTRLC Bit No. [7:6] Bit No. [7:6] [5] [5:2] [1] [0] 1 Description FREF range 00 = 10 MHz to 25 MHz 01 = 25 MHz to 50 MHz 10 = 50 MHz to 100 MHz 11 = 100 MHz to 200 MHz Data rate/DIV_FREF ratio 0000 = 1 0001 = 2 0010 = 4 ... n = 2n ... 1000 = 256 Set to 0 Lock to RFCLK 0 = lock to input data 1 = lock to reference clock [4] [3:2] [1] [0] Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock section). Table 11. Control Register, CTRLD Table 9. Control Register, CTRLB Bit No. [7] Bit No. [7:6] [5] [6] [4:0] Description Set to 0 Bus swap 0 = DAT3 is earliest bit 1 = DAT0 is earliest bit Parallel CLKOUT mode 0 = full rate parallel clock 1 = half rate parallel clock (DDR mode) RxCLK phase adjust 00 = CLK edge in center of eye 01 = +2 UI vs. baseline (CLK edge aligned with data transition) 10 = +0.5 UI vs. baseline 11 = -1.5 UI vs. baseline Set to 0 Output boost 0 = default 1 = boost output swing Description Set to 0 Initiate acquisition; write a 1 followed by 0 to initiate a new acquisition Set to 0 [5] [4:1] [0] Rev. B | Page 10 of 20 Description Output mode 0 = parallel output 1 = serial output Disable data buffer 0 = default 1 = disable data output buffer Disable clock buffer 0 = default 1 = disable clock output buffer Set to 0 Serial CLKOUT mode 0 = half rate serial clock 1 = full rate serial clock Data Sheet ADN2855 THEORY OF OPERATION The ADN2855 is designed specifically for burst mode data recovery in GPON/BPON/GEPON optical line terminal (OLT) receivers. The ADN2855 requires a reference clock that is frequency locked to the incoming data. The FLL (frequency-locked loop) of the ADN2855 acquires frequency lock with respect to this reference clock, pulling the VCO towards 0 ppm frequency error. It is assumed that the upstream bursts to the OLT are clocked by the recovered clock from the optical network terminal (ONT) CDR. This guarantees frequency lock to the OLT system clock. The ADN2855 has a preamble detector that looks for a maximum transition density pattern (1010...) within the preamble. Once this pattern is detected in the preamble, the on-chip delay/phaselocked loop (D/PLL) quickly acquires phase lock to the incoming burst within 12 UI of the 1010... pattern. The D/PLL also pulls in any remaining frequency error that was not pulled in by the FLL. The incoming data is retimed by the recovered clock and output either serially or in a 4-bit parallel output nibble. The ADN2855 requires a RESET signal between bursts to set the device into a fast phase acquisition mode. The RESET signal must be asserted within 8 UI of the end of the previous burst, and it must be deasserted prior to the start of the maximum transition density portion of the preamble, which is specifically provided for the burst mode clock recovery device to acquire the phase of the incoming burst. The RESET signal must be at least 16 UI wide. See the Reset Timing Options section for more details. Rev. B | Page 11 of 20 ADN2855 Data Sheet FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION I2C INTERFACE The ADN2855 operates in burst data recovery mode, which requires the use of the OLT system reference clock as an acquisition aid. The ADN2855 acquires frequency with respect to this reference clock, which is frequency locked to the incoming burst of data from the ONT. The ADN2855 supports a 2-wire, I2C-compatible serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADN2855 has four possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address, SADDR[7] is factory programmed to 1. Bit 2 of the slave address, SADDR[2], is set by Pin 1. Bit 1 of the slave address, SADDR[1], is set by Pin 3. Slave Address Bits[6:3] are defaulted to all 0s. The slave address consists of the seven MSBs of an 8-bit word. The LSB of the word, SADDR[0], sets either a read or write operation (see Figure 10). Logic 1 corresponds to a read operation, and Logic 0 corresponds to a write operation. The ADN2855 must be placed in lock to reference clock mode by setting CTRLA[0] = 1. A frequency acquisition is then initiated by writing a 1 to 0 transition into CTRLB[5]. This must be done well before the ADN2855 is expected to lock to an incoming burst, preferably right after power-up and once there is a valid reference clock being supplied to the device. As long as the reference clock to the ADN2855 is always present, this frequency acquisition needs to take place only once. It does not need to be repeated between bursts of data in its normal operating mode. The initial frequency acquisition with respect to the reference clock takes ~10 ms. To lock to burst data, a RESET signal must be asserted following a previous burst (or at startup) according to the timing diagrams shown in the Reset Timing Options section. The RESET signal must be deasserted prior to the 1010... portion of the preamble. The ADN2855 uses a preamble detector that identifies the 1010... portion of the preamble and quickly acquires the phase of the incoming burst within 12 UI. The frequency loop requires a single external capacitor between Pin 14, CF2, and Pin 15, CF1. A 0.47 F 20%, X7R ceramic chip capacitor with <10 nA leakage current is recommended. Leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 F capacitor, ~3 V, by the insulation resistance of the capacitor. The insulation resistance of the 0.47 F capacitor should be greater than 300 M. DATAV Operation The ADN2855 has a data valid indicator that asserts when the ADN2855 acquires the phase of the maximum transition density portion of the preamble. This takes 12 UI from the start of the 1010... pattern in the preamble. The DATAV output remains asserted until the RESET signal is asserted following the end of the current burst of data, at which point the DATAV output deasserts. The DATAV output is active low and is LVTTL compatible. SQUELCH MODE When the squelch input, Pin 30, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the squelch function is not required, Pin 30 should be tied to VEE. If it is desired that the DATxP/DATxN and CLKOUTP/ CLKOUN outputs be squelched while the output data is invalid, then the DATAV pin can be hardwired directly to the SQUELCH input. To control the device on the bus, use the following protocol. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2855 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/W bit. The ADN2855 has six subaddresses to enable the user-accessible internal registers (see Table 7 through Table 11). It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCK high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADN2855 does not issue an acknowledge, and returns to the idle condition. If the Rev. B | Page 12 of 20 Data Sheet ADN2855 user exceeds the highest subaddress while reading back in autoincrement mode, then the highest subaddress register contents continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. In a noacknowledge condition, the SDATA line is not pulled low on the ninth pulse. See Figure 11 and Figure 12 for sample write and read data transfers and Figure 13 for a more detailed timing diagram. REFERENCE CLOCK Using the Reference Clock to Lock onto Data In this mode, the ADN2855 locks onto a frequency derived from the reference clock according to the following equation: Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The reference clock can be anywhere between 10 MHz and 200 MHz. By default, the ADN2855 expects a reference clock of between 10 MHz and 25 MHz. If it is between 25 MHz and 50 MHz, 50 MHz and 100 MHz, or 100 MHz and 200 MHz, the user needs to configure the ADN2855 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. A reference clock is required to perform burst mode clock and data recovery with the ADN2855. The reference clock must be frequency locked to the incoming burst data. It is assumed that the incoming burst data from the ONT is timed by a clock recovered from the downstream data from the OLT and, therefore, is inherently frequency clocked to the OLT system clock. The reference clock can be driven differentially or single-ended. See Figure 15 and Figure 16 for sample configurations. Bit No. CTRLA[7:6] The REFCLK input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical. CTRLA[5:2] Table 12. CTRLA Settings REFCLKP 10 BUFFER 11 100k 100k VCC/2 06660-013 REFCLKN The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF ratio, where DIV_FREF represents the divided-down reference referred to the 10 MHz to 25 MHz band. For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mbps, then CTRLA[7:6] should be set to 01 to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] should be set to 0101, that is, 5, because Figure 15. Differential REFCLK Configuration VCC REFCLKP 10 REFCLKN BUFFER 11 100k 100k VCC/2 06660-014 CLK OSC OUT Description FREF range 00 = 10 MHz to 25 MHz 01 = 25 MHz to 50 MHz 10 = 50 MHz to 100 MHz 11 = 100 MHz to 200 MHz Data rate/DIV_FREF ratio 0000 = 1 0001 = 2 ... n = 2n ... 1000 = 256 622.08 Mbps/19.44 MHz = 25 Figure 16. Single-Ended REFCLK Configuration The ADN2855 must be operated in lock to reference clock mode when in burst data recovery mode. Lock to reference clock mode is enabled by writing a 1 to I2C Control Register CTRLA, Bit 0. A frequency acquisition in this mode must be initiated by writing a 1 to 0 transition to CTRLB[5]. While the ADN2855 is operating in lock to reference clock mode, if the user ever changes the reference frequency, the FREF range (CTRLA[7:6]), or the data rate/DIV_FREF ratio (CTRLA[5:2]), this must be followed by writing a 0 to 1 transition into the CTRLB[5] bit to initiate a new frequency acquisition. Rev. B | Page 13 of 20 ADN2855 Data Sheet OUTPUT MODES When the ADN2855 is in serial output mode (deserializer off), CTRLD[7] = 1, the default is for a half rate output clock where the data switches on both falling and rising edges of the output clock. Setting CTRLD[0] = 1 sets the serial clock output into full rate mode so that the output data switches only on the rising edges of the output clock. Parallel or Serial Output Mode The output of the ADN2855 can be configured in a 4-bit parallel output nibble mode, or it can be configured in a serial output mode. The default mode of operation is for the Rx data to be deserialized and output in a 4-bit nibble, present at DATxP/DATxN, where the earliest bit is present on DAT3P/DAT3N. Setting Bit CTRLC[5] = 1 reverses the order of the DATxP/DATxN bus such that the earliest bit is present on DAT0P/DAT0N. RxCLK Phase Adjust Setting bit CTRLD[7] = 1 puts the device into serial output mode. In this mode, the Rx data is present on DAT0P/DAT0N. Double Data Rate Mode The default output mode for the ADN2855 is for a 4-bit deserialized output with a full rate output clock, where the output data switches on the rising edge of the output clock. When the ADN2855 is programmed to be in parallel output mode (CTRLD[7] = 0), setting CTRLC[4] = 1 puts the ADN2855 clock output through divide-by-two circuitry, allowing direct interfacing to FPGAs that support data clocking on both rising and falling edges. The ADN2855 provides the option of adjusting the phase of the output clock with respect to the parallel output data. In parallel mode, the duration of each bit is 4 UI wide, due to the deserialization. There are three additional phase adjust options other than the baseline (that is, CLK edge in the center of the data eye): +2 UI, +0.5 UI, and -1.5 UI. The output clock phase adjustment feature is accessed via CTRLC[3:2]. See Table 10 for details. DISABLE OUTPUT BUFFERS The ADN2855 provides the option of disabling the output buffers for power savings. The clock output buffers can be disabled by setting CTRLD[5] = 1. For additional power savings (for example, in a low power standby mode), the data output buffers can also be disabled by setting CTRLD[6] = 1. Rev. B | Page 14 of 20 Data Sheet ADN2855 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2855 VCC pins. Proper RF PCB design techniques must be used for optimal performance. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance. Refer to the schematic in Figure 17 for recommended connections. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance. The exposed pad should be connected to the GND plane using plugged vias so that solder does not leak through the vias during reflow. By using adjacent power supply and GND planes, excellent high frequency decoupling can be realized by using close spacing between the planes. This capacitance is given by C PLANE [pf ] = 0.88 r A/d where: r is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). Use of a 10 F electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they For FR-4, r = 4.4 mm and 0.25 mm spacing, CPLANE 15 pF/cm2. VCC OLT SYSTEM CLOCK VCC 1nF 0.47F REFCLKP, REFCLKN CF1 CF2 VEE VCC 0.1F LOOP FILTER PHASE DET LOOP FILTER VCC RESET PIN LAOUTP PIN NIN LAOUTN NIN PHASE SHIFTER CML INPUT BUFFER VCO ADN2855 SQUELCH DATA RETIMING 2 SQUELCH 4x2 DATxP, DATxN OLT MAC Figure 17. Typical Application Circuit Rev. B | Page 15 of 20 I2C DIVIDER 2 2 CLKOUTP, CLKOUTPN 06660-015 DESERIALIZER SDA SADDR[2:1] RESET FREQ, LOCK DET DATAV VCC VEE VPD SCK 0.1F 0.1F ADN2855 Data Sheet Transmission Lines Soldering Guidelines for Chip Scale Package Use of 50 transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATxP, DATxN (also REFCLKP and REFCLKN if a high frequency reference clock is used, such as 155.52 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP/CLKOUTN and DATxP/DATxN output traces to be matched in length to avoid skew between the differential traces. All high speed LVDS outputs, CLKOUTP/CLKOUTN and DATxP/DATxN, require a 100 differential termination at the differential input to the device being driven by the ADN2855 outputs. The lands on the 32-lead LFCSP are rectangular. The PCB pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad to ensure that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the PCB should be at least as large as this exposed pad. The user must connect the exposed pad to VEE (GND) using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. The high speed inputs, PIN and NIN, are internally terminated with 50 to an internal reference voltage. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. Rev. B | Page 16 of 20 Data Sheet ADN2855 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 1 24 0.50 BSC 3.40 3.30 SQ 3.20 EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 END VIEW PKG-003530 SEATING PLANE 0.45 0.40 0.35 9 16 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF BOTTOM VIEW 0.25 MIN 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 03-17-2017-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-32-20) Dimensions shown in millimeters ORDERING GUIDE Model1 ADN2855ACPZ ADN2855ACPZ-R7 ADN2855-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 17 of 20 Package Option CP-32-20 CP-32-20 ADN2855 Data Sheet NOTES Rev. B | Page 18 of 20 Data Sheet ADN2855 NOTES Rev. B | Page 19 of 20 ADN2855 Data Sheet NOTES (c)2009-2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06660-0-4/17(B) Rev. B | Page 20 of 20