Preliminary Datasheet January 2015 AQR405 10GBASE-T Ethernet PHY Transceiver General Description The AQR405 is a complete quad port low-power, full-reach, AQRateTM, five-speed 10GBASE-T / 5G / 2.5G / 1000BASE-T / 100BASE-TX PHY transceiver. The device performs all the physical layer functions required to implement AQRateTM and 10GBASE-T / 1000BASE-T / 100BASE-TX transmission over 100+m of twisted pair cabling. Features Benefits * High-Density 25mm Quad, Pin + Software Compatible with AQ1402 * Full-spec 10GBASE-T performance o 100m on Augmented Cat 6 (Cat 6A) and Cat 7 o 55m on Cat 6 and best-effort on Cat 5e * AQRateTM Adaptive Rate Operation o Standard 130m 1000Base-T and 100Base-TX operation * 2.9 W full-reach typical operating power per port o 2.4 W short-reach (IEEE 30m mode) typical operating power o 1.9 W data-center (10m) mode typical operating power * Integrated MACsec, 1588, and EEE support o Full support for AES-256 and stand-alone operation * Enables refresh of legacy switches without spinning ASICs * Integrated Wake-On-LAN Support o Compliant to Microsoft Network Device Class specification * Integrated packet filtering allows sub-1W support in 100BASE-TX mode * Built-in thermal management capabilities o On-die thermal sensor with alarm and warning thresholds * Enables deployment in thermally constrained environments * 25 x 25 mm flip-chip 576-ball BGA package o 1mm ball pitch o Low thermal resistance ( ) jc * * Low cost Flexible heat-sinking Compatible with volume PCB manufacturing * Interoperability with existing Ethernet infrastructure Reduces BOM cost as one or no FLASH devices required Enables firmware download/upgrade and FLASH image loading during manufacturing (R) Allows seamless upgrade of existing designs to the latest low-power technology en tia l * Ability to support worst case channels while reducing power and latency when channel characteristics permit * Super-speed (5G and 2.5G) operation over legacy infrastructure, plus full inter-operability with existing equipment * Enables high-density 10GBASE-T switching applications Co nfi d * * IEEE 802.3an-2008 compliant autonegotiation * External SPI FLASH interface with optional FLASH-less operation o At-manufacture FLASH burn capability o Daisy-chain mode allows a single FLASH for multiple devices * * 50 MHz Differential Clock Operation o Integrated ultra-low phase noise synthesizer * Outputs primary and secondary 50 MHz received reference for synchronous Ethernet * Advanced Cable Diagnostics o On-chip high-resolution cable analyzer * Enables the deployment of meaningful cable analysis tools for debugging installation problems * High-Performance full KR (with autonegotiation) / XFI / USXGMII / RXAUI / 2500BASE-X / SGMII I/F w/ AC-JTAG o 2nd KR / SGMII interface for optical dual-media capability * Ensures trouble-free operation over a range of interconnect scenarios * Advance Loopback and Diagnostic Capability o Flexible on-chip BERT o Supports numerous loopbacks o Full 1 second packet counters and CRC-32 checkers * Enables extensive system test and debug with remote loopback control * Integrated MDI Filter and Advanced RFI Cancellation o Eliminates external filter components * Patented RFI technology provides error-free performance in the presence of RF interference Str i ctl y * * Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 AQR405 10GBASE-T Ethernet PHY Transceiver Preliminary Datasheet January 2015 Detailed Description A block diagram of the AQR405 is shown in Figure 1. Each port utilizes a common analog front-end for all 5 modes AQRate 25mm Quad Lookaside P[3:0]_TX_LN2_P,N P[3:0]_RX_LN2_P,N SRDS2 10G MDIO 2.5G PCS SGMII PCS 0 1G PCS SGMII PCS 1 100M PCS MDIO Registers MACSEC SMB_DAT SMB_CLK THP A/D THP THP Precoder Precoder Precoder VGA & THP THP THP Filter Precoder Precoder Precoder VGA & Filter RAM PController JTAG JTAG FLASH / Daisy Chain Timing 50 MHz Timing Power Supply P[3:0]_LED[2:0] COMMON VDD VA12 P[3:0]_VA22 AVSS/VSS Bandgap VDD_SENSE TDIO_N[3,0] Thermal Diodes TDIO_P[3,0] TX_DC_DATA TX_DC_CLK TX_DC_SOF TX_DC_RST_N Daisy-Chain I/F RX_DC_DATA RX_DC_CLK RX_DC_SOF RX_DC_RST_N SCLK SIN SOUT CE_N Co nfi d Boot Loader Serial FLASH I/F CLK_N Config Control P[3:0]_CM_P,N LED LED I/F DC_MASTER_N RST_OUT_N P[3:0]_[D:A]_P,N REPLICATED FOUR TIMES Autonegotiation P[3:0]_PRST* RST_N ADDR[4:2] INV_ADDR[1:0] THP Hybrid THP THP Precoder Precoder Precoder CLK_1588_P,N 1588_SYNC CLKO_50M_A,B P[3:0]_WAKE DAC / THP THP THP Driver Precoder Precoder Precoder A/D CLK_P WoL KR/USXGMII PCS 1 TDI TDO TCK TMS TRST_N SMBus MDIO Management 5G PCS RREF_BG[3:0] P[3:0]_MDC P[3:0]_MDIO P[3:0]_INT_N KR/USXGMII PCS 0 DSP SRDS0 10G LINE 10G PCS en tia l P[3:0]_TX_LN0_P,N P[3:0]_RX_LN0_P,N SERDES System I/F XAUI/RXAUI PCS Power Figure 1 AQR405 block diagram Str ict ly of operation, and a common system interface (configurable as dual KR, RXAUI in 10G, 2500BASE-X in 2.5G, and dual SGMII in 1G / 100M, or all rates via USXGMII). In the transmit direction in 10G, 5G, and 2.5G modes, data from the system interface is equalized and received. This data is then mapped into a virtual internal XGMII interface where blocks of two XGMII frames (32 bits of data + 4 bits of control) are encoded into a single 65B block, using the 64B/65B encoding scheme specified in Clause 55. In 10G mode, fifty of these 65B blocks are aggregated together, along with a prepended auxiliary bit, and an appended CRC-8 to form the 3259-bit 10GBASE-T transmission frame payload. This payload is encoded using a combination of LDPC encoding and coset partitioning, with the LDPC encoding adding an additional 325 systematic check bits to produce a 3584-bit 10GBASE-T transmission frame. The coset partitioning effectively divides the frame up into 512 7-bit symbols, where the upper 3 bits are uncoded and describe the coset, while the lower 4 bits are coded and identify an element within the coset. These 8 cosets are then mapped onto a 128-DSQ constellation (a 16 x 16 checkerboard pattern) which is physically encoded as two back-to-back PAM-16 symbols. These symbols are then THP precoded, filtered, and sent out over the four twisted pairs in the cable. AQRate 5G transmission is done in a similar fashion, but uses a fully LDPC encoded 320 ns PAM-16 frame containing twenty-five 65B blocks. AQRate 2.5G transmission is also similar, but uses a 640 ns frame containing twenty-five 65B blocks. In the receive direction in 10G, 5G, and 2.5G modes, PAM-16 coded symbols enter the AQR405 from the line interface and pass through the hybrid, which provides transmit / receive isolation. These symbols are then filtered and amplified prior to being sampled by four high-speed, high-precision A/D converters. The outputs of these A/D converters are then passed through an extensive set of adaptive equalizers which provide both cross-talk and echo cancellation. After timing is recovered, the data from the four channels is aligned and merged together to form the . The line facing (Lookaside/Dual Media mode) SERDES lanes are shown in grey. The inactive PCS block items (i.e. XAUI) are shown in grey. Strictly Confidential ii AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. AQR405 10GBASE-T Ethernet PHY Transceiver Preliminary Datasheet January 2015 original, but noisy transmission frames. In all three modes, the data is decoded using an LDPC decoder. However, in 10G mode the data is further sliced using knowledge of the coset partitioning and 128-DSQ mapping to produce the original 10GBASE-T transmission frame payload. The CRC-8 over this payload is then checked to ensure integrity of the uncoded bits. Finally, in all schemes, the auxiliary bit is stripped, the 65B blocks remapped into XGMII blocks, and the received Ethernet data transmitted out the MAC interface. When operating in 1G or 100M modes, receive data from the analog front-end is routed to either the 1G or 100M PCS where timing is recovered and equalization performed. In 1G mode, Viterbi decoding is also done. From here, the data passes across a virtual GMII interface to the system interface which is either SGMII, or USXGMII mode on logical Lane 0. In the transmit direction, 1G or 100M data is received on either the SGMII, or USXGMII interface, passed through the 1G or 100M PCS and then transmitted by the common analog front-end. Figure 2 shows a typical system-level block diagram of a 10GBASE-T channel with an optional dual-media KR Line AQ R4 05 Str ict ly FLASH Daisy Chain MAC I/F MAC MDIO & Control Line PHY Slice Common XFMR Line SFP+ RJ-45 SPI Power Supply z H M 0 5 Serial FLASH Figure 2 AQR405 system block interconnect interface built using the AQR405. On the line side of the AQR405, a robust interface providing good common-mode rejection and electrical protection against cable discharge is implemented. On the MAC side, the AQR405 provides a robust SERDES interface with configurable pre-emphasis and receive equalization. For test coverage, this interface also incorporates AC JTAG. Control over the chip is done via an external C-language application program interface (API) which provides an easy-to-use abstraction of the AQR405, and via an MDIO interface which provides the standard Clause 45 register set for control of 10GBASE-T devices. On-chip, the AQR405 contains a 32-bit microcontroller which manages the state machines and operation of the various elements within the chip. Consequently, there is a great deal of flexibility afforded to the end user because of the presence of this microcontroller, and as such the AQR405 offers a high degree of control and flexibility. The image for the microcontroller is stored either in an optional external SPI FLASH (which can be daisy-chained over multiple devices), or loaded at boot time via the MDIO interface (MDIO boot-load). This interface also provides the user the capability of directly programming the FLASH during manufacturing. In addition to the Ethernet interfaces, the AQR405 provides three 20 mA LED outputs per port which are configurable via software to respond to a variety of conditions such as link activity and connection status. Clocking for the AQR405 is provided from a 50 MHz differential clock. Power for the AQR405 is provided from three supply voltages, with configurable I/O voltage levels. In order to assist the system designer in deploying the AQR405, a reference design (part numbers, schematics, and layout) is provided which is optimized for performance, efficiency and cost. Strictly Confidential Aquantia Corp. AQR405 Revision 0.11 - January 5, 2015 iii AQR405 10GBASE-T Ethernet PHY Transceiver Preliminary Datasheet January 2015 Package Information ctl yC on fid e nti al The AQR405 is packaged in a 25 x 25 mm flip-chip BGA with 576 balls (24 rows x 24 columns). The package is marked as follows: Release Notes Figure 3 Part marking The AQR405 Release Notes must be consulted for a full list of known issues and errata associated with AQR405. Ordering Information Part Number Silicon Rev. B1 10GBASE-T PHY RoHS 6/6 Matte Tin Balls Str i AQR405 Description Ordering Part Number 1 AQR405-B1-EG-Y 1. Lead-free bump and lead-free BGA balls IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc. For additional information, contact your Aquantia Account Manager or the following: INTERNET: Home: http://www.aquantia.com E-MAIL: sales@aquantia.com ADDRESS: Aquantia Corp., 700 Tasman Drive, Milpitas, CA 95035 408-228-8300, FAX 408-228-1190 PROPRIETARY AND CONFIDENTIAL: All of the information included herein, as well as any oral or written discussions regarding such information and any materials generated as a result of such discussions, is confidential information that is proprietary to Aquantia Corporation and should be used by its recipient solely as authorized by Aquantia Corporation under written non-disclosure agreement. Aquantia Corp. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Aquantia is a registered trademark of Aquantia Corp. Aquantia and the Aquantia logo are trademarks of Aquantia Corp. Consult the current Release Notes for the AQR405 to obtain a list of all currently known issues and errata associated with the AQR405. Copyright (c) 2015 Aquantia Corp. All Rights Reserved Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General Deployment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 en tia l Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERDES Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Co nfi d SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cable Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-On-LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug and Diagnostics Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . API & Programming Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MACsec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 2 2 2 2 3 3 4 4 4 5 6 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Ingress Lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 MACsec Ingress Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Egress Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Str ict ly Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Precision Time Protocol (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 Hardware Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI FLASH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Daisy-chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Boot-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Provisionable Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Gang-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 v Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SERDES Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SERDES System I/F Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 en tia l 10G Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 1000BASE-X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 XSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 USXGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 All-Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 XSGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 USXGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Str ict ly Co nfi d MDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Metrology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wake-On-LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 46 47 47 49 49 50 50 52 55 56 3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXAUI Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXAUI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGMII Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 59 60 60 61 62 63 64 64 65 Table of Contents Section Page en tia l SGMII Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KR Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KR Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500BASE-X Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2500BASE-X Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 66 66 67 67 68 Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Co nfi d Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Full-Reach Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Full-Reach VA22 and VA12 Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Full-Reach VDD Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Other Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 VDD_IO and VDD_FLASH Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Str ict ly Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line (MDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 77 78 79 79 80 Input Clock Pins CLK_P and CLK_N - LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Input Clock Pins CLK_1588_P and CLK_1588_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Reference Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 vii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Theta J's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 en tia l Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Format and Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMA Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 88 88 89 91 93 Str ict ly Co nfi d PMA Standard Control 1: Address 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMA Standard Status 1: Address 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PMA Standard Device Identifier 1: Address 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PMA Standard Device Identifier 2: Address 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PMA Standard Speed Ability: Address 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PMA Standard Devices in Package 1: Address 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PMA Standard Devices in Package 2: Address 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PMA Standard Control 2: Address 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PMA Standard Status 2: Address 1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PMD Standard Transmit Disable Control: Address 1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PMD Standard Signal Detect: Address 1.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PMD Standard 10G Extended Ability Register: Address 1.B . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PMA Standard Package Identifier 1: Address 1.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PMA Standard Package Identifier 2: Address 1.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PMA 10GBASE-T Status: Address 1.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 . . . . . . . . . . . . . . . . . . . . . . . . 104 PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 . . . . . . . . . . . . . 105 PMA 10GBASE-T Test Modes: Address 1.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85 . . . . . . . . . . . . . . . . . . . . 107 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86 . . . . . . . . . . . . . . . . . . . . 107 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 . . . . . . . . . . . . . . . . . . . . 108 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 . . . . . . . . . . . . . . . . . . . . 108 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 . . . . . . . . . . . . . 109 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A . . . . . . . . . . . . 109 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B . . . . . . . . . . . . 110 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C . . . . . . . . . . . . 110 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D . . . . . . . . . . . . . . . . . . . . . 111 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E . . . . . . . . . . . . . . . . . . . . . 111 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F . . . . . . . . . . . . . . . . . . . . . 111 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 . . . . . . . . . . . . . . . . . . . . . 112 PMA 10GBASE-T Skew Delay 1: Address 1.91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PMA 10GBASE-T Skew Delay 2: Address 1.92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 PMA 10GBASE-T Fast Retrain Status and Control: Address 1.93 . . . . . . . . . . . . . . . . . . . . . . 114 TimeSync PMA Capability: Address 1.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 . . . . . . . . . . . . . . . . . . . . . . . . . 115 TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 . . . . . . . . . . . . . . . . . . . . . . . . . 115 TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 . . . . . . . . . . . . . . . . . . . . . . . . . 116 viii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 1: Address 1.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 2: Address 1.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 3: Address 1.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 4: Address 1.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Control: Address 1.8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 . . . . . . . . . . . . . . . . . . XENPAK Header - NVR Size 1: Address 1.8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - NVR Size 2: Address 1.8009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Memory Used 1: Address 1.800A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Memory Used 2: Address 1.800B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Basic Memory Start Address: Address 1.800C . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Customer Memory Offset: Address 1.800D . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Vendor Memory Start Address: Address 1.800E . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F . . . . . . . . . . . . . . . . . XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x11: Address 1.8011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Transceiver Type: Address 1.8012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Connector Type: Address 1.8013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Encoding: Address 1.8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Bit Rate 0: Address 1.8015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Bit Rate 1: Address 1.8016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Protocol: Address 1.8017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Standards Compliance Codes: Address 1.8018 . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 1: Address 1.8019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 2: Address 1.801A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 3: Address 1.801B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 4: Address 1.801C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 5: Address 1.801D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 6: Address 1.801E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 7: Address 1.801F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 8: Address 1.8020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 9: Address 1.8021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 10: Address 1.8022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 11: Address 1.8023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 12: Address 1.8024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 13: Address 1.8025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 14: Address 1.8026 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 15: Address 1.8027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 16: Address 1.8028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 17: Address 1.8029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 18: Address 1.802A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 19: Address 1.802B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 20: Address 1.802C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 21: Address 1.802D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 22: Address 1.802E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 23: Address 1.802F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 24: Address 1.8030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x19 25: Address 1.8031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Package Identifier 1: Address 1.8032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Package Identifier 2: Address 1.8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Package Identifier 3: Address 1.8034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Package Identifier 4: Address 1.8035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 116 116 117 117 117 118 119 119 119 120 120 120 121 121 121 122 122 122 123 123 124 124 124 125 125 125 126 126 126 127 127 127 128 128 128 129 129 129 130 130 130 131 131 131 132 132 132 133 133 133 133 134 134 Table of Contents Section Page Str ict ly Co nfi d en tia l XENPAK Basic - Vendor Identifier 1: Address 1.8036 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 XENPAK Basic - Vendor Identifier 2: Address 1.8037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Identifier 3: Address 1.8038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Identifier 4: Address 1.8039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Name 1: Address 1.803A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Name 2: Address 1.803B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 XENPAK Basic - Vendor Name 3: Address 1.803C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 XENPAK Basic - Vendor Name 4: Address 1.803D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 XENPAK Basic - Vendor Name 5: Address 1.803E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 XENPAK Basic - Vendor Name 6: Address 1.803F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 XENPAK Basic - Vendor Name 7: Address 1.8040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 XENPAK Basic - Vendor Name 8: Address 1.8041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 XENPAK Basic - Vendor Name 9: Address 1.8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 XENPAK Basic - Vendor Name 10: Address 1.8043 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 XENPAK Basic - Vendor Name 11: Address 1.8044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 XENPAK Basic - Vendor Name 12: Address 1.8045 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 XENPAK Basic - Vendor Name 13: Address 1.8046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 XENPAK Basic - Vendor Name 14: Address 1.8047 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 XENPAK Basic - Vendor Name 15: Address 1.8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 XENPAK Basic - Vendor Name 16: Address 1.8049 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 XENPAK Basic - Vendor Part Number 1: Address 1.804A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 XENPAK Basic - Vendor Part Number 2: Address 1.804B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 XENPAK Basic - Vendor Part Number 3: Address 1.804C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 XENPAK Basic - Vendor Part Number 4: Address 1.804D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 XENPAK Basic - Vendor Part Number 5: Address 1.804E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 XENPAK Basic - Vendor Part Number 6: Address 1.804F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 XENPAK Basic - Vendor Part Number 7: Address 1.8050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 XENPAK Basic - Vendor Part Number 8: Address 1.8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 XENPAK Basic - Vendor Part Number 9: Address 1.8052 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 XENPAK Basic - Vendor Part Number 10: Address 1.8053 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 XENPAK Basic - Vendor Part Number 11: Address 1.8054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 XENPAK Basic - Vendor Part Number 12: Address 1.8055 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 XENPAK Basic - Vendor Part Number 13: Address 1.8056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 XENPAK Basic - Vendor Part Number 14: Address 1.8057 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 XENPAK Basic - Vendor Part Number 15: Address 1.8058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 XENPAK Basic - Vendor Part Number 16: Address 1.8059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A . . . . . . . . . . . . . . . . . . . . . 146 XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B . . . . . . . . . . . . . . . . . . . . . 146 XENPAK Basic - Vendor Serial Number 1: Address 1.805C . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 XENPAK Basic - Vendor Serial Number 2: Address 1.805D . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 XENPAK Basic - Vendor Serial Number 3: Address 1.805E . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 XENPAK Basic - Vendor Serial Number 4: Address 1.805F . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 XENPAK Basic - Vendor Serial Number 5: Address 1.8060 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 XENPAK Basic - Vendor Serial Number 6: Address 1.8061 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 XENPAK Basic - Vendor Serial Number 7: Address 1.8062 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 XENPAK Basic - Vendor Serial Number 8: Address 1.8063 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 XENPAK Basic - Vendor Serial Number 9: Address 1.8064 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 XENPAK Basic - Vendor Serial Number 10: Address 1.8065 . . . . . . . . . . . . . . . . . . . . . . . . . . 150 XENPAK Basic - Vendor Serial Number 11: Address 1.8066 . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 XENPAK Basic - Vendor Serial Number 12: Address 1.8067 . . . . . . . . . . . . . . . . . . . . . . . . . . 150 XENPAK Basic - Vendor Serial Number 13: Address 1.8068 . . . . . . . . . . . . . . . . . . . . . . . . . . 151 XENPAK Basic - Vendor Serial Number 14: Address 1.8069 . . . . . . . . . . . . . . . . . . . . . . . . . . 151 XENPAK Basic - Vendor Serial Number 15: Address 1.806A . . . . . . . . . . . . . . . . . . . . . . . . . . 151 x Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l XENPAK Basic - Vendor Serial Number 16: Address 1.806B . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 1: Address 1.806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 2: Address 1.806D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 3: Address 1.806E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 4: Address 1.806F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 5: Address 1.8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 6: Address 1.8071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 7: Address 1.8072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 8: Address 1.8073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 9: Address 1.8074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Date Code 10: Address 1.8075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - 5V Loading: Address 1.8076 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - 3.3V Loading: Address 1.8077 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - APS Loading: Address 1.8078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - APS Voltage: Address 1.8079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - DOM Capability: Address 1.807A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Low-Power Startup Capability: Address 1.807B . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x7C: Address 1.807C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Checksum: Address 1.807D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 1: Address 1.807E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 2: Address 1.807F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 3: Address 1.8080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 4: Address 1.8081 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 5: Address 1.8082 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 6: Address 1.8083 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 7: Address 1.8084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 8: Address 1.8085 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 9: Address 1.8086 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 10: Address 1.8087 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 11: Address 1.8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 12: Address 1.8089 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 13: Address 1.808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 14: Address 1.808B . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 15: Address 1.808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 16: Address 1.808D . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 17: Address 1.808E . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 18: Address 1.808F . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 19: Address 1.8090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 20: Address 1.8091 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 21: Address 1.8092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 22: Address 1.8093 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 23: Address 1.8094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 24: Address 1.8095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 25: Address 1.8096 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 26: Address 1.8097 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 27: Address 1.8098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 28: Address 1.8099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 29: Address 1.809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 30: Address 1.809B . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 31: Address 1.809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 32: Address 1.809D . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 33: Address 1.809E . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 34: Address 1.809F . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 152 152 152 153 153 153 153 154 154 154 155 155 156 156 157 157 158 158 158 159 159 159 160 160 160 161 161 161 162 162 162 163 163 163 164 164 164 165 165 165 166 166 166 167 167 167 168 168 168 169 169 169 170 Table of Contents Section Page Str ict ly Co nfi d en tia l XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 XENPAK Customer - Reserved 0x7E 45: Address 1.80AA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 XENPAK Customer - Reserved 0x7E 46: Address 1.80AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 XENPAK Customer - Reserved 0x7E 47: Address 1.80AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 XENPAK Customer - Reserved 0x7E 48: Address 1.80AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 19: Address 1.80C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 20: Address 1.80C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 21: Address 1.80C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 xii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Rx_Alarm - Control: Address 1.9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Tx_Alarm - Control: Address 1.9001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK LASI - Control: Address 1.9002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 188 188 188 189 189 189 190 190 190 191 191 191 192 192 192 193 193 193 194 194 194 195 195 195 196 196 196 197 197 197 198 198 198 199 199 199 200 200 200 201 201 201 202 202 202 203 203 203 204 204 204 205 206 Table of Contents Section Page Str ict ly Co nfi d en tia l XENPAK Rx_Alarm - Status: Address 1.9003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 XENPAK Tx_Alarm - Status: Address 1.9004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 XENPAK LASI - Status: Address 1.9005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 XENPAK DOM - Tx Control: Address 1.9006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 . . . . . . . . . . . . . . 210 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 . . . . . . . . . . . . . . 211 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002 . . . . . . . . . . . . . . . 211 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 . . . . . . . . . . . . . . 212 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 . . . . . . . . . . . . 212 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 . . . . . . . . . . . . 213 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006 . . . . . . . . . . . . . 213 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 . . . . . . . . . . . . 214 XENPAK DOM - Temperature LSW: Address 1.A060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 XENPAK DOM - Temperature MSW: Address 1.A061 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Status: Address 1.A06E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Capability: Address 1.A06F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Alarms 1: Address 1.A070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 XENPAK DOM - Alarms 2: Address 1.A071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 XENPAK DOM - Alarms 3: Address 1.A072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Alarms 4: Address 1.A073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Alarms 5: Address 1.A074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 . . . 218 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412 . . . . . . . . . . . . . . . . . . . . . . 218 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413 . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 1: Address 1.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 2: Address 1.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 3: Address 1.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 PMA Transmit Standard Interrupt Mask 1: Address 1.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 PMA Transmit Standard Interrupt Mask 2: Address 1.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400 . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401 . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402 . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor Debug 1: Address 1.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 . . . . . . . . . . . . . . . . . . . . . . . 222 PMA Receive Vendor State 1: Address 1.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 PMA Receive Reserved Vendor State 1: Address 1.E810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 PMA Receive Reserved Vendor State 2: Address 1.E811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PMA Vendor Global Interrupt Flags 1: Address 1.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PCS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 PCS Standard Control 1: Address 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 PCS Standard Status 1: Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 PCS Standard Device Identifier 1: Address 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 PCS Standard Device Identifier 2: Address 3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 PCS Standard Speed Ability: Address 3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 PCS Standard Devices in Package 1: Address 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 PCS Standard Devices in Package 2: Address 3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 PCS Standard Control 2: Address 3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 PCS Standard Status 2: Address 3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 PCS Standard Package Identifier 1: Address 3.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 PCS Standard Package Identifier 2: Address 3.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 PCS EEE Capability Register : Address 3.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 xiv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l PCS 10G Status 1: Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10G Status 2: Address 3.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Capability: Address 3.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 1: Address 3.1801 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 2: Address 3.1802 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 3: Address 3.1803 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 4: Address 3.1804 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 1: Address 3.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 2: Address 3.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 3: Address 3.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 4: Address 3.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Provisioning 1: Address 3.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Provisioning 2: Address 3.C401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410 . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 1: Address 3.C455 . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 2: Address 3.C456 . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 3: Address 3.C457 . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 4: Address 3.C458 . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 5: Address 3.C459 . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Memory Control Register: Address 3.C4C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Control Register 1: Address 3.C4C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Local fault Control Register: Address 3.C4C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 MAC Local fault Control Register: Address 3.C4C3 . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Auto-Neg Control Register: Address 3.C4C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 PTP Control Register: Address 3.C4C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 PKT Info Message Register-0: Address 3.C4C6 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 PKT Info Message Register-1: Address 3.C4C7 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 PKT Info Message Register-2: Address 3.C4C8 . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 link Fill Data Register-0: Address 3.C4C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 link Fill Data Register-1: Address 3.C4CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Link FIFO Control Register: Address 3.C4CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 TX FIFO Control Register: Address 3.C4CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Local Advertisement Register: Address 3.C4CD . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Memory Control Register: Address 3.C4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Control Register 1: Address 3.C4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Local fault Control Register: Address 3.C4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 236 237 237 238 238 238 239 239 239 240 240 241 241 242 242 243 243 243 244 244 244 245 245 245 246 246 246 247 247 247 248 248 248 249 250 250 252 252 253 254 254 255 256 256 256 257 257 257 258 259 260 260 262 Table of Contents Section Page Str ict ly Co nfi d en tia l PCS USX1 MAC Local fault Control Register: Address 3.C4E3 . . . . . . . . . . . . . . . . . . . . . . . . 262 PCS USX1 Auto-Neg Control Register: Address 3.C4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PCS USX1 PTP Control Register: Address 3.C4E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PCS USX1 PKT Info Message Register-0: Address 3.C4E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 PCS USX1 PKT Info Message Register-1: Address 3.C4E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 PKT Info Message Register-2: Address 3.C4E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 link Fill Data Register-0: Address 3.C4E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 link Fill Data Register-1: Address 3.C4EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PCS USX1 Link FIFO Control Register: Address 3.C4EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PCS USX1 TX FIFO Control Register: Address 3.C4EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 PCS USX1 Local Advertisement Register: Address 3.C4ED . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0 . . . . . . . . . . . . . . . . . . . . . . . . . . 269 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 . . . . . . . . . . . . . . . . . 270 PCS Transmit Vendor FCS No Error Frame Counter 2: Address 3.C821 . . . . . . . . . . . . . . . . . 270 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit XFI0 Vendor State 1: Address 3.C860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit XFI0 Vendor State 2: Address 3.C861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 PCS Transmit XFI0 Vendor State 3: Address 3.C862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 PCS Transmit XFI0 Vendor State 4: Address 3.C863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 PCS Transmit XFI1 Vendor State 1: Address 3.C870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 PCS Transmit XFI1 Vendor State 2: Address 3.C871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 PCS Transmit XFI1 Vendor State 3: Address 3.C872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 PCS Transmit XFI1 Vendor State 4: Address 3.C873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 PCS Transmit XGS Vendor State 1: Address 3.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 PCS Transmit XGS Vendor State 2: Address 3.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 PCS Transmit XGS Vendor State 3: Address 3.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 PCS Transmit XGS Vendor State 4: Address 3.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 PCS Transmit XGS Vendor State 5: Address 3.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 PCS USX0 Transmit Status : Address 3.C8C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 PCS Transmit Vendor System Interface State 1: Address 3.C8F0 . . . . . . . . . . . . . . . . . . . . . . 277 PCS PTP Vendor State 1: Address 3.C900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 PCS PTP Vendor State 2: Address 3.C901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PCS PTP Vendor State 3: Address 3.C902 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PCS PTP Vendor State 4: Address 3.C903 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 PCS PTP Vendor State 5: Address 3.C904 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 PCS PTP Vendor State 6: Address 3.C905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 PCS PTP Vendor State 7: Address 3.C906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 PCS PTP Vendor State 8: Address 3.C907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 PCS PTP Vendor State 9: Address 3.C908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 PCS PTP Vendor State 10: Address 3.C909 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 PCS PTP Vendor State 11: Address 3.C90A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 PCS PTP Vendor State 12: Address 3.C90B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 PCS PTP Vendor State 13: Address 3.C90C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 PCS PTP Vendor State 14: Address 3.C90D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 PCS PTP Vendor State 15: Address 3.C90E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 PCS PTP Vendor State 16: Address 3.C90F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 PCS PTP Vendor State 17: Address 3.C910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 PCS PTP Vendor State 18: Address 3.C911 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 PCS PTP Vendor State 19: Address 3.C912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 PCS PTP Vendor State 20: Address 3.C913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 PCS PTP Vendor State 21: Address 3.C914 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 xvi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l PCS PTP Vendor State 22: Address 3.C915 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 23: Address 3.C916 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 24: Address 3.C917 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 25: Address 3.C918 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 26: Address 3.C919 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 27: Address 3.C91A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 28: Address 3.C91B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 29: Address 3.C91C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 31: Address 3.C91E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 32: Address 3.C91F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 33: Address 3.C920 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 34: Address 3.C921 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 35: Address 3.C922 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 1: Address 3.C930 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 2: Address 3.C931 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 3: Address 3.C932 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 4: Address 3.C933 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 5: Address 3.C934 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 6: Address 3.C935 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Egress Vendor State 7: Address 3.C936 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Alarms 1: Address 3.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Alarms 2: Address 3.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Alarms 3: Address 3.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Alarms 4: Address 3.CC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Interrupt Mask 1: Address 3.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Interrupt Mask 2: Address 3.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Interrupt Mask 3: Address 3.D002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Debug 1: Address 3.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Provisioning 1: Address 3.E400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive XFI0 Provisioning 1: Address 3.E460 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive XFI0 Provisioning 2: Address 3.E461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive XFI1 Provisioning 1: Address 3.E470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive XFI1 Provisioning 2: Address 3.E471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 RX Control Register: Address 3.E4D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 RX FIFO Control Register: Address 3.E4D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 SM Control Register: Address 3.E4D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Link Timer Control Register: Address 3.E4D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 RX Fault Control Register: Address 3.E4D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 RX Control Register: Address 3.E4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 RX FIFO Control Register: Address 3.E4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 SM Control Register: Address 3.E4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Link Timer Control Register: Address 3.E4E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 RX Fault Control Register: Address 3.E4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 1: Address 3.E600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 284 285 285 285 286 286 286 287 287 287 288 288 288 289 289 289 290 290 291 291 291 292 293 293 293 294 295 296 296 297 297 297 298 299 299 300 301 301 302 303 304 305 305 306 307 307 308 309 309 311 312 313 313 Table of Contents Section Page Str ict ly Co nfi d en tia l PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 PCS Receive Vendor State 1: Address 3.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810 . . . . . . . . . . . . . . . . . . . . . . . . 332 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811 . . . . . . . . . . . . . . . . . . . . . . . . 333 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 . . . . . . . . . . . . . . . . . . 333 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 . . . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 . . . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 . . . . . . . . . . . . . . . . . . . 335 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 . . . . . . . . . . . . . . . . . . . 335 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 . . . . . . . . . . . . 336 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 . . . . . . . . . . . . 336 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 . . . . . . . . . . . . 337 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 . . . . . . . . . . . . 337 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 . . . . . . . . . . . . 338 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 . . . . . . . . . . . . 338 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 . . . . . . . . . . . . 339 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 . . . . . . . . . . . . 339 xviii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 . . . . . . . . . . . . 340 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 . . . . . . . . . . . . 340 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 . . . . . . . . . . . . . 341 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 . . . . . . . . . . . . . 341 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 . . . . . . . . . . . . . 341 PCS Receive XFI0 Vendor State 1: Address 3.E860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 2: Address 3.E861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 3: Address 3.E862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 4: Address 3.E863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 5: Address 3.E864 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 6: Address 3.E865 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 7: Address 3.E866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 1: Address 3.E870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 2: Address 3.E871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 3: Address 3.E872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 4: Address 3.E873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 5: Address 3.E874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 6: Address 3.E875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 PCS Receive XFI1 Vendor State 7: Address 3.E876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 . . . . . . . . . . . . . . . . . . . . . 346 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Unidata and SM status Register: Address 3.E8D4 . . . . . . . . . . . . . . . . . . . . . . . . . 348 PCS USX0 Receive Status Register: Address 3.E8D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 349 PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 . . . . . . . . . . . . . . . . . . . . . 350 PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 . . . . . . . . . . . . . . . . . . . . . . . . . 351 PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 . . . . . . . . . . . . . . . . . . . . . . . . . 351 PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 . . . . . . . . . . . . . . . . . . . . . . . . . 351 PCS USX1 Unidata and SM status Register: Address 3.E8E4 . . . . . . . . . . . . . . . . . . . . . . . . . 352 PCS USX1 Receive Status Register: Address 3.E8E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 353 PCS Receive Vendor Alarms 1: Address 3.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 PCS Receive Vendor Alarms 2: Address 3.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 PCS Receive Vendor Alarms 3: Address 3.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 PCS Receive Vendor Alarms 4: Address 3.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 PCS Receive Vendor Alarms 5: Address 3.EC04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 PCS Receive Vendor Alarms 6: Address 3.EC05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 PCS Receive Vendor Alarms 7: Address 3.EC06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 PCS Receive Vendor Alarms 10: Address 3.EC09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 PCS Receive Vendor Alarms 14: Address 3.EC0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 PCS Receive Vendor Alarms 15: Address 3.EC0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 PCS Receive Vendor Alarms 16: Address 3.EC0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 PCS Receive Vendor Alarms 17: Address 3.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 PCS Receive Vendor Internal Alarms : Address 3.ED0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 PCS Receive Vendor Internal Alarms : Address 3.ED0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 PCS Receive Vendor Internal Alarms : Address 3.ED0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 PCS Receive Vendor Internal Alarms : Address 3.ED10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 PCS Receive Vendor Interrupt Mask 1: Address 3.F400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 PCS Receive Vendor Interrupt Mask 2: Address 3.F401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 PCS Receive Vendor Interrupt Mask 3: Address 3.F402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 PCS Receive Vendor Interrupt Mask 4: Address 3.F403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 xix Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page PCS Receive Vendor Interrupt Mask 5: Address 3.F404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 PCS Receive Vendor Interrupt Mask 6: Address 3.F405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 PCS Receive Vendor Interrupt Mask 7: Address 3.F406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 PCS Receive Vendor Debug 1: Address 3.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 PCS Vendor Global Interrupt Flags 3: Address 3.FC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 en tia l PHY XS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Str ict ly Co nfi d PHY XS Standard Control 1: Address 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 PHY XS Standard Status 1: Address 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 PHY XS Standard Device Identifier 1: Address 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 PHY XS Standard Device Identifier 2: Address 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 PHY XS Standard Speed Ability: Address 4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 PHY XS Standard Devices in Package 1: Address 4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 PHY XS Standard Devices in Package 2: Address 4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 PHY XS Standard Status 2: Address 4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 PHY XS Standard Package Identifier 1: Address 4.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 PHY XS Standard Package Identifier 2: Address 4.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 PHY XS EEE Capability Register: Address 4.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 PHY XS EEE Wake Error Counter: Address 4.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 PHY XS Standard XGXS Lane Status: Address 4.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 PHY XS Standard XGXS Test Control: Address 4.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 TimeSync PHY XS Capability: Address 4.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 . . . . . . . . . . . . . . . . . . . . . . . 393 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 . . . . . . . . . . . . . . . . . . . . . . . 393 PHY XS SERDES Configuration 1: Address 4.C180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . 394 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 . . . . . . . . . . . . . . . . . . . . . . . . . . 394 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS SERDES LUT 256: Address 4.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 . . . . . . . . . . . 396 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 . . . . . . . . . . . 398 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 . . . . . . . . . . . 400 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 . . . . . . . . . . . 401 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 . . . . . . . . . . . 402 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 . . . . . . . . . . . . . . . . . 406 PHY XS Transmit (XAUI Rx) Reserved Vendor State 3: Address 4.C822 . . . . . . . . . . . . . . . . . 406 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 . . . . . . . . . . . . . . . . . . . . . . . 407 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 . . . . . . . . . . . . . . . . . . . . . . . 407 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 . . . . . . . . . . . . . . . . . . . . . . . 409 xx Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 . . . . . . . . . . . . . . . . 409 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 . . . . . . . . . . . . . . . . 410 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400 . . . . . . . . . . . . . . . . . 410 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401 . . . . . . . . . . . . . . . . . 411 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402 . . . . . . . . . . . . . . . . . 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 . . . . . . . . . . . . . . . . . . . . . . . . 413 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 . . . . . . . . . . . . . . . . . . . . . . . . 414 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 . . . . . . . . . . . . . . 415 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 . . . . . . . . . . . . . . 415 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 . . . . . . . . . . . . . . 416 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 . . . . . . . . . . . . . . 416 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 . . . . . . . . . . . . . . 417 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 . . . . . . . . . . . . 417 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 . . . . . . . . . . . . 418 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 . . . . . . . . . . . . 419 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 . . . . . . . . . . . . 420 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 . . . . . . . . . . . . 420 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 . . . . . . . . . . . . 421 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 7: Address 4.E416 . . . . . . . . . . . . 421 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 . . . . . . . . . . . . 422 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 . . . . . . . . . . . . 422 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810 . . . . . . . . . . . . . . . . . 424 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 . . . . . . . . . . . . . . . . . . . . . . . . 426 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 . . . . . . . . . . . . . . . . . . . . . . . . 427 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400 . . . . . . . . . . . . . . . . . . 428 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401 . . . . . . . . . . . . . . . . . . 429 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 . . . . . . . . . . . . . . . . . . . . . . . . 430 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 . . . . . . . . . . . . . . . . . . . . . . . . 430 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 . . . . . . . . . . . . . . . . . . . . . . . . 431 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Autonegotiation Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Autonegotiation Standard Control 1: Address 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Status 1: Address 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Device Identifier 1: Address 7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Device Identifier 2: Address 7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Devices in Package 1: Address 7.5 . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Devices in Package 2: Address 7.6 . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Status 2: Address 7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Package Identifier 1: Address 7.E . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Package Identifier 2: Address 7.F . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Advertisement Register: Address 7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 433 434 435 435 436 437 437 438 438 438 Table of Contents Section Page Str ict ly Co nfi d en tia l Autonegotiation Link Partner Base Page Ability Register: Address 7.13 . . . . . . . . . . . . . . . . . . 440 Autonegotiation Extended Next Page Transmit Register: Address 7.16 . . . . . . . . . . . . . . . . . . 442 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 . . . . . . . . . 443 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 . . . . . . . . . 443 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 . . . . . . . . . . 443 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A 444 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B 445 Autonegotiation 10GBASE-T Control Register: Address 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Autonegotiation 10GBASE-T Status Register: Address 7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Autonegotiation EEE Advertisement Register: Address 7.3C . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Autonegotiation EEE Link Partner Ability Register: Address 7.3D . . . . . . . . . . . . . . . . . . . . . . . 448 KR0 Autonegotiation Control: Address 7.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 KR0 Autonegotiation Status: Address 7.C201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 KR0 Autonegotiation Advertisement Word 1: Address 7.C210 . . . . . . . . . . . . . . . . . . . . . . . . . 452 KR0 Autonegotiation Advertisement Word 2: Address 7.C211 . . . . . . . . . . . . . . . . . . . . . . . . . 453 KR0 Autonegotiation Advertisement Word 3: Address 7.C212 . . . . . . . . . . . . . . . . . . . . . . . . . 454 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 . . . . . . . . . . . . . . . 454 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 . . . . . . . . . . . . . . . 456 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 . . . . . . . . . . . . . . . 457 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216 . . . . . . . . 457 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217 . . . . . . . . 458 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218 . . . . . . . . 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B 459 KR1 Autonegotiation Control: Address 7.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 KR1 Autonegotiation Status: Address 7.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 KR1 Autonegotiation Advertisement Word 1: Address 7.C310 . . . . . . . . . . . . . . . . . . . . . . . . . 461 KR1 Autonegotiation Advertisement Word 2: Address 7.C311 . . . . . . . . . . . . . . . . . . . . . . . . . 462 KR1 Autonegotiation Advertisement Word 3: Address 7.C312 . . . . . . . . . . . . . . . . . . . . . . . . . 463 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 . . . . . . . . . . . . . . . 463 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 . . . . . . . . . . . . . . . 465 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 . . . . . . . . . . . . . . . 466 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316 . . . . . . . . 466 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317 . . . . . . . . 467 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318 . . . . . . . . 467 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 467 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A 467 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B 468 Autonegotiation Vendor Provisioning 1: Address 7.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 . . . . . . . . . . . . . . . . . . . . . 470 Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 . . . . . . . . . . . . . . . . . . . . . 472 Autonegotiation Vendor Status 1: Address 7.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Autonegotiation Reserved Vendor Status 1: Address 7.C810 . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Autonegotiation Reserved Vendor Status 2: Address 7.C811 . . . . . . . . . . . . . . . . . . . . . . . . . . 475 Autonegotiation Reserved Vendor Status 3: Address 7.C812 . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Autonegotiation Reserved Vendor Status 4: Address 7.C813 . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Autonegotiation Reserved Vendor Status 5: Address 7.C814 . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Autonegotiation Standard Interrupt Mask 1: Address 7.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . 478 Autonegotiation Standard Interrupt Mask 2: Address 7.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 . . . . . . . . . . . . . . . . . . . . 479 xxii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page en tia l Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 1: Address 7.E820 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 2: Address 7.E821 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 3: Address 7.E822 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 4: Address 7.E823 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 1: Address 7.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 2: Address 7.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 3: Address 7.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 4: Address 7.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 . . . . . . . . . . . . . . . . . . . . . Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 . . . . . . . . . . . . . . . . . . . . . . 480 480 481 482 482 482 483 483 484 484 485 485 486 486 486 487 487 488 Co nfi d 100BASE-TX and 1000BASE-T Registers . . . . . . . . . . . . . . . . . . . . . . . 491 Str ict ly GbE Standard Device Identifier 1: Address 1D.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Device Identifier 2: Address 1D.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Devices in Package 1: Address 1D.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Vendor Devices in Package 2: Address 1D.6 . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Status 2: Address 1D.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Package Identifier 1: Address 1D.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Package Identifier 2: Address 1D.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII Test Control : Address 1D.C282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 1: Address 1D.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 2: Address 1D.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 3: Address 1D.C302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 4: Address 1D.C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 5: Address 1D.C304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 6: Address 1D.C305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 7: Address 1D.C306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 8: Address 1D.C307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 9: Address 1D.C308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 10: Address 1D.C309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 11: Address 1D.C30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 12: Address 1D.C30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 13: Address 1D.C30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 14: Address 1D.C30D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 15: Address 1D.C30E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 16: Address 1D.C30F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 17: Address 1D.C310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 18: Address 1D.C311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 19: Address 1D.C312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 20: Address 1D.C313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 21: Address 1D.C314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 22: Address 1D.C315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 23: Address 1D.C316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 24: Address 1D.C317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 25: Address 1D.C318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 491 491 491 492 493 493 494 494 494 495 495 495 495 496 496 496 497 497 497 498 498 498 499 499 499 500 500 500 501 501 501 502 502 Table of Contents Section Page Str ict ly Co nfi d en tia l GbE PHY WoL Control 26: Address 1D.C319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 GbE PHY WoL Control 27: Address 1D.C31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 28: Address 1D.C31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 29: Address 1D.C31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 30: Address 1D.C31D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 31: Address 1D.C31E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 32: Address 1D.C31F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 33: Address 1D.C320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 34: Address 1D.C321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 35: Address 1D.C322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 36: Address 1D.C323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 37: Address 1D.C324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 38: Address 1D.C325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 39: Address 1D.C326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 GbE PHY WoL Control 40: Address 1D.C327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 GbE PHY WoL Control 41: Address 1D.C328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 GbE PHY WoL Control 42: Address 1D.C329 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 GbE PHY WoL Control 43: Address 1D.C32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 GbE PHY WoL Control 44: Address 1D.C32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 GbE PHY WoL Control 45: Address 1D.C32C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 GbE PHY WoL Control 46: Address 1D.C32D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 GbE PHY WoL Control 47: Address 1D.C32E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 GbE PHY WoL Control 48: Address 1D.C32F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 GbE PHY WoL Control 49: Address 1D.C330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 GbE PHY WoL Control 50: Address 1D.C331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 GbE PHY WoL Control 51: Address 1D.C332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 GbE PHY WoL Control 52: Address 1D.C333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 GbE PHY WoL Control 53: Address 1D.C334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 GbE PHY WoL Control 54: Address 1D.C335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 GbE PHY WoL Control 55: Address 1D.C336 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 GbE PHY WoL Control 56: Address 1D.C337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 GbE PHY WoL Control 57: Address 1D.C338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 GbE PHY WoL Control 58: Address 1D.C339 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 GbE PHY WoL Control 59: Address 1D.C33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 GbE PHY WoL Control 60: Address 1D.C33B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 GbE PHY Extended WoL Control 1: Address 1D.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 GbE PHY Extended WoL Control 2: Address 1D.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 GbE PHY Extended WoL Control 3: Address 1D.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 GbE PHY Extended WoL Control 4: Address 1D.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 GbE PHY Extended WoL Control 5: Address 1D.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 GbE PHY Extended WoL Control 6: Address 1D.C425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 GbE PHY Extended WoL Control 7: Address 1D.C426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 GbE PHY Extended WoL Control 8: Address 1D.C427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 GbE PHY Extended WoL Control 9: Address 1D.C428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 GbE PHY Extended WoL Control 10: Address 1D.C429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 GbE PHY Extended WoL Control 11: Address 1D.C42A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 GbE PHY Extended WoL Control 12: Address 1D.C42B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 GbE PHY Extended WoL Control 13: Address 1D.C42C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 GbE PHY Extended WoL Control 14: Address 1D.C42D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 GbE PHY Extended WoL Control 15: Address 1D.C42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 GbE PHY Extended WoL Control 16: Address 1D.C42F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 GbE PHY Extended WoL Control 17: Address 1D.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 GbE PHY Extended WoL Control 18: Address 1D.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 xxiv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l GbE PHY Extended WoL Control 19: Address 1D.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 20: Address 1D.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 21: Address 1D.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 22: Address 1D.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 23: Address 1D.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 24: Address 1D.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 25: Address 1D.C438 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 26: Address 1D.C439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 27: Address 1D.C43A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 28: Address 1D.C43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 29: Address 1D.C43C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 30: Address 1D.C43D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Reserved Provisioning 1: Address 1D.C500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Reserved Provisioning 2: Address 1D.C501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 1: Address 1D.D280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 2: Address 1D.D281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 7: Address 1D.D286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 8: Address 1D.D287 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Rx Status 9: Address 1D.D288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 1: Address 1D.D290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 2: Address 1D.D291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 3: Address 1D.D292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 4: Address 1D.D293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 5: Address 1D.D294 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 6: Address 1D.D295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 7: Address 1D.D296 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 8: Address 1D.D297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Rx Status 9: Address 1D.D298 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 WoL Status: Address 1D.D302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 1: Address 1D.D303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 2: Address 1D.D304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 3: Address 1D.D305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 4: Address 1D.D306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 5: Address 1D.D307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 6: Address 1D.D308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 7: Address 1D.D309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 8: Address 1D.D30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 9: Address 1D.D30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII1 Tx Status 10: Address 1D.D30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SGMII0 WoL Status : Address 1D.D312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 1: Address 1D.D313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 2: Address 1D.D314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 3: Address 1D.D315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 4: Address 1D.D316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 5: Address 1D.D317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 6: Address 1D.D318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 7: Address 1D.D319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 8: Address 1D.D31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 9: Address 1D.D31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 520 520 521 521 521 522 522 522 523 523 523 524 524 525 526 527 527 527 528 528 528 529 529 530 531 531 532 532 532 533 533 533 534 535 535 535 536 536 536 537 537 537 538 538 538 539 539 539 540 540 540 541 541 Table of Contents Section Page GbE PHY SGMII0 Tx Status 10: Address 1D.D31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 GbE PHY SGMII WoL Status: Address 1D.D322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . 547 en tia l Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Str ict ly Co nfi d Global Standard Control 1: Address 1E.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Global Standard Device Identifier 1: Address 1E.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Global Standard Device Identifier 2: Address 1E.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 Global Standard Devices in Package 1: Address 1E.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 Global Standard Vendor Devices in Package 2: Address 1E.6 . . . . . . . . . . . . . . . . . . . . . . . . . 551 Global Standard Status 2: Address 1E.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Global Standard Package Identifier 1: Address 1E.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Global Standard Package Identifier 2: Address 1E.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 Global Firmware ID: Address 1E.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Global NVR Interface 1: Address 1E.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 Global NVR Interface 2: Address 1E.101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 Global NVR Interface 3: Address 1E.102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Global NVR Interface 4: Address 1E.103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 Global NVR Interface 5: Address 1E.104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 Global NVR Interface 6: Address 1E.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Global Mailbox Interface 1: Address 1E.200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 Global Mailbox Interface 2: Address 1E.201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 Global Mailbox Interface 3: Address 1E.202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Global Mailbox Interface 4: Address 1E.203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Global Mailbox Interface 5: Address 1E.204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 Global Mailbox Interface 6: Address 1E.205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Global Mailbox Interface 7: Address 1E.206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Global Microprocessor Scratch Pad 1: Address 1E.300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 Global Microprocessor Scratch Pad 2: Address 1E.301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Global Control 1: Address 1E.C000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Global Control 2: Address 1E.C001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Global Reset Control: Address 1E.C006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Global Diagnostic Provisioning: Address 1E.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Global Thermal Provisioning 1: Address 1E.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Global Thermal Provisioning 2: Address 1E.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Global Thermal Provisioning 3: Address 1E.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Global Thermal Provisioning 4: Address 1E.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Global Thermal Provisioning 5: Address 1E.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Global LED Provisioning 1: Address 1E.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Global LED Provisioning 2: Address 1E.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 Global LED Provisioning 3: Address 1E.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Global LED Provisioning 4: Address 1E.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 Global LED Provisioning 5: Address 1E.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 6: Address 1E.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 7: Address 1E.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 8: Address 1E.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 15: Address 1E.C43E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Global General Provisioning 1: Address 1E.C440 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Global General Provisioning 2: Address 1E.C441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 xxvi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Table of Contents Section Page Str ict ly Co nfi d en tia l Global General Provisioning 3: Address 1E.C442 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 4: Address 1E.C443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 5: Address 1E.C444 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 6: Address 1E.C445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 7: Address 1E.C446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 8: Address 1E.C447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 9: Address 1E.C448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Provisioning 10: Address 1E.C449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Provisioning 1: Address 1E.C450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Provisioning 2: Address 1E.C451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Provisioning 3: Address 1E.C452 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Provisioning 4: Address 1E.C453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 1: Address 1E.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 2: Address 1E.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 3: Address 1E.C472 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 4: Address 1E.C473 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 5: Address 1E.C474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 6: Address 1E.C475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 9: Address 1E.C478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 10: Address 1E.C479 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 11: Address 1E.C47A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Provisioning 12: Address 1E.C47B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C . . . . . . . . . . . . . PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D . . . . . . . . . . . . . PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E . . . . . . . . . . . . . PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F . . . . . . . . . . . . . Global SMBus 0 Provisioning 6: Address 1E.C485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global SMBus 1 Provisioning 6: Address 1E.C495 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global EEE Provisioning 1: Address 1E.C4A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 1: Address 1E.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 2: Address 1E.C801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 3: Address 1E.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 4: Address 1E.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 5: Address 1E.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 6: Address 1E.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 7: Address 1E.C806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 8: Address 1E.C807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Thermal Status 1: Address 1E.C820 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Thermal Status 2: Address 1E.C821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Status 1: Address 1E.C830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Status 2: Address 1E.C831 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Pin Status: Address 1E.C840 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Daisy Chain Status 2: Address 1E.C842 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Fault Message: Address 1E.C850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 1: Address 1E.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 2: Address 1E.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 3: Address 1E.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 4: Address 1E.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Status: Address 1E.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 1: Address 1E.C885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 2: Address 1E.C886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 3: Address 1E.C887 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 4: Address 1E.C888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxvii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 574 575 575 575 575 576 576 576 577 578 578 579 580 581 582 583 584 584 587 587 588 591 591 591 592 592 593 593 593 594 595 596 596 596 597 597 597 598 598 598 600 602 602 603 604 605 606 608 609 610 610 611 612 Table of Contents Section Page en tia l Global Alarms 1: Address 1E.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 Global Alarms 2: Address 1E.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Global Alarms 3: Address 1E.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616 Global Interrupt Mask 1: Address 1E.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 Global Interrupt Mask 2: Address 1E.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 Global Interrupt Mask 3: Address 1E.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . 620 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 623 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 . . . . . . . . . . . . . . . . . . . . . . . . . 624 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 Str ict ly Co nfi d References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627 xxviii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Figures Figure Page AQR405 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii AQR405 system block interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 en tia l Ethertype and VLAN parsing algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 11 User priority resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MDIO bus turn-around during Read operations . . . . . . . . . . . . . . . . . . . 25 SPI Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Co nfi d SPI Burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SPI burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Daisy-chain operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Daisy-chain signals and direction of flow . . . . . . . . . . . . . . . . . . . . . . . . 33 AQR405 operational blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AQR405 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 MDIO setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Str ict ly Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Daisy-chain timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RXAUI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 RXAUI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SGMII transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SGMII receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 KR transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 KR receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2500BASE-X transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2500BASE-X receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 xxix Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Figures Page Figure 50 MHz input timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 50.000 MHz phase noise mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 50 MHz reference clock output timing diagram . . . . . . . . . . . . . . . . . . . 69 JTAG timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 en tia l Power versus time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 AQR405 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Str ict ly Co nfi d Functional view of AQR405. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 xxx Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l Additional ingress MACsec statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional egress MACsec statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 "Per SCI" 32-bit mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAC statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Management Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MDIO frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-on reset thresholds for core supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial FLASH signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC_MASTER_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SERDES signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 KR diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 RXAUI/XAUI diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 SGMII diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SERDES lane assignments for different operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 XSGMII base page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 USXGMII base page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 MDI signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Timing signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LED signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Reference Resistors signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Metrology signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Wake-On-LAN signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Debug signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Reserved signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 MDIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Daisy-chain timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 SERDES receiver jitter tolerance specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 SERDES transmit jitter tolerance specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 RXAUI transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 RXAUI receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SGMII transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 SGMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 KR transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 KR receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 2500BASE-X transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2500BASE-X receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 xxxi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l 50.000 MHz input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 50 MHz reference clock output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 JTAG timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 AQR405 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 AQR405 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Full-reach VA22 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Full-reach VA12 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Full-reach VDD fixed supply electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 VDD_IO electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 VDD_FLASH electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 1.2V mode MDIO electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I/O pin electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 70% / 30% VDD_IO mode MDIO electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 77 SPI pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SERDES transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SERDES receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 MDI electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 LVDS 50MHz input electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 CLK_1588 input electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Bandgap reference resistor electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Theta J's . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MMD device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Field types within the MDIO register space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Terms used within the register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 PMA Standard Control 1: Address 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PMA Standard Status 1: Address 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PMA Standard Device Identifier 1: Address 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PMA Standard Device Identifier 2: Address 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 PMA Standard Speed Ability: Address 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PMA Standard Devices in Package 1: Address 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 PMA Standard Devices in Package 2: Address 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 PMA Standard Control 2: Address 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 PMA Standard Status 2: Address 1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 PMD Standard Transmit Disable Control: Address 1.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PMD Standard Signal Detect: Address 1.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PMD Standard 10G Extended Ability Register: Address 1.B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PMA Standard Package Identifier 1: Address 1.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 PMA Standard Package Identifier 2: Address 1.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 PMA 10GBASE-T Status: Address 1.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 xxxii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 . . . . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 . . . . . . . . . . . . . . . . PMA 10GBASE-T Test Modes: Address 1.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85. . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86. . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 . . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A. . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B . . . . . . . . . . . . . . . PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C . . . . . . . . . . . . . . . PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Skew Delay 1: Address 1.91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Skew Delay 2: Address 1.92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PMA 10GBASE-T Fast Retrain Status and Control : Address 1.93 . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Capability: Address 1.1800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 1: Address 1.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 2: Address 1.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 3: Address 1.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PMA Receive Path Data Delay 4: Address 1.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Control: Address 1.8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 . . . . . . . . . . . . . . . . . . . . . XENPAK Header - NVR Size 1: Address 1.8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - NVR Size 2: Address 1.8009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Memory Used 1: Address 1.800A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Memory Used 2: Address 1.800B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Basic Memory Start Address: Address 1.800C . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Customer Memory Offset: Address 1.800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Vendor Memory Start Address: Address 1.800E . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F . . . . . . . . . . . . . . . . . . . . XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Reserved 0x11: Address 1.8011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Transceiver Type: Address 1.8012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Connector Type: Address 1.8013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxiii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 104 105 106 107 107 108 108 109 109 110 110 111 111 111 112 112 113 114 115 115 115 116 116 116 117 117 117 118 119 119 119 120 120 120 121 121 121 122 122 122 123 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Basic - Encoding: Address 1.8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 XENPAK Basic - Bit Rate 0: Address 1.8015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 XENPAK Basic - Bit Rate 1: Address 1.8016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 XENPAK Basic - Protocol: Address 1.8017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 XENPAK Basic - Standards Compliance Codes: Address 1.8018 . . . . . . . . . . . . . . . . . . . . . . . . . . 125 XENPAK Basic - Reserved 0x19 1: Address 1.8019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 XENPAK Basic - Reserved 0x19 2: Address 1.801A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 XENPAK Basic - Reserved 0x19 3: Address 1.801B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 XENPAK Basic - Reserved 0x19 4: Address 1.801C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 XENPAK Basic - Reserved 0x19 5: Address 1.801D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 XENPAK Basic - Reserved 0x19 6: Address 1.801E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 XENPAK Basic - Reserved 0x19 7: Address 1.801F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 XENPAK Basic - Reserved 0x19 8: Address 1.8020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 XENPAK Basic - Reserved 0x19 9: Address 1.8021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 XENPAK Basic - Reserved 0x19 10: Address 1.8022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 XENPAK Basic - Reserved 0x19 11: Address 1.8023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 XENPAK Basic - Reserved 0x19 12: Address 1.8024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 XENPAK Basic - Reserved 0x19 13: Address 1.8025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 XENPAK Basic - Reserved 0x19 14: Address 1.8026 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 XENPAK Basic - Reserved 0x19 15: Address 1.8027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 XENPAK Basic - Reserved 0x19 16: Address 1.8028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 XENPAK Basic - Reserved 0x19 17: Address 1.8029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 XENPAK Basic - Reserved 0x19 18: Address 1.802A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 XENPAK Basic - Reserved 0x19 19: Address 1.802B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 XENPAK Basic - Reserved 0x19 20: Address 1.802C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 XENPAK Basic - Reserved 0x19 21: Address 1.802D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 XENPAK Basic - Reserved 0x19 22: Address 1.802E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 XENPAK Basic - Reserved 0x19 23: Address 1.802F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 XENPAK Basic - Reserved 0x19 24: Address 1.8030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 XENPAK Basic - Reserved 0x19 25: Address 1.8031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 XENPAK Basic - Package Identifier 1: Address 1.8032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 XENPAK Basic - Package Identifier 2: Address 1.8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 XENPAK Basic - Package Identifier 3: Address 1.8034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 XENPAK Basic - Package Identifier 4: Address 1.8035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 XENPAK Basic - Vendor Identifier 1: Address 1.8036 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 XENPAK Basic - Vendor Identifier 2: Address 1.8037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Identifier 3: Address 1.8038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Identifier 4: Address 1.8039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Name 1: Address 1.803A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 XENPAK Basic - Vendor Name 2: Address 1.803B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 XENPAK Basic - Vendor Name 3: Address 1.803C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 xxxiv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Basic - Vendor Name 4: Address 1.803D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 5: Address 1.803E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 6: Address 1.803F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 7: Address 1.8040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 8: Address 1.8041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 9: Address 1.8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 10: Address 1.8043 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 11: Address 1.8044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 12: Address 1.8045 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 13: Address 1.8046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 14: Address 1.8047 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 15: Address 1.8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Name 16: Address 1.8049 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 1: Address 1.804A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 2: Address 1.804B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 3: Address 1.804C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 4: Address 1.804D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 5: Address 1.804E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 6: Address 1.804F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 7: Address 1.8050. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 8: Address 1.8051. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 9: Address 1.8052. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 10: Address 1.8053. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 11: Address 1.8054. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 12: Address 1.8055. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 13: Address 1.8056. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 14: Address 1.8057. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 15: Address 1.8058. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Number 16: Address 1.8059. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 1: Address 1.805C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 2: Address 1.805D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 3: Address 1.805E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 4: Address 1.805F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 5: Address 1.8060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 6: Address 1.8061 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 7: Address 1.8062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 8: Address 1.8063 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 9: Address 1.8064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Basic - Vendor Serial Number 10: Address 1.8065 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 136 137 137 137 138 138 138 139 139 139 140 140 140 141 141 141 142 142 142 143 143 143 144 144 144 145 145 145 146 146 146 147 147 147 148 148 148 149 149 149 150 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Basic - Vendor Serial Number 11: Address 1.8066. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 XENPAK Basic - Vendor Serial Number 12: Address 1.8067. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 XENPAK Basic - Vendor Serial Number 13: Address 1.8068. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 XENPAK Basic - Vendor Serial Number 14: Address 1.8069. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 XENPAK Basic - Vendor Serial Number 15: Address 1.806A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 XENPAK Basic - Vendor Serial Number 16: Address 1.806B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 XENPAK Basic - Vendor Date Code 1: Address 1.806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 XENPAK Basic - Vendor Date Code 2: Address 1.806D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 XENPAK Basic - Vendor Date Code 3: Address 1.806E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 XENPAK Basic - Vendor Date Code 4: Address 1.806F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 XENPAK Basic - Vendor Date Code 5: Address 1.8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 XENPAK Basic - Vendor Date Code 6: Address 1.8071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 XENPAK Basic - Vendor Date Code 7: Address 1.8072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 XENPAK Basic - Vendor Date Code 8: Address 1.8073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 XENPAK Basic - Vendor Date Code 9: Address 1.8074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 XENPAK Basic - Vendor Date Code 10: Address 1.8075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 XENPAK Basic - 5V Loading: Address 1.8076 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 XENPAK Basic - 3.3V Loading: Address 1.8077 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 XENPAK Basic - APS Loading: Address 1.8078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 XENPAK Basic - APS Voltage: Address 1.8079. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 XENPAK Basic - DOM Capability: Address 1.807A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 XENPAK Basic - Low-Power Startup Capability: Address 1.807B . . . . . . . . . . . . . . . . . . . . . . . . . . 158 XENPAK Basic - Reserved 0x7C: Address 1.807C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 XENPAK Basic - Checksum: Address 1.807D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 XENPAK Customer - Reserved 0x7E 1: Address 1.807E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 XENPAK Customer - Reserved 0x7E 2: Address 1.807F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 XENPAK Customer - Reserved 0x7E 3: Address 1.8080. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 XENPAK Customer - Reserved 0x7E 4: Address 1.8081. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 XENPAK Customer - Reserved 0x7E 5: Address 1.8082. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 XENPAK Customer - Reserved 0x7E 6: Address 1.8083. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 XENPAK Customer - Reserved 0x7E 7: Address 1.8084. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 XENPAK Customer - Reserved 0x7E 8: Address 1.8085. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 XENPAK Customer - Reserved 0x7E 9: Address 1.8086. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 XENPAK Customer - Reserved 0x7E 10: Address 1.8087. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 XENPAK Customer - Reserved 0x7E 11: Address 1.8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 XENPAK Customer - Reserved 0x7E 12: Address 1.8089. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 XENPAK Customer - Reserved 0x7E 13: Address 1.808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 XENPAK Customer - Reserved 0x7E 14: Address 1.808B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 XENPAK Customer - Reserved 0x7E 15: Address 1.808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 XENPAK Customer - Reserved 0x7E 16: Address 1.808D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 XENPAK Customer - Reserved 0x7E 17: Address 1.808E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 xxxvi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Customer - Reserved 0x7E 18: Address 1.808F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 19: Address 1.8090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 20: Address 1.8091 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 21: Address 1.8092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 22: Address 1.8093 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 23: Address 1.8094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 24: Address 1.8095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 25: Address 1.8096 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 26: Address 1.8097 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 27: Address 1.8098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 28: Address 1.8099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 29: Address 1.809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 30: Address 1.809B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 31: Address 1.809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 32: Address 1.809D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 33: Address 1.809E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 34: Address 1.809F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 45: Address 1.80AA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 46: Address 1.80AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 47: Address 1.80AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Customer - Reserved 0x7E 48: Address 1.80AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxvii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 164 165 165 165 166 166 166 167 167 167 168 168 168 169 169 169 170 170 170 171 171 171 172 172 172 173 173 173 174 174 174 175 175 175 176 176 176 177 177 177 178 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 xxxviii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Rx_Alarm - Control: Address 1.9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK Tx_Alarm - Control: Address 1.9001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK LASI - Control: Address 1.9002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxix Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 192 192 192 193 193 193 194 194 194 195 195 195 196 196 196 197 197 197 198 198 198 199 199 199 200 200 200 201 201 201 202 202 202 203 203 203 204 204 204 205 206 List of Tables Table Page Str ict ly Co nfi d en tia l XENPAK Rx_Alarm - Status: Address 1.9003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 XENPAK Tx_Alarm - Status: Address 1.9004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 XENPAK LASI - Status: Address 1.9005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 XENPAK DOM - Tx Control: Address 1.9006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 . . . . . . . . . . . . . . . . . 210 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 . . . . . . . . . . . . . . . . . 211 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002. . . . . . . . . . . . . . . . . . 211 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 . . . . . . . . . . . . . . . . . 212 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 . . . . . . . . . . . . . . . 212 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 . . . . . . . . . . . . . . . 213 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006. . . . . . . . . . . . . . . . 213 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 . . . . . . . . . . . . . . . 214 XENPAK DOM - Temperature LSW: Address 1.A060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 XENPAK DOM - Temperature MSW: Address 1.A061. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Status: Address 1.A06E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Capability: Address 1.A06F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 XENPAK DOM - Alarms 1: Address 1.A070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 XENPAK DOM - Alarms 2: Address 1.A071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 XENPAK DOM - Alarms 3: Address 1.A072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Alarms 4: Address 1.A073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Alarms 5: Address 1.A074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 . . . . . . 218 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412. . . . . . . . . . . . . . . . . . . . . . . . . . 218 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413. . . . . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 1: Address 1.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 2: Address 1.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 PMA Transmit Vendor Alarms 3: Address 1.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 PMA Transmit Standard Interrupt Mask 1: Address 1.D000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 PMA Transmit Standard Interrupt Mask 2: Address 1.D001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 PMA Transmit Vendor Debug 1: Address 1.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 . . . . . . . . . . . . . . . . . . . . . . . . . . 222 PMA Receive Vendor State 1: Address 1.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 PMA Receive Reserved Vendor State 1: Address 1.E810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 PMA Receive Reserved Vendor State 2: Address 1.E811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PMA Vendor Global Interrupt Flags 1: Address 1.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 PCS Standard Control 1: Address 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 PCS Standard Status 1: Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 PCS Standard Device Identifier 1: Address 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 xl Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PCS Standard Device Identifier 2: Address 3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Speed Ability: Address 3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Devices in Package 1: Address 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Devices in Package 2: Address 3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Control 2: Address 3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Status 2: Address 3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Package Identifier 1: Address 3.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Standard Package Identifier 2: Address 3.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS EEE Capability Register : Address 3.14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10G Status 2: Address 3.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Capability: Address 3.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 1: Address 3.1801. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 2: Address 3.1802. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 3: Address 3.1803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Transmit Path Data Delay 4: Address 3.1804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 1: Address 3.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 2: Address 3.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 3: Address 3.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TimeSync PCS Receive Path Data Delay 4: Address 3.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Provisioning 1: Address 3.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Vendor Provisioning 2: Address 3.C401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410. . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 1: Address 3.C455. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 2: Address 3.C456. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 3: Address 3.C457. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 4: Address 3.C458. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 5: Address 3.C459. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xli Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 230 230 231 232 232 233 234 234 234 235 236 237 237 238 238 238 239 239 239 240 240 241 241 242 242 243 243 243 244 244 244 245 245 245 246 246 246 247 247 247 248 List of Tables Table Page Str ict ly Co nfi d en tia l PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 PCS USX0 Memory Control Register: Address 3.C4C0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 PCS USX0 Control Register 1: Address 3.C4C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 PCS USX0 Local fault Control Register: Address 3.C4C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 PCS USX0 MAC Local fault Control Register: Address 3.C4C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 PCS USX0 Auto-Neg Control Register: Address 3.C4C4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 PCS USX0 PTP Control Register: Address 3.C4C5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 PCS USX0 PKT Info Message Register-0: Address 3.C4C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 PCS USX0 PKT Info Message Register-1: Address 3.C4C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 PCS USX0 PKT Info Message Register-2: Address 3.C4C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 PCS USX0 link Fill Data Register-0: Address 3.C4C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 PCS USX0 link Fill Data Register-1: Address 3.C4CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 PCS USX0 Link FIFO Control Register: Address 3.C4CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 PCS USX0 TX FIFO Control Register: Address 3.C4CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 PCS USX0 Local Advertisement Register: Address 3.C4CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 PCS USX1 Memory Control Register: Address 3.C4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 PCS USX1 Control Register 1: Address 3.C4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 PCS USX1 Local fault Control Register: Address 3.C4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 PCS USX1 MAC Local fault Control Register: Address 3.C4E3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 PCS USX1 Auto-Neg Control Register: Address 3.C4E4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PCS USX1 PTP Control Register: Address 3.C4E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 PCS USX1 PKT Info Message Register-0: Address 3.C4E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 PCS USX1 PKT Info Message Register-1: Address 3.C4E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 PKT Info Message Register-2: Address 3.C4E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 link Fill Data Register-0: Address 3.C4E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 PCS USX1 link Fill Data Register-1: Address 3.C4EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PCS USX1 Link FIFO Control Register: Address 3.C4EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 PCS USX1 TX FIFO Control Register: Address 3.C4EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 PCS USX1 Local Advertisement Register: Address 3.C4ED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 . . . . . . . . . . . . . . . . . . . . 270 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . . . . 270 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 . . . . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit XFI0 Vendor State 1: Address 3.C860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 PCS Transmit XFI0 Vendor State 2: Address 3.C861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 PCS Transmit XFI0 Vendor State 3: Address 3.C862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 xlii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PCS Transmit XFI0 Vendor State 4: Address 3.C863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor State 1: Address 3.C870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor State 2: Address 3.C871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor State 3: Address 3.C872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XFI1 Vendor State 4: Address 3.C873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XGS Vendor State 1: Address 3.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XGS Vendor State 1: Address 3.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XGS Vendor State 3: Address 3.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XGS Vendor State 4: Address 3.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Transmit XGS Vendor State 5: Address 3.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Transmit Status : Address 3.C8C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 1: Address 3.C900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 2: Address 3.C901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 3: Address 3.C902 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 4: Address 3.C903 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 5: Address 3.C904 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 6: Address 3.C905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 7: Address 3.C906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 8: Address 3.C907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 9: Address 3.C908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 10: Address 3.C909 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 11: Address 3.C90A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 12: Address 3.C90B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 13: Address 3.C90C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 14: Address 3.C90D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 15: Address 3.C90E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 16: Address 3.C90F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 17: Address 3.C910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 18: Address 3.C911 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 19: Address 3.C912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 20: Address 3.C913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 21: Address 3.C914 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 22: Address 3.C915 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 23: Address 3.C916 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 24: Address 3.C917 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 25: Address 3.C918 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 26: Address 3.C919 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 27: Address 3.C91A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Vendor State 28: Address 3.C91B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xliii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 272 273 273 273 274 274 274 275 275 275 276 276 277 277 278 278 278 279 279 279 280 280 280 281 281 281 282 282 282 283 283 283 284 284 284 285 285 285 286 286 286 List of Tables Table Page Str ict ly Co nfi d en tia l PCS PTP Vendor State 29: Address 3.C91C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 PCS PTP Vendor State 31: Address 3.C91E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 PCS PTP Vendor State 32: Address 3.C91F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PCS PTP Vendor State 33: Address 3.C920 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PCS PTP Vendor State 34: Address 3.C921 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 PCS PTP Vendor State 35: Address 3.C922 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 PCS PTP Egress Vendor State 2: Address 3.C931 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 PCS PTP Egress Vendor State 3: Address 3.C932 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 PCS PTP Egress Vendor State 4: Address 3.C933 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 PCS PTP Egress Vendor State 5: Address 3.C934 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 PCS PTP Egress Vendor State 6: Address 3.C935 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 PCS PTP Egress Vendor State 7: Address 3.C936 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 PCS Transmit Vendor Alarms 1: Address 3.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 PCS Transmit Vendor Alarms 2: Address 3.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 PCS Transmit Vendor Alarms 3: Address 3.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 PCS Transmit Vendor Alarms 4: Address 3.CC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 PCS Standard Interrupt Mask 1: Address 3.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 PCS Standard Interrupt Mask 2: Address 3.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 PCS Standard Interrupt Mask 3: Address 3.D002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 PCS Transmit Vendor Debug 1: Address 3.D800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 PCS Receive Vendor Provisioning 1: Address 3.E400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 PCS Receive XFI0 Provisioning 1: Address 3.E460. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 PCS Receive XFI0 Provisioning 2: Address 3.E461. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 PCS Receive XFI1 Provisioning 1: Address 3.E470. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 PCS Receive XFI1 Provisioning 2: Address 3.E471. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 PCS USX0 RX Control Register: Address 3.E4D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 PCS USX0 RX FIFO Control Register: Address 3.E4D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 PCS USX0 SM Control Register: Address 3.E4D2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 PCS USX0 Link Timer Control Register: Address 3.E4D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 PCS USX0 RX Fault Control Register: Address 3.E4D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 PCS USX1 RX Control Register: Address 3.E4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 PCS USX1 RX FIFO Control Register: Address 3.E4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 PCS USX1 SM Control Register: Address 3.E4E2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 PCS USX1 Link Timer Control Register: Address 3.E4E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 PCS USX1 RX Fault Control Register: Address 3.E4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 xliv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PCS USX1 RX Control Register: Address 3.E4E0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 309 311 312 313 313 314 314 314 315 315 315 316 316 316 317 317 317 318 318 318 319 319 320 320 321 321 322 322 324 325 325 326 326 327 327 328 329 329 330 330 331 List of Tables Table Page Str ict ly Co nfi d en tia l PCS Receive Vendor State 1: Address 3.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810. . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811. . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 . . . . . . . . . . . . . . . . . . . . . 333 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 . . . . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 . . . . . . . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 . . . . . . . . . . . . . . . . . . . . . . . . 334 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 . . . . . . . . . . . . . . . . . . . . . . 335 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 . . . . . . . . . . . . . . . . . . . . . . 335 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 . . . . . . . . . . . . . . . 336 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 . . . . . . . . . . . . . . . 336 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 . . . . . . . . . . . . . . . 337 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 . . . . . . . . . . . . . . . 337 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 . . . . . . . . . . . . . . . 338 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 . . . . . . . . . . . . . . . 338 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 . . . . . . . . . . . . . . . 339 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 . . . . . . . . . . . . . . . 339 PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 . . . . . . . . . . . . . . . 340 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 . . . . . . . . . . . . . . . 340 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 . . . . . . . . . . . . . . . . . 341 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 . . . . . . . . . . . . . . . . . 341 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 . . . . . . . . . . . . . . . . . 341 PCS Receive XFI0 Vendor State 1: Address 3.E860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 2: Address 3.E861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 3: Address 3.E862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 PCS Receive XFI0 Vendor State 4: Address 3.E863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 5: Address 3.E864 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 6: Address 3.E865 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 PCS Receive XFI0 Vendor State 7: Address 3.E866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 1: Address 3.E870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 2: Address 3.E871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 PCS Receive XFI1 Vendor State 3: Address 3.E872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 4: Address 3.E873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 5: Address 3.E874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 PCS Receive XFI1 Vendor State 6: Address 3.E875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 PCS Receive XFI1 Vendor State 7: Address 3.E876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 . . . . . . . . . . . . . . . . . . . . . . . . 346 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 PCS USX0 Unidata and SM status Register: Address 3.E8D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 xlvi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PCS USX0 Receive Status Register: Address 3.E8D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 . . PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Unidata and SM status Register: Address 3.E8E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Receive Status Register: Address 3.E8E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 . . PCS Receive Vendor Alarms 1: Address 3.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 2: Address 3.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 3: Address 3.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 4: Address 3.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 5: Address 3.EC04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 6: Address 3.EC05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 7: Address 3.EC06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 10: Address 3.EC09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 14: Address 3.EC0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 15: Address 3.EC0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 16: Address 3.EC0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Alarms 17: Address 3.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Internal Alarms : Address 3.ED0D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Internal Alarms : Address 3.ED0E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Internal Alarms : Address 3.ED0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Internal Alarms : Address 3.ED10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 1: Address 3.F400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 2: Address 3.F401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 3: Address 3.F402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 4: Address 3.F403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 5: Address 3.F404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 6: Address 3.F405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Interrupt Mask 7: Address 3.F406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Receive Vendor Debug 1: Address 3.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Vendor Global Interrupt Flags 1: Address 3.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCS Vendor Global Interrupt Flags 3: Address 3.FC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Control 1: Address 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Status 1: Address 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Device Identifier 1: Address 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Device Identifier 2: Address 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Speed Ability: Address 4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHY XS Standard Devices in Package 1: Address 4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlvii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 348 349 350 351 351 351 352 352 353 354 356 356 356 356 357 357 358 360 361 363 365 366 368 369 371 372 374 374 374 375 375 376 377 378 380 381 382 384 384 384 385 List of Tables Table Page Str ict ly Co nfi d en tia l PHY XS Standard Devices in Package 2: Address 4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 PHY XS Standard Status 2: Address 4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 PHY XS Standard Package Identifier 1: Address 4.E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 PHY XS Standard Package Identifier 2: Address 4.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 PHY XS EEE Capability Register: Address 4.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 PHY XS EEE Wake Error Counter: Address 4.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 PHY XS Standard XGXS Lane Status: Address 4.18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 PHY XS Standard XGXS Test Control: Address 4.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 TimeSync PHY XS Capability: Address 4.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 . . . . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 . . . . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 . . . . . . . . . . . . . . . . . . . . . . . . . . 391 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 . . . . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . 392 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . 393 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . 393 PHY XS SERDES Configuration 1: Address 4.C180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS SERDES LUT 256: Address 4.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 . . . . . . . . . . . . . . 396 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 . . . . . . . . . . . . . . 398 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 . . . . . . . . . . . . . . 400 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 . . . . . . . . . . . . . . 401 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 . . . . . . . . . . . . . . 402 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 . . . . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 . . . . . . . . . . . . . . . . . . . . 405 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 . . . . . . . . . . . . . . . . . . . . 406 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 . . . . . . . . . . . . . . . . . . . . 406 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . 407 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 407 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . 409 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 . . . . . . . . . . . . . . . . . . . 409 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 . . . . . . . . . . . . . . . . . . . 410 xlviii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400. . . . . . . . . . . . . . . . . . . . . 410 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401. . . . . . . . . . . . . . . . . . . . . 411 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402. . . . . . . . . . . . . . . . . . . . . 412 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 . . . . . . . . . . . . . . . . . 415 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 . . . . . . . . . . . . . . . . . 415 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 . . . . . . . . . . . . . . . . . 416 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 . . . . . . . . . . . . . . . . . 416 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 . . . . . . . . . . . . . . . . . 417 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 . . . . . . . . . . . . . . . 417 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 . . . . . . . . . . . . . . . 418 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 . . . . . . . . . . . . . . . 419 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 . . . . . . . . . . . . . . . 420 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 . . . . . . . . . . . . . . . 420 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 . . . . . . . . . . . . . . . 421 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 . . . . . . . . . . . . . . . 421 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 . . . . . . . . . . . . . . . 422 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 . . . . . . . . . . . . . . . 422 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 . . . . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810. . . . . . . . . . . . . . . . . . . . . 424 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400. . . . . . . . . . . . . . . . . . . . . . 428 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401. . . . . . . . . . . . . . . . . . . . . . 429 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Autonegotiation Standard Control 1: Address 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Autonegotiation Standard Status 1: Address 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Autonegotiation Standard Device Identifier 1: Address 7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Autonegotiation Standard Device Identifier 2: Address 7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 Autonegotiation Standard Devices in Package 1: Address 7.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Autonegotiation Standard Devices in Package 2: Address 7.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 xlix Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l Autonegotiation Standard Status 2: Address 7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Autonegotiation Standard Package Identifier 1: Address 7.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Autonegotiation Standard Package Identifier 2: Address 7.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Autonegotiation Advertisement Register: Address 7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Autonegotiation Link Partner Base Page Ability Register: Address 7.13 . . . . . . . . . . . . . . . . . . . . . 440 Autonegotiation Extended Next Page Transmit Register: Address 7.16 . . . . . . . . . . . . . . . . . . . . . 442 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 . . . . . . . . . . . . 443 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 . . . . . . . . . . . . 443 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 . . . . . . . . . . . . . 443 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A . . 444 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B . . 445 Autonegotiation 10GBASE-T Control Register: Address 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Autonegotiation 10GBASE-T Status Register: Address 7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Autonegotiation EEE Advertisement Register: Address 7.3C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Autonegotiation EEE Link Partner Ability Register: Address 7.3D . . . . . . . . . . . . . . . . . . . . . . . . . . 448 KR0 Autonegotiation Control: Address 7.C200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 KR0 Autonegotiation Status: Address 7.C201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 KR0 Autonegotiation Advertisement Word 1: Address 7.C210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 KR0 Autonegotiation Advertisement Word 2: Address 7.C211. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 KR0 Autonegotiation Advertisement Word 3: Address 7.C212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 . . . . . . . . . . . . . . . . . . 454 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 . . . . . . . . . . . . . . . . . . 456 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 . . . . . . . . . . . . . . . . . . 457 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216. . . . . . . . . . . . 457 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217. . . . . . . . . . . . 458 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218. . . . . . . . . . . . 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 . 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A . 458 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B . 459 KR1 Autonegotiation Control: Address 7.C300. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 KR1 Autonegotiation Status: Address 7.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 KR1 Autonegotiation Advertisement Word 1: Address 7.C310. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 KR1 Autonegotiation Advertisement Word 2: Address 7.C311. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 KR1 Autonegotiation Advertisement Word 3: Address 7.C312. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 . . . . . . . . . . . . . . . . . . 463 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 . . . . . . . . . . . . . . . . . . 465 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 . . . . . . . . . . . . . . . . . . 466 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316. . . . . . . . . . . . 466 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317. . . . . . . . . . . . 467 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318. . . . . . . . . . . . 467 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 . 467 l Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A . KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B . Autonegotiation Vendor Provisioning 1: Address 7.C400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Vendor Status 1: Address 7.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Status 1: Address 7.C810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Status 2: Address 7.C811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Status 3: Address 7.C812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Status 4: Address 7.C813 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Reserved Vendor Status 5: Address 7.C814 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Interrupt Mask 1: Address 7.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Standard Interrupt Mask 2: Address 7.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 1: Address 7.E820 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 2: Address 7.E821 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 3: Address 7.E822 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Link Partner Status 4: Address 7.E823 . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 1: Address 7.EC00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 2: Address 7.EC01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 3: Address 7.EC02. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Alarms 4: Address 7.EC03. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 . . . . . . . . . . . . . . . . . . . . . . . . Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Device Identifier 1: Address 1D.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Device Identifier 2: Address 1D.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Devices in Package 1: Address 1D.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Vendor Devices in Package 2: Address 1D.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Status 2: Address 1D.8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Package Identifier 1: Address 1D.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE Standard Package Identifier 2: Address 1D.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . li Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 467 468 468 470 472 473 474 475 476 476 476 477 477 478 479 479 480 480 481 482 482 482 483 483 484 484 485 485 486 486 486 487 487 488 491 491 491 492 493 493 494 List of Tables Table Page Str ict ly Co nfi d en tia l GbE PHY SGMII Test Control : Address 1D.C282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 GbE PHY WoL Control 1: Address 1D.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 GbE PHY WoL Control 2: Address 1D.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 GbE PHY WoL Control 3: Address 1D.C302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 GbE PHY WoL Control 4: Address 1D.C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 GbE PHY WoL Control 5: Address 1D.C304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 GbE PHY WoL Control 6: Address 1D.C305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 GbE PHY WoL Control 7: Address 1D.C306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 GbE PHY WoL Control 7: Address 1D.C306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 GbE PHY WoL Control 9: Address 1D.C308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 GbE PHY WoL Control 10: Address 1D.C309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 GbE PHY WoL Control 11: Address 1D.C30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 GbE PHY WoL Control 12: Address 1D.C30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 GbE PHY WoL Control 13: Address 1D.C30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 GbE PHY WoL Control 14: Address 1D.C30D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 GbE PHY WoL Control 15: Address 1D.C30E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 GbE PHY WoL Control 16: Address 1D.C30F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 GbE PHY WoL Control 17: Address 1D.C310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 GbE PHY WoL Control 18: Address 1D.C311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 GbE PHY WoL Control 19: Address 1D.C312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 GbE PHY WoL Control 20: Address 1D.C313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 GbE PHY WoL Control 21: Address 1D.C314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 GbE PHY WoL Control 22: Address 1D.C315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 GbE PHY WoL Control 23: Address 1D.C316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 GbE PHY WoL Control 24: Address 1D.C317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 GbE PHY WoL Control 25: Address 1D.C318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 GbE PHY WoL Control 26: Address 1D.C319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 GbE PHY WoL Control 27: Address 1D.C31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 28: Address 1D.C31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 29: Address 1D.C31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503 GbE PHY WoL Control 30: Address 1D.C31D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 31: Address 1D.C31E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 32: Address 1D.C31F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 GbE PHY WoL Control 33: Address 1D.C320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 34: Address 1D.C321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 35: Address 1D.C322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 GbE PHY WoL Control 36: Address 1D.C323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 37: Address 1D.C324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 38: Address 1D.C325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506 GbE PHY WoL Control 39: Address 1D.C326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 GbE PHY WoL Control 40: Address 1D.C327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 lii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l GbE PHY WoL Control 41: Address 1D.C328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 42: Address 1D.C329 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 43: Address 1D.C32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 44: Address 1D.C32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 45: Address 1D.C32C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 46: Address 1D.C32D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 47: Address 1D.C32E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 48: Address 1D.C32F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 49: Address 1D.C330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 50: Address 1D.C331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 51: Address 1D.C332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 52: Address 1D.C333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 53: Address 1D.C334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 54: Address 1D.C335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 55: Address 1D.C336 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 56: Address 1D.C337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 57: Address 1D.C338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 58: Address 1D.C339 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 59: Address 1D.C33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY WoL Control 60: Address 1D.C33B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 1: Address 1D.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 2: Address 1D.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 3: Address 1D.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 4: Address 1D.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 5: Address 1D.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 6: Address 1D.C425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 7: Address 1D.C426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 8: Address 1D.C427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 9: Address 1D.C428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 10: Address 1D.C429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 11: Address 1D.C42A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 12: Address 1D.C42B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 13: Address 1D.C42C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 14: Address 1D.C42D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 15: Address 1D.C42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 16: Address 1D.C42F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 17: Address 1D.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 18: Address 1D.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 19: Address 1D.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 20: Address 1D.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Extended WoL Control 21: Address 1D.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . liii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 507 508 508 508 509 509 509 510 510 510 511 511 511 512 512 512 513 513 513 514 514 514 515 515 515 516 516 516 517 517 517 518 518 518 519 519 519 520 520 520 521 List of Tables Table Page Str ict ly Co nfi d en tia l GbE PHY Extended WoL Control 22: Address 1D.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 GbE PHY Extended WoL Control 23: Address 1D.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 GbE PHY Extended WoL Control 24: Address 1D.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 GbE PHY Extended WoL Control 25: Address 1D.C438 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 GbE PHY Extended WoL Control 26: Address 1D.C439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 GbE PHY Extended WoL Control 27: Address 1D.C43A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 GbE PHY Extended WoL Control 28: Address 1D.C43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 GbE PHY Extended WoL Control 29: Address 1D.C43C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 GbE PHY Extended WoL Control 30: Address 1D.C43D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 GbE Reserved Provisioning 1: Address 1D.C500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 GbE Reserved Provisioning 2: Address 1D.C501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 GbE PHY SGMII1 Rx Status 1: Address 1D.D280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 GbE PHY SGMII1 Rx Status 2: Address 1D.D281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 GbE PHY SGMII1 Rx Status 7: Address 1D.D286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 GbE PHY SGMII1 Rx Status 8: Address 1D.D287 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 GbE PHY SGMII1 Rx Status 9: Address 1D.D288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 GbE PHY SGMII0 Rx Status 1: Address 1D.D290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 GbE PHY SGMII0 Rx Status 2: Address 1D.D291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 GbE PHY SGMII0 Rx Status 3: Address 1D.D292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 GbE PHY SGMII0 Rx Status 4: Address 1D.D293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 GbE PHY SGMII0 Rx Status 5: Address 1D.D294 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 GbE PHY SGMII0 Rx Status 6: Address 1D.D295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 GbE PHY SGMII0 Rx Status 7: Address 1D.D296 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 GbE PHY SGMII0 Rx Status 8: Address 1D.D297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 GbE PHY SGMII0 Rx Status 9: Address 1D.D298 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 GbE PHY SGMII1 WoL Status: Address 1D.D302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 GbE PHY SGMII1 Tx Status 5: Address 1D.D307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 GbE PHY SGMII1 Tx Status 6: Address 1D.D308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 GbE PHY SGMII1 Tx Status 7: Address 1D.D309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 GbE PHY SGMII1 Tx Status 8: Address 1D.D30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 GbE PHY SGMII1 Tx Status 9: Address 1D.D30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 GbE PHY SGMII1 Tx Status 10: Address 1D.D30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 SGMII0 WoL Status : Address 1D.D312. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 liv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l GbE PHY SGMII0 Tx Status 1: Address 1D.D313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 2: Address 1D.D314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 3: Address 1D.D315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 4: Address 1D.D316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 5: Address 1D.D317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 6: Address 1D.D318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 7: Address 1D.D319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 8: Address 1D.D31A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 9: Address 1D.D31B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII0 Tx Status 10: Address 1D.D31C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII WoL Status: Address 1D.D322. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Control 1: Address 1E.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Device Identifier 1: Address 1E.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Device Identifier 2: Address 1E.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Devices in Package 1: Address 1E.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Vendor Devices in Package 2: Address 1E.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Status 2: Address 1E.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Package Identifier 1: Address 1E.E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Standard Package Identifier 2: Address 1E.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Firmware ID: Address 1E.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 1: Address 1E.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 2: Address 1E.101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 3: Address 1E.102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 4: Address 1E.103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 5: Address 1E.104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global NVR Interface 6: Address 1E.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 1: Address 1E.200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 2: Address 1E.201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 3: Address 1E.202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 4: Address 1E.203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 5: Address 1E.204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 6: Address 1E.205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Mailbox Interface 7: Address 1E.206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Microprocessor Scratch Pad 1: Address 1E.300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Microprocessor Scratch Pad 2: Address 1E.301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Control 1: Address 1E.C000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lv Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 538 539 539 539 540 540 540 541 541 541 542 542 543 544 545 547 549 549 550 550 551 552 552 552 553 553 554 555 555 556 557 557 558 559 559 559 560 560 560 561 561 List of Tables Table Page Str ict ly Co nfi d en tia l Global Control 2: Address 1E.C001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Global Reset Control: Address 1E.C006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Global Diagnostic Provisioning: Address 1E.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562 Global Thermal Provisioning 1: Address 1E.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Global Thermal Provisioning 2: Address 1E.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563 Global Thermal Provisioning 3: Address 1E.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564 Global Thermal Provisioning 4: Address 1E.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Global Thermal Provisioning 5: Address 1E.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Global LED Provisioning 1: Address 1E.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566 Global LED Provisioning 2: Address 1E.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 Global LED Provisioning 3: Address 1E.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570 Global LED Provisioning 4: Address 1E.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 Global LED Provisioning 5: Address 1E.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 6: Address 1E.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 7: Address 1E.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 8: Address 1E.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Global LED Provisioning 15: Address 1E.C43E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Global General Provisioning 1: Address 1E.C440 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Global General Provisioning 2: Address 1E.C441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 Global General Provisioning 3: Address 1E.C442 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 Global General Provisioning 4: Address 1E.C443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Global General Provisioning 5: Address 1E.C444 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Global General Provisioning 6: Address 1E.C445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Global General Provisioning 7: Address 1E.C446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Global General Provisioning 8: Address 1E.C447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 Global General Provisioning 9: Address 1E.C448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 Global General Provisioning 10: Address 1E.C449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 Global NVR Provisioning 1: Address 1E.C450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 Global NVR Provisioning 2: Address 1E.C451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 Global NVR Provisioning 3: Address 1E.C452 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 Global NVR Provisioning 4: Address 1E.C453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 Global Reserved Provisioning 1: Address 1E.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Global Reserved Provisioning 2: Address 1E.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Global Reserved Provisioning 3: Address 1E.C472 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 Global Reserved Provisioning 4: Address 1E.C473 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 Global Reserved Provisioning 5: Address 1E.C474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 Global Reserved Provisioning 6: Address 1E.C475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 Global Reserved Provisioning 9: Address 1E.C478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Global Reserved Provisioning 10: Address 1E.C479 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 Global Reserved Provisioning 11: Address 1E.C47A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 Global Reserved Provisioning 12: Address 1E.C47B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 lvi Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 List of Tables Table Page Str ict ly Co nfi d en tia l PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C . . . . . . . . . . . . . . . . PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D . . . . . . . . . . . . . . . . PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E . . . . . . . . . . . . . . . . PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F . . . . . . . . . . . . . . . . Global SMBus 0 Provisioning 6: Address 1E.C485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global SMBus 1 Provisioning 6: Address 1E.C495 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global EEE Provisioning 1: Address 1E.C4A0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 1: Address 1E.C800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 2: Address 1E.C801. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 3: Address 1E.C802. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 4: Address 1E.C803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 5: Address 1E.C804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 6: Address 1E.C805. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 7: Address 1E.C806. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Status 8: Address 1E.C807. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Thermal Status 1: Address 1E.C820. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Thermal Status 2: Address 1E.C821. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Status 1: Address 1E.C830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global General Status 2: Address 1E.C831 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Pin Status: Address 1E.C840 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Daisy Chain Status 2: Address 1E.C842 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Fault Message: Address 1E.C850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 1: Address 1E.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 2: Address 1E.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 3: Address 1E.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Cable Diagnostic Impedance 4: Address 1E.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Status: Address 1E.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 1: Address 1E.C885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 2: Address 1E.C886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 3: Address 1E.C887 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Reserved Status 4: Address 1E.C888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Alarms 1: Address 1E.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Alarms 2: Address 1E.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Alarms 3: Address 1E.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Interrupt Mask 1: Address 1E.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Interrupt Mask 2: Address 1E.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Interrupt Mask 3: Address 1E.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lvii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 591 591 592 592 593 593 593 594 595 596 596 596 597 597 597 598 598 598 601 602 602 603 604 605 606 608 609 610 610 611 612 613 615 616 617 618 619 620 623 624 625 List of Tables Page Str ict ly Co nfi d en tia l Table lviii Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 1 Overview 1- 1.1 Introduction en tia l The AQR405 is a quad port 28 nm CMOS 10GBASE-T / 5G / 2.5G / 1000BASE-T / 100BASE-TX five-speed PHY that is designed to be a low-power, stand-alone solution for all NIC, switch, and LAN-on-Motherboard applications that require 10GBASE-T capability. This chapter is intended to provide an overview of the AQR405 and its operating modes. 1.2 General Deployment 1.2.1 Mechanical Co nfi d This section briefly touches on the hardware implementation. For more detailed hardware design information, please see the Hardware Design Guide[13]. The AQR405 is packaged in a 25 mm x 25 mm flip-chip 576 pin BGA (24 rows x 24 rows). Consequently, the jc is a low 0.42C/W. Meanwhile, the die is rated to operate up to 105C junction temperature, so engineering an appropriate thermal solution for the target system is a straightforward task. 1.2.2 Power Supplies Str ict ly The AQR405 utilizes three power supplies: a 0.85V digital supply (VDD), and 1.2V and 2.1V analog supplies (VA12 and VA22 respectively). All supplies should come up within 100ms from the first rail rising to the last rail reaching its 70% voltage level. The power up sequence requires that the VDD and 1.2V rails reach their nominal voltage levels in any order first and then followed by the other power rails in any order. The same order must be followed for power down sequence. For the I/O, the AQR405 offers a separate VDD_IO supply, which will set the logic thresholds for the I/O at 70% / 30% of its voltage. In addition to the VDD_IO supply voltages of 2.1V and 2.5V, a separate control pin (MDIO_1P2_SELECT_N when pulled low) allows pins MDC, MDIO, INT_N, and RST_N to operate at 1.2V logic levels, regardless of the voltage on VDD_IO. AVSS, VSS, and VSS_SRDS must be tied to the same ground plane. 1.2.3 Reset The AQR405 supports on-chip power-on reset generation and it is also capable of supplying this reset to the rest of the system via a RST_OUT_N pin. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 2 1.2.4 Clocks The AQR405 uses a 50 MHz differential clock to synthesize all of the required clocks. For Synchronous Ethernet (Sync-E) applications, the AQR405 is capable of outputting to the system primary and secondary 50 MHz clocks phase-locked to the line clocks of any of the PHYs in the package. 1.2.5 FLASH Co nfi d en tia l The AQR405 is capable of operating with a 512 KByte (4 Mbit) or larger SPI serial FLASH for autonomous operation, or of being boot-loaded via the MDIO interface. In both cases, the image stored in FLASH and the MDIO boot-load image are identical. If autonomous operation is not a requirement, and the target system is capable of providing the boot-load image, the FLASH can be eliminated. To support configurations such as switches, where multiple PHYs are deployed on the same board, a daisy-chain mechanism exists within the PHY that allows one FLASH device to contain the images for all of the PHYs. The PHY with the FLASH device is designated as being the daisy-chain master, and it broadcasts the image to all of the other PHYs using a serial bus. For the FLASH I/O, the AQR405 offers a separate VDD_FLASH supply that is used to run the FLASH interface. VDD_FLASH requires 2.5V. If boot-loading is desired, it is possible to gang-load multiple parts via a broadcast MDIO address in the AQR405. Str ict ly 1.2.6 Power-on Default Values The AQR405 has a fixed set of hardware default values that exist in the chip for all configurable registers. However, the firmware is capable of storing in its boot image any change to these defaults for up to 48 PHYs within a single image, effectively allowing the user to configure the chip to come out of reset in the desired operating state. This can be done by using the Aquantia web-provisioning tool to alter the boot image. 1.2.7 SERDES Configuration The AQR405 is capable of routing any logical SERDES lane to any physical SERDES lane, as well as performing polarity inversions. On the line side, in addition to supporting MDI / MDI-X and automatic polarity correction, the AQR405 supports lane swapping of the ABCD pairs to enable easy board routing with different magnetics pin-outs. Note that polarity inversion is also referred to as "Lane Invert" in the register map. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 3 1.3 SERDES The AQR405 is designed to be used in conjunction with a five-speed MAC chip. The AQR405's interface to the system for 10G operation is KR and RXAUI, and for 1G / 100M operation is SGMII / USXGMII on SERDES logical Lane 0. The AQR405 is capable of being configured so that the MAC interface can start in one of the following modes: en tia l 1) Start with the 10G interface on (KR, RXAUI). 2) Start with the 1000BASE-X interface on (SGMII without autonegotiation). 3) Start with extended SGMII autonegotiation (USXGMII) enabled. 4) Start with all interfaces off. 1.4 Power-On Co nfi d Once a connection to a link partner has been established, the interface will then switch to the correct MAC interface speed. More information on this can be found in Section 2.5 The AQR405 is designed to perform the following operations at boot: 1) Power-up calibration of internal VCOs and variable power supplies (if variable supply operation is enabled) Str ict ly 2) Provision stored default values* 3) Calibration of the analog front-end 4) Autonegotiation 5) Perform training (as required) Note that the AQR405 internally has 4 SERDES per PHY, but only physical Lanes 0 and 2 are connected. Consequently, the register map contains information for XAUI and for Lanes 1 and 3, but these cannot be used in the AQR405. Note that USXGMII operation and autonegotiation is identical to SGMII operation and autonegotiation when 2.5G/5G/10G operation is not enabled. * The AQR405 is capable of storing in its firmware image a list of registers whose default values should be overwritten with a user-specified value on power up. This is done using the web-based Aquantia Firmware Provisioning Tool, and allows the PHY to be personalized for certain modes of operation. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 4 6) Verify error-free operation 7) Enter steady state 1.5 Cable Diagnostics en tia l The AQR405 implements a powerful cable diagnostic algorithm to accurately measure all of the TDR and TDT sequences within the group of four channels. The algorithm used transmits a pseudo-noise sequence with an amplitude of less than 300 mV for a brief period of time, and from this converges the 10GBASE-T equalizers on all of the other channels. From the results of this measurement, the length of each pair, the top impairment along the pair, and the impedance of the cable are flagged. These measurements are reported to an accuracy to 1m using a cable propagation characteristics[11] of 4.83 ns/m and are presented in the Global MMD register map. Co nfi d 1.6 Wake-On-LAN The AQR405 has an integrated Wake-On-LAN filter compliant to the Microsoft Network Device Class Version 2.0 specification[9]. This filter is capable of detecting a wake-up sequence / frame in 100BASE-TX and 1000BASE-T mode and driving a WAKE signal high upon receiving the appropriate magic packet or magic frame. In this mode, the AQR405 operating power in 100BASE-TX mode is less than 1W, with only the MDIO interface and the receive 100 Mb/s interface operational. Str ict ly The AQR405 can support up to 8 programmable magic frame types. Each frame type has a 128-bit mask field that corresponds to the first 128 bytes of the wakeup frame and a programmable CRC-32. This CRC-32 is calculated over the selected bytes in the frame and is used as a signature to determine reception of a magic packet. Each bit selects whether the corresponding byte is included in the CRC-32. To support magic packets, the AQR405 will hunt for an occurrence of the synchronization stream, which is defined by 6 bytes of 0xFF. Then it will check to see if this sequence is followed by 16 duplications of a programmable MAC address. 1.7 Debug and Diagnostics Tools The AQR405 supports a full suite of network and system loopbacks at all three rates. The loopbacks are shown below. The cross-channel impulse responses. The CRC-32 chosen is the same one that is used for the Ethernet packet frame check sequence (i.e. CCITT-32) in the 802.3 standard[3]. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 5 MDIO SRDS2 10G MDIO Management 10G PCS KR/USXGMII PCS 0 5G PCS KR/USXGMII PCS 1 2.5G PCS SGMII PCS 0 1G PCS SGMII PCS 1 100M PCS MDIO Registers MACSEC System Interface - System Loopback PCS Loopback A-B / C-D Cable Loopback Co nfi d System Interface - Network Loopback PMA Loopback DSP System I/F XAUI/RXAUI PCS DAC / THP THP THP Driver Precoder Precoder Precoder THP Hybrid THP THP Precoder Precoder Precoder THP A/D THP THP Precoder Precoder Precoder VGA & THP THP THP Filter Precoder Precoder Precoder en tia l SRDS0 10G SERDES AQRate 25mm Quad A/D LINE VGA & Filter System Interface - Network Loopback PHY-XS Loopback Network Interface - Network Loopback Str ict ly Figure 1.1 Loopbacks In addition to the loopbacks, the AQR405 supports CRC-32 packet checking on both the receive and transmit traffic at all three rates, and maintains 1 second interval packet counters for both errored and good packets. Finally, the AQR405 is able to generate all of the IEEE test mode patterns, as well as CRPAT generation and checking in both line and system directions. It also supports (via the API) the ability to generate an eye diagram for each of the receive lanes. RXAUI and On the KR interfaces, the AQR405 supports x9, x31, square wave, and pseudo-noise generation and checking, as well as CRPAT generation and checking. 1.8 API & Programming Tools Associated with the AQR405 are the following software tools: Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 6 1) A set of ANSI C register structures for each MMD that provide bit level and word level access to all of the AQR405 registers. Documentation for these structures are found in the API document[12]. en tia l 2) An ANSI C API that provides a set of structures and associated Set / Get functions to implement all normal PHY operations. This API is written with register name abstraction so the registers are visible, and it is documented using Doxygen, which allows users to view the code and click on a variable to get the datasheet definition. This API also contains functions to burn new FLASH images, as well as perform MDIO boot-load operations, etc. Documentation for this is found in the API document[12]. 1.9 MACsec Co nfi d The AQR405 supports integrated MACsec at all rates. It supports two modes of operation: 1) Autonomous Operation: In this mode, the AQR405 does all of the gap insertion, etc. required to add the MACsec headers and integrity check values (ICVs). It does this via two integrated MACs and 64KB of buffering in each direction. These MACs monitor the buffer fill-depths, and generates port-based PAUSE frames in either direction as required. It also responds to port-based PAUSE frames. 802.1Qbb class-based PAUSE frames are passed through. Str ict ly 2) Cut-through Operation: In this mode, the AQR405 expects to receive packets from the system pre-gapped, and all the AQR405 does is insert the MACsec headers and ICVs. 3) Bypass Operation: In this mode the MACsec block is completely bypassed, in scenarios where MACsec in the PHY is not necessary. 1.9.1 General Features The MACsec supports the following general features: 1) AES-256, AES-128, and clear operation with simultaneous mixed usage, where the encryption and decryption are decided on a per-packet basis based on an access control list (ACL) that looks either at the MACsec header or fields in the packet header (explicit or implicit secure channel identification). Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 7 2) 16 secure channels (SCs), with two security associations (SAs) per SC with automatic roll-over between SAs on a programmable packet number (PN) value. 3) Full support of the 802.1AE[7] MIB 4) Per packet Galois counter mode (GCM) authentication on the ICV (16 or 32 byte). en tia l 5) Strict and out-of-order replay checking with a per SC programmable 32-bit (i.e from 0 to 231-1 packets) replay window for out-of-order mode. 6) A programmable confidentiality offset per SA of between 0 and 127 bytes offset. Name Description Ingress Control Packets The number of ingress control packets received Ingress Untagged Hit Packets The number of ingress untagged packets received that passed the implicit SCI lookup Ingress Untagged Miss Packets The number of ingress untagged packets received that had no implicit SCI lookup Str ict ly Per SA Co nfi d 7) A MIB containing the following additional statistics counters: Ingress Hit Packets Dropped The number of ingress packets that passed the SCI lookup, but were tagged for Drop Ingress Tagged Packets The number of ingress packets with a MACsec header Ingress Tagged Packets Bad Tag The number of ingress packets with an invalid SecTag or packet number (PN). Ingress Tagged Packets SCI Miss The number of ingress tagged packets with a missing SCI or an SCI that was not in the table. Ingress Tagged Non-Operational SA The number of ingress packets with an identified, but non-operational SA. Packets Table 1.1 Additional ingress MACsec statistics Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 8 Per SA Name Ingress Fail Authentication Ingress Packets Replay Fail The number of ingress packets that fail the replay check Ingress Packets Late The number of ingress packets that fail the replay check because they are late Ingress Packets OK Ingress Reserved Counter 0 Ingress Reserved Counter 1 Ingress Reserved Counter 2 The number of ingress packets that pass all checks Co nfi d Ingress Reserved Counter 3 The number of ingress packets that fail authentication en tia l Packets Description Table 1.1 Additional ingress MACsec statistics Per SA Description Egress Control Packets The number of egress control packets transmitted Egress Packets Unknown SA The number of egress packets transmitted with an unknown SA (Table Miss and Untagged) Egress Untagged Packets The number of egress packets transmitted without a MACsec header Egress Protected Packets The number of egress packets transmitted with a valid ICV (authenticated + encrypted) Str ict ly Name Table 1.2 Additional egress MACsec statistics 1.9.2 Ingress Lookup On ingress, the MACsec block can: 1) Remove the MACsec header 2) Strip zero-padded bytes for runt packets 3) Corrupt the FCS for any failed packets Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 9 4) Run a consistency check against another ACL 5) Count control packets 6) Enforce maximum MTU sizes via either truncation or FCS corruption. 7) Generate an interrupt on security failure a) MAC DA - 48 bits b) MAC SA - 48 bits c) Payload Ether-Type - 16 bits en tia l 8) Lookup up the implicit SCI based on the following fields: Co nfi d d) QTAG_VLD and STAG_VLD (Ingress Consistency Check only) e) TCI / AN - 8 bits (Note TCI needs preprocessing as per Clause 9.1.2) f) SCI - 64 bits g) VLAN - 12 bits (Ingress Consistency Check only) h) Any four programmable bytes within the first 64 bytes of the packet Str ict ly i) Origin (loopback versus front panel) - ingress table only j) Valid bit 9) Lookup up the implicit SCI based on the following fields: The MACsec block for the AQR405 shall support the ability to calculate the Ethertype, VLAN, and User-Priority of a packet using a 32 bit mapping table that is provided with each entry in the SCI lookup. There Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 10 is one mapping table per port. The mapping table contains the following fields: Bit Name Function PARSE_QTAG Enable parsing 802.1Q VLAN tags 30 PARSE_STAG Enable parsing 802.1Q MST tags 29 PARSE_QINQ Enable Q-in-Q parsing 28 QTAG_UP_EN 27 STAG_UP_EN DEF_UP 23:0 MAP_TBL Enable the use of the 802.1Q priority Enable the use of the 802.1S priority Default user-priority Priority mapping for 802.1Q priority tags Co nfi d 26:24 en tia l 31 Table 1.3 "Per SCI" 32-bit mapping table Str ict ly Ethertype, VLAN, and User-Priority of a packet are determined as follows (using this mapping table): Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 11 a) Ethertype and VLAN resolution is determined as shown in Figure 1.2. Here the 802.1S and 802.1Q EtherTypes are provisionable per (ETH_TYP == 802.1Q) && PARSE_QTAG No QTAG_VLD = 1 TMP_UP = 802.1Q PCP VLAN = 802.1Q VID ETH_TYP = Next Ethertype en tia l ETH_TYP = Ethertype (ETH_TYP == 802.1S) && PARSE_STAG ((ETH_TYP == 802.1S) && PARSE_STAG) || ((ETH_TYP == 802.1Q) && PARSE_QTAG) STAG_VLD = 1 TMP_UP = 802.1Q PCP VLAN = 802.1Q VID ETH_TYP = Next Ethertype Co nfi d Done Yes ETH_TYP = Next Ethertype Done ((ETH_TYP == 802.1S) && PARSE_STAG) || ((ETH_TYP == 802.1Q) && PARSE_QTAG) ETH_TYP = Next Ethertype Done Str ict ly Done Done Figure 1.2 Ethertype and VLAN parsing algorithm port. b) User priority is resolved as shown in Figure 1.3: 10)Support a provisioned definition of the 802.1Q and 802.1S Ethertype tags. 11)Support the following actions from the SCI lookup: a) Decrypt / Authenticate (provisioned per SA) b) Drop Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 12 STAG_VLD && STAG_UP_EN Yes UP = TMP_UP Done No Yes UP = MAP_TBL >> (3*TMP_UP) &0x7 No UP = DEF_UP Done en tia l QTAG_VLD && QTAG_UP_EN Done c) Bypass Co nfi d Figure 1.3 User priority resolution d) Re-direct (capture to debug) 12)Support globally changing the action for the lookup on a table basis (for allowing rapid debug). 1.9.3 MACsec Ingress Post-Processing After decryption during post-processing, the MACsec block can: Str ict ly 1) Remove or leave the MACsec header 2) Over-write the PN field of the MACsec header with provisionable data when operating in MACsec header non-removal mode. 3) Strip zero-padding bytes from the packet according to the MACsec header short-length (SL) field. 4) Grow short packets that are not SL stripped back to 64-bytes (i.e. MACsec packet is >= 64 bytes, but after removal of the MACsec, the packet is sub-64 bytes). 5) Support the corruption of the FCS on packets which fail any enabled security check in both the ingress and egress directions. 6) Support a 32 entry per port consistency check after decryption based on: Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 13 a) SAI_HIT b) SAI[3:0] c) VLAN[11:0] d) VLAN_VLD f) Payload Ethertype[15:0] en tia l e) ETYPE_VLD (Ethertype > Programmable max length) g) Each of these fields shall be maskable and have a single action bit indicating whether to drop the packet or not. Co nfi d h) The port shall also support a 33rd entry indicating what to do with a miss. 7) Generate an interrupt on security failure 1.9.4 Egress Processing On egress, the MACsec block can: 1) Support the same lookup and mapping mechanism as is used in the ingress direction. Str ict ly 2) Support the ability to perform lookup with and without the presence of a MACsec header. 3) Zero pad short packets and mark the SL field in the MACsec header accordingly. 4) Fill in the remainder of the MACsec header, given provided TCI and SL fields. This means that the MACsec EtherType (88_E5), AN, PN, and optional SCI are filled in by the PHY. 5) Support the following actions from the SCI lookup: a) Encrypt / Authenticate (provisioned per SA) b) Drop c) Bypass Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 14 d) Re-direct (loopback or capture to debug) 6) Count control packets 7) Enforce maximum MTU sizes via either truncation or FCS corruption. 8) Support globally changing the action for the lookup on a table basis (for allowing rapid debug). 1.9.5 MACs The MACs in the MACsec block can: en tia l 9) Generate an interrupt on security failure Co nfi d 1) Support ingress and egress MIBs with per-Ethertype 40-bit counters and RMONs (packet drop and packet pass-through). 2) In store-and-forward mode shall support port-based PAUSE flow-control in both directions, with programmable thresholds and hysteresis. 3) Ignore 802.1Qbb class-based PAUSE frames and pass them through the PHY. 4) Support programmable ingress and egress inter-packet gap (IPG) of between 4 and 63 bytes. Str ict ly 5) Support processor access to the MAC buffers for debug. 6) Support the ability to recognize control packets via the following criteria: a) MAC_DA[47:4] = 01_80_C2_00_00_0 b) MAC_DA[47:4] = 01_00_0C_CC_CC_CC c) 8 per port programmable MAC_DA addresses d) 8 per port programmable Ethertype matches e) 1 per port programmable MAC_DA with Don't Care mask With each packet having a fixed 7-byte preamble and 1-byte start-of frame delimiter (SFD). Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 15 f) 2 sets of per port programmable MAC_DA and Ethertype combinations These shall be provisionable on a port by port basis. 7) Support sending and receiving up to 512 byte packets in both the ingress and egress directions. en tia l Both the ingress and egress ports shall each support a programmable MAC address, and the ability to disable operation of these ports. Co nfi d 8) Support a non-destructive L2 system loopback, with a programmable MAC address and an enable. This loopback FIFO shall be 512 bytes in size and shall support head and tail drop (provisionable). This FIFO shall be capable of being stopped at any time (on a packet by packet granularity) and the packet(s) within read out. The depth of this FIFO shall be programmable. Packets larger than a programmable size can be dropped or truncated (programmable). Packets which are dropped due to overflow must be counted on a per SA basis using an 8-bit counter (saturating, clear-on-read). These looped-back packets must be accounted for in a similar set of counters to the ingress MAC, as they are not accounted for there (i.e. loopback after ingress MAC). 9) Enforcing a per priority, programmable maximum MTU size with an option for either truncation or FCS corruption. Str ict ly 10)Support the following statistics on ingress and egress: Egress Ingress Per Priority Name Description Total Packets The total number of packets (good + bad) Total Packets (per priority) The total number of packets (good + bad) (per priority) Dropped Packets Packets dropped for any reason Dropped Packets (per priority) Packets dropped for any reason (per priority) Bytes Total frame octets Bytes (per priority) Total frame octets (per priority) Table 1.4 MAC statistics Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 16 Ingress Per Priority Name Broadcast Packets Total broadcast packets with a good FCS Multicast Packets Total multicast packets with a good FCS Fragments Frames < 64 bytes with a bad FCS Jabbers Frames > MTUMAX with a bad FCS CRC Align Errors Bad Packets Good Packets Description en tia l Egress Frames with a bad FCS that are neither fragments nor jabbers in-the-clear Frames with a bad FCS Frames with a good FCS Undersize Packets 64 Byte Packets The total number of packets (good + bad) of 64 byte length 65 To 127 Byte Packets The total number of packets (good + bad) between 65 and 127 byte length 128 To 255 Byte Packets The total number of packets (good + bad) between 128 and 255 byte length Str ict ly Co nfi d Frames with a good FCS less than 64 bytes 256 To 511 Byte Packets The total number of packets (good + bad) between 256 and 511 byte length 512 To 1023 Byte Packets The total number of packets (good + bad) between 512 and 1023 byte length 1024 To 1518 Byte Packets The total number of packets (good + bad) between 1024 and 1518 byte length 1519 To 1522 Byte Packets The total number of packets (good + bad) between 1519 and 1522 byte length 1523 To 1548 Byte Packets The total number of packets (good + bad) between 1523 and 1548 byte length Table 1.4 MAC statistics Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 17 Ingress Per Priority 1549 To 2000 Byte Packets The total number of packets (good + bad) between 1549 and 2000 byte length 2001 To 2500 Byte Packets The total number of packets (good + bad) between 2001 and 2500 byte length 2501 To MTU Byte Packets The total number of packets (good + bad) between 2501 and MTU byte length in-the-clear 1549 To MTU Byte Packets The total number of packets (good + bad) between 1549 and MTU byte length in-the-clear Oversize Packets (per priority) The total number of packets of length greater than MTU bytes and a good FCS in-the-clear MAC Control Packets MAC Control Frames with EtherType 88_08 in-the-clear or secured (option for both) Errored Packets Packets with Code or Symbol Errors Description Co nfi d Name en tia l Egress Table 1.4 MAC statistics Str ict ly 11)Count MAC control packets that are either secured, unsecured, or both. 1.10 Energy Efficient Ethernet The AQR405 provides support for EEE on KR, RXAUI, 10GBASE-T, 5G, 2.5G, and 1000BASE-T interfaces. It is also capable of running in both normal operating mode, where the system controls entering and exiting from the EEE state, and autonomous operation on the line, where the PHY will control entering and exiting EEE operation via a provisionable "no-traffic" timer. If no traffic is seen within a certain period of time, the PHY will go to sleep on the line if connected at either 10G or 1G rates. This mode of operation requires the MACsec buffers and MACs to be in operation, as rate pacing during startup is done via PAUSE frames. 1.11 Precision Time Protocol (PTP) The AQR405 provides support for PTP and related protocols. Specifically it supports the following protocols (running both over MACsec or in the clear): 1) 1588 Version 1 (1 step and 2 step) Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 18 2) 1588 Version 2 (1 step and 2 step) 3) NTP Version 3 4) NTP Version 4 5) SNTP Version 4 1) A 48-bit seconds counter en tia l To support these protocols, the AQR405 has the following counters: 2) A 32-bit nanoseconds counter. Note that since 109 = 0x3B9ACA00, only 30 bits of this counter actually count. 3) A 32-bit fractional nanoseconds counter (LSbit = 2-32 ns) Co nfi d 4) A programmable increment sufficient to add the correct amount of nanoseconds and fractional nanoseconds to the counter each reference clock cycle. (i.e. if you are running on a 200 MHz clock, the increment should nominally be 5 ns per cycle, hence only 3 nanosecond bits and 32 fractional nanosecond bits are required). All of these counters support the ability to be hitlessly altered. Str ict ly Ingress timestamping accuracy in the AQR405 is rounded to 16 fractional nanosecond bits (48 + 32 + 16 = 96 bits). This timestamp is appended to the packet (or placed in the packet preamble when operating in USXGMII mode) and the packet's header and FCS are altered accordingly. The packet can then be passed to the system interface, or placed in a 512 byte FIFO that can be accessed from the MDIO registers space. A similar FIFO in the egress direction supports the ability to send sync packets into the data stream. The MACsec buffers and associated MACS must be operating for this to work. In order to support asymmetry between the Tx and Rx path, the AQR405 supports a correction register to offset the timestamps by the required amount. The AQR405 also supports the following PTP features: 1) Running the PTP clocks from the received line clock 2) Running the PTP clocks from an external (up to) 400 MHz LVDS clock input. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 19 Str ict ly Co nfi d en tia l 3) Transparent clock mode Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Str ict ly Co nfi d en tia l 20 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Hardware Interfaces 2- 2.1 Management Interface Interrupt* Pin Name(s) INT_N Pin Number(s) K18 Type OD Description The 2.5V tolerant open-drain interrupt signal from PHY 0 of the AQR405. On reset this is set high. This input can be driven to work at 1.2V via the MDIO_1P2_SELECT_N pin, regardless of the voltage on VDD_IO. en tia l Signal Name This open-drain 20 mA output is on the VDD_IO domain. MDIO Data ADDR1, ADDR3, MDC K15, J15, J16, H16, G17 J18 MDIO I Co nfi d MDIO Clock ADDR0, ADDR2, ADDR4 I L18 I/O Str ict ly MDIO Address The logic inputs to set the MDIO PHY address of the AQR405. These inputs are on the VDD_IO domain and have pull-ups associated with them. The MDIO clock input for the AQR405. This input is on the VDD_IO domain. The MDIO data line (w/ Schmitt triggered logic levels) for the AQR405. On reset this is set to high-impedance. This tri-state 20 mA I/O is on the VDD_IO domain. Table 2.1 Management Interface signals Table Conventions: any signal name that ends with "*" or pin name that ends with "_N" are active low. 21 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 22 Signal Name Reset Out* Pin Name(s) RST_OUT_N Pin Number(s) H3 Type OD Description The open-drain reset output from the AQR405. This may be used to drive the power-up reset signal for a board, as it outputs the on-chip power-up reset signal from the AQR405. J4 I TX_EN F5 I Str ict ly Tx Enable RST_N Co nfi d Reset* en tia l This open-drain 20 mA output is on the VDD_IO domain. The hard reset input (w/ Schmitt triggered logic levels) for the AQR405. This input can be driven to work at 1.2V via the MDIO_1P2_SELECT_N pin, regardless of the voltage on VDD_IO. This input is on the VDD_IO domain and has a pull-up associated with it. When pulled low, this input disables the output line drivers on the AQR405, and guarantees less than -53 dBm output power. This input can be driven to work at 1.2V via the MDIO_1P2_SELECT_N pin, regardless of the voltage on VDD_IO. This input is on the VDD_IO domain and has a pull-up associated with it. Table 2.1 Management Interface signals The management interface on the AQR405 is a two wire interface with a unidirectional MDC clock and a bidirectional MDIO data. The MDIO interface on the AQR405 is a robust implementation of this standard. It is designed to operate up to 10.5 MHz and is capable of withstanding voltages up to double the operating voltage (the theoretical worst-case maximum reflection on an unterminated bus). It utilizes a Schmitt-trigger in conjunction with a debounce state machine to debounce the signals, and is capable of hot-insertion. The This is a function of whether the output is set to push-pull or open-drain mode, and on the capacitance of the bus. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 23 data line is capable of pulling low a 280 load tied to 1.2V, and may be configured to support either open-drain, or push-pull operation in "Global General Provisioning 2: Address 1E.C441". Push-pull is the default operating mode. en tia l In order to provide flexibility to the implementation, the AQR405 utilizes a programmable I/O voltage. The logic thresholds for the I/O are set at 70% and 30% of VDD_IO for VIH/VOH and VIL/VOL respectively. For 1.2V MDIO operation (affects MDC, MDIO, INT_N, RST_N) a separate signal called MDIO_1P2_SELECT_N is provided that will force 1.2V operation on these signals, regardless of the VDD_IO voltage. Co nfi d The management interface allows communication between the Station Management (STA) and a physical layer device (PHY). The STA is the external host controller which is the master of the management interface bus. Consequently, it always sources the MDC clock. When the MDIO is sourced by the STA, the PHY will sample the MDIO at the rising edge of MDC. When the MDIO is sourced by the PHY during read operations, the STA will sample the MDIO at the rising edge. Table 2.2 shows the management interface frame format (802.3-2005 45.3). The PRE ST OP PHYAD MMDAD TA Address 1...1 00 00 PPPPP EEEEE 10 AAAAAAAAAAAAAAAA Z Write 1...1 00 01 PPPPP EEEEE 10 DDDDDDDDDDDDDDDD Z Read 1...1 00 11 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z Post-read increment address 1...1 EEEEE Z0 DDDDDDDDDDDDDDDD Z Str ict ly Frame 00 10 PPPPP Data IDLE Table 2.2 MDIO frame format fields are described below: IDLE (idle condition): The idle condition on the management interface is a high-impedance state. All tri-state drivers are disabled and the pull-up resistor(s) on the MDIO bus will pull the MDIO line to a one. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 24 PRE (preamble): en tia l Normal Operation: At the beginning of each transaction, the station management entity will send a sequence of 32 contiguous ones on the MDIO data line, along with 32 corresponding cycles on the MDC to provide the MMD with a pattern that it can use to establish synchronization. Each MMD will observe a sequence of 32 contiguous one bits on MDIO with 32 corresponding cycles on MDC before it responds to any transaction. ST (start of frame): Co nfi d Preamble Suppression: The MDIO interface can optionally disable preamble detection by setting the "MDIO Preamble Detection Disable" bit in "Global General Provisioning 2: Address 1E.C441". In this mode of operation, one or more preamble bit are required followed by the 0x0 start of frame ST bits. The start of frame for indirect access cycles is indicated by the <00> pattern. This pattern assures a transition from the default one and identifies the frame as an indirect access. Frames that contain the ST=<01> pattern defined in Clause 22 will be ignored by the MMDs within the AQR405. OP (operation code): Str ict ly The operation code field indicates the type of transaction being performed by the frame. A <00> pattern indicates that the frame payload contains the address of the register to access. A <01> pattern indicates that the frame payload contains data to be written to the register whose address was provided in the previous address frame. A <11> pattern indicates that the frame is read operation. A <10> pattern indicates that the frame is a post-read increment address operation. PHYAD (PHY address): The PHY address is five bits, allowing for 32 unique PHY addresses, and hence up to 32 PHYs on an MDIO bus. (The address of the PHY is determined from the ADDR[4:2] pins). The first PHY address bit to be transmitted and received is the MSB of the address. The station management entity must have a priori knowledge of the appropriate PHY address for each PHY to which it is attached, whether connected to a single PHY or to multiple PHYs. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 25 MMDAD (MMD address): The MMD address is five bits, allowing for 32 unique MMDs per PHY. The first MMD address bit transmitted and received is the MSB of the address. en tia l In addition the AQR405 supports a broadcast mode when the PHYAD is 0x00. Only the write and load address opcodes are supported in broadcast mode. Read and post-read increment opcodes are ignored in broadcast mode. This mode of operation can be enabled via the "MDIO Broadcast Mode Enable"bits ("Global General Provisioning 2: Address 1E.C441". TA (turnaround): Co nfi d The turnaround time is a 2-bit time spacing between the MMD address field and the data field of a management frame to avoid contention during a read transaction. For a read or post-read increment address transaction, both the STA and the MMD remain in a high-impedance state for the first bit time of the turnaround. The MMD then drives a zero bit during the second bit time of the turnaround of a read or post-read increment address transaction. During a write or address transaction, the STA transmits a one for the first bit time of the turnaround and a zero for the second bit time of the turnaround. This behavior is shown in Figure VIL MDIO Line VIH VIL <MMD Address[0]> <Z> Str ict ly MDC* <MMD Address[1]> VIH MDIO Driven by STA <0> Data[15] MDIO Driven by PHY MMD Figure 2.1 MDIO bus turn-around during Read operations 2.1: ADDRESS / DATA: The address/data field is 16 bits. For an address cycle, it contains the address of the register to be accessed on the next cycle. For the data cycle of a write frame, the field contains the data to be written to the register. For a read or post-read increment address frame, the field Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 26 contains the contents of the register. The first bit transmitted and received shall be bit 15. For counters that are greater than 16-bits, the LSW must be read first, then the MSW must be read immediately afterwards. When the LSW is read, the counter is cleared and the MSW is stored in a shadow register. Reading the MSW actually reads the shadow register. en tia l Optionally the host may read the MSW first, then the LSW immediately afterwards by setting the "MDIO Read MSW First Enable"bit in "Global General Provisioning 2: Address 1E.C441". 2.1.1 Interrupt The AQR405 supports an open-drain interrupt pin per PHY. This signal conforms to the XENPAK LASI signal requirements. Co nfi d 2.1.2 Reset The AQR405 supports an active-low reset input that conforms to the XENPAK Reset* requirements. In addition to this, the AQR405 is capable of generating a RST_OUT_N signal from its internal power-on reset generation circuitry that can be used by the external board circuitry. Operation of the reset machinery is as follows: Str ict ly 1) Release from the Reset state begins when the RST_N input is high, and all of the core power supplies are above their required thresholds. These thresholds are listed below: 2) Once all of the conditions for release from Reset are true, a 20ms timer will engage, the purpose of which is to allow the supplies to settle prior to allowing the PHY to boot 3) After the 20ms timer has completed, hardware state machines designed to guarantee PLL and band-gap stability engage. 4) After the PLLs and band-gap are locked and functioning properly, the processor and digital circuitry are released from reset. Note that there are no timing requirements on issuance of reset relative to the clock Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 27 Supply Parameter Min Max Units Power-on reset threshold for VA22 DC supply 1.70 1.80 V VA12 Power-on reset threshold for VA12 DC supply 0.93 0.99 V VDD Power-on reset threshold for VDD DC supply 0.56 0.60 V en tia l VA22 Table 2.3 Power-on reset thresholds for core supply voltages 5) The PHY image is then loaded (either via the daisy-chain, or through MDIO boot-load) and the processor boots. Co nfi d 6) After the processor boots, any provisioned register values are set, and the PHY enters the provisioned operating state. 7) Once this is complete, the processor raises the MMD reset bits and sets the Reset Completed alarm, indicating it has completed reset and is ready for operation. 2.1.3 Configuration Str ict ly The AQR405 contains a number of static configuration pins which are used to set the power-up operation of the AQR405. These signals are: 1) MDIO Address (ADDR[4:2]) In the AQR405 package, the MDIO addressing is tied off internally so that the LSBs increment according to the PHY number in the package. This MDIO address can either be overridden via a register in the Global MMD via provisioning, or the incrementation order can be altered via the INV_ADDR[1:0] pins which are exclusive OR'd with their respective address pins. 2.2 Serial FLASH The AQR405 is capable of three modes of boot operation: 1) Daisy-chain master 2) Daisy-chain slave 3) MDIO boot-load Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 28 Signal Name Daisy-chain Clock Input Pin Name(s) RX_DC_CLK Pin Number(s) J1 Type I Description The daisy chain receive serial clock. This signal travels away from FLASH. This input is on the VDD_IO domain and has a pull-down associated with it. TX_DC_CLK N18 O The daisy chain transmit serial clock. This signal travels away from FLASH. en tia l Daisy-chain Clock Output This 20 mA output is on the VDD_IO domain. Daisy-chain Master* Daisy-chain Reset* Input Daisy-chain Reset* Output H1 TX_DC_DATA M17 DC_MASTER_N RX_DC_RST_N TX_DC_RST_N I Co nfi d Daisy-chain Data Output RX_DC_DATA E1 Str ict ly Daisy-chain Data Input N17 H2 O I The daisy chain receive serial data. This signal travels away from FLASH. This input is on the VDD_IO domain and has a pull-down associated with it. The daisy chain transmit serial data. This signal travels away from FLASH. This 20 mA output is on the VDD_IO domain. The daisy-chain mode control: 0 = Daisy Chain Master, 1 = Daisy Chain Slave. This input is on the VDD_IO domain and has a pull-up associated with it. I The daisy chain receive reset. This signal travels towards FLASH. This input is on the VDD_IO domain and has a pull-up associated with it. O The daisy chain transmit reset. This signal travels towards FLASH. This 20 mA output is on the VDD_IO domain. Table 2.4 Serial FLASH signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 29 Signal Name Daisy-chain Start-of-Fram e Input Pin Name(s) RX_DC_SOF Pin Number(s) J2 Type I Description The daisy chain receive start of frame. This signal travels away from FLASH. This input is on the VDD_IO domain and has a pull-down associated with it. TX_DC_SOF M18 O The daisy chain transmit start of frame. This signal travels away from FLASH. en tia l Daisy-chain Start-of-Fram e Output This 20 mA output is on the VDD_IO domain. SPI Serial Input Data SPI Serial Output Data G2 O Co nfi d SPI Serial Clock CE_N SCLK G1 SIN F1 Str ict ly SPI Chip Enable* SOUT F2 O I The SPI CE* signal from the AQR405 to the serial FLASH. On reset this is set high. This 20 mA output is on the VDD_FLASH domain. The SPI clock from the AQR405 to the serial FLASH. On reset this is set low. This 20 mA output is on the VDD_FLASH domain. The SPI input data from the serial FLASH to the AQR405. This input is on the VDD_FLASH domain and has a pull-up associated with it. O The SPI output data from the AQR405 to the serial FLASH. On reset this is set low. This 20 mA output is on the VDD_FLASH domain. Table 2.4 Serial FLASH signals When functioning in Daisy-chain master mode, the AQR405 has an attached SPI FLASH, and the PHY's firmware image is loaded from the FLASH. When functioning in Daisy-chain slave mode (see Section 2.2.1), a series of PHYs are strung together in a daisy-chain, with one functioning as the master with an attached FLASH device, and the others (the Daisy-chain slaves) receiving their firmware image from the Daisy-chain master. In both cases, integrity checking of the loaded image is performed in hardware via a CRC embedded in the image, and Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 30 if there is an error, a reload is automatically requested. When functioning in MDIO boot-load mode, no FLASH device is required. Instead, the firmware image is loaded via the MDIO interface, and integrity checking of the loaded image is performed via a hardware CRC function on the memory interface. In order to use MDIO boot-load, the boot-load functions from the API should be carefully studied, or utilized verbatim. 2.2.1 SPI FLASH Interface en tia l The SPI interface is responsible for connecting the AQR405 to the external FLASH memory device. The microcontroller on the AQR405 will access the boot code and AQR405 default register values from the FLASH memory after power-on reset. This FLASH memory is also accessible via the MDIO interface for firmware updates and manufacturing burn via the API, or via the registers in the Global MMD. PHY SCLK Co nfi d The SPI interface is a four wire, unidirectional, serial bus as shown in Figure 2.2. It is composed of a serial clock output "SCLK", a serial data output "SOUT", a serial data input "SIN", and a chip-select "CE*". All the signals are unidirectional. SOUT CE* SI CS* SO Str ict ly SIN NVR SCK Figure 2.2 SPI Interface Block Diagram The AQR405 is set up to function as a Mode 0 (0,0) SPI device, which means that the clock defaults to zero when not bursting. Data on this interface, for both SIN and SOUT, is always sourced on the falling edge of SCLK, and sampled on the rising edge of SCLK. Figures 2.3 - Figures 2.5 show typical read, burst read, and write operations for the AQR405. In all of these scenarios, the API or the NVR interface in the Global MMD is used to access the FLASH. The NVR interface in the AQR405 is designed to be able to output any arbitrary opcode, followed by a programmable zero to three address bytes, followed by a programmable zero to four data bytes. This allows any variation of opcodes to be Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 31 CS* 0 SCLK 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 Mode 0 1 1 SIN A2 0 0 0 0 0 0 A1 A0 Opcode = 0x3 Dn SOUT Dn+1 Dn+2 Dn+3 CS* 0 SCLK 1 2 3 4 5 6 7 8 15 16 23 24 31 32 Mode 0 1 1 SIN A2 0 0 0 0 0 0 A1 en tia l Figure 2.3 SPI read A0 Opcode = 0x3 39 40 Dn SOUT 47 48 55 56 Dn+2 Dn+1 63 Dn+3 Gap 64 65 66 Bit 7 6 5 Dn+4 CS* 0 SCLK 7 8 15 16 Mode 0 SIN 0?2 PGM Co nfi d Figure 2.4 SPI Burst read A2 SOUT 23 24 A1 31 32 A0 39 40 Dn 47 48 Dn+1 55 56 Dn+2 63 Dn+3 Gap 64 65 66 Bit 7 6 5 Dn+4 Figure 2.5 SPI burst write Str ict ly output to the attached FLASH device. This interface also supports a burst read and write mode, which keeps the CS* line pulled low to enable back-to-back reads and writes. To support this, the NVR interface supports two 16-bit address registers and two 16-bit data registers, which allows up to 4 data bytes in a burst over the SPI interface. In order to extend this to longer bursts, the AQR405 halts the clock after the last bit in the data burst allowing the host processor to load another block of data to / from the NVR interface. This is shown in Figures 2.4 - 2.5 and allows the data burst to be extended by as many bytes as necessary, without outstripping the MDIO's I/O capabilities.Note that typical NVRs require that writing be performed on a block basis, and thus the addresses usually wrap within the block being programmed. As such, it is desirable from a speed and efficiency perspective to attempt to write entire blocks, versus pieces of blocks. In order to assure that no polling is required on NVR interface, it is recommended that the NVR clock speed be set to at least: Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 32 64 f SCLK > ------ f MDIO 63 The desired FLASH memory should be chosen to be at least 512K bytes in size, and must be capable of interfacing to a 2.5V CMOS SPI. 2.2.2 Daisy-chain Operation Co nfi d en tia l In an effort to reduce BOM costs and have multiple chips share a single FLASH device, the AQR405 supports the direct loading of firmware from a daisy-chained FLASH image to the PHYs internal instruction and data RAM. Operation of the FLASH daisy-chain is shown in Figure 2.6. Here, the FLASH image from a daisy-chain master chip, which has an external FLASH device attached, is streamed along a daisy-chain to slave chips which do not have an external FLASH. These slave chips will directly load their local processor's IRAM and DRAM from the streaming FLASH image as it is received, while at the same time forwarding the image to the next slave chip in the chain. On a micro-scale each chip contains a primary and secondary PHY. Only the primary PHY on the master chip is connected to the FLASH device. The secondary PHY is always daisy-chained to the primary PHY. Str ict ly The daisy-chain bus consists of a clock, data, and start of frame (SOF) signal. In the reverse direction, a daisy-chain reset signal is provided so that when a slave chip is reset, it has the ability to send a rebroadcast request to the daisy-chain master chip. The master chip will then reread the FLASH and re-stream the image onto the daisy-chain bus. Master PHY FLASH Data Clock SoF Data Clock SoF Slave PHY Daisy-chain Reset Slave PHY Daisy-chain Reset Figure 2.6 Daisy-chain operation When DC_MASTER_N is pulled low, the AQR405 will be in daisy-chain master This is derived from the fact that the longest burst instruction on the SPI is 64 bits, at one bit per clock, whereas to write a register on the MDIO takes 64 clocks, and the data is not written until the last bit - hence the 63. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 33 RX_DC_SOF RX_DC_DATA RX_DC_CLK TX_DC_RST_N TX_DC_SOF TX_DC_DATA TX_DC_CLK RX_DC_RST_N Rebroadcast Request en tia l Figure 2.7 Daisy-chain signals and direction of flow mode. In this mode, the AQR405 will load the FLASH image directly into PHY's IRAM and DRAM, while at the same time, streaming the FLASH image onto the daisy-chain bus to other PHYs which are configured as a daisy-chain slaves (DC_MASTER_N = 1). Description Co nfi d DC_MASTER_N 0x0 Daisy-chain master mode: indicates that this AQR405 has the attached FLASH and will stream the image when requested. 0x1 Daisy-chain slave mode: indicates that this AQR405 has no attached FLASH and will boot-load its image from the image streamed over the daisy-chain bus. Table 2.5 DC_MASTER_N Str ict ly In addition, each daisy-chain slave AQR405 will have the ability to assert its daisy-chain reset signal (which is AND'ed with the incoming daisy-chain reset signal) which travels in the reverse direction back to the daisy-chain master. This will cause the daisy-chain master chip to re-stream the FLASH image back onto the daisy-chain bus. The daisy-chain slave chip must assert the daisy-chain reset for a minimum of 100 ns. If a daisy-chain reset occurs in the middle of streaming a FLASH image, the daisy-chain master chip will complete streaming the image and then when it is finished, re-stream the image again. Load integrity of the image is guaranteed via a CCITT-16 CRC which is broadcast in the daisy-chain header data. Also contained in this header is a hop counter (PHY0 is the daisy-chain master and is hop-count #0, the second PHY in the daisy-chain is hop-count #1, on so on...) which is used to disambiguate devices in the Daisy-chain for firmware provisioning. In order to ensure that the daisy-chain bus and SPI FLASH interface are in synchronization, the SPI FLASH interface is rate paced so that it doesn't overrun the daisy-chain streaming rate. Similarly, the daisy-chain clock is gated to ensure that is does not outpace the read-rate of the FLASH. Granularity for rate-pacing is in blocks of 32 bits. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 34 2.2.3 Boot-load Regardless of whether the PHY is a daisy-chain master or slave, a new image can always be boot-loaded into the PHY's IRAM and DRAM via the MDIO interface. As well, if boot-load operation is desired as the product's standard operating mode, the FLASH can be depopulated, and the image always loaded on power up. For more information on this mode of operation, please consult the API documentation. en tia l 2.3 Firmware 2.3.1 Provisionable Default Co nfi d The AQR405 contains a 32-bit microcontroller. This microcontroller is designed to have it's IRAM and DRAM either loaded on power-up / reset from the attached FLASH, via the daisy-chain loading mechanism described in Section 2.2, or to have its boot image loaded by the host processor via the MDIO interface. Programming of the FLASH on the daisy-chain master device is done via the appropriate function in the API. Another feature of the AQR405 is the ability to change and store the default values of any field marked as "PD". A delta list of all defaults that are different from the hardware defaults are stored in the image, and upon power-up, the PHY's microprocessor will overwrite the hardware defaults with these new values. Provisioning these new default values is done using the Aquantia Default Provisioning tool, and PHYs are identified by hop count along the daisy-chain bus, allowing each PHY to be uniquely provisioned. Str ict ly 2.3.2 Gang-load In order to save time on MDIO boot-loading operations, the AQR405 supports a gang-load feature, whereby multiple AQR405 chips on a single MDIO bus may be simultaneously loaded with boot images. This is done by temporarily setting all of the device's MDIO addresses to be the same, loading the boot image, and then toggling the MDIO Address Reset bit in the Global register MMD. Again this can also be handled via the API. Another option is to enable MDIO broadcast on address 0. 2.4 SERDES The AQR405 SERDES interface is both robust and flexible, and provides numerous loopback and diagnostic capabilities which ease system interface-PHY board design and bring-up, as well as AC JTAG. The interface is capable of providing arbitrary lane swapping and inversion. In the transmit direction, there is a programmable 3 taps equalizer (1 precursor and 1 postcursor tap), as well as the ability to program the Tx drive strength, and Tx termination. In the receive direction, there is programmable gain and programmable boost. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 35 Signal Name Pin Name(s) Pin Number(s) Type Description RX_LN0_P, RX_LN0_N P2, P1 I Physical Lane 0 differential Rx of the AQR405 SERDES interface. This lane can operate in KR, RXAUI, XAUI, and SGMII mode. Lane 0 Tx TX_LN0_P, TX_LN0_N T2, T1 O Physical Lane 0 differential Tx of the AQR405 SERDES interface. This lane can operate in KR, RXAUI, XAUI, and SGMII mode. Lane 1 Rx RX_LN1_P, RX_LN1_N U2, V2 Lane 1 Tx TX_LN1_P, TX_LN1_N U3, V3 Lane 2 Rx RX_LN2_P, RX_LN2_N Lane 2 Tx Lane 3 Tx Physical Lane 1 differential Rx of the AQR405 SERDES interface. This lane can operate in XAUI, and SGMII mode. O Physical Lane 1 differential Tx of the AQR405 SERDES interface. This lane can operate in XAUI, and SGMII mode. U4, V4 I Physical Lane 2 differential Rx of the AQR405 SERDES interface. This lane can operate in KR, RXAUI, XAUI, and SGMII mode. TX_LN2_P, TX_LN2_N U6, V6 O Physical Lane 2 differential Tx of the AQR405 SERDES interface. This lane can operate in KR, RXAUI, XAUI, and SGMII mode. RX_LN3_P, RX_LN3_N U7, V7 I Physical Lane 3 differential Rx of the AQR405 SERDES interface. This lane can operate in XAUI, and SGMII mode. TX_LN3_P, TX_LN3_N U8, V8 O Physical Lane 3 differential Tx of the AQR405 SERDES interface. This lane can operate in XAUI, and SGMII mode. Co nfi d I Str ict ly Lane 3 Rx en tia l Lane 0 Rx Table 2.6 SERDES signals In SGMII mode, the interface operates at 1.25 Gb/s over SERDES logical Lane 0 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 36 and is compliant to the Cisco SGMII specification[10]. In 2500BASE-X mode, the interface operates at 3.125 Gb/s over any of the lanes. In RXAUI mode, the interface operates over Lanes 0 and 2 and is compliant to Marvell and Dune specifications. Since RXAUI is essentially a front-end MUX for XAUI, the XAUI registers are reused in RXAUI mode. In KR mode, two separate 10G interfaces are provided operating over Lanes 0 and 2. Test Description x9 PRBS x31 PRBS 9 5 x +x +1 x 31 28 +1 Clause 49.2.12 Pseudo-Noise CRPAT Generate Check Invert Co nfi d Square Wave +x en tia l The SERDES interface on the AQR405 also contains diagnostic pattern generation and checking functionality that is listed below: IEEE 802.3 Annex48A.4 Table 2.7 KR diagnostic pattern capabilities Test Description x7 PRBS 6 x23 PRBS x31 PRBS Check Invert x 15 +x 14 +1 x 23 +x 18 +1 x 31 +x 28 +1 Str ict ly x15 PRBS 7 x +x +1 Generate CRPAT IEEE 802.3 Annex48A.4 CJPAT IEEE 802.3 Annex48A.5 Table 2.8 RXAUI/XAUI diagnostic pattern capabilities The Lane 0 KR interface is dedicated to the optics lookaside port (i.e. facing towards the network), and the Lane 2 KR interface is dedicated to the system interface. Note that these are the only lanes that are connected in the AQR405. As such there are still references to Lanes 1 and 3 as well as XAUI in the register map, but these are not operational in the AQR405. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 37 Test Description Generate Check Invert CRPAT IEEE 802.3 Annex48A.4 Table 2.9 SGMII diagnostic pattern capabilities en tia l Another feature the AQR405 SERDES interface can provide is the eye-diagram mode, which allows the user to create an eye-diagram. To use this functionality, the appropriate API functions must be called. All of the parameters associated with the SERDES interface have provisionable default values, which means that the AQR405 SERDES interface can be tailored to power-up with the optimal settings for any given application. 2.5 SERDES Operating Modes Co nfi d For the purposes of this discussion, the AQR405 can be viewed as a set of blocks as shown below: On the left side of the diagram is the system interface, which consists of the two SERDES lanes. Lanes 0 and 2 have the ability to run at rates from 1.25 Gb/s to 10.3125 Gb/s. These lanes support SGMII, 2500BASE-X, RXAUI, and KR. In the AQR405 only two of the four SERDES lanes on the chip are actually run out, but these lanes are still referred to as Lane 0 and Lane 2. At the PCS layer, there are two SGMII cores, two KR cores, and one RXAUI core, even though only the two SGMII and KR cores are used. System I/F MDIO SRDS2 10G MDIO Management XAUI/RXAUI PCS 10G PCS KR/USXGMII PCS 0 5G PCS KR/USXGMII PCS 1 2.5G PCS SGMII PCS 0 1G PCS SGMII PCS 1 100M PCS MDIO Registers DSP SRDS0 10G SERDES Str ict ly From a system perspective, the two SGMII and KR PCS cores (designated SGMII0 / SGMII1 and KR0 / KR1 respectively) allow the chip to support a "look-aside" optical port. What this does is allow a common system interface with the ability to either go out on the MDI interface (copper) or go out the chip on the second KR interface (optical). This mode is shown below. MACSEC Figure 2.8 AQR405 operational blocks Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 DAC / THP THP THP Driver Precoder Precoder Precoder THP Hybrid THP THP Precoder Precoder Precoder THP A/D THP THP Precoder Precoder Precoder VGA & THP THP THP Filter Precoder Precoder Precoder A/D VGA & Filter LINE 38 NOTE!! The SGMII0 and KR0 cores are exclusively dedicated to the lookaside interface, and SGMII1 and KR1 cores are exclusively dedicated to the system interface. These different SERDES operating modes are summarized in Table 2.10. Operating Mode / Core Used Lane 0 RXAUI X Lane 3 X X KR1 SGMII0 X KR0 X Co nfi d Line Lane 2 X SGMII1 System Lane 1 en tia l Interface Table 2.10 SERDES lane assignments for different operating modes 2.6 SERDES System I/F Start-Up In start-up on the system interface side, there are four different operating scenarios for the SERDES I/F: a) 10G mode (KR or RXAUI) b) 1000BASE-X mode Str ict ly c) XSGMII mode d) USXGMII mode e) All-off mode These different modes affect only the system interface, and function independently of whether the MDI or KR-look-aside interface is selected. XSGMII is an extension of the Cisco SGMII protocol which informs the system interface what the PHY has autonegotiated as a rate. The XSGMII extension as proposed by Aquantia uses this same mechanism, but also informs of a 10G connection. After receiving acknowledgement of a 10G connection, the PHY will switch to the pre-configured 10G mode. For more details see "XSGMII" on page 42. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 39 2.6.1 10G Mode 1) In this mode, which is the hardware default, the AQR405 comes up in the pre-configured 10G mode (KR or RXAUI) and transmits Local Faults / Idles, and remains in this state until a connection to a link partner is established. en tia l 2) After connection to a link partner has been established, the AQR405 will either stay in the pre-configured 10G mode, or switch to 1000BASE-X mode, or 100M SGMII mode depending on that the autonegotiated line rate was. 3) Once the SERDES I/F has synchronized, traffic flows. Co nfi d 4) If the link fails and the system interface was in 10G mode, the AQR405 generates a Local Fault message towards the system I/F, effectively restarting. If the link had transitioned to 1G operation, the SERDES is restarted in 10G mode generating Local Faults / Idles. 5) Autonegotiation restarts after the link break timer expires. 2.6.2 1000BASE-X Mode 1) In this mode the AQR405 comes up in 1000BASE-X mode and transmits idles, and remains in this state until a connection to a link partner is established. Str ict ly 2) After a connection to a link partner has been established, the AQR405 will either stay in 1000BASE-X mode, or switch to the pre-configured 10G mode, or 100M SGMII mode depending on that the autonegotiated line rate was. 3) Once the SERDES I/F has synchronized, traffic flows. 4) If the link fails and the system interface was in the pre-configured 10G mode (KR or RXAUI), the AQR405 generates a Local Fault message towards the system I/F, and effectively restarts in 1000BASE-X mode, generating Idles. Otherwise the link just stays in 1000BASE-X mode generating Idles. 5) Autonegotiation restarts after the link break timer expires. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 40 2.6.3 XSGMII Mode 1) In this mode the AQR405 comes up in XSGMII mode. After sending and receiving an ACK on an XSGMII link-down autonegotiation message (see Table 2.11), the SERDES transmits Idles, and remains in this state until connection to a link partner is established. en tia l 2) After a connection to a link partner has been established, the AQR405 will send an XSGMII Link Up autonegotiation message with the appropriate rate (see Table 2.11) and receive an ACK. 3) Upon receiving the acknowledge from the system interface, the AQR405 will either switch to 100M SGMII mode, stay in 1G SGMII mode (essentially 1000BASE-X), or switch to the pre-configured 10G mode (KR or RXAUI), depending on whether the autonegotiated line rate was 1G / 100M or 10G. Co nfi d 4) Once the SERDES I/F has synchronized, traffic flows. Str ict ly 5) If the link fails and the AQR405 was in the pre-configured 10G mode, the AQR405 generates a Local Fault message towards the system I/F and then transitions back to XSGMII mode, where it sends and receives an ACK on an XSGMII link-down autonegotiation message and then resumes transmitting Idles. If the link fails and the AQR405 was in 1G SGMII mode, the AQR405 first sends and receives an ACK on an XSGMII link-down autonegotiation message and then resumes transmitting Idles, with no interruption in SERDES operation. If the system I/F was in 100M SGMII mode, the SERDES transitions back to XSGMII mode, where it sends and receives an ACK on an XSGMII link-down autonegotiation message and then resumes transmitting Idles. 6) Autonegotiation restarts after the link break timer expires. 2.6.4 USXGMII Mode 1) In this mode the AQR405 comes up in USXGMII mode. After sending and receiving an ACK on an USXGMII link-down autonegotiation message (see Table 2.12), the SERDES transmits Idles, and remains in this state until connection to a link partner is established. The SGMII autonegotiation machinery was derived from 1000BASE-X and involves exchanging 16 bit control words via /C and /I ordered sets. It was adopted for SGMII to solve the issue of how a copper SFP module would inform the system interface what rate it had autonegotiated on the line, without having an MDIO interface (SFP only supports ). Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 41 2) After a connection to a link partner has been established, the AQR405 will send an USXGMII Link Up autonegotiation message with the appropriate rate (see Table 2.12) and receive an ACK. 3) Upon receiving the acknowledge from the system interface, the AQR405 will either switch to the desired rate, depending on whether the autonegotiated line rate was 100M, 1G, 2.5G, 5G, or 10G. en tia l 4) Once the SERDES I/F has synchronized, traffic flows. 5) If the link fails, the AQR405 generates a Local Fault message towards the system I/F and then transitions back to USXGMII Idle mode, where it sends and receives an ACK on an USXGMII link-down autonegotiation message and then resumes transmitting Idles. 2.6.5 All-Off Mode Co nfi d 6) Autonegotiation restarts after the link break timer expires. 1) In this mode the AQR405 comes up with the system interface off, and remains in this state until connection to a link partner is established. 2) After connection to a link partner has been established, the AQR405 will either turn on 1000BASE-X, or turn on the pre-configured 10G mode (KR or RXAUI), or 100M SGMII mode depending on that the autonegotiated line rate was. Str ict ly 3) Once the SERDES I/F has synchronized, traffic flows. 4) If the link fails and was in the pre-configured 10G mode, the AQR405 generates a Local Fault message towards the system I/F and shuts off. Otherwise the system interface just shuts off. 5) Autonegotiation restarts after the link break timer expires. 2.6.6 Interrupts In all of these modes, the processor has the ability to generate an interrupt upon completing autonegotiation. The SGMII autonegotiation machinery was derived from 1000BASE-X and involves exchanging 16 bit control words via /C and /I ordered sets. It was adopted for SGMII to solve the issue of how a copper SFP module would inform the system interface what rate it had autonegotiated on the line, without having an MDIO interface (SFP only supports ). Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 42 2.6.7 XSGMII XSGMII is an extension of the SGMII interface and provides the signaling and control for moving to a 10G connection mode in addition to the SGMII rates of 1G, 100M, and 10M. XSGMII builds upon the existing specification for SGMII[10], and existing 10GE specifications defined in 802.3-2005[3]. en tia l The creation of XSGMII requires a minimal change to the existing SGMII specification: namely the addition of a 10G connect rate. Thus: 1) System interface and PHY connect and synchronize the SGMII 1.25 Gb/s 8B/10B SERDES link. Co nfi d 2) PHY uses Clause 28 autonegotiation over the MDI to establish a connection with the remote PHY, constrained by the abilities the local system interface communicated during 1, above. 3) PHY uses SGMII (Clause 37) autonegotiation to inform the system interface which rate it is selecting. 4) If a 10G connection is established, after receiving the acknowledgement from the system interface, the PHY switches over to 10G operation and traffic begins to flow after the 10GBASE-T training sequence is completed. Str ict ly 5) If a 100M or 1G connection is established, after receiving the acknowledgement from the system interface, the PHY stays in SGMII mode and traffic begins to flow after the link is established. The above sequence requires the modifications to Table 1 of the SGMII specification as shown in Table 2.11, with the modification indicated in red. 2.6.8 USXGMII USXGMII is an extension of the XFI interface and provides the signaling and control for moving to a 100M, 1G, 2.5G, and 5G connection mode in addition to the XFI rates of 10G. USXGMII builds upon the existing specification for XFI and existing 10GE specifications defined in 802.3-2005[3]. The creation of USXGMII requires a minimal change to the existing XFI specification: namely the addition of 100M, 1G, 2.5G, and 5G connection rates. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 43 tx_config_Reg[15:0] sent from the PHY to the system interface tx_config_Reg[15:0] sent from the system interface to the PHY 15 Link: 1 = link up, 0 = link down 0: Reserved for future use 14 Reserved for Auto-Negotiation acknowledge as specified in 802.3z 1 13 0: Reserved for future use 0: Reserved for future use 12 Duplex mode: 1 = full duplex (required) 0: Reserved for future use 11:10 Speed: Bit 11, 10 1 1 = 10 Gbps: 10GBASE-T, 10GBASE-R 1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 = 100Mbps: 100BASE-TX, 100BASE-FX 0 0 = 10Mbps: 10BASET, 10BASE2, 10BASE5 0: Reserved for future use 9:1 0: Reserved for future use 0: Reserved for future use 0 0 en tia l Bit Number 1 Co nfi d Table 2.11 XSGMII base page Thus: 1) System interface and PHY connect and synchronize the XFI 10.3125 Gb/s 64B/66B SERDES link. 2) PHY uses Clause 28 autonegotiation over the MDI to establish a connection with the remote PHY, constrained by the abilities the local system interface communicated during 1, above. Str ict ly 3) PHY uses SGMII (Clause 37) autonegotiation to inform the system interface which rate it is selecting. 4) If a 10G connection is established, after receiving the acknowledgement from the system interface, the PHY switches over to 10G operation and traffic begins to flow after the 10GBASE-T training sequence is completed. 5) If a 100M, 1G, 2.5G, or 5G connection is established, after receiving the acknowledgement from the system interface, the PHY stays in SGMII mode and traffic begins to flow after the link is established. Table 2.12 shows the USXGMII base page.. 2.7 MDI In 10G mode, the line interface on the AQR405 is capable of driving up to 100 m of CAT-6a unshielded twisted pair or 100 m of CAT-7 shielded cable (100 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 44 usxgmiiChannelInfo[15:0] sent from the PHY to the system interface usxgmiiChannelInfo[15:0] sent from the system interface to the PHY 15 Link: 1 = link up, 0 = link down 0: Reserved for future use 14 Reserved for Auto-Negotiation acknowledge 1 13 0: Reserved for future use 0: Reserved for future use 12 Duplex mode: 1 = full duplex (required) 0 = half duplex 0: Reserved for future use 11:9 Speed: Bit 11, 10, 9 0 0 0 = 10Mbps: 10BASET, 10BASE2, 10BASE5 0 0 1 = 100Mbps: 100BASE-TX, 100BASE-FX 0 1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X 0 1 1 = 10 Gbps: 10GBASE-T, 10GBASE-R 1 0 0 = 2500 Mbps: AQRATE 2.5G 1 0 1 = 5000 Mbps: AQRATE 5G 1 1 0 = Reserved 1 1 1 = Reserved 8 EEE capability: 1= supported, 0 = not supported 7 EEE clock stop capability: 1= supported, 0 = not supported 0: Reserved for future use 6:1 0: Reserved for future use 0: Reserved for future use 0 1 = USXGMII supported device en tia l Bit Number 0: Reserved for future use Co nfi d 0: Reserved for future use 1 Table 2.12 USXGMII base page Signal Name Pin Name(s) Pin Number(s) Type Description CM_P, CM_N E8, D8 I Common Mode Sense Input. Pair A A_P, A_N B2, A2 I/O Pair A of the AQR405 line interface. These should connect to the Pair A inputs of the transformer, with capacitive bypassing via the center-tap. On reset this is set to high-impedance. Pair B B_P, B_N B4, A4 I/O Pair B of the AQR405 line interface. These should connect to the Pair B inputs of the transformer, with capacitive bypassing via the center-tap. On reset this is set to high-impedance. Str ict ly CMS Table 2.13 MDI signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 45 Signal Name Pin Name(s) Pin Number(s) Type Description C_P, C_N B6, A6 I/O Pair C of the AQR405 line interface. These should connect to the Pair C inputs of the transformer, with capacitive bypassing via the center-tap. On reset this is set to high-impedance. Pair D D_P, D_N B8, A8 I/O Pair D of the AQR405 line interface. These should connect to the Pair D inputs of the transformer, with capacitive bypassing via the center-tap. On reset this is set to high-impedance. en tia l Pair C Table 2.13 MDI signals Co nfi d differential impedance). It can also drive 55 m of CAT-6 cable, and a lesser distance of CAT-5e cable. In 2.5G and 5G mode, it can drive 100m of CAT-5e (or better) cable. In 1G and 100M modes, it can drive 130m of CAT-5e (or better) cable. It is designed to drive this via a quad, 50 , center-tapped 1:1 transformer connected to an RJ-45 PCB-mount jack. Str ict ly The line interface on the AQR405 supports automatic A/B and C/D pair swaps, inversions (auto-X), and semi-cross (A/B or C/D only). It also supports provisionable ABCD to DCBA pair reversal for ease of routing with stack-jacks via bit 1.E400.0. Note that this reversal does not swap polarities, thus A+ maps to D+, etc. This distance is indeterminate because CAT-5e cable performance is not specified past 100 MHz[11]. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 46 2.8 Timing Signal Name 50 MHz Clock Termination Pin Name(s) Pin Number(s) 50M_CLK_TERM G13 Type I Description Selects whether PHY provides 100 differential termination for 50 MHz clock input: 1 = Terminated, 0 = Open. XTAL_SELECT_N XTAL_I Crystal Output XTAL_O F18 Str ict ly Crystal Input F17 I Co nfi d Clock Source Select en tia l This input is on the VDD_IO domain and has a pull-up associated with it. G18 The 50 MHz reference clock source selector for the AQR405. When XTAL_SELECT_N is pulled low, these XTAL_I and XTAL_O pins operate in crystal mode, otherwise they operate in LVDS oscillator input mode. This input is on the VDD_IO domain and has a pull-up associated with it. I The 50 MHz reference clock input for the AQR405. When XTAL_SELECT_N is pulled low, these pins operate in crystal mode, otherwise they are the differential LVDS inputs for an external oscillator, with XTAL_I being the positive input and XTAL_O being the negative input. In oscillator mode, this DC-coupled input has an internal 100 termination resistor associated with it. I The 50 MHz crystal oscillator output of the AQR405. This connects to the output of an inverting amplifier. In XO mode, this is high-impedance. Table 2.14 Timing signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 47 PTP / 1588 Sync Pin Name(s) Pin Number(s) 1588_SYNC N15 Type I Description The PTP sync input used to align the PTP clocks on multiple PHYs on a platform to have the same time. The PHY timestamps the rising edge of this input and this timestamp can then be used on each of the PHYs to perform the alignment. en tia l Signal Name This input is on the VDD_IO domain and has a pull-up associated with it. CLK_1588_P, CLK_1588_N Sync-E Primary Clock CLKO_50M_A D1, C1 I Co nfi d PTP External Clock D2 O The PTP differential LVDS clock input. This input has a 100 termination associated with it, and will operate in the frequency range of 40 MHz to 160 MHz. This pin should be AC coupled. The primary recovered clock output used for synchronous Ethernet (Sync-E). This 20 mA output is on the VDD_IO domain. Table 2.14 Timing signals 2.9 LED Str ict ly The AQR405 contains a high-performance synthesizer, which is capable of producing all of the clocks required internally, as well as sourcing the recovered 50 MHz CMOS clock for use by other components in the system. This synthesizer operates from a differential 50 MHz clock. The 50 MHz CMOS clock output is synchronized to the recovered clock and is thus capable of being used in a synchronous Ethernet application. Enabling and selection of these clocks is done via the Global MMD. The AQR405 supports three 20 mA open-drain CMOS LED outputs. Configuration of the LEDs is done via the API. 2.10 Reference Resistors The AQR405 relies on 1% precision resistors to calibrate its internal voltage levels. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 48 Signal Name LED [2:0] Pin Name(s) Pin Number(s) LED0, LED1, LED2 K1, L1, M1 Type OD Description The 2.5V tolerant, open-drain LED outputs for PHY. These open-drain 20 mA outputs are on the VDD_IO domain. Signal Name Bandgap Reference Resistor Pin Name(s) RREF_BG en tia l Table 2.15 LED signals Pin Number(s) A10 Type Description Analog The connection point for the bandgap reference resistor. This should be a precision 1%, 2.00 k resistor tied to ground. Str ict ly Co nfi d Table 2.16 Reference Resistors signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 49 2.11 Test Signal Name JTAG Clock Pin Name(s) TCK Pin Number(s) K14 Type I Description The JTAG clock input. This input is on the VDD_IO domain and has a pull-down associated with it. TDI I The JTAG data input signal. This input is on the VDD_IO domain and has a pull-down associated with it. JTAG Data Output TDO JTAG Reset TRST_N L15 O The JTAG data output signal. This 20 mA output is on the VDD_IO domain. M15 TMS M16 Str ict ly JTAG Test Mode State L14 en tia l Data I Co nfi d JTAG Input I The JTAG reset signal. If JTAG is not used, this pin must be pulled low. This input is on the VDD_IO domain and has a pull-up associated with it. The JTAG test mode state signal. This input is on the VDD_IO domain and has a pull-down associated with it. Table 2.17 Test signals The AQR405 supports a IEEE 1149.1 compliant JTAG interface, with 1149.6 AC JTAG support on the SERDES interface. Note that for normal operation, TRST_N should be held low. 2.12 Metrology Signal Name Thermal Diode Pin Name(s) TDIO_P, TDIO_N Pin Number(s) G3, F3 Type Analog Description Thermal diode terminals. Table 2.18 Metrology signals The AQR405 contains two thermal diodes which can be used to monitor the die temperature without going through the MDIO registers. The "P" indicates the anode Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 50 terminal (i.e. current input) of the thermal diode. 2.13 Wake-On-LAN Signal Name PERST* Pin Name(s) Pin Number(s) PERST_N L3 Type I Description PCI-Express Reset* input. Wake WAKE K3 en tia l This input is on the VDD_IO domain and has a pull-up associated with it. O Wake signal. This 20 mA output is on the VDD_IO domain. Table 2.19 Wake-On-LAN signals Co nfi d For Wake-On-LAN functionality, the AQR405 uses the PRST* input to sense the state of the PCI Express PERST# signal which is low when the main power is turned off (i.e. the processor is in the S3 state). It uses WAKE to drive the PCI Express WAKE# wake-up signal through an external open-drain buffer. 2.14 Debug SMBus Clock SMBus Data Pin Name(s) Pin Number(s) SMB_CLK H17 Str ict ly Signal Name SMB_DAT H18 Type I Description Clock signal for slave SMBus used for debug port into PHY MDIO register space. This signal requires a pull-up to VDD_IO. This input is on the VDD_IO domain and has a pull-down associated with it. I/O Data signal for used for debug MDIO register signal requires VDD_IO. slave SMBus port into PHY space. This a pull-up to This 20 mA I/O is on the VDD_IO domain and has a pull-down associated with it. Table 2.20 Debug signals The AQR405 supports a side-access port to the MDIO register space via a slave SMBus. Addressing for this SMBus is provisioned on a per PHY basis. It is Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 51 Str ict ly Co nfi d en tia l recommended that every design connect these SMBus pins to a header to allow in-system debug. This obviates the need to disconnect the MDIO lines, and allows for normal system operation during debug. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 52 2.15 Power Signal Name Pin Name(s) Pin Number(s) Type Description VA12 D4, D6, E5, E7, E9 Supply 1.2V analog supply. AVDD22 VA22 A3, A5, A7, A9, C3, C5, C7, C9 Supply 2.1V analog supply. AVSS AVSS B3, B5, B7, B9, B12, B14, B16, C2, C4, C6, C8, C11, C13, C15, C17, D3, D5, D7, D9, D12, D14, D16, D18, E4, E11, E13, E15, E17, F6, F8, F10, F12, G5, G7, G9, G11, H6, H8, H10, H12 Supply Analog ground. AVSS PLL AVSS_PLL E6 Supply Analog ground for PHY PLL. Analog VDD AFE_DVDD E10 Supply 0.85V supply for circuitry in the AFE. VCC Crystal VA22_XTAL E18 Supply 2.1V supply for the crystal oscillator. VDD VDD J6, J8, J10, J12, K5, K7, K9, K11, K13, L6, L8, L10, L12, M7, M9, M11, M13, N6, N8, N10, N12, P5, P7, P9, P11, P13, R8, R10, R12 Supply 0.85V digital supply. VDD FLASH VDD_FLASH E3 Supply FLASH (2.5V). VDD Power Supply VDD_IO J3, K4, L16 Supply The power supply for the general I/O on the AQR405. High and low logic levels are scaled to 70% and 30% of the supply voltage respectively. IO Str ict ly Co nfi d en tia l AVDD K16, Table 2.21 Power signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 I/O Power digital Supply 53 Signal Name VDD Select IO Pin Name(s) Pin Number(s) MDIO_1P2_SELE CT_N H4 Type I Description When pulled low, this signal sets the I/O voltages for MDC, MDIO, and RST_N to 1.2V levels, regardless of the VDD_IO voltage. en tia l This input is on the VDD_IO domain and has a pull-up associated with it. VDD_SRDS R5, T8, T10, T12 Supply SERDES 0.85V digital supply. VDD22 SERDES V22_SRDS P4, R3 Supply SERDES 2.1V supply. VREG SERDES P0_VREG_SRDS T4, T6 Supply 1.8V SERDES regulator output used for decoupling and monitoring. VSS VSS VSS SERDES VSS_SRDS, VSS_SRDS, VSS_SRDS, VSS_SRDS, VSS_SRDS, VSS_SRDS, VSS_SRDS Co nfi d VDD SERDES Supply Digital ground. P18, P17, , , , U18, N1, N2, P3, R1, R2, R4, R6, R14, T3, T5, T7, T9, T11, T13, U1, U5, U9, U11, V5, V9, V11 VSS_ SRDS SERDES ground. Str ict ly J5, J7, J9, J11, J13, K6, K8, K10, K12, L7, L9, L11, L13, M6, M8, M10, M12, N5, N7, N9, N11, N13, P6, P8, P10, P12, R7, R9, R11, R13 Table 2.21 Power signals The AQR405 utilizes three separate power supplies to minimize power consumption: 1) VDD 2) 1.2V 3) 2.1V Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 54 Str ict ly Co nfi d en tia l As mentioned earlier, in order to provide maximum flexibility to the implementation, the AQR405 utilizes a programmable I/O voltage. The logic thresholds for the I/O are set at 70% and 30% of VDD_IO for VIH/VOH and VIL/VOL respectively. For 1.2V MDIO operation (affects MDC, MDIO, RST_N), a separate signal called MDIO_1P2_SELECT_N is provided that will force 1.2V operation on these signals, regardless of the VDD_IO voltage. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 55 2.16 Reserved Signal Name Pin Name(s) NC Reserved Ground RG_L4, RG_A18 Type A11, A12, A13, A14, A15, A16, A17, B10, B11, B13, B15, B17, B18, C12, C14, C16, C18, D11, D13, D15, D17, E12, E14, E16, F7, F9, F11, F14, G6, G8, G10, G12, G15, H5, H7, H9, H11, H13, J17, K2, K17, L2, L17, M2, M3, N3, P15, R15, R16, R17, R18, T16, T17, T18, U10, U12, U13, U14, U15, U17, V10, V12, V13, V14, V15, V17 n/a L4, A1, A18 I Description These pins are floating in the package and can be connected as convenience dictates. Str ict ly RG_A1, Co nfi d en tia l Floating Pin Number(s) Table 2.22 Reserved signals Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Reserved ground signal. These pins must be connected to digital ground in the PCB design. These inputs are on the VDD_IO domain and have pull-downs associated with them. 56 Pin Name(s) Pin Number(s) Reserved No Connect RNC_E2, RNC_T14, RNC_B1, RNC_F13, RNC_G14, RNC_N4, RNC_M4, RNC_F4, RNC_G4, RNC_C10, RNC_D10, RNC_F15, RNC_G16, RNC_H15, RNC_H14, RNC_J14, RNC_P14, RNC_M14, RNC_N14, RNC_N16, RNC_P16, RNC_V18, RNC_F16, RNC_V1, RNC_M5, RNC_L5 E2, T14, B1, F13, G14, N4, M4, F4, G4, C10, D10, F15, G16, H15, H14, J14, P14, M14, N14, N16, P16, V18, F16, V1, M5, L5 Type n/a Description Reserved no-connect signal. These pins must be left unconnected in the PCB design. Co nfi d en tia l Signal Name Table 2.22 Reserved signals Str ict ly 2.17 Pin-Out The pin-out for the AQR405 is shown on the next page. The signals are color coded to group similar functionalities together. The view is looking from the top of the chip. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 57 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A RG_A1 P0_VA22 P0_A_N P0_VA22 P0_C_N P0_VA22 P0_CM_N P1_VA22 P1_B_N P1_VA22 P1_D_N RREF_BG0 RREF_BG3 P2_A_N P2_VA22 P2_C_N P2_VA22 P3_CM_N P3_VA22 P3_B_N P3_VA22 P3_D_N P3_VA22 RG_A24 A B RNC_B1 AVSS P0_A_P AVSS P0_C_P AVSS P0_CM_P AVSS P1_B_P AVSS P1_D_P RREF_BG1 RREF_BG2 P2_A_P AVSS P2_C_P AVSS P3_CM_P AVSS P3_B_P AVSS P3_D_P AVSS RNC_B24 B C AVSS P0_VA22 AVSS P0_VA22 AVSS P1_VA22 AVSS P1_VA22 AVSS P1_VA22 AVSS RNC_C12 RNC_C13 AVSS P2_VA22 AVSS P2_VA22 AVSS P2_VA22 AVSS P3_VA22 AVSS P3_VA22 SMB_DAT C D VA22_XTAL AVSS P0_B_N AVSS P0_D_N AVSS P1_CM_N AVSS P1_A_N AVSS P1_C_N RNC_D12 RNC_D13 P2_B_N AVSS P2_D_N AVSS P2_CM_N AVSS P3_A_N AVSS P3_C_N AVSS SMB_CLK D E AVSS AVSS P0_B_P AVSS P0_D_P AVSS P1_CM_P AVSS P1_A_P AVSS P1_C_P AVSS AVSS P2_B_P AVSS P2_D_P AVSS P2_CM_P AVSS P3_A_P AVSS P3_C_P AVSS AVSS E F CLK_P VA12_A AVSS VA12_A AVSS VA12_A AVSS VA12_A AVSS VA12_A AVSS AFE_DVDD_A AVSS G CLK_N AVSS VA12_A P0_AVSS_PLL VA12_A AVSS VA12_A P1_AVSS_PLL VA12_A AVSS VA12_A AVSS AVSS NC AVSS NC AVSS NC AVSS VA12_B AVSS VA12_B AVSS VA12_B AVSS VA12_B VA12_B AFE_DVDD_B VA12_B P2_AVSS_PLL VA12_B AVSS VA12_B P3_AVSS_PLL VA12_B AVSS VA12_B AVSS AVSS NC AVSS NC AVSS NC AVSS NC AVSS P3_LED0 TDIO_N_3 TDIO_P_3 VDD_IO RNC_H24 H AVSS NC AVSS NC AVSS NC AVSS P3_WAKE ADDR4 ADDR3 ADDR2 J NC AVSS NC AVSS NC AVSS P3_LED1 P1_MDC P0_MDC P2_MDC P3_MDC K RNC_J4 RNC_J5 AVSS NC AVSS NC AVSS NC AVSS NC SCLK CE_N RG_K3 RNC_K4 RNC_K5 NC AVSS NC AVSS NC AVSS NC AVSS P0_WAKE VDD_IO MDIO_1P2_SE LECT_N AVSS NC AVSS NC VSS VDD P2_INT_N P3_INT_N VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS P3_PERST_N P1_MDIO P0_MDIO P2_MDIO P3_MDIO VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD P2_LED2 P2_WAKE VDD VSS VDD VSS VDD VSS VDD VSS VDD RNC_P19 P2_LED1 RNC_P21 VSS VDD VSS VDD VSS VDD VSS VDD VSS RNC_R19 P2_LED0 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS P1_LED2 P1_WAKE VSS VDD VSS VDD VSS P0_LED0 P0_LED1 P0_LED2 INV_ADDR1 VDD VSS VDD VSS VDD RST_N INV_ADDR0 P1_PERST_N RNC_T4 VSS VDD VSS VDD VSS VSS_SRDS VSS_SRDS VDD_IO RNC_U4 VDD VSS VDD VSS VDD VSS_SRDS VDD_SRDS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD_SRDS VSS_SRDS V22_SRDS VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS VSS_SRDS V22_SRDS VSS_SRDS VDD_SRDS VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VDD_SRDS RNC_Y22 V22_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS V22_SRDS RNC_AB3 P0_VREG_ SRDS VSS_SRDS P0_VREG_ SRDS RNC_AB7 P1_VREG_ SRDS VSS_SRDS P1_VREG_ SRDS VSS_SRDS V22_SRDS VSS_SRDS V22_SRDS P2_VREG_ SRDS VSS_SRDS P2_VREG_ SRDS RNC_AB18 P3_VREG_ SRDS VSS_SRDS P3_VREG_ SRDS VSS_SRDS VSS_SRDS P1_TX_LN0_P VSS_SRDS P1_RX_LN2_P VSS_SRDS P1_TX_LN2_P VSS_SRDS VSS_SRDS P2_RX_LN0_P VSS_SRDS P2_TX_LN0_P VSS_SRDS P2_RX_LN2_P VSS_SRDS P2_TX_LN2_P VSS_SRDS P3_RX_LN0_P VSS_SRDS VSS_SRDS VSS_SRDS P1_TX_LN0_N VSS_SRDS P1_RX_LN2_N VSS_SRDS P1_TX_LN2_N VSS_SRDS VSS_SRDS P2_RX_LN0_N VSS_SRDS P2_TX_LN0_N VSS_SRDS P2_RX_LN2_N VSS_SRDS P2_TX_LN2_N VSS_SRDS P3_RX_LN0_N VSS_SRDS RG_AD24 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS_SRDS VSS_SRDS AC VSS_SRDS VSS_SRDS P0_TX_LN2_P VSS_SRDS P1_RX_LN0_P AD RG_AD1 VSS_SRDS P0_TX_LN2_N VSS_SRDS P1_RX_LN0_N 1 2 3 4 5 Figure 2.9 AQR405 pin-out Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 RNC_R21 TCK NC VDD_IO 1588_SYNC TDI TDO TRST_N TMS VDD VDD_SENS E RNC_U21 RNC_U22 VSS_SRDS VSS_SRDS P3_TX_LN2_P P3_TX_LN2_N VSS_SRDS VSS_SRDS P3_RX_LN2_P P3_RX_LN2_N VSS_SRDS VSS_SRDS P3_TX_LN0_P P3_TX_LN0_N AB AB P0_RX_LN2_N P0_RX_LN2_P TX_DC_CLK AA AA VSS_SRDS RX_DC_RST_ N Y Y P0_TX_LN0_N P0_TX_LN0_P RNC_P22 W W VSS_SRDS Str ict ly P1_LED1 P0_RX_LN0_N P0_RX_LN0_P P2_PERST_N TX_DC_DATA TX_DC_SOF V P1_LED0 V RX_DC_CLK AD VDD P0_INT_N AC VSS P1_INT_N U VDD P3_LED2 T TDIO_P_0 NC R RX_DC_SOF P0_PERST_N AVSS P VSS NC N VDD AVSS M VSS NC L VDD AVSS U VSS NC T TDIO_N_0 AVSS R TX_DC_RST_ VDD_FLASH N NC P RX_DC_DATA AVSS N CLKO_50M_A RST_OUT_N Co nfi d RG_J3 M SOUT L SIN K AVSS J VA12_B G CLK_1588_N CLKO_50M_B AVSS F DC_MASTER_ CLK_1588_P N en tia l 2 H 1 Str ict ly Co nfi d en tia l 58 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Timing 3- 3.1 MDIO 1/ fMDC MDC VIH tL tH VIL VIL MDC tHOLD_IN en tia l MDIO Input tSETUP VIH VIH VIL MDIO Output Co nfi d tHOLD_OUT VIH VIL Figure 3.1 MDIO setup and hold times Symbol Parameter Test Condition Min Typ Max Units 10.5 MHz MDC Frequency tL MDC Low Time 20 ns tH MDC High Time 20 ns tSETUP Input Setup Time 8 ns tHOLD_IN Input Hold Time 10 ns Output Hold Time 29 Str ict ly fMDC tHOLD_OUT 38 ns Table 3.1 MDIO timing Data is sampled on the rising edge of MDC at the PHY, and at the STA. 59 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 60 3.2 Interrupt tINT MD_INT* VIH VIL tF tR Symbol en tia l Figure 3.2 Interrupt timing diagram Parameter tF Fall Time tR Rise Time Test Condition Interrupt Time tINT Min Typ Max Units 1 ns 1 ns n/a1 ns Co nfi d Table 3.2 Interrupt timing 1. INT* stays low until the interrupt is serviced 3.3 Reset tRESET RST* VIH VIL RST_OUT* tRESET_OUT VIH Str ict ly VIL Test Condition Reset Out Time fC = 50.00 MHz tF tR Figure 3.3 Reset timing diagram Symbol tRESET tF tR tRESET_OUT Parameter Min Typ Max Units Reset Time 100 ms Fall Time 1 ns Rise Time 1 ns 20 ms Table 3.3 Reset timing Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 61 3.4 SPI tCE VOH CE* VOL tCES tL tH VOL tHI tSU VIH SIN VALID IN VIL en tia l SCLK tCEH VOH tV VOH SOUT VOL tHO Symbol Parameter SCLK Clock Frequency1 Test Conditions Min 0 Typ Max Units 50.0 MHz tH SCLK High Time 12 ns tL SCLK Low Time 12 ns tCE CE* High Time 50 ns tCES CE* Setup Time 25 ns tCEH Str ict ly fSCLK Co nfi d Figure 3.4 SPI timing diagram CE* Hold Time 25 ns SIN Setup Time 14 ns SIN Hold Time -4 ns tSU tHI tV tHO SOUT Output Valid SOUT Hold Time 4 -4 ns ns Table 3.4 SPI timing 1. An attached FLASH device which supports 40 MHz operation, must have a tV (output valid time) of less than 12.5 ns. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 62 3.5 Daisy-chain 1/ fDC_CLK TX_DC_CLK V IH tL tH VIL TX_DC_SOF tOUT V IH TX_DC_DATA en tia l VIL V IH VIL RX_DC_CLK V IH VIL VIL RX_DC_DATA tHOLD Co nfi d RX_DC_SOF tSETUP V IH V IH VIL tRST_N TX_DC_RST_N V IH VIL Symbol fDC_CLK Str ict ly Figure 3.5 Daisy-chain timing diagram Parameter Test Conditions Min Typ Max Units 20 MHz Daisy-chain Clock Frequency 0 SCLK High Time 22 ns SCLK Low Time 22 ns Daisy-chain Output 0 Daisy-chain Setup Input 4 ns tHOLD Daisy-chain Hold Input 2 ns tRST_N Daisy-chain Reset1 5 ns tH tL tOUT tSETUP Table 3.5 Daisy-chain timing Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 4 ns 63 1. TX_DC_RST_N stays low until the slave(s) finish loading. Also - note that this is an asynchronous input. 3.6 SERDES Maximum Random Jitter (RJMAX) Maximum Data Dependent Jitter (DDJMAX) 1.00 0.25 0.55 Maximum Deterministi c Jitter (DJMAX) Maximum Periodic Jitter (PJMAX) en tia l Maximum Total Jitter (TJMAX) 0.10 0.10 Units UIpp Table 3.6 SERDES receiver jitter tolerance specifications Maximum Random Jitter (RJMAX) Maximum Deterministic Jitter (DJMAX) Maximum Periodic Jitter (PJMAX) Units 0.25 0.15 0.05 0.05 UIpp Co nfi d Maximum Total Jitter (TJMAX) Table 3.7 SERDES transmit jitter tolerance specifications Str ict ly f SYMBOL The measurement BW for these specs is from -------------------- to , as the tracking 1667 f SYMBOL bandwidth of the PLL for the SERDES is up to -------------------- . For instance, for KR, the 1667 f SYMBOL symbol rate is 10.3125 GHz, so -------------------- 6 MHZ . Thus the measurement BW for 1667 the integrated jitter is from roughly 6 MHz to infinity. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 64 3.7 RXAUI Transmit 1/fS Lane 0 Tx VIH-DIFF VIL-DIFF tj_TX Lane n Tx VIH-DIFF en tia l VIL-DIFF tSKEW_TX Figure 3.6 RXAUI transmit timing diagram Symbol tSKEW_TX Test Condition Symbol Rate Min Typ Max 6.25 Transmit Skew Between any two channels Co nfi d fS Parameter TBD Units GS/s TBD Symbols Table 3.8 RXAUI transmit timing 3.8 RXAUI Receive 1/(fRX+f) Lane 0 Rx VIH-DIFF VIL-DIFF Lane n Rx Str ict ly tj_TOL VIH-DIFF VIL-DIFF tSKEW_RX Figure 3.7 RXAUI receive timing diagram Symbol Parameter fRX Receive Symbol Rate f Frequency Tolerance tSKEW_RX Test Condition Min Max 6.25 -300 Receiver Skew Tolerance Typ Between any two channels Table 3.9 RXAUI receive timing Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Units GS/s 300 ppm TBD Symbols 65 3.9 SGMII Transmit 1/fS SGMII Tx V IH-DIFF V IL-DIFF tj_TX Symbol fS en tia l Figure 3.8 SGMII transmit timing diagram Parameter Test Condition Symbol Rate Min Typ Max 1.25 Units GS/s Table 3.10 SGMII transmit timing Co nfi d 3.10 SGMII Receive 1/(fRX+f) SGMII Rx V IH-DIFF V IL-DIFF tj_TOL Figure 3.9 SGMII receive timing diagram Symbol Parameter Receive Symbol Rate f Frequency Tolerance Str ict ly fRX Test Condition Min Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Max 1.25 -300 Table 3.11 SGMII receive timing Aquantia Corp. - Strictly Confidential Typ Units GS/s 300 ppm 66 3.11 KR Transmit 1/fS KR Tx VIH-DIFF VIL-DIFF tj_TX Symbol fS en tia l Figure 3.10 KR transmit timing diagram Parameter Test Condition Symbol Rate Min Typ Max 10.3125 Units GS/s Table 3.12 KR transmit timing Co nfi d 3.12 KR Receive 1/(fRX+'f) KR Rx VIH-DIFF VIL-DIFF tj_TOL Figure 3.11 KR receive timing diagram Symbol Parameter Receive Symbol Rate f Frequency Tolerance Str ict ly fRX Test Condition Min Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Max 10.3125 -50 Table 3.13 KR receive timing Aquantia Corp. - Strictly Confidential Typ Units GS/s 50 ppm 67 3.13 2500BASE-X Transmit 1/fS VIH-DIFF 2500BASE-X Tx VIL-DIFF tj_TX Symbol Parameter fS en tia l Figure 3.12 2500BASE-X transmit timing diagram Test Condition Symbol Rate Min Typ Max 3.125 Units GS/s Table 3.14 2500BASE-X transmit timing Co nfi d 3.14 2500BASE-X Receive 1/(fRX+'f) VIH-DIFF 2500BASE-X Rx VIL-DIFF tj_TOL Figure 3.13 2500BASE-X receive timing diagram Symbol Parameter Receive Symbol Rate f Frequency Tolerance Str ict ly fRX Test Condition Min Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Max 3.125 -300 Table 3.15 2500BASE-X receive timing Aquantia Corp. - Strictly Confidential Typ Units GS/s 300 ppm 68 3.15 Clocks 3.15.1 Input 1/(fC+f) Oscillator Clock Input VIH VIL Symbol en tia l Figure 3.14 50 MHz input timing diagram Parameter Clock Frequency f Frequency Tolerance tj RMS Jitter1 DC Duty Cycle Min Typ Max 50.0 -50 12 kHz - 20 MHz Co nfi d fC Test Condition 45 Units MHz 50 ppm 1.0 ps 55 % Table 3.16 50.000 MHz input timing 1. This includes all period jitter and tones 0 -20 -40 -60 Str ict ly Phase Noise (dBc/Hz) The phase noise of the 50 MHz input clock should be at least as good as the mask shown below: -80 -100 -120 -140 -160 -180 10 1,000 100,000 Frequency (Hz) Figure 3.15 50.000 MHz phase noise mask Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 10,000,000 69 3.15.2 Output 1/(fC+f) Ref_CLK Output VIH VIL en tia l The timing information for the AQR405 output clocks (CLKO_50M_A and CLKO_50M_B) are shown below. Note that the 50 MHz clock is phase-locked to the incoming receive signal in 1G and 10G slave mode. The result is that their frequency accuracy in these modes is a function of the far-end device's clock accuracy. Figure 3.16 50 MHz reference clock output timing diagram Parameter fC Clock Frequency f Frequency Tolerance tj RMS Period Jitter tL Clock Low Time tH Clock High Time tR / tF DC Test Condition Clock Rise / Fall Time Duty Cycle Min Typ Max 50.000 Co nfi d Symbol -50 ppm 1 ps 8 12 ns 8 12 ns 2 45 Str ict ly Table 3.17 50 MHz reference clock output timing Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 MHz 50 6 pF load Aquantia Corp. - Strictly Confidential Units ns 55 % 70 3.16 JTAG 1/ fTCK TCK VIH VIL tL tH tSETUP V TDI IH TMS V IL tHOLD_IN TDO en tia l tHOLD_OUT VIH VIL Figure 3.17 JTAG timing diagram Parameter fTCK Clock Frequency tL Clock Low Time tH Clock High Time tSETUP Input Setup Time tHOLD_IN Input Hold Time tHOLD_OUT Output Hold Time Test Condition Co nfi d Symbol Str ict ly Table 3.18 JTAG timing Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Min Typ Max Units 20 MHz 20 ns 20 ns 5 ns 15 ns 10 22 ns Electrical Specifications 4- 4.1 Absolute Maximum Ratings Symbol Parameter Test Condition Min Max Units 0.85V Digital Supply -0.5 0.935 V VA12 1.2V Analog Supply -0.5 1.32 V VA22 2.1V Analog Supply -0.5 2.31 V -0.5 2.75 V -0.5 2.75 V -0.5 2.75 V HBM 2 kV CDM 500 V MM 200 V 100 m cable 2 kV 150 C Max Units 2.1V VDD General I/O Supply VDD_IO 2.5V VDD General I/O Supply VDD_FLASH VESD 2.5V FLASH I/O Supply Co nfi d ESD on all pins except Line en tia l VDD VCO Cable discharge on Line Storage Temperature TSTORE -50 Table 4.1 AQR405 absolute maximum ratings 4.2 Recommended Operating Conditions TJ TJST Parameter Test Condition Str ict ly Symbol Min Junction Temperature 0 108 C Short-Term Junction Temperature1 0 110 C Table 4.2 AQR405 recommended operating conditions 1. In order to not degrade the life of the part, the AQR405 should not be operated at this temperature for more than 1 week / year. 4.3 Power The AQR405 automatically adjusts is power consumption based on the length of the channel: consequently there is no explicit "short reach mode". However the Thus when PHY power consumption is characterized at 30m, it is simply what the power consumption of the PHY is when operating on a 30m link. 71 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 72 power consumption of the AQR405 can be characterized over the IEEE 30m short-reach channel. The following tables specify the power-supply requirements and operating power per port for the AQR405 in both full-reach and short reach operation. 4.3.1 Operating Modes en tia l The AQR405 has several different operating regimes that each use different amounts of power. These regimes are listed below, and power consumption for each of these regimes is given in Table 4.4. 1) Low power (LP): In this mode, everything is shut off except the internal microprocessor and the MDIO interface. It is designed for out-of-service ports, and is the lowest power operating mode. Co nfi d 2) Autonegotiation (ANEG): In this mode, the AQR405 is attempting to autonegotiate with the far-end PHY and is sending and trying to receive link pulses. This is the second lower operating power mode, and usually last between 1.6 and 1.8 seconds. 3) 10G Training (TRNG): This is the highest power mode, and occurs at the beginning of a 10GBASE-T session. This training mode lasts for a maximum of 2 seconds. This sets the maximum requirements for the VA12, VA22, and VDD power supplies. Str ict ly 4) 10G Steady-state Operation (10GSS): This is the second highest power mode, and occurs during normal 10GBASE-T operation. This sets the maximum requirements for the thermal design, and the maximum for the VDD power supply. 5) 5G Steady-state Operation (5GSS): This is the power seen during normal 5G AQRate operation 6) 2.5G Steady-state Operation (2.5GSS): This is the power seen during normal 2.5G AQRate operation. 7) 1G Steady-state Operation (1GSS): This is the power seen during normal 1000BASE-T operation. 8) 100M Steady-state Operation (100MSS): This is the power seen during normal 100BASE-TX operation. This autonegotiation time assumes that an active link-partner is present. If one is not present, the AQR405 will continue attempting to autonegotiate until a PHY is connected. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 73 An example of the power consumption versus time for some of these modes in 10G operation is shown in Figure 4.1. In this figure, the device starts off in low-power Power Autonegotiation ~1.6 seconds 0 t Co nfi d Low Power t+1 Steady State en tia l 10G Training ~2 seconds t+2 t+3 t+4 Time (seconds) PHY is enabled Figure 4.1 Power versus time mode, and then at time t, the AQR405 is enabled, and autonegotiation begins. After 10GBASE-T is agreed on as the connection rate, 10GBASE-T training starts, and then after 2 seconds, 10GBASE-T steady-state is entered into. Str ict ly 4.4 Full-Reach Power Supplies 4.4.1 Full-Reach VA22 and VA12 Supply Specifications The following tables provide the per port analog VA22 and VA12 power supply requirements for the AQR405 operating in full-reach mode. VA22 includes the following supplies: Px_VA22, VA22_XTAL and V22_SRDS. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 74 VA12 includes the follwoing supplies: VA12_A and VA12_B.. Symbol Parameter Test Condition Min Typ Max Units 2.037 2.10 2.163 V 13 mV VA22 TOTAL Input Voltage1 VA22 RIPPLE Input Voltage Ripple Peak to Peak IVA22 TOTAL Input Current 10G Training2 510 mA IVA22 TOTAL Input Current 10G Steady-State 480 mA en tia l 0 Table 4.3 Full-reach VA22 electrical parameters 1. The input voltage is specified as DC accuracy. 2. This assumes KR start-up Symbol Parameter Test Condition Min Typ Max Units 1.20 1.236 V 48 mV Input Voltage1 VA12 RIPPLE Input Voltage Ripple Peak to Peak IVA12 TOTAL Input Current 10G Training2 350 mA IVA12 TOTAL Input Current 10G Steady-State 300 mA Co nfi d VA12 TOTAL 1.164 0 Table 4.4 Full-reach VA12 electrical parameters 1. The input voltage is specified as DC accuracy. 2. This assumes KR start-up VVDD TOTAL Str ict ly 4.4.2 Full-Reach VDD Supply Specifications VVDD RIPPLE Input Voltage Ripple Peak to Peak IVDD TOTAL Input Current 10G Training2 3670 mA IVDD TOTAL Input Current 10G Steady-State 3050 mA The following tables provide the per port digital VDD power supply requirements for the AQR405 operating in full-reach mode with a fixed supply. VDD includes the following supplies: VDD_SRDS, AFE_DVDD_A, AFE_DVDD_B and the core supply.. Symbol Parameter Test Condition Input Voltage1 Min Typ Max 0.8245 0.850 0.8755 V 34 mV 0 Table 4.5 Full-reach VDD fixed supply electrical parameters Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Units 75 1. The input voltage is specified as DC accuracy. 2. This assumes KR start-up 4.5 Other Power Supplies 4.5.1 VDD_IO and VDD_FLASH Supply Specifications VDD_IO operates on 2.1V or 2.5V. VDD_FLASH only operates on 2.5V. . en tia l The following tables provide power supply requirements for the VDD_IO and VDD_FLASH power supplies for the AQR405. Parameter Test Condition Min Typ Max VDD_IO TOTAL 2.1 V Input Voltage1The input voltage is specified as DC accuracy. 2.037 2.10 2.163 V VDD_IO RIPPLE 2.1V Input Voltage Ripple Peak to Peak 84 mV IVDD_IO TOTAL 2.1V Input Current 10G Training2 TBD mA IVDD_IO TOTAL 2.1V Input Current 10G Steady-State TBD mA VDD_IO TOTAL 2.5 V Input Voltage1 2.575 V VDD_IO RIPPLE 2.5V Input Voltage Ripple Peak to Peak 100 mV IVDD_IO TOTAL 2.5V Input Current 10G Training2 TBD mA IVDD_IO TOTAL 2.5V Input Current 10G Steady-State TBD mA Str ict ly Co nfi d Symbol 0 2.425 2.50 0 Units Table 4.6 VDD_IO electrical parameters 1. The input voltage is specified as DC accuracy. 2. This assumes KR start-up Symbol VDD_FLASH TOTAL Parameter Test Condition Input Voltage1 Min Typ Max 2.425 2.50 2.575 Table 4.7 VDD_FLASH electrical parameters Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Units V 76 Symbol Parameter Test Condition VDD_FLASH RIPPLE Input Voltage Ripple Peak to Peak IVDD_FLASH TOTAL Input Current IVDD_FLASH TOTAL Input Current Min Typ 0 Max Units 100 mV 10G Training2 20 mA 10G Steady-State 20 mA 4.6 Management Interface en tia l Table 4.7 VDD_FLASH electrical parameters 1. The input voltage is specified as DC accuracy. 2. This assumes KR start-up The management interface includes the following signals: 2) MDIO 3) RST_N Symbol Parameter VIL Input low voltage VIH Input high voltage VOL Output low voltage IOL IOH1 ILKG Ci CL Test Condition Min Typ Max Units 0.36 V 0.84 V IOL = -4 mA 0.0 0.2 V IOH =0 mA 1.0 1.5 V IOH = 10 mA 0.96 1.5 V IOH = 20 mA 0.9 1.5 V Output low current VOL = 0.2 V 4 Output high current VOH = 1.0 V Tristate Leakage VIN = 0 V or VCC Str ict ly VOH Co nfi d 1) MDC Output high voltage mA 0 mA 10 A Input capacitance 10 pF Maximum capacitive load 470 pF -10 Table 4.8 1.2V mode MDIO electrical interface characteristics 1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line) Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 77 Symbol Parameter Test Condition Min Typ Max Units VIL Input low voltage VIH Input high voltage VOL Output low voltage IOL = -4 mA 0 20 %VDD_IO VOH Output high voltage IOH =0 mA 80 120 %VDD_IO IOH = 20 mA 80 120 %VDD_IO 30 %VDD_IO en tia l 70 Output low current VOL = 20% VDD_IO IOH1 Output high current VOH = 80% VDD_IO ILKG Tristate Leakage VIN = 0 V or VCC Ci Input capacitance CL Maximum capacitive load Co nfi d IOL %VDD_IO 4 -10 mA 0 mA 10 A 10 pF 120 pF Table 4.9 70% / 30% VDD_IO mode MDIO electrical interface characteristics 1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line) 4.7 I/O All of the non-management interface I/O on the AQR405 run from either VDD_IO or VDD_FLASH and use the same I/O cell that has the following characteristics: VIL VIH VOL VOH IOL IOH1 Parameter Test Condition Min Input low voltage Str ict ly Symbol Typ Max 30 Input high voltage 70 Units %VDD_IO %VDD_IO Output low voltage IOL = -4 mA 0 20 %VDD_IO Output high voltage IOH =0 mA 80 120 %VDD_IO IOH = 20 mA 80 120 %VDD_IO Output low current VOL = VDD_IO 20% 4 Output high current VOH = VDD_IO 80% Table 4.10 I/O pin electrical parameters Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 mA 0 mA 78 Symbol Parameter Test Condition Min Typ Max Units 10 A Input capacitance 10 pF Maximum capacitive load 120 pF ILKG Tristate Leakage Ci CL VIN = 0 V or VCC -10 4.8 Serial FLASH Symbol COUT CIN Parameter en tia l Table 4.10 I/O pin electrical parameters 1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line) Test Condition Max Units Output Capacitance (SCLK, CS*, SOUT) VOUT = 0 V 5 pF Input Capacitance (SIN) VIN = 0 V 5 pF Symbol Parameter Co nfi d Table 4.11 SPI pin capacitance Test Condition ILKG Tristate Leakage VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IOL Output low current IOH Output high current VIN = 0 V or VCC Min Typ -10 Max 10 A 20 %VDD_FLASH 80 IOL = 4 mA Str ict ly IOH = -4 mA Units %VDD_FLASH 20 %VDD_FLASH 80 %VDD_FLASH 4 mA Table 4.12 SPI DC Characteristics The SPI interface is 2.5 V tolerant. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 -4 mA 79 4.9 SERDES Parameter Output Voltage1 Test Condition Min Peak-to-peak differential Transmit Common Mode Voltage Differential Output Impedance Max Units 400 1400 mV 200 700 mV Programmable 80 100 120 20 25 30 Typ Max Units en tia l Common Mode Output Impedance Typ Table 4.13 SERDES transmitter characteristics 1. Near end programmable output range Test Condition Min Input Voltage Peak-to-peak differential 50 2000 mV Input Common Mode Voltage Peak-to-peak differential 650 1000 mV 175 mV 120 27.5 Input Loss of Signal Voltage Differential Input Impedance1 Common Mode Input Impedance Receiver Differential Return Loss Co nfi d Parameter Receiver Common-Mode Return Loss Peak-to-peak differential 75 Programmable 80 20 120 25 DC -20 dB 5 GHz -5 dB DC -10 dB 5 GHz -6 dB Str ict ly Table 4.14 SERDES receiver characteristics 1. This is programmable to 10% 4.10 Line (MDI) Symbol VOH-DIFF CIN RIN Parameter Test Condition Min Typ Max Units Differential Output Voltage 2.0 Vpk-pk Input Capacitance 2.5 pF 52 Input Resistance 48 50 Table 4.15 MDI electrical parameters The AQR405 uses a voltage-mode driver to drive the MDI, so only decoupling is required on the transformer center-tap. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 80 4.11 Reference Clocks 4.11.1 Input Clock Pins CLK_P and CLK_N - LVDS Symbol VSWING Parameter Min Typ Max Units 0.35 V Common-Mode Voltage Level 1.2 V VIH Input High 1.375 V VIL Input Low 1.025 V CIN Input Capacitance VCOMMON ZIN-DIFF Input Impedance RIN-DIFF Input Termination en tia l Single-Ended Input Voltage Swing 1 pF 100 100 Co nfi d Table 4.16 LVDS 50MHz input electrical parameters 4.11.2 Input Clock Pins CLK_1588_P and CLK_1588_N Symbol VSWING VCOMMON Parameter Common-Mode Voltage Level1 0.175 V 1.35 1.45 1.1025 V Input Low 0.55 0.65 0.75 V Operating Frequency 40 160 MHz 1 pF Str ict ly RIN-DIFF Units V VIL ZIN-DIFF Max -0.175 Input High CIN Typ Single-Ended Input Voltage Swing VIH fCLK_1588 Min Input Capacitance Input Impedance 100 Input Termination 100 Table 4.17 CLK_1588 input electrical parameters 1. CLK_1588 support AC-coupled LVDS and LVPECL clock Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 81 4.12 Reference Resistors Parameter Reference Resistance Test Condition Tied to 0V Min Typ Max 2.00 Units k Resistor Accuracy 1 % Maximum Power 5 mW 50 en tia l Temperature Variation Str ict ly Co nfi d Table 4.18 Bandgap reference resistor electrical parameters Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 ppm/C Str ict ly Co nfi d en tia l 82 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Package 5- 5.1 Mechanical Co nfi d en tia l The AQR405 is packaged in a 25 mm x 25 mm flip-chip 576 pin FCBGA (24 rows x 24 rows), with a thermal heat spreader. The mechanical drawings of this package are shown in Figure 5.1. Str ict ly Figure 5.1 AQR405 package drawing 83 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Str ict ly Co nfi d en tia l 84 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 5.2 Thermal 5.2.1 Theta J's The AQR405 utilizes an copper heat spreader that is directly attached to the back of the die with thermal epoxy. The result is a low JC path to the top of the package, and a relatively low JB to the board. The values of the various J's are given in Table 5.1: Thermal Coefficient JA Theta Junction to Ambient (no PCB thermal vias) JA Theta Junction to Ambient (PCB thermal vias) JB JC Theta Junction to Case Value Units Still air at 55C 11.1 C/W Still air at 55C 9.98 C/W JEDEC 2s2p1 4.69 C/W MIL STD 883e 0.42 C/W Co nfi d Theta Junction to Board Test Condition en tia l Name Table 5.1 Theta J's 1. Top/bottom trace 2 oz. copper Middle planes 1 oz. copper Equivalent 20% 2 oz. copper coverage adjacent to package Bottom copper 2 oz. 20% coverage 5.2.2 Thermal Model Str ict ly For the AQR405, Aquantia supplies a Flotherm(R) PDML model. 85 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Str ict ly Co nfi d en tia l 86 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Register Map 6- 6.1 Introduction The AQR405 is internally divided into a series of MDIO Manageable Devices (MMDs), each of which performs a logical function as per the 10GBASE-T standard. A block diagram of this partitioning is shown below Here the MMD #1 en tia l AQRate 25mm Quad Lookaside MMD #3: PCS XAUI/RXAUI PCS SRDS2 10G PHY XS MDIO 2.5G PCS SGMII PCS 0 1G PCS SGMII PCS 1 100M PCS P[3:0]_PRST* P[3:0]_CM_P,N REPLICATED FOUR TIMES LED LED I/F P[3:0]_LED[2:0] Boot Loader CLK_N 50 MHz Timing FLASH / Daisy Chain Power Supply COMMON VDD VA12 P[3:0]_VA22 AVSS/VSS JTAG Timing VDD_SENSE JTAG CLK_1588_P,N 1588_SYNC CLKO_50M_A,B Bandgap CLK_P Thermal Diodes TDI TDO TCK TMS TRST_N Daisy-Chain I/F RX_DC_DATA RX_DC_CLK RX_DC_SOF RX_DC_RST_N Serial FLASH I/F SCLK SIN SOUT CE_N Control RREF_BG[3:0] Str ict ly RST_N ADDR[4:2] INV_ADDR[1:0] VGA & Filter A/D MMD #30: Global Config DC_MASTER_N RST_OUT_N VGA & THP THP THP Filter Precoder Precoder Precoder THP A/D THP THP Precoder Precoder Precoder Autonegotiation RAM PController P[3:0]_[D:A]_P,N MMD #1: PMA MMD #7: Autonegotiation MACSEC SMB_DAT SMB_CLK P[3:0]_WAKE THP Hybrid THP THP Precoder Precoder Precoder MMD #29: Clause 22 Extension TDIO_N[3,0] WoL MDIO Registers KR/USXGMII PCS 1 TDIO_P[3,0] SMBus MDIO Management 5G PCS TX_DC_DATA TX_DC_CLK TX_DC_SOF TX_DC_RST_N P[3:0]_MDC P[3:0]_MDIO P[3:0]_INT_N KR/USXGMII PCS 0 DAC / THP THP THP Driver Precoder Precoder Precoder DSP P[3:0]_TX_LN2_P,N P[3:0]_RX_LN2_P,N LINE 10G PCS Co nfi d P[3:0]_TX_LN0_P,N P[3:0]_RX_LN0_P,N SRDS0 10G SERDES System I/F MMD #4: Power Figure 6.1 Functional view of AQR405 contains the PMA, which is basically the analog front-end of the chip. This is connected to MMD #3, which contains the PCS, which handles the 10GBASE-T 87 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 88 en tia l transmission frame coding and decoding, including the 128-DSQ and LDPC work. This block is in turn connected to MMD #4, which contains the XAUI interface. In addition to these MMDs, there are three others: MMD #7, which contains the autonegotiation function, MMD #29, which contains the controls for the GbE and 100M PCS machinery, and MMD# 30, which contains the global control functionality for the AQR405. Not shown, but present within the AQR405, is another MMD, #31, which is used for proprietary purposes as an adjunct to the PMA. 6.2 Register Structure A map of these regions is shown in Table 6.1. Any attempt to read from the 5 bit Device Address (Hex) MMD Name 0 reserved 2 3 4 56 7 8 1C PMA/PMD (128 DSQ) Co nfi d 1 reserved PCS (64/65B coder/decoder) PHY XS (XAUI) reserved Auto-negotiation reserved Clause 22 Extension 1E Global 1F Aquantia Proprietary Str ict ly 1D Table 6.1 MMD device addresses reserved MMD addresses will return a value of 0x00, and any writes to these addresses will have no effect. 6.3 Format and Nomenclature Registers within the device are referenced in the format: Region . Register . Bit where Region corresponds to the MMD region being addressed, Register corresponds to the register within the MMD region, and Bit is the bit within the Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 89 register. All registers within the MDIO register space are 16 bits. The address of the register is the 16 bit MDIO address. All read and write operation are word based, which means that the entire 16 bit register is read or written (versus individual bits). Within the MDIO register space, there are several different bit types. A list of these bit types are found in Table 6.2. Abbreviation Type Description Latching Low If the condition the bit is monitoring goes low, this bit latches low, generates a maskable interrupt, and stays low until read. Reading this bit resets it to one. This bit is read-only. LH Latching High If the condition the bit is monitoring goes high, this bit latches high, generates a maskable interrupt, and stays high until read. Reading this bit resets it to zero. This bit is read-only. PD Provisionable Defaults RO Read Only R/W Read / Write SC Self-Clearing SCT SCTL SCTM Co nfi d Latch Rising or Falling Set high on either a rising or falling edge. If a transition occurs, this bit latches high, generates a maskable interrupt, and stays high until read. Reading this bit resets it to zero. This bit is read-only. Indicates that the default value associated with this field is provisionable. Read-only field. Writes are ignored. Field can be both read from and written to. A read/write register which resets itself upon completion of an action. Str ict ly LRF en tia l LL Saturating Counter A read-only counter that saturates at the limit, and is cleared on read. Saturating Counter LSW The Least Significant Word of a Saturating Counter. This register clears the pair to zero on read and snapshots the mate MSW to shadow memory, awaiting read. Saturating Counter MSW The Most Significant Word of a Saturating Counter. Reading this completes the read process of the register pair. Table 6.2 Field types within the MDIO register space 6.4 Structure The following structure is used for registers: 1) All Clause 45 registers (registers defined in Clause 45) are placed in their respective areas within the MMDs as specified. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 90 2) XENPAK / X2 registers are placed in MMD #1 3) Aquantia specific registers associated with each of the Clause 45 MMDs are placed in the Aquantia specific area beginning at 0xC000, according to the register map shown in Table 6.3. Base Offset (Hex) Description Tx & Overall MMD Control C400 Tx & Overall MMD Provisioning C800 Tx & Overall MMD State CC00 Tx & Overall MMD Alarms D000 Standard Interrupt Mask D400 Tx & Overall MMD Interrupt Mask DC00 E000 E400 E800 EC00 Tx & Overall MMD Debug reserved Rx Control Rx Provisioning Rx State Rx Alarms Standard Interrupt Mask Str ict ly F000 Co nfi d D800 en tia l C000 F400 Rx Interrupt Mask F800 Rx Debug FC00 Global Interrupt Flags Table 6.3 Register layout The table is split into a transmit portion, and a receive portion, with the transmit portion also containing any overall Aquantia specific registers for the MMD. In this table, the following definitions apply: Term Control Provisioning State Definition Action bits that affect the operation of the MMD, such as reset. Static provisioning bits that control the behavior of the MMD. Bits that reflect the state of the MMD. Table 6.4 Terms used within the register layout Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 91 Term Definition Alarm Bits that can generate maskable interrupts. Standard Interrupt Mask Interrupt masks for alarm bits defined in the Clause 45 register set. Aquantia Specific Interrupt Mask Interrupt masks for Aquantia Specific alarms. en tia l Table 6.4 Terms used within the register layout Co nfi d 4) Interrupts are handled in an hierarchical fashion, with the top level interrupt indication being the INT* interrupt pin on the AQR405. Below this are two maskable interrupt trees: one composed of standard interrupts, and one composed of Aquantia defined interrupts. The top level summary register for these trees resides at the end of the register space in MMD #30 - the Aquantia Global MMD (1E.FC00). Feeding this are interrupt registers from each of the individual MMDs. a) The standard interrupt tree is designed so that the source of any interrupt can be determined in a maximum of two reads. b) The Aquantia defined interrupt tree requires at most three reads to determine the source of an interrupt. c) All interrupts are maskable, whether they are from the Standard interrupt tree, or from the Aquantia Specific interrupt tree. Str ict ly 6.5 Registers and Documentation The registers for the AQR405 are provided in the following tables, listed by the numerical order of their MMD address. Associated with these registers is a set of C-language header files and associated Doxygen[8] documentation for them. These header files contain all of the appropriate C-structures to access the registers and fields within the registers. Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 Str ict ly Co nfi d en tia l 92 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 6.6 PMA Registers Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.6.1 PMA Standard Control 1: Address 1.0 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F Reset 1 = PMA reset 0 = Normal operation E Reserved Internal reserved - do not modify D Speed Selection LSB {6,D} 1 1 = Speed set by Bits [5:2] 1 0 = 1000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s C Reserved Internal reserved - do not modify B Low Power 1 = Low-power mode 0 = Normal operation Type Default R/W SC 1 R/W PD 1 R/W PD 0 Note The reset bit is automatically cleared upon completion of the reset sequence by the microcontroller. This bit is set to 1 during reset. The reset is internally stretched by approximately 1.7 us. Therefore the MDIO or uP should allow for 1.7 us before writing any PMA registers after this bit is set. A one written to this register causes the PMA to enter low-power mode. If a global chip low-power state is desired, use Bit B in "Global Standard Control 1: Address 1E.0" NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F A:7 Reserved Internal reserved - do not modify Table 6.5 PMA Standard Control 1: Address 1.0 93 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name 6 Speed Selection MSB Type Default {6,D} 1 1 = Speed set by Bits [5:2] 1 0 = 1000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s R/W PD 1 10G Speed Selection [3:0] 1 x x x = Reserved x 1 x x = Reserved x x 1 x = Reserved x x x 1 = 10PASS-TS / 2BASE-TL 0 0 0 0 = 10 Gb/s ROS 0x0 1 Reserved Internal reserved - do not modify 0 Loopback 1 = Enable loopback mode 0 = Normal operation R/W PD 0 5:2 Description Note This enables the PMA Analog System Loopback. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F Table 6.5 PMA Standard Control 1: Address 1.0 6.6.2 PMA Standard Status 1: Address 1.1 Bit F:8 7 6:3 Name Description Reserved Internal reserved - do not modify Fault 1 = Fault condition detected 0 = No fault detected Reserved Internal reserved - do not modify Type RO Default Note This is the top-level fault indicator flag for the PMA. This bit is set if either of the two bits 1.8.B or 1.8.A are set. Table 6.6 PMA Standard Status 1: Address 1.1 Bit Name Description Type Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 2 PMA Receive Link Status Status of the PMA receive link 1 = Link up 0 = Link lost since last read LL 1 Low Power Ability 1 = PMA supports low-power mode 0 = no low-power mode supported ROS 0 Reserved Internal reserved - do not modify Default Note This indicates the status of the PMA receive link. This is the latch version of 1.E800.0. Note that this is latching low, so it can only be used to detect link drops, and not the current status of the link without performing back-to-back reads. 1 Indicates whether the PHY supports a low-power mode Table 6.6 PMA Standard Status 1: Address 1.1 6.6.3 PMA Standard Device Identifier 1: Address 1.2 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default Note RO Table 6.7 PMA Standard Device Identifier 1: Address 1.2 6.6.4 PMA Standard Device Identifier 2: Address 1.3 Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.8 PMA Standard Device Identifier 2: Address 1.3 95 6.6.5 PMA Standard Speed Ability: Address 1.4 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:7 Reserved Internal reserved - do not modify 6 PMA 10M Capable 1 = PMA is 10 Mb/s capable 0 = PMA is not 10 Mb/s capable ROS 0 This is always set to 0 in the AQR405. 5 PMA 100M Capable 1 = PMA is 100 Mb/s capable 0 = PMA is not 100 Mb/s capable ROS 1 This is always set to 1 in the AQR405. 4 PMA 1G Capable 1 = PMA is 1 Gb/s capable 0 = PMA is not 1 Gb/s capable ROS 1 This is always set to 1 in the AQR405. 3 Reserved Internal reserved - do not modify 2 10PASS-TS Capable 1 = PMA is 10PASS-TS capable 0 = PMA is not 10PASS-TS capable ROS 0 This is always set to 0 in the AQR405. 1 2BASE-TL Capable 1 = PMA is 2BASE-TL capable 0 = PMA is not 2BASE-TL capable ROS 0 This is always set to 0 in the AQR405. 0 PMA 10G Capable 1 = PMA is 10 Gb/s capable 0 = PMA is not 10 Gb/s capable ROS 1 This is always set to 1 in the AQR405. Table 6.9 PMA Standard Speed Ability: Address 1.4 6.6.6 PMA Standard Devices in Package 1: Address 1.5 Bit F:8 7 Name Description Reserved Internal reserved - do not modify Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package Type Default ROS 1 Note This is always set to 1, as there is Autonegotiation in the AQR405. Table 6.10 PMA Standard Devices in Package 1: Address 1.5 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - January 5, 2015 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. 5 DTE XS Present 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no DTE XAUI interface in the AQR405. 4 PHY XS Present 1 = PHY XS is present in package 0 = PHY XS is not present in package ROS 1 This is always set to 1 as there is a PHY XS interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.10 PMA Standard Devices in Package 1: Address 1.5 6.6.7 PMA Standard Devices in Package 2: Address 1.6 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the Global registers. Table 6.11 PMA Standard Devices in Package 2: Address 1.6 97 Bit Name Description Type Default ROS 1 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package C:0 Reserved Internal reserved - do not modify Note This is always set to 1 as the AQR405 utilizes this device for the GbE registers. Table 6.11 PMA Standard Devices in Package 2: Address 1.6 6.6.8 PMA Standard Control 2: Address 1.7 Bit Name Description F:4 Reserved Internal reserved - do not modify 3:0 PMA Device Type [3:0] [3:0] 3210 1 1 1 1 = 10BASE-T PMA/PMD type 1 1 1 0 = 100BASE-TX PMA/PMD type 1 1 0 1 = 1000BASE-KX PMA/PMD type 1 1 0 0 = 1000BASE-T PMA/PMD type 1 0 1 1 = 10GBASE-KR PMA/PMD type 1 0 1 0 = 10GBASE-KX4 PMA/PMD type 1 0 0 1 = 10GBASE-T PMA type 1 0 0 0 = 10GBASE-LRM PMA/PMD type 0 1 1 1 = 10GBASE-SR PMA/PMD type 0 1 1 0 = 10GBASE-LR PMA/PMD type 0 1 0 1 = 10GBASE-ER PMA/PMD type 0 1 0 0 = 10GBASE-LX4 PMA/PMD type 0 0 1 1 = 10GBASE-SW PMA/PMD type 0 0 1 0 = 10GBASE-LW PMA/PMD type 0 0 0 1 = 10GBASE-EW PMA/PMD type 0 0 0 0 = 10GBASE-CX4 PMA/PMD type Type Default ROS 0x9 Note This is always set to 0x9 as the AQR405 is a 10GBASE-T device. Table 6.12 PMA Standard Control 2: Address 1.7 6.6.9 PMA Standard Status 2: Address 1.8 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - January 5, 2015 Device Present [1:0] [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address ROS 0x2 This field is always set to 0x2, as the PMA is present in the AQR405. D Transmit Fault Location Ability 1 = PMA has the capability to detect a fault condition on the transmit path 0= PMA does not have the capability to detect a fault condition on the transmit path ROS 1 This bit indicates whether the PMA has the ability to locate faults along the transmit path. C Receive Fault Location Ability 1 = PMA has the capability to detect a fault condition on the receive path 0= PMA does not have the capability to detect a fault condition on the receive path ROS 1 This bit indicates whether the PMA has the ability to locate faults along the receive path. B Transmit Fault 1 = Fault condition on transmit path 0 = No fault condition on transmit path LH This bit indicates whether there is a fault somewhere along the transmit path. This is a hardware fault and should never occur during normal operation. A Receive Fault 1 = Fault condition on receive path 0 = No fault condition on receive path LH This bit indicates whether there is a fault somewhere along the receive path.This is a hardware fault and should never occur during normal operation. 9 Extended Abilities 1 = PMA has extended abilities listed in regsister 1.11 0= PMA does not have extended abilities ROS 1 This field is set to 1, as the PMA in AQR405 has extended abilities. 8 PMD Transmit Disable Ability 1 = PMD has the capability of disabling the transmitter 0= PMD does not have the capability of disabling the transmitter ROS 1 This bit indicates whether the PMD has the capability of disabling its transmitter. This field is always set to 0x1, as the PMD in the AQR405 has this ability. Table 6.13 PMA Standard Status 2: Address 1.8 99 F:E Bit Name Description Type Default Note Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - Janu- 7 PMA 10GBASE-SR Capable 1 = PMA supports 10GBASE-SR 0 = PMA does not support 10GBASE-SR ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 6 PMA 10GBASE-LR Capable 1 = PMA supports 10GBASE-LR 0 = PMA does not support 10GBASE-LR ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 5 PMA 10GBASE-ER Capable 1 = PMA supports 10GBASE-ER 0 = PMA does not support 10GBASE-ER ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 4 PMA 10GBASE-LX4 Capable 1 = PMA supports 10GBASE-LX4 0 = PMA does not support 10GBASE-LX4 ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 3 PMA 10GBASE-SW Capable 1 = PMA supports 10GBASE-SW 0 = PMA does not support 10GBASE-SW ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 2 PMA 10GBASE-LW Capable 1 = PMA supports 10GBASE-LW 0 = PMA does not support 10GBASE-LW ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 1 PMA 10GBASE-EW Capable 1 = PMA supports 10GBASE-EW 0 = PMA does not support 10GBASE-EW ROS 0 This field is always set to 0, as the PMA in the AQR405 only supports 10GBASE-T. 0 PMA Loopback Ability 1 = PMA supports loopback 0 = PMA does not support loopback ROS 1 This is always set to 1, as the PMA in the AQR405 supports loopback. Table 6.13 PMA Standard Status 2: Address 1.8 6.6.10 PMD Standard Transmit Disable Control: Address 1.9 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:5 Name Description Type Default Revision 0.11 - January 5, 2015 - January 5, 2015 Reserved Internal reserved - do not modify 4 PMD Channel 3 Transmit Disable 1 = Disable output on transmit channel 3 0 = Normal operation R/W PD 0 3 PMD Channel 2 Transmit Disable 1 = Disable output on transmit channel 2 0 = Normal operation R/W PD 0 2 PMD Channel 1 Transmit Disable 1 = Disable output on transmit channel 1 0 = Normal operation R/W PD 0 1 PMD Channel 0 Transmit Disable 1 = Disable output on transmit channel 0 0 = Normal operation R/W PD 0 PMD Global Transmit Disable 1 = Disable output on all channels 0 = Normal operation R/W PD 0 0 Note When disabled, the average launch power on a pair is set to less than -53 dBm NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F When set, this bit disables (and overrides) all four channels, and sets the average launch power on all pairs to less than -53 dBm NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F Table 6.14 PMD Standard Transmit Disable Control: Address 1.9 6.6.11 PMD Standard Signal Detect: Address 1.A Bit F:5 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.15 PMD Standard Signal Detect: Address 1.A 101 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description Type 4 PMD Channel 3 Signal Detect 1 = Signal detected on receive channel 3 0 = No signal detected RO 3 PMD Channel 2 Signal Detect 1 = Signal detected on receive channel 2 0 = No signal detected RO 2 PMD Channel 1 Signal Detect 1 = Signal detected on receive channel 1 0 = No signal detected RO 1 PMD Channel 0 Signal Detect 1 = Signal detected on receive channel 0 0 = No signal detected RO 0 PMD Global Signal Detect 1 = Signals detected on all required channels 0 = No signal detected RO Default Note These bits are used to indicate the presence of signals on a given pair. A signal is defined as an autonegotiation pulse or Ethernet signals. This bit is marked when all required, valid Ethernet signals to create a connection are present on the line. Table 6.15 PMD Standard Signal Detect: Address 1.A 6.6.12 PMD Standard 10G Extended Ability Register: Address 1.B Bit F:9 Name Description Type Default Note Reserved Internal reserved - do not modify 8 PMA 10BASE-T Capable 1 = PMA capable of 10BASE-T 0 = PMA incapable of 10BASE-T ROS 0 This field is always set to 0, as the PMA in the AQR405 does not support 10BASE-TX. 7 PMA 100BASE-TX Capable 1 = PMA capable of 100BASE-TX 0 = PMA incapable of 100BASE-TX ROS 1 This field is always set to 1, as the PMA in the AQR405 supports 100BASE-TX. 6 PMA 1000BASE-KX Capable 1 = PMA capable of 1000BASE-KX 0 = PMA incapable of 1000BASE-KX ROS 1 This field is always set to 1, as the PMA in the AQR405 supports 1000BASE-KX. Table 6.16 PMD Standard 10G Extended Ability Register: Address 1.B Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - January 5, 2015 5 PMA 1000BASE-T Capable 1 = PMA capable of 1000BASE-T 0 = PMA incapable of 1000BASE-T ROS 1 This field is set to 1, as the PMA in the AQR405 supports 1000BASE-T. 4 PMA 10GBASE-KR Capable 1 = PMA capable of 10GBASE-KR 0 = PMA incapable of 10GBASE-KR ROS 1 This field is set to 1, as the PMA in the AQR405 supports 10GBASE-KR 3 PMA 10GBASE-KX4 Capable 1 = PMA capable of 10GBASE-KX4 0 = PMA incapable of 10GBASE-KX4 ROS 1 This field is set to 1, as the PMA in the AQR405 supports 10GBASE-KX4 2 PMA 10GBASE-T Capable 1 = PMA capable of 10GBASE-T 0 = PMA incapable of 10GBASE-T ROS 1 This field is set to 1, as the PMA in the AQR405 supports 10GBASE-T 1 PMA 10GBASE-LRM Capable 1 = PMA capable of 10GBASE-LRM 0 = PMA incapable of 10GBASE-LRM ROS 0 This field is always set to 0, as the PMA in the AQR405 does not support 10GBASE-LRM. 0 PMA 10GBASE-CX4 Capable 1 = PMA capable of 10GBASE-CX4 0 = PMA incapable of 10GBASE-CX4 ROS 0 This field is always set to 0, as the PMA in the AQR405 does not support 10GBASE-CX4. Table 6.16 PMD Standard 10G Extended Ability Register: Address 1.B 6.6.13 PMA Standard Package Identifier 1: Address 1.E Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.17 PMA Standard Package Identifier 1: Address 1.E 103 6.6.14 PMA Standard Package Identifier 2: Address 1.F Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default Note RO Table 6.18 PMA Standard Package Identifier 2: Address 1.F 6.6.15 PMA 10GBASE-T Status: Address 1.81 Bit F:1 0 Name Description Reserved Internal reserved - do not modify Link Partner Information Valid 1 = 10GBASE-T Link Partner information is valid 0 = 10GBASE-T Link Partner information is not valid Type Default RO Note When set, this bit indicates that the startup protocol (55.4.2.5) has completed. Table 6.19 PMA 10GBASE-T Status: Address 1.81 6.6.16 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 Bit Name Description F:C Reserved Internal reserved - do not modify B:8 Pair Polarity [3:0] 1 = Polarity of Pair is reversed 0 = Polarity of Pair is normal [3] = Pair D Polarity [2] = Pair C Polarity [1] = Pair B Polarity [0] = Pair A Polarity Type RO Default Note When set, this bit indicates that the wires on the respective pair are reversed. Table 6.20 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 7:2 Reserved Internal reserved - do not modify 1:0 MDI / MD-X Connection State [1:0] [1:0] 1 1 = No crossover 1 0 = Pair A / B crossover 0 1 = Pair C / D crossover 0 0 = Pair A / B and C / D crossover Type Default RO Note These two bits indicate the current status of pair swaps at the MDI / MD-X Table 6.20 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 6.6.17 PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 Bit Name Description Type Default Note Revision 0.11 - January 5, 2015 - January 5, 2015 Link Partner Tx Power Backoff [2:0] [F:D] 0x7 = 14 dB 0x6 = 12 dB 0x5 = 10 dB 0x4 = 8 dB 0x3 = 6 dB 0x2 = 4 dB 0x1 = 2 dB 0x0 = 0 dB RO The power backoff of the link partner C:A Tx Power Backoff [2:0] [C:A] 0x7 = 14 dB 0x6 = 12 dB 0x5 = 10 dB 0x4 = 8 dB 0x3 = 6 dB 0x2 = 4 dB 0x1 = 2 dB 0x0 = 0 dB RO The power backoff of the PMA 9:1 Reserved Internal reserved - do not modify Short Reach Mode 1 = Set PMA to operate in short-reach mode 0 = PMA is in normal operation 0 R/W PD 0 When set, this bit places the PMA into short-reach mode Table 6.21 PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 105 F:D 6.6.18 PMA 10GBASE-T Test Modes: Address 1.84 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:D Name Test Mode Control [2:0] Description Type Default [F:D] 0x7 = Pseudo random test mode for BER Monitor 0x6 = Transmitter Droop test 0x5 = PSD and power level test 0x4 = Transmitter distortion test 0x3 = Slave mode jitter test 0x2 = Master mode jitter test 0x1 = Master source for slave mode jitter test 0x0 = Normal operation R/W PD 0x0 R/W PD C:A Transmitter Test Frequencies [2:0] [C:A] 0x7 = Reserved 0x6 = Dual Tone #5 0x5 = Dual Tone #4 0x4 = Dual Tone #3 0x3 = Reserved 0x2 = Dual Tone #2 0x1 = Dual Tone #1 0x0 = Reserved 9:0 Reserved Internal reserved - do not modify Note Test mode control for the PMA as defined in Section 55.5.2 of 802.3an. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 0x0 The test frequencies associated with Test Mode #4 in [F:D]. Table 6.22 PMA 10GBASE-T Test Modes: Address 1.84 6.6.19 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name F:0 Channel A Operating Margin [F:0] Description Operating margin (dB) of Channel A Type Default RO Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.23 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85 6.6.20 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name F:0 Channel B Operating Margin [F:0] Description Operating margin (dB) of Channel B Type RO Default Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.24 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86 107 6.6.21 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:0 Channel C Operating Margin [F:0] Description Operating margin (dB) of Channel C Type Default RO Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.25 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 6.6.22 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 Bit Name F:0 Channel D Operating Margin [F:0] Description Operating margin (dB) of Channel D Type RO Default Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.26 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 6.6.23 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Channel A Minimum Operating Margin [F:0] Minimum operating margin (dB) of Channel A since last link up Type Default RO Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.27 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 6.6.24 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name Description F:0 Channel B Minimum Operating Margin [F:0] Minimum operating margin (dB) of Channel B since last link up Type RO Default Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.28 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A 109 6.6.25 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Channel C Minimum Operating Margin [F:0] Minimum operating margin (dB) of Channel C since last link up Type Default RO Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.29 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B 6.6.26 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C Bit Name Description F:0 Channel D Minimum Operating Margin [F:0] Minimum operating margin (dB) of Channel D since last link up Type RO Default Note The excess SNR that is enjoyed by the channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.30 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C 6.6.27 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name F:0 Channel A Received Signal Power [F:0] Description Received signal power (dBm) for Channel A Type Default RO Note The received signal power on the channel. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -20.0 dB to +5.5dB. The number is in offset two's complement notation, with 0.0 dB represented by 0x8000. Table 6.31 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D 6.6.28 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name F:0 Channel B Received Signal Power [F:0] Description Received signal power (dBm) for Channel B Type Default RO Note The received signal power on the channel. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -20.0 dB to +5.5dB. The number is in offset two's complement notation, with 0.0 dB represented by 0x8000. Table 6.32 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E 6.6.29 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F Bit Name F:0 Channel C Received Signal Power [F:0] Description Received signal power (dBm) for Channel C Type RO Default Note Table 6.33 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F 111 The received signal power on the channel. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -20.0 dB to +5.5dB. The number is in offset two's complement notation, with 0.0 dB represented by 0x8000. 6.6.30 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:0 Channel D Received Signal Power [F:0] Description Type Received signal power (dBm) for Channel D Default RO Note The received signal power on the channel. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -20.0 dB to +5.5dB. The number is in offset two's complement notation, with 0.0 dB represented by 0x8000. Table 6.34 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 6.6.31 PMA 10GBASE-T Skew Delay 1: Address 1.91 Bit F Name Description Reserved Internal reserved - do not modify E:8 Skew Delay B [6:0] Skew delay for pair B 7:0 Reserved Internal reserved - do not modify Type RO Default Note The skew delay reports the current skew delay on each of the pair with respect to physical pair A. It is reported with 1.25 ns resolution to an accuracy of 2.5 ns. The number is in two's complement notation with positive values representing delay and negative values representing advance with respect to physical pair A. If the delay exceed the maximum amount that can be represented by the range (-80 ns to +78.75 ns), the field displays the maximum respective value. Table 6.35 PMA 10GBASE-T Skew Delay 1: Address 1.91 6.6.32 PMA 10GBASE-T Skew Delay 2: Address 1.92 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F E:8 Revision 0.11 - January 5, 2015 - January 5, 2015 7 6:0 Name Description Reserved Internal reserved - do not modify Skew Delay D [6:0] Skew delay for pair D Reserved Internal reserved - do not modify Skew Delay C [6:0] Skew delay for pair C Type Default Note RO The skew delay reports the current skew delay on each of the pair with respect to physical pair A. It is reported with 1.25 ns resolution to an accuracy of 2.5 ns. The number is in two's complement notation with positive values representing delay and negative values representing advance with respect to physical pair A. If the delay exceed the maximum amount that can be represented by the range (-80 ns to +78.75 ns), the field displays the maximum respective value. RO The skew delay reports the current skew delay on each of the pair with respect to physical pair A. It is reported with 1.25 ns resolution to an accuracy of 2.5 ns. The number is in two's complement notation with positive values representing delay and negative values representing advance with respect to physical pair A. If the delay exceed the maximum amount that can be represented by the range (-80 ns to +78.75 ns), the field displays the maximum respective value. Table 6.36 PMA 10GBASE-T Skew Delay 2: Address 1.92 113 6.6.33 PMA 10GBASE-T Fast Retrain Status and Control: Address 1.93 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:B LP Fast Retrain Count [4:0] A:6 Type Default Counts the number of fast retrains requested by the link partner SCT 0x00 Saturating clear on read counter. LD Fast Retrain Count [4:0] Counts the number of fast retrains requested by the local device SCT 0x00 Saturating clear on read counter. 5 Reserved Internal reserved - do not modify 4 Fast Retrain Ability 1 = Fast retrain capability is supported 0 = Fast retrain capability is not supported RO 3 Fast Retrain Negotiated 1 = Fast retrain capability was negotiated 0 = Fast retrain capability was not negotiated RO Fast Retrain Signal Type [1:0] 11 = Reserved 10 = PHY signals Link Interruption during fast retrain 01 = PHY signals Local Fault during fast retrain 00 = PHY signals IDLE during fast retrain R/W 0x0 Fast Retrain Enable 1 = Fast retrain capability is enabled 0 = Fast retrain capability is disabled R/W 0 2:1 0 Description Note Table 6.37 PMA 10GBASE-T Fast Retrain Status and Control : Address 1.93 6.6.34 TimeSync PMA Capability: Address 1.1800 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:2 Name Description Type Reserved Internal reserved - do not modify 1 TimeSync Transmit Path Data Delay 1 = PMA provides information on transmit path data delay in registers 1.1801 through 1.1804 0 = PMA does not provide information on transmit path data delay RO 0 TimeSync Receive Path Data Delay 1 = PMA provides information on receive path data delay in registers 1.1805 through 1.1808 0 = PMA does not provide information on receive path data delay RO Default Note Revision 0.11 - January 5, 2015 - January 5, 2015 Table 6.38 TimeSync PMA Capability: Address 1.1800 6.6.35 TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 Bit Name Description F:0 Maximum PMA Transmit Path Data Delay LSW [F:0] LSW of maximum PMA transmit delay in nanoseconds Type Default Note RO Table 6.39 TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 6.6.36 TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 Bit F:0 Name MSW of maximum PMA transmit delay in nanoseconds Type Default Note RO Table 6.40 TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 115 Maximum PMA Transmit Path Data Delay MSW [F:0] Description 6.6.37 TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Minimum PMA Transmit Path Data Delay LSW [F:0] LSW of minimum PMA transmit delay in nanoseconds Type Default Note RO Table 6.41 TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 6.6.38 TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 Bit F:0 Name Minimum PMA Transmit Path Data Delay MSW [F:0] Description MSW of minimum PMA transmit delay in nanoseconds Type Default Note RO Table 6.42 TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 6.6.39 TimeSync PMA Receive Path Data Delay 1: Address 1.1805 Bit Name Description F:0 Maximum PMA Receive Path Data Delay LSW [F:0] LSW of maximum PMA receive delay in nanoseconds Type Default RO Table 6.43 TimeSync PMA Receive Path Data Delay 1: Address 1.1805 Note 6.6.40 TimeSync PMA Receive Path Data Delay 2: Address 1.1806 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:0 Name Maximum PMA Receive Path Data Delay MSW [F:0] Description MSW of maximum PMA receive delay in nanoseconds Type Default Note RO Table 6.44 TimeSync PMA Receive Path Data Delay 2: Address 1.1806 6.6.41 TimeSync PMA Receive Path Data Delay 3: Address 1.1807 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name Description F:0 Minimum PMA Receive Path Data Delay LSW [F:0] LSW of minimum PMA receive delay in nanoseconds Type Default Note RO Table 6.45 TimeSync PMA Receive Path Data Delay 3: Address 1.1807 6.6.42 TimeSync PMA Receive Path Data Delay 4: Address 1.1808 Bit F:0 Name Minimum PMA Receive Path Data Delay MSW [F:0] Description MSW of minimum PMA receive delay in nanoseconds Type Default Note RO Table 6.46 TimeSync PMA Receive Path Data Delay 4: Address 1.1808 117 6.6.43 XENPAK Control: Address 1.8000 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:9 Vendor Specific [6:0] Reserved 8:6 Reserved Internal reserved - do not modify 5 Command 1 = Read NVR 0 = Write NVR Type Default R/W 0x00 R/W 0 Note Writing to this register initiates the command indicated by the value that is written. These commands are used in conjunction with regular MDIO reads and writes to burn the value permanently into the NVR, versus just altering a volatile copy of the register. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 4 Reserved Internal reserved - do not modify 3:2 Command Status [1:0] [3:2] 0x3 = Command failed 0x2 = Command in progress 0x1 = Command succeeded 0x0 = Idle RO 1:0 Extended Commands [1:0] [1:0] 0x3 = Read all NVR contents 0x2 = Vendor Specific 0x1 = Vendor Specific 0x0 = Vendor Specific R/W Status of command. When a command has completed, the read returns either 0x3 or 0x1, depending on the outcome of the command. Subsequent reads return Idle (0x0), until a new command is initiated. This field is RO by the MDIO and is R/W by the uP and will automatically clear to 0x0 when the value is either 0x3 or 0x1 when read by the MDIO. 0x0 Table 6.47 XENPAK Control: Address 1.8000 If the extended command bits are set to 0x3 when a read command is issued, all of the NVR volatile registers will have their values re-initialized to the default values stored in the NVR. This is similar to a reset. 6.6.44 XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Version [7:0] [7:0] = Version * 10 Type Default RO Note Version * 10: i.e Maximum version = 25.5. Table 6.48 XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 6.6.45 XENPAK Header - NVR Size 1: Address 1.8008 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 NVR Size MSW [F:8] [7:0] = Bits [F:8] of NVR size in bytes Type Default ROS 0x01 Note 256 Bytes synthetic NVR Table 6.49 XENPAK Header - NVR Size 1: Address 1.8008 6.6.46 XENPAK Header - NVR Size 2: Address 1.8009 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 NVR Size LSW [7:0] [7:0] = Bits [7:0] of NVR size in bytes Type Default ROS 0x00 Note 256 Bytes synthetic NVR Table 6.50 XENPAK Header - NVR Size 2: Address 1.8009 119 6.6.47 XENPAK Header - Memory Used 1: Address 1.800A Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Memory Used MSW [7:0] [7:0] = Bits [F:8] of memory used in bytes Type Default ROS 0x01 Note Table 6.51 XENPAK Header - Memory Used 1: Address 1.800A 6.6.48 XENPAK Header - Memory Used 2: Address 1.800B Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Memory Used LSW [7:0] [7:0] = Bits [7:0] of memory used in bytes Type Default ROS 0x00 Note Table 6.52 XENPAK Header - Memory Used 2: Address 1.800B 6.6.49 XENPAK Header - Basic Memory Start Address: Address 1.800C Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Basic Memory Offset [7:0] [7:0] = Basic memory start address Type Default ROS 0x0C Note The address where the basic memory starts in the NVR. Table 6.53 XENPAK Header - Basic Memory Start Address: Address 1.800C 6.6.50 XENPAK Header - Customer Memory Offset: Address 1.800D Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Customer Memory Offset [7:0] [7:0] = Customer memory start address Type Default ROS 0x7E Note The address where the customer memory starts. Table 6.54 XENPAK Header - Customer Memory Offset: Address 1.800D 6.6.51 XENPAK Header - Vendor Memory Start Address: Address 1.800E Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor Memory Offset [7:0] [7:0] = Vendor memory start address Type Default ROS 0xAE Note The address where the vendor memory starts. Table 6.55 XENPAK Header - Vendor Memory Start Address: Address 1.800E 6.6.52 XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Extended Vendor Offset LSW [7:0] [7:0] = Bits [7:0] of extended vendor memory start address Type Default ROS 0x07 Note The LSW of the address where the extended vendor memory starts. Table 6.56 XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F 121 6.6.53 XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Extended Vendor Offset MSW [7:0] [7:0] = Bits [F:8] of extended vendor memory start address Type Default ROS 0x01 Note The MSW of the address where the extended vendor memory starts. Table 6.57 XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 6.6.54 XENPAK Basic - Reserved 0x11: Address 1.8011 Bit Name F:8 Reserved 7:0 Basic Reserved 0x11 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.58 XENPAK Basic - Reserved 0x11: Address 1.8011 6.6.55 XENPAK Basic - Transceiver Type: Address 1.8012 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Transceiver Type [7:0] [7:0] 0x8 0x2 = Reserved 0x1 = XENPAK 0x0 = Unspecified Type Default ROS 0x01 Note All non-power of 2 values are invalid. Table 6.59 XENPAK Basic - Transceiver Type: Address 1.8012 6.6.56 XENPAK Basic - Connector Type: Address 1.8013 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Connector Type [7:0] [7:0] 0x80 = Reserved 0x40 = RJ-45 0x20 = Pigtail 0x10 = FC / PC 0x08 = MU 0x04 = MT-RJ 0x02 = LC 0x01 = SC 0x00 = Unspecified Type Default ROS 0x40 Note The connector type used. Note the power of 2 encoding. All non-power of 2 values are invalid. Table 6.60 XENPAK Basic - Connector Type: Address 1.8013 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.57 XENPAK Basic - Encoding: Address 1.8014 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Encoding [7:0] [7:0] 0x8 = Reserved 0x4 = 128 DSQ 0x2 = FEC 0x1 = NRZ 0x0 = Unspecified Type Default ROS 0x04 Note All non-power of 2 values are invalid. Table 6.61 XENPAK Basic - Encoding: Address 1.8014 123 6.6.58 XENPAK Basic - Bit Rate 0: Address 1.8015 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Bit Rate MSW [F:8] [7:0] = [7:0] of bit rate in Mb/s Type Default ROS 0x27 Note 0x2710 = 10,000 Mb/s Table 6.62 XENPAK Basic - Bit Rate 0: Address 1.8015 6.6.59 XENPAK Basic - Bit Rate 1: Address 1.8016 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Bit Rate LSW [7:0] [7:0] = [F:8] of bit rate in Mb/s Type Default ROS 0x10 Note 0x2710 = 10,000 Mb/s Table 6.63 XENPAK Basic - Bit Rate 1: Address 1.8016 6.6.60 XENPAK Basic - Protocol: Address 1.8017 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Protocol [7:0] [7:0] 0x80 0x20 = Reserved 0x10 = SONET / SDH 0x08 = LSS 0x04 = WIS 0x02 = 10GFC 0x01 = 10 GbE 0x0 = Unspecified Type Default ROS 0x01 Note All non-power of 2 values are invalid. Table 6.64 XENPAK Basic - Protocol: Address 1.8017 6.6.61 XENPAK Basic - Standards Compliance Codes: Address 1.8018 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Standard Code [7:0] [7:0] 0x80 = 10GBASE-T 0x40 = 10GBASE-EW 0x20 = 10GBASE-LW 0x10 = 10GBASE-SW 0x08 = 10GBASE-LX4 0x04 = 10GBASE-ER 0x02 = 10GBASE-LR 0x01 = 10GBASE-SR 0x0 = Unspecified Type Default ROS 0x80 Note All non-power of 2 values are invalid. Table 6.65 XENPAK Basic - Standards Compliance Codes: Address 1.8018 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.62 XENPAK Basic - Reserved 0x19 1: Address 1.8019 Bit Name F:8 Reserved 7:0 Basic Reserved 0x19 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.66 XENPAK Basic - Reserved 0x19 1: Address 1.8019 6.6.63 XENPAK Basic - Reserved 0x19 2: Address 1.801A Bit Name Reserved 7:0 Basic Reserved 0x1A [7:0] Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.67 XENPAK Basic - Reserved 0x19 2: Address 1.801A 125 F:8 Description 6.6.64 XENPAK Basic - Reserved 0x19 3: Address 1.801B Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Basic Reserved 0x1B [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.68 XENPAK Basic - Reserved 0x19 3: Address 1.801B 6.6.65 XENPAK Basic - Reserved 0x19 4: Address 1.801C Bit Name F:8 Reserved 7:0 Basic Reserved 0x1C [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.69 XENPAK Basic - Reserved 0x19 4: Address 1.801C 6.6.66 XENPAK Basic - Reserved 0x19 5: Address 1.801D Bit Name F:8 Reserved 7:0 Basic Reserved 0x1D [7:0] Description Type Default ROS 0x00 Internal reserved - do not modify Table 6.70 XENPAK Basic - Reserved 0x19 5: Address 1.801D Note 6.6.67 XENPAK Basic - Reserved 0x19 6: Address 1.801E Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Basic Reserved 0x1E [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.71 XENPAK Basic - Reserved 0x19 6: Address 1.801E 6.6.68 XENPAK Basic - Reserved 0x19 7: Address 1.801F Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Basic Reserved 0x1F [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.72 XENPAK Basic - Reserved 0x19 7: Address 1.801F 6.6.69 XENPAK Basic - Reserved 0x19 8: Address 1.8020 Bit Name F:8 Reserved 7:0 Basic Reserved 0x20 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.73 XENPAK Basic - Reserved 0x19 8: Address 1.8020 127 6.6.70 XENPAK Basic - Reserved 0x19 9: Address 1.8021 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Basic Reserved 0x21 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.74 XENPAK Basic - Reserved 0x19 9: Address 1.8021 6.6.71 XENPAK Basic - Reserved 0x19 10: Address 1.8022 Bit Name F:8 Reserved 7:0 Basic Reserved 0x22 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.75 XENPAK Basic - Reserved 0x19 10: Address 1.8022 6.6.72 XENPAK Basic - Reserved 0x19 11: Address 1.8023 Bit Name F:8 Reserved 7:0 Basic Reserved 0x23 [7:0] Description Type Default ROS 0x00 Internal reserved - do not modify Table 6.76 XENPAK Basic - Reserved 0x19 11: Address 1.8023 Note 6.6.73 XENPAK Basic - Reserved 0x19 12: Address 1.8024 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Basic Reserved 0x24 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.77 XENPAK Basic - Reserved 0x19 12: Address 1.8024 6.6.74 XENPAK Basic - Reserved 0x19 13: Address 1.8025 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Basic Reserved 0x25 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.78 XENPAK Basic - Reserved 0x19 13: Address 1.8025 6.6.75 XENPAK Basic - Reserved 0x19 14: Address 1.8026 Bit Name F:8 Reserved 7:0 Basic Reserved 0x26 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.79 XENPAK Basic - Reserved 0x19 14: Address 1.8026 129 6.6.76 XENPAK Basic - Reserved 0x19 15: Address 1.8027 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Basic Reserved 0x27 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.80 XENPAK Basic - Reserved 0x19 15: Address 1.8027 6.6.77 XENPAK Basic - Reserved 0x19 16: Address 1.8028 Bit Name F:8 Reserved 7:0 Basic Reserved 0x28 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.81 XENPAK Basic - Reserved 0x19 16: Address 1.8028 6.6.78 XENPAK Basic - Reserved 0x19 17: Address 1.8029 Bit Name F:8 Reserved 7:0 Basic Reserved 0x29 [7:0] Description Type Default ROS 0x00 Internal reserved - do not modify Table 6.82 XENPAK Basic - Reserved 0x19 17: Address 1.8029 Note 6.6.79 XENPAK Basic - Reserved 0x19 18: Address 1.802A Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Basic Reserved 0x2A [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.83 XENPAK Basic - Reserved 0x19 18: Address 1.802A 6.6.80 XENPAK Basic - Reserved 0x19 19: Address 1.802B Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Basic Reserved 0x2B [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.84 XENPAK Basic - Reserved 0x19 19: Address 1.802B 6.6.81 XENPAK Basic - Reserved 0x19 20: Address 1.802C Bit Name F:8 Reserved 7:0 Basic Reserved 0x2C [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.85 XENPAK Basic - Reserved 0x19 20: Address 1.802C 131 6.6.82 XENPAK Basic - Reserved 0x19 21: Address 1.802D Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Basic Reserved 0x2D [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.86 XENPAK Basic - Reserved 0x19 21: Address 1.802D 6.6.83 XENPAK Basic - Reserved 0x19 22: Address 1.802E Bit Name F:8 Reserved 7:0 Basic Reserved 0x2E [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.87 XENPAK Basic - Reserved 0x19 22: Address 1.802E 6.6.84 XENPAK Basic - Reserved 0x19 23: Address 1.802F Bit Name F:8 Reserved 7:0 Basic Reserved 0x2F [7:0] Description Type Default ROS 0x00 Internal reserved - do not modify Table 6.88 XENPAK Basic - Reserved 0x19 23: Address 1.802F Note 6.6.85 XENPAK Basic - Reserved 0x19 24: Address 1.8030 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Basic Reserved 0x30 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.89 XENPAK Basic - Reserved 0x19 24: Address 1.8030 6.6.86 XENPAK Basic - Reserved 0x19 25: Address 1.8031 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Basic Reserved 0x31 [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.90 XENPAK Basic - Reserved 0x19 25: Address 1.8031 6.6.87 XENPAK Basic - Package Identifier 1: Address 1.8032 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Package ID 1 [1F:18] [7:0] = [1F:18] of Package ID Type Default RO Note Clone of Registers 1.E:F Table 6.91 XENPAK Basic - Package Identifier 1: Address 1.8032 6.6.88 XENPAK Basic - Package Identifier 2: Address 1.8033 Bit Name Description Reserved Internal reserved - do not modify 7:0 Package ID 2 [17:10] [7:0] = [17:10] of Package ID Default Note 133 F:8 Type RO Clone of Registers 1.E:F Table 6.92 XENPAK Basic - Package Identifier 2: Address 1.8033 6.6.89 XENPAK Basic - Package Identifier 3: Address 1.8034 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Package ID 3 [F:8] [7:0] = [F:8] of Package ID Type Default RO Note Clone of Registers 1.E:F Table 6.93 XENPAK Basic - Package Identifier 3: Address 1.8034 6.6.90 XENPAK Basic - Package Identifier 4: Address 1.8035 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Package ID 4 [7:0] [7:0] = [7:0] of Package ID Type Default RO Note Clone of Registers 1.E:F Table 6.94 XENPAK Basic - Package Identifier 4: Address 1.8035 6.6.91 XENPAK Basic - Vendor Identifier 1: Address 1.8036 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor ID 1 [1F:18] [7:0] = [1F:18] of Vendor ID Type Default RO Table 6.95 XENPAK Basic - Vendor Identifier 1: Address 1.8036 Note 6.6.92 XENPAK Basic - Vendor Identifier 2: Address 1.8037 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor ID 2 [17:10] [7:0] = [17:10] of Package ID Type Default Note RO Table 6.96 XENPAK Basic - Vendor Identifier 2: Address 1.8037 6.6.93 XENPAK Basic - Vendor Identifier 3: Address 1.8038 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor ID 3 [F:8] [7:0] = [F:8] of Package ID Type Default Note RO Revision 0.11 - January 5, 2015 - January 5, 2015 Table 6.97 XENPAK Basic - Vendor Identifier 3: Address 1.8038 6.6.94 XENPAK Basic - Vendor Identifier 4: Address 1.8039 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor ID 4 [7:0] [7:0] = [7:0] of Package ID Type Default Note RO Table 6.98 XENPAK Basic - Vendor Identifier 4: Address 1.8039 6.6.95 XENPAK Basic - Vendor Name 1: Address 1.803A Bit Name Description Reserved Internal reserved - do not modify 7:0 Vendor Name 1 [7:0] [7:0] = 1st Character Default RO Table 6.99 XENPAK Basic - Vendor Name 1: Address 1.803A Note 135 F:8 Type 6.6.96 XENPAK Basic - Vendor Name 2: Address 1.803B Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 2 [7:0] [7:0] = 2nd Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.100 XENPAK Basic - Vendor Name 2: Address 1.803B 6.6.97 XENPAK Basic - Vendor Name 3: Address 1.803C Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 3 [7:0] [7:0] = 3rd Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.101 XENPAK Basic - Vendor Name 3: Address 1.803C 6.6.98 XENPAK Basic - Vendor Name 4: Address 1.803D Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 4 [7:0] [7:0] = 4th Character Type RO Default Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.102 XENPAK Basic - Vendor Name 4: Address 1.803D 6.6.99 XENPAK Basic - Vendor Name 5: Address 1.803E Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 5 [7:0] [7:0] = 5th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.103 XENPAK Basic - Vendor Name 5: Address 1.803E 6.6.100 XENPAK Basic - Vendor Name 6: Address 1.803F Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 6 [7:0] [7:0] = 6th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.104 XENPAK Basic - Vendor Name 6: Address 1.803F 6.6.101 XENPAK Basic - Vendor Name 7: Address 1.8040 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 7 [7:0] [7:0] = 7th Character Type RO Default Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.105 XENPAK Basic - Vendor Name 7: Address 1.8040 137 6.6.102 XENPAK Basic - Vendor Name 8: Address 1.8041 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 8 [7:0] [7:0] = 8th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.106 XENPAK Basic - Vendor Name 8: Address 1.8041 6.6.103 XENPAK Basic - Vendor Name 9: Address 1.8042 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 9 [7:0] [7:0] = 9th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.107 XENPAK Basic - Vendor Name 9: Address 1.8042 6.6.104 XENPAK Basic - Vendor Name 10: Address 1.8043 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 10 [7:0] [7:0] = 10th Character Type RO Default Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.108 XENPAK Basic - Vendor Name 10: Address 1.8043 6.6.105 XENPAK Basic - Vendor Name 11: Address 1.8044 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 11 [7:0] [7:0] = 11th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.109 XENPAK Basic - Vendor Name 11: Address 1.8044 6.6.106 XENPAK Basic - Vendor Name 12: Address 1.8045 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 12 [7:0] [7:0] = 12th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.110 XENPAK Basic - Vendor Name 12: Address 1.8045 6.6.107 XENPAK Basic - Vendor Name 13: Address 1.8046 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 13 [7:0] [7:0] = 13th Character Type RO Default Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.111 XENPAK Basic - Vendor Name 13: Address 1.8046 139 6.6.108 XENPAK Basic - Vendor Name 14: Address 1.8047 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 14 [7:0] [7:0] = 14th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.112 XENPAK Basic - Vendor Name 14: Address 1.8047 6.6.109 XENPAK Basic - Vendor Name 15: Address 1.8048 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 15 [7:0] [7:0] = 15th Character Type Default RO Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.113 XENPAK Basic - Vendor Name 15: Address 1.8048 6.6.110 XENPAK Basic - Vendor Name 16: Address 1.8049 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Name 16 [7:0] [7:0] = 16th Character Type RO Default Note Vendor name in ASCII, left aligned, and zero padded on the right. Table 6.114 XENPAK Basic - Vendor Name 16: Address 1.8049 6.6.111 XENPAK Basic - Vendor Part Number 1: Address 1.804A Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 1 [7:0] [7:0] = 1st Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.115 XENPAK Basic - Vendor Part Number 1: Address 1.804A 6.6.112 XENPAK Basic - Vendor Part Number 2: Address 1.804B Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 2 [7:0] [7:0] = 2nd Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.116 XENPAK Basic - Vendor Part Number 2: Address 1.804B 6.6.113 XENPAK Basic - Vendor Part Number 3: Address 1.804C Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 3 [7:0] [7:0] = 3rd Character Type RO Default Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.117 XENPAK Basic - Vendor Part Number 3: Address 1.804C 141 6.6.114 XENPAK Basic - Vendor Part Number 4: Address 1.804D Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 4 [7:0] [7:0] = 4th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.118 XENPAK Basic - Vendor Part Number 4: Address 1.804D 6.6.115 XENPAK Basic - Vendor Part Number 5: Address 1.804E Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 5 [7:0] [7:0] = 5th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.119 XENPAK Basic - Vendor Part Number 5: Address 1.804E 6.6.116 XENPAK Basic - Vendor Part Number 6: Address 1.804F Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 6 [7:0] [7:0] = 6th Character Type RO Default Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.120 XENPAK Basic - Vendor Part Number 6: Address 1.804F 6.6.117 XENPAK Basic - Vendor Part Number 7: Address 1.8050 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 7 [7:0] [7:0] = 7th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.121 XENPAK Basic - Vendor Part Number 7: Address 1.8050 6.6.118 XENPAK Basic - Vendor Part Number 8: Address 1.8051 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 8 [7:0] [7:0] = 8th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.122 XENPAK Basic - Vendor Part Number 8: Address 1.8051 6.6.119 XENPAK Basic - Vendor Part Number 9: Address 1.8052 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 9 [7:0] [7:0] = 9th Character Type RO Default Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.123 XENPAK Basic - Vendor Part Number 9: Address 1.8052 143 6.6.120 XENPAK Basic - Vendor Part Number 10: Address 1.8053 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 10 [7:0] [7:0] = 10th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.124 XENPAK Basic - Vendor Part Number 10: Address 1.8053 6.6.121 XENPAK Basic - Vendor Part Number 11: Address 1.8054 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 11 [7:0] [7:0] = 11th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.125 XENPAK Basic - Vendor Part Number 11: Address 1.8054 6.6.122 XENPAK Basic - Vendor Part Number 12: Address 1.8055 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 12 [7:0] [7:0] = 12th Character Type RO Default Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.126 XENPAK Basic - Vendor Part Number 12: Address 1.8055 6.6.123 XENPAK Basic - Vendor Part Number 13: Address 1.8056 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 13 [7:0] [7:0] = 13th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.127 XENPAK Basic - Vendor Part Number 13: Address 1.8056 6.6.124 XENPAK Basic - Vendor Part Number 14: Address 1.8057 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 14 [7:0] [7:0] = 14th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.128 XENPAK Basic - Vendor Part Number 14: Address 1.8057 6.6.125 XENPAK Basic - Vendor Part Number 15: Address 1.8058 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 15 [7:0] [7:0] = 15th Character Type RO Default Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.129 XENPAK Basic - Vendor Part Number 15: Address 1.8058 145 6.6.126 XENPAK Basic - Vendor Part Number 16: Address 1.8059 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor PN 16 [7:0] [7:0] = 16th Character Type Default RO Note Vendor part number in ASCII, left aligned, and zero padded on the right. Table 6.130 XENPAK Basic - Vendor Part Number 16: Address 1.8059 6.6.127 XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Part RN 1 [7:0] [7:0] = 1st Character Type Default RO Note Vendor part revision number in ASCII, left aligned, and zero padded on the right. Table 6.131 XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A 6.6.128 XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor Part RN 2 [7:0] [7:0] = 2nd Character Type RO Default Note Vendor part revision number in ASCII, left aligned, and zero padded on the right. Table 6.132 XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B 6.6.129 XENPAK Basic - Vendor Serial Number 1: Address 1.805C Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 1 [7:0] [7:0] = 1st Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.133 XENPAK Basic - Vendor Serial Number 1: Address 1.805C 6.6.130 XENPAK Basic - Vendor Serial Number 2: Address 1.805D Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 2 [7:0] [7:0] = 2nd Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.134 XENPAK Basic - Vendor Serial Number 2: Address 1.805D 6.6.131 XENPAK Basic - Vendor Serial Number 3: Address 1.805E Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 3 [7:0] [7:0] = 3rd Character Type RO Default Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.135 XENPAK Basic - Vendor Serial Number 3: Address 1.805E 147 6.6.132 XENPAK Basic - Vendor Serial Number 4: Address 1.805F Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 4 [7:0] [7:0] = 4th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.136 XENPAK Basic - Vendor Serial Number 4: Address 1.805F 6.6.133 XENPAK Basic - Vendor Serial Number 5: Address 1.8060 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 5 [7:0] [7:0] = 5th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.137 XENPAK Basic - Vendor Serial Number 5: Address 1.8060 6.6.134 XENPAK Basic - Vendor Serial Number 6: Address 1.8061 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 6 [7:0] [7:0] = 6th Character Type RO Default Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.138 XENPAK Basic - Vendor Serial Number 6: Address 1.8061 6.6.135 XENPAK Basic - Vendor Serial Number 7: Address 1.8062 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 7 [7:0] [7:0] = 7th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.139 XENPAK Basic - Vendor Serial Number 7: Address 1.8062 6.6.136 XENPAK Basic - Vendor Serial Number 8: Address 1.8063 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 8 [7:0] [7:0] = 8th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.140 XENPAK Basic - Vendor Serial Number 8: Address 1.8063 6.6.137 XENPAK Basic - Vendor Serial Number 9: Address 1.8064 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 9 [7:0] [7:0] = 9th Character Type RO Default Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.141 XENPAK Basic - Vendor Serial Number 9: Address 1.8064 149 6.6.138 XENPAK Basic - Vendor Serial Number 10: Address 1.8065 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 10 [7:0] [7:0] = 10th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.142 XENPAK Basic - Vendor Serial Number 10: Address 1.8065 6.6.139 XENPAK Basic - Vendor Serial Number 11: Address 1.8066 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 11 [7:0] [7:0] = 11th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.143 XENPAK Basic - Vendor Serial Number 11: Address 1.8066 6.6.140 XENPAK Basic - Vendor Serial Number 12: Address 1.8067 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 12 [7:0] [7:0] = 12th Character Type RO Default Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.144 XENPAK Basic - Vendor Serial Number 12: Address 1.8067 6.6.141 XENPAK Basic - Vendor Serial Number 13: Address 1.8068 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 13 [7:0] [7:0] = 13th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.145 XENPAK Basic - Vendor Serial Number 13: Address 1.8068 6.6.142 XENPAK Basic - Vendor Serial Number 14: Address 1.8069 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 14 [7:0] [7:0] = 14th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.146 XENPAK Basic - Vendor Serial Number 14: Address 1.8069 6.6.143 XENPAK Basic - Vendor Serial Number 15: Address 1.806A Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 15 [7:0] [7:0] = 15th Character Type RO Default Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.147 XENPAK Basic - Vendor Serial Number 15: Address 1.806A 151 6.6.144 XENPAK Basic - Vendor Serial Number 16: Address 1.806B Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Vendor SN 16 [7:0] [7:0] = 16th Character Type Default RO Note Vendor serial number in ASCII, left aligned, and zero padded on the right. Table 6.148 XENPAK Basic - Vendor Serial Number 16: Address 1.806B 6.6.145 XENPAK Basic - Vendor Date Code 1: Address 1.806C Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Year 1 [7:0] [7:0] = 1st character of year Type Default RO Note ASCII 1000's character Table 6.149 XENPAK Basic - Vendor Date Code 1: Address 1.806C 6.6.146 XENPAK Basic - Vendor Date Code 2: Address 1.806D Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Year 2 [7:0] [7:0] = 2nd character of year Type RO Default Note ASCII 100's character Table 6.150 XENPAK Basic - Vendor Date Code 2: Address 1.806D 6.6.147 XENPAK Basic - Vendor Date Code 3: Address 1.806E Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Year 3 [7:0] [7:0] = 3rd character of year Type Default RO Note ASCII 10's character Table 6.151 XENPAK Basic - Vendor Date Code 3: Address 1.806E 6.6.148 XENPAK Basic - Vendor Date Code 4: Address 1.806F Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Year 4 [7:0] [7:0] = 4th character of year Type Default RO Note ASCII 1's character Revision 0.11 - January 5, 2015 - January 5, 2015 Table 6.152 XENPAK Basic - Vendor Date Code 4: Address 1.806F 6.6.149 XENPAK Basic - Vendor Date Code 5: Address 1.8070 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Month 1 [7:0] [7:0] = 1st character of month Type Default RO Note ASCII 10's character Table 6.153 XENPAK Basic - Vendor Date Code 5: Address 1.8070 6.6.150 XENPAK Basic - Vendor Date Code 6: Address 1.8071 Bit Name Description Reserved Internal reserved - do not modify 7:0 Month 2 [7:0] [7:0] = 2nd character of month RO Default Note ASCII 1's character Table 6.154 XENPAK Basic - Vendor Date Code 6: Address 1.8071 153 F:8 Type 6.6.151 XENPAK Basic - Vendor Date Code 7: Address 1.8072 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Day 1 [7:0] [7:0] = 1st character of day Type Default RO Note ASCII 10's character Table 6.155 XENPAK Basic - Vendor Date Code 7: Address 1.8072 6.6.152 XENPAK Basic - Vendor Date Code 8: Address 1.8073 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Day 2 [7:0] [7:0] = 2nd character of day Type Default RO Note ASCII 1's character Table 6.156 XENPAK Basic - Vendor Date Code 8: Address 1.8073 6.6.153 XENPAK Basic - Vendor Date Code 9: Address 1.8074 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Lot 1 [7:0] [7:0] = 1st character of lot Type RO Default Note ASCII 10's character Table 6.157 XENPAK Basic - Vendor Date Code 9: Address 1.8074 6.6.154 XENPAK Basic - Vendor Date Code 10: Address 1.8075 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Lot 2 [7:0] [7:0] = 2nd character of lot Type Default RO Note ASCII 1's character Table 6.158 XENPAK Basic - Vendor Date Code 10: Address 1.8075 6.6.155 XENPAK Basic - 5V Loading: Address 1.8076 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved Internal reserved - do not modify 7:0 5V Loading [7:0] [7:0] 0x80 = 90% - 99% 0x40 = 80% - 89% 0x20 = 70% - 79% 0x10 = 60% - 69% 0x08 = 50% - 59% 0x04 = 40% - 49% 0x02 = 30% - 39% 0x01 = 20% - 29% 0x0 = 5V not used Type RO Default Note All non-power of 2 values are invalid. Table 6.159 XENPAK Basic - 5V Loading: Address 1.8076 155 6.6.156 XENPAK Basic - 3.3V Loading: Address 1.8077 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 3.3V Loading [7:0] [7:0] 0x80 = 90% - 99% 0x40 = 80% - 89% 0x20 = 70% - 79% 0x10 = 60% - 69% 0x08 = 50% - 59% 0x04 = 40% - 49% 0x02 = 30% - 39% 0x01 = 20% - 29% 0x0 = 3.3V not used Type Default RO Note All non-power of 2 values are invalid. Table 6.160 XENPAK Basic - 3.3V Loading: Address 1.8077 6.6.157 XENPAK Basic - APS Loading: Address 1.8078 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 APS Loading [7:0] [7:0] 0x80 = 90% - 99% 0x40 = 80% - 89% 0x20 = 70% - 89% 0x10 = 60% - 89% 0x08 = 50% - 89% 0x04 = 40% - 89% 0x02 = 30% - 89% 0x01 = 20% - 89% 0x0 = APS not used Type RO Default Note All non-power of 2 values are invalid. Table 6.161 XENPAK Basic - APS Loading: Address 1.8078 6.6.158 XENPAK Basic - APS Voltage: Address 1.8079 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 APS Voltage [7:0] [7:0] 0x80 = Reserved 0x40 = C 0x20 = 1.8V 0x10 = 1.5V 0x08 = 1.3V 0x04 = 1.2V 0x02 = 1V 0x01 = 0.9V 0x0 = Unspecified Type Default RO Note All non-power of 2 values are invalid. Table 6.162 XENPAK Basic - APS Voltage: Address 1.8079 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.159 XENPAK Basic - DOM Capability: Address 1.807A Bit F:8 Name Description Type Default Note Reserved Internal reserved - do not modify 7 DOM Control Capability 1 = Implemented 0 = Not implemented ROS 1 When set this bit indicates whether the XENPAK supports DOM control and status registers. 6 DOM Capability 1 = Implemented 0 = Not implemented ROS 1 When set this bit indicates whether the XENPAK supports DOM. Reserved Internal reserved - do not modify 5:0 Table 6.163 XENPAK Basic - DOM Capability: Address 1.807A 157 6.6.160 XENPAK Basic - Low-Power Startup Capability: Address 1.807B Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:1 0 Name Description Reserved Internal reserved - do not modify Low Power Start-up Capability 1 = Low-power start-up capable 0 = Not capable Type Default ROS 1 Note When set this bit indicates whether the XENPAK can come up in a low-power mode. Table 6.164 XENPAK Basic - Low-Power Startup Capability: Address 1.807B 6.6.161 XENPAK Basic - Reserved 0x7C: Address 1.807C Bit Name F:8 Reserved 7:0 Basic Reserved 0x7C [7:0] Description Type Default ROS 0x00 Note Internal reserved - do not modify Table 6.165 XENPAK Basic - Reserved 0x7C: Address 1.807C 6.6.162 XENPAK Basic - Checksum: Address 1.807D Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Checksum [7:0] [7:0] = Checksum Type RO Default Note The checksum over the LSBs of all the registers from 1.8007 to 1.807C. Table 6.166 XENPAK Basic - Checksum: Address 1.807D 6.6.163 XENPAK Customer - Reserved 0x7E 1: Address 1.807E Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x7E [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.167 XENPAK Customer - Reserved 0x7E 1: Address 1.807E 6.6.164 XENPAK Customer - Reserved 0x7E 2: Address 1.807F Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x7F [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.168 XENPAK Customer - Reserved 0x7E 2: Address 1.807F 6.6.165 XENPAK Customer - Reserved 0x7E 3: Address 1.8080 Bit Name F:8 Reserved 7:0 Customer Reserved 0x80 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.169 XENPAK Customer - Reserved 0x7E 3: Address 1.8080 159 6.6.166 XENPAK Customer - Reserved 0x7E 4: Address 1.8081 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x81 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.170 XENPAK Customer - Reserved 0x7E 4: Address 1.8081 6.6.167 XENPAK Customer - Reserved 0x7E 5: Address 1.8082 Bit Name F:8 Reserved 7:0 Customer Reserved 0x82 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.171 XENPAK Customer - Reserved 0x7E 5: Address 1.8082 6.6.168 XENPAK Customer - Reserved 0x7E 6: Address 1.8083 Bit Name F:8 Reserved 7:0 Customer Reserved 0x83 [7:0] Description Type Default Internal reserved - do not modify RO Table 6.172 XENPAK Customer - Reserved 0x7E 6: Address 1.8083 Note 6.6.169 XENPAK Customer - Reserved 0x7E 7: Address 1.8084 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x84 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.173 XENPAK Customer - Reserved 0x7E 7: Address 1.8084 6.6.170 XENPAK Customer - Reserved 0x7E 8: Address 1.8085 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x85 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.174 XENPAK Customer - Reserved 0x7E 8: Address 1.8085 6.6.171 XENPAK Customer - Reserved 0x7E 9: Address 1.8086 Bit Name F:8 Reserved 7:0 Customer Reserved 0x86 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.175 XENPAK Customer - Reserved 0x7E 9: Address 1.8086 161 6.6.172 XENPAK Customer - Reserved 0x7E 10: Address 1.8087 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x87 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.176 XENPAK Customer - Reserved 0x7E 10: Address 1.8087 6.6.173 XENPAK Customer - Reserved 0x7E 11: Address 1.8088 Bit Name F:8 Reserved 7:0 Customer Reserved 0x88 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.177 XENPAK Customer - Reserved 0x7E 11: Address 1.8088 6.6.174 XENPAK Customer - Reserved 0x7E 12: Address 1.8089 Bit Name F:8 Reserved 7:0 Customer Reserved 0x89 [7:0] Description Type Default Internal reserved - do not modify RO Table 6.178 XENPAK Customer - Reserved 0x7E 12: Address 1.8089 Note 6.6.175 XENPAK Customer - Reserved 0x7E 13: Address 1.808A Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x8A [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.179 XENPAK Customer - Reserved 0x7E 13: Address 1.808A 6.6.176 XENPAK Customer - Reserved 0x7E 14: Address 1.808B Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x8B [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.180 XENPAK Customer - Reserved 0x7E 14: Address 1.808B 6.6.177 XENPAK Customer - Reserved 0x7E 15: Address 1.808C Bit Name F:8 Reserved 7:0 Customer Reserved 0x8C [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.181 XENPAK Customer - Reserved 0x7E 15: Address 1.808C 163 6.6.178 XENPAK Customer - Reserved 0x7E 16: Address 1.808D Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x8D [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.182 XENPAK Customer - Reserved 0x7E 16: Address 1.808D 6.6.179 XENPAK Customer - Reserved 0x7E 17: Address 1.808E Bit Name F:8 Reserved 7:0 Customer Reserved 0x8E [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.183 XENPAK Customer - Reserved 0x7E 17: Address 1.808E 6.6.180 XENPAK Customer - Reserved 0x7E 18: Address 1.808F Bit Name F:8 Reserved 7:0 Customer Reserved 0x8F [7:0] Description Type Default Internal reserved - do not modify RO Table 6.184 XENPAK Customer - Reserved 0x7E 18: Address 1.808F Note 6.6.181 XENPAK Customer - Reserved 0x7E 19: Address 1.8090 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x90 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.185 XENPAK Customer - Reserved 0x7E 19: Address 1.8090 6.6.182 XENPAK Customer - Reserved 0x7E 20: Address 1.8091 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x91 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.186 XENPAK Customer - Reserved 0x7E 20: Address 1.8091 6.6.183 XENPAK Customer - Reserved 0x7E 21: Address 1.8092 Bit Name F:8 Reserved 7:0 Customer Reserved 0x92 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.187 XENPAK Customer - Reserved 0x7E 21: Address 1.8092 165 6.6.184 XENPAK Customer - Reserved 0x7E 22: Address 1.8093 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x93 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.188 XENPAK Customer - Reserved 0x7E 22: Address 1.8093 6.6.185 XENPAK Customer - Reserved 0x7E 23: Address 1.8094 Bit Name F:8 Reserved 7:0 Customer Reserved 0x94 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.189 XENPAK Customer - Reserved 0x7E 23: Address 1.8094 6.6.186 XENPAK Customer - Reserved 0x7E 24: Address 1.8095 Bit Name F:8 Reserved 7:0 Customer Reserved 0x95 [7:0] Description Type Default Internal reserved - do not modify RO Table 6.190 XENPAK Customer - Reserved 0x7E 24: Address 1.8095 Note 6.6.187 XENPAK Customer - Reserved 0x7E 25: Address 1.8096 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x96 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.191 XENPAK Customer - Reserved 0x7E 25: Address 1.8096 6.6.188 XENPAK Customer - Reserved 0x7E 26: Address 1.8097 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x97 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.192 XENPAK Customer - Reserved 0x7E 26: Address 1.8097 6.6.189 XENPAK Customer - Reserved 0x7E 27: Address 1.8098 Bit Name F:8 Reserved 7:0 Customer Reserved 0x98 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.193 XENPAK Customer - Reserved 0x7E 27: Address 1.8098 167 6.6.190 XENPAK Customer - Reserved 0x7E 28: Address 1.8099 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x99 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.194 XENPAK Customer - Reserved 0x7E 28: Address 1.8099 6.6.191 XENPAK Customer - Reserved 0x7E 29: Address 1.809A Bit Name F:8 Reserved 7:0 Customer Reserved 0x9A [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.195 XENPAK Customer - Reserved 0x7E 29: Address 1.809A 6.6.192 XENPAK Customer - Reserved 0x7E 30: Address 1.809B Bit Name F:8 Reserved 7:0 Customer Reserved 0x9B [7:0] Description Type Default Internal reserved - do not modify RO Table 6.196 XENPAK Customer - Reserved 0x7E 30: Address 1.809B Note 6.6.193 XENPAK Customer - Reserved 0x7E 31: Address 1.809C Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0x9C [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.197 XENPAK Customer - Reserved 0x7E 31: Address 1.809C 6.6.194 XENPAK Customer - Reserved 0x7E 32: Address 1.809D Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0x9D [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.198 XENPAK Customer - Reserved 0x7E 32: Address 1.809D 6.6.195 XENPAK Customer - Reserved 0x7E 33: Address 1.809E Bit Name F:8 Reserved 7:0 Customer Reserved 0x9E [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.199 XENPAK Customer - Reserved 0x7E 33: Address 1.809E 169 6.6.196 XENPAK Customer - Reserved 0x7E 34: Address 1.809F Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0x9F [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.200 XENPAK Customer - Reserved 0x7E 34: Address 1.809F 6.6.197 XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 Bit Name F:8 Reserved 7:0 Customer Reserved 0xA0 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.201 XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 6.6.198 XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 Bit Name F:8 Reserved 7:0 Customer Reserved 0xA1 [7:0] Description Type Default Internal reserved - do not modify RO Table 6.202 XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 Note 6.6.199 XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0xA2 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.203 XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 6.6.200 XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0xA3 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.204 XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 6.6.201 XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 Bit Name F:8 Reserved 7:0 Customer Reserved 0xA4 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.205 XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 171 6.6.202 XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0xA5 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.206 XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 6.6.203 XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 Bit Name F:8 Reserved 7:0 Customer Reserved 0xA6 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.207 XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 6.6.204 XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 Bit Name F:8 Reserved 7:0 Customer Reserved 0xA7 [7:0] Description Type Default Internal reserved - do not modify RO Table 6.208 XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 Note 6.6.205 XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 Bit Name Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Customer Reserved 0xA8 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.209 XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 6.6.206 XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 Bit Name Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Customer Reserved 0xA9 [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.210 XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 6.6.207 XENPAK Customer - Reserved 0x7E 45: Address 1.80AA Bit Name F:8 Reserved 7:0 Customer Reserved 0xAA [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.211 XENPAK Customer - Reserved 0x7E 45: Address 1.80AA 173 6.6.208 XENPAK Customer - Reserved 0x7E 46: Address 1.80AB Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 Customer Reserved 0xAB [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.212 XENPAK Customer - Reserved 0x7E 46: Address 1.80AB 6.6.209 XENPAK Customer - Reserved 0x7E 47: Address 1.80AC Bit Name F:8 Reserved 7:0 Customer Reserved 0xAC [7:0] Description Type Default Note Internal reserved - do not modify RO Table 6.213 XENPAK Customer - Reserved 0x7E 47: Address 1.80AC 6.6.210 XENPAK Customer - Reserved 0x7E 48: Address 1.80AD Bit Name F:8 Reserved 7:0 Customer Reserved 0xAD [7:0] Description Type Default Internal reserved - do not modify RO Table 6.214 XENPAK Customer - Reserved 0x7E 48: Address 1.80AD Note 6.6.211 XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xAE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.215 XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE 6.6.212 XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xAF [7:0] Type Default Note Internal reserved - do not modify RO Table 6.216 XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF 6.6.213 XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xBO [7:0] Type Default Note Internal reserved - do not modify RO Table 6.217 XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 175 6.6.214 XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB1 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.218 XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 6.6.215 XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB2 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.219 XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 6.6.216 XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB3 [7:0] Type Default Internal reserved - do not modify RO Table 6.220 XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 Note 6.6.217 XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xB4 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.221 XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 6.6.218 XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xB5 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.222 XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 6.6.219 XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB6 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.223 XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 177 6.6.220 XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB7 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.224 XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 6.6.221 XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB8 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.225 XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 6.6.222 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xB9 [7:0] Type Default Internal reserved - do not modify RO Table 6.226 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 Note 6.6.223 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xBA [7:0] Type Default Note Internal reserved - do not modify RO Table 6.227 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA 6.6.224 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xBB [7:0] Type Default Note Internal reserved - do not modify RO Table 6.228 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB 6.6.225 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xBC [7:0] Type Default Note Internal reserved - do not modify RO Table 6.229 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC 179 6.6.226 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xBD [7:0] Type Default Note Internal reserved - do not modify RO Table 6.230 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD 6.6.227 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xBE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.231 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE 6.6.228 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xBF [7:0] Type Default Internal reserved - do not modify RO Table 6.232 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF Note 6.6.229 XENPAK Vendor - Reserved 0xAE 19: Address 1.80C0 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xC0 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.233 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD 6.6.230 XENPAK Vendor - Reserved 0xAE 20: Address 1.80C1 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xC1 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.234 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE 6.6.231 XENPAK Vendor - Reserved 0xAE 21: Address 1.80C2 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC2 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.235 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF 181 6.6.232 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC3 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.236 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 6.6.233 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC4 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.237 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 6.6.234 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC5 [7:0] Type Default Internal reserved - do not modify RO Table 6.238 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 Note 6.6.235 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xC6 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.239 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 6.6.236 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xC7 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.240 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 6.6.237 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC8 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.241 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 183 6.6.238 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xC9 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.242 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 6.6.239 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xCA [7:0] Type Default Note Internal reserved - do not modify RO Table 6.243 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA 6.6.240 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xCB [7:0] Type Default Internal reserved - do not modify RO Table 6.244 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB Note 6.6.241 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xCC [7:0] Type Default Note Internal reserved - do not modify RO Table 6.245 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC 6.6.242 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xCD [7:0] Type Default Note Internal reserved - do not modify RO Table 6.246 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD 6.6.243 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xCE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.247 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE 185 6.6.244 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xCF [7:0] Type Default Note Internal reserved - do not modify RO Table 6.248 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF 6.6.245 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD0 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.249 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 6.6.246 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD1 [7:0] Type Default Internal reserved - do not modify RO Table 6.250 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 Note 6.6.247 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xD2 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.251 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 6.6.248 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xD3 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.252 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 6.6.249 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD4 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.253 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 187 6.6.250 XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD5 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.254 XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 6.6.251 XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD6 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.255 XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 6.6.252 XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xD7 [7:0] Type Default Internal reserved - do not modify RO Table 6.256 XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 Note 6.6.253 XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xD8 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.257 XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 6.6.254 XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xD9 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.258 XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 6.6.255 XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xDA [7:0] Type Default Note Internal reserved - do not modify RO Table 6.259 XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA 189 6.6.256 XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xDB [7:0] Type Default Note Internal reserved - do not modify RO Table 6.260 XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB 6.6.257 XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xDC [7:0] Type Default Note Internal reserved - do not modify RO Table 6.261 XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC 6.6.258 XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xDD [7:0] Type Default Internal reserved - do not modify RO Table 6.262 XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD Note 6.6.259 XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xDE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.263 XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE 6.6.260 XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xDF [7:0] Type Default Note Internal reserved - do not modify RO Table 6.264 XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF 6.6.261 XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE0 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.265 XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 191 6.6.262 XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE1 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.266 XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 6.6.263 XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE2 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.267 XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 6.6.264 XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE3 [7:0] Type Default Internal reserved - do not modify RO Table 6.268 XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 Note 6.6.265 XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xE4 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.269 XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 6.6.266 XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xE5 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.270 XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 6.6.267 XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE6 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.271 XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 193 6.6.268 XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE7 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.272 XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 6.6.269 XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE8 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.273 XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 6.6.270 XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xE9 [7:0] Type Default Internal reserved - do not modify RO Table 6.274 XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 Note 6.6.271 XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xEA [7:0] Type Default Note Internal reserved - do not modify RO Table 6.275 XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA 6.6.272 XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xEB [7:0] Type Default Note Internal reserved - do not modify RO Table 6.276 XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB 6.6.273 XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xEC [7:0] Type Default Note Internal reserved - do not modify RO Table 6.277 XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC 195 6.6.274 XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xED [7:0] Type Default Note Internal reserved - do not modify RO Table 6.278 XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED 6.6.275 XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xEE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.279 XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE 6.6.276 XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xEF [7:0] Type Default Internal reserved - do not modify RO Table 6.280 XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF Note 6.6.277 XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xF0 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.281 XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 6.6.278 XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xF1 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.282 XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 6.6.279 XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF2 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.283 XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 197 6.6.280 XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF3 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.284 XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 6.6.281 XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF4 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.285 XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 6.6.282 XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF5 [7:0] Type Default Internal reserved - do not modify RO Table 6.286 XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 Note 6.6.283 XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xF6 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.287 XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 6.6.284 XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xF7 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.288 XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 6.6.285 XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF8 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.289 XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 199 6.6.286 XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xF9 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.290 XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 6.6.287 XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xFA [7:0] Type Default Note Internal reserved - do not modify RO Table 6.291 XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA 6.6.288 XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xFB [7:0] Type Default Internal reserved - do not modify RO Table 6.292 XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB Note 6.6.289 XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0xFC [7:0] Type Default Note Internal reserved - do not modify RO Table 6.293 XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC 6.6.290 XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0xFD [7:0] Type Default Note Internal reserved - do not modify RO Table 6.294 XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD 6.6.291 XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xFE [7:0] Type Default Note Internal reserved - do not modify RO Table 6.295 XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE 201 6.6.292 XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0xFF [7:0] Type Default Note Internal reserved - do not modify RO Table 6.296 XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF 6.6.293 XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0x100 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.297 XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 6.6.294 XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0x101 [7:0] Type Default Internal reserved - do not modify RO Table 6.298 XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 Note 6.6.295 XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved 7:0 Vendor Reserved 0x102 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.299 XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 6.6.296 XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 Bit Name Description Revision 0.11 - January 5, 2015 - January 5, 2015 F:8 Reserved 7:0 Vendor Reserved 0x103 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.300 XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 6.6.297 XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0x104 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.301 XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 203 6.6.298 XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0x105 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.302 XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 6.6.299 XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 Bit Name Description F:8 Reserved 7:0 Vendor Reserved 0x106 [7:0] Type Default Note Internal reserved - do not modify RO Table 6.303 XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 6.6.300 XENPAK Rx_Alarm - Control: Address 1.9000 Bit F:6 Name Description Type Default Reserved Internal reserved - do not modify 5 Reserved 1 Reserved for future use R/W PD 0 4 PMA Receive Fault Enable Setting this bit high enables generation of interrupts on PMA Receive Fault R/W PD 1 Note This bit is mirrored to 1E.C473.2 Note F/W performs mirror. Completion of this operation can be monitored via 1E.C831.F Table 6.304 XENPAK Rx_Alarm - Control: Address 1.9000 Bit 3 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 2:1 0 Name PCS Receive Fault Enable Description Setting this bit high enables generation of interrupts on PCS Receive Fault Reserved Internal reserved - do not modify PHY XS Receive Fault Enable Setting this bit high enables generation of interrupts on PHY XS Receive Fault Type Default R/W PD 1 Note This bit is mirrored to 1E.C473.1 Note F/W performs mirror. Completion of this operation can be monitored via 1E.C831.F R/W PD 1 This bit is mirrored to 1E.C473.0 Note F/W performs mirror. Completion of this operation can be monitored via 1E.C831.F Table 6.304 XENPAK Rx_Alarm - Control: Address 1.9000 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.301 XENPAK Tx_Alarm - Control: Address 1.9001 Bit F:9 Name Description Type Default R/W PD 0 R/W PD 0 Internal reserved - do not modify 8 Temperature Fault Enable Setting this bit high enables generation of interrupts on Temperature Fault 7 Reserved Internal reserved - do not modify 6 Reserved 1 Reserved for future use 5 Reserved Internal reserved - do not modify 4 PMA Transmit Fault Enable Setting this bit high enables generation of interrupts on PMA Transmit Fault R/W PD 1 3 PCS Transmit Fault Enable Setting this bit high enables generation of interrupts on PCS Transmit Fault R/W PD 1 Setting this bit enables the generation of interrupt for the temperature high and low alarms (1.A070.7:6). The generation of interrupt for the temperature high and low warnings is not supported. Table 6.305 XENPAK Tx_Alarm - Control: Address 1.9001 205 Reserved Note Bit 2:1 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential 0 Name Description Reserved Internal reserved - do not modify PHY XS Transmit Fault Enable Setting this bit high enables generation of interrupts on PHY XS Transmit Fault Type Default R/W PD 1 Note Table 6.305 XENPAK Tx_Alarm - Control: Address 1.9001 6.6.302 XENPAK LASI - Control: Address 1.9002 Bit F:3 2 Name Description Reserved Internal reserved - do not modify Rx Alarm Enable Setting this bit high enables generation of interrupts on Rx Fault Type Default R/W PD 0 Note This bit is copied to 1E.C473.6 Note F/W performs the copy. Completion of this operation can be monitored via 1E.C831.F 1 Tx Alarm Enable Setting this bit high enables generation of interrupts on Tx Fault R/W PD 0 This bit is copied to 1E.C473.5 Note F/W performs the copy. Completion of this operation can be monitored via 1E.C831.F 0 Link Status Alarm Enable Setting this bit high enables generation of interrupts on Link Status Change R/W PD 0 This enables the generation of interrupts on link status change. Specifically if the AND of 1.A.0, 3.20.0, and 4.18.C changes, an alarm is generated. This bit is copied to 1E.C473.4 Note F/W performs copy. Completion of this operation can be monitored via 1E.C831.F Table 6.306 XENPAK LASI - Control: Address 1.9002 6.6.303 XENPAK Rx_Alarm - Status: Address 1.9003 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:6 Name Description Type Reserved Internal reserved - do not modify 5 Reserved 1 Reserved for future use LH 4 PMA Receive Fault 1 = PMA Receive Fault LH Default Note This bit is automatically set by H/W if bit 1.8.A is set. This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. 3 PCS Receive Fault 1 = PCS Receive Fault LH This bit is automatically set by H/W if bit 3.8.A is set. Revision 0.11 - January 5, 2015 - January 5, 2015 This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. 2:1 0 Reserved Internal reserved - do not modify PHY XS Receive Fault 1 = PHY XS Receive Fault LH This bit is automatically set by H/W if bit 4.8.A is set. This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. Table 6.307 XENPAK Rx_Alarm - Status: Address 1.9003 207 6.6.304 XENPAK Tx_Alarm - Status: Address 1.9004 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:9 8 Name Description Reserved Internal reserved - do not modify Temperature Fault 1 = Temperature Fault Type LH Default Note This bit is set if either a high or low temperature alarm (1.A070.7:6) is set and the corresponding temperature interrupt enable (1.900.7:6) is set. This bit reverts to RO behavior if bit 1E.C441.1 is set. 7 Reserved Internal reserved - do not modify 6 Reserved 1 Reserved for future use 5 Reserved Internal reserved - do not modify 4 PMA Transmit Fault 1 = PMA Transmit Fault LH LH This bit is automatically set by H/W if bit 1.8.B is set. This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. 3 PCS Transmit Fault 1 = PCS Transmit Fault LH This bit is automatically set by H/W if bit 3.8.B is set. This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. Table 6.308 XENPAK Tx_Alarm - Status: Address 1.9004 Bit 2:1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 0 Name Description Reserved Internal reserved - do not modify PHY XS Transmit Fault 1 = PHY XS Transmit Fault Type Default LH Note This bit is automatically set by H/W if bit 4.8.B is set. This bit is automatically mirrored by H/W to 1.8.B, i.e. if 1.8.B is cleared, this bit will be automatically cleared and vice versa. Table 6.308 XENPAK Tx_Alarm - Status: Address 1.9004 6.6.305 XENPAK LASI - Status: Address 1.9005 Bit Name Description Type Default Note Revision 0.11 - January 5, 2015 - January 5, 2015 F:3 Reserved Internal reserved - do not modify 2 Rx Alarm 1 = Rx Fault RO This bit is automatically set by H/W if any of the Rx fault bits (1.9003.0, 1.9003.3, or 1.9003.4) are set and mask is enabled. 1 Tx Alarm 1 = Tx Fault RO This bit is automatically set by H/W if any of the Tx fault bits (1.9004.0, 1.9004.3, or 1.9004.4) are set and mask is enabled. 0 Link Status Alarm 1 = Link Status Change LRF This bit is automatically set by H/W if the AND of 1.A.0, 3.20.0, and 4.18.C has changed state (i.e. this bit is set if a rising or falling edge is detected on the AND). Table 6.309 XENPAK LASI - Status: Address 1.9005 209 6.6.306 XENPAK DOM - Tx Control: Address 1.9006 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:8 Name Description Type Default Note Reserved Internal reserved - do not modify 7 High Temperature Alarm Enable Setting this bit high enables generation of alarms on the temperature exceeding the high temperature threshold. R/W PD 0 This enables the generation of interrupt for the high temperature alarm. The generation for high temperature warning is not supported. 6 Low Temperature Alarm Enable Setting this bit high enables generation of alarms on the temperature exceeding the low temperature threshold. R/W PD 0 This enables the generation of interrupt for the low temperature alarm. The generation for low temperature warning is not supported. Reserved Internal reserved - do not modify 5:0 Table 6.310 XENPAK DOM - Tx Control: Address 1.9006 6.6.307 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 High Temp Threshold [7:0] [7:0] of high temperature Type Default R/W PD 0x00 Note In XENPAK mode, F/W will use 1.A000 and 1.A001 registers instead of 1E.C421. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD8. Default is 70C. Table 6.311 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 6.6.308 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 High Temp Threshold [F:8] [F:8] of high temperature Type Default R/W PD 0x46 Note In XENPAK mode, F/W will use 1.A000 and 1.A001 registers instead of 1E.C421. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD8. Default is 70C. Table 6.312 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 6.6.309 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Low Temp Threshold [7:0] [7:0] of low temperature Type Default R/W PD 0x00 Note In XENPAK mode, F/W will use 1.A002 and 1.A003 registers instead of 1E.C422. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 0C. Table 6.313 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002 211 6.6.310 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Low Temp Threshold [F:8] [F:8] of low temperature Type Default R/W PD 0x00 Note In XENPAK mode, F/W will use 1.A002 and 1.A003 registers instead of 1E.C422. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 0C. Table 6.314 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 6.6.311 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 High Temp Warning Threshold [7:0] [7:0] of high temperature Type Default R/W PD 0x00 Note In XENPAK mode, F/W will use 1.A004 and 1.A005 registers instead of 1E.C423. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 60C. Table 6.315 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 6.6.312 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 High Temp Warning Threshold [F:8] [F:8] of high temperature Type Default R/W PD 0x3C Note In XENPAK mode, F/W will use 1.A004 and 1.A005 registers instead of 1E.C423. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 60C. Table 6.316 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 6.6.313 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Low Temp Warning Threshold [7:0] [7:0] of low temperature Type Default R/W PD 0x00 Note In XENPAK mode, F/W will use 1.A006 and 1.A007 registers instead of 1E.C424. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 10C. Table 6.317 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006 213 6.6.314 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Low Temp Warning Threshold [F:8] [F:8] of low temperature Type Default R/W PD 0x0A Note In XENPAK mode, F/W will use 1.A006 and 1.A007 registers instead of 1E.C424. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 10C. Table 6.318 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 6.6.315 XENPAK DOM - Temperature LSW: Address 1.A060 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 Temperature [7:0] [7:0] of temperature Type RO Default Note 1.A060 and 1.A061 combine to form the 16-bit temperature. This register is connected to and driven by the register 1E.C820. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Table 6.319 XENPAK DOM - Temperature LSW: Address 1.A060 6.6.316 XENPAK DOM - Temperature MSW: Address 1.A061 Bit Name Description Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:8 Reserved Internal reserved - do not modify 7:0 Temperature [F:8] [F:8] of temperature Type Default RO Note 1.A060 and 1.A061 combine to form the 16-bit temperature. This register is connected to and driven by the output of 1E.C820. 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Table 6.320 XENPAK DOM - Temperature MSW: Address 1.A061 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.317 XENPAK DOM - Status: Address 1.A06E Bit F:1 0 Name Description Reserved Internal reserved - do not modify Temperature Ready 1 = temperature measurement is valid Type Default RO Note This register is connected to and driven by the register 1E.C821. Table 6.321 XENPAK DOM - Status: Address 1.A06E 6.6.318 XENPAK DOM - Capability: Address 1.A06F Bit F:8 7 Description Reserved Internal reserved - do not modify Temperature Capability 1 = device supports temperature measurement capability Reserved Internal reserved - do not modify Type Default ROS 1 Table 6.322 XENPAK DOM - Capability: Address 1.A06F Note 215 6:0 Name 6.6.319 XENPAK DOM - Alarms 1: Address 1.A070 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:8 7 Name Description Reserved Internal reserved - do not modify High Temperature Alarm 1 = High temperature alarm Type Default LH Note This register is set when the temperature in register (1.A060 and 1.A061) is greater than the high temperature alarm threshold (1.A000 and 1.A001). Note this bit is set by F/W. 6 Low Temperature Alarm 1 = Low temperature alarm LH This register is set when the temperature in register (1.A060 and 1.A061) is less than the high temperature alarm threshold (1.A002 and 1.A003). Note this bit is set by F/W. 5:0 Reserved Internal reserved - do not modify Table 6.323 XENPAK DOM - Alarms 1: Address 1.A070 6.6.320 XENPAK DOM - Alarms 2: Address 1.A071 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.324 XENPAK DOM - Alarms 2: Address 1.A071 Note 6.6.321 XENPAK DOM - Alarms 3: Address 1.A072 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.325 XENPAK DOM - Alarms 3: Address 1.A072 6.6.322 XENPAK DOM - Alarms 4: Address 1.A073 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.326 XENPAK DOM - Alarms 4: Address 1.A073 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.323 XENPAK DOM - Alarms 5: Address 1.A074 Bit F:8 7 Name Description Reserved Internal reserved - do not modify High Temperature Warning 1 = High temperature warning Type LH Default Note This register is set when the temperature in register (1.A060 and 1.A061) is greater than the high temperature alarm threshold (1.A003 and 1.A005). Note this bit is set by F/W. 6 Low Temperature Warning 1 = Low temperature warning LH This register is set when the temperature in register (1.A060 and 1.A061) is less than the high temperature alarm threshold (1.A006 and 1.A007). Note this bit is set by F/W. Reserved Internal reserved - do not modify Table 6.327 XENPAK DOM - Alarms 5: Address 1.A074 217 5:0 6.6.324 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description Type F:4 Reserved Internal reserved - do not modify 3:2 Reserved 1 [1:0] Reserved for future use RO 1:0 Reserved 2 [1:0] Reserved for future use RO Default Note These registers are not implemented as mirroring is done on a steady basis, regardless. Table 6.328 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 6.6.325 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412 Bit Name F:4 Reserved Spare Transmit Provisioning 0 [B:0] 3:0 Tx Polarity Invert Enable [3:0] Description Type Default Reserved for future use R/W PD 0x000 1 = Invert corresponding Tx lane R/W 0x0 Note Bit 0 corresponds to Lane A, Bit 1 to Lane B, etc. Table 6.329 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412 6.6.326 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413 Bit Name Description Type Default Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:C Channel Mask[3:0] Channel mask specifying which channels will be affected by the TX PSD target. R/W PD 0x000 B:8 Reserved Spare Transmit Provisioning 1 [3:0] Reserved for future use R/W PD 0x000 7:0 Incremental Tx PSD Target [7:0] Deviation from the current TX PSD target based on registers A.A and A.B in 2's complement form s7. R/W PD 0x00 Note Revision 0.11 - January 5, 2015 - January 5, 2015 Table 6.330 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413 6.6.327 PMA Transmit Vendor Alarms 1: Address 1.CC00 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.331 PMA Transmit Vendor Alarms 1: Address 1.CC00 6.6.328 PMA Transmit Vendor Alarms 2: Address 1.CC01 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.332 PMA Transmit Vendor Alarms 2: Address 1.CC01 219 6.6.329 PMA Transmit Vendor Alarms 3: Address 1.CC02 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F:2 Name Description Type Reserved PMA Transmit Alarms 3 [D:0] Reserved for internal use LH 1 Zero Defined as 0 ROS 0 Reset Complete 1 = Hardware and Firmware reset has completed LH Default 0 Note Used to provide a guaranteed zero location in the same register as Reset Complete This bit is a mirror of 1E.CC00.6, but has associated with it a known zero bit that can be used to ascertain that HW reset has completed, enabling Reset Complete to be read in one shot without double polling and dealing with tristate MDIO issues. It avoids of problem of not knowing if / when the HW complete phase of a reset has occurred when double-polling Table 6.333 PMA Transmit Vendor Alarms 3: Address 1.CC02 6.6.330 PMA Transmit Standard Interrupt Mask 1: Address 1.D000 Bit F:3 2 1:0 Name Description Reserved Internal reserved - do not modify PMA Receive Link Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify Type Default R/W PD 0 Note Mask for Bit 1.1.2. Table 6.334 PMA Transmit Standard Interrupt Mask 1: Address 1.D000 6.6.331 PMA Transmit Standard Interrupt Mask 2: Address 1.D001 Bit Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential F:C Name Description Type Default Note Reserved Internal reserved - do not modify B Transmit Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 1.8.B A Receive Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 1.8.A Reserved Internal reserved - do not modify 9:0 Table 6.335 PMA Transmit Standard Interrupt Mask 2: Address 1.D001 6.6.332 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400 Revision 0.11 - January 5, 2015 - January 5, 2015 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.336 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400 6.6.333 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.337 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401 6.6.334 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402 Bit Reserved Description Type Default Internal reserved - do not modify Table 6.338 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402 Note 221 F:0 Name 6.6.335 PMA Transmit Vendor Debug 1: Address 1.D800 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit F E:0 Name Description Type Default PMA Digital System Loopback 1 = Enable PMA digital system loopback R/W PD 0 Reserved Internal reserved - do not modify Note Table 6.339 PMA Transmit Vendor Debug 1: Address 1.D800 6.6.336 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 Bit F Name External PHY Loopback Description 1 = Enable external PHY loopback 0 = Normal operation Type Default R/W PD 0 Note External PHY loopback expects a loopback connector such that Pair A is connected to Pair B, and Pair C is connected to Pair D. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F E:3 2 Reserved Receive Provisioning 1 [B:0] Reserved for future use R/W PD 0x000 Enable Aquantia Fast Retrain 1 = Enable PMA Fast Link Retrain 0 = Disable PMA Fast Link Retrain R/W PD 0 If the link partner is an Aquantia PHY and also has Fast Retrain enabled use a special retrain sequence to bring the link back up without going back through the Autonegotiation sequence. Table 6.340 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 1 Force MDI Configuration 1 = Ignore state of MDI_CFG pin 0 = Set MDI Configuration based on state of MDI_CFG R/W PD 0 MDI_CFG pin is not brought out. Set this bit to 1 and use the MDI Configuration bit to control the MDI pairs' arrangement. 0 MDI Configuration 1 = MDI Reversed (ABCD -> DCBA) 0 = MDI Normal (ABCD -> ABCD) R/W PD 0 The setting of this bit determines whether the MDI is reversed or not. Note that the reversal does not change pair polarity - i.e. A+ maps to D+, etc. The value of this bit is sampled during autonegotiation. If this bit is changed manually after autonegotiation completes, autonegotiation must be restarted to achieve the desired MDI configuration. Table 6.340 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 Revision 0.11 - January 5, 2015 - January 5, 2015 6.6.337 PMA Receive Vendor State 1: Address 1.E800 Bit F:1 0 Name Description Reserved Internal reserved - do not modify PMA Receive Link Current Status 1 = Rx link good Type Default RO Note This is the current state of 1.1.2 Table 6.341 PMA Receive Vendor State 1: Address 1.E800 6.6.338 PMA Receive Reserved Vendor State 1: Address 1.E810 Bit F:0 Name Accumulated Fast Retrain Time[F:0] Description Accumulated time in milliseconds spent in fast retrain since the last auto-negotiation sequence Type RO Default Note This is a saturating register. 223 Table 6.342 PMA Receive Reserved Vendor State 1: Address 1.E810 6.6.339 PMA Receive Reserved Vendor State 2: Address 1.E811 Revision 0.11 - January 5, 2015 - Janu- Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:8 Total Number Of Link Recovery Events Since Last AutoNeg [7:0] The count of the cumulative number of Link Recovery Events since last autonegotiation RO This register is automatically reset to 0 during Auto-negotiation. It increments once for each series of back-to-back Fast Retrain events. The result is reported modulo 256 (wrap around). 7:0 Total Number Of RFI Training Link Recovery Events Since Last AutoNeg [7:0] The count of the cumulative number of RFI Training Link Recovery Events since last autonegotiation RO This register is automatically reset to 0 during Auto-negotiation. The result is reported modulo 256 (wrap around). Table 6.343 PMA Receive Reserved Vendor State 2: Address 1.E811 6.6.340 PMA Vendor Global Interrupt Flags 1: Address 1.FC00 Bit Name Description Type Default Note F Vendor Specific Tx Alarms 1 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "PMA Transmit Vendor Alarms 1: Address 1.CC00" on page 129.) and the corresponding mask register (See "PMA Transmit Vendor Interrupt Mask 1: Address 1.D400" on page 132.) E Vendor Specific Tx Alarms 2 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "PMA Transmit Vendor Alarms 2: Address 1.CC01" on page 129.) and the corresponding mask register (See "PMA Transmit Vendor Interrupt Mask 2: Address 1.D401" on page 132.) Table 6.344 PMA Vendor Global Interrupt Flags 1: Address 1.FC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - January 5, 2015 Bit Name D Vendor Specific Tx Alarms 3 Interrupt 1 = Interrupt C Reserved Internal reserved - do not modify B Standard Alarm 1 Interrupt A 9:0 Description Type Default Note RO An interrupt was generated from status register (See "PMA Transmit Vendor Alarms 3: Address 1.CC02" on page 130.) and the corresponding mask register (See "PMA Transmit Vendor Interrupt Mask 3: Address 1.D402" on page 133.) 1 = Interrupt RO An interrupt was generated from bit 1.1.2. An interrupt was generated from status register (See "PMA Standard Status 1: Address 1.1" on page 2.) and the corresponding mask register (See "PMA Transmit Standard Interrupt Mask 1: Address 1.D000" on page 131.) Standard Alarm 2 Interrupt 1 = Interrupt RO An interrupt was generated from either bit 1.8.B or 1.8.A. An interrupt was generated from status register (See "PMA Standard Status 2: Address 1.8" on page 8.) and the corresponding mask register (See "PMA Transmit Standard Interrupt Mask 2: Address 1.D001" on page 131.) Reserved Internal reserved - do not modify Table 6.344 PMA Vendor Global Interrupt Flags 1: Address 1.FC00 225 Aquantia Corp. - Strictly Confidential Revision 0.11 - January 5, 2015 - Janu- Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7 PCS Registers 6.7.1 PCS Standard Control 1: Address 3.0 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F Reset 1 = PCS reset 0 = Normal operation R/W SC 1 Resets the entire PHY. The reset bit is automatically cleared upon completion of the reset sequence by the microcontroller. This bit is set to 1 during reset. The reset is internally stretched by approximately 1.7 us. Therefore the MDIO or uP should allow for 1.7 us before writing any PCS registers after this bit is set. E Loopback 1 = Enable loopback mode 0 = Normal operation R/W PD 0 This enables the PCS DSQ System Loopback. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F D Speed Selection LSB {6,D} 1 1 = Speed set by Bits [5:2] 1 0 = 1000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s C Reserved Internal reserved - do not modify R/W PD 1 Table 6.345 PCS Standard Control 1: Address 3.0 227 Bit B Name Low Power Description AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 = Low-power mode 0 = Normal operation Type Default R/W PD 0 Note A one written to this register causes the PCS to enter low-power mode. If a global chip low-power state is desired, use Bit B in "Global Standard Control 1: Address 1E.0" should be set. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F A Clock Stop Enable 1 = The PHY may stop the clock during LPI 0 = Clock not stoppable Reserved Internal reserved - do not modify Speed Selection MSB 5:2 1:0 9:7 6 R/W PD 0 {6,D} 1 1 = Speed set by Bits [5:2] 1 0 = 1000 Mb/s 0 1 = 100 Mb/s 0 0 = 10 Mb/s R/W PD 1 10G Speed Selection [3:0] 1 x x x = Reserved x 1 x x = Reserved x x 1 x = Reserved x x x 1 = 10PASS-TS / 2BASE-TL 0 0 0 0 = 10 Gb/s R/W PD 0x0 Reserved Internal reserved - do not modify Table 6.345 PCS Standard Control 1: Address 3.0 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.2 PCS Standard Status 1: Address 3.1 Bit F:C Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify B Tx LPI Received 1 = Tx PCS has received LPI 0 = LPI not received LH The source of the LPI signal is configured in 1E.C4A1.3:0. A Rx LPI Received 1 = Rx PCS has received LPI 0 = LPI not received LH The source of the LPI signal is configured in 1E.C4A1.3:0. 9 Tx LPI Indication 1 = Tx PCS is currently receiving LPI 0 = Tx PCS is not currently receiving LPI RO The source of the LPI signal is configured in 1E.C4A1.3:0. 8 Rx LPI Indication 1 = Rx PCS is currently receiving LPI 0 = Rx PCS is not currently receiving LPI RO The source of the LPI signal is configured in 1E.C4A1.3:0. 7 Fault 1 = Fault condition detected 0 = No fault detected RO This is the top-level fault indicator flag for the PCS block, This bit is set if either of the two bits 3.8.B or 3.8.A are set. 6 Clock Stop Capable 1 = The MAC may stop the clock during LPI 0 = Clock not stoppable ROS 5:3 Reserved Internal reserved - do not modify 2 PCS Receive Link Status Status of the PCS receive link 1 = Link up 0 = Link lost since last read LL 1 Low Power Ability 1 = PCS supports low-power mode 0 = no low-power mode supported ROS 0 Reserved Internal reserved - do not modify 0 This indicates the status of the PCS receive link. This is a latching low version of Bit 3.20.C. 1 Table 6.346 PCS Standard Status 1: Address 3.1 229 Indicates whether the XAUI interface supports a low-power mode 6.7.3 PCS Standard Device Identifier 1: Address 3.2 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default Note RO Table 6.347 PCS Standard Device Identifier 1: Address 3.2 6.7.4 PCS Standard Device Identifier 2: Address 3.3 Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.348 PCS Standard Device Identifier 2: Address 3.3 6.7.5 PCS Standard Speed Ability: Address 3.4 Bit F:2 Name Description Type Default Note Reserved Internal reserved - do not modify 1 10PASS-TS / 2BASE-TL Capable 1 = PCS is 10PASS-TS / 2BASE-TL capable 0 = PCS is not 10PASS-TS / 2BASE-TL capable ROS 0 This is always set to 0 in the AQR405. 0 10G Capable 1 = PCS is 10 Gb/s capable 0 = PCS is not 10 Gb/s capable ROS 1 This is always set to 1 in the AQR405. Table 6.349 PCS Standard Speed Ability: Address 3.4 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.6 PCS Standard Devices in Package 1: Address 3.5 Bit F:8 Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify 7 Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package ROS 1 This is always set to 1, as there is Autonegotiation in the AQR405. 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. 5 DTE XS Present 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no DTE XAUI interface in the AQR405. 4 PHY XS Present 1 = PHY XS is present in package 0 = PHY XS is not present in package ROS 1 This is always set to 1 as there is a PHY XS interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.350 PCS Standard Devices in Package 1: Address 3.5 231 6.7.7 PCS Standard Devices in Package 2: Address 3.6 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the global control registers. D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the GbE registers. C:0 Reserved Internal reserved - do not modify Table 6.351 PCS Standard Devices in Package 2: Address 3.6 6.7.8 PCS Standard Control 2: Address 3.7 Bit Name Description F:2 Reserved Internal reserved - do not modify 1:0 PCS Device Type [1:0] [1:0] 0x3 = 10GBASE-T 0x2 = 10GBASE-W 0x1 = 10GBASE-X 0x0 = 10GBASE-R Type Default R/W PD 0x3 Note This defaults to 10GBASE-T Table 6.352 PCS Standard Control 2: Address 3.7 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.9 PCS Standard Status 2: Address 3.8 Bit Name Description Type Default ROS 0x2 Note This field is always set to 0x2, as the PCS registers reside here in the AQR405. AQR405 Revision 0.11 - January 5, 2015 Device Present [1:0] [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address D:C Reserved Internal reserved - do not modify B Transmit Fault 1 = Fault condition on transmit path 0 = No fault condition on transmit path LH This bit indicates whether there is a fault somewhere along the transmit path. This bit is duplicated at 3.CC01.0. A Receive Fault 1 = Fault condition on receive path 0 = No fault condition on receive path LH This bit indicates whether there is a fault somewhere along the receive path. This bit is duplicated at 3.EC04.2. Reserved Internal reserved - do not modify 3 10GBASE-T capable 1 = PCS supports 10GBASE-T PCS type 0 = PCS does not support 10GBASE-T ROS 1 This field is always set to 1, as the PCS in the AQR405 only supports 10GBASE-T and 10GBASE-R. 2 10GBASE-W capable 1 = PCS supports 10GBASE-W PCS type 0 = PCS does not support 10GBASE-W ROS 0 This field is always set to 0, as the PCS in the AQR405 only supports 10GBASE-T and 10GBASE-R. 1 10GBASE-X capable 1 = PCS supports 10GBASE-X PCS type 0 = PCS does not support 10GBASE-X ROS 0 This field is always set to 0, as the PCS in the AQR405 only supports 10GBASE-T and 10GBASE-R. 0 10GBASE-R capable 1 = PCS supports 10GBASE-R PCS type 0 = PCS does not support 10GBASE-R ROS 1 This field is always set to 1, as the PCS in the AQR405 only supports 10GBASE-T and 10GBASE-R. 9:4 Table 6.353 PCS Standard Status 2: Address 3.8 233 F:E 6.7.10 PCS Standard Package Identifier 1: Address 3.E AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.354 PCS Standard Package Identifier 1: Address 3.E 6.7.11 PCS Standard Package Identifier 2: Address 3.F Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default Note RO Table 6.355 PCS Standard Package Identifier 2: Address 3.F 6.7.12 PCS EEE Capability Register : Address 3.14 Bit F:7 Name Description Type Default Reserved Internal reserved - do not modify 6 10GBASE-KR EEE 1 = Advertise that the 10GBASE-KR has EEE capability 0 = Do not advertise that the 10GBASE-KR has EEE capability ROS 1 5 10GBASE-KX4 EEE 1 = Advertise that the 10GBASE-KX4 has EEE capability 0 = Do not advertise that the 10GBASE-KX4 has EEE capability ROS 1 Table 6.356 PCS EEE Capability Register : Address 3.14 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description AQR405 Revision 0.11 - January 5, 2015 Type Default 4 1000BASE-KX EEE 1 = Advertise that the 1000BASE-KX has EEE capability 0 = Do not advertise that the 1000BASE-KX has EEE capability ROS 1 3 10GBASE-T EEE 1 = Advertise that the 10GBASE-T has EEE capability 0 = Do not advertise that the 10GBASE-T has EEE capability ROS 1 2 1000BASE-T EEE 1 = Advertise that the 1000BASE-T has EEE capability 0 = Do not advertise that the 1000BASE-T has EEE capability ROS 1 1 100BASE-TX EEE 1 = Advertise that the 100BASE-TX has EEE capability 0 = Do not advertise that the 100BASE-TX has EEE capability ROS 0 0 Reserved Internal reserved - do not modify Note Table 6.356 PCS EEE Capability Register : Address 3.14 6.7.13 PCS EEE Wake Error Counter: Address 3.16 Bit Name F:0 EEE Wake Error Counter [F:0] Description EEE wake error counter Type Default Note SCT 0x0000 This register is a 16-bit saturating clear on read counter. The wake error source is configured with 1E.C4A1.A:8. The default wake error source is from the RPL. 235 Table 6.357 PCS EEE Wake Error Counter: Address 3.16 6.7.14 PCS 10G Status 1: Address 3.20 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:D Name Description Type Default Note Reserved Internal reserved - do not modify 10G Receive Link Status 1 = 10G Receive Link Up 0 = 10G Receive Link Down Reserved Internal reserved - do not modify 3 10GBASE-R PRBS9 Pattern Testing Ability 1 = PCS is able to support PRBS9 pattern testing on KR Interface 0 = PCS is not able to support PRBS9 pattern testing on KR Interface ROS 1 2 10GBASE-R PRBS31 Pattern Testing Ability 1 = PCS is able to support PRBS31 pattern testing on KR Interface 0 = PCS is not able to support PRBS31 pattern testing on KR Interface ROS 1 1 10G High BER 1 = PCS is reporting a BER 10-4 0 = PCS is reporting a BER < 10-4 RO When set, this bit indicates a high BER is being seen at the PCS. The interrupt for this bit is at 3.21.E. The status bit for medium BER is found in "Global Alarms 2: Address 1E.CC01" on page 615. 0 10G PCS Block Lock 1 = 10GBASE-T PCS Framer is locked 0 = 10GBASE-T PCS Framer is not locked RO When set, this bit indicates that 10G PCS Framer has acquired frame synchronization and is locked. The interrupt for this bit is at 3.21.F. C B:4 RO When set, this bit indicates that the 10G Receive Link is functioning properly. This is a non-latching version of bit 3.1.2. See "PCS Standard Status 1: Address 3.1" on page 229. The Receive Link is up when the Block Lock status is asserted and the High BER is deasserted.) Table 6.358 PCS EEE Wake Error Counter: Address 3.16 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.15 PCS 10G Status 2: Address 3.21 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F PCS Block Lock Latched 1 = 10GBASE-T PCS Framer is Locked 0 = 10GBASE-T PCS Framer is not locked LL When set, this bit indicates that 10G PCS Framer has acquired frame synchronization and is locked. This is the interrupt for bit 3.20.0. See "PCS EEE Wake Error Counter: Address 3.16" on page 235. E High BER Latched 1 = PCS is reporting a BER 10-4 0 = PCS is reporting a BER < 10-4 LH When set, this bit indicates a high BER is being seen at the PCS. This is the interrupt for bit 3.20.1. See "PCS EEE Wake Error Counter: Address 3.16" on page 235. D:8 Errored Frame Counter [5:0] A saturating count of the number of times a bad LDPC frame is received. SCT 0x00 Clear on read. In 10GBASE-T mode, this is taken from the state machine in Figure 55.14 in the 10GBASE-T specification. In 10GBASE-R mode, this is calculated using controls in 7:0 Errored Block Counter [7:0] A saturating count of the number of times a bad 65B block is received. SCT 0x00 Clear on read. In 10GBASE-T mode, this is taken from the state machine in Figure 55.16 in the 10GBASE-T specification. Table 6.359 PCS 10G Status 2: Address 3.21 6.7.16 PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 Bit Name F:0 Test Pattern Seed A Bits 15:0 [F:0] Description Test pattern seed A bits 15:0 Type Default R/W PD 0x0000 237 Table 6.360 PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 Note 6.7.17 PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Test Pattern Seed A Bits 31:16 [1F:10] Description Test pattern seed A bits 31:16 Type Default R/W PD 0x0000 Note Table 6.361 PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 6.7.18 PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 Bit F:0 Name Test Pattern Seed A Bits 47:32 [2F:20] Description Test pattern seed A bits 47:32 Type Default R/W PD 0x0000 Note Table 6.362 PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 6.7.19 PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 Test Pattern Seed A Bits 57:48 [39:30] Test pattern seed A bits 57:48 Type Default R/W PD 0x000 Table 6.363 PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.20 PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 Bit Name F:0 Test Pattern Seed B Bits 15:0 [F:0] Description Test pattern seed B bits 15:0 Type Default R/W PD 0x0000 Note Table 6.364 PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 6.7.21 PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 Bit AQR405 Revision 0.11 - January 5, 2015 F:0 Name Test Pattern Seed B Bits 31:16 [1F:10] Description Test pattern seed B bits 31:16 Type Default R/W PD 0x0000 Note Table 6.365 PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 6.7.22 PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 Bit F:0 Name Test Pattern Seed B Bits 47:32 [2F:20] Description Test pattern seed B bits 47:32 Type Default R/W PD 0x0000 Note Table 6.366 PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 239 6.7.23 PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 Test Pattern Seed B Bits 57:48 [39:30] Test pattern seed B bits 57:48 Type Default R/W PD 0x000 Note Table 6.367 PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 6.7.24 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A Bit F:7 Name Description Type Default Reserved Internal reserved - do not modify 6 PRBS9 Transmit Test-Pattern Enable 1 = Enable PRBS9 test-pattern mode on the transmit path 0 = Disable PRBS9 test-pattern mode on the transmit path R/W PD 0 5 PRBS31 Receive Test-Pattern Enable 1 = Enable PRBS31 test-pattern mode on the receive path 0 = Enable PRBS31 test-pattern mode on the receive path R/W PD 0 4 PRBS31 Transmit Test-Pattern Enable 1 = Enable PRBS31 test-pattern mode on the transmit path 0 = Enable PRBS31 test-pattern mode on the transmit path R/W PD 0 3 Transmit Test-Pattern Enable 1 = Enable transmit test pattern 0 = Disable transmit test pattern R/W PD 0 Table 6.368 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default 2 Receive Test-Pattern Enable 1 = Enable receive test-pattern testing 0 = Disable receive test-pattern testing R/W PD 0 1 Test-Pattern Select 1 = Square wave test pattern 0 = Pseudo random test pattern R/W PD 0 0 Data Pattern Select 1 = Zeros data pattern 0 = LF data pattern R/W PD 0 Note Table 6.368 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A AQR405 Revision 0.11 - January 5, 2015 6.7.25 PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B Bit F:0 Name Test-Pattern Error Counter [F:0] Description Error Counter Type Default R/W PD 0x0000 Note Table 6.369 PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B 6.7.26 TimeSync PCS Capability: Address 3.1800 Bit F:2 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.370 TimeSync PCS Capability: Address 3.1800 241 Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 TimeSync Transmit Path Data Delay 1 = PCS provides information on transmit path data delay in registers 3.1801 through 3.1804 0 = PCS does not provide information on transmit path data delay RO 0 TimeSync Receive Path Data Delay 1 = PCS provides information on receive path data delay in registers 3.1805 through 3.1808 0 = PCS does not provide information on receive path data delay RO Default Note Table 6.370 TimeSync PCS Capability: Address 3.1800 6.7.27 TimeSync PCS Transmit Path Data Delay 1: Address 3.1801 Bit Name Description F:0 Maximum PCS Transmit Path Data Delay LSW [F:0] LSW of maximum PCS transmit delay in nanoseconds Type Default Note RO Table 6.371 TimeSync PCS Transmit Path Data Delay 1: Address 3.1801 6.7.28 TimeSync PCS Transmit Path Data Delay 2: Address 3.1802 Bit F:0 Name Maximum PCS Transmit Path Data Delay MSW [F:0] Description MSW of maximum PCS transmit delay in nanoseconds Type Default RO Table 6.372 TimeSync PCS Transmit Path Data Delay 2: Address 3.1802 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.29 TimeSync PCS Transmit Path Data Delay 3: Address 3.1803 Bit Name Description F:0 Minimum PCS Transmit Path Data Delay LSW [F:0] LSW of minimum PCS transmit delay in nanoseconds Type Default Note RO Table 6.373 TimeSync PCS Transmit Path Data Delay 3: Address 3.1803 6.7.30 TimeSync PCS Transmit Path Data Delay 4: Address 3.1804 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Minimum PCS Transmit Path Data Delay MSW [F:0] Description MSW of minimum PCS transmit delay in nanoseconds Type Default Note RO Table 6.374 TimeSync PCS Transmit Path Data Delay 4: Address 3.1804 6.7.31 TimeSync PCS Receive Path Data Delay 1: Address 3.1805 Bit Name Description F:0 Maximum PCS Receive Path Data Delay LSW [F:0] LSW of maximum PCS receive delay in nanoseconds Type Default Note RO Table 6.375 TimeSync PCS Receive Path Data Delay 1: Address 3.1805 243 6.7.32 TimeSync PCS Receive Path Data Delay 2: Address 3.1806 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Maximum PCS Receive Path Data Delay MSW [F:0] Description MSW of maximum PCS receive delay in nanoseconds Type Default Note RO Table 6.376 TimeSync PCS Receive Path Data Delay 2: Address 3.1806 6.7.33 TimeSync PCS Receive Path Data Delay 3: Address 3.1807 Bit Name Description F:0 Minimum PCS Receive Path Data Delay LSW [F:0] LSW of minimum PCS receive delay in nanoseconds Type Default Note RO Table 6.377 TimeSync PCS Receive Path Data Delay 3: Address 3.1807 6.7.34 TimeSync PCS Receive Path Data Delay 4: Address 3.1808 Bit F:0 Name Minimum PCS Receive Path Data Delay MSW [F:0] Description MSW of minimum PCS receive delay in nanoseconds Type Default RO Table 6.378 TimeSync PCS Receive Path Data Delay 4: Address 3.1808 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.35 PCS Transmit Vendor Provisioning 1: Address 3.C400 Bit F:1 0 Name Description Reserved Internal reserved - do not modify PCS Tx Auxilliary Bit Value The value that will be set in the auxilliary bit of the PCS transmission frame Type Default R/W PD 0 Note This bit is currently undefined in the 802.3an standard. Table 6.379 PCS Transmit Vendor Provisioning 1: Address 3.C400 6.7.36 PCS Transmit Vendor Provisioning 2: Address 3.C401 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.380 PCS Transmit Vendor Provisioning 2: Address 3.C401 6.7.37 PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410 Bit F:1 0 Name Description Type Default Reserved for future use R/W PD 0x0000 PCS IEEE Loopback Passthrough Disable 1 = Disable data passthrough on IEEE loopback R/W PD 0 When set, this bit disables the output of the PHY when IEEE loopback is set. Table 6.381 PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410 245 Reserved Transmit Provisioning 1 [F:1] Note 6.7.38 PCS Transmit XFI Vendor Provisioning 1: Address 3.C455 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 XFI Test Pattern Seed A Word 0 [F:0] Description XFI test pattern seed A bits 15:0 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed A Used for both XFI0 and XFI1. Table 6.382 PCS Transmit XFI Vendor Provisioning 1: Address 3.C455 6.7.39 PCS Transmit XFI Vendor Provisioning 2: Address 3.C456 Bit Name F:0 XFI Test Pattern Seed A Word 1 [F:0] Description XFI test pattern seed A bits 31:16 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed A Used for both XFI0 and XFI1. Table 6.383 PCS Transmit XFI Vendor Provisioning 2: Address 3.C456 6.7.40 PCS Transmit XFI Vendor Provisioning 3: Address 3.C457 Bit Name F:0 XFI Test Pattern Seed A Word 2 [F:0] Description XFI test pattern seed A bits 47:32 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed A Used for both XFI0 and XFI1. Table 6.384 PCS Transmit XFI Vendor Provisioning 3: Address 3.C457 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.41 PCS Transmit XFI Vendor Provisioning 4: Address 3.C458 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI Test Pattern Seed A Word 3 [9:0] XFI test pattern seed A bits 57:48 Type Default R/W 0x000 Note 10GBASE-R Test Pattern Seed A Used for both XFI0 and XFI1. Table 6.385 PCS Transmit XFI Vendor Provisioning 4: Address 3.C458 6.7.42 PCS Transmit XFI Vendor Provisioning 5: Address 3.C459 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 XFI Test Pattern Seed B Word 0 [F:0] Description XFI test pattern seed B bits 15:0 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed B Used for both XFI0 and XFI1. Table 6.386 PCS Transmit XFI Vendor Provisioning 5: Address 3.C459 6.7.43 PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A Bit Name F:0 XFI Test Pattern Seed B Word 1 [F:0] Description XFI test pattern seed B bits 31:16 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed B Used for both XFI0 and XFI1. Table 6.387 PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A 247 6.7.44 PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 XFI Test Pattern Seed B Word 2 [F:0] Description XFI test pattern seed B bits 47:32 Type Default R/W 0x0000 Note 10GBASE-R Test Pattern Seed B Used for both XFI0 and XFI1. Table 6.388 PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B 6.7.45 PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI Test Pattern Seed B Word 3 [9:0] XFI test pattern seed B bits 57:48 Type Default R/W 0x000 Note 10GBASE-R Test Pattern Seed B Used for both XFI0 and XFI1. Table 6.389 PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C 6.7.46 PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 Bit Name Description F:2 Reserved Internal reserved - do not modify 1 XFI0 PCS Scrambler Disable 1 = Disable PCS scrambler 0 Reserved Internal reserved - do not modify Type Default R/W PD 0 Note PCS Scrambler Disable (default: 0) Table 6.390 PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.47 PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 Bit F:A Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify 9 XFI0 Test Sqaure Wave Test Duration 0 = 6 ones followed by 6 zeroes 1 = 11 ones followed by 11 zeroes R/W 0 10GBASE-R Square Wave Test Duration. Repeating pattern of n ones, followed by n zeros, where n = 6 or 11 (0:n= 6, 1:n=11, default:0) 8 XFI0 Test Data Select 1 = Data pattern select R/W 0 10GBASE-R Data 1:Zero, default:0) 7 XFI0 Test Mode Select 1 = Test pattern select R/W 0 10GBASE-R Test Pattern Select (0:Pseudo random, 1:Square wave, default:0) 6 XFI0 Test PRBS-9 Enable 1 = Test pattern PRBS-9 enabled R/W 0 10GBASE-R PRBS 9 Test Pattern Enable (0:disable, 1:enable, default:0) 5 XFI0 Test PRBS-31 Enable 1 = Test pattern PRBS-31 enabled R/W 0 10GBASE-R PRBS 31 Test Pattern Enable (0:disable, 1:enable, default:0) 4 XFI0 Test Pattern Enable 1 = Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern Enable (0:disable, 1:enable, default:0) 3 XFI0 Local Fault Inject 1 = Inject local fault R/W 0 Inject Local_Fault (default:0) 2 XFI0 Inject Single Error 1 = Inject single Error R/W 0 Inject single error on the 10GBASE-R Test Pattern including pseudo-random, PRB31 or PRBS9 (default:0) 1 XFI0 PCS High BER Inject 1 = Inject PCS High BER R/W 0 Inject error to cause HI_BER at far-end (default:0) 0 XFI0 PCS Loss Of Lock Inject 1 = Inject loss of lock R/W 0 Inject error to cause loss of block_lock at far-end (default:0) Select (0:LF, 249 Table 6.391 PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 Pattern 6.7.48 PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:2 Reserved Internal reserved - do not modify 1 XFI1 PCS Scrambler Disable 1 = Disable PCS scrambler 0 Reserved Internal reserved - do not modify Type Default R/W PD 0 Note PCS Scrambler Disable (default: 0) Table 6.392 PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 6.7.49 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 Bit F:A Name Description Type Default Note Reserved Internal reserved - do not modify 9 XFI1 Test Sqaure Wave Test Duration 0 = 6 ones followed by 6 zeroes 1 = 11 ones followed by 11 zeroes R/W 0 10GBASE-R Square Wave Test Duration. Repeating pattern of n ones, followed by n zeros, where n = 6 or 11 (0:n= 6, 1:n=11, default:0) 8 XFI1 Test Data Select 1 = Data pattern select R/W 0 10GBASE-R Data 1:Zero, default:0) 7 XFI1 Test Mode Select 1 = Test pattern select R/W 0 10GBASE-R Test Pattern Select (0:Pseudo random, 1:Square wave, default:0) Table 6.393 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 Pattern Select (0:LF, Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 6 XFI1 Test PRBS-9 Enable Description 1 = Test pattern PRBS-9 enabled Type Default R/W 0 Note 10GBASE-R PRBS 9 Test Pattern Enable (0:disable, 1:enable, default:0) NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 5 XFI1 Test PRBS-31 Enable 1 = Test pattern PRBS-31 enabled R/W 0 10GBASE-R PRBS 31 Test Pattern Enable (0:disable, 1:enable, default:0) NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F AQR405 Revision 0.11 - January 5, 2015 4 XFI1 Test Pattern Enable 1 = Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern Enable (0:disable, 1:enable, default:0) 3 XFI1 Local Fault Inject 1 = Inject local fault R/W 0 Inject Local_Fault (default:0) 2 XFI1 Inject Single Error 1 = Inject single Error R/W 0 Inject single error on the 10GBASE-R Test Pattern including pseudo-random, PRB31 or PRBS9 (default:0) 1 XFI1 PCS High BER Inject 1 = Inject PCS High BER R/W 0 Inject error to cause HI_BER at far-end (default:0) 0 XFI1 PCS Loss Of Lock Inject 1 = Inject loss of lock R/W 0 Inject error to cause loss of block_lock at far-end (default:0) Table 6.393 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 251 6.7.50 PCS USX0 Memory Control Register: Address 3.C4C0 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:7 Name Description Type Default Reserved Internal reserved - do not modify 6 USX0 Memory power down USX0 Memory power down R/W 0 5:0 USX0 Memory RM [5:0] USX0 Memory RM bits R/W 0x00 Note Table 6.394 PCS USX0 Memory Control Register: Address 3.C4C0 6.7.51 PCS USX0 Control Register 1: Address 3.C4C1 Bit Name Description Type Default Note F USX0 Clock Enable USX0 Clock Enable R/W 1 Enable clock of USX0 block E USX0 Bypass USX0 Bypass R/W 0 Bypass USX0 block. This can be set to one to bypass USX for regular XFI 10G operation to reduce latency and power. D USX0 Link FIFO Mode USX0 Link FIFO Mode R/W 0 This shall be set to one to enable frame-adaptation in USX0 for AQRate 5G/2.5G mode. C USX0 Replication Mode USX0 Replication Mode R/W 1 Set to 1 to select word-based replication. Set to 0 to select byte-based replication. Always set this to 1 (default). Reserved Internal reserved - do not modify USX0 PCS Reset USX0 PCS Reset R/W 0 PCS Reset B:8 7 Table 6.395 PCS USX0 Control Register 1: Address 3.C4C1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 6 USX0 PCS low power USX0 PCS low power R/W 0 PCS Low Power 5 USX0 Parity check sense USX0 Parity check sense (default:0) R/W 0 Always leave to 0. Set to1 to force parity error for diagnostics. 4:3 USX0 Speed mode[1:0] USX0 Speed mode (00:based on AQRate mode, 10:1G, 11:100M) R/W 0x0 Configure link speed. Set to 0 to select 10G or AQRate mode. Otherwise, set to 2 or 3 to select 1G or 100M mode. 2:1 USX0 AQRate mode[1:0] USX0 AQRate mode (00:10G, 10:5G, 11:2.5G) R/W 0x0 This register is ignored if the USX0 Speed mode is set to non-zero (1G or 100M mode). USX0 XGS RKL mode USX0 XGS RKL mode R/W 0 This shall be set to1 to enable XGS to support USX0. 0 Table 6.395 PCS USX0 Control Register 1: Address 3.C4C1 6.7.52 PCS USX0 Local fault Control Register: Address 3.C4C2 Bit F:9 8 7:0 Name Description Type Default Note Reserved Internal reserved - do not modify USX0 Inject Tx Local_Fault USX0 Inject Tx USXGMII Local_Fault (default:0) R/W 0 Toggle this bit to inject single Local_Fault towards the external MAC. USX0 Local_Fault code[7:0] USX0 USXGMII Local_Fault code (default:0x11) R/W 0x11 Configure the LSB 8-bit of the Local_Fault codeword. Table 6.396 PCS USX0 Local fault Control Register: Address 3.C4C2 253 6.7.53 PCS USX0 MAC Local fault Control Register: Address 3.C4C3 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:8 USX0 user define code[7:0] 7 6:0 Description Type Default Note USX0 User-defined code to replace USXGMII Local_Fault received (default:0x01). R/W 0x01 Configure the LSB 8-bit to replace the Rx USXGMII Local_Fault codeword if enabled. USX0 Inject Local Fault signal USX0 Inject Local Fault signal towards the MAC in 1G/100M mode (default:0) R/W 0 Set to1 to inject Local_Fault towards the external MAC in 1G/100M mode continuously with the progammable gap. USX0 Number of Idle coulmn[6:0] USX0 Number of Idle coulmn between Local Fault signals (0 to 127, default:31) R/W 0x1F Configures the number of Idle column between Local_Fault signals during injection in 1G/100M mode. Table 6.397 PCS USX0 MAC Local fault Control Register: Address 3.C4C3 6.7.54 PCS USX0 Auto-Neg Control Register: Address 3.C4C4 Bit F:A Name Description Type Default Note Reserved Internal reserved - do not modify 9 USX0 Restart Auto-Negotiatio n USX0 Restart Auto-Negotiation R/W 0 Toggle this bit to restart USXGMII Auto-Negotiation. 8 USX0 Auto-neg Enable USX0 Auto negotiation Enable R/W 0 Set to 1 to enable USXGMII Auto-Negotiation. 7:0 USX0 Auto neg Message code[7:0] USX0 USXGMII Auto-Negotiation Message Opcode. R/W 0x03 Configure the message opcode for USXGMII Auto-Negotiation. Table 6.398 PCS USX0 Auto-Neg Control Register: Address 3.C4C4 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.55 PCS USX0 PTP Control Register: Address 3.C4C5 Bit Name Description Type Default Note R/W 0x0 Bit 0: Set to 1 to insert USXGMII Local Fault when the Link FIFO is empty Bit 1: reserved Bit 2: Set to 1 to swap bit-order of CRC Bit 3: Set to 1 to swap byte-order of CRC AQR405 Revision 0.11 - January 5, 2015 F:C Reserved Internal reserved - do not modify B:8 USX0 Tx Rsvd Control[3:0] USX0 Transmit Reserved Control 7 Reserved Internal reserved - do not modify 6 USX0 Header CRC Gen USX0 Header CRC Generation Enable R/W 0 Set to 1 to generate CRC for the Packet Information Message and replace the SFD byte of transmit frame. 5 USX0 Enable PTP timestamp USX0 Enable the injection of PTP timestamp into Extension Field of the Packet Information Message R/W 0 Enable the injection of PTP timestamp into Extension Field of the Packet Information Message 4 USX0 Enable Packet Information Message USX0 Enable the injection of the Packet Information Message R/W 0 Enable the injection of the Packet Information Message 3:0 USX0 GMII to XGMII Conversion Control[3:0] USX0 GMII/MII to XGMII Conversion Control R/W 0x0 Bit 0: Disable continuous Idle insertion to MAC when FIFO depth is below the IFG thresh Bit 1: Enable error char insertion to MAC upon corrupted or missing SFD Bit 2: Enable Idle deletion to MAC when FIFO depth is beyond the high thresh Bit 3: Reserved 255 Table 6.399 PCS USX0 PTP Control Register: Address 3.C4C5 6.7.56 PCS USX0 PKT Info Message Register-0: Address 3.C4C6 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name USX0 Packet info message 15:0 [F:0] Description USX0 Packet Information Message to be injected bits [15:0] Type Default Note R/W 0x0000 Configure the message word before enabling the injection. Table 6.400 PCS USX0 PKT Info Message Register-0: Address 3.C4C6 6.7.57 PCS USX0 PKT Info Message Register-1: Address 3.C4C7 Bit F:0 Name USX0 Packet info message 31:16 [1F:10] Description USX0 Packet Information Message to be injected bits [31:16] Type Default R/W 0x0000 Note Table 6.401 PCS USX0 PKT Info Message Register-1: Address 3.C4C7 6.7.58 PCS USX0 PKT Info Message Register-2: Address 3.C4C8 Bit F:0 Name USX0 Packet info message 47:32 [2F:20] Description USX0 Packet Information Message to be injected bits [47:32] Type Default R/W 0x0000 Table 6.402 PCS USX0 PKT Info Message Register-2: Address 3.C4C8 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.59 PCS USX0 link Fill Data Register-0: Address 3.C4C9 Bit F:0 Name USX0 XGMII Link Fill Word[F:0] Description Type Default USX0 XGMII data for link fill word[15:0] R/W 0xBAD 1 Note This has to be different from normal control words in standard XGMII traffic. Table 6.403 PCS USX0 link Fill Data Register-0: Address 3.C4C9 6.7.60 PCS USX0 link Fill Data Register-1: Address 3.C4CA Bit AQR405 Revision 0.11 - January 5, 2015 F:0 Name USX0 XGMII Link Fill Word[1F:10] Description Type Default USX0 XGMII data for link fill word[31:16] R/W 0xBAD 2 Note Table 6.404 PCS USX0 link Fill Data Register-1: Address 3.C4CA 6.7.61 PCS USX0 Link FIFO Control Register: Address 3.C4CB Bit Name Description Type Default Note F:A USX0 High Threshold[5:0] USX0 Configure the high threshold for the link FIFO R/W 0x14 When the link FIFO is beyond this threshold, it requests the upstream to pause traffic by inserting link fill words. When link FIFO mode is set to one, idle words can also be deleted. 9:5 USX0 Low Threshold[4:0] USX0 Configure the low threshold for the link FIFO R/W 0x0A When the link FIFO is below this threshold, idle words can be inserted if link FIFO mode is set to one. 257 Table 6.405 PCS USX0 Link FIFO Control Register: Address 3.C4CB Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 4 USX0 Link Fifo Reset USX0 Set to 1 to force link FIFO to reset This FIFO is only used for AQRate 5G/2.5G mode. R/W 0 3:0 USX0 Link Fill Control[3:0] USX0 XGMII control for link fill word. R/W 0xF Note Table 6.405 PCS USX0 Link FIFO Control Register: Address 3.C4CB 6.7.62 PCS USX0 TX FIFO Control Register: Address 3.C4CC Bit F:D Name Description Type Default Reserved Internal reserved - do not modify C USX0 TX FIFO Reset USX0 MAC Tx FIFO reset R/W 0 B:8 USX0 TX FIFO threshold[3:0] USX0 MAC Tx FIFO threshold This is used to establish minimum FIFO depth before starting to read. R/W 0x1 7:4 USX0 Tx FIFO IFG threshold[3:0] USX0 MAC Tx FIFO IFG threshold This is used to insert Idle when FIFO depth is below this threshold. R/W 0x8 3:0 USX0 Tx FIFO hi threshold[3:0] USX0 MAC Tx FIFO High threshold This is used to delete Idle when FIFO depth is beyond this threshold. R/W 0xA Table 6.406 PCS USX0 TX FIFO Control Register: Address 3.C4CC Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.63 PCS USX0 Local Advertisement Register: Address 3.C4CD Bit F Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 USX0 Local advertisement status. 0 = Link down 1 = Link up R/W 0 Reserved USX0 Local Advertisement 0 [1:0] Reserved for future use. R/W 0x0 C USX0 Local Advertisement Duplex USX0 Local advertisement duplex. 0 = Half duplex 1 = Full duplex R/W 0 B:9 USX0 Local Advertisement Speed [2:0] USX0 Local advertisement speed. 0 = 10M 1 = 100M 2 = 1G 3 = 10G 4 = 2.5G 5 = 5G R/W 0x0 8 USX0 Local Advertisement EEE Capability USX0 Local advertisement EEE capability. 0 = Not supported 1 = Supported R/W 0 7 USX0 Local Advertisement EEE Clock Stop Capability USX0 Local advertisement EEE Clock Stop capability. 0 = Not supported 1 = Supported R/W 0 E:D Table 6.407 PCS USX0 Local Advertisement Register: Address 3.C4CD 259 USX0 Local Advertisement Status Note AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name 6:1 Reserved USX0 Local Advertisement 1 [5:0] USX0 Local Advertisement Mode 0 Description Type Default Reserved for future use. R/W 0x00 USX0 Local advertisement mode. 0 = SGMII 1 = USXGMII R/W 1 Note Table 6.407 PCS USX0 Local Advertisement Register: Address 3.C4CD 6.7.64 PCS USX1 Memory Control Register: Address 3.C4E0 Bit F:7 Name Description Type Default Reserved Internal reserved - do not modify 6 USX1 Memory power down USX1 Memory power down R/W 0 5:0 USX1 Memory RM [5:0] USX1 Memory RM bits R/W 0x00 Note Table 6.408 PCS USX1 Memory Control Register: Address 3.C4E0 6.7.65 PCS USX1 Control Register 1: Address 3.C4E1 Bit Name Description Type Default Note F USX1 Clock Enable USX1 Clock Enable R/W 1 Enable clock of USX1 block E USX1 Bypass USX1 Bypass R/W 0 Bypass USX1 block. This can be set to one to bypass USX for regular XFI 10G operation to reduce latency and power. Table 6.409 PCS USX1 Control Register 1: Address 3.C4E1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name D USX1 Link FIFO Mode C AQR405 Revision 0.11 - January 5, 2015 Type Default USX1 Link FIFO Mode R/W 0 This can be set to one to enable frame-adaptation in USX1 for AQRate 5G/2.5G mode. USX1 Replication Mode USX1 Replication Mode R/W 1 Set to 1 to select word-based replication. Set to 0 to select byte-based replication. Always set this to 1 (default). Reserved Internal reserved - do not modify 7 USX1 PCS Reset USX1 PCS Reset R/W 0 6 USX1 PCS low power USX1 PCS low power R/W 0 5 USX1 Parity check sense USX1 Parity check sense R/W 0 4:3 USX1 Speed mode[1:0] USX1 Speed mode (00:10G, 10:1G, 11:100M) R/W 0x0 2:1 USX1 AQRate mode[1:0] USX1 AQRate mode (00:10G, 10:5G, 11:2.5G) R/W 0x0 USX1 XGS RKL mode USX1 XGS RKL mode R/W 0 B:8 0 Description Note Table 6.409 PCS USX1 Control Register 1: Address 3.C4E1 261 6.7.66 PCS USX1 Local fault Control Register: Address 3.C4E2 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:9 8 7:0 Name Description Type Default Reserved Internal reserved - do not modify USX1 Inject Tx Local_Fault USX1 Inject Tx USXGMII Local_Fault R/W 0 USX1 Local_Fault code[7:0] USX1 USXGMII Local_Fault code R/W 0x11 Note Table 6.410 PCS USX1 Local fault Control Register: Address 3.C4E2 6.7.67 PCS USX1 MAC Local fault Control Register: Address 3.C4E3 Bit Name F:8 USX1 user define code[7:0] 7 6:0 Description Type Default USX1 User-defined code to replace USXGMII Local_Fault received. R/W 0x01 USX1 Inject Local Fault signal USX1 Inject Local Fault signal towards the MAC in 1G/100M mode R/W 0 USX1 Number of Idle coulmn[6:0] USX1 Number of Idle coulmn between Local Fault signals R/W 0x1F Table 6.411 PCS USX1 MAC Local fault Control Register: Address 3.C4E3 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.68 PCS USX1 Auto-Neg Control Register: Address 3.C4E4 Bit F:A Name Description Type Default Reserved Internal reserved - do not modify 9 USX1 Restart Auto-Negotiatio n USX1 Restart Auto-Negotiation R/W 0 8 USX1 Auto-neg Enable USX1 Auto negotiation Enable R/W 0 7:0 USX1 Auto neg Message code[7:0] USX1 USXGMII Auto-Negotiation Message Opcode. R/W 0x03 Note AQR405 Revision 0.11 - January 5, 2015 Table 6.412 PCS USX1 Auto-Neg Control Register: Address 3.C4E4 6.7.69 PCS USX1 PTP Control Register: Address 3.C4E5 Bit Name Description Type Default R/W 0x0 Reserved Internal reserved - do not modify B:8 USX1 Tx Rsvd Control[3:0] USX1 Transmit Reserved Control 7 Reserved Internal reserved - do not modify 6 USX1 Header CRC Gen USX1 Header CRC Generation Enable R/W 0 5 USX1 Enable PTP timestamp USX1 Enable the injection of PTP timestamp into Extension Field of the Packet Information Message R/W 0 Table 6.413 PCS USX1 PTP Control Register: Address 3.C4E5 263 F:C Note Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 4 USX1 Enable Packet Information Message USX1 Enable the injection of the Packet Information Message R/W 0 3:0 USX1 GMII to XGMII Conversion Control[3:0] USX1 GMII/MII to XGMII Conversion Control Bit 0: Disable continuous Idle insertion to MAC when FIFO depth is below the IFG thresh Bit 1: Enable error char insertion to MAC upon corrupted or missing SFD Bit 2: Enable Idle deletion to MAC when FIFO depth is beyond the high thresh Bit 3: Reserved R/W 0x0 Note Table 6.413 PCS USX1 PTP Control Register: Address 3.C4E5 6.7.70 PCS USX1 PKT Info Message Register-0: Address 3.C4E6 Bit F:0 Name USX1 Packet info message 15:0 [F:0] Description USX1 Packet Information Message to be injected bits [15:0] Type Default R/W 0x0000 Table 6.414 PCS USX1 PKT Info Message Register-0: Address 3.C4E6 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.71 PCS USX1 PKT Info Message Register-1: Address 3.C4E7 Bit F:0 Name USX1 Packet info message 31:16 [1F:10] Description USX1 Packet Information Message to be injected bits [31:16] Type Default R/W 0x0000 Note Table 6.415 PCS USX1 PKT Info Message Register-1: Address 3.C4E7 6.7.72 PCS USX1 PKT Info Message Register-2: Address 3.C4E8 Bit AQR405 Revision 0.11 - January 5, 2015 F:0 Name USX1 Packet info message 47:32 [2F:20] Description USX1 Packet Information Message to be injected bits [47:32] Type Default R/W 0x0000 Note Table 6.416 PCS USX1 PKT Info Message Register-2: Address 3.C4E8 6.7.73 PCS USX1 link Fill Data Register-0: Address 3.C4E9 Bit F:0 Name USX1 XGMII Link Fill Word[F:0] Description Type Default USX1 XGMII data for link fill word[15:0] R/W 0xBAD 1 Note Table 6.417 PCS USX1 link Fill Data Register-0: Address 3.C4E9 265 6.7.74 PCS USX1 link Fill Data Register-1: Address 3.C4EA AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name USX1 XGMII Link Fill Word[1F:10] Description Type Default USX1 XGMII data for link fill word[31:16] R/W 0xBAD 2 Note Table 6.418 PCS USX1 link Fill Data Register-1: Address 3.C4EA 6.7.75 PCS USX1 Link FIFO Control Register: Address 3.C4EB Bit Name Description Type Default Note F:A USX1 High Threshold[5:0] Configure the high threshold for the link FIFO R/W 0x14 When the link FIFO is beyond this threshold, it requests the upstream to pause traffic by inserting link fill words. When link FIFO mode is set to one, idle words can also be deleted. 9:5 USX1 Low Threshold[4:0] Configure the low threshold for the link FIFO R/W 0x0A When the link FIFO is below this threshold, idle words can be inserted if link FIFO mode is set to one. 4 USX1 Link Fifo Reset Set to 1 to force link FIFO to reset This FIFO is only used for AQRate 5G/2.5G mode. R/W 0 3:0 USX1 Link Fill Control[3:0] USX1 XGMII control for link fill word. R/W 0xF Table 6.419 PCS USX1 Link FIFO Control Register: Address 3.C4EB Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.76 PCS USX1 TX FIFO Control Register: Address 3.C4EC Bit F:D Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify C USX1 TX FIFO Reset USX1 MAC Tx FIFO reset R/W 0 B:8 USX1 TX FIFO threshold[3:0] USX1 MAC Tx FIFO threshold This is used to establish minimum FIFO depth before starting to read. R/W 0x1 7:4 USX1 Tx FIFO IFG threshold[3:0] USX1 MAC Tx FIFO IFG threshold This is used to insert Idle when FIFO depth is below this threshold. R/W 0x8 3:0 USX1 Tx FIFO hi threshold[3:0] USX1 MAC Tx FIFO High threshold This is used to delete Idle when FIFO depth is beyond this threshold. R/W 0xA Note Table 6.420 PCS USX1 TX FIFO Control Register: Address 3.C4EC 6.7.77 PCS USX1 Local Advertisement Register: Address 3.C4ED Bit F Description Type Default USX1 Local Advertisement Status USX1 Local advertisement status. 0 = Link down 1 = Link up R/W 0 Reserved USX1 Local Advertisement 0 [1:0] Reserved for future use. R/W 0x0 Table 6.421 PCS USX1 Local Advertisement Register: Address 3.C4ED Note 267 E:D Name Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 C USX1 Local Advertisement Duplex USX1 Local advertisement duplex. 0 = Half duplex 1 = Full duplex R/W 0 B:9 USX1 Local Advertisement Speed [2:0] USX1 Local advertisement speed. 0 = 10M 1 = 100M 2 = 1G 3 = 10G 4 = 2.5G 5 = 5G R/W 0x0 8 USX1 Local Advertisement EEE Capability USX1 Local advertisement EEE capability. 0 = Not supported 1 = Supported R/W 0 7 USX1 Local Advertisement EEE Clock Stop Capability USX1 Local advertisement EEE Clock Stop capability. 0 = Not supported 1 = Supported R/W 0 6:1 Reserved USX1 Local Advertisement 1 [5:0] Reserved for future use. R/W 0x00 USX1 Local Advertisement Mode USX1 Local advertisement mode. 0 = SGMII 1 = USXGMII R/W 1 0 Table 6.421 PCS USX1 Local Advertisement Register: Address 3.C4ED Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.78 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0 AQR405 Revision 0.11 - January 5, 2015 Name Description Type Default Note F:E Serdes Mux Swap TX Lane 3 [1:0] The lane swap setting for Lane 3, in the Tx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 3, 1=lane 0, 2=lane 1, 3=lane 2 D:C Serdes Mux Swap TX Lane 2 [1:0] The lane swap setting for Lane 2, in the Tx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 2, 1=lane 3, 2=lane 0, 3=lane 1 B:A Serdes Mux Swap TX Lane 1 [1:0] The lane swap setting for Lane 1, in the Tx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 1, 1=lane 2, 2=lane 3, 3=lane 0 9:8 Serdes Mux Swap TX Lane 0 [1:0] The lane swap setting for Lane 0, in the Tx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 0, 1=lane 1, 2=lane 2, 3=lane 3 7:6 Serdes Mux Swap RX Lane 3 [1:0] The lane swap setting for Lane 3, in the Rx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 3, 1=lane 0, 2=lane 1, 3=lane 2 5:4 Serdes Mux Swap RX Lane 2 [1:0] The lane swap setting for Lane 2, in the Rx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 2, 1=lane 3, 2=lane 0, 3=lane 1 Table 6.422 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0 269 Bit AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note 3:2 Serdes Mux Swap RX Lane 1 [1:0] The lane swap setting for Lane 1, in the Rx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 1, 1=lane 2, 2=lane 3, 3=lane 0 1:0 Serdes Mux Swap RX Lane 0 [1:0] The lane swap setting for Lane 0, in the Rx direction. It is implemented at the internal interface between the SerDes and digital logic. R/W 0x0 0=lane 0, 1=lane 1, 2=lane 2, 3=lane 3 Table 6.422 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0 6.7.79 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 Bit F:0 Name 10GBASE-T Good Frame Counter LSW [F:0] Description Type Default 10GBASE-T Good Frame Counter LSW SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.423 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 6.7.80 PCS Transmit Vendor FCS No Error Frame Counter 2: Address 3.C821 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 10GBASE-T Good Frame Counter MSW [19:10] 10GBASE-T Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.424 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.81 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 Bit F:0 Name 10GBASE-T Error Frame Counter LSW [F:0] Description 10GBASE-T Bad Frame Counter LSW Type Default SCT L 0x0000 Note This counts Ethernet bad frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.425 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 6.7.82 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 10GBASE-T Error Frame Counter MSW [19:10] 10GBASE-T Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.426 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 6.7.83 PCS Transmit XFI0 Vendor State 1: Address 3.C860 Bit F:0 Name XFI0 Good Frame Counter LSW [F:0] Description XFI0 Good Frame Counter LSW Type Default SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). 271 Table 6.427 PCS Transmit XFI0 Vendor State 1: Address 3.C860 6.7.84 PCS Transmit XFI0 Vendor State 2: Address 3.C861 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI0 Good Frame Counter MSW [9:0] XFI0 Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.428 PCS Transmit XFI0 Vendor State 2: Address 3.C861 6.7.85 PCS Transmit XFI0 Vendor State 3: Address 3.C862 Bit Name F:0 XFI0 Bad Frame Counter LSW [F:0] Description XFI0 Bad Frame Counter LSW Type Default Note SCT L 0x0000 This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.429 PCS Transmit XFI0 Vendor State 3: Address 3.C862 6.7.86 PCS Transmit XFI0 Vendor State 4: Address 3.C863 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI0 Bad Frame Counter MSW [9:0] XFI0 Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.430 PCS Transmit XFI0 Vendor State 4: Address 3.C863 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.87 PCS Transmit XFI1 Vendor State 1: Address 3.C870 Bit F:0 Name XFI1 Good Frame Counter LSW [F:0] Description XFI1 Good Frame Counter LSW Type Default SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.431 PCS Transmit XFI1 Vendor State 1: Address 3.C870 6.7.88 PCS Transmit XFI1 Vendor State 2: Address 3.C871 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:A Reserved Internal reserved - do not modify 9:0 XFI1 Good Frame Counter MSW [9:0] XFI1 Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.432 PCS Transmit XFI1 Vendor State 2: Address 3.C871 6.7.89 PCS Transmit XFI1 Vendor State 3: Address 3.C872 Bit Name F:0 XFI1 Bad Frame Counter LSW [F:0] Description XFI1 Bad Frame Counter LSW Type Default Note SCT L 0x0000 This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.433 PCS Transmit XFI1 Vendor State 3: Address 3.C872 273 6.7.90 PCS Transmit XFI1 Vendor State 4: Address 3.C873 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI1 Bad Frame Counter MSW [9:0] XFI1 Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.434 PCS Transmit XFI1 Vendor State 4: Address 3.C873 6.7.91 PCS Transmit XGS Vendor State 1: Address 3.C880 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XGS Collision Events Counter 0 [7:0] XGS collision events: Byte location from 1 to 64 bytes counter Type Default SCT 0x00 Note 1G/100M PHY collision events: Byte location from 1 to 64 counter Table 6.435 PCS Transmit XGS Vendor State 1: Address 3.C880 6.7.92 PCS Transmit XGS Vendor State 2: Address 3.C881 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XGS Collision Events Counter 1 [7:0] XGS collision events: Byte location from 65 to 96 bytes counter Type Default SCT 0x00 Note 1G/100M PHY collision events: Byte location from 65 to 96 counter Table 6.436 PCS Transmit XGS Vendor State 1: Address 3.C880 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.93 PCS Transmit XGS Vendor State 3: Address 3.C882 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XGS Collision Events Counter 2 [7:0] XGS collision events: Byte location from 97 to 128 counter Type Default SCT 0x00 Note 1G/100M PHY collision events: Byte location from 97 to 128 bytes counter Table 6.437 PCS Transmit XGS Vendor State 3: Address 3.C882 6.7.94 PCS Transmit XGS Vendor State 4: Address 3.C883 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XGS Collision Events Counter 3 [7:0] XGS collision events: Byte location from 129 to 192 counter Type Default SCT 0x00 Note 1G/100M PHY collision events: Byte location from 129 to 192 bytes counter Table 6.438 PCS Transmit XGS Vendor State 4: Address 3.C883 6.7.95 PCS Transmit XGS Vendor State 5: Address 3.C884 Bit Name Description Reserved Internal reserved - do not modify 7:0 XGS Collision Events Counter 4 [7:0] XGS collision events: Byte location from 193 to 320 counter Default SCT 0x00 Note 1G/100M PHY collision events: Byte location from 193 to 320 bytes counter Table 6.439 PCS Transmit XGS Vendor State 5: Address 3.C884 275 F:8 Type 6.7.96 PCS USX0 Transmit Status : Address 3.C8C0 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:C Reserved Internal reserved - do not modify B:8 USX0 Tx Rsvd Status[3:0] USX0 Tx Reserved Status 7:6 Reserved Internal reserved - do not modify 5 USX0 Tx Idle Insertion USX0 Tx Idle Insertion LH Tx Link Idle insertion 4 USX0 Tx Idle Deletion USX0 Tx Idle Deletion LH Rx Link Idle deletion USX0 Tx GMII to XGMII convertion status[3:0] USX0 GMII/MII to XGMII Conversion Status LH Bit 0: Detect FIFO empty during sending packet Bit 1: Inject Local_Fault to MAC Bits 2-3: Reserved 3:0 LH Table 6.440 PCS USX0 Transmit Status : Address 3.C8C0 6.7.97 PCS USX1 Transmit Status : Address 3.C8D0 Bit Name Description F:C Reserved Internal reserved - do not modify B:8 USX1 Tx Rsvd Status[3:0] USX1 Tx Reserved Status 7:6 Reserved Internal reserved - do not modify USX1 Tx Idle Insertion USX1 Tx Idle Insertion 5 Type Default LH LH Table 6.441 PCS USX1 Transmit Status : Address 3.C8D0 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 4 3:0 Name Description Type USX1 Tx Idle Deletion USX1 Tx Idle Deletion LH USX1 TX GMII to XGMII convertion status[3:0] USX1 GMII/MII to XGMII Conversion Status LH Default Note Bit 0: Detect FIFO empty during sending packet Bit 1: Inject Local_Fault to MAC Bits 2-3: Reserved Table 6.441 PCS USX1 Transmit Status : Address 3.C8D0 6.7.98 PCS Transmit Vendor System Interface State 1: Address 3.C8F0 Bit AQR405 Revision 0.11 - January 5, 2015 F:1 0 Name Description Reserved Internal reserved - do not modify System Interface Transmit Fault 1 = Fault condition on transmit path 0 = No fault condition on transmit path Type Default RO Note See "PCS Standard Status 1: Address 3.1" Table 6.442 PCS USX1 Transmit Status : Address 3.C8D0 6.7.99 PCS PTP Vendor State 1: Address 3.C900 Bit F:0 Name PTP Digital Clock Seconds Count Bits 15:0 [F:0] Description PTP digital clock seconds count bits 15:0 Type RO Default Note Digital clock seconds counter current value Table 6.443 PCS PTP Vendor State 1: Address 3.C900 277 6.7.100 PCS PTP Vendor State 2: Address 3.C901 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Digital Clock Seconds Count Bits 31:16 [1F:10] Description PTP digital clock seconds count bits 31:16 Type Default RO Note Digital clock seconds counter current value Table 6.444 PCS PTP Vendor State 2: Address 3.C901 6.7.101 PCS PTP Vendor State 3: Address 3.C902 Bit Name F:0 PTP Digital Clock Seconds Count Bits 47:32 [2F:20] Description PTP digital clock seconds count bits 47:32 Type Default RO Note Digital clock seconds counter current value Table 6.445 PCS PTP Vendor State 3: Address 3.C902 6.7.102 PCS PTP Vendor State 4: Address 3.C903 Bit Name F:0 PTP Digital Clock Nanoseconds Count LSW [F:0] Description PTP digital clock nanoseconds count bits 15:0 Type RO Default Note Digital clock nano-seconds counter current value Table 6.446 PCS PTP Vendor State 4: Address 3.C903 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.103 PCS PTP Vendor State 5: Address 3.C904 Bit F:0 Name PTP Digital Clock Nanoseconds Count MSW [1F:10] Description PTP digital clock nanoseconds count bits 31:16 Type Default RO Note Digital clock nano-seconds counter current value Table 6.447 PCS PTP Vendor State 5: Address 3.C904 6.7.104 PCS PTP Vendor State 6: Address 3.C905 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 PTP Digital Clock Fractional Nanoseconds Count LSW [F:0] Description PTP digital clock fractional nanoseconds count bits 15:0 Type Default RO Note Digital clock fractional nano-seconds counter current value Table 6.448 PCS PTP Vendor State 6: Address 3.C905 6.7.105 PCS PTP Vendor State 7: Address 3.C906 Name F:0 PTP Digital Clock Fractional Nanoseconds Count MSW [1F:10] Description PTP digital clock fractional nanoseconds count bits 31:16 Type RO Default Note Digital clock fractional nano-seconds counter current value Table 6.449 PCS PTP Vendor State 7: Address 3.C906 279 Bit 6.7.106 PCS PTP Vendor State 8: Address 3.C907 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Digital Clock Fractional Seconds Count LSW [F:0] Description PTP digital clock fractional seconds count bits 15:0 Type Default RO Note Digital clock fractional seconds counter current value Table 6.450 PCS PTP Vendor State 8: Address 3.C907 6.7.107 PCS PTP Vendor State 9: Address 3.C908 Bit Name F:0 PTP Digital Clock Fractional Seconds Count MSW [1F:10] Description PTP digital clock fractional seconds count bits 31:16 Type Default RO Note Digital clock fractional seconds counter current value Table 6.451 PCS PTP Vendor State 9: Address 3.C908 6.7.108 PCS PTP Vendor State 10: Address 3.C909 Bit F:0 Name PTP External Clock Count LSW [F:0] Description PTP external clock count bits 15:0 Type RO Default Note External clock counter value Table 6.452 PCS PTP Vendor State 10: Address 3.C909 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.109 PCS PTP Vendor State 11: Address 3.C90A Bit Name Description F:E Reserved Internal reserved - do not modify D:0 PTP External Clock Count MSW [1D:10] PTP external clock count bits 29:16 Type Default RO Note External clock counter value Table 6.453 PCS PTP Vendor State 11: Address 3.C90A 6.7.110 PCS PTP Vendor State 12: Address 3.C90B AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name PTP External Clock Seconds Count Bits 15:0 [F:0] Description PTP external clock seconds count bits 15:0 Type Default RO Note External clock seconds counter value Table 6.454 PCS PTP Vendor State 12: Address 3.C90B 6.7.111 PCS PTP Vendor State 13: Address 3.C90C Bit Name F:0 PTP External Clock Seconds Count Bits 31:16 [1F:10] Description PTP external clock seconds count bits 31:16 Type RO Default Note External clock seconds counter value 281 Table 6.455 PCS PTP Vendor State 13: Address 3.C90C 6.7.112 PCS PTP Vendor State 14: Address 3.C90D AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP External Clock Seconds Count Bits 47:32 [2F:20] Description PTP external clock seconds count bits 47:32 Type Default RO Note External clock seconds counter value Table 6.456 PCS PTP Vendor State 14: Address 3.C90D 6.7.113 PCS PTP Vendor State 15: Address 3.C90E Bit Name Description F:0 PTP External Clock Nanoseconds Count LSW [F:0] PTP external clock nanoseconds count bits 15:0 Type Default RO Note External clock nanoseconds counter value Table 6.457 PCS PTP Vendor State 15: Address 3.C90E 6.7.114 PCS PTP Vendor State 16: Address 3.C90F Bit F:0 Name PTP External Clock Nanoseconds Count MSW [1F:10] Description PTP external clock nanoseconds count bits 31:16 Type RO Default Note External clock nanoseconds counter value Table 6.458 PCS PTP Vendor State 16: Address 3.C90F Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.115 PCS PTP Vendor State 17: Address 3.C910 Bit Name F:0 PTP External Clock Fractional Nanoseconds Count LSW [F:0] Description PTP external clock fractional nanoseconds count bits 15:0 Type Default RO Note External clock fractional nanoseconds counter value Table 6.459 PCS PTP Vendor State 17: Address 3.C910 6.7.116 PCS PTP Vendor State 18: Address 3.C911 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 PTP External Clock Fractional Nanoseconds Count MSW [1F:10] Description PTP external clock fractional nanoseconds count bits 31:16 Type Default RO Note External clock fractional nanoseconds counter value Table 6.460 PCS PTP Vendor State 18: Address 3.C911 6.7.117 PCS PTP Vendor State 19: Address 3.C912 Bit Name F:0 PTP External Clock Fractional Seconds Count LSW [F:0] Description PTP external clock fractional seconds count bits 15:0 Type RO Default Note External clock fractional seconds counter value 283 Table 6.461 PCS PTP Vendor State 19: Address 3.C912 6.7.118 PCS PTP Vendor State 20: Address 3.C913 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP External Clock Fractional Seconds Count MSW [1F:10] Description PTP external clock fractional seconds count bits 31:16 Type Default RO Note External clock fractional seconds counter value Table 6.462 PCS PTP Vendor State 20: Address 3.C913 6.7.119 PCS PTP Vendor State 21: Address 3.C914 Bit F:0 Name PTP External GPIO Clock Seconds Count LSW [F:0] Description PTP external GPIO clock seconds count bits 15:0 Type Default RO Note External GPIO seconds counter value Table 6.463 PCS PTP Vendor State 21: Address 3.C914 6.7.120 PCS PTP Vendor State 22: Address 3.C915 Bit F:0 Name PTP External GPIO Clock Seconds Count MSW [1F:10] Description PTP external GPIO clock seconds count bits 31:16 Type RO Default Note External GPIO seconds counter value Table 6.464 PCS PTP Vendor State 22: Address 3.C915 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.121 PCS PTP Vendor State 23: Address 3.C916 Bit Name F:0 PTP External GPIO Clock Nanoseconds Count LSW [F:0] Description PTP external GPIO clock nanosecods count bits 15:0 Type Default RO Note External GPIO nanosecods counter value Table 6.465 PCS PTP Vendor State 23: Address 3.C916 6.7.122 PCS PTP Vendor State 24: Address 3.C917 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name PTP External GPIO Clock Nanoseconds Count MSW [1F:10] Description PTP external GPIO clock nanosecods count bits 31:16 Type Default RO Note External GPIO nanosecods counter value Table 6.466 PCS PTP Vendor State 24: Address 3.C917 6.7.123 PCS PTP Vendor State 25: Address 3.C918 Name F:0 PTP External GPIO Clock Fractional Nanoseconds Count LSW [F:0] Description PTP external GPIO clock fractional nanosecods count bits 15:0 Type RO Default Note External GPIO fractional nanosecods counter value Table 6.467 PCS PTP Vendor State 25: Address 3.C918 285 Bit 6.7.124 PCS PTP Vendor State 26: Address 3.C919 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name PTP External GPIO Clock Fractional Nanoseconds Count MSW [1F:10] Description PTP external GPIO clock fractional nanosecods count bits 31:16 Type Default RO Note External GPIO fractional nanosecods counter value Table 6.468 PCS PTP Vendor State 26: Address 3.C919 6.7.125 PCS PTP Vendor State 27: Address 3.C91A Bit F:0 Name PTP External GPIO Clock Fractional Seconds Count LSW [F:0] Description PTP external GPIO clock fractional seconds count bits 15:0 Type Default RO Note External GPIO fractional seconds counter value Table 6.469 PCS PTP Vendor State 27: Address 3.C91A 6.7.126 PCS PTP Vendor State 28: Address 3.C91B Bit F:0 Name PTP External GPIO Clock Fractional Seconds Count MSW [1F:10] Description PTP external GPIO clock fractional seconds count bits 31:16 Type RO Default Note External GPIO fractional seconds counter value Table 6.470 PCS PTP Vendor State 28: Address 3.C91B Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.127 PCS PTP Vendor State 29: Address 3.C91C Bit F:1 0 Name Description Reserved Internal reserved - do not modify PTP External GPIO Clock Update Done PTP external GPIO clock update done Type Default BLH Note External GPIO fractional seconds counter value Table 6.471 PCS PTP Vendor State 29: Address 3.C91C 6.7.128 PCS PTP Vendor State 30: Address 3.C91D AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 PTP USX0 Rx Timestamp Bits 15:0 [F:0] Description PTP USX0 Rx Timestamp bits 15:0 Type Default RO Note USX0 Rx timestamp current value Table 6.472 PCS PTP Vendor State 30: Address 3.C91D 6.7.129 PCS PTP Vendor State 31: Address 3.C91E Bit Name F:0 PTP USX0 Rx Timestamp Bits 31:16 [1F:10] Description PTP USX0 Rx Timestamp bits 31:16 Type RO Default Note USX0 Rx timestamp current value Table 6.473 PCS PTP Vendor State 31: Address 3.C91E 287 6.7.130 PCS PTP Vendor State 32: Address 3.C91F AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 PTP USX0 Rx Timestamp Bits 34:32 [22:20] PTP USX0 Rx Timestamp bits 34:32 Type Default RO Note USX0 Rx timestamp current value Table 6.474 PCS PTP Vendor State 32: Address 3.C91F 6.7.131 PCS PTP Vendor State 33: Address 3.C920 Bit Name F:0 PTP USX1 Rx Timestamp Bits 15:0 [F:0] Description PTP USX1 Rx Timestamp bits 15:0 Type Default RO Note USX1 Rx timestamp current value Table 6.475 PCS PTP Vendor State 33: Address 3.C920 6.7.132 PCS PTP Vendor State 34: Address 3.C921 Bit Name F:0 PTP USX1 Rx Timestamp Bits 31:16 [1F:10] Description PTP USX1 Rx Timestamp bits 31:16 Type RO Default Note USX1 Rx timestamp current value Table 6.476 PCS PTP Vendor State 34: Address 3.C921 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.133 PCS PTP Vendor State 35: Address 3.C922 Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 PTP USX1 Rx Timestamp Bits 34:32 [22:20] PTP USX1 Rx Timestamp bits 34:32 Type Default RO Note USX1 Rx timestamp current value Table 6.477 PCS PTP Vendor State 35: Address 3.C922 6.7.134 PCS PTP Egress Vendor State 1: Address 3.C930 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 PTP Egress Packet Count [2:0] PTP Egress packet count Type Default RO Note PTP packet count (0 to 4) Table 6.478 PCS PTP Vendor State 30: Address 3.C91D 6.7.135 PCS PTP Egress Vendor State 2: Address 3.C931 Bit F:0 Name PTP Egress Packet Data LSW [F:0] Description PTP Egress packet count Type RO Default Note PTP packet data 289 Table 6.479 PCS PTP Egress Vendor State 2: Address 3.C931 6.7.136 PCS PTP Egress Vendor State 3: Address 3.C932 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name PTP Egress Packet Data MSW [1F:10] Description PTP Egress packet count Type Default RO Note PTP packet data Table 6.480 PCS PTP Egress Vendor State 3: Address 3.C932 6.7.137 PCS PTP Egress Vendor State 4: Address 3.C933 Bit F:3 Name Description Type Default Note Reserved Internal reserved - do not modify 2 PTP Egress Packet Truncated PTP Egress packet EOP RO Asserted when PTP packet has been truncated because it is longer than 128 byte. 1 PTP Egress Packet EOP PTP Egress packet EOP RO Asserted when the PTP packet data returns the last word of packet 0 PTP Egress Packet SOP PTP Egress packet SOP RO Asserted when the PTP packet data returns the first word of packet Table 6.481 PCS PTP Egress Vendor State 4: Address 3.C933 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.138 PCS PTP Egress Vendor State 5: Address 3.C934 Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 PTP Egress Packet Time Stamp Count [2:0] PTP Egress packet count Type Default RO Note PTP packet timestamp count (0 to 4) Table 6.482 PCS PTP Egress Vendor State 5: Address 3.C934 6.7.139 PCS PTP Egress Vendor State 6: Address 3.C935 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name PTP Egress Packet Time Stamp [F:0] Description PTP Egress packet count Type Default RO Note PTP packet timestamp Report arrival timestamp in 8 consecutive reads for every packet (MSB first): 48-bit sec, 32-bit nano-sec, 16-bit fractional nano-sec, 32-bit fractional sec Table 6.483 PCS PTP Egress Vendor State 6: Address 3.C935 6.7.140 PCS PTP Egress Vendor State 7: Address 3.C936 Bit F:8 Name Reserved Description Type Default Note Internal reserved - do not modify 291 Table 6.484 PCS PTP Egress Vendor State 7: Address 3.C936 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note 7 PTP Egress Gap FIFO Error PTP Egress Gap FIFO error RO Read Egress Gap FIFO error for debug 6:0 PTP Egress Rx Packet Information [6:0] PTP Egress packet count RO Received PTP packet information Report diagnostic information about the type of PTP packet being received. Bits[1:0]: 0=L2, 1=IPv4, 2=IPv6, 3=reserved Bits[3:2]: 0=1588v1, 1=1588v2, 2=NTP/SNTP, 3=reserved For IEEE 1588: Bits[6:4]: 0=Sync, 1=Delay_Req, 2=General, 3=PDelay_Req, 4=Pdelay_Resp, 5=User-defined, 6 to 7=reserved For NTP/SNTP: Bits [6:4]: 0=Non-control, 1=Control & Private, 2 to 7=reserved Table 6.484 PCS PTP Egress Vendor State 7: Address 3.C936 6.7.141 PCS Transmit Vendor Alarms 1: Address 3.CC00 Bit F:1 0 Name Description Type Reserved PCS Transmit Vendor Alarms 1 [F:1] Reserved for future use LH XAUI Transmit Invalid 64B Block Detected 1 = Bad 64B block detected LH Default Table 6.485 PCS Transmit Vendor Alarms 1: Address 3.CC00 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.7.142 PCS Transmit Vendor Alarms 2: Address 3.CC01 Bit Name F:0 Reserved PCS Transmit Vendor Alarms 2 [F:0] Description Type Reserved for future use Default Note LH Table 6.486 PCS Transmit Vendor Alarms 2: Address 3.CC01 6.7.143 PCS Transmit Vendor Alarms 3: Address 3.CC02 Table 6.487 PCS Transmit Vendor Alarms 3: Address 3.CC02 Bit AQR405 Revision 0.11 - January 5, 2015 F:0 Name Reserved PCS Transmit Vendor Alarms 3 [F:0] Description Reserved for future use Type Default Note Default Note LH 6.7.144 PCS Transmit Vendor Alarms 4: Address 3.CC03 Bit Name Description Type Internal reserved - do not modify D XFI1 Transmit Invalid XGMII Character Received 1 = Invalid XGMII Character Received LH C XFI1 Transmit Reserved XGMII Character Received 1 = Reserved XGMII Character Received LH B XFI1 Transmit 64B Encode Error 1 = 64B Encode Error LH Table 6.488 PCS Transmit Vendor Alarms 4: Address 3.CC03 293 Reserved F:E Bit A:9 Name Description Type Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify XFI1 Transmit LOF Detected 1 = Loss of Frame detected Reserved Internal reserved - do not modify 5 XFI0 Transmit Invalid XGMII Character Received 1 = Invalid XGMII Character Received LH 4 XFI0 Transmit Reserved XGMII Character Received 1 = Reserved XGMII Character Received LH 3 XFI0 Transmit 64B Encode Error 1 = 64B Encode Error LH Reserved Internal reserved - do not modify XFI0 Transmit LOF Detected 1 = Loss of frame detected 8 7:6 2:1 0 Default Note LH LH Table 6.488 PCS Transmit Vendor Alarms 4: Address 3.CC03 6.7.145 PCS Standard Interrupt Mask 1: Address 3.D000 Bit F:C Name Description Type Default Note Reserved Internal reserved - do not modify B Tx LPI Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for Bit 3.1.B. A Rx LPI Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for Bit 3.1.A. Table 6.489 PCS Standard Interrupt Mask 1: Address 3.D000 Bit 9:3 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 2 1:0 Name Description Reserved Internal reserved - do not modify PCS Receive Link Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify Type Default R/W PD 0 Note Mask for Bit 3.1.2. Note this bit also shows up as Bit 3.20.C, but only as a status bit. Table 6.489 PCS Standard Interrupt Mask 1: Address 3.D000 6.7.146 PCS Standard Interrupt Mask 2: Address 3.D001 Bit F:C Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify B Transmit Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 3.8.B A Receive Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 3.8.A Reserved Internal reserved - do not modify 9:0 Table 6.490 PCS Standard Interrupt Mask 2: Address 3.D001 295 6.7.147 PCS Standard Interrupt Mask 3: Address 3.D002 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F 10GBASE-T PCS Block Lock Latched Mask E D:0 Description Type Default Note 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 When set, this bit indicates that 10GBASE-T PCS Framer has acquired frame synchronization and is locked. This is the interrupt for bit 3.21.F 10GBASE-T High BER Latched Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 When set, this bit indicates a high BER is being seen at the PCS. This is the interrupt for bit 3.21.E Reserved Internal reserved - do not modify Table 6.491 PCS Standard Interrupt Mask 3: Address 3.D002 6.7.148 PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 Bit Name F:1 Reserved PCS Transmit Vendor Alarms 1 Mask [F:1] 0 XAUI Transmit Invalid 64B Block Detected Mask Description Type Default 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0000 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.492 PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 Note 6.7.149 PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Reserved PCS Transmit Vendor Alarms 2 Mask [F:0] 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0x0000 Note Table 6.493 PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 6.7.150 PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Reserved PCS Transmit Vendor Alarms 3 Mask [F:0] Description 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0x000 Note Table 6.494 PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 6.7.151 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 Bit Name Description Type Default Internal reserved - do not modify D XFI1 Transmit Invalid XGMII Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 C XFI1 Transmit Reserved XGMII Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.495 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 297 Reserved F:E Note Bit B Name Description AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Type Default R/W PD 0 XFI1 Transmit Encode 64B Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify 5 XFI0 Transmit Invalid XGMII Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 4 XFI0 Transmit Reserved XGMII Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 3 XFI0 Transmit Encode 64B Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify A:6 2:0 Note Table 6.495 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 6.7.152 PCS Transmit Vendor Debug 1: Address 3.D800 Bit Name Description Type Default Note F PCS Tx Scrambler Disable 1 = Tx Scrambler Disabled 0 = Normal Operation R/W PD 0 Setting this bit disables the Tx scrambler during regular data transmission (i.e. scrambler functionality during training and startup is unmodified). E PCS Tx Inject CRC Error 1 = Inject CRC Error R/W 0 Setting this bit injects a CRC error in a single frame. Table 6.496 PCS Transmit Vendor Debug 1: Address 3.D800 Bit D Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential C:0 Name Description PCS Tx Inject Frame Error 1 = Inject frame error Reserved Internal reserved - do not modify Type Default R/W 0 Note Setting this bit injects an error at the location contained in Bits C:0 in the next PCS transmission frame. Table 6.496 PCS Transmit Vendor Debug 1: Address 3.D800 6.7.153 PCS Receive Vendor Provisioning 1: Address 3.E400 Bit F:1 0 Name Description Reserved Internal reserved - do not modify PCS Rx Error LDPC Frame Enable 1 = Enable erroring the LDPC frame payload 0 = Disable erroring the LDPC frame payload Type Default R/W PD 1 Note Error the entire LDPC frame payload upon uncorrectable LDPC parity or CRC error. AQR405 Revision 0.11 - January 5, 2015 Table 6.497 PCS Receive Vendor Provisioning 1: Address 3.E400 6.7.154 PCS Receive XFI0 Provisioning 1: Address 3.E460 Bit Name Description Reserved Internal reserved - do not modify 1 XFI0 Rx Descrambler Disable 1 = XFI0 Disable PCS scrambler 0 Reserved Internal reserved - do not modify F:2 Type Default R/W 0 Note PCS Descrambler Disable Table 6.498 PCS Receive XFI0 Provisioning 1: Address 3.E460 299 6.7.155 PCS Receive XFI0 Provisioning 2: Address 3.E461 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:9 Name Description Type Default Note Reserved Internal reserved - do not modify 8 XFI0 Test Data Source XFI0 Data pattern select 1 = All-zero input for pseudo-random test 1 = Local-fault (LF) input for pseudo-random test R/W 0 This bit determines the source of the data for the pseudo-random test (selected by Bit 7). 7:5 XFI0 Test Mode Select [2:0] Test Pattern Select: xx1 = PRBS-31 x10 = PRBS-9 100 = Square-wave 000 = Pseudo-random R/W 0x0 Note that the source for the pseudo-random test is determined by Bit 8. 4 XFI0 Test Pattern Enable 1 = XFI0 Enable test pattern R/W 0 10GBASE-R Pseudo-Random Test Pattern Enable - see the external view for an explanation 3 XFI0 Local Fault Inject 1 = XFI0 Inject local fault R/W 0 Inject Local_Fault Reserved Internal reserved - do not modify 2:0 Table 6.499 PCS Receive XFI0 Provisioning 2: Address 3.E461 6.7.156 PCS Receive XFI1 Provisioning 1: Address 3.E470 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:2 Name Description Reserved Internal reserved - do not modify 1 XFI1 Rx Descrambler Disable 1 = XFI1 Disable PCS scrambler 0 Reserved Internal reserved - do not modify Type Default R/W 0 Note PCS Descrambler Disable Table 6.500 PCS Receive XFI1 Provisioning 1: Address 3.E470 6.7.157 PCS Receive XFI1 Provisioning 2: Address 3.E471 Bit AQR405 Revision 0.11 - January 5, 2015 F:9 Name Description Type Default Note Reserved Internal reserved - do not modify 8 XFI1 Test Data Source XFI1 Data pattern select 1 = All-zero input for pseudo-random test 1 = Local-fault (LF) input for pseudo-random test R/W 0 This bit determines the source of the data for the pseudo-random test (selected by Bit 7). 7:5 XFI0 Test Mode Select [2:0] Test Pattern Select: xx1 = PRBS-31 x10 = PRBS-9 100 = Square-wave 000 = Pseudo-random R/W 0x0 Note that the source for the pseudo-random test is determined by Bit 8. 4 XFI1 Test Pattern Enable 1 = XFI1 Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern Enable - see the external view for an explanation Table 6.501 PCS Receive XFI1 Provisioning 2: Address 3.E471 301 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name 3 XFI1 Local Fault Inject 1 = XFI1 Inject local fault Reserved Internal reserved - do not modify 2:0 Description Type Default R/W 0 Note Inject Local_Fault Table 6.501 PCS Receive XFI1 Provisioning 2: Address 3.E471 6.7.158 PCS USX0 RX Control Register: Address 3.E4D0 Bit Name Description Type Default R/W 0x0 F:C USX0 Rx Rsvd Control[3:0] USX0 Receive Reserved Control B:A Reserved Internal reserved - do not modify 9 USX0 Header CRC Chk USX0 Header CRC Check Enable R/W 0 8 USX0 RX PKT Info Extension Field Set to 1 to include the Extension Field for the detection of the change notification, otherwise the Extension Field is ignored. R/W 0 7:6 USX0 RX Local Fault Mode[1:0] Rx USXGMII Local_Fault mode: 0=Pass-through 1=Replaced with Idle 2=Replaced with user-defined code 3=Reserved R/W 0x0 Table 6.502 PCS USX0 RX Control Register: Address 3.E4D0 Note Bit Name Description Type Default Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 5:4 USX0 RX IFG mode[1:0] Rx Inter-Frame Gap Mode [1:0] Minimum IFG assured on traffic sent to GMII/MII (0:12-byte, 1 to 2: reserved, 3:none, default:0) R/W 0x0 3:0 USX0 RX XGMII to GMII conversion control[3:0] XGMII to GMII/MII Conversion Control Bits 0-3: Reserved R/W 0x0 Note Table 6.502 PCS USX0 RX Control Register: Address 3.E4D0 6.7.159 PCS USX0 RX FIFO Control Register: Address 3.E4D1 AQR405 Revision 0.11 - January 5, 2015 Bit F:9 Name Description Type Default Reserved Internal reserved - do not modify 8 USX0 RX FIFO Reset MAC Rx FIFO reset R/W 0 7:4 USX0 RX FIFO Threshold[3:0] MAC Rx FIFO threshold This is used to establish minimum FIFO depth before starting to read. R/W 0x1 3:0 USX0 RX FIFO IFG Threshold[3:0] MAC Rx FIFO IFG threshold (default:8) This is used to delete Idle when FIFO depth is beyond this threshold. R/W 0x8 Note Table 6.503 PCS USX0 RX FIFO Control Register: Address 3.E4D1 303 6.7.160 PCS USX0 SM Control Register: Address 3.E4D2 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default F:C Reserved Internal reserved - do not modify B USX0 SM Freeze SAN State Machine Freeze R/W 0 A USX0 SM Force SAN State Machine Force R/W 0 9 USX0 SM Redirect SAN State Machine Redirect R/W 0 8:6 USX0 SM Current State Match[2:0] SAN State Machine Current State Match R/W 0x0 5:3 USX0 SM Next state Match[2:0] SAN State Machine Next State Match R/W 0x0 2:0 USX0 SM Redirect state[2:0] SAN State Machine redirect State. R/W 0x0 Table 6.504 PCS USX0 SM Control Register: Address 3.E4D2 Note 6.7.161 PCS USX0 Link Timer Control Register: Address 3.E4D3 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:C Name Description Type Default Reserved Internal reserved - do not modify B USX0 Link Timer Reset Link_timer Reset (0=Normal, 1=Reset to 0) R/W 0 A USX0 Link Timer Freeze Link_timer Freeze (0=Normal, 1=Frozen) R/W 0 9:0 USX0 Link Timer Threshold[9:0] Link timer threshold (in terms of 12.8us, default=125 for 1.6ms) R/W 0x07D Note Table 6.505 PCS USX0 Link Timer Control Register: Address 3.E4D3 AQR405 Revision 0.11 - January 5, 2015 6.7.162 PCS USX0 RX Fault Control Register: Address 3.E4D4 Bit Name Description Type Default F:8 USX0 RX Fault Mask[7:0] Set to 1 to compare the corresponding bit(s) against the Fault data pattern, otherwise the corresponding bit(s) are ignored. R/W 0xFF 7:0 USX0 RX Fault Data[7:0] Data pattern with the corresponding mask to compare against the receive data for the detection of Fault signal. R/W 0x11 Note Table 6.506 PCS USX0 RX Fault Control Register: Address 3.E4D4 305 6.7.163 PCS USX1 RX Control Register: Address 3.E4E0 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default R/W 0x0 F:C USX1 Rx Rsvd Control[3:0] USX0 Receive Reserved Control B:A Reserved Internal reserved - do not modify 9 USX1 Header CRC Chk USX1 Header CRC Check Enable R/W 0 8 USX1 RX PKT Info Extension Field Set to 1 to include the Extension Field for the detection of the change notification, otherwise the Extension Field is ignored. R/W 0 7:6 USX1 RX Local Fault Mode[1:0] Rx USXGMII Local_Fault mode: 0=Pass-through 1=Replaced with Idle 2=Replaced with user-defined code 3=Reserved R/W 0x0 5:4 USX1 RX IFG mode[1:0] Rx Inter-Frame Gap Mode [1:0] Minimum IFG assured on traffic sent to GMII/MII (0:12-byte, 1 to 2: reserved, 3:none, default:0) R/W 0x0 3:0 USX1 RX XGMII to GMII conversion control[3:0] XGMII to GMII/MII Conversion Control Bits 0-3: Reserved R/W 0x0 Table 6.507 PCS USX1 RX Control Register: Address 3.E4E0 Note 6.7.164 PCS USX1 RX FIFO Control Register: Address 3.E4E1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:9 Name Description Type Default Reserved Internal reserved - do not modify 8 USX1 RX FIFO Reset MAC Rx FIFO reset R/W 0 7:4 USX1 RX FIFO Threshold[3:0] MAC Rx FIFO threshold This is used to establish minimum FIFO depth before starting to read. R/W 0x1 3:0 USX1 RX FIFO IFG Threshold[3:0] MAC Rx FIFO IFG threshold (default:8) This is used to delete Idle when FIFO depth is beyond this threshold. R/W 0x8 Note AQR405 Revision 0.11 - January 5, 2015 Table 6.508 PCS USX1 RX FIFO Control Register: Address 3.E4E1 6.7.165 PCS USX1 SM Control Register: Address 3.E4E2 Bit Name Description Type Default F:C Reserved Internal reserved - do not modify B USX0 SM Freeze SAN State Machine Freeze R/W 0 A USX1 SM Force SAN State Machine Force R/W 0 9 USX1 SM Redirect SAN State Machine Redirect R/W 0 307 Table 6.509 PCS USX1 SM Control Register: Address 3.E4E2 Note Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 8:6 USX1 SM Current State Match[2:0] SAN State Machine Current State Match R/W 0x0 5:3 USX1 SM Next state Match[2:0] SAN State Machine Next State Match R/W 0x0 2:0 USX1 SM Redirect state[2:0] SAN State Machine redirect State. R/W 0x0 Note Table 6.509 PCS USX1 SM Control Register: Address 3.E4E2 6.7.166 PCS USX1 Link Timer Control Register: Address 3.E4E3 Bit F:C Name Description Type Default Reserved Internal reserved - do not modify B USX1 Link Timer Reset Link_timer Reset (0=Normal, 1=Reset to 0) R/W 0 A USX1 Link Timer Freeze Link_timer Freeze (0=Normal, 1=Frozen) R/W 0 9:0 USX1 Link Timer Threshold[9:0] Link timer threshold (in terms of 12.8us, default=125 for 1.6ms) R/W 0x07D Table 6.510 PCS USX1 Link Timer Control Register: Address 3.E4E3 Note 6.7.167 PCS USX1 RX Fault Control Register: Address 3.E4E4 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default F:8 USX1 RX Fault Mask[7:0] Set to 1 to compare the corresponding bit(s) against the Fault data pattern, otherwise the corresponding bit(s) are ignored. R/W 0xFF 7:0 USX1 RX Fault Data[7:0] Data pattern with the corresponding mask to compare against the receive data for the detection of Fault signal. R/W 0x11 Note Table 6.511 PCS USX1 RX Fault Control Register: Address 3.E4E4 AQR405 Revision 0.11 - January 5, 2015 6.7.168 PCS PTP Ingress Vendor Provisioning 1: Address 3.E600 Bit Name Description Type Default Note F PTP Ingress VLAN Tagging Enable 1 = PTP Ingress VLAN tagging enabled R/W 0 Enable VLAN tagging for IEEE1588 or NTP/SNTP packet (default:0x1) E PTP Ingress IPv6/UDP Encapsulated Enabled 1 = PTP Ingress IPv6/UDP encapsulated enable R/W 0 Enable IPv6/UDP encapsulated IEEE1588 or NTP/SNTP packet (default: 0) D PTP Ingress IPv4/UDP Encapsulated Enabled 1 = PTP Ingress IPv4/UDP encapsulated enable R/W 0 Enable IPv4/UDP encapsulated IEEE1588 or NTP/SNTP packet (default: 0) Table 6.512 PCS USX1 RX Control Register: Address 3.E4E0 309 Bit Description Type Default PTP Ingress Ethernet Encapsulated Enable 1 = PTP Ingress ethernet encapsulated enable R/W 0 Enable Ethernet encapsulated IEEE1588 packet (default: 0) B:A Reserved Internal reserved - do not modify 9:8 PTP Ingress NTP Configuration [1:0] PTP Ingress NTP/SNTP configuration R/W 0x0 NTP/SNTP configuration (bit 0: 0=client, 1=server, bit 1: 0=Ingress, 1=ingress) 7:6 Reserved Internal reserved - do not modify 5 PTP Ingress Back Pressure Enable 1 = PTP Ingress back pressure enable R/W 0 PTP FIFO ready enable (default: 0) Set to 1 to enable the back pressure during the appending of timestamp to the end of packet Set to 0 to disable the back pressue. 4 PTP Ingress NTP Enable 1 = PTP Ingress NTP/SNTP enable R/W 0 Enable NTP/SNTP Reserved Internal reserved - do not modify 1 PTP Ingress 1588 Version 2 Enable 1 = PTP Ingress 1588 version 2 enable R/W 0 Enable IEEE 1588 Version 2 0 PTP Ingress 1588 Version 1 Enable 1 = PTP Ingress 1588 version 1 enable R/W 0 Enable IEEE 1588 Version 1 C Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 3:2 Name Note Table 6.512 PCS USX1 RX Control Register: Address 3.E4E0 6.7.169 PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify E:C PTP Ingress IPv6 Destination Address Matching Enable [2:0] PTP Ingress IPv6 destination address matching enable R/W 0x3 Enable IPv6 destination address matching for IEEE1588 (default:0x3) bit 0: FF0X:0:0:0:0:0:0:181 (X: 0x0 to 0xF) bit 1: FF02:0:0:0:0:0:0:6B bit 2: user-defined B:8 PTP Ingress IPv4 Destination Address Matching Enable [3:0] PTP Ingress IPv4 destination address matching enable R/W 0x7 Enable IPv4 destination address matching for IEEE1588 (default:0x7) bit 0: 224.0.1.129 bit 1: 224.0.1.130-132 bit 2: 224.0.0.107 bit 3: user-defiined Reserved Internal reserved - do not modify 6:4 PTP Ingress MAC Destination Address Matching Enable [2:0] PTP Ingress MAC destination address matching enable R/W 0x3 Enable MAC destination address matching for IEEE1588 (default:0x3) bit 0: 01-1B-19-00-00-00 bit 1: 01-80-C2-00-00-0E bit 2: user-defined 3:2 Reserved Internal reserved - do not modify 1:0 PTP Ingress Ethertype Matching Enable [1:0] PTP Ingress ethertype matching enable R/W 0x1 Enable Ethertype matching for Ethernet encapsulated IEEE1588 packet (default:0x1) bit 0: 0x88F7 bit 1: user-defined This shall be configured before enable Ethernet encapsulation. At least one bit needs to be set. 7 Table 6.513 PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 311 6.7.170 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F Name Description Type Default R/W 0x3 Note Reserved Internal reserved - do not modify PTP Ingress NTP/SNTP Version [2:0] PTP Ingress NTP/SNTP version PTP Ingress 1588 Version [3:0] PTP Ingress IEEE 1588 version Reserved Internal reserved - do not modify 5 PTP Ingress 1588 2 Step Enable PTP Ingress 1588 2 step enable R/W 0 Set to 1 to consider the two-step flag for IEEE1588v2 (or PTP_ASSIST for IEEE1588v1). It will prevent timestamp overwritten for 2-step Sync message. Set to 0 will allow timestamp update regardless of the flag (default: 0) 4 PTP Ingress 1588 Version 2 Domain Matching Enable 1 = PTP Ingress 1588 version 2 domain matching enable R/W 0 Enable domain matching for IEEE1588v2 (default: 0) E:C B:8 7:6 Version of NTP/SNTP (default: 3) It specifies the minimum value of version number of NTP/SNTP to be supported. It shall not be less than 3, but a value of 0 will disable version checking. R/W 0x2 Latest version of IEEE1588 (default: 2) It allows support of future versions of the IEEE 1588. It shall not be less than 2, but a value of 0 will disable version checking and assume to be compatible with version 2. Table 6.514 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 Bit 3 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 2:0 Name Description Reserved Internal reserved - do not modify PTP Ingress UDP Destination Port Matching Enable [2:0] PTP Ingress UDP destination port matching enable Type Default R/W 0x3 Note Enable UDP destination port matching for IEEE 1588 or NTP/SNTP (default:0x3) bit 0: 319 for IEEE1588, or 123 for NTP/SNTP bit 1: 320 for IEEE1588, not used for NTP/SNTP bit 2: user-defined Table 6.514 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 6.7.171 PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 PTP Ingress Ethertype [F:0] Description PTP Ingress UDP destination port matching enable Type Default R/W 0x0000 Note User-defined EtherType for Ethernet encapsulated IEEE1588 packets (default: 0) Table 6.515 PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 6.7.172 PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 Bit Name F:0 PTP Ingress MAC Destination Address Bits 15:0 [F:0] Description PTP Ingress MAC destination address bits 15:0 Type Default R/W 0x0000 Note User-defined MAC destination address (default: 0) Table 6.516 PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 313 6.7.173 PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Ingress MAC Destination Address Bits 31:16 [1F:10] Description PTP Ingress MAC destination address bits 31:16 Type Default R/W 0x0000 Note User-defined MAC destination address (default: 0) Table 6.517 PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 6.7.174 PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 Bit Name F:0 PTP Ingress MAC Destination Address Bits 47:32 [2F:20] Description PTP Ingress MAC destination address bits 47:32 Type Default R/W 0x0000 Note User-defined MAC destination address (default: 0) Table 6.518 PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 6.7.175 PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 Bit Name F:0 PTP Ingress IPv4 Destination Address LSW [F:0] Description PTP Ingress IPv4 destination address bits 15:0 Type Default R/W 0x0000 Note User-defined IPv4 destination address (default: 0) Table 6.519 PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 6.7.176 PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Ingress IPv4 Destination Address MSW [1F:10] Description PTP Ingress IPv4 destination address bits 31:16 Type Default R/W 0x0000 Note User-defined IPv4 destination address (default: 0) Table 6.520 PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 6.7.177 PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 15:0 [F:0] Description PTP Ingress IPv6 destination address bits 15:0 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.521 PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 6.7.178 PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 31:16 [1F:10] Description PTP Ingress IPv6 destination address bits 31:16 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.522 PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A 315 6.7.179 PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 47:32 [2F:20] Description PTP Ingress IPv6 destination address bits 47:32 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.523 PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B 6.7.180 PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 63:48 [3F:30] Description PTP Ingress IPv6 destination address bits 63:48 Type Default R/W 0x0000 Note User-defined (default: 0) IPv6 destination address Table 6.524 PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C 6.7.181 PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 79:64 [4F:40] Description PTP Ingress IPv6 destination address bits 79:64 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.525 PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D 6.7.182 PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 95:80 [5F:50] Description PTP Ingress IPv6 destination address bits 95:80 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.526 PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E 6.7.183 PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 111:96 [6F:60] Description PTP Ingress IPv6 destination address bits 111:96 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.527 PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F 6.7.184 PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 Bit Name F:0 PTP Ingress IPv6 Destination Address Bits 127:112 [7F:70] Description PTP Ingress IPv6 destination address bits 127:112 Type Default R/W 0x0000 Note User-defined IPv6 destination address (default: 0) Table 6.528 PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 317 6.7.185 PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 PTP Ingress UDP Destination Port [F:0] Description PTP Ingress UDP destination port Type Default Note R/W 0x0000 User-defined UDP destination port (default: 0) Table 6.529 PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 6.7.186 PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 PTP Ingress 1588 Version 2 Domain [7:0] PTP Ingress 1588 Version 2 Domain Type Default R/W 0x00 Note User-defined domain for IEEE1588v2 (default:0) Table 6.530 PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 6.7.187 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 Bit F:4 3 Name Description Reserved Internal reserved - do not modify PTP Ingress Correction Offset Sign 1 = PTP Ingress correction offset sign Type Default R/W 0 Note Correction field offset sign (0: add, 1:subtract, default: 0) This indicates whether to add or subtract the correction field offset. Table 6.531 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 2 PTP Ingress Time Stamp Offset Sign 1 = PTP Ingress time stamp offset sign R/W 0 Timestamp nano-/fractional-seconds offset sign (0: add, 1:subtract, default: 0) This indicates whether to add or subtract the timestamp compensation offset. 1 PTP Ingress Set Time Stamp Offset 1 = PTP Ingress set time stamp offset R/W 0 Toggle to set the new offsets of the timestamp and correction field (default: 0) 0 PTP Ingress Byte Swap 1 = PTP Ingress byte swap R/W 0 Swap byte order of the 32-bit packet data (default:0) Table 6.531 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 6.7.188 PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name PTP Ingress Time Stamp Nanosecond Offset [F:0] Description PTP Ingress time stamp nanosecond offset Type Default Note R/W 0x0000 Timestamp nanoseconds offset (default: 0) This compensates the difference between MDI and timestamping point. Table 6.532 PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 6.7.189 PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 Bit F:0 Name PTP Ingress Time Stamp Fractional Second Offset LSW [F:0] Description PTP Ingress time stamp fractional second offset Default Note R/W 0x0000 Timestamp fractional-seconds offset (default: 0) This is the LSB 19-bit of the 32-bit fractionalseconds counter. Software shall this value is equivalent to the corresponding nanoseconds offset. Table 6.533 PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 319 Type 6.7.190 PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 PTP Ingress Time Stamp Fractional Second Offset MSW [12:10] PTP Ingress time stamp fractional second offset Type Default R/W 0x0 Note Timestamp fractional-seconds offset (default: 0) This is the LSB 19-bit of the 32-bit fractionalseconds counter. Software shall this value is equivalent to the corresponding nanoseconds offset. Table 6.534 PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 6.7.191 PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 Bit Name F:0 PTP Ingress Correction Offset LSW [F:0] Description PTP Ingress correction offset Type Default Note R/W 0x0000 Correction field offset (16-bit nano-second & 16-bit fractional nano-second, default: 0) This compensates the asymmetrical Tx/Rx delay, and/or any adjustment for transparent application. Table 6.535 PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 6.7.192 PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:0 Name PTP Ingress Correction Offset MSW [1F:10] Description PTP Ingress correction offset Type Default Note R/W 0x0000 Correction field offset (16-bit nano-second & 16-bit fractional nano-second, default: 0) This compensates the asymmetrical Tx/Rx delay, and/or any adjustment for transparent application. Table 6.536 PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 6.7.193 PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:C Reserved Internal reserved - do not modify B:0 PTP Ingress Packet Action [B:0] PTP Ingress packet action Type Default R/W 0x000 Note IEEE 1588v2 packet action(0=None, 1=Capture, 2=reserved, 3=Capture & forward, default: 0) Bits [1:0]: Sync message Bits [3:2]: Delay_Req message Bits [5:4]: Pdelay_Req message Bits [7:6]: Pdelay_Resp message Bits [9:8]: User-defined message Bits [11:10]: General messages Table 6.537 PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 321 6.7.194 PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:E Reserved Internal reserved - do not modify D:C PTP Ingress NTP/SNTP Time Stamp Action [1:0] PTP Ingress correct action R/W 0x0 NTP/SNTP timestamp action (0=None, 1=Overwrite, 2=Append, 3=reserved) B:8 PTP Ingress NTP/SNTP Packet Action [3:0] PTP Ingress correct action R/W 0x0 NTP/SNTP packet action (0=None, 1=Capture, 2=reserved, 3=Capture & forward, 3=reserved) Bits [1:0]: Non-control messages Bits [3:2]: Control & Private-use messages 7:0 Reserved Internal reserved - do not modify Table 6.538 PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A 6.7.195 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B Bit F:6 5 Name Description Reserved Internal reserved - do not modify PTP Ingress Correction Fractional Nanosecond Timestampe Enable 1 = PTP Ingress CRC append enable Type Default R/W 0 Note Correction fractional-nanoseconds timestamp enable (default: 0) Set to 1 to allow the fractional-nanoseconds count of the timestamp to be carried by the LSB 16-bit of the original Correction field (See pif_ptp_ing_correct_act_i=3). Set to 0 to ignore the fractional-nanoseconds count during update of the Correction field. Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 4 PTP Ingress Correction Clear Timestamp Enable 3 2 Description AQR405 Revision 0.11 - January 5, 2015 Type Default Note 1 = PTP Ingress CRC append enable R/W 1 Correction clear timestamp enable (default: 1) Set to 1 to allow the timestamp field to be cleared to 0 by the corresponding Correction field action (See pif_ptp_ing_correct_act_i). Set to 0 to keep the timestamp field determined by the corresponding timestamp action (See pif_ptp_ing_ts_act_i) PTP Ingress CRC Append Enable 1 = PTP Ingress CRC append enable R/W 0 Ethernet FCS appending enable (default: 0) Set to 1 to append FCS into Ethernet frame. Set to 0 to have no FCS at the end of frame. PTP Ingress UDP Append Format 1 = PTP Ingress UDP append format R/W 0 UDP packet appending format (default: 0) This applies only for IEEE 1588v1 or NTP/SNTP packets. Set to 1 to replace the last 16-bit of appended timestamp (fractional nanoseconds) with a 16-bit word to compensate for the change of UDP checksum due to the appended timestamp. This allows timestamp removal of any packet length without the need of disabling the UDP checksum (setting to all-zeroes). See ptp_pif_egr_pkt_remove_err_o for more information. Set to 0 to append 96-bit timestamp without UDP checksum compensation. There is no need for IEEE 1588v2 because the packet length shall be supported without error, and the 16-bit fractional nanoseconds are used to update the Correction field. Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B 323 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 PTP Ingress UDP Append Enable 1 = PTP Ingress UDP append enable R/W 1 UDP packet appending enable (default: 1)Set to1 to append timestamp/correction field (if enabled by the corresponding action) into UDP payload. Set to 0 to append those into L2 Ethernet payload 0 PTP Ingress UDP Checksum Enable 1 = PTP Ingress UDP checksum enable R/W 1 UDP checksum calculation enable (default: 1) Set to 1 to recalculate the UDP checksum Set to 0 to set the UDP checksum to all-zeroes Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B 6.7.196 PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C Bit Name F PTP Ingress Packet Pipeline Reset E D:0 Description Type Default Note 1 = PTP Ingress packet pipeline reset R/W 0 PTP packet pipeline reset (default:0) Set to 1 to reset PTP packet pipeline PTP Ingress Packet Ready FIFO Reset 1 = PTP Ingress packet ready FIFO reset R/W 0 PTP packet ready FIFO reset (default:0) Set to 1 to reset PTP packet ready FIFO Reserved Internal reserved - do not modify Table 6.540 PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C 6.7.197 PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:4 Reserved Internal reserved - do not modify 3:0 PTP Ingress Packet Pipeline Threshold [3:0] 1 = PTP Ingress UDP append enable Type Default R/W 0x5 Note PTP packet pipeline threshold (default: 0x5) This is used in 1G or 100M mode to regulate packet flow. This has no effect in 10G mode. Table 6.541 PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D 6.7.198 PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E Bit F AQR405 Revision 0.11 - January 5, 2015 E:1 0 Name Description PTP Ingress Packet Buffer Reset 1 = PTP Ingress packet buffer reset Reserved Internal reserved - do not modify PTP Ingress Packet Buffer Read Enable 1 = PTP Ingress packet buffer read enable Type Default Note R/W 0 PTP packet buffer reset (default: 0) Set to 1 to reset PTP packet extraction buffer and timestamp R/W 0 PTP packet buffer read (default: 0) Toggle 0->1->0 to read the next packet data out of extraction FIFO Table 6.542 PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E 325 6.7.199 PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:2 Name Description Type Default Note Reserved Internal reserved - do not modify 1 PTP Ingress Packet Pause PTP Ingress packet pause R/W 0 PTP packet & timestamp extraction pause (default: 0) Set to 1 to pause the extraction of packet and timestamp into the corresponding buffers. Set to 0 to resume the extraction. 0 PTP Ingress Packet Size Limit PTP Ingress packet size limit R/W 0 PTP packet size limit (default: 0) Set to 1 to limit PTP packet to 128-byte to ensure packet buffer is enough to fit up to 4 packets Table 6.543 PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F 6.7.200 PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 Bit F:1 0 Name Description Reserved Internal reserved - do not modify PTP Ingress Packet Time Stamp Read Enable 1 = PTP Ingress packet time stamp reset enable Type Default R/W 0 Note PTP packet timestamp read (default: 0) Toggle 0->1->0 to read the next word of corresponding timestamp of the extracted packet Table 6.544 PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 6.7.201 PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:C Reserved Internal reserved - do not modify B:8 PTP Ingress 1588 Version 1 Time Stamp Action [3:0] PTP ingress 1588 version 1 time stamp action Type Default R/W 0x0 Note IEEE 1588v1 timestamp action (0=None, 1=Overwrite, 2=Append, 3=Remove, default: 0). Bits [1:0]: Sync messages Bits [3:2]: All other event messages 7:6 Reserved Internal reserved - do not modify 5:0 PTP Ingress 1588 Version 1 Packet Action [5:0] PTP ingress 1588 version 1 packet action R/W 0x00 IEEE 1588v1 packet action (0=None, 1=Capture, 2=reserved, 3=Capture & forward, default: 0). Bits [1:0]: Sync message AQR405 Revision 0.11 - January 5, 2015 Bits [3:2]: All other event messages Bits [5:4]: General messages Table 6.545 PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 6.7.202 PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 Bit F:0 Name PTP Ingress Stacked VLAN ID [F:0] Description User-defined Tag Protocol Identifier (TPID) for stacked VLAN Type Default Note R/W 0x88A8 User-defined Tag Protocol Identifier (TPID) for stacked VLAN (default: 0x88A8 for 802.1ad). For Q-in-Q, it can be 0x9100 or other user-defined values. In addition, 0x8100 will always be recognized as valid TPID. Table 6.546 PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 327 6.7.203 PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:0 Name Description Reserved Internal reserved - do not modify PTP Ingress Correction Action [E:0] PTP Ingress correct action Type Default Note R/W 0x0000 IEEE 1588v2 correction field action (default:0) 0: No change 1: Correction + TS - TS(Append) + Offset 2: Correction + Offset 3: TS - Timestamp + Offset (Timestamp field will be set to 0 if enabled. See pif_ptp_egr_correct_clr_ts_en_i) 4: Correction + TS + Offset 5: Correction - TS + Offset 6 to 7: Reserved Bits [2:0]: Sync messages Bits [5:3]: Delay_Req message Bits [8:6]: Pdelay_Req message Bits [11:9]: Pdelay_Resp message Bits [14:12]: User-defined message Table 6.547 PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 6.7.204 PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 PTP Ingress Time Stamp Action [9:0] PTP Ingress packet action Type Default R/W 0x000 Note IEEE 1588v2 timestamp action (0=None, 1=Overwrite, 2=Append, 3=Remove, default: 0). Bits [1:0]: Sync messages Bits [3:2]: Delay_Req message Bits [5:4]: Pdelay_Req message Bits [7:6]: Pdelay_Resp message Bits [9:8]: User-defined message Table 6.548 PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 AQR405 Revision 0.11 - January 5, 2015 6.7.205 PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 Bit Name Description F:4 Reserved Internal reserved - do not modify 3:0 PTP Ingress 1588 Version 2 Message Type [3:0] PTP Ingress 1588 version 2 message type Type Default R/W 0xF Note IEEE 1588v2 User-defined Message Type Bit pattern to compare against the messageType field after applying the bit mask (default:0xF) Table 6.549 PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 329 6.7.206 PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:4 Reserved Internal reserved - do not modify 3:0 PTP Ingress 1588 Version 2 Message Mask [3:0] PTP Ingress 1588 version 2 message mask Type Default R/W 0xF Note IEEE 1588v2 User-defined Message Mask Bit mask to compare against the messageType field (for each bit, 1=compare, 0=ignore, default: 0xF) Table 6.550 PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 6.7.207 PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 Bit Name Description F:4 Reserved Internal reserved - do not modify 3:0 PTP Ingress Packet IFG Threshold [3:0] PTP Ingress packet IFG threshold Type Default R/W 0x0 Note PTP packet IFG threshold (default: 0x0) This is used in 1G or 100M mode to insert extra idle during IFG. This has no effect in 10G mode. Table 6.551 PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 6.7.208 PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F:8 PTP Ingress RX MAC FIFO base [7:0] PTP Ingress RX MAC FIFO Base Value R/W 0x0a When = 0, the ingress Gap FIFO is bypassed. 7:6 PTP Ingress RX MAC FIFO Correction [1:0] PTP Ingress RX MAC FIFO Correction Amount R/W 0x3 Compensates for the additional latency incurred if the MAC RX FIFO fill beyond the "base" (bits F:8) value. A value of 1 corresponds to 1ns, 2 -> 2n, 3 -> 3n, and 4 -> 4ns. 5 PTP Ingress RX MAC FIFO Correction Enable PTP Ingress RX MAC FIFO Correction Enable R/W 0 Enables the compensation 4 PTP Ingress Gap FIFO Bypass PTP Ingress Gap FIFO bypass R/W 1 When = 0, the ingress Gap FIFO is bypassed. PTP Ingress Packet Ready Threshold [3:0] PTP Ingress packet ready threshold R/W 0x2 PTP packet Ready threshold (default: 0x2) This is used in 1G or 100M mode to deassert ready when the pipeline FIFO is almost full. This has no effect in 10G mode. 3:0 Note MAC RX FIFO latency Table 6.552 PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 331 6.7.209 PCS Receive Vendor State 1: Address 3.E800 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:1 0 Name Description Reserved Internal reserved - do not modify PCS Rx Current Value of Auxilliary Bit The current value of the PCS Rx auxilliary bit Type Default RO Note This value has a maskable interrupt associated with it in 3.EC00.0. Table 6.553 PCS Receive Vendor State 1: Address 3.E800 6.7.210 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810 Bit F:0 Name CRC-8 Error Counter LSW [F:0] Description Lower 16 bits of CRC-8 error counter Type Default Note SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of CRC-8 errors (but without LDPC frame parity error) has been detected on the received LDPC frame. Table 6.554 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810 6.7.211 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:6 Reserved Internal reserved - do not modify 5:0 CRC-8 Error Counter MSW [15:10] Upper 6 bits of CRC-8 error counter Type Default SCT M 0x00 Note The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of CRC-8 errors (but without LDPC frame parity error) has been detected on the received LDPC frame. Table 6.555 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811 AQR405 Revision 0.11 - January 5, 2015 6.7.212 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 Bit F:0 Name 10GBASE-T Good Frame Counter LSW [F:0] Description Type Default 10GBASE-T Good Frame Counter LSW SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.556 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 333 6.7.213 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 10GBASE-T Good Frame Counter MSW [19:10] 10GBASE-T Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.557 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 6.7.214 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 Bit F:0 Name 10GBASE-T Error Frame Counter LSW [F:0] Description 10GBASE-T Bad Frame Counter LSW Type Default Note SCT L 0x0000 This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.558 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 6.7.215 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 10GBASE-T Error Frame Counter MSW [19:10] 10GBASE-T Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.559 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 6.7.216 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:0 Name Description Uncorrected Frame Counter LSW [F:0] Lower 16 bits of LDPC uncorrected frames which the decoder abandoned. Type Default Note SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of uncorrected frames. Table 6.560 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 6.7.217 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Description Uncorrected Frame Counter MSW [1F:10] Upper 16 bits of LDPC uncorrected frames which the decoder abandoned Type Default Note SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of uncorrected frames. Table 6.561 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 335 6.7.218 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:0 Corrected Frames 1 Iteration Counter LSW [F:0] Lower 16 bits of LDPC corrected frames which converged in 1 iteration SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of corrected frames which converged in 1 iteration. Table 6.562 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 6.7.219 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 Bit Name Description Type Default Note F:0 Corrected Frames 1 Iteration Counter MSW [1F:10] Upper 16 bits of LDPC corrected frames which converged in 1 iteration SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of corrected frames which converged in 1 iteration. Table 6.563 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 6.7.220 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:0 Corrected Frames 2 Iteration Counter LSW [F:0] Lower 16 bits of LDPC corrected frames which converged in 2 iteration SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of corrected frames which converged in 2 iteration. Table 6.564 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 6.7.221 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F:0 Corrected Frames 2 Iteration Counter MSW [1F:10] Upper 16 bits of LDPC corrected frames which converged in 2 iteration SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of corrected frames which converged in 2 iteration. Table 6.565 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 337 6.7.222 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:0 Corrected Frames 3 Iteration Counter LSW [F:0] Lower 16 bits of LDPC corrected frames which converged in 3 iteration SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of corrected frames which converged in 3 iteration. Table 6.566 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 6.7.223 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 Bit Name Description Type Default Note F:0 Corrected Frames 3 Iteration Counter MSW [1F:10] Upper 16 bits of LDPC corrected frames which converged in 3 iteration SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of corrected frames which converged in 3 iteration. Table 6.567 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 6.7.224 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:0 Corrected Frames 4 Iteration Counter LSW [F:0] Lower 16 bits of LDPC corrected frames which converged in 4 iteration SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of corrected frames which converged in 4 iteration. Table 6.568 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 6.7.225 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F:0 Corrected Frames 4 Iteration Counter MSW [1F:10] Upper 16 bits of LDPC corrected frames which converged in 4 iteration SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of corrected frames which converged in 4 iteration. Table 6.569 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 339 6.7.226 PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:0 Corrected Frames 5 Iteration Counter LSW [F:0] Lower 16 bits of LDPC corrected frames which converged in 5 iteration SCT L 0x0000 When the LSW is read, the MSW will be copied to a shadow register and then both the LSW and MSW are cleared. The LSW of the counter must be read first. The MSW of the counter must be read immediately after the LSW is read. A saturating counter that counts the number of corrected frames which converged in 5 iteration. Table 6.570 PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 6.7.227 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 Bit Name Description Type Default Note F:0 Corrected Frames 5 Iteration Counter MSW [1F:10] Upper 16 bits of LDPC corrected frames which converged in 5 iteration SCT M 0x0000 The MSW of the counter must be read immediately after the LSW of the counter is read. The MSW is actually a shadow copy of the MSW of the counter and is loaded after the LSW of the counter is read. A saturating counter that counts the number of corrected frames which converged in 5 iteration. Table 6.571 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 6.7.228 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Corrected Frames 6 Iteration Counter [F:0] LDPC corrected frames which converged in 6 iteration Type Default Note SCT 0x0000 Clear on read. A saturating counter that counts the number of corrected frames which converged in 6 iteration. Table 6.572 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 6.7.229 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:0 Corrected Frames 7 Iteration Counter [F:0] LDPC corrected frames which converged in 7 iteration Type Default Note SCT 0x0000 Clear on read. A saturating counter that counts the number of corrected frames which converged in 7 iteration. Table 6.573 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 6.7.230 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 Bit Name Description F:0 Corrected Frames 8 Iteration Counter [F:0] LDPC corrected frames which converged in 8 iteration Type Default Note SCT 0x0000 Clear on read. A saturating counter that counts the number of corrected frames which converged in 8 iteration. Table 6.574 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 341 6.7.231 PCS Receive XFI0 Vendor State 1: Address 3.E860 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name XFI0 Good Frame Counter LSW [F:0] Description XFI0 Good Frame Counter LSW Type Default SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.575 PCS Receive XFI0 Vendor State 1: Address 3.E860 6.7.232 PCS Receive XFI0 Vendor State 2: Address 3.E861 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI0 Good Frame Counter MSW [9:0] XFI0 Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.576 PCS Receive XFI0 Vendor State 2: Address 3.E861 6.7.233 PCS Receive XFI0 Vendor State 3: Address 3.E862 Bit Name F:0 XFI0 Bad Frame Counter LSW [F:0] Description XFI0 Bad Frame Counter LSW Type Default Note SCT L 0x0000 This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.577 PCS Receive XFI0 Vendor State 3: Address 3.E862 6.7.234 PCS Receive XFI0 Vendor State 4: Address 3.E863 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI0 Bad Frame Counter MSW [9:0] XFI0 Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.578 PCS Receive XFI0 Vendor State 4: Address 3.E863 6.7.235 PCS Receive XFI0 Vendor State 5: Address 3.E864 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:6 Reserved Internal reserved - do not modify 5:0 XFI0 BER Counter [5:0] XFI0 BER counter Type Default SCT 0x00 Note 10GBASE-R BER Counter[5:0] saturating clear on read Table 6.579 PCS Receive XFI0 Vendor State 5: Address 3.E864 6.7.236 PCS Receive XFI0 Vendor State 6: Address 3.E865 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XFI0 Errored Block Counter [7:0] XFI0 errored block counter Type Default SCT 0x00 Note 10GBASE-R Errored Block saturating clear on read Counter[7:0] Table 6.580 PCS Receive XFI0 Vendor State 6: Address 3.E865 343 6.7.237 PCS Receive XFI0 Vendor State 7: Address 3.E866 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name XFI0 Test Pattern Error Counter [F:0] Description XFI0 test pattern error counter Type Default Note SCT 0x0000 10GBASE-R Test Pattern Error Counter[15:0] saturating clear on read Table 6.581 PCS Receive XFI0 Vendor State 7: Address 3.E866 6.7.238 PCS Receive XFI1 Vendor State 1: Address 3.E870 Bit F:0 Name XFI1 Good Frame Counter LSW [F:0] Description XFI1 Good Frame Counter LSW Type Default SCT L 0x0000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.582 PCS Receive XFI1 Vendor State 1: Address 3.E870 6.7.239 PCS Receive XFI1 Vendor State 2: Address 3.E871 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 XFI1 Good Frame Counter MSW [9:0] XFI1 Good Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.583 PCS Receive XFI1 Vendor State 2: Address 3.E871 6.7.240 PCS Receive XFI1 Vendor State 3: Address 3.E872 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name F:0 XFI1 Bad Frame Counter LSW [F:0] Description XFI1 Bad Frame Counter LSW Type Default Note SCT L 0x0000 This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.584 PCS Receive XFI1 Vendor State 3: Address 3.E872 6.7.241 PCS Receive XFI1 Vendor State 4: Address 3.E873 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:A Reserved Internal reserved - do not modify 9:0 XFI1 Bad Frame Counter MSW [9:0] XFI1 Bad Frame Counter MSW Type Default SCT M 0x000 Note This counts Ethernet bad frames (i.e. Ethernet CRC-32 / FCS errors). Table 6.585 PCS Receive XFI1 Vendor State 4: Address 3.E873 6.7.242 PCS Receive XFI1 Vendor State 5: Address 3.E874 Bit Name Description F:6 Reserved Internal reserved - do not modify 5:0 XFI1 BER Counter [5:0] XFI1 BER counter Type Default SCT 0x00 Note 10GBASE-R BER Counter[5:0] saturating clear on read Table 6.586 PCS Receive XFI1 Vendor State 5: Address 3.E874 345 6.7.243 PCS Receive XFI1 Vendor State 6: Address 3.E875 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 XFI1 Errored Block Counter [7:0] XFI1 errored block counter Type Default SCT 0x00 Note 10GBASE-R Errored Block saturating clear on read Counter[7:0] Table 6.587 PCS Receive XFI1 Vendor State 6: Address 3.E875 6.7.244 PCS Receive XFI1 Vendor State 7: Address 3.E876 Bit F:0 Name XFI1 Test Pattern Error Counter [F:0] Description XFI1 test pattern error counter Type Default Note SCT 0x0000 10GBASE-R Test Pattern Error Counter[15:0] saturating clear on read Table 6.588 PCS Receive XFI1 Vendor State 7: Address 3.E876 6.7.245 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 Bit F:0 Name USX0 Header CRC Error Counter [F:0] Description Rx Header CRC error counter Type Default Note SCT 0x0000 This register is a 16-bit saturating clear on read counter for USXGMII Header CRC error Table 6.589 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 6.7.246 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:0 Name USX0 Packet Information Message to be injected 15:0 [F:0] Description Packet Information Message to be injected15:0 Type Default RO Note Rx Packet Information message bit's 15:0 Table 6.590 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 6.7.247 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 USX0 Packet Information Message to be injected 31:16 [1F:10] Description Packet Information Message to be injected 31:16 Type Default RO Note Rx Packet Information message bit's 31:16 Table 6.591 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 6.7.248 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 Bit F:0 Name USX0 Packet Information Message to be injected 47:32 [2F:20] Description Packet Information Message to be injected 47:32 Type RO Default Note Rx Packet Information message bit's 47:32 Table 6.592 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 347 6.7.249 PCS USX0 Unidata and SM status Register: Address 3.E8D4 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:6 Reserved Internal reserved - do not modify 5:4 USX0 Rx_Unidata Indication[1:0] Rx_Unidata Indication (0=None, 1=Invalid, 2=Idle, 3=Config) Reserved Internal reserved - do not modify USX0 SAN State Machine current state[2:0] SAN State Machine current state 3 2:0 Type Default Note RO RO Table 6.593 PCS USX0 Unidata and SM status Register: Address 3.E8D4 6.7.250 PCS USX0 Receive Status Register: Address 3.E8D5 Bit Name Description Type F:8 Reserved Internal reserved - do not modify 7:4 USX0 Rx Rsvd Status[3:0] USX0 Rx Reserved Status BLH 3:0 USX0 XGMII to GMII conversion Status[3:0] XGMII to GMII/MII Conversion Status Bit 0: Detect Rx min IFG error Bit 1: Detect Rx Signal Ordered_set Bits 2-3: Reserved BLH Default Table 6.594 PCS USX0 Receive Status Register: Address 3.E8D5 Note 6.7.251 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 USX0 Link Partner Advertisement Status USX0 Link Partner advertisement status. 0 = Link down 1 = Link up RO Reserved USX0 Link Partner Advertisement 0 [1:0] Reserved for future use. RO C USX0 Link Partner Advertisement Duplex USX0 Link Partner advertisement duplex. 0 = Half duplex 1 = Full duplex RO B:9 USX0 Link Partner Advertisement Speed [2:0] USX0 Link Partner advertisement speed. 0 = 10M 1 = 100M 2 = 1G 3 = 10G 4 = 2.5G 5 = 5G RO 8 USX0 Link Partner Advertisement EEE Capability USX0 Link Partner advertisement EEE capability. 0 = Not supported 1 = Supported RO F E:D Default Note Table 6.595 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 349 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description 7 USX0 Link Partner Advertisement EEE Clock Stop Capability USX0 Link Partner advertisement EEE Clock Stop capability. 0 = Not supported 1 = Supported RO 6:1 Reserved USX0 Link Partner Advertisement 1 [5:0] Reserved for future use. RO USX0 Link Partner Advertisement Mode USX0 Link Partner advertisement mode. 0 = SGMII 1 = USXGMII RO 0 Type Default Note Table 6.595 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 6.7.252 PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 Bit F:0 Name USX1 Header CRC Error Counter [F:0] Description Rx Header CRC error counter Type Default Note SCT 0x0000 This register is a 16-bit saturating clear on read counter for USXGMII Header CRC error Table 6.596 PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 6.7.253 PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:0 Name USX1 Packet Information Message to be injected 15:0 [F:0] Description Packet Information Message to be injected15:0 Type Default RO Note Rx Packet Information message bit's 15:0 Table 6.597 PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 6.7.254 PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 USX1 Packet Information Message to be injected 31:16 [1F:10] Description Packet Information Message to be injected 31:16 Type Default RO Note Rx Packet Information message bit's 31:16 Table 6.598 PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 6.7.255 PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 Bit F:0 Name USX1 Packet Information Message to be injected 47:32 [2F:20] Description Packet Information Message to be injected 47:32 Type RO Default Note Rx Packet Information message bit's 47:32 Table 6.599 PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 351 6.7.256 PCS USX1 Unidata and SM status Register: Address 3.E8E4 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:6 Reserved Internal reserved - do not modify 5:4 USX1 Rx_Unidata Indication[1:0] Rx_Unidata Indication (0=None, 1=Invalid, 2=Idle, 3=Config) Reserved Internal reserved - do not modify USX1 SAN State Machine current state[2:0] SAN State Machine current state 3 2:0 Type Default Note RO RO Table 6.600 PCS USX1 Unidata and SM status Register: Address 3.E8E4 6.7.257 PCS USX1 Receive Status Register: Address 3.E8E5 Bit Name Description Type F:8 Reserved Internal reserved - do not modify 7:4 USX1 Rx Rsvd Status[3:0] USX1 Rx Reserved Status BLH 3:0 USX1 XGMII to GMII conversion Status[3:0] XGMII to GMII/MII Conversion Status Bit 0: Detect Rx min IFG error Bit 1: Detect Rx Signal Ordered_set Bits 2-3: Reserved BLH Default Table 6.601 PCS USX1 Receive Status Register: Address 3.E8E5 Note 6.7.258 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 USX1 Link Partner Advertisement Status USX1 Link Partner advertisement status. 0 = Link down 1 = Link up RO Reserved USX1 Link Partner Advertisement 0 [1:0] Reserved for future use. RO C USX1 Link Partner Advertisement Duplex USX1 Link Partner advertisement duplex. 0 = Half duplex 1 = Full duplex RO B:9 USX1 Link Partner Advertisement Speed [2:0] USX1 Link Partner advertisement speed. 0 = 10M 1 = 100M 2 = 1G 3 = 10G 4 = 2.5G 5 = 5G RO 8 USX1 Link Partner Advertisement EEE Capability USX1 Link Partner advertisement EEE capability. 0 = Not supported 1 = Supported RO F E:D Default Note Table 6.602 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 353 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description 7 USX1 Link Partner Advertisement EEE Clock Stop Capability USX1 Link Partner advertisement EEE Clock Stop capability. 0 = Not supported 1 = Supported RO 6:1 Reserved USX1 Link Partner Advertisement 1 [5:0] Reserved for future use. RO USX1 Link Partner Advertisement Mode USX1 Link Partner advertisement mode. 0 = SGMII 1 = USXGMII RO 0 Type Default Note Table 6.602 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 6.7.259 PCS Receive Vendor Alarms 1: Address 3.EC00 Bit Name Description Type Default Note F CRC Error 1 = Rx CRC Frame error LH This bit is set when a CRC-8 error is detected on the receive PCS frame. E LDPC Decode Failure 1 = LDPC decode failure LH This bit is set when the LDPC decoder fails to decode an LDPC block. Reserved Internal reserved - do not modify B Local Fault Detect 1 = RPL local fault detect LH Local_Fault Interrupt A LOF Detect 1 = RPL LOF detect LH LOF Detection Interrupt D:C Table 6.603 PCS Receive Vendor Alarms 1: Address 3.EC00 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 9 40G BIP Lock 1 = RPL 40G BIP lock LH Indicates the 40G BIP checker has achieved lock to the alignment marker 8 Invalid 65B Block 1 = Invalid Rx 65B block received in PCS transmission frame LH This bit is set when an invalid 65B block (but without LDPC frame parity error) has been detected on the received LDPC frame. 7 EEE Rx LPI Active Off 1 = EEE Rx LPI Active Off LL 6 EEE Rx LPI Active On 1 = EEE Rx LPI Active On LH 5 LDPC Consecutive Errored Frame Exceeded 1 = Rx PCS LDPC consecutive errored frame threshold exceeded LH Indicates the consecutive LDPC errored frame has exceeded the threshold. 4 EEE Rx LPI Alert 1 = Rx PCS received alert indication LH Indicate Rx PCS received alert indication 3 EEE Rx LPI Received Latched Low 1 = Rx LPI has been detected LL Indicate LPI ordered-set is detected 2 EEE Rx LPI Received Latched High 1 = Rx LPI has been detected LH Indicate LPI ordered-set is detected 1 Reserved Internal reserved - do not modify 0 Change in Auxilliary Bit 1 = Indicates a change in the value of the auxilliary bit LRF This bit is set when a change is detected in the auxilliary bit. Table 6.603 PCS Receive Vendor Alarms 1: Address 3.EC00 355 6.7.260 PCS Receive Vendor Alarms 2: Address 3.EC01 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.604 PCS Receive Vendor Alarms 2: Address 3.EC01 6.7.261 PCS Receive Vendor Alarms 3: Address 3.EC02 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.605 PCS Receive Vendor Alarms 3: Address 3.EC02 6.7.262 PCS Receive Vendor Alarms 4: Address 3.EC03 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.606 PCS Receive Vendor Alarms 4: Address 3.EC03 6.7.263 PCS Receive Vendor Alarms 5: Address 3.EC04 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.607 PCS Receive Vendor Alarms 5: Address 3.EC04 Note 6.7.264 PCS Receive Vendor Alarms 6: Address 3.EC05 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:C B A:4 3 2:0 Name Description Reserved Internal reserved - do not modify XFI1 Invalid 66B Character Received 1 = XFI1 Receive invalid 66B character received Reserved Internal reserved - do not modify XFI0 Invalid 66B Character Received 1 = XFI0 Receive invalid 66B character received Reserved Internal reserved - do not modify Type Default Note LH Invalid 66B code error LH Invalid 66B code error Table 6.608 PCS Receive Vendor Alarms 6: Address 3.EC05 AQR405 Revision 0.11 - January 5, 2015 6.7.265 PCS Receive Vendor Alarms 7: Address 3.EC06 Bit F:8 Name Description Type Reserved Internal reserved - do not modify 7 XFI1 Receive Link Status Latch High Status of the XFI1 receive link 6 Reserved Internal reserved - do not modify 5 XFI1 High BER Status 1 = XFI1 High BER condition LH 4 XFI1 Block Lock Status 1 = XFI1 Block Lock condition LL LH Default Note This indicates the status of the XFI1 receive link. 357 Table 6.609 PCS Receive Vendor Alarms 7: Address 3.EC06 Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 3 XFI0 Receive Link Status Latch High Status of the XFI0 receive link 2 Reserved Internal reserved - do not modify 1 XFI0 High BER Status 1 = XFI0 High BER condition LH 0 XFI0 Block Lock Status 1 = XFI0 Block Lock condition LL Default LH Note This indicates the status of the XFI0 receive link. Table 6.609 PCS Receive Vendor Alarms 7: Address 3.EC06 6.7.266 PCS Receive Vendor Alarms 10: Address 3.EC09 Bit F:C Name Description Type Default Note Reserved Internal reserved - do not modify B PTP Ingress Packet Ready FIFO Error 1 = PTP Ingress packet ready FIFO error LH Asserted when PTP packet ready FIFO has detected FIFO error A PTP Ingress Packet Ready FIFO Parity Error 1 = PTP Ingress packet ready FIFO parity error LH Asserted when PTP packet ready FIFO has detected parity error 9 PTP Ingress Packet Remove Error 1 = PTP Ingress packet remove error LH Asserted when the packet length is too long for the UDP checksum to be updated during removal of the timestamp appended at the end of packet. When this happens, the UDP checksum will be set to all-zeroes. 8 PTP Ingress Packet Received 1 = PTP Ingress packet received LH Asserted when a valid PTP packet has been received. This can be used as the valid signal for the received PTP packet information. Table 6.610 PCS Receive Vendor Alarms 10: Address 3.EC09 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 7 PTP Ingress Packet Pipeline FIFO Error 1 = PTP Ingress packet pipeline FIFO error detected LH Asserted when PTP detected parity error packet buffer has 6 PTP Ingress Packet Pipeline Parity Error 1 = PTP Ingress packet pipeline parity error detected LH Asserted when PTP timestamp buffer has detected parity error 5 PTP Ingress Time Stamp Buffer Parity Error 1 = PTP Ingress time stamp buffer parity error detected LH Asserted when PTP packet pipeline has detected parity error 4 PTP Ingress Packet Buffer Parity Error 1 = PTP Ingress packet buffer parity error detected LH Asserted when PTP packet pipeline has detected FIFO error 3 PTP Ingress Packet Correction Field Error 1 = PTP Ingress packet correction field error LH Asserted when the packet length is too long for the Correction field to be updated due to the ingress timestamp appended at the end of packet. This shall not happen for IEEE1588v2 compliant packets. But when this happens, the Correction field will not be changed. 2 PTP Ingress Packet Buffer Overflow Error 1 = PTP Ingress packet buffer overflow error detected LH Asserted when PTP packet has not been captured because the buffer was full 1 PTP Ingress Time Stamp Ready 1 = PTP Ingress packet time stamp ready RO Asserted when PTP packet timestamp has captured. It will be cleared when the timestamp buffer is empty 0 PTP Ingress Packet Ready 1 = PTP Ingress packet ready RO Asserted when PTP packet has captured. It will be cleared when the buffer is empty Table 6.610 PCS Receive Vendor Alarms 10: Address 3.EC09 359 6.7.267 PCS Receive Vendor Alarms 14: Address 3.EC0D AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type F Reserved Internal reserved - do not modify E USX0 Rx Header CRC Error Detect Rx Header CRC Error LH D USX0 Rx USXGMII Local_Fault Detect Rx USXGMII Local_Fault LH C USX0 Link FIFO Overflow Error Link FIFO Overflow Error LH B USX0 Link FIFO Underflow Error Link FIFO Underflow Error LH A USX0 Link FIFO Parity Error Link FIFO Parity Error LH 9 USX0 RX Packet Info Message Indicate the received Packet Information Message has changed. LH 8 USX0 MAC Rx FIFO Parity Error MAC Rx FIFO Parity Error LH 7 USX0 MAC Rx FIFO Overflow Err MAC Rx FIFO Overflow Error LH Default Table 6.611 PCS Receive Vendor Alarms 14: Address 3.EC0D Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 6 USX0 MAC Rx FIFO Underflow Err MAC Rx FIFO Underflow Error LH 5 USX0 MAC Rx FIFO Idle deletion MAC Rx FIFO Idle deletion LH 4 USX0 MAC Tx FIFO Parity Err MAC Tx FIFO Parity Error LH 3 USX0 MAC Tx FIFO Overflow MAC Tx FIFO Overflow Error LH 2 USX0 MAC Tx FIFO Underflow MAC Tx FIFO Underflow Error LH 1 USX0 MAC Tx SFD Error MAC Tx SFD Error LH 0 USX0 MAC Tx FIFO Idle insertion MAC Tx FIFO Idle insertion LH Default Note Table 6.611 PCS Receive Vendor Alarms 14: Address 3.EC0D 6.7.268 PCS Receive Vendor Alarms 15: Address 3.EC0E Bit Name Description F Reserved Internal reserved - do not modify E USX1 Rx Header CRC Error Detect Rx Header CRC Error Type Default Note LH 361 Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E Bit Name Description Type Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 D USX1 Rx USXGMII Local_Fault Detect Rx USXGMII Local_Fault LH C USX1 Link FIFO Overflow Error Link FIFO Overflow Error LH B USX1 Link FIFO Underflow Error Link FIFO Underflow Error LH A USX1 Link FIFO Parity Error Link FIFO Parity Error LH 9 USX1 RX Packet Info Message Indicate the received Packet Information Message has changed. LH 8 USX1 MAC Rx FIFO Parity Error MAC Rx FIFO Parity Error LH 7 USX1 MAC Rx FIFO Overflow Err MAC Rx FIFO Overflow Error LH 6 USX1 MAC Rx FIFO Underflow Err MAC Rx FIFO Underflow Error LH 5 USX1 MAC Rx FIFO Idle deletion MAC Rx FIFO Idle deletion LH 4 USX1 MAC Tx FIFO Parity Err MAC Tx FIFO Parity Error LH Default Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E Note Bit Name Description Type Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 3 USX1 MAC Tx FIFO Overflow MAC Tx FIFO Overflow Error LH 2 USX1 MAC Tx FIFO Underflow MAC Tx FIFO Underflow Error LH 1 USX1 MAC Tx SFD Error MAC Tx SFD Error LH 0 USX1 MAC Tx FIFO Idle insertion MAC Tx FIFO Idle insertion LH Default Note Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E 6.7.269 PCS Receive Vendor Alarms 16: Address 3.EC0F AQR405 Revision 0.11 - January 5, 2015 Bit F:B Name Description Type Reserved Internal reserved - do not modify A USX0 Auto Neg Complete Latch Low Auto-Negotiation complete LL 9 USX0 Auto Neg Complete Latch High Auto-Negotiation complete LH 8 USX0 AN State Machine Interrupt Auto-Negotiation State Machine Interrupt LH 7 USX0 RX Unidata Config Change Rx_Unidata or Rx_Config_Reg (Link partner advertisement register) change LH Default 363 Table 6.613 PCS Receive Vendor Alarms 16: Address 3.EC0F Note Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 6 USX0 Invocation of the priority resolution function Invocation of the priority resolution function LH 5 USX0 Link Timer Done Link Timer Done LH 4 USX0 Ability match indication Ability match indication LH 3 USX0 Acknowledgeme nt match indication Acknowledgement match indication LH 2 USX0 Consistency match indication Consistency match indication LH 1 USX0 Idle Match Indication Idle Match Indication LH 0 USX0 Link Partner Adv Change Link partner advertisement register change LH Default Table 6.613 PCS Receive Vendor Alarms 16: Address 3.EC0F Note 6.7.270 PCS Receive Vendor Alarms 17: Address 3.EC10 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:B Name Description Type AQR405 Revision 0.11 - January 5, 2015 Internal reserved - do not modify A USX1 Auto Neg Complete Latch Low Auto-Negotiation complete LL 9 USX1 Auto Neg Complete Latch High Auto-Negotiation complete LH 8 USX1 AN State Machine Interrupt Auto-Negotiation State Machine Interrupt LH 7 USX1 RX Unidata Config Change Rx_Unidata or Rx_Config_Reg (Link partner advertisement register) change LH 6 USX1 Invocation of the priority resolution function Invocation of the priority resolution function LH 5 USX1 Link Timer Done Link Timer Done LH 4 USX1 Ability match indication Ability match indication LH 3 USX1 Acknowledgeme nt match indication Acknowledgement match indication LH Table 6.614 PCS Receive Vendor Alarms 17: Address 3.EC10 Note 365 Reserved Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type 2 USX1 Consistency match indication Consistency match indication LH 1 USX1 Idle Match Indication Idle Match Indication LH 0 USX1 Link Partner Adv Change Link partner advertisement register change LH Default Note Table 6.614 PCS Receive Vendor Alarms 17: Address 3.EC10 6.7.271 PCS Receive Vendor Internal Alarms : Address 3.ED0D Bit Name Description Type F Reserved Internal reserved - do not modify E USX0 Rx Header CRC Error Detect Rx Header CRC Error LH D USX0 Rx USXGMII Local_Fault Detect Rx USXGMII Local_Fault LH C USX0 Link FIFO Overflow Error Link FIFO Overflow Error LH B USX0 Link FIFO Underflow Error Link FIFO Underflow Error LH A USX0 Link FIFO Parity Error Link FIFO Parity Error LH Default Table 6.615 PCS Receive Vendor Internal Alarms : Address 3.ED0D Note Bit Name Description Type Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 9 USX0 RX Packet Info Message Indicate the received Packet Information Message has changed. LH 8 USX0 MAC Rx FIFO Parity Error MAC Rx FIFO Parity Error LH 7 USX0 MAC Rx FIFO Overflow Err MAC Rx FIFO Overflow Error LH 6 USX0 MAC Rx FIFO Underflow Err MAC Rx FIFO Underflow Error LH 5 USX0 MAC Rx FIFO Idle deletion MAC Rx FIFO Idle deletion LH 4 USX0 MAC Tx FIFO Parity Err MAC Tx FIFO Parity Error LH 3 USX0 MAC Tx FIFO Overflow MAC Tx FIFO Overflow Error LH 2 USX0 MAC Tx FIFO Underflow MAC Tx FIFO Underflow Error LH 1 USX0 MAC Tx SFD Error MAC Tx SFD Error LH 0 USX0 MAC Tx FIFO Idle insertion MAC Tx FIFO Idle insertion LH Default Note Table 6.615 PCS Receive Vendor Internal Alarms : Address 3.ED0D 367 6.7.272 PCS Receive Vendor Internal Alarms : Address 3.ED0E AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type F Reserved Internal reserved - do not modify E USX1 Rx Header CRC Error Detect Rx Header CRC Error LH D USX1 Rx USXGMII Local_Fault Detect Rx USXGMII Local_Fault LH C USX1 Link FIFO Overflow Error Link FIFO Overflow Error LH B USX1 Link FIFO Underflow Error Link FIFO Underflow Error LH A USX1 Link FIFO Parity Error Link FIFO Parity Error LH 9 USX1 RX Packet Info Message Indicate the received Packet Information Message has changed. LH 8 USX1 MAC Rx FIFO Parity Error MAC Rx FIFO Parity Error LH 7 USX1 MAC Rx FIFO Overflow Err MAC Rx FIFO Overflow Error LH Default Table 6.616 PCS Receive Vendor Internal Alarms : Address 3.ED0E Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 6 USX1 MAC Rx FIFO Underflow Err MAC Rx FIFO Underflow Error LH 5 USX1 MAC Rx FIFO Idle deletion MAC Rx FIFO Idle deletion LH 4 USX1 MAC Tx FIFO Parity Err MAC Tx FIFO Parity Error LH 3 USX1 MAC Tx FIFO Overflow MAC Tx FIFO Overflow Error LH 2 USX1 MAC Tx FIFO Underflow MAC Tx FIFO Underflow Error LH 1 USX1 MAC Tx SFD Error MAC Tx SFD Error LH 0 USX1 MAC Tx FIFO Idle insertion MAC Tx FIFO Idle insertion LH Default Note Table 6.616 PCS Receive Vendor Internal Alarms : Address 3.ED0E 6.7.273 PCS Receive Vendor Internal Alarms : Address 3.ED0F Bit F:B A Name Description Reserved Internal reserved - do not modify USX0 Auto Neg Complete Latch Low Auto-Negotiation complete Type Default Note LL Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F 369 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 9 USX0 Auto Neg Complete Latch High Auto-Negotiation complete LH 8 USX0 AN State Machine Interrupt Auto-Negotiation State Machine Interrupt LH 7 USX0 RX Unidata Config Change Rx_Unidata or Rx_Config_Reg (Link partner advertisement register) change LH 6 USX0 Invocation of the priority resolution function Invocation of the priority resolution function LH 5 USX0 Link Timer Done Link Timer Done LH 4 USX0 Ability match indication Ability match indication LH 3 USX0 Acknowledgeme nt match indication Acknowledgement match indication LH 2 USX0 Consistency match indication Consistency match indication LH Default Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type 1 USX0 Idle Match Indication Idle Match Indication LH 0 USX0 Link Partner Adv Change Link partner advertisement register change LH Default Note Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F 6.7.274 PCS Receive Vendor Internal Alarms : Address 3.ED10 Bit F:B Name Description Type AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify A USX1 Auto Neg Complete Latch Low Auto-Negotiation complete LL 9 USX1 Auto Neg Complete Latch High Auto-Negotiation complete LH 8 USX1 AN State Machine Interrupt Auto-Negotiation State Machine Interrupt LH 7 USX1 RX Unidata Config Change Rx_Unidata or Rx_Config_Reg (Link partner advertisement register) change LH 6 USX1 Invocation of the priority resolution function Invocation of the priority resolution function LH Default 371 Table 6.618 PCS Receive Vendor Internal Alarms : Address 3.ED10 Note Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 5 USX1 Link Timer Done Link Timer Done LH 4 USX1 Ability match indication Ability match indication LH 3 USX1 Acknowledgeme nt match indication Acknowledgement match indication LH 2 USX1 Consistency match indication Consistency match indication LH 1 USX1 Idle Match Indication Idle Match Indication LH 0 USX1 Link Partner Adv Change Link partner advertisement register change LH Default Note Table 6.618 PCS Receive Vendor Internal Alarms : Address 3.ED10 6.7.275 PCS Receive Vendor Interrupt Mask 1: Address 3.F400 Bit Name F CRC Error Mask E D:C Description Type Default Note 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 This bit is set when a CRC-8 error is detected on the receive PCS frame. LDPC Decode Failure Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 This bit is set when the LDPC decoder fails to decode an LDPC block. Reserved Internal reserved - do not modify Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400 Bit Name Description Type Default Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 B Local Fault Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 A LOF Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 9 40G BIP Lock Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 8 Invalid 65B Block Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 7 EEE Rx LPI Active Off Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 6 EEE Rx LPI Active On Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 5 LDPC Consecutive Errored Frame Exceeded Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 4 EEE Rx LPI Alert Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 3 EEE Rx LPI Received Latched Low Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note This bit is set when an invalid 65B block (but without LDPC frame parity error) has been detected on the received LDPC frame. Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400 373 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 2 EEE Rx LPI Received Latched High Mask 1 = Enable interrupt generation 0 = Disable interrupt generation 1 Reserved Internal reserved - do not modify 0 Change in Auxilliary Bit Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0 R/W PD 0 Note This bit is set when a change is detected in the auxilliary bit. Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400 6.7.276 PCS Receive Vendor Interrupt Mask 2: Address 3.F401 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.620 PCS Receive Vendor Interrupt Mask 2: Address 3.F401 6.7.277 PCS Receive Vendor Interrupt Mask 3: Address 3.F402 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.621 PCS Receive Vendor Interrupt Mask 3: Address 3.F402 6.7.278 PCS Receive Vendor Interrupt Mask 4: Address 3.F403 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.622 PCS Receive Vendor Interrupt Mask 4: Address 3.F403 Note 6.7.279 PCS Receive Vendor Interrupt Mask 5: Address 3.F404 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.623 PCS Receive Vendor Interrupt Mask 5: Address 3.F404 6.7.280 PCS Receive Vendor Interrupt Mask 6: Address 3.F405 Bit F:C B AQR405 Revision 0.11 - January 5, 2015 A:4 3 2:0 Name Description Reserved Internal reserved - do not modify XFI1 Invalid 66B Character Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify XFI0 Invalid 66B Character Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify Type Default R/W PD 0 R/W PD 0 Note Table 6.624 PCS Receive Vendor Interrupt Mask 6: Address 3.F405 375 6.7.281 PCS Receive Vendor Interrupt Mask 7: Address 3.F406 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:8 Name Description Type Default R/W PD 0 Reserved Internal reserved - do not modify 7 XFI1 Receive Link Status Latch High Mask 1 = Enable interrupt generation 0 = Disable interrupt generation 6 Reserved Internal reserved - do not modify 5 XFI1 High BER Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 4 XFI1 Block Lock Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 3 XFI0 Receive Link Status Latch High Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 2 Reserved Internal reserved - do not modify 1 XFI0 High BER Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 XFI0 Block Lock Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.625 PCS Receive Vendor Interrupt Mask 7: Address 3.F406 Note 6.7.282 PCS Receive Vendor Debug 1: Address 3.F800 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F Name Description Type Default Note R/W PD 0 Setting this bit disables the Rx descrambler during regular data transmission (i.e. descrambler functionality during training and startup is unmodified). AQR405 Revision 0.11 - January 5, 2015 PCS Rx Descrambler Disable 1 = Rx Descrambler Disabled 0 = Normal Operation Reserved Internal reserved - do not modify 2 PCS Network Loopback Merge When set to 1, XAUI data from the local MAC and PCS Network Loopback data will be merged. R/W PD 1 If the MAC sends data, it will take priority over the PCS Network Loopback data. The loopback data will be dropped. 1 PCS Network Loopback Pass Through When set to 1, this bit enables loopback traffic from the PCS Network Loopback to pass-through towards the System XAUI side. When set to 0, the data sent towards the system XUAI will be an IDLE ordered set data stream when in PCS Network Loopback R/W PD 1 This enables traffic to pass through as well as loopback when the PCS Network Loopback is enabled. 0 PCS Network Loopback When set to 1, data after the Rx PCS layer will be looped back to the Tx PCS layer and transmitted back towards the network UTP line. R/W PD 0 E:3 Table 6.626 PCS Receive Vendor Debug 1: Address 3.F800 377 6.7.283 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F Standard Alarm 1 Interrupt 1 = Interrupt in standard alarms 1 RO An interrupt was generated from status register (See "PCS Standard Status 1: Address 3.1" on page 229.) and the corresponding mask register (See "PCS Standard Interrupt Mask 1: Address 3.D000" on page 294.). E Standard Alarm 2 Interrupt 1 = Interrupt in standard alarms 2 RO An interrupt was generated from status register (See "PCS Standard Status 2: Address 3.8" on page 233.) and the corresponding mask register (See "PCS Standard Interrupt Mask 2: Address 3.D001" on page 295.). D Standard Alarm 3 Interrupt 1 = Interrupt in standard alarms 3 RO An interrupt was generated from status register (See "PCS 10G Status 2: Address 3.21" on page 237.) and the corresponding mask register (See "PCS Standard Interrupt Mask 3: Address 3.D002" on page 296.). C Reserved Internal reserved - do not modify B Vendor Specific Tx Alarms 1 Interrupt 1 = Interrupt in vendor specific Tx alarms 1 RO An interrupt was generated from status register (See "PCS Transmit Vendor Alarms 1: Address 3.CC00" on page 292.) and the corresponding mask register (See "PCS Transmit Vendor Interrupt Mask 1: Address 3.D400" on page 296.). A Vendor Specific Tx Alarms 2 Interrupt 1 = Interrupt in vendor specific Tx alarms 2 RO An interrupt was generated from status register (See "PCS Transmit Vendor Alarms 2: Address 3.CC01" on page 293.) and the corresponding mask register (See "PCS Transmit Vendor Interrupt Mask 2: Address 3.D401" on page 297.). Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description 9 Vendor Specific Tx Alarms 3 Interrupt 1 = Interrupt in vendor specific Tx alarms 3 Reserved Internal reserved - do not modify 6 Vendor Specific Rx Alarms 1 Interrupt 5 Type Default Note AQR405 Revision 0.11 - January 5, 2015 RO An interrupt was generated from status register (See "PCS Transmit Vendor Alarms 3: Address 3.CC02" on page 293.) and the corresponding mask register (See "PCS Transmit Vendor Interrupt Mask 3: Address 3.D402" on page 297.). 1 = Interrupt in vendor specific Rx alarms 1 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 1: Address 3.EC00" on page 354.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 1: Address 3.F400" on page 372.). Vendor Specific Rx Alarms 2 Interrupt 1 = Interrupt in vendor specific Rx alarms 2 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 2: Address 3.EC01" on page 356.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 2: Address 3.F401" on page 374.). 4 Vendor Specific Rx Alarms 3 Interrupt 1 = Interrupt in vendor specific Rx alarms 3 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 3: Address 3.EC02" on page 356.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 3: Address 3.F402" on page 374.). 3 Vendor Specific Rx Alarms 4 Interrupt 1 = Interrupt in vendor specific Rx alarms 4 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 4: Address 3.EC03" on page 356.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 4: Address 3.F403" on page 374.). 8:7 379 Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name 2 Vendor Specific Rx Alarms 5 Interrupt 1 = Interrupt in vendor specific Rx alarms 5 Reserved Internal reserved - do not modify 1:0 Description Type Default RO Note An interrupt was generated from status register (See "PCS Receive Vendor Alarms 5: Address 3.EC04" on page 356.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 5: Address 3.F404" on page 375.). Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00 6.7.284 PCS Vendor Global Interrupt Flags 3: Address 3.FC02 Bit F:8 Name Description Type Default Note Reserved Internal reserved - do not modify 7 Vendor Specific Rx Alarms 6 Interrupt 1 = Interrupt in vendor specific Rx alarms 6 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 6: Address 3.EC05" on page 357.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 6: Address 3.F405" on page 375.). 6 Vendor Specific Rx Alarms 7 Interrupt 1 = Interrupt in vendor specific Rx alarms 7 RO An interrupt was generated from status register (See "PCS Receive Vendor Alarms 7: Address 3.EC06" on page 357.) and the corresponding mask register (See "PCS Receive Vendor Interrupt Mask 7: Address 3.F406" on page 376.). Reserved Internal reserved - do not modify 5:0 Table 6.628 PCS Vendor Global Interrupt Flags 3: Address 3.FC02 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8 PHY XS Registers 6.8.1 PHY XS Standard Control 1: Address 4.0 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F Reset 1 = PHY XS reset 0 = Normal operation R/W SC 1 Resets the entire PHY. The reset bit is automatically cleared upon completion of the reset sequence by the microcontroller. This bit is set to 1 during reset. The reset is internally stretched by approximately 1.7 us. Therefore the MDIO or uP should allow for 1.7 us before writing any PHY XS registers after this bit is set. E Loopback 1 = System Interface Network Loopback 0 = Normal operation R/W 0 This enables network loopback on the designated system interface. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F D Speed Selection 0 1 = 10Gb/s and above 0 = Unspecified C Reserved Internal reserved - do not modify B Low Power 1 = Low-power mode 0 = Normal operation ROS 1 This should always be set to 1 R/W 0 A one written to this register causes the PHY XS to enter low-power mode. If a global chip low-power state is desired, use Bit B in "Global Standard Control 1: Address 1E.0" should be set. Table 6.629 PHY XS Standard Control 1: Address 4.0 381 NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name A Clock Stop Enable 9 Type Default 1 = The PHY XS may stop the clock during LPI 0 = Clock not stoppable R/W 0 XAUI Stop Enable 1 = The PHY XS may stop XAUI signals during LPI 0 = XAUI not stoppable R/W 0 Reserved Internal reserved - do not modify 6 Speed Selection 1 1 = 10Gb/s and above 0 = Unspecified ROS 1 This should always be set to 1 5:2 Speed Selection 2 [3:0] 1 x x x = Reserved x 1 x x = Reserved x x 1 x = Reserved x x x 1 = Reserved 0 0 0 0 = 10 Gb/s ROS 0x0 This should always be set to 0 1:0 Reserved Internal reserved - do not modify 8:7 Description Note Table 6.629 PHY XS Standard Control 1: Address 4.0 6.8.2 PHY XS Standard Status 1: Address 4.1 Bit Name Description Type Default Note Reserved Internal reserved - do not modify B Tx LPI Received 1 = Tx PHY XS has received LPI 0 = LPI not received LH The source of the LPI signal is configured in 1E.C4A2.3:0. A Rx LPI Received 1 = Rx PHY XS has received LPI 0 = LPI not received LH The source of the LPI signal is configured in 1E.C4A2.3:0. F:C Table 6.630 PHY XS Standard Status 1: Address 4.1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description 9 Tx LPI Indication 1 = Tx PHY XS is currently receiving LPI 0 = Tx PHY XS is not currently receiving LPI RO The source of the LPI signal is configured in 1E.C4A2.3:0. 8 Rx LPI Indication 1 = Rx PHY XS is currently receiving LPI 0 = Rx PHY XS is not currently receiving LPI RO The source of the LPI signal is configured in 1E.C4A2.3:0. 7 Fault 1 = Fault condition detected 0 = No fault detected RO This is the top-level fault indicator flag for the PHY XS (aka XAUI) block, This bit is set if either of the two bits 4.8.B or 4.8.A are set. 6 Clock Stop Capable 1 = The attached PHY may stop the clock during LPI 0 = Clock not stoppable ROS 5:3 Reserved Internal reserved - do not modify PHY XS Transmit Link Alignment Status Status of receive XAUI interface alignment: 1 Low Power Ability 1 = PHY XS supports low-power mode 0 = no low-power mode supported 0 Reserved Internal reserved - do not modify 2 Type Default Note 0 LL This indicates the status of the lane alignment function on the receive XAUI interface. This is a latching low version of Bit 4.18.C. 1 = XAUI receiver is aligned correctly 0 = XAUI receiver is not aligned ROS 1 Indicates whether the XAUI interface supports a low-power mode Table 6.630 PHY XS Standard Status 1: Address 4.1 383 6.8.3 PHY XS Standard Device Identifier 1: Address 4.2 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default Note RO Table 6.631 PHY XS Standard Device Identifier 1: Address 4.2 6.8.4 PHY XS Standard Device Identifier 2: Address 4.3 Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.632 PHY XS Standard Device Identifier 2: Address 4.3 6.8.5 PHY XS Standard Speed Ability: Address 4.4 Bit F:1 0 Name Description Reserved Internal reserved - do not modify 10G Capable 1 = PHY XS is 10 Gb/s capable 0 = PHY XS is not 10 Gb/s capable Type Default ROS 1 Note This is always set to 1 in the AQR405. Table 6.633 PHY XS Standard Speed Ability: Address 4.4 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.6 PHY XS Standard Devices in Package 1: Address 4.5 Bit F:8 Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify 7 Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package ROS 1 This is always set to 1, as there is Autonegotiation in the AQR405. 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. 5 DTE XS Present 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no DTE XAUI interface in the AQR405. 4 PHY XS Present 1 = PHY XS is present in package 0 = PHY XS is not present in package ROS 1 This is always set to 1 as there is a PHY XS interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.634 PHY XS Standard Devices in Package 1: Address 4.5 385 6.8.7 PHY XS Standard Devices in Package 2: Address 4.6 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the Global registers. D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the GbE registers. C:0 Reserved Internal reserved - do not modify Table 6.635 PHY XS Standard Devices in Package 2: Address 4.6 6.8.8 PHY XS Standard Status 2: Address 4.8 Bit Name Description F:E Device Present [1:0] [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address D:C Reserved Internal reserved - do not modify Type Default ROS 0x2 Note This field is always set to 2, as the PHY XS is present in the AQR405. Table 6.636 PHY XS Standard Status 2: Address 4.8 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note B Transmit Fault 1 = Fault condition on transmit path 0 = No fault condition on transmit path LH This bit indicates whether there is a fault somewhere along the transmit path. A fault will be indicated if there is an alignment fault, a synchronization fault on any lane, or a FIFO underflow/overflow error. A Receive Fault 1 = Fault condition on receive path 0 = No fault condition on receive path LH This bit indicates whether there is a fault somewhere along the receive path. A fault will be indicated if there is a FIFO underflow/overflow error. Reserved Internal reserved - do not modify 9:0 Table 6.636 PHY XS Standard Status 2: Address 4.8 AQR405 Revision 0.11 - January 5, 2015 6.8.9 PHY XS Standard Package Identifier 1: Address 4.E Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.637 PHY XS Standard Package Identifier 1: Address 4.E 6.8.10 PHY XS Standard Package Identifier 2: Address 4.F Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default Note RO Table 6.638 PHY XS Standard Package Identifier 2: Address 4.F 387 6.8.11 PHY XS EEE Capability Register: Address 4.14 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:5 4 3:1 0 Name Description Reserved Internal reserved - do not modify PHY XS EEE 1 = EEE is supported for PHY XS 0 = EEE is not supported for PHY XS Reserved Internal reserved - do not modify XAUI Stop Capable 1 = The DTE XS may stop XAUI signals during LPI 0 = XAUI signals not stoppable Type Default ROS 1 ROS 0 Note Table 6.639 PHY XS EEE Capability Register: Address 4.14 6.8.12 PHY XS EEE Wake Error Counter: Address 4.16 Bit Name F:0 EEE Wake Error Counter [F:0] Description EEE wake error counter Type Default Note SCT 0x0000 This register is a 16-bit saturating clear on read counter. The wake error source is configured with 1E.C4A2.A:8. The default wake error source is from the TXI. Table 6.640 PHY XS EEE Wake Error Counter: Address 4.16 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.13 PHY XS Standard XGXS Lane Status: Address 4.18 Bit F:D Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify C PHY XGXS Lane Alignment Status 1 = XAUI Rx lanes aligned 0 = XAUI Rx lanes not aligned RO B PHY XGXS Pattern Testing Ability 1 = XAUI has the ability to generate XAUI Tx test patterns 0 = XAUI does not have the ability to generate XAUI Tx test patterns ROS 1 This is always set to 1 as the AQR405 is capable of generating test patterns at the XAUI interface. A PHY XGXS Loopback Ability 1 = XAUI has the ability to perform a loopback function 0 = XAUI does not have the ability to perform a loopback function ROS 1 This is always set to 1 as the AQR405 is capable of performing loopback at the XAUI interface. 9:4 Reserved Internal reserved - do not modify 3:0 Lane Sync [3:0] 1 = Lane is synchronized 0 = Lane is not synchronized Bit 0 corresponds to Lane 0 and so on When set, this bit indicates that the four XAUI Rx lanes are properly aligned. This is a non-latching version of bit 4.1.2. RO When set, these bits indicates that the corresponding lane of the XAUI interface is synchronized. Table 6.641 PHY XS Standard XGXS Lane Status: Address 4.18 6.8.14 PHY XS Standard XGXS Test Control: Address 4.19 Bit F:3 Name Reserved Description Type Default Note Internal reserved - do not modify 389 Table 6.642 PHY XS Standard XGXS Test Control: Address 4.19 Bit 2 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1:0 Name Description Type Default Note Receive TestPattern Enable 1 = XAUI Tx test pattern enabled 0 = XAUI Tx test pattern not enabled R/W PD 0 When set, this bit places the transmitters of the XAUI interface into test pattern mode. Test-Pattern Select [1:0] 0x3 = Reserved 0x2 = Mixed-frequency test pattern 0x1 = Low-frequency test pattern 0x0 = High-frequency test pattern R/W PD 0x2 These test patterns are described in Annex 48A of 802.3ae. These bits also interact with the Extended Test Pattern Control bits [C:B] in "PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800" on page 413. The full range of options is described there, but for these functions to correspond to the test-patterns described here, bits [C:B] must be set to zero. Table 6.642 PHY XS Standard XGXS Test Control: Address 4.19 6.8.15 TimeSync PHY XS Capability: Address 4.1800 Bit F:2 Name Description Type Reserved Internal reserved - do not modify 1 TimeSync Transmit Path Data Delay 1 = PHY XS provides information on transmit path data delay in registers 4.1801 through 4.1804 0 = PHY XS does not provide information on transmit path data delay RO 0 TimeSync Receive Path Data Delay 1 = PHY XS provides information on receive path data delay in registers 4.1805 through 4.1808 0 = PHY XS does not provide information on receive path data delay RO Default Table 6.643 TimeSync PHY XS Capability: Address 4.1800 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.16 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 Bit Name F:0 Maximum PHY XS Transmit Path Data Delay LSW [F:0] Description LSW of maximum PHY XS transmit delay in nanoseconds Type Default Note RO Table 6.644 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 6.8.17 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Maximum PHY XS Transmit Path Data Delay MSW [F:0] Description MSW of maximum PHY XS transmit delay in nanoseconds Type Default Note RO Table 6.645 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 6.8.18 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 Bit Name Description F:0 Minimum PHY XS Transmit Path Data Delay LSW [F:0] LSW of minimum PHY XS transmit delay in nanoseconds Type Default Note RO Table 6.646 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 391 6.8.19 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Minimum PHY XS Transmit Path Data Delay MSW [F:0] Description MSW of minimum PHY XS transmit delay in nanoseconds Type Default Note RO Table 6.647 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 6.8.20 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 Bit Name Description F:0 Maximum PHY XS Receive Path Data Delay LSW [F:0] LSW of maximum PHY XS receive delay in nanoseconds Type Default Note RO Table 6.648 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 6.8.21 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 Bit Name F:0 Maximum PHY XS Receive Path Data Delay MSW [F:0] Description MSW of maximum PHY XS receive delay in nanoseconds Type Default RO Table 6.649 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.22 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 Bit Name Description F:0 Minimum PHY XS Receive Path Data Delay LSW [F:0] LSW of minimum PHY XS receive delay in nanoseconds Type Default Note RO Table 6.650 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 6.8.23 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:0 Minimum PHY XS Receive Path Data Delay MSW [F:0] MSW of minimum PHY XS receive delay in nanoseconds Type Default Note RO Table 6.651 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 6.8.24 PHY XS SERDES Configuration 1: Address 4.C180 Bit F:5 4 Name Description Reserved Internal reserved - do not modify SERDES Configuration Reserved 1-1 Reserved Type Default R/W 0 393 Table 6.652 PHY XS SERDES Configuration 1: Address 4.C180 Note Bit 3 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 2:0 Name Description Reserved Internal reserved - do not modify SERDES Configuration Reserved 1-2 [2:0] Reserved Type Default R/W 0x0 Note Table 6.652 PHY XS SERDES Configuration 1: Address 4.C180 6.8.25 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 Bit F:1 0 Name Description Reserved Internal reserved - do not modify SERDES Lane 0 Configuration Reserved 1 Reserved Type Default R/W 1 Note Table 6.653 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 6.8.26 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 Bit F:1 0 Name Description Reserved Internal reserved - do not modify SERDES Lane 1 Configuration Reserved 1 Reserved Type Default R/W 1 Table 6.654 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.27 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 Bit F:1 0 Name Description Reserved Internal reserved - do not modify SERDES Lane 2 Configuration Reserved 1 Reserved Type Default R/W 1 Note Table 6.655 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 6.8.28 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 AQR405 Revision 0.11 - January 5, 2015 Bit F:1 0 Name Description Reserved Internal reserved - do not modify SERDES Lane 3 Configuration Reserved 1 Reserved Type Default R/W 1 Note Table 6.656 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 6.8.29 PHY XS SERDES LUT 256: Address 4.C200 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 SERDES LUT 256 Reserved [7:0] Reserved Type Default R/W 0x00 Note Spans 0xC200 to 0xC2FF. 395 Table 6.657 PHY XS SERDES LUT 256: Address 4.C200 6.8.30 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:D C B Name Description Type Default Reserved Transmit Provisioning C440 [2:0] Reserved for future use R/W PD 0x0 50 MHz Primary Output Enable This bit enables the output of the 50 MHz reference clock on the primary output: 1 = Enable the 50 MHz primary output 0 = Disable the 50 MHz primary output R/W PD 0 This bit enables the output of the 50 MHz reference clock on the secondary output: 1 = Enable the 50 MHz secondary output 0 = Disable the 50 MHz secondary output R/W PD 50 MHz Secondary Output Enable Note These fields can only be changed through the primary PHY only (i.e. PHY 0)!! NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 0 Table 6.658 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit A:1 0 Name Description Type Default Reserved Transmit Provisioning 1 [9:0] Reserved for future use R/W PD 0x000 SERDES Reset 1 = Reset SERDES 0 = Reset completed R/W SC 0 Note This self-clearing register reinitializes the SERDES. If the network interface is linked, the SERDES will be reinitialized at the current line rate. If not, the rate used will be based on the SERDES startup mode. AQR405 Revision 0.11 - January 5, 2015 NOTE! This bit will not self-clear in the absence of a valid Rx signal that can be used to perform Rx autocal NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F Table 6.658 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 397 6.8.31 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:E System I/F 10G Operating Mode [1:0] D System I/F 2500BASE-X Enable Description Type Default This field sets the 10G configuration of the system I/F: 0x0 = XAUI 0x1 = RXAUI 0x2 = KR (SERDES2 = XFI1) 0x3 = Reserved R/W PD 0x0 0 = Normal mode 1 = Enable 2500BASE-X mode for 2.5G R/W PD Note This field can only be changed via provisioning. NOTE! The start-up mode for these rates is selected in 7.C410.F:D. Also - KR autonegotiation is not supported as it is not defined to operate with Clause 28 Autonegotation. If UXSGMII operation is desired, select KR, and it will be used for all rates. 0 If enabled, 2500BASE-X mode will be used for 2.5G. In normal mode, 2.5G operation depends on the 10G Operating Mode setting (4.C441.[F:E]) Operation mode of other speeds depend on the 10G Operating Mode setting and SERDES Start-Up Mode (7.C410.[F:D]). C:B A:9 System I/F 1G/100M Operating Mode [1:0] This field sets the 1G/100M configuration of the system I/F: 0x0 = Normal mode 0x1 = XFI 0x2 - 0x3 = reserved R/W PD Reserved Transmit Provisioning 2a [1:0] Reserved for future use R/W PD 0x0 This field can only be changed via provisioning. In normal mode, 1G/100M operating mode depends on the SERDES Start-Up Mode (7.C410.[F:D]) 0x0 Table 6.659 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 PHY Operating Mode [2:0] This field sets the connectivity of the PHY: 0x0 = Selected 10G mode on System I/F UTP (RJ-45) is Network I/F 0x1 = Look-aside Mode: KR1 is System I/F (SERDES 2 = XFI1 / SGMII1) KR0 is Network I/F (SERDES 0 = SFI0 / SGMII0) 0x2 = 1+ 1 (SERDES 2 = KR1 / SGMII1 of the selected PHY (see Bit 5) is the System I/F) 0x3 = Reserved 0x4 -> 0x7 = Reserved R/W PD 0x0 This register selects the basic PHY configuration. This field can only be changed via provisioning. 5 RXAUI Operating Mode 1 = Dune 0 = Marvell R/W PD 0 This bit governs whether the RXAUI functions in Marvell mode (default) or Dune mode. 4 Enable KR Training 1 = KR Training Enabled 0 = KR Training Disabled R/W PD 0 This bit governs whether KR training is performed if KR is selected as the 10G operating interface. NOTE! KR without training enabled is essentially XFI+. 3 USX Autoneg Control For MAC 1 = Enable 0 = Disable R/W PD 0 USX enable/disable control for MAC. This gives USX autonegotiation control to MAC to enable/disable at any time after PHY reset. 2 Reserved Transmit Provisioning 2b Reserved for future use R/W PD 0 1:0 Lookaside Port Operating Mode [1:0] 0x0 = 10GBASE-R (XFI0) 0x1 = 1000BASE-X (SGMII0) 0x3 = KR / USXGMII R/W PD 0x0 This field is used to control the start-up behavior of the PHY's lookaside port I/F, when the PHY Operation Mode (Bits 7:6) is set to 0x1. Table 6.659 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 399 8:6 6.8.32 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default F:E XAUI Rx Lane 3 SERDES [1:0] Designates the SERDES for XAUI Lane 3 R/W PD 0x0 D:C XAUI Rx Lane 2 SERDES [1:0] Designates the SERDES for XAUI Lane 2 R/W PD 0x0 Note These are used to change the mapping of the SERDES to the XAUI lanes, allowing for flexible PCB layout. This field can only be changed via provisioning. B:A XAUI Rx Lane 1 SERDES [1:0] Designates the SERDES for XAUI Lane 1 R/W PD 0x0 9:8 XAUI Rx Lane 0 SERDES [1:0] Designates the SERDES for XAUI Lane 0 R/W PD 0x0 7:4 XAUI Rx Lane Invert [3:0] A 1 inverts the selected XAUI lane(s), with Bit 0 = Lane 0, etc. R/W PD 0x0 3:2 System SGMII Rx SERDES [1:0] This sets the lane to be used for System SGMII Rx Interface (GbE Tx path): 0x0 = SERDES 0 0x1 = SERDES 1 0x2 = SERDES 2 0x3 = SERDES 3 R/W PD 0x0 This selection is independent of what rate / format the system 10G interface is running at, except if look-aside mode (Bits 4.C441.7:6). In this case, Lane 2 must be used as the SGMII interface. This field can only be changed via provisioning. 1 System SGMII Rx Invert 1 = Invert the System SGMII Rx Interface R/W PD 0 This inverts the SGMII Rx interface. This field can only be changed via provisioning. 0 Reserved Internal reserved - do not modify Table 6.660 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.33 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F:C Reserved Transmit Provisioning 4a [3:0] Reserved for future use R/W PD 0x0 B System KR Rx Invert 1 = Invert System KR Rx (SERDES2 = KR1) R/W PD 0 This field can only be changed via provisioning. A Lookaside Port Rx Invert 1 = Invert KR0 / SGMII0 Rx R/W PD 0 SERDES0 = KR0 / SGMII0 is the network interface. This field can only be changed via provisioning. 9:0 Reserved Transmit Provisioning 4 [9:0] Reserved for future use R/W PD 0x000 Table 6.661 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 401 6.8.34 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:B Name Loopback Control [4:0] Description Type Default 0x00 = No loopback 0x01 = System Interface - System Loopback 0x02 = Reserved 0x03 = System Interface - Network Loopback 0x04 - 0x08 = Reserved 0x09 = Network Interface - System Loopback 0x0A = Reserved 0x0B = Network Interface - Network Loopback 0x0C - 0x1F = Reserved R/W PD 0x00 Note These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F A:6 5 Reserved Transmit Provisioning 5 [4:0] Reserved for future use R/W PD 0x00 MDI Packet Generation 1 = CRPAT packet generation out MDI interface 0 = No CRPAT packet generation out MDI interface R/W PD 0 Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F Table 6.662 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default 4 Look-Aside Port Packet Generation 1 = CRPAT packet generation out 10G look-aside interface (KR0) 0 = No CRPAT packet generation out 10G look-aside interface (KR0) R/W PD 0 Note Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 3 AQR405 Revision 0.11 - January 5, 2015 System I/F Packet Generation 1 = CRPAT packet generation out 10G system interface 0 = No CRPAT packet generation out 10G system interface R/W PD 0 Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 2:0 Rate [2:0] 0x7 - 0x6 = reserved 0x5 = 5G 0x4 = 2.5G 0x3 = 10G 0x2 = 1G 0x1 = 100M 0x0 = reserved R/W PD 0x0 These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. 403 Table 6.662 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 6.8.35 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Reserved Transmit Provisioning 6 [F:0] Description Reserved for future use Type Default R/W PD 0x0000 Note Table 6.663 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 6.8.36 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 Bit F:0 Name Tx Frame Counter LSW [F:0] Description Tx Good Frame Counter Type Default Note SCT L 0x0000 This counts 10G Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.664 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 6.8.37 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 Tx Frame Counter MSW [9:0] Tx Good Frame Counter Type Default SCT M 0x000 Note This counts 10G Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.665 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.38 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 Bit F:0 Name Description Tx Frame Error Counter LSW [F:0] Tx Bad Frame Counter Type Default SCT L 0x0000 Note This counts 10G Ethernet frames with a bad FCS (aka CRC-32). Table 6.666 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 6.8.39 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:A Reserved Internal reserved - do not modify 9:0 Tx Frame Error Counter MSW [9:0] Tx Bad Frame Counter Type Default SCT M 0x000 Note This counts 10G Ethernet frames with a bad FCS (aka CRC-32). Table 6.667 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 6.8.40 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 Bit F:0 Name Numbers of Serdes Cals [F:0] Description Number of SERDES calibrations since the last PHY reset (or power-up). Type RO Default Note This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. Table 6.668 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 405 6.8.41 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:8 Number of SIF Block Lock Transtitions 1 - 0 [7:0] Number of SIF block lock transitions since PHY reset from 1 to 0 i.e. loss of block lock. RO This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. 7:0 Number of SIF Block Lock Transtitions 0 - 1 [7:0] Number of SIF block lock transitions since PHY reset from 0 to 1, i.e. regained block lock. RO This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. Table 6.669 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 6.8.42 PHY XS Transmit (XAUI Rx) Reserved Vendor State 3: Address 4.C822 Bit F:0 Name Description Number of SIF XGS Switch-overs [F:0] Number of SIF side XGS Switch-overs since Phy Reset. Type RO Default Note This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. Table 6.670 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.43 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 Bit Name Description Type F CRPAT Test Pattern Checker Sync Error 1 = Test pattern checker is out of sync 0 = Test pattern checker is in sync LH E:B PRBS Test Pattern Checker Sync Error [3:0] 1 = Test pattern checker is out of sync 0 = Test pattern checker is in sync LH Default Note Bit 0 corresponds to lane 0 and so on AQR405 Revision 0.11 - January 5, 2015 A:1 0 Reserved Internal reserved - do not modify MACSEC Egress Interrupt 1 = MACSEC Egress Interrupt LH Table 6.671 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 6.8.44 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 Bit F:E Name Description Reserved Internal reserved - do not modify D XAUI Rx Sequence Ordered Set Deletion 1 = Sequence ordered set was deleted on the XAUI Rx interface C Reserved Internal reserved - do not modify Type Default Note LH 407 Table 6.672 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 Bit B:A Name Description Type Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 XAUI Rx Lane Alignment Lock Status [1:0] 1 = Lanes locked LL 9 XAUI Rx Reserved XGMII Character Received 1 = Reserved XGMII character was received on the XAUI Rx interface LH 8 XAUI Rx Invalid XGMII Character Received 1 = Invalid XGMII character was received on the XAUI Rx interface LH XAUI Rx Code Violation Error [3:0] 1 = A code violation error was detected on the corresponding lane of the XAUI Rx interface. LH 7:4 Default Bit 0 corresponds to lane 0 and so on 3:0 XAUI Rx Running Disparity Error [3:0] 1 = A running disparity error was detected on the corresponding lane of the XAUI Rx interface. LH Bit 0 corresponds to lane 0 and so on Table 6.672 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.45 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 Bit Name Description Type F:C Loss of Signal [3:0] 1 = Loss of Signal on associated logical lane: Bit 0: KR0, XAUI Lane 0, SGMII Bit 1: XAUI Lane 1 Bit 2: KR1, XAUI Lane 2 Bit 3: XAUI Lane 3 LH B:0 Reserved PHY XS Transmit Alarms [B:0] Reserved LH Default Note These bits provide the Loss of Signal indication for the logical SERDES lane that loses signal. AQR405 Revision 0.11 - January 5, 2015 Table 6.673 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 6.8.46 6.8.47 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 Bit Name Description Type Default Note Internal reserved - do not modify B Tx LPI Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for Bit 4.1.B. A Rx LPI Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for Bit 4.1.A. Reserved Internal reserved - do not modify 9:3 Mask for Bit 4.1.B. Table 6.674 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 409 Reserved F:C AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name 2 PHY XS Transmit Link Alignment Status Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Internal reserved - do not modify 1:0 Description Type Default R/W PD 0 Note Mask for Bit 4.1.2. Note this bit also shows up as Bit 4.24.C, but only as a status bit. Table 6.674 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 6.8.48 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 Bit F:C Name Description Type Default Note Reserved Internal reserved - do not modify B Transmit Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 4.8.B A Receive Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Bit 4.8.A Reserved Internal reserved - do not modify 9:0 Table 6.675 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 6.8.49 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400 Bit Name Description F CRPAT Test Pattern Checker Sync Error Mask E:B PRBS Test Pattern Checker Sync Error Mask [3:0] Type Default 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 Note Table 6.676 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit A:1 0 Name Description Reserved Internal reserved - do not modify MACSEC Egress Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0 Note Table 6.676 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400 6.8.50 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401 Bit F:E Name Description AQR405 Revision 0.11 - January 5, 2015 Type Default R/W PD 0 Reserved Internal reserved - do not modify D XAUI Rx Sequence Ordered Set Deletion Mask 1 = Enable interrupt generation 0 = Disable interrupt generation C Reserved Internal reserved - do not modify B:A XAUI Rx Lane Alignment Lock Status Mask [1:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 9 XAUI Rx Reserved XGMII Character Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 8 XAUI Rx Invalid XGMII Character Received Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note 411 Table 6.677 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 7:4 XAUI Rx Code Violation Error Mask [3:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 3:0 XAUI Rx Running Disparity Error Mask [3:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 Note Table 6.677 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401 6.8.51 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402 Bit Name Description Type Default F:C Loss of Signal Mask [3:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W 0x0 B:0 Reserved PHY XS Transmit Alarms Mask [B:0] Reserved R/W 0x000 Note Table 6.678 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402 6.8.52 6.8.53 6.8.54 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.55 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Test Pattern Force Error 1 = Force test pattern error R/W 0 This injects 10 PRBS Errors or 32 CRPAT errors E Test Pattern Mode 7 Force Error 1 = Force test pattern #7 error R/W 0 This injects 32 errors D XAUI Rx Local Fault Injection 1 = Inject local fault towards UTP Line R/W 0 Test-Pattern Extended Select [1:0] {Test-Pattern Extended Select [C:B], Test-Pattern Select[1:0]} 0x0 = Annex 48A.1 High Frequency 0x1 = Annex 48A.2 Low Frequency 0x2 = Annex 48A.3 Mixed Frequency 0x4 = Annex 48A.4 CRPAT 0x5 = Annex 48A.5 CJPAT 0x6 = At speed CRPAT out the line 0x7 = PRBS-31 (x^31+x^28+1) 0x8 = PRBS-23 (x^23+x^18+1) 0x9 = PRBS-7 (x^7+x^6+1) 0xA = PRBS-15 (x^15+x^14+1) 0x3, 0xC -> 0xF = Reserved R/W PD 0x0 These bits combine with the standard defined bits [1:0] in "PHY XS Standard XGXS Test Control: Address 4.19" on page 10 to define a broader suite of tests. Test Pattern Check Enable 1 = Test pattern checker enabled 0 = Test pattern checker not enabled R/W PD 0 Test pattern checker enable. (Used for PRBS, Annex 48.4, and datapath error checking.) This should only be enabled after the test mode is selected. Reserved Internal reserved - do not modify Test Pattern Check Point Test pattern check point for CRPAT and data path tests. R/W PD 0 This is latched on the rising edge of "Test Pattern Check Enable" C:B A 9:8 7 Table 6.679 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 413 F Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 6 Test Pattern Mode 7 Check Enable Enable checking for Test Mode 7 R/W PD 0 5 Test Pattern Invert Inverts the PRBS generation and checking R/W PD 1 Test Pattern Synchronization Threshold [4:0] PRBS synchronization threshold configuration. If the number of PRBS bit errors is greater than or equal to the threshold within a 4 clock cycle window, the PRBS checker will declare a synchronization error and attempt to resynchronize to the incoming PRBS pattern. Setting this to 0, disables the resynchronization R/W PD 0x0A 4:0 Note Inversion can also be done using the individual Tx and Rx lane inversion bits. Table 6.679 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 6.8.56 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 Bit F Name Description Type Default Reserved Internal reserved - do not modify E:C Test Pattern Insert Extra Idles [2:0] Number of extra 4 Idle Octets to insert R/W 0x0 B:8 Test Pattern Check Select [3:0] 1 = Enable PRBS checking on the corresponding XAUI Rx Lane R/W 0x0 Note Number of extra 4 idle octets to insert in CRPAT and CJPAT generation. Table 6.680 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description 7:4 Reserved Internal reserved - do not modify 3:0 Test Pattern Channel Select [3:0] 1 = Test Pattern enabled Type Default R/W 0x0 Note Used to select which XAUI channel(s) the PRBS is inserted on. Table 6.680 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 6.8.57 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 Channel 0 Test Pattern Error Counter [F:0] Description Type Default Note A saturating 16 bit counter for errors detected from the test mode. Error counters for CRPAT, CJPAT, XAUI PRBS7,23,31 (for channel(s) selected). Note that CRPAT and CJPAT only use channel 0 SCT 0x0000 Clear on read. This is a saturating 16-bit counter which accumulates the number of test errors during pattern test. Note that the API must be used to read the x^15 error counts. Table 6.681 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 6.8.58 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 Bit F:0 Name Channel 1 Test Pattern Error Counter [F:0] Type Default Note A saturating 16 bit counter for errors detected from the test mode. Error counters for CRPAT, CJPAT, XAUI PRBS7,23,31 (for channel(s) selected). Note that CRPAT and CJPAT only use channel 0 SCT 0x0000 Clear on read. This is a saturating 16-bit counter which accumulates the number of test errors during pattern test. Note that the API must be used to read the x^15 error counts. Table 6.682 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 415 Description 6.8.59 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Channel 2 Test Pattern Error Counter [F:0] Description Type Default Note A saturating 16 bit counter for errors detected from the test mode. Error counters for CRPAT, CJPAT, XAUI PRBS7,23,31 (for channel(s) selected). Note that CRPAT and CJPAT only use channel 0 SCT 0x0000 Clear on read. This is a saturating 16-bit counter which accumulates the number of test errors during pattern test. Note that the API must be used to read the x^15 error counts. Table 6.683 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 6.8.60 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 Bit F:0 Name Channel 3 Test Pattern Error Counter [F:0] Description Type Default Note A saturating 16 bit counter for errors detected from the test mode. Error counters for CRPAT, CJPAT, XAUI PRBS7,23,31 (for channel(s) selected). Note that CRPAT and CJPAT only use channel 0 SCT 0x0000 Clear on read. This is a saturating 16-bit counter which accumulates the number of test errors during pattern test. Note that the API must be used to read the x^15 error counts. Table 6.684 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.61 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 Bit F:0 Name Description Test Pattern Mode 7 Error Counter [F:0] A saturating 16 bit counter for errors detected from the test mode #7 Type Default Note SCT 0x0000 This is a saturating 16-bit counter which accumulates the number of test errors during pattern test as specified in test mode #7 Clause 55 test. Table 6.685 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 6.8.62 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F:E XAUI Tx Lane 3 SERDES [1:0] Designates the SERDES for XAUI Lane 3 R/W PD 0x0 D:C XAUI Tx Lane 2 SERDES [1:0] Designates the SERDES for XAUI Lane 2 R/W PD 0x0 B:A XAUI Tx Lane 1 SERDES [1:0] Designates the SERDES for XAUI Lane 1 R/W PD 0x0 9:8 XAUI Tx Lane 0 SERDES [1:0] Designates the SERDES for XAUI Lane 0 R/W PD 0x0 7:4 XAUI Tx Lane Invert [3:0] A 1 inverts the selected XAUI lane(s), with Bit 0 = Lane 0, etc. R/W PD 0x0 Note These are used to change the mapping of the SERDES to the XAUI lanes, allowing for flexible PCB layout. This field can only be changed via provisioning. This field can only be changed via provisioning. 417 Table 6.686 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 Bit Name Description Type Default Note Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 3:2 System SGMII Tx SERDES [1:0] This sets the lane to be used for System SGMII Tx (GbE Rx path): 0x0 = SERDES 0 0x1 = SERDES 1 0x2 = SERDES 2 0x3 = SERDES 3 R/W PD 0x0 This selection is independent of what rate / format the system 10G interface is running at, except if look-aside mode (Bits 4.C441.7:6). In this case, Lane 2 must be used as the SGMII interface. This field can only be changed via provisioning. 1 System SGMII Tx Invert 1 = Invert System SGMII Tx Interface R/W PD 0 This inverts the System SGMII Tx interface. This field can only be changed via provisioning. 0 Reserved Receive Provisioning 1 Reserved for future use R/W PD 0 Table 6.686 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 6.8.63 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 Bit Name Description Type Default Note F:C Reserved Receive Provisioning 2a [3:0] Reserved for future use R/W PD 0x0 B System KR Tx Invert 1 = Invert System KR Tx (SERDES2 = KR1) R/W PD 0 This field can only be changed via provisioning. A Lookaside Port Tx Invert 1 = Invert SERDES0 = KR0 / SGMII0 Tx R/W PD 0 This field can only be changed via provisioning. Table 6.687 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 9 Apply SERDES Tx Settings Reserved Receive Provisioning 2 [8:0] 8:0 Description Type Default 1 = Apply SERDES transmit settings R/W PD 0 Reserved for future use R/W PD 0x000 Note When set to 1, the SERDES transmit settings in 4.E412 through 4.E419 will be propogated to the SERDES core registers. This bit will be cleared after the transfer is completed. Table 6.687 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 6.8.64 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F:C Reserved Rx Provisioning 3 [3:0] R/W PD 0x0 B:8 SERDES Lane 0 Post Tap 1 [3:0] R/W PD 0x0 7:5 SERDES Lane 0 Pre Tap [2:0] R/W PD 0x0 4:0 SERDES Lane 0 Main Tap [4:0] R/W PD 0x00 Note Table 6.688 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 419 6.8.65 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:3 Reserved Rx Provisioning 4 [C:0] 2:0 SERDES Lane 0 Amplitude [2:0] Description Reserved for internal use Type Default R/W PD 0x0000 R/W PD 0x0 Note Table 6.689 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 6.8.66 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 Bit Name Description Type Default F:C Reserved Rx Provisioning 5 [3:0] R/W PD 0x0 B:8 SERDES Lane 1 Post Tap 1 [3:0] R/W PD 0x0 7:5 SERDES Lane 1 Pre Tap [2:0] R/W PD 0x0 4:0 SERDES Lane 1 Main Tap [4:0] R/W PD 0x00 Note Table 6.690 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.67 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 Bit Name F:3 Reserved Rx Provisioning 6 [C:0] 2:0 SERDES Lane 1 Amplitude [2:0] Description Reserved for internal use Type Default R/W PD 0x0000 R/W PD 0x0 Note Table 6.691 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 AQR405 Revision 0.11 - January 5, 2015 6.8.68 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 7: Address 4.E416 Bit Name Description Type Default F:C Reserved Rx Provisioning 7 [3:0] R/W PD 0x0 B:8 SERDES Lane 2 Post Tap 1 [3:0] R/W PD 0x0 7:5 SERDES Lane 2 Pre Tap [2:0] R/W PD 0x0 4:0 SERDES Lane 2 Main Tap [4:0] R/W PD 0x00 Note 421 Table 6.692 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 6.8.69 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:3 Reserved Rx Provisioning 8 [C:0] 2:0 SERDES Lane 2 Amplitude [2:0] Description Reserved for internal use Type Default R/W PD 0x0000 R/W PD 0x0 Note Table 6.693 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 6.8.70 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 Bit Name Description Type Default F:C Reserved Rx Provisioning 9 [3:0] R/W PD 0x0 B:8 SERDES Lane 3 Post Tap 1 [3:0] R/W PD 0x0 7:5 SERDES Lane 3 Pre Tap [2:0] R/W PD 0x0 4:0 SERDES Lane 3 Main Tap [4:0] R/W PD 0x00 Note Table 6.694 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.71 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 Bit Name F:3 Reserved Rx Provisioning 10 [C:0] 2:0 SERDES Lane 3 Amplitude [2:0] Description Reserved for internal use Type Default R/W PD 0x0000 R/W PD 0x0 Note Table 6.695 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 AQR405 Revision 0.11 - January 5, 2015 6.8.72 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 Bit F:0 Name Rx Frame Counter LSW [F:0] Description Rx Good Frame Counter Type Default Note SCT L 0x0000 This counts 10G Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.696 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 6.8.73 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 Bit Name Description Reserved Internal reserved - do not modify 9:0 Rx Frame Counter MSW [9:0] Rx Good Frame Counter Default SCT M 0x000 Note This counts 10G Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.697 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 423 F:A Type 6.8.74 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:0 Rx Frame Error Counter LSW [F:0] Rx Bad Frame Counter Type Default SCT L 0x0000 Note This counts 10G Ethernet frames with a bad FCS (aka CRC-32). Table 6.698 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 6.8.75 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 Bit Name Description F:A Reserved Internal reserved - do not modify 9:0 Rx Frame Error Counter MSW [9:0] Rx Bad Frame Counter Type Default SCT M 0x000 Note This counts 10G Ethernet frames with a bad FCS (aka CRC-32). Table 6.699 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 6.8.76 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810 Bit Name Description F:0 Number of USX Aneg Restarts [F:0] Number of USX autonegotiations since PHY reset. Type RO Default Note This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset Table 6.700 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.77 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:E System Interface Autoneg Status [1:0] 0 = N/A 1 = Not Complete 2 = Complete 3 = Reserved RO Indicates the completion progress of the system interface's autonegotation. D Rx Link Up 0 = Link Not Up 1 = Link Up RO Indicates that the system interface has linked and is ready to receive. C Tx Ready 0 = Not Ready 1 = Ready RO Indicates that the system interface is ready to transmit. System Interface Rate [3:0] 0 = 10M 1 = 100M 2 = 1G 3 = 10G 4 = 2.5G 5 = 5G 6 = Power Down 7 - 0xF = Reserved RO Indicates the currently active data rate for the system interface. B:8 Description Type Default Note Table 6.701 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812 425 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 7:3 System Interface In Use [4:0] 0 = Backplane KR 1 = Backplane KX 2 = XFI 3 = USXGMII 4 = XAUI 5 = XAUI Pause Based 6 = SGMII 7 = RXAUI 8 = MAC 9 = OFF 0xA - 0x1F = Reserved RO 2:0 Reserved Receive State 3 [2:0] Reserved for future use RO Default Note Indicates the currently active mode for the system interface. Table 6.701 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812 6.8.78 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 Bit Name Description Type F Reserved XGMII Character Received from PCS 1 = Reserved XGMII character was received from the PCS LH E Invalid XGMII Character Received from PCS 1 = Invalid XGMII character was received from the PCS LH Default Table 6.702 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit D C:1 0 Name Description Link status Message Received from PCS 1 = Link status message was received from the PCS Reserved Internal reserved - do not modify MACSEC Ingress Interrupt 1 = MACSEC Ingress Interrupt Type Default Note LH LH Table 6.702 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 6.8.79 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F System Interface Rx Link Up 1 = System Interface Rx has come up LH This bit indicates that the SERDES receive link has come up. This is an alarm bit corresponding to a 1 value of the status bit: 4.E812.D E System Interface Rx Link Down 1 = System Interface Rx has gone down LH This bit indicates that the SERDES receive link has gone down. This is an alarm bit corresponding to a 0 value of the status bit: 4.E812.D D System Interface Tx Ready 1 = System Interface Tx has become ready to transmit LH This bit indicates that the SERDES transmit link has become ready to transmit. This is an alarm bit corresponding to a 1 value of the status bit: 4.E812.C Table 6.703 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 427 Bit C AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential B:0 Name Description Type System Interface Tx Not Ready 1 = System Interface Tx has become not-ready to transmit LH Reserved PHY XS Receive Alarms 2 [B:0] Reserved LH Default Note This bit indicates that the SERDES transmit link has become not-ready to transmit. This is an alarm bit corresponding to a 0 value of the status bit: 4.E812.C Table 6.703 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 6.8.80 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400 Bit Name F Reserved XGMII Character Received from PCS Mask E D C:1 0 Description Type Default 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Invalid XGMII Character Received from PCS Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Link status Message Received from PCS Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify MACSEC Ingress Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note Table 6.704 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.81 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401 Bit Name AQR405 Revision 0.11 - January 5, 2015 Type Default F System Interface Rx Link Up Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for alarm: 4.EC01.F E System Interface Rx Link Down Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for alarm: 4.EC01.E D System Interface Tx Ready Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for alarm: 4.EC01.D C System Interface Tx Not Ready Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mask for alarm: 4.EC01.C Reserved PHY XS Receive Alarms 2 Mask [B:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0000 1 = Enable interrupt generation 0 = Disable interrupt generation B:0 Description Note Table 6.705 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401 429 6.8.82 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note XAUI Tx Error Injection Lane Select [2:0] [F:D] 0x0 = Lane 0 0x1 = Lane 1 0x2 = Lane 2 0x3 = Lane 3 0x4 = All four lanes R/W 0x0 This controls which of the 4 Tx XAUI lanes debug error injection occurs on. C XAUI Tx Inject Synchronization Error 1 = Inject a synchronization error R/W 0 This injects a synchronization error on the lanes selected in F:D B XAUI Tx Inject Alignment Error 1 = Inject an alignment error R/W 0 This injects an alignment error on the lanes selected in F:D A XAUI Tx Inject Code Violation 1 = Inject code violation error R/W 0 This injects the 10B codeword on the lanes selected in F:D 9:0 XAUI Tx 10B Violation Codeword [9:0] [9:0] = 10B violation codeword to be injected by writing a 1 to Bit A R/W 0x000 F:D Table 6.706 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 6.8.83 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.707 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.8.84 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F PHY XS System Loopback Pass Through When set to 1, this bit enables loopback traffic from the PHY XS System Loopback to pass-through towards the network UTP line. When set to 0, the data sent towards the network UTP line will be all IDLEs when in PHY XS System Loopback R/W 0 This enables traffic to pass through as well as loopback when the PHY XS System Loopback is enabled. E PHY XS System Loopback Enable 1 = Enable PHY XS System Loopback mode 0 = Normal operation R/W 0 This bit enables the PHY XS System Loopback from the Tx XAUI Interface after lane alignment to the Rx XAUI interface. D XAUI Tx Local Fault Injection 1 = Inject local fault towards XAUI system side 0 = Normal operation R/W 0 C Reserved 4 Reserved for future use R/W 0 Reserved Internal reserved - do not modify B:0 Note Table 6.708 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 6.8.85 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 Name Description Type Default Note F Standard Alarms 1 Interrupt 1 = Interrupt in standard alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. E Standard Alarms 2 Interrupt 1 = Interrupt in standard alarms 2 RO An interrupt was generated from the status register and the corresponding mask register. Table 6.709 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 431 Bit Bit D:B Name Description Type Default Note Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Reserved Internal reserved - do not modify A Vendor Specific Tx Alarms 1 Interrupt 1 = Interrupt in vendor specific Tx alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. 9 Vendor Specific Tx Alarms 2 Interrupt 1 = Interrupt in vendor specific Tx alarms 2 RO An interrupt was generated from the status register and the corresponding mask register. 8 Vendor Specific Tx Alarms 3 Interrupt 1 = Interrupt in vendor specific Tx alarms 3 RO An interrupt was generated from the status register and the corresponding mask register. Reserved Internal reserved - do not modify 2 Vendor Specific Rx Alarms 1 Interrupt 1 = Interrupt in vendor specific Rx alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. 1 Vendor Specific Rx Alarms 2 Interrupt 1 = Interrupt in vendor specific Rx alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. 0 Reserved Internal reserved - do not modify 7:3 Table 6.709 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9 Autonegotiation Registers 6.9.1 Autonegotiation Standard Control 1: Address 7.0 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 Default Note R/W SC 1 Resets the entire PHY. The reset bit is automatically cleared upon completion of the reset sequence by the microcontroller. This bit is set to 1 during reset. The reset is internally stretched by approximately 1.7 us. Therefore the MDIO or uP should allow for 1.7 us before writing any Autonegotiation registers after this bit is set. F Reset E Reserved D Extended Next Page Control 1 = Extended next pages are enabled 0 = Extended next pages are disabled R/W PD 1 This bit is OR'ed with bit 7.10.C. C Autonegotiation Enable 1 = Enable autonegotiation 0 = Disable autonegotiation R/W PD 1 When enabled, autonegotiation determines the link speed. If this bit is disabled, autonegotiation is disabled. R/W SC 0 NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F B:A 9 8:0 Reserved Restart Autonegotiation Reserved 1 = Autonegotiation reset 0 = Normal operation Type Internal reserved - do not modify Internal reserved - do not modify 1 = Restart autonegotiation process 0 = Normal operation Internal reserved - do not modify 433 Table 6.710 Autonegotiation Standard Control 1: Address 7.0 6.9.2 Autonegotiation Standard Status 1: Address 7.1 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:A Name Reserved Description Type Default Note Internal reserved - do not modify 1 = A fault has been detected via the parallel detection function 0 = A fault has not been detected via the parallel detection function LH 9 Parallel Detection Fault 8 Reserved 7 Extended Next Page Status 1 = Extended next page will be used 0 = Extended next page will not be used RO Indicates that both the local device and the link partner have indicated support for extended next page. 6 Page Received 1 = A page has been received 0 = A page has not been received LH Indicates that a page has been received. If a regular page, it is placed in 7.13 ->7.15. If an extended next page it is placed in registers 7.19 -> 7.1B 5 Autonegotiation Complete 1 = Autonegotiation complete 0 = Autonegotiation in process RO This indicates the status of the Autonegotiation receive link. 4 Remote Fault 1 = Remote fault condition detected 0 = No remote fault condition detected LH This indicates that the remote PHY has a fault. 3 Autonegotiation Ability 1 = PHY is able to perform autonegotiation 0 = PHY is not able to perform autonegotiation ROS 2 Link Status 1 = Link is up 0 = Link lost since last read LL Internal reserved - do not modify 1 Always set as 1 as the local device has autonegotiation ability. This bit it is a duplicate of the PMA link status bit in 1.1.2. Note that this is latching low, so it can only be used to detect link drops, and not the current status of the link without performing back-to-back reads. Table 6.711 Autonegotiation Standard Status 1: Address 7.1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 1 Reserved 0 Link Partner Autonegotiation Ability Description Type Default Note Internal reserved - do not modify RO 1 = Link Partner able to perform autonegotiation 0 = Link Partner not able to perform autonegotiation Table 6.711 Autonegotiation Standard Status 1: Address 7.1 6.9.3 Autonegotiation Standard Device Identifier 1: Address 7.2 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default Note RO Table 6.712 Autonegotiation Standard Device Identifier 1: Address 7.2 6.9.4 Autonegotiation Standard Device Identifier 2: Address 7.3 Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.713 Autonegotiation Standard Device Identifier 2: Address 7.3 435 6.9.5 Autonegotiation Standard Devices in Package 1: Address 7.5 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:8 Name Reserved Description Type Default Note Internal reserved - do not modify 7 Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package ROS 1 This is always set to 1, as there is Autonegotiation in the AQR405. 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. 5 DTE XS Present 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no DTE XAUI interface in the AQR405. 4 PHY XS Present 1 = PHY XS is present in package 0 = PHY XS is not present in package ROS 1 This is always set to 1 as there is a PHY XS interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.714 Autonegotiation Standard Devices in Package 1: Address 7.5 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.6 Autonegotiation Standard Devices in Package 2: Address 7.6 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the global control registers. D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the GbE registers. C:0 Reserved Internal reserved - do not modify Table 6.715 Autonegotiation Standard Devices in Package 2: Address 7.6 6.9.7 Autonegotiation Standard Status 2: Address 7.8 Bit Name F:E Device Present [1:0] D:0 Reserved Description [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address Type Default ROS 0x2 Note This field is always set to 0x2, as the Autonegotiation resides here in the AQR405. Internal reserved - do not modify Table 6.716 Autonegotiation Standard Status 2: Address 7.8 437 6.9.8 Autonegotiation Standard Package Identifier 1: Address 7.E AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.717 Autonegotiation Standard Package Identifier 1: Address 7.E 6.9.9 Autonegotiation Standard Package Identifier 2: Address 7.F Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default Note RO Table 6.718 Autonegotiation Standard Package Identifier 2: Address 7.F 6.9.10 Autonegotiation Advertisement Register: Address 7.10 Bit Name F Next page Ability E Reserved Description 1 = Next page ability Type Default R/W PD 1 Note If a device implements Next Page ability and wishes to engage in Next Page exchange, it shall set the NP bit to 1. A device may implement Next Page ability and choose not to engage in Next Page exchange by setting the NP bit to a 0. Internal reserved - do not modify Table 6.719 Autonegotiation Advertisement Register: Address 7.10 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit D Name Advertisement Remote Fault Description 1 = Remote fault Type Default R/W 0 Note The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. Note: The PHY does not support a remote fault sensing function. C Extended Next Page Ability 1 = Extended next page capable 0 = Not capable of extended next pages R/W PD 1 AQR405 Revision 0.11 - January 5, 2015 The Extended Next Page (XNP) bit indicates that the local device supports transmission of extended next pages when set to 1 and indicates that the local device does not support extended next pages when set to 0. Table 6.719 Autonegotiation Advertisement Register: Address 7.10 439 This register is used in conjunction with bit 7.C400.5 to hard provision the autonegotiation base page that will be sent. AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default B:5 Technology Ability Field [6:0] Bit 0: 10BASE-T Bit 1: 10BASE-T full duplex Bit 2: 100BASE-TX Bit 3: 100BASE-TX full duplex Bit 4: 100BASE-T4 Bit 5: PAUSE operation for full duplex links Bit 6: Asymmetric PAUSE operation for full duplex links R/W PD 0x00 Note The Technology Ability Field contains information indicating supported technologies defined in Annex 28B.2 and Annex 28D. Multiple technologies may be advertised in the link code word. A device shall support the data service ability for a technology it advertises. Since the PHY does not support 10BASE-T or 100BASE-T4, these bits (0, 1, 4) should always be set to zero. 4:0 Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved R/W PD 0x01 This field should always be set to 0x01 as the PHY is only capable of handling 802.3 Ethernet. Table 6.719 Autonegotiation Advertisement Register: Address 7.10 6.9.11 Autonegotiation Link Partner Base Page Ability Register: Address 7.13 Bit Name Description Type Default Note F Link Partner Next Page Ability 1 = Next page ability 0 = Next page ability not supported or not engaged RO If Next Page ability is not supported, the NP bit shall always be set to 0. If a device implements Next Page ability and wishes to engage in Next Page exchange, it shall set the NP bit to logic 1. E Link Partner Base Page Acknowledge 1 = Acknowledge RO The Acknowledge (ACK) is used by the Auto-Negotiation function to indicate that a device has successfully received its Link Partner's Link Code Word. Table 6.720 Autonegotiation Link Partner Base Page Ability Register: Address 7.13 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 D Link Partner Remote Fault 1 = Remote fault RO The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. C Link Partner Extended Next Page Ability 1 = Extended next page capable 0 = Not capable of extended next pages RO The extended next page indicates that the link partner has indicated support for the extended next page when set to 1. When set to 0, the link partner does not support extended next page. B:5 Link Partner Technology Ability Field [6:0] Bit 0: 10BASE-T Bit 1: 10BASE-T full duplex Bit 2: 100BASE-TX Bit 3: 100BASE-TX full duplex Bit 4: 100BASE-T4 Bit 5: PAUSE operation for full duplex links Bit 6: Asymmetric PAUSE operation for full duplex links RO Technology ability field contains information indicating supported technologies defined in Annex 28B.2 and Annex 28D. Multiple technologies may be advertised in the link code word. A device shall support the data service ability for a technology it advertises. The arbitration function determines the common mode of operation shared by a link partner and resolves the multiple common modes. 4:0 Link Partner Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved RO Selector field encodes 32 possible messages defined in Annex 28A. Combinations not specified are reserved for future use and shall not be transmitted. Table 6.720 Autonegotiation Link Partner Base Page Ability Register: Address 7.13 441 6.9.12 Autonegotiation Extended Next Page Transmit Register: Address 7.16 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Default Note R/W 0 Next page is used by the next page function to indicate whether or not this is the last next page to be transmitted. F Next Page E Reserved D Message Page 1 = Message page 0 = Unformatted page R/W 0 Message page is used by the next page function to differentiate a message page from an unformatted page. C Acknowledge 2 1 = Will comply with corresponding message 0 = Cannot comply with corresponding message R/W 0 Acknowledge 2 is used by the next page function to indicate that a device has the ability to comply with the message. B Toggle Value of toggle bit RO Message Code Field [A:0] [A:0] = Message Code Field: R/W PD A:0 1 = Additional next page will follow 0 = Last page Type Internal reserved - do not modify 0x0 = Reserved 0x1 = Null message 0x2 -> 0x3 Reserved Expansion message 0x4 = Remote fault details message 0x5 = OUI message 0x6 = PHY ID message 0x7 = 100BASE-T2 message 0x8 = 1000BASE-T message 0x9 = 10GBASE-T message Set to opposite of corresponding bit in previous page. 0x001 Interpreted as message code (see 802.3 Appendix 28C) if Message Page bit is set to one (7.16:1). Otherwise interpreted as an unformatted code field. Table 6.721 Autonegotiation Extended Next Page Transmit Register: Address 7.16 This register is used in conjunction with bit 7.C400.5 and registers 7.17 and 7.18 to hard provision the autonegotiation extended next page that will be sent. Using this it is possible to hard-code the 1G and 10G capabilities, as well as short-reach capability. Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.13 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 Bit F:0 Name Unformatted Code Field 1 [1F:10] Description [F:0] = Unformatted Code Field 1 Type Default R/W PD 0x0000 Note Table 6.722 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 6.9.14 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 Unformatted Code Field 2 [2F:20] Description [F:0] = Unformatted Code Field 2 Type Default R/W PD 0x0000 Note Table 6.723 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 6.9.15 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 Bit Name Description Type F Link Partner Next Page 1 = Next page ability RO E Link Partner Extended Next Page Acknowledge 1 = Link Partner acknowledges receipt of corresponding page RO D Link Partner Message Page 1 = Message page 0 = Unformatted page RO Default Note Acknowledge is used by the autonegotiation function to indicate that a device has successfully received its link partners link code word. 443 Table 6.724 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential C Link Partner Acknowledge 2 1 = Link partner acknowledges that they can comply with the current next page 0 = Link partner cannot comply with the current next page RO B Link Partner Toggle Value of link partner's toggle bit RO Set to opposite of corresponding bit in previous page. Link Partner Message Code Field [A:0] [A:0] = Message Code Field: RO Interpreted as message code (see 802.3 Appendix 28C) if Message Page bit is set to one (7.16:1). Otherwise interpreted as an unformatted code field. A:0 0x0 = Reserved 0x1 = Null message 0x2 -> 0x3 Reserved Expansion message 0x4 = Remote fault details message 0x5 = OUI message 0x6 = PHY ID message 0x7 = 100BASE-T2 message 0x8 = 1000BASE-T message 0x9 = 10GBASE-T message Table 6.724 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 6.9.16 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A Bit F:0 Name Link Partner Unformatted Code Field 1 [F:0] Description [F:0] = Unformatted Code Field 1 [15:0] Type Default Note RO Table 6.725 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A This register, along with 7.1A and 7.1B, are used to store the received next pages. If an extended next page is used, it is stored in 7.19 -> 7.1B. Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.17 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B Bit F:0 Name Link Partner Unformatted Code Field 2 [F:0] Description [F:0] = Unformatted Code Field 2 [15:0] Type Default Note RO Table 6.726 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B 6.9.18 Autonegotiation 10GBASE-T Control Register: Address 7.20 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 F MASTER-SLAVE Manual Configuration Enable 1 = Enable MASTER-SLAVE Manual configuration 0 = Disable MASTER-SLAVE Manual configuration R/W PD 0 E MASTER-SLAVE Configuration 1 = MASTER 0 = SLAVE R/W PD 0 D Port Type 1 = Multiport device 0 = Single port device R/W PD 0 C 10GBASE-T Ability 1 = Advertise PHY as 10GBASE-T capable 0 = Do not advertise PHY as 10GBASE-T capable R/W PD 1 R/W PD 0 B:3 2 Reserved LD PMA Training Reset Request Note Internal reserved - do not modify Table 6.727 Autonegotiation 10GBASE-T Control Register: Address 7.20 445 1 = Local device requests that Link Partner reset PMA training PRBS every frame 0 = Local device requests that Link Partner run PMA training PRBS continuously Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 LD Fast Retrain Ability 1 = Advertise PHY as 10GBASE-T fast retrain capable 0 = Do not advertise PHY as 10GBASE-T fast retrain capable R/W PD 0 0 LD Loop Timing Ability 1 = Advertise PHY as capable of loop timing 0 = Do not advertise PHY as capable of loop timing R/W PD 1 Note Table 6.727 Autonegotiation 10GBASE-T Control Register: Address 7.20 6.9.19 Autonegotiation 10GBASE-T Status Register: Address 7.21 Bit Name Description Type Default Note F MASTER-SLAVE Configuration Fault 1 = MASTER-SLAVE configuration fault LH E MASTER-SLAVE Configuration Resolution 1 = Local PHY resolved to MASTER 0 = Local PHY resolved to SLAVE RO D Local Receiver Status 1 = Local receiver OK 0 = Local receiver not OK RO Set by microcontroller C Remote Receiver Status 1 = Remote receiver OK 0 = Remote receiver not OK RO Set by microcontroller B Link Partner 10GBASE-T Ability 1 = Link partner is 10GBASE-T capable 0 = Link partner is not 10GBASE-T capable RO This bit is only valid when the Page received bit 7.1.6 is set to 1. A Link Partner Loop Timing Ability 1 = Link partner is capable of loop timing 0 = Link partner is not capable of loop timing RO Table 6.728 Autonegotiation 10GBASE-T Status Register: Address 7.21 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 9 8:2 Name Description Link Partner Training Reset Request 1 = Link partner has requested that PMA PRBS training be reset every frame 0 = Link partner has requested that PMA PRBS training run continuously. Reserved 1 Link Partner Fast Retrain Ability 0 Reserved Type Default Note RO Internal reserved - do not modify 1 = Link partner is capable of 10GBASE-T fast retrain 0 = Link partner is not capable of 10GBASE-T fast retrain. RO Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 Table 6.728 Autonegotiation 10GBASE-T Status Register: Address 7.21 6.9.20 Autonegotiation EEE Advertisement Register: Address 7.3C Bit F:7 Name Description Reserved Type Default Note Internal reserved - do not modify 10GBASE-KR EEE 1 = Advertise that the 10GBASE-KR has EEE capability 0 = Do not advertise that the 10GBASE-KR has EEE capability R/W 0 5 10GBASE-KX4 EEE 1 = Advertise that the 10GBASE-KX4 has EEE capability 0 = Do not advertise that the 10GBASE-KX4 has EEE capability R/W 0 4 1000BASE-KX EEE 1 = Advertise that the 1000BASE-KX has EEE capability 0 = Do not advertise that the 1000BASE-KX has EEE capability R/W 0 Table 6.729 Autonegotiation EEE Advertisement Register: Address 7.3C 447 6 Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 3 10GBASE-T EEE 1 = Advertise that the 10GBASE-T has EEE capability 0 = Do not advertise that the 10GBASE-T has EEE capability R/W 1 2 1000BASE-T EEE 1 = Advertise that the 1000BASE-T has EEE capability 0 = Do not advertise that the 1000BASE-T has EEE capability R/W 1 1 100BASE-TX EEE 1 = Advertise that the 100BASE-TX has EEE capability 0 = Do not advertise that the 100BASE-TX has EEE capability R/W 0 0 Reserved Note Internal reserved - do not modify Table 6.729 Autonegotiation EEE Advertisement Register: Address 7.3C 6.9.21 Autonegotiation EEE Link Partner Ability Register: Address 7.3D Bit F:7 Name Description Reserved Type Default Internal reserved - do not modify 6 Link Partner 10GBASE-KR EEE 1 = Link partner is advertising that its 10GBASE-KR has EEE capability 0 = Link partner is advertising that its 10GBASE-KR does not have EEE capability RO 5 Link Partner 10GBASE-KX4 EEE 1 = Link partner is advertising that its 10GBASE-KX4 has EEE capability 0 = Link partner is advertising that its 10GBASE-KX4 does not have EEE capability RO Table 6.730 Autonegotiation EEE Link Partner Ability Register: Address 7.3D Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type 4 Link Partner 1000BASE-KX EEE 1 = Link partner is advertising that its 1000BASE-KX has EEE capability 0 = Link partner is advertising that its 1000BASE-KX does not have EEE capability RO 3 Link Partner 10GBASE-T EEE 1 = Link partner is advertising that its 10GBASE-T has EEE capability 0 = Link partner is advertising that its 10GBASE-T does not have EEE capability RO 2 Link Partner 1000BASE-T EEE 1 = Link partner is advertising that its 1000BASE-T has EEE capability 0 = Link partner is advertising that its 1000BASE-T does not have EEE capability RO 1 Link Partner 100BASE-TX EEE 1 = Link partner is advertising that its 100BASE-TX has EEE capability 0 = Link partner is advertising that its 100BASE-TX does not have EEE capability RO 0 Reserved Default Note Internal reserved - do not modify Table 6.730 Autonegotiation EEE Link Partner Ability Register: Address 7.3D 449 6.9.22 KR0 Autonegotiation Control: Address 7.C200 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:D C B:A 9 8:0 Name Description Type Default Reset 1 = Autonegotiation reset 0 = Normal operation R/W SC 1 Reserved 0 [1:0] Reserved for future use R/W PD 0x0 Autonegotiation Enable 1 = Enable autonegotiation 0 = Disable autonegotiation R/W PD 0 Reserved 1 [1:0] Reserved for future use R/W PD 0x0 Autonegotiation Restart 1 = Restart autonegotiation 0 = Normal operation R/W SC 0 Reserved 2 [8:0] Reserved for future use R/W PD 0x000 Note Table 6.731 KR0 Autonegotiation Control: Address 7.C200 6.9.23 KR0 Autonegotiation Status: Address 7.C201 Bit F:A 9 Name Description Type Default 0x00 Reserved 0 [5:0] Reserved for future use R/W PD Parallel Detection Fault 1 = Fault detected 0 = No fault detected LH Table 6.732 KR0 Autonegotiation Status: Address 7.C201 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default 0x0 AQR405 Revision 0.11 - January 5, 2015 8:7 Reserved 1 [1:0] Reserved for future use R/W PD 6 Page Received 1 = A new DME page has been received 0 = Normal operation LH 5 Autonegotiation Complete 1 = Autonegotiation complete 0 = Normal operation LH 4 Reserved 2 Reserved for future use R/W PD 0 3 Autonegotiation Ability 1 = PHY is able to perform autonegotiation 0 = PHY is not able to perform autonegotiation ROS 1 Reserved 3 [1:0] Reserved for future use R/W PD 0x0 Link Partner Autonegotiation Ability 1 = Link partner is able to perform autonegotiation 0 = Link partner is not able to perform autonegotiation ROS 0 2:1 0 Note Always set as 1 as the local device has autonegotiation ability. Table 6.732 KR0 Autonegotiation Status: Address 7.C201 451 6.9.24 KR0 Autonegotiation Advertisement Word 1: Address 7.C210 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F Next Page 1 = Next page ability 0 = Next page ability not supported or not engaged R/W PD 0 E Acknowledge 1 = Acknowledge 0 = No fault detected R/W PD 0 The Acknowledge (Ack) is used by the Autonegotiation function to indicate that a device has successfully received its Link Partner's Link Code Word. D Remote Fault 1 = Remote fault R/W 0 The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. C Reserved 0 Reserved for future use R/W PD 0 Pause Capability [1:0] Bit B: PAUSE operation for full duplex links Bit A: Asymmetric PAUSE operation for full duplex links R/W PD 0x0 B:A Table 6.733 KR0 Autonegotiation Advertisement Word 1: Address 7.C210 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default 9:5 Echoed Nonce [4:0] Echoed nonce R/W PD 0x00 4:0 Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved R/W PD 0x01 Note This field should always be set to 0x01 as the PHY is only capable of handling 802.3 Ethernet. AQR405 Revision 0.11 - January 5, 2015 Table 6.733 KR0 Autonegotiation Advertisement Word 1: Address 7.C210 6.9.25 KR0 Autonegotiation Advertisement Word 2: Address 7.C211 Bit F:8 Name Description Type Default Reserved for future technology R/W PD 0x00 7 Technology Ability Bit A2 1 = 10GBASE-KR is supported 0 = 10GBASE-KR is not supported R/W PD 1 6 Technology Ability Bit A1 1 = 10GBASE-KX4 is supported 0 = 10GBASE-KX4 is not supported R/W PD 0 5 Technology Ability Bit A0 1 = 10GBASE-KX is supported 0 = 10GBASE-KX is not supported R/W PD 1 4:0 Transmitted Nonce [4:0] Transmitted nonce R/W PD 0x00 Table 6.734 KR0 Autonegotiation Advertisement Word 2: Address 7.C211 453 Technology Ability Bits A3 to A10 [7:0] Note 6.9.26 KR0 Autonegotiation Advertisement Word 3: Address 7.C212 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default F FEC Requested 1 = Enable 10GBASE-KR FEC ability. 0 = Disable 10GBASE-KR FEC ability. R/W PD 0 E FEC Ability 1 = 10GBASE-KR PHY has FEC capability. 0 = 10GBASE-KR PHY does not have FEC capability. R/W PD 0 Technology Ability Bits A11 to A24 [D:0] Reserved for future technology R/W PD 0x0000 D:0 Note Table 6.735 KR0 Autonegotiation Advertisement Word 3: Address 7.C212 6.9.27 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 Bit Name Description Type F Link Partner Next Page 1 = Next page ability 0 = Next page ability not supported or not engaged RO E Link Partner Acknowledge 1 = Acknowledge 0 = No fault detected RO Default Note The Acknowledge (Ack) is used by the Autonegotiation function to indicate that a device has successfully received its Link Partner's Link Code Word. Table 6.736 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 D Link Partner Remote Fault 1 = Remote fault RO C Reserved 0 Reserved for future use RO B:A Link Partner Pause Capability [1:0] Bit B: PAUSE operation for full duplex links Bit A: Asymmetric PAUSE operation for full duplex links RO 9:5 Link Partner Echoed Nonce [4:0] Echoed nonce RO 4:0 Link Partner Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved RO Default Note The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. This field should always be set to 0x01 as the PHY is only capable of handling 802.3 Ethernet. Table 6.736 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 455 6.9.28 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type F:8 Link Partner Technology Ability bits A3 to A10 [7:0] Reserved for future technology RO 7 Link Partner Technology Ability bit A2 1 = 10GBASE-KR is supported 0 = 10GBASE-KR is not supported RO 6 Link Partner Technology Ability bit A1 1 = 10GBASE-KX4 is supported 0 = 10GBASE-KX4 is not supported RO 5 Link Partner Technology Ability Bit A0 1 = 10GBASE-KX is supported 0 = 10GBASE-KX is not supported RO 4:0 Link Partner Transmitted Nonce [4:0] Transmitted nonce RO Default Note Table 6.737 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.29 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 F Link Partner FEC Requested 1 = Enable 10GBASE-KR FEC ability. 0 = Disable 10GBASE-KR FEC ability. RO E Link Partner FEC Ability 1 = 10GBASE-KR PHY has FEC capability. 0 = 10GBASE-KR PHY does not have FEC capability. RO D:0 Link Partner Technology Ability Bits A11 to A24 [D:0] Reserved for future technology RO Default Note Table 6.738 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 6.9.30 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216 Bit F:0 Name Extended Next Page 0 [F:0] Description Extended next page bits [F:0] Type Default R/W PD 0x0000 Note Table 6.739 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216 457 6.9.31 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Extended Next Page 1 [1F:10] Description Extended next page bits [1F:10] Type Default R/W PD 0x0000 Note Table 6.740 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217 6.9.32 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218 Bit F:0 Name Extended Next Page 2 [2F:20] Description Extended next page bits [2F:20] Type Default R/W PD 0x0000 Note Table 6.741 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218 6.9.33 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 Bit F:0 Name Link Partner Extended Next Page 0 [F:0] Description Extended next page bits [F:0] Type Default Note RO Table 6.742 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 6.9.34 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A Bit F:0 Name Link Partner Extended Next Page 1 [1F:10] Description Extended next page bits [1F:10] Type Default Note RO Table 6.743 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.35 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B Bit F:0 Name Link Partner Extended Next Page 2 [2F:20] Description Extended next page bits [2F:20] Type Default Note RO Table 6.744 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B 6.9.36 KR1 Autonegotiation Control: Address 7.C300 Bit F AQR405 Revision 0.11 - January 5, 2015 E:D C B:A 9 8:0 Name Description Type Default Reset 1 = Autonegotiation reset 0 = Normal operation R/W SC 1 Reserved 0 [1:0] Reserved for future use R/W PD 0x0 Autonegotiation Enable 1 = Enable autonegotiation 0 = Disable autonegotiation R/W PD 0 Reserved 1 [1:0] Reserved for future use R/W PD 0x0 Autonegotiation Restart 1 = Restart autonegotiation 0 = Normal operation R/W SC 0 Reserved 2 [8:0] Reserved for future use R/W PD 0x000 Note Table 6.745 KR1 Autonegotiation Control: Address 7.C300 459 6.9.37 KR1 Autonegotiation Status: Address 7.C301 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:A Name Description Type Default 0x00 Reserved 0 [5:0] Reserved for future use R/W PD Parallel Detection Fault 1 = Fault detected 0 = No fault detected LH 8:7 Reserved 1 [1:0] Reserved for future use R/W PD 6 Page Received 1 = A new DME page has been received 0 = Normal operation LH 5 Autonegotiation Complete 1 = Autonegotiation complete 0 = Normal operation LH 4 Reserved 2 Reserved for future use R/W PD 0 3 Autonegotiation Ability 1 = PHY is able to perform autonegotiation 0 = PHY is not able to perform autonegotiation ROS 1 Reserved 3 [1:0] Reserved for future use R/W PD 0x0 Link Partner Autonegotiation Ability 1 = Link partner is able to perform autonegotiation 0 = Link partner is not able to perform autonegotiation ROS 0 9 2:1 0 Note 0x0 Always set as 1 as the local device has autonegotiation ability. Table 6.746 KR1 Autonegotiation Status: Address 7.C301 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.38 KR1 Autonegotiation Advertisement Word 1: Address 7.C310 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F Next Page 1 = Next page ability 0 = Next page ability not supported or not engaged R/W PD 0 E Acknowledge 1 = Acknowledge 0 = No fault detected R/W PD 0 The Acknowledge (Ack) is used by the Autonegotiation function to indicate that a device has successfully received its Link Partner's Link Code Word. D Remote Fault 1 = Remote fault R/W 0 The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. C Reserved 0 Reserved for future use R/W PD 0 Pause Capability [1:0] Bit B: PAUSE operation for full duplex links Bit A: Asymmetric PAUSE operation for full duplex links R/W PD 0x0 B:A Table 6.747 KR1 Autonegotiation Advertisement Word 1: Address 7.C310 461 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 9:5 Echoed Nonce [4:0] Echoed nonce R/W PD 0x00 4:0 Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved R/W PD 0x01 Note This field should always be set to 0x01 as the PHY is only capable of handling 802.3 Ethernet. Table 6.747 KR1 Autonegotiation Advertisement Word 1: Address 7.C310 6.9.39 KR1 Autonegotiation Advertisement Word 2: Address 7.C311 Bit F:8 Name Description Type Default Technology Ability Bits A3 to A10 [7:0] Reserved for future technology R/W PD 0x00 7 Technology Ability Bit A2 1 = 10GBASE-KR is supported 0 = 10GBASE-KR is not supported R/W PD 1 6 Technology Ability Bit A1 1 = 10GBASE-KX4 is supported 0 = 10GBASE-KX4 is not supported R/W PD 0 5 Technology Ability Bit A0 1 = 10GBASE-KX is supported 0 = 10GBASE-KX is not supported R/W PD 1 4:0 Transmitted Nonce [4:0] Transmitted nonce R/W PD 0x00 Table 6.748 KR1 Autonegotiation Advertisement Word 2: Address 7.C311 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.40 KR1 Autonegotiation Advertisement Word 3: Address 7.C312 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 F FEC Requested 1 = Enable 10GBASE-KR FEC ability. 0 = Disable 10GBASE-KR FEC ability. R/W PD 0 E FEC Ability 1 = 10GBASE-KR PHY has FEC capability. 0 = 10GBASE-KR PHY does not have FEC capability. R/W PD 0 Technology Ability Bits A11 to A24 [D:0] Reserved for future technology R/W PD 0x0000 D:0 Note Table 6.749 KR1 Autonegotiation Advertisement Word 3: Address 7.C312 6.9.41 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 Bit Name Description Type F Link Partner Next Page 1 = Next page ability 0 = Next page ability not supported or not engaged RO E Link Partner Acknowledge 1 = Acknowledge 0 = No fault detected RO Default Note The Acknowledge (Ack) is used by the Autonegotiation function to indicate that a device has successfully received its Link Partner's Link Code Word. 463 Table 6.750 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 Bit Name Description Type Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 D Link Partner Remote Fault 1 = Remote fault RO C Reserved 0 Reserved for future use RO B:A Link Partner Pause Capability [1:0] Bit B: PAUSE operation for full duplex links Bit A: Asymmetric PAUSE operation for full duplex links RO 9:5 Link Partner Echoed Nonce [4:0] Echoed nonce RO 4:0 Link Partner Selector Field [4:0] This defines the device compatibility: 0x00 = Reserved 0x01 = IEEE 802.3 0x02 = IEEE 802.9 ISLAN-16T 0x03 = IEEE 802.5 0x04 = IEEE 1394 0x05 -> 0x1F = Reserved RO Default Note The remote fault bit provides a standard transport mechanism for the transmission of simple fault information. When the RF bit in the received base link code word is set to 1, the RF bit will be set to 1. This field should always be set to 0x01 as the PHY is only capable of handling 802.3 Ethernet. Table 6.750 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.42 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type F:8 Link Partner Technology Ability Bits A3 to A10 [7:0] Reserved for future technology RO 7 Link Partner Technology Ability Bit A2 1 = 10GBASE-KR is supported 0 = 10GBASE-KR is not supported RO 6 Link Partner Technology Ability Bit A1 1 = 10GBASE-KX4 is supported 0 = 10GBASE-KX4 is not supported RO 5 Link Partner Technology Ability Bit A0 1 = 10GBASE-KX is supported 0 = 10GBASE-KX is not supported RO 4:0 Link Partner Transmitted Nonce [4:0] Transmitted nonce RO Default Note Table 6.751 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 465 6.9.43 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type F Link Partner FEC Requested 1 = Enable 10GBASE-KR FEC ability. 0 = Disable 10GBASE-KR FEC ability. RO E Link Partner FEC Ability 1 = 10GBASE-KR PHY has FEC capability. 0 = 10GBASE-KR PHY does not have FEC capability. RO D:0 Link Partner Technology Ability Bits A11 to A24 [D:0] Reserved for future technology RO Default Note Table 6.752 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 6.9.44 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316 Bit F:0 Name Extended Next Page 0 [F:0] Description Extended next page bits [F:0] Type Default R/W PD 0x0000 Note Table 6.753 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.9.45 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317 Bit F:0 Name Extended Next Page 1 [1F:10] Description Extended next page bits [1F:10] Type Default R/W PD 0x0000 Note Table 6.754 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317 6.9.46 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 Extended Next Page 2 [2F:20] Description Extended next page bits [2F:20] Type Default R/W PD 0x0000 Note Table 6.755 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318 6.9.47 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 Bit F:0 Name Link Partner Extended Next Page 0 [F:0] Description Extended next page bits [F:0] Type Default Note RO Table 6.756 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 6.9.48 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A Bit Link Partner Extended Next Page 1 [1F:10] Description Extended next page bits [1F:10] Type Default Note RO Table 6.757 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A 467 F:0 Name 6.9.49 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Description Link Partner Extended Next Page 2 [2F:20] Extended next page bits [2F:20] Type Default Note RO Table 6.758 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B 6.9.50 Autonegotiation Vendor Provisioning 1: Address 7.C400 Bit Name Description Type Default F 1000BASE-T Full Duplex Ability 1 = Advertise PHY as 1000BASE-T Full Duplex capable 0 = Do not advertise PHY as 1000BASE-T Full Duplex capable R/W PD 0 E 1000BASE-T Half Duplex Ability 1 = Advertise PHY as 1000BASE-T Half Duplex capable 0 = Do not advertise PHY as 1000BASE-T Half Duplex capable R/W PD 0 D Short-Reach 1 = Advertise PHY as operating in short-reach mode 0 = Do not advertise PHY as operating in short-reach mode R/W PD 0 C AQRate Downshift Capability 1 = Advertise PHY as supporting AQRate fast-retrain downshift mechanism 0 = Do not advertise PHY as supporting AQRate fast-retrain downshift mechanism R/W PD 0 Table 6.759 Autonegotiation Vendor Provisioning 1: Address 7.C400 Note Bit Name Description Type Default Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 B 5G 1 = Advertise PHY as supporting 5G 0 = Do not advertise PHY as supporting 5G R/W PD 0 A 2.5G 1 = Advertise PHY as supporting 2.5G 0 = Do not advertise PHY as supporting 2.55G R/W PD 0 Reserved1 [2:0] Reserved for future use R/W PD 0x0 6 Exchange PHY ID Information 1 = Exchange PHY ID Information R/W PD 1 5 User Provided Autonegotiation Data 1 = User provides the next page or extended next page data directly (7.16 -> 7.18), and the configuration info in 7.20 and 7.C400 is ignored. 0 = Construct the correct autonegotiation words based on the register settings of 7.10, 7.20, and 7.C400 R/W PD 0 Automatic Downshift Enable 1 = Enable automatic downshift 0 = Manual downshift R/W PD 1 Retry Attempts Before Downshift [3:0] Number of retry attempts before downshift R/W PD 0x4 9:7 4 3:0 Note If this bit is set, the PHY will attempt to use the user provided autonegotiation words. If there is a mismatch (such as a legacy 1GBASE-T device attempting connect), the PHY will then attempt to construct a new set of autonegotiation words from the data provided in these words. Otherwise, the PHY will construct the correct autonegotiation words based on the provisioned values. If Automatic Downshifting is enabled, this is the number of retry attempts the PHY will make to connect at the maximum mutually acceptable rate, before removing this rate from the list and trying the next lower rate. 469 Table 6.759 Autonegotiation Vendor Provisioning 1: Address 7.C400 6.9.51 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:D Name SERDES Start-Up Mode [2:0] Description Type Default The state up mode of the MAC interface: R/W PD 0x0 0x0 = Selected 10G interface on with automatic rate select 0x1 = Reserved 0x2 = SGMII on with automatic rate select and SGMII autonegotiation (XSGMII mode) 0x3 = USXGMII Mode 0x4 = 1000BASE-X on with automatic rate select and no SGMII autonegotiation 0x5 = Reserved 0x6 = All interfaces off with automatic rate select 0x7 = Reserved Note This sets the start-up mode for the MAC interface. In all scenarios, the AQR405 sets the interface rate based on the autonegotiated line rate. The interface selection controls are in 4.C441. NOTE! USXGMII requires KR to be selected in 4.C441, and when selected it will be used for all rates. C:B Reserved Provisioning 0 [1:0] Reserved for future use R/W PD 0x0 A:8 Semi-Cross Link Attempt Period [2:0] Number of failed link attempts before trying semi cross R/W PD 0x0 Set to zero (0) to disable semi-cross. Set to 0x7 to always use semi-cross. 7 WoL Mode 0 = 100BASE-TX 1 = 1000BASE-T R/W PD 0 This bit indicates whether the AQR405 is going to go into 100BASE-TX or 1000BASE-T Wake-On-LAN operation. 6 WoL Enable 1 = Enable Wake-On-LAN operation 0 = Normal Operation R/W PD 0 Setting this bit enables Wake-On-LAN operation. In this state, power is minimized by turning all interfaces except the MDI receive path and the MDIO interface off. Table 6.760 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default 5:2 1:0 Note Extra Page Count [3:0] Number of extra pages to send at end of auto-negotiation sequence when link partner is legacy gigabit PHY. R/W PD 0x0 Intervals between pages for GbE PHYs may be much longer. When this is the case, the link partner may still be in auto-negotiation when the AQR405 has started training. This may confuse the link partner MDI/MDI-X state machine. Sending extra pages seems to solve this problem. MDI / MDI-X Control [1:0] 0x0 = Automatic MDI / MDI-X operation 0x1 = Manual MDI 0x2 = Manual MDI-X 0x3 = Reserved R/W PD 0x0 These bits are used to force a manual MDI or MDI-X configuration Table 6.760 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 AQR405 Revision 0.11 - January 5, 2015 471 6.9.52 Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:C Autonegotiation Timeout [3:0] The length of time in (seconds*2) before autonegotiation restarts. Valueof zero indicates there is no timeout. R/W PD 0x0 These bits control the use of autonegotiation timeout watchdog during the Arbit state machine B Autonegotiation Timeout Mode 0 = Enable timeout for all autonegotiation behavior 1 = Enable timeout only if the following are enabled: LPLU, downshifting R/W PD 0 The timeout behavior can be described as follows: Bits F:C = non-zero, Bit B = 0: Timeout exists for all autonegotiation behavior, including LPLU and if downshift is enabled. Bits F:C = 0, Bit B = 0: No timeout enabled Bits F:C = non-zero, Bit B = 1: If we are in LPLU or downshift is enabled, timeout exists. If we are not in LPLU or downshift is not enabled, there is no timeout. Bits F:C = 0, Bit B = 1: If we are in LPLU or downshift is enabled, there is no timeout. If we are not in LPLU or downshift is not enabled, there is no timeout. IE, there is no timeout. A:0 Reserved Internal reserved - do not modify Table 6.761 Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 6.9.53 Autonegotiation Vendor Status 1: Address 7.C800 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F:4 Reserved 3:1 Connect Rate [2:0] The rate the PHY connected or attempting to connect at: 0x5 = 5G 0x4 = 2.5G 0x3 = 10GBASE-T 0x2 = 1000BASE-T 0x1 = 100BASE-TX 0x0 = 10BASE-T RO This field is used in conjunction with Connection State in "Autonegotiation Reserved Vendor Status 1: Address 7.C810" to indicated the rate the PHY is connected or attempting to connect at. 0 Connect Type The duplex method the PHY connected or attempting to connect at: RO This field is used in conjunction with Connection State in "Autonegotiation Reserved Vendor Status 1: Address 7.C810" to indicated the duplex method the PHY is connected or attempting to connect at. Internal reserved - do not modify 1 = Full Duplex 0 = Half-Duplex Table 6.762 Autonegotiation Vendor Status 1: Address 7.C800 473 6.9.54 Autonegotiation Reserved Vendor Status 1: Address 7.C810 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name F Energy On Line 1 = Energy detected on line 0 = No energy detected on line RO This bit is used to indicate that the PHY has detected energy on the line. Specifically, when MDI/MDI-X resolution has completed, this bit is true. This bit will be set false before entering autonegotiation. E Device Present 1 = Far-end Ethernet device present 0 = No far-end Ethernet device detected RO If true, a far-end Ethernet device exists, as valid link pulses have been detected in the most recent autonegotiation session, or a valid Ethernet connection has been established. If false, no connection is established, and the most recent attempt at autonegotiation failed to detect any valid link pulses. Specifically, when MDI/MDI-X resolution has completed, this bit is true. This bit will be set false before entering autonegotiation. Connection State [4:0] The current state of the connection: 0x00 = Inactive (i.e. high-impedance) 0x01 = Cable diagnostics 0x02 = Autonegotiation 0x03 = Training (10G, 5G, 2.5G and 1G only) 0x04 = Connected 0x05 = Fail (Autonegotiation Break Link) 0x06 = Test Mode 0x07 = Loopback Mode 0x08 = Low Power Mode 0x09 = Connected Wake-On-LAN Mode 0x0A = System Calibrating 0x0B = Cable Disconnected 0x0C -> 0x1E = Reserved 0x1F = Invalid RO This field is used in conjunction with Connect Rate and Connect Type in "Autonegotiation Vendor Status 1: Address 7.C800" to indicated the current state the PHY is in. D:9 Description Type Default Note Table 6.763 Autonegotiation Reserved Vendor Status 1: Address 7.C810 Bit Name Description Type Default Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 8 MDI/MDI-X 0 = MDI 1 = MDI-X RO When autonegotiation is completed, this register indicates whether the connection was made as an MDI or MDI-X connection. 7 Duplicate Link Partner Autonegotiation Ability Link Partner is capable of Autonegotiation. RO This is a duplicate of the bit at 07.0001.0. 6:2 Reserved Status 1 [6:2] Reserved for future use RO 1 Receive PAUSE Resolution 1 = Receive PAUSE Enabled 0 = Receive PAUSE Disabled RO 0 Transmit PAUSE Resolution 1 = Transmit PAUSE Enabled 0 = Transmit PAUSE Disabled RO PAUSE resolution from 28B-3 Table 6.763 Autonegotiation Reserved Vendor Status 1: Address 7.C810 6.9.55 Autonegotiation Reserved Vendor Status 2: Address 7.C811 Bit Name Description F:0 Autonegotiation Attempts [F:0] The number of autonegotiation attempts since the last successful connection (or power-up) Type RO Default Note This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset, or the completion of a successful connection. Table 6.764 Autonegotiation Reserved Vendor Status 2: Address 7.C811 475 6.9.56 Autonegotiation Reserved Vendor Status 3: Address 7.C812 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type F Link Pulse Detected Status 1 = Link Pulse Detected 0 = Link Pulse not Detected RO E:0 Reserved State 3 [E:0] Reserved for future use RO Default Note Table 6.765 Autonegotiation Reserved Vendor Status 3: Address 7.C812 6.9.57 Autonegotiation Reserved Vendor Status 4: Address 7.C813 Bit Name Description F:0 Autonegotiation Restarts Handled [F:0] The number of line-side autonegotiation restart commands received. Type Default Note This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. RO Table 6.766 Autonegotiation Reserved Vendor Status 4: Address 7.C813 6.9.58 Autonegotiation Reserved Vendor Status 5: Address 7.C814 Bit Name Description F:0 Autonegotiation Attempts Since Reset [F:0] The number of autonegotiation attempts since the last PHY reset (or power-up). Type RO Default Note Increments when the line-side goes back to `break-link' state and then re-negotiates. This is a rolling counter (i.e. upon saturation it reverts to zero). It is cleared upon reset. Table 6.767 Autonegotiation Reserved Vendor Status 5: Address 7.C814 6.9.59 Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:4 Name Description Reserved Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 3 Autonegotiation Completed For Non-supported Rate 1 = Autonegotiation has completed for a rate that is not supported by the AQR405 LH 2 Autonegotiation Completed for Supported Rate 1 = Autonegotiation has completed successfully for a rate that is supported by the AQR405 LH 1 Automatic Downshift 1 = Automatic downshift has occurred LH 0 Connection State Change 1 = The connection state has changed LH This means that the AQR405 has completed autonegotiation, and was unable to agree on a rate that both could operate at. Indication should be ignored in case of Master/Slave resolution fault This interrupt indicates a change in Connection State [D:B] in "Autonegotiation Reserved Vendor Status 1: Address 7.C810" on page 474. Note that this indicates any state change, versus 7.CC01.0 which indicates a connect or disconnect event. Table 6.768 Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 6.9.60 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 Bit F Name Link Pulse Detect Description 1 = Link Pulse Detected Type Default Note LH Table 6.769 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 477 Bit E:1 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 0 Name Description Type Reserved Vendor Alarms 2 [D:0] Reserved for future use LH Link Connect / Disconnect 1 = MDI Link has either connected or disconnected LH Default Note This indicates whether the link has achieved a connect state, or was in a connect state and disconnected. Table 6.769 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 6.9.61 Autonegotiation Standard Interrupt Mask 1: Address 7.D000 Bit F:A 9 8:7 Name Description Reserved Parallel Detection Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 R/W PD 0 R/W PD 0 R/W PD 0 Internal reserved - do not modify Reserved Extended Next Page Received Mask 5 Reserved 4 Remote Fault Mask 3 Reserved 2 Link Status Mask Reserved Default Internal reserved - do not modify 6 1:0 Type 1 = Enable interrupt generation 0 = Disable interrupt generation Internal reserved - do not modify 1 = Enable interrupt generation 0 = Disable interrupt generation Internal reserved - do not modify 1 = Enable interrupt generation 0 = Disable interrupt generation Internal reserved - do not modify Table 6.770 Autonegotiation Standard Interrupt Mask 1: Address 7.D000 Note 6.9.62 Autonegotiation Standard Interrupt Mask 2: Address 7.D001 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F E:0 Name Description MASTER-SLAVE Configuration Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Reserved Type Default R/W PD 0 Note Internal reserved - do not modify Table 6.771 Autonegotiation Standard Interrupt Mask 2: Address 7.D001 6.9.63 Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 Bit F:4 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 3 Autonegotiation Completed For Non-supported Rate Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 2 Autonegotiation Completed for Supported Rate Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 Automatic Downshift Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 Connection State Change Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.772 Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 479 6.9.64 Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:1 0 Name Description Type Default Link Pulse Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Vendor Alarms 2 Mask [D:0] Reserved for future use R/W PD 0x0000 Link Connect / Disconnect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note Table 6.773 Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 6.9.65 Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.774 Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 Note 6.9.66 Autonegotiation Receive Link Partner Status 1: Address 7.E820 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 F Link Partner 1000BASE-T Full Duplex Ability 1 = Link Partner is 1000BASE-T Full Duplex capable 0 = Link Partner is not 1000BASE-T Full Duplex capable RO E Link Partner 1000BASE-T Half Duplex Ability 1 = Link Partner is 1000BASE-T Half-Duplex capable 0 = Link Partner is not 1000BASE-T Half-Duplex capable RO D Link Partner Short-Reach 1 = Link Partner is operating in short-reach mode 0 = Link Partner is not operating in short-reach mode RO C Link Partner AQRate Downshift Capability 1 = Link Partner PHY supports AQRate fast-retrain downshift mechanism 0 = Link Partner PHY does not support AQRate fast-retrain downshift mechanism R/W PD 0 B Link Partner 5G 1 = Link Partner PHY is 5G capable 0 = Link Partner PHY is not 5G capable R/W PD 0 A Link Partner 2.5G 1 = Link Partner PHY is 5G capable 0 = Link Partner PHY is not 5G capable R/W PD 0 Reserved2 [6:0] Reserved for future use RO Aquantia Link Partner 1 = Link Partner is an Aquantia PHY 0 = Link Partner is not an Aquantia PHY RO 9:3 2 1:0 Reserved Note Internal reserved - do not modify Table 6.775 Autonegotiation Receive Link Partner Status 1: Address 7.E820 481 6.9.67 Autonegotiation Receive Link Partner Status 2: Address 7.E821 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.776 Autonegotiation Receive Link Partner Status 2: Address 7.E821 6.9.68 Autonegotiation Receive Link Partner Status 3: Address 7.E822 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.777 Autonegotiation Receive Link Partner Status 3: Address 7.E822 6.9.69 Autonegotiation Receive Link Partner Status 4: Address 7.E823 Bit Name Description Type F:8 Link Partner Firmware Major Revision Number [7:0] [F:8] = Link partner firmware major revision number RO 7:0 Link Partner Firmware Minor Revision Number [7:0] [7:0] = Link partner firmware minor revision number RO Default Note Only the lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. Consequently the upper 2 bits of the major and minor revision should always be zero. Table 6.778 Autonegotiation Receive Link Partner Status 4: Address 7.E823 6.9.70 Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F:C Link Attempts[3:0] Number of attempts needed to establish current link RO RW Once a link has been established, save the total number of auto-negotiation and training sequence passes. B:9 Link Partner PHY Tag [2:0] When the link partner is Aquantia and PHY ID pages have been exchanged this field contains the vendor specific link partner PHY tag value RO RW This field is only valid if the link partner is Aquantia and PHY ID link pages have been exchanged during Autonegotiation. 8:0 Reserved Receive Status 1 [8:0] Reserved for future use RO Table 6.779 Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 AQR405 Revision 0.11 - January 5, 2015 6.9.71 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 Bit F:E D Name Description Reserved Type Default Note Internal reserved - do not modify Autonegotiation Protocol Error State 1 = Link partner has violated the Autonegotation protocol RO This is the state bit associated with "Autonegotiation Protocol Error" (See "Autonegotiation Receive Vendor Alarms 2: Address 7.EC01" on page 485.) Table 6.780 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 483 Bit C AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential B:0 Name Description Type Default Note FLP Idle Error State 1 = No FLP Burst has been seen for 50 milliseconds forcing the receive state machine back to the Idle state RO This is the state bit associated with "FLP Idle Error" (See "Autonegotiation Receive Vendor Alarms 2: Address 7.EC01" on page 485.) Reserved Receive State 2 [B:0] Reserved for future use RO This is the state bit associated with "Reserved Receive Vendor Alarms 2 [B:0]" (See "Autonegotiation Receive Vendor Alarms 2: Address 7.EC01" on page 485.) Table 6.780 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 6.9.72 Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 Bit Name F:1 Reserved Receive State 3 [E:0] Reserved for future use RO Link Partner AFR Enabled 1 = The link partner has Aquantia Fast Reframe capability enabled RO 0 Description Type Default Note Table 6.781 Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 6.9.73 Autonegotiation Receive Vendor Alarms 1: Address 7.EC00 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.782 Autonegotiation Receive Vendor Alarms 1: Address 7.EC00 Note 6.9.74 Autonegotiation Receive Vendor Alarms 2: Address 7.EC01 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit F:E Name Description Reserved Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 D Autonegotiation Protocol Error 1 = Link partner has violated the Autonegotation protocol LH If the Arbiter state machine detects a protocol violation, the Autonegotiation process resets itself and goes back to the "break link" state. C FLP Idle Error 1 = No FLP Burst has been seen for 50 milliseconds forcing the receive state machine back to the Idle state LH Once FLP bursts are detected on any receive channel, they must keep coming. If no burst has been detected for a period of 50 milliseconds, the Autonegotiation process resets itself and goes back to the "break link" state. Reserved Receive Vendor Alarms 2 [B:0] Reserved for future use LH B:0 Table 6.783 Autonegotiation Receive Vendor Alarms 2: Address 7.EC01 6.9.75 Autonegotiation Receive Vendor Alarms 3: Address 7.EC02 Bit F:3 2 1:0 Name Reserved 10BASE-T Device Detect Reserved Description Type Default Note Internal reserved - do not modify 0 = 10BASE-T device detected LL This bit indicates that the detected far-end device is 10BASE-T when it is 0. This bit is 1 when link pulses are no longer received Internal reserved - do not modify Table 6.784 Autonegotiation Receive Vendor Alarms 3: Address 7.EC02 485 6.9.76 Autonegotiation Receive Vendor Alarms 4: Address 7.EC03 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type F:1 Reserved Receive Vendor Alarms 4 [E:0] Reserved LH 0 100BASE-TX Parallel Detect 1 = 100BASE-TX parallel event detection occurred LH Default Note Table 6.785 Autonegotiation Receive Vendor Alarms 4: Address 7.EC03 6.9.77 Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 Bit F:0 Name Description Reserved Receive Vendor Alarms 1 Mask [F:0] 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0x0000 Note Table 6.786 Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 6.9.78 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 Bit F:E D Name Description Reserved Type Default R/W PD 0 Note Internal reserved - do not modify Autonegotiation Protocol Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Table 6.787 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 Bit C Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential B:0 Name Description Type Default FLP Idle Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Receive Vendor Alarms 2 Mask [B:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x000 Note Table 6.787 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 6.9.79 Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 Bit F:3 2 AQR405 Revision 0.11 - January 5, 2015 1:0 Name Description Reserved Type Default R/W PD 0 Note Internal reserved - do not modify 10BASE-T Device Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Internal reserved - do not modify Reserved Table 6.788 Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 6.9.80 Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 Bit F:1 0 Name Description Type Default Reserved Receive Vendor Alarms 4 Mask [E:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0000 100BASE-TX Parallel Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note 487 Table 6.789 Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 6.9.81 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name F Standard Alarms 1 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Standard Status 1: Address 7.1" on page 434.) and the corresponding mask register (See "Autonegotiation Standard Interrupt Mask 1: Address 7.D000" on page 478.). E Standard Alarms 2 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation 10GBASE-T Status Register: Address 7.21" on page 446.) and the corresponding mask register (See "Autonegotiation Standard Interrupt Mask 2: Address 7.D001" on page 479.). D:B Description Reserved Type Default Note Internal reserved - do not modify A Vendor Specific Alarms 1 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00" on page 477.) and the corresponding mask register (See "Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400" on page 479.). 9 Vendor Specific Alarms 2 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01" on page 477.) and the corresponding mask register (See "Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401" on page 480.). 8:4 Reserved Internal reserved - do not modify Table 6.790 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note 3 Vendor Specific Rx Alarms 1 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Receive Vendor Alarms 1: Address 7.EC00" on page 484.) and the corresponding mask register (See "Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400" on page 486.). 2 Vendor Specific Rx Alarms 2 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Receive Vendor Alarms 2: Address 7.EC01" on page 485.) and the corresponding mask register (See "Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401" on page 486.). 1 Vendor Specific Rx Alarms 3 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Receive Vendor Alarms 3: Address 7.EC02" on page 485.) and the corresponding mask register (See "Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402" on page 487.). 0 Vendor Specific Rx Alarms 4 Interrupt 1 = Interrupt RO An interrupt was generated from status register (See "Autonegotiation Receive Vendor Alarms 4: Address 7.EC03" on page 486.) and the corresponding mask register (See "Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403" on page 487.). Table 6.790 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 489 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10 100BASE-TX and 1000BASE-T Registers 6.10.1 GbE Standard Device Identifier 1: Address 1D.2 Bit Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default Note RO Table 6.791 GbE Standard Device Identifier 1: Address 1D.2 6.10.2 GbE Standard Device Identifier 2: Address 1D.3 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.792 GbE Standard Device Identifier 2: Address 1D.3 6.10.3 GbE Standard Devices in Package 1: Address 1D.5 Bit F:8 Name Reserved Description Type Default Note Internal reserved - do not modify Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package ROS 1 This is always set to 1, as there is Autonegotiation in the AQR405. 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. Table 6.793 GbE Standard Devices in Package 1: Address 1D.5 491 7 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name 5 DTE XS Present 4 Description Type Default Note 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no MAC XAUI interface in the AQR405. Control Present 1 = Control is present in package 0 = Control is not present in package ROS 1 This is always set to 1 as there is a PHY XAUI interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.793 GbE Standard Devices in Package 1: Address 1D.5 6.10.4 GbE Standard Vendor Devices in Package 2: Address 1D.6 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the global control registers. Table 6.794 GbE Standard Vendor Devices in Package 2: Address 1D.6 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default ROS 1 D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package C:0 Reserved Internal reserved - do not modify Note This is always set to 1 as the AQR405 utilizes this device for the global control registers. Table 6.794 GbE Standard Vendor Devices in Package 2: Address 1D.6 6.10.5 GbE Standard Status 2: Address 1D.8 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:E Device Present [1:0] [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address D:0 Reserved Internal reserved - do not modify Type Default ROS 0x2 Note This field is always set to 2, as the Control is present in the AQR405. Table 6.795 GbE Standard Status 2: Address 1D.8 6.10.6 GbE Standard Package Identifier 1: Address 1D.E Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.796 GbE Standard Package Identifier 1: Address 1D.E 493 6.10.7 GbE Standard Package Identifier 2: Address 1D.F AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default Note RO Table 6.797 GbE Standard Package Identifier 2: Address 1D.F 6.10.8 GbE PHY SGMII Test Control : Address 1D.C282 Bit F:1 0 Name Reserved SGMII Test Pattern Injection Enable Description Type Default R/W 0 Note Internal reserved - do not modify 1 = Inject test pattern 0 = Normal mode Table 6.798 GbE PHY SGMII Test Control : Address 1D.C282 6.10.9 GbE PHY WoL Control 1: Address 1D.C300 Bit F:0 Name Reserved Description Type Default Internal reserved - do not modify Table 6.799 GbE PHY WoL Control 1: Address 1D.C300 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.10 GbE PHY WoL Control 2: Address 1D.C301 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.800 GbE PHY WoL Control 2: Address 1D.C301 6.10.11 GbE PHY WoL Control 3: Address 1D.C302 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 Table 6.801 GbE PHY WoL Control 3: Address 1D.C302 6.10.12 GbE PHY WoL Control 4: Address 1D.C303 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.802 GbE PHY WoL Control 4: Address 1D.C303 6.10.13 GbE PHY WoL Control 5: Address 1D.C304 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.803 GbE PHY WoL Control 5: Address 1D.C304 495 6.10.14 GbE PHY WoL Control 6: Address 1D.C305 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:1 0 Name Reserved Wake Up Frame Detection Enable Description Type Default R/W 0 Note Internal reserved - do not modify Wake Up Frame Detection Enable Table 6.804 GbE PHY WoL Control 6: Address 1D.C305 6.10.15 GbE PHY WoL Control 7: Address 1D.C306 Bit Name F:0 Wake Up Frame Mask 0 Word 0 [F:0] Description Wake Up Frame Pattern Mask 0 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.805 GbE PHY WoL Control 7: Address 1D.C306 6.10.16 GbE PHY WoL Control 8: Address 1D.C307 Bit Name F:0 Wake Up Frame Mask 0 Word 1 [F:0] Description Wake Up Frame Pattern Mask 0 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.806 GbE PHY WoL Control 7: Address 1D.C306 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.17 GbE PHY WoL Control 9: Address 1D.C308 Bit Name F:0 Wake Up Frame Mask 0 Word 2 [F:0] Description Wake Up Frame Pattern Mask 0 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.807 GbE PHY WoL Control 9: Address 1D.C308 6.10.18 GbE PHY WoL Control 10: Address 1D.C309 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 0 Word 3 [F:0] Description Wake Up Frame Pattern Mask 0 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.808 GbE PHY WoL Control 10: Address 1D.C309 6.10.19 GbE PHY WoL Control 11: Address 1D.C30A Bit Name F:0 Wake Up Frame Mask 0 Word 4 [F:0] Description Wake Up Frame Pattern Mask 0 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.809 GbE PHY WoL Control 11: Address 1D.C30A 497 6.10.20 GbE PHY WoL Control 12: Address 1D.C30B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 0 Word 5 [F:0] Description Wake Up Frame Pattern Mask 0 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.810 GbE PHY WoL Control 12: Address 1D.C30B 6.10.21 GbE PHY WoL Control 13: Address 1D.C30C Bit Name F:0 Wake Up Frame Mask 0 Word 6 [F:0] Description Wake Up Frame Pattern Mask 0 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.811 GbE PHY WoL Control 13: Address 1D.C30C 6.10.22 GbE PHY WoL Control 14: Address 1D.C30D Bit Name F:0 Wake Up Frame Mask 0 Word 7 [F:0] Description Wake Up Frame Pattern Mask 0 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 0 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.812 GbE PHY WoL Control 14: Address 1D.C30D Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.23 GbE PHY WoL Control 15: Address 1D.C30E Bit Name F:0 Wake Up Frame CRC 0 Word 0 [F:0] Description Wake Up Frame CRC 0 bits 15:0 Type Default R/W 0x0000 Note Table 6.813 GbE PHY WoL Control 15: Address 1D.C30E 6.10.24 GbE PHY WoL Control 16: Address 1D.C30F AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame CRC 0 Word 1 [F:0] Description Wake Up Frame CRC 0 bits 31:16 Type Default R/W 0x0000 Note Table 6.814 GbE PHY WoL Control 16: Address 1D.C30F 6.10.25 GbE PHY WoL Control 17: Address 1D.C310 Bit Name F:0 Wake Up Frame Mask 1 Word 0 [F:0] Description Wake Up Frame Pattern Mask 1 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.815 GbE PHY WoL Control 17: Address 1D.C310 499 6.10.26 GbE PHY WoL Control 18: Address 1D.C311 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 1 Word 1 [F:0] Description Wake Up Frame Pattern Mask 1 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.816 GbE PHY WoL Control 18: Address 1D.C311 6.10.27 GbE PHY WoL Control 19: Address 1D.C312 Bit Name F:0 Wake Up Frame Mask 1 Word 2 [F:0] Description Wake Up Frame Pattern Mask 1 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.817 GbE PHY WoL Control 19: Address 1D.C312 6.10.28 GbE PHY WoL Control 20: Address 1D.C313 Bit Name F:0 Wake Up Frame Mask 1 Word 3 [F:0] Description Wake Up Frame Pattern Mask 1 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.818 GbE PHY WoL Control 20: Address 1D.C313 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.29 GbE PHY WoL Control 21: Address 1D.C314 Bit Name F:0 Wake Up Frame Mask 1 Word 4 [F:0] Description Wake Up Frame Pattern Mask 1 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.819 GbE PHY WoL Control 21: Address 1D.C314 6.10.30 GbE PHY WoL Control 22: Address 1D.C315 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 1 Word 5 [F:0] Description Wake Up Frame Pattern Mask 1 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.820 GbE PHY WoL Control 22: Address 1D.C315 6.10.31 GbE PHY WoL Control 23: Address 1D.C316 Bit Name F:0 Wake Up Frame Mask 1 Word 6 [F:0] Description Wake Up Frame Pattern Mask 1 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.821 GbE PHY WoL Control 23: Address 1D.C316 501 6.10.32 GbE PHY WoL Control 24: Address 1D.C317 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 1 Word 7 [F:0] Description Wake Up Frame Pattern Mask 1 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 1 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.822 GbE PHY WoL Control 24: Address 1D.C317 6.10.33 GbE PHY WoL Control 25: Address 1D.C318 Bit Name F:0 Wake Up Frame CRC 1 Word 0 [F:0] Description Wake Up Frame CRC 1 bits 15:0 Type Default R/W 0x0000 Note Table 6.823 GbE PHY WoL Control 25: Address 1D.C318 6.10.34 GbE PHY WoL Control 26: Address 1D.C319 Bit Name F:0 Wake Up Frame CRC 1 Word 1 [F:0] Description Wake Up Frame CRC 1 bits 31:16 Type Default R/W 0x0000 Table 6.824 GbE PHY WoL Control 26: Address 1D.C319 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.35 GbE PHY WoL Control 27: Address 1D.C31A Bit Name F:0 Wake Up Frame Mask 2 Word 0 [F:0] Description Wake Up Frame Pattern Mask 2 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.825 GbE PHY WoL Control 27: Address 1D.C31A 6.10.36 GbE PHY WoL Control 28: Address 1D.C31B AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 2 Word 1 [F:0] Description Wake Up Frame Pattern Mask 2 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.826 GbE PHY WoL Control 28: Address 1D.C31B 6.10.37 GbE PHY WoL Control 29: Address 1D.C31C Bit Name F:0 Wake Up Frame Mask 2 Word 2 [F:0] Description Wake Up Frame Pattern Mask 2 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.827 GbE PHY WoL Control 29: Address 1D.C31C 503 6.10.38 GbE PHY WoL Control 30: Address 1D.C31D AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 2 Word 3 [F:0] Description Wake Up Frame Pattern Mask 2 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.828 GbE PHY WoL Control 30: Address 1D.C31D 6.10.39 GbE PHY WoL Control 31: Address 1D.C31E Bit Name F:0 Wake Up Frame Mask 2 Word 4 [F:0] Description Wake Up Frame Pattern Mask 2 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.829 GbE PHY WoL Control 31: Address 1D.C31E 6.10.40 GbE PHY WoL Control 32: Address 1D.C31F Bit Name F:0 Wake Up Frame Mask 2 Word 5 [F:0] Description Wake Up Frame Pattern Mask 2 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.830 GbE PHY WoL Control 32: Address 1D.C31F Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.41 GbE PHY WoL Control 33: Address 1D.C320 Bit Name F:0 Wake Up Frame Mask 2 Word 6 [F:0] Description Wake Up Frame Pattern Mask 2 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.831 GbE PHY WoL Control 33: Address 1D.C320 6.10.42 GbE PHY WoL Control 34: Address 1D.C321 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 2 Word 7 [F:0] Description Wake Up Frame Pattern Mask 2 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 2 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.832 GbE PHY WoL Control 34: Address 1D.C321 6.10.43 GbE PHY WoL Control 35: Address 1D.C322 Bit Name F:0 Wake Up Frame CRC 2 Word 0 [F:0] Description Wake Up Frame CRC 2 bits 15:0 Type Default R/W 0x0000 Note Table 6.833 GbE PHY WoL Control 35: Address 1D.C322 505 6.10.44 GbE PHY WoL Control 36: Address 1D.C323 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame CRC 2 Word 1 [F:0] Description Wake Up Frame CRC 2 bits 31:16 Type Default R/W 0x0000 Note Table 6.834 GbE PHY WoL Control 36: Address 1D.C323 6.10.45 GbE PHY WoL Control 37: Address 1D.C324 Bit Name F:0 Wake Up Frame Mask 3 Word 0 [F:0] Description Wake Up Frame Pattern Mask 3 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.835 GbE PHY WoL Control 37: Address 1D.C324 6.10.46 GbE PHY WoL Control 38: Address 1D.C325 Bit Name F:0 Wake Up Frame Mask 3 Word 1 [F:0] Description Wake Up Frame Pattern Mask 3 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.836 GbE PHY WoL Control 38: Address 1D.C325 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.47 GbE PHY WoL Control 39: Address 1D.C326 Bit Name F:0 Wake Up Frame Mask 3 Word 2 [F:0] Description Wake Up Frame Pattern Mask 3 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.837 GbE PHY WoL Control 39: Address 1D.C326 6.10.48 GbE PHY WoL Control 40: Address 1D.C327 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 3 Word 3 [F:0] Description Wake Up Frame Pattern Mask 3 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.838 GbE PHY WoL Control 40: Address 1D.C327 6.10.49 GbE PHY WoL Control 41: Address 1D.C328 Bit Name F:0 Wake Up Frame Mask 3 Word 4 [F:0] Description Wake Up Frame Pattern Mask 3 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.839 GbE PHY WoL Control 41: Address 1D.C328 507 6.10.50 GbE PHY WoL Control 42: Address 1D.C329 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 3 Word 5 [F:0] Description Wake Up Frame Pattern Mask 3 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.840 GbE PHY WoL Control 42: Address 1D.C329 6.10.51 GbE PHY WoL Control 43: Address 1D.C32A Bit Name F:0 Wake Up Frame Mask 3 Word 6 [F:0] Description Wake Up Frame Pattern Mask 3 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.841 GbE PHY WoL Control 43: Address 1D.C32A 6.10.52 GbE PHY WoL Control 44: Address 1D.C32B Bit Name F:0 Wake Up Frame Mask 3 Word 7 [F:0] Description Wake Up Frame Pattern Mask 3 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 3 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.842 GbE PHY WoL Control 44: Address 1D.C32B Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.53 GbE PHY WoL Control 45: Address 1D.C32C Bit Name F:0 Wake Up Frame CRC 3 Word 0 [F:0] Description Wake Up Frame CRC 3 bits 15:0 Type Default R/W 0x0000 Note Table 6.843 GbE PHY WoL Control 45: Address 1D.C32C 6.10.54 GbE PHY WoL Control 46: Address 1D.C32D AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame CRC 3 Word 1 [F:0] Description Wake Up Frame CRC 3 bits 31:16 Type Default R/W 0x0000 Note Table 6.844 GbE PHY WoL Control 46: Address 1D.C32D 6.10.55 GbE PHY WoL Control 47: Address 1D.C32E Bit Name F:0 Wake Up Frame Mask 4 Word 0 [F:0] Description Wake Up Frame Pattern Mask 4 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.845 GbE PHY WoL Control 47: Address 1D.C32E 509 6.10.56 GbE PHY WoL Control 48: Address 1D.C32F AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 4 Word 1 [F:0] Description Wake Up Frame Pattern Mask 4 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.846 GbE PHY WoL Control 48: Address 1D.C32F 6.10.57 GbE PHY WoL Control 49: Address 1D.C330 Bit Name F:0 Wake Up Frame Mask 4 Word 2 [F:0] Description Wake Up Frame Pattern Mask 4 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.847 GbE PHY WoL Control 49: Address 1D.C330 6.10.58 GbE PHY WoL Control 50: Address 1D.C331 Bit Name F:0 Wake Up Frame Mask 4 Word 3 [F:0] Description Wake Up Frame Pattern Mask 4 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.848 GbE PHY WoL Control 50: Address 1D.C331 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.59 GbE PHY WoL Control 51: Address 1D.C332 Bit Name F:0 Wake Up Frame Mask 4 Word 4 [F:0] Description Wake Up Frame Pattern Mask 4 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Note : This configuration is used for the RSI and RSI2. It is not used for RSI1. Table 6.849 GbE PHY WoL Control 51: Address 1D.C332 6.10.60 GbE PHY WoL Control 52: Address 1D.C333 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 4 Word 5 [F:0] Description Wake Up Frame Pattern Mask 4 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.850 GbE PHY WoL Control 52: Address 1D.C333 6.10.61 GbE PHY WoL Control 53: Address 1D.C334 Bit Name F:0 Wake Up Frame Mask 4 Word 6 [F:0] Description Wake Up Frame Pattern Mask 4 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.851 GbE PHY WoL Control 53: Address 1D.C334 511 6.10.62 GbE PHY WoL Control 54: Address 1D.C335 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 4 Word 7 [F:0] Description Wake Up Frame Pattern Mask 4 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 4 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.852 GbE PHY WoL Control 54: Address 1D.C335 6.10.63 GbE PHY WoL Control 55: Address 1D.C336 Bit Name F:0 Wake Up Frame CRC 4 Word 0 [F:0] Description Wake Up Frame CRC 4 bits 15:0 Type Default R/W 0x0000 Note Table 6.853 GbE PHY WoL Control 55: Address 1D.C336 6.10.64 GbE PHY WoL Control 56: Address 1D.C337 Bit Name F:0 Wake Up Frame CRC 4 Word 1 [F:0] Description Wake Up Frame CRC 4 bits 31:16 Type Default R/W 0x0000 Table 6.854 GbE PHY WoL Control 56: Address 1D.C337 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.65 GbE PHY WoL Control 57: Address 1D.C338 Bit F:1 0 Name Reserved Magic Packet Frame Detection Enable Description Type Default R/W 0 Note Internal reserved - do not modify 1 = Magic Packet Frame Detection Enable Table 6.855 GbE PHY WoL Control 57: Address 1D.C338 6.10.66 GbE PHY WoL Control 58: Address 1D.C339 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Magic Packet Frame Pattern Word 0 [F:0] Description Magic Packet Frame Pattern bits 15:0 Type Default R/W 0x0000 Note Magic packet frame pattern (MAC address) Table 6.856 GbE PHY WoL Control 58: Address 1D.C339 6.10.67 GbE PHY WoL Control 59: Address 1D.C33A Bit F:0 Name Magic Packet Frame Pattern Word 1 [F:0] Description Type Default Magic Packet Frame Pattern bits 31:16 R/W 0x0000 Note Magic packet frame pattern (MAC address) Table 6.857 GbE PHY WoL Control 59: Address 1D.C33A 513 6.10.68 GbE PHY WoL Control 60: Address 1D.C33B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Magic Packet Frame Pattern Word 2 [F:0] Description Type Default Magic Packet Frame Pattern bits 47:32 R/W 0x0000 Note Magic packet frame pattern (MAC address) Table 6.858 GbE PHY WoL Control 60: Address 1D.C33B 6.10.69 GbE PHY Extended WoL Control 1: Address 1D.C420 Bit Name F:0 Wake Up Frame Mask 5 Word 0 [F:0] Description Wake Up Frame Pattern Mask 5 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.859 GbE PHY Extended WoL Control 1: Address 1D.C420 6.10.70 GbE PHY Extended WoL Control 2: Address 1D.C421 Bit Name F:0 Wake Up Frame Mask 5 Word 1 [F:0] Description Wake Up Frame Pattern Mask 55 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.860 GbE PHY Extended WoL Control 2: Address 1D.C421 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.71 GbE PHY Extended WoL Control 3: Address 1D.C422 Bit Name F:0 Wake Up Frame Mask 5 Word 2 [F:0] Description Wake Up Frame Pattern Mask 5 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.861 GbE PHY Extended WoL Control 3: Address 1D.C422 6.10.72 GbE PHY Extended WoL Control 4: Address 1D.C423 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 5 Word 3 [F:0] Description Wake Up Frame Pattern Mask 5 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.862 GbE PHY Extended WoL Control 4: Address 1D.C423 6.10.73 GbE PHY Extended WoL Control 5: Address 1D.C424 Bit Name F:0 Wake Up Frame Mask 5 Word 4 [F:0] Description Wake Up Frame Pattern Mask 5 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.863 GbE PHY Extended WoL Control 5: Address 1D.C424 515 6.10.74 GbE PHY Extended WoL Control 6: Address 1D.C425 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 5 Word 5 [F:0] Description Wake Up Frame Pattern Mask 5 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.864 GbE PHY Extended WoL Control 6: Address 1D.C425 6.10.75 GbE PHY Extended WoL Control 7: Address 1D.C426 Bit Name F:0 Wake Up Frame Mask 5 Word 6 [F:0] Description Wake Up Frame Pattern Mask 5 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.865 GbE PHY Extended WoL Control 7: Address 1D.C426 6.10.76 GbE PHY Extended WoL Control 8: Address 1D.C427 Bit Name F:0 Wake Up Frame Mask 5 Word 7 [F:0] Description Wake Up Frame Pattern Mask 5 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 5 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.866 GbE PHY Extended WoL Control 8: Address 1D.C427 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.77 GbE PHY Extended WoL Control 9: Address 1D.C428 Bit Name F:0 Wake Up Frame CRC 5 Word 0 [F:0] Description Wake Up Frame CRC 5 bits 15:0 Type Default R/W 0x0000 Note Table 6.867 GbE PHY Extended WoL Control 9: Address 1D.C428 6.10.78 GbE PHY Extended WoL Control 10: Address 1D.C429 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame CRC 5 Word 1 [F:0] Description Wake Up Frame CRC 5 bits 31:16 Type Default R/W 0x0000 Note Table 6.868 GbE PHY Extended WoL Control 10: Address 1D.C429 6.10.79 GbE PHY Extended WoL Control 11: Address 1D.C42A Bit Name F:0 Wake Up Frame Mask 6 Word 0 [F:0] Description Wake Up Frame Pattern Mask 6 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.869 GbE PHY Extended WoL Control 11: Address 1D.C42A 517 6.10.80 GbE PHY Extended WoL Control 12: Address 1D.C42B AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 6 Word 1 [F:0] Description Wake Up Frame Pattern Mask 65 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.870 GbE PHY Extended WoL Control 12: Address 1D.C42B 6.10.81 GbE PHY Extended WoL Control 13: Address 1D.C42C Bit Name F:0 Wake Up Frame Mask 6 Word 2 [F:0] Description Wake Up Frame Pattern Mask 6 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.871 GbE PHY Extended WoL Control 13: Address 1D.C42C 6.10.82 GbE PHY Extended WoL Control 14: Address 1D.C42D Bit Name F:0 Wake Up Frame Mask 6 Word 3 [F:0] Description Wake Up Frame Pattern Mask 6 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.872 GbE PHY Extended WoL Control 14: Address 1D.C42D Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.83 GbE PHY Extended WoL Control 15: Address 1D.C42E Bit Name F:0 Wake Up Frame Mask 6 Word 4 [F:0] Description Wake Up Frame Pattern Mask 6 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.873 GbE PHY Extended WoL Control 15: Address 1D.C42E 6.10.84 GbE PHY Extended WoL Control 16: Address 1D.C42F AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 6 Word 5 [F:0] Description Wake Up Frame Pattern Mask 6 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.874 GbE PHY Extended WoL Control 16: Address 1D.C42F 6.10.85 GbE PHY Extended WoL Control 17: Address 1D.C430 Bit Name F:0 Wake Up Frame Mask 6 Word 6 [F:0] Description Wake Up Frame Pattern Mask 6 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.875 GbE PHY Extended WoL Control 17: Address 1D.C430 519 6.10.86 GbE PHY Extended WoL Control 18: Address 1D.C431 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 6 Word 7 [F:0] Description Wake Up Frame Pattern Mask 6 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 6 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.876 GbE PHY Extended WoL Control 18: Address 1D.C431 6.10.87 GbE PHY Extended WoL Control 19: Address 1D.C432 Bit Name F:0 Wake Up Frame CRC 6 Word 0 [F:0] Description Wake Up Frame CRC 6 bits 15:0 Type Default R/W 0x0000 Note Table 6.877 GbE PHY Extended WoL Control 19: Address 1D.C432 6.10.88 GbE PHY Extended WoL Control 20: Address 1D.C433 Bit F:0 Name Rx Wake Up Frame CRC 6 Word 1 [F:0] Description Wake Up Frame CRC 6 bits 31:16 Type Default R/W 0x0000 Table 6.878 GbE PHY Extended WoL Control 20: Address 1D.C433 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.89 GbE PHY Extended WoL Control 21: Address 1D.C434 Bit Name F:0 Wake Up Frame Mask 7 Word 0 [F:0] Description Wake Up Frame Pattern Mask 7 bits 15:0 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.879 GbE PHY Extended WoL Control 21: Address 1D.C434 6.10.90 GbE PHY Extended WoL Control 22: Address 1D.C435 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 7 Word 1 [F:0] Description Wake Up Frame Pattern Mask 75 bits 31:16 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.880 GbE PHY Extended WoL Control 22: Address 1D.C435 6.10.91 GbE PHY Extended WoL Control 23: Address 1D.C436 Bit Name F:0 Wake Up Frame Mask 7 Word 2 [F:0] Description Wake Up Frame Pattern Mask 7 bits 47:32 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.881 GbE PHY Extended WoL Control 23: Address 1D.C436 521 6.10.92 GbE PHY Extended WoL Control 24: Address 1D.C437 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame Mask 7 Word 3 [F:0] Description Wake Up Frame Pattern Mask 7 bits 63:48 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.882 GbE PHY Extended WoL Control 24: Address 1D.C437 6.10.93 GbE PHY Extended WoL Control 25: Address 1D.C438 Bit Name F:0 Wake Up Frame Mask 7 Word 4 [F:0] Description Wake Up Frame Pattern Mask 7 bits 79:64 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.883 GbE PHY Extended WoL Control 25: Address 1D.C438 6.10.94 GbE PHY Extended WoL Control 26: Address 1D.C439 Bit Name F:0 Wake Up Frame Mask 7 Word 5 [F:0] Description Wake Up Frame Pattern Mask 7 bits 95:80 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.884 GbE PHY Extended WoL Control 26: Address 1D.C439 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.95 GbE PHY Extended WoL Control 27: Address 1D.C43A Bit Name F:0 Wake Up Frame Mask 7 Word 6 [F:0] Description Wake Up Frame Pattern Mask 7 bits 111:96 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.885 GbE PHY Extended WoL Control 27: Address 1D.C43A 6.10.96 GbE PHY Extended WoL Control 28: Address 1D.C43B AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 Wake Up Frame Mask 7 Word 7 [F:0] Description Wake Up Frame Pattern Mask 7 bits 127:112 Type Default R/W 0x0000 Note Wake-up Frame Pattern Mask 7 (0=disable, 1=enable, bit 0 for the first byte, default:all-zeroes) Table 6.886 GbE PHY Extended WoL Control 28: Address 1D.C43B 6.10.97 GbE PHY Extended WoL Control 29: Address 1D.C43C Bit Name F:0 Wake Up Frame CRC 7 Word 0 [F:0] Description Wake Up Frame CRC 7 bits 15:0 Type Default R/W 0x0000 Note Table 6.887 GbE PHY Extended WoL Control 29: Address 1D.C43C 523 6.10.98 GbE PHY Extended WoL Control 30: Address 1D.C43D AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 Wake Up Frame CRC 7 Word 1 [F:0] Description Wake Up Frame CRC 7 bits 31:16 Type Default R/W 0x0000 Note Table 6.888 GbE PHY Extended WoL Control 30: Address 1D.C43D 6.10.99 GbE Reserved Provisioning 1: Address 1D.C500 Bit F Name 100M System Loopback Description 1 = Enable System Loopback Type Default R/W PD 0 Note Setting this bit enables the 100M system loopback. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F E GbE System Loopback 1 = Enable System Loopback R/W PD 0 Setting this bit enables the 1G system loopback. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F D:0 Reserved Provisioning 1 [D:0] Reserved for future use R/W PD 0x0000 Table 6.889 GbE Reserved Provisioning 1: Address 1D.C500 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.100 GbE Reserved Provisioning 2: Address 1D.C501 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F:D Test Mode [2:0] 000 = Normal mode 001 = Test Mode 1 - Transmit waveform test 010 = Test Mode 2 - Master transmit jitter test 011 = Test Mode 3 - Slave transmit jitter test 100 = Test Mode 4 - Transmitter distortion test 101 -> 1111 = Reserved R/W 0x0 C:2 Reserved Provisioning 2 [A:0] Reserved for future use R/W PD 0x000 1:0 100BASE-TX Test Mode [1:0] 00 = Normal mode 01 = 100BASE-TX IEEE Test Mode 10 = 100BASE-TX ANSI Jitter Test 11 = 100BASE-TX ANSI Droop Test R/W 0x0 Note NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F 100BASE-TX IEEE Test Mode = MLT-3 Idle Sequence ANSI Jitter Test = FDDI - Clause 9.1.3 Fig. 12 ANSI Droop Test = FDDI - Clause 9.1.8 Fig. 14 NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F Table 6.890 GbE Reserved Provisioning 2: Address 1D.C501 525 6.10.101 GbE PHY SGMII1 Rx Status 1: Address 1D.D280 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:9 Name Reserved Description Type Default Note Internal reserved - do not modify 8 SGMII Synchronization Status 1 = SGMII is Synchronized RO 7 SGMII Loopback Idle Insertion Detected 1 = SGMII Idle Insertion Detected LH 6 SGMII Loopback Idle Deletion Detected 1 = SGMII Idle Deletion Detected LH 5 SGMII Idle Insertion Detected 1 = SGMII Idle Insertion Detected LH 4 SGMII Idle Deletion Detected 1 = SGMII Idle Deletion Detected LH 3:2 Reserved Internal reserved - do not modify 1 SGMII TX_ER Suppression 1 = TX_ER suppressed LH Indicate TX_ER has been suppressed when TX_EN was not asserted 0 SGMII Rx Link Activity 1 = SGMII Rx Link Activity LH SGMII Start Character K27_7 detected Table 6.891 GbE PHY SGMII1 Rx Status 1: Address 1D.D280 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.102 GbE PHY SGMII1 Rx Status 2: Address 1D.D281 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.892 GbE PHY SGMII1 Rx Status 2: Address 1D.D281 6.10.103 GbE PHY SGMII1 Rx Status 3: Address 1D.D282 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 SGMII1 Rx Frame Counter LSW [F:0] Description SGMII1 Rx Good Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.893 GbE PHY SGMII1 Rx Status 3: Address 1D.D282 6.10.104 GbE PHY SGMII1 Rx Status 4: Address 1D.D283 Bit Name F:A Reserved 9:0 SGMII1 Rx Frame Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII1 Rx Good Frame Counter This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.894 GbE PHY SGMII1 Rx Status 4: Address 1D.D283 527 6.10.105 GbE PHY SGMII1 Rx Status 5: Address 1D.D284 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name SGMII1 Rx Frame Error Counter LSW [F:0] Description SGMII1 Rx Bad Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.895 GbE PHY SGMII1 Rx Status 5: Address 1D.D284 6.10.106 GbE PHY SGMII1 Rx Status 6: Address 1D.D285 Bit Name F:A Reserved 9:0 SGMII1 Rx Frame Error Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII1 Rx Bad Frame Counter This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.896 GbE PHY SGMII1 Rx Status 6: Address 1D.D285 6.10.107 GbE PHY SGMII1 Rx Status 7: Address 1D.D286 Bit F:1 0 Name Reserved SGMII1 Rx Comma Detect Description Type Default Note Internal reserved - do not modify 1 = SGMII1 Rx Comma Detected LH Indicates when SGMII Rx has detected a comma character Table 6.897 GbE PHY SGMII1 Rx Status 7: Address 1D.D286 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.108 GbE PHY SGMII1 Rx Status 8: Address 1D.D287 Bit Name F:8 Reserved 7:0 SGMII1 Rx False Carrier Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII1 Rx False Carrier Counter TSI detects false carrier on the SGMII interface. Table 6.898 GbE PHY SGMII1 Rx Status 8: Address 1D.D287 6.10.109 GbE PHY SGMII1 Rx Status 9: Address 1D.D288 AQR405 Revision 0.11 - January 5, 2015 Bit Name F:C Reserved B:8 SGMII1 Rx EEE Rx LPI State Machine [3:0] 7:5 Reserved Description Type Default Note Internal reserved - do not modify SGMII1 Rx EEE Rx LPI state machine RO Rx LPI state machine Internal reserved - do not modify SGMII1 Rx EEE Rx LPI Ordered Set Dectected 1 = SGMII1 Rx LPI ordered set detected LH Indicate LPI ordered_set is detected 3 SGMII1 Rx EEE Rx LPI Wake Timer Fault Error 1 = SGMII1 Rx Rx LPI detected wake timer fault LH Indicate Rx LPI detected wake timer fault 2 SGMII1 Rx EEE Rx LPI Wake Done State 1 = SGMII1 Rx Rx LPI is in wake done state RO Indicate Rx LPI is in wake done state Table 6.899 GbE PHY SGMII1 Rx Status 9: Address 1D.D288 529 4 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note 1 SGMII1 Rx EEE Rx LPI Quiet State 1 = SGMII1 Rx Rx LPI is in quiet state RO Indicate Rx LPI is in quiet state 0 SGMII1 Rx EEE Rx LPI Active State 1 = SGMII1 Rx Rx LPI is in active state RO Indicate Rx LPI is in active state Table 6.899 GbE PHY SGMII1 Rx Status 9: Address 1D.D288 6.10.110 GbE PHY SGMII0 Rx Status 1: Address 1D.D290 Bit F:9 Name Reserved Description Type Default Internal reserved - do not modify 8 SGMII0 Rx Synchronization Status 1 = SGMII0 Rx is Synchronized RO 7 SGMII0 Rx Loopback Idle Insertion Detected 1 = SGMII0 Rx Idle Insertion Detected LH 6 SGMII0 Rx Loopback Idle Deletion Detected 1 = SGMII0 Rx Idle Deletion Detected LH 5 SGMII0 Rx Idle Insertion Detected 1 = SGMII0 Rx Idle Insertion Detected LH 4 SGMII0 Rx Idle Deletion Detected 1 = SGMII0 Rx Idle Deletion Detected LH Table 6.900 GbE PHY SGMII0 Rx Status 1: Address 1D.D290 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 3:2 Name Reserved Description Type Default Note Internal reserved - do not modify 1 SGMII0 Rx TX_ER Suppression 1 = SGMII0 Rx TX_ER suppressed LH Indicate TX_ER has been suppressed when TX_EN was not asserted 0 SGMII0 Rx Rx Link Activity 1 = SGMII0 Rx Rx Link Activity LH SGMII Start Character K27_7 detected Table 6.900 GbE PHY SGMII0 Rx Status 1: Address 1D.D290 6.10.111 GbE PHY SGMII0 Rx Status 2: Address 1D.D291 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.901 GbE PHY SGMII0 Rx Status 2: Address 1D.D291 6.10.112 GbE PHY SGMII0 Rx Status 3: Address 1D.D292 Bit F:0 Name SGMII0 Rx Frame Counter LSW [F:0] Description SGMII0 Rx Good Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.902 GbE PHY SGMII0 Rx Status 3: Address 1D.D292 531 6.10.113 GbE PHY SGMII0 Rx Status 4: Address 1D.D293 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:A Reserved 9:0 SGMII0 Rx Frame Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII0 Rx Good Frame Counter This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.903 GbE PHY SGMII0 Rx Status 4: Address 1D.D293 6.10.114 GbE PHY SGMII0 Rx Status 5: Address 1D.D294 Bit F:0 Name SGMII0 Rx Frame Error Counter LSW [F:0] Description SGMII0 Rx Bad Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.904 GbE PHY SGMII0 Rx Status 5: Address 1D.D294 6.10.115 GbE PHY SGMII0 Rx Status 6: Address 1D.D295 Bit Name F:A Reserved 9:0 SGMII0 Rx Frame Error Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII0 Rx Bad Frame Counter This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.905 GbE PHY SGMII0 Rx Status 6: Address 1D.D295 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.116 GbE PHY SGMII0 Rx Status 7: Address 1D.D296 Bit F:1 0 Name Reserved SGMII0 Rx Comma Detect Description Type Default Note Internal reserved - do not modify 1 = SGMII0 Rx Comma Detected LH Indicates when Rx has detected a comma character Table 6.906 GbE PHY SGMII0 Rx Status 7: Address 1D.D296 6.10.117 GbE PHY SGMII0 Rx Status 8: Address 1D.D297 Bit Name AQR405 Revision 0.11 - January 5, 2015 F:8 Reserved 7:0 SGMII0 Rx False Carrier Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII0 Rx False Carrier Counter False carrier events on XFI0 SGMII interface. Table 6.907 GbE PHY SGMII0 Rx Status 8: Address 1D.D297 6.10.118 GbE PHY SGMII0 Rx Status 9: Address 1D.D298 Bit Name Reserved B:8 SGMII0 Rx EEE Rx LPI State Machine [3:0] 7:5 Reserved Type Default Note Internal reserved - do not modify SGMII0 Rx EEE Rx LPI state machine RO Rx LPI state machine Internal reserved - do not modify Table 6.908 GbE PHY SGMII0 Rx Status 9: Address 1D.D298 533 F:C Description Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note 4 SGMII0 Rx EEE Rx LPI Ordered Set Dectected 1 = SGMII0 Rx LPI ordered set detected LH Indicate LPI ordered_set is detected 3 SGMII0 Rx EEE Rx LPI Wake Timer Fault Error 1 = SGMII0 Rx Rx LPI detected wake timer fault LH Indicate Rx LPI detected wake timer fault 2 SGMII0 Rx EEE Rx LPI Wake Done State 1 = SGMII0 Rx Rx LPI is in wake done state RO Indicate Rx LPI is in wake done state 1 SGMII0 Rx EEE Rx LPI Quiet State 1 = SGMII0 Rx Rx LPI is in quiet state RO Indicate Rx LPI is in quiet state 0 SGMII0 Rx EEE Rx LPI Active State 1 = SGMII0 Rx Rx LPI is in active state RO Indicate Rx LPI is in active state Table 6.908 GbE PHY SGMII0 Rx Status 9: Address 1D.D298 6.10.119 GbE PHY SGMII1 WoL Status: Address 1D.D302 Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 Wake Up Frame Type [2:0] Wake Up Frame Type Type RO Default Note Wake-up Frame type 4:Wake-up Frame 0 to 4) Table 6.909 GbE PHY SGMII1 WoL Status: Address 1D.D302 detected (0 to Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.120 GbE PHY SGMII1 Tx Status 1: Address 1D.D303 Bit F:0 Name SGMII1 Tx Frame Counter LSW [F:0] Description SGMII1 Tx Good Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.910 GbE PHY SGMII1 Rx Status 3: Address 1D.D282 6.10.121 GbE PHY SGMII1 Tx Status 2: Address 1D.D304 Bit Name AQR405 Revision 0.11 - January 5, 2015 F:A Reserved 9:0 SGMII1 Tx Frame Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII1 Tx Good Frame Counter This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.911 GbE PHY SGMII1 Rx Status 4: Address 1D.D283 6.10.122 GbE PHY SGMII1 Tx Status 3: Address 1D.D305 Bit F:0 Name SGMII1 Tx Frame Error Counter LSW [F:0] Description SGMII1 Tx Bad Frame Error Counter Type Default SCT L 0x0000 Note Frames with CRC error counter. Table 6.912 GbE PHY SGMII1 Rx Status 5: Address 1D.D284 535 6.10.123 GbE PHY SGMII1 Tx Status 4: Address 1D.D306 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:A Reserved 9:0 SGMII1 Tx Frame Error Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII1 Tx Bad Frame Error Counter Frames with CRC error counter. Table 6.913 GbE PHY SGMII1 Rx Status 6: Address 1D.D285 6.10.124 GbE PHY SGMII1 Tx Status 5: Address 1D.D307 Bit Name F:8 Reserved 7:0 SGMII1 Tx False Carrier Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII1 Tx False Carrier Counter SGMII1 Tx detected false carrier event the on the SERDES interface. Table 6.914 GbE PHY SGMII1 Tx Status 5: Address 1D.D307 6.10.125 GbE PHY SGMII1 Tx Status 6: Address 1D.D308 Bit Name F:8 Reserved 7:0 SGMII1 Tx Collision Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII1 Tx Collision Counter SGMII1 Tx detected a collision on the SERDES interface. Table 6.915 GbE PHY SGMII1 Tx Status 6: Address 1D.D308 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.126 GbE PHY SGMII1 Tx Status 7: Address 1D.D309 Bit Name F:8 Reserved 7:0 SGMII1 Tx Line Collision Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII1 Tx Line Collision Counter SGMII1 Tx detects collision on the GMII/MII interface. Table 6.916 GbE PHY SGMII1 Tx Status 7: Address 1D.D309 6.10.127 GbE PHY SGMII1 Tx Status 8: Address 1D.D30A AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name SGMII1 Tx Frame Alignment Counter [F:0] Description SGMII1 Tx Frame Alignment Counter Type Default Note SCT 0x0000 SGMII1 Tx Frame Count with alignment error. This is detected by CRC error with an extra nibble on MII interface (100M mode) on the GMII/MII interface. Table 6.917 GbE PHY SGMII1 Tx Status 8: Address 1D.D30A 6.10.128 GbE PHY SGMII1 Tx Status 9: Address 1D.D30B Bit Name F:0 SGMII1 Tx Runt Frame Counter LSW [F:0] Description SGMII1 Tx Runt Frame Counter Type Default SCT L 0x0000 Note SGMII1 Tx Runt Frame (less than 64 byte long) Count on the GMII/MII interface. Table 6.918 GbE PHY SGMII1 Tx Status 9: Address 1D.D30B 537 6.10.129 GbE PHY SGMII1 Tx Status 10: Address 1D.D30C AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:6 Reserved 5:0 SGMII1 Tx Runt Frame Counter MSW [5:0] Description Type Default SCT M 0x00 Note Internal reserved - do not modify SGMII1 Tx Runt Frame Counter Rx Runt Frame (less than 64 byte long) Count on the GMII/MII interface. Table 6.919 GbE PHY SGMII1 Tx Status 10: Address 1D.D30C 6.10.130 SGMII0 WoL Status : Address 1D.D312 Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 SGMII0 Wake Up Frame Type [2:0] SGMII0 Wake Up Frame Type Type Default RO Note Wake-up Frame type detected (0 to 7: Wake-up Frame 0 to 7) Table 6.920 SGMII0 WoL Status : Address 1D.D312 6.10.131 GbE PHY SGMII0 Tx Status 1: Address 1D.D313 Bit F:0 Name SGMII0 Tx Frame Counter LSW [F:0] Description SGMII0 Tx Good Frame Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.921 GbE PHY SGMII0 Tx Status 1: Address 1D.D313 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.132 GbE PHY SGMII0 Tx Status 2: Address 1D.D314 Bit Name F:A Reserved 9:0 SGMII0 Tx Frame Counter MSW [9:0] Description Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII0 Tx Good Frame Counter This counts 100M / GbE Ethernet good frames (i.e. no Ethernet CRC-32 / FCS errors). Table 6.922 GbE PHY SGMII0 Tx Status 2: Address 1D.D314 6.10.133 GbE PHY SGMII0 Tx Status 3: Address 1D.D315 AQR405 Revision 0.11 - January 5, 2015 Bit F:0 Name SGMII0 Tx Frame Error Counter LSW [F:0] Description SGMII0 Tx Bad Frame Error Counter Type Default Note SCT L 0x0000 This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.923 GbE PHY SGMII0 Tx Status 3: Address 1D.D315 6.10.134 GbE PHY SGMII0 Tx Status 4: Address 1D.D316 Bit Name Reserved 9:0 SGMII0 Tx Frame Error Counter MSW [9:0] Type Default SCT M 0x000 Note Internal reserved - do not modify SGMII0 Tx Bad Frame Error Counter This counts 100M / GbE Ethernet frames with a bad FCS (aka CRC-32). Table 6.924 GbE PHY SGMII0 Tx Status 4: Address 1D.D316 539 F:A Description 6.10.135 GbE PHY SGMII0 Tx Status 5: Address 1D.D317 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:8 Reserved 7:0 SGMII0 Tx False Carrier Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII0 Tx False Carrier Counter SGMII0 Tx detected false carrier on the GMII/MII interface. Table 6.925 GbE PHY SGMII0 Tx Status 5: Address 1D.D317 6.10.136 GbE PHY SGMII0 Tx Status 6: Address 1D.D318 Bit Name F:8 Reserved 7:0 SGMII0 Tx Collision Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII0 Tx Collision Counter SGMII0 Tx detected a collision on the SGMII interface. Table 6.926 GbE PHY SGMII0 Tx Status 6: Address 1D.D318 6.10.137 GbE PHY SGMII0 Tx Status 7: Address 1D.D319 Bit Name F:8 Reserved 7:0 SGMII0 Tx Line Collision Counter [7:0] Description Type Default SCT 0x00 Note Internal reserved - do not modify SGMII0 Tx Line Collision Counter SGMII0 Tx detected a collision on the GMII/MII interface. Table 6.927 GbE PHY SGMII0 Tx Status 7: Address 1D.D319 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.138 GbE PHY SGMII0 Tx Status 8: Address 1D.D31A Bit F:0 Name SGMII0 Tx Frame Alignment Counter [F:0] Description SGMII0 Tx Frame Alignment Counter Type Default Note SCT 0x0000 SGMII0 Tx Frame Count with alignment error. This is detected by CRC error with an extra nibble on the MII interface (100M mode) on the GMII/MII interface. Table 6.928 GbE PHY SGMII0 Tx Status 8: Address 1D.D31A 6.10.139 GbE PHY SGMII0 Tx Status 9: Address 1D.D31B AQR405 Revision 0.11 - January 5, 2015 Bit Name F:0 SGMII0 Tx Runt Frame Counter LSW [F:0] Description SGMII0 Tx Runt Frame Counter Type Default SCT L 0x0000 Note SGMII0 Tx Runt Frame (less than 64 byte long) Count on the GMII/MII interface. Table 6.929 GbE PHY SGMII0 Tx Status 9: Address 1D.D31B 6.10.140 GbE PHY SGMII0 Tx Status 10: Address 1D.D31C Bit Name F:6 Reserved 5:0 SGMII0 Tx Runt Frame Counter MSW [5:0] Description Type Default SCT M 0x00 Note Internal reserved - do not modify SGMII0 Tx Runt Frame Counter SGMII0 Tx Runt Frame (less than 64 byte long) Count on the GMII/MII interface. Table 6.930 GbE PHY SGMII0 Tx Status 10: Address 1D.D31C 541 6.10.141 GbE PHY SGMII WoL Status: Address 1D.D322 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:3 Reserved Internal reserved - do not modify 2:0 SGMII Wake Up Frame Type [2:0] SGMII Wake Up Frame Type Type Default RO Note Wake-up Frame type detected (0 to 7: Wake-up Frame 0 to 7) Table 6.931 GbE PHY SGMII WoL Status: Address 1D.D322 6.10.142 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 Bit F:8 Name Reserved Description Type Default Internal reserved - do not modify 7 SGMII0 Rx Loss of Signal 1 = SGMII0 Loss of Signal LH 6 SGMII0 Rx Invalid Character Error 1 = SGMII0 Rx Invalid Character Error LH 5 SGMII0 Rx Running Disparity Error 1 = SGMII0 Rx Running Disparity Error LH 4 SGMII0 Rx Code Violation Error 1 = SGMII0 Rx Code Violation Error LH 3 SGMII1 Rx Loss of Signal 1 = SGMII1 Loss of Signal LH 2 SGMII1 Rx Invalid Character Error 1 = SGMII1 Rx Invalid Character Error LH Table 6.932 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type 1 SGMII1 Rx Running Disparity Error 1 = SGMII1 Rx Running Disparity Error LH 0 SGMII1 Rx Code Violation Error 1 = SGMII1 Rx Code Violation Error LH Default Note Table 6.932 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 6.10.143 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 Bit AQR405 Revision 0.11 - January 5, 2015 F:A Name Reserved Description Type Default Note Internal reserved - do not modify 9 SGMII Magic Packet Frame Detected 1 = SGMII Magic Packet Frame Detected LH 8 SGMII Wake Up Frame Detected 1 = SGMII Wake Up Frame Detected LH 7 Reserved 6 SGMII0 Tx Invalid GMII Character Detected 1 = SGMII0 Tx Invalid GMII Character Detected LH 5 SGMII0 Magic Packet Frame Detected 1 = SGMII0 Magic Packet Frame Detected LH 4 SGMII0 Wake Up Frame Detected 1 = SGMII0 Wake Up Frame Detected LH 3 Reserved Internal reserved - do not modify 543 Internal reserved - do not modify Table 6.933 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 Bit Name Description Type AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 2 SGMII1 Tx Invalid GMII Character Detected 1 = SGMII1 Tx Invalid GMII Character Detected LH 1 SGMII1 Magic Packet Frame Detected 1 = SGMII1 Magic Packet Frame Detected LH 0 SGMII1 Wake Up Frame Detected 1 = SGMII1 Wake Up Frame Detected LH Default Note Table 6.933 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 6.10.144 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 Bit F:8 Name Reserved Description Type Default Internal reserved - do not modify 7 SGMII0 Rx Loss of Signal Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 6 SGMII0 Rx Invalid Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 5 SGMII0 Rx Running Disparity Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.934 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 4 SGMII0 Rx Code Violation Error Mask 3 Description AQR405 Revision 0.11 - January 5, 2015 Type Default 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 SGMII1 Rx Loss of Signal Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 2 SGMII1 Rx Invalid Character Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 SGMII1 Rx Running Disparity Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 SGMII1 Rx Code Violation Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note Table 6.934 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 6.10.145 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420 Bit F:A Name Reserved Description Type Default Note Internal reserved - do not modify SGMII Magic Packet Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 8 SGMII Wake Up Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.935 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420 545 9 Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 7 Reserved Internal reserved - do not modify 6 SGMII0 Tx Invalid GMII Character Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 5 SGMII0 Magic Packet Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 4 SGMII0 Wake Up Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 3 Reserved 2 SGMII1 Tx Invalid GMII Character Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 SGMII1 Magic Packet Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 SGMII1 Wake Up Frame Detected Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Internal reserved - do not modify Table 6.935 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.10.146 GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 Bit F:5 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 4 Vendor Specific SGMII Tx Alarms 1 Interrupt 1 = Interrupt in vendor specific SGMII Tx Alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. 3 Vendor Specific SGMII Tx Alarms 2 Interrupt 1 = Interrupt in vendor specific SGMII Tx Alarms 2 RO An interrupt was generated from the status register and the corresponding mask register. 2 Vendor Specific SGMII Rx Alarms 1 Interrupt 1 = Interrupt in vendor specific SGMII Tx Alarms 1 RO An interrupt was generated from the status register and the corresponding mask register. 1 Vendor Specific SGMII Rx Alarms 2 Interrupt 1 = Interrupt in vendor specific SGMII Tx Alarms 2 RO An interrupt was generated from the status register and the corresponding mask register. 0 Reserved Internal reserved - do not modify Table 6.936 GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 547 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11 Global Registers 6.11.1 Global Standard Control 1: Address 1E.0 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F Soft Reset 1 = Global soft reset 0 = Normal operation E:C Reserved Internal reserved - do not modify Low Power 1 = Low-power mode 0 = Normal operation Reserved Internal reserved - do not modify B A:0 Type Default Note R/W SC 1 Resets the entire PHY. Setting this bit initiates a global soft reset on all of the digital logic not including the microprocessor (i.e. microprocessor is not reset). Upon completion of the reset sequence, this bit is set back to 0by the microprocessor. Note this bit is OR'ed with the individual MMD resets. This bit should be set to 0 before setting the individual MMD resets. R/W PD 0 A one written to this register causes the chip to enter low-power mode. This bit puts the entire chip in low-power mode, with only the MDIO and microprocessor functioning, and turns off the analog front-end: i.e. places it in high-impedance mode. Setting this bit also sets all of the Low Power bits in the other MMDs. Table 6.937 Global Standard Control 1: Address 1E.0 6.11.2 Global Standard Device Identifier 1: Address 1E.2 Name F:0 Device ID MSW [1F:10] Description Bits 31 - 16 of Device ID Type Default RO Table 6.938 Global Standard Device Identifier 1: Address 1E.2 Note 549 Bit 6.11.3 Global Standard Device Identifier 2: Address 1E.3 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Device ID LSW [F:0] Description Bits 15 - 0 of Device ID Type Default Note RO Table 6.939 Global Standard Device Identifier 2: Address 1E.3 6.11.4 Global Standard Devices in Package 1: Address 1E.5 Bit F:8 Name Description Type Default Note Reserved Internal reserved - do not modify 7 Autonegotiation Present 1 = Autonegotiation is present in package 0 = Autonegotiation is not present in package ROS 1 This is always set to 1, as there is Autonegotiation in the AQR405. 6 TC Present 1 = TC is present in package 0 = TC is not present in package ROS 0 This is always set to 0, as there is no TC functionality in the AQR405. 5 DTE XS Present 1 = DTE XS is present in package 0 = DTE XS is not present in package ROS 0 This is always set to 0, as there is no DTE XAUI interface in the AQR405. 4 PHY XS Present 1 = PHY XS is present in package 0 = PHY XS is not present in package ROS 1 This is always set to 1 as there is a PHY XS interface in the AQR405. 3 PCS Present 1 = PCS is present in package 0 = PCS is not present in package ROS 1 This is always set to 1 as there is PCS functionality in the AQR405. 2 WIS Present 1 = WIS is present in package 0 = WIS is not present in package ROS 0 This is always set to 0, as there is no WIS functionality in the AQR405. Table 6.940 Global Standard Devices in Package 1: Address 1E.5 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note 1 PMA Present 1 = PMA is present in package 0 = PMA is not present ROS 1 This is always set to 1 as there is PMA functionality in the AQR405. 0 Clause 22 Registers Present 1 = Clause 22 registers are present in package 0 = Clause 22 registers are not present in package ROS 0 This is always set to 0 in the AQR405, as there are no Clause 22 registers in the device. Table 6.940 Global Standard Devices in Package 1: Address 1E.5 6.11.5 Global Standard Vendor Devices in Package 2: Address 1E.6 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F Vendor Specific Device #2 Present 1 = Device #2 is present in package 0 = Device #2 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the DSP PMA registers. E Vendor Specific Device #1 Present 1 = Device #1 is present in package 0 = Device #1 is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the global control registers. D Clause 22 Extension Present 1 = Clause 22 Extension is present in package 0 = Clause 22 Extension is not present in package ROS 1 This is always set to 1 as the AQR405 utilizes this device for the GbE registers. C:0 Reserved Internal reserved - do not modify Table 6.941 Global Standard Vendor Devices in Package 2: Address 1E.6 551 6.11.6 Global Standard Status 2: Address 1E.8 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:E Device Present [1:0] [F:E] 0x3 = No device at this address 0x2 = Device present at this address 0x1 = No device at this address 0x0 = No device at this address D:0 Reserved Internal reserved - do not modify Type Default ROS 0x2 Note This field is always set to 0x2, as the Global MMD resides here in the AQR405. Table 6.942 Global Standard Status 2: Address 1E.8 6.11.7 Global Standard Package Identifier 1: Address 1E.E Bit F:0 Name Package ID MSW [1F:10] Description Bits 31- 16 of Package ID Type Default Note RO Table 6.943 Global Standard Package Identifier 1: Address 1E.E 6.11.8 Global Standard Package Identifier 2: Address 1E.F Bit Name F:0 Package ID LSW [F:0] Description Bits 15 - 0 of Package ID Type Default RO Table 6.944 Global Standard Package Identifier 2: Address 1E.F Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.9 Global Firmware ID: Address 1E.20 Bit Name F:8 Firmware Major Revision Number [7:0] [F:8] = Major revision number Firmware Minor Revision Number [7:0] [7:0] = Minor revision number 7:0 Description Type Default Note RO The lower six bits of major and minor firmware revision are exchanged in autonegotiation when the PHYID message is sent. RO Table 6.945 Global Firmware ID: Address 1E.20 AQR405 Revision 0.11 - January 5, 2015 6.11.10 Global NVR Interface 1: Address 1E.100 Bit Name Description Type Default Note NVR Execute Operation 1 = Start NVR Operation R/W SC 0 When set to 1, the NVR operation will begin. Ensure that the uP is stalled using the "uP Run Stall" bit to ensure no NVR contention. E NVR Write Mode 1 = Write to NVR 0 = Read from NVR R/W 0 D Freeze NVR CRC 1 = Freeze NVR Mailbox CRC calculation register R/W 0 To prevent an erroneous answer, this bit should not be set at the same time the "NVR Execute Operation" bit is set. C Reset NVR CRC 1 = Reset NVR Mailbox CRC calculation register R/W SC 0 To prevent an erroneous answer, this bit should not be set at the same time the "NVR Execute Operation" bit is set. B Reserved Internal reserved - do not modify Table 6.946 Global NVR Interface 1: Address 1E.100 553 F Bit Name Description Type Default R/W 0 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 A NVR Burst 0 = Single read or write operation of up to 4 bytes 1 = Burst operation 9 Reserved Internal reserved - do not modify 8 NVR Busy 1 = NVR is busy 0 = NVR is ready RO NVR Opcode [7:0] NVR instruction opcode R/W 7:0 Note When this bit is set, the operation is a burst operation where more than 32-bits is read from the NVR or written to the NVR. This bit should be set to one until the last burst in the read or write operation, when it should be set to zero. It operates by gating the SPI clock, and not restarting it until new data is ready to be written, or the previous contents have been read. Each burst of data requires the NVR Execute Operation bit to be set to initiate the next phase. When set to 1, the NVR is busy. A new NVR operation should not occur until this bit is 0. If the NVR clock is greater than 64/63 of the MDIO clock, this bit never needs to be polled when operating over the MDIO. 0x03 Table 6.946 Global NVR Interface 1: Address 1E.100 6.11.11 Global NVR Interface 2: Address 1E.101 Bit Name Description F:0 NVR Mailbox CRC [F:0] The running CRC-16 of everything passing through the NVR interface Type RO Default Note The CRC-16 over all data written or read through the NVR interface. The CRC-16 is calculated by dividing the data by: x^16 + x^12 + x^5 + 1 Table 6.947 Global NVR Interface 2: Address 1E.101 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.12 Global NVR Interface 3: Address 1E.102 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:0 NVR Address MSW [17:10] NVR address MSW bits [17:10] Type Default R/W 0x00 Note The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. The increment amount is based on the data length (i.e. increments by 4 if the data length is 4 bytes) Table 6.948 Global NVR Interface 3: Address 1E.102 AQR405 Revision 0.11 - January 5, 2015 6.11.13 Global NVR Interface 4: Address 1E.103 Bit F:0 Name NVR Address LSW [F:0] Description NVR address LSW bits [F:0] Type Default Note R/W 0x0000 The address of where to read and write from in the NVR. This is self-incrementing and will automatically increment after each read or write operation. Table 6.949 Global NVR Interface 4: Address 1E.103 555 6.11.14 Global NVR Interface 5: Address 1E.104 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 NVR Data MSW [1F:10] Description NVR data MSW bits [1F:10] Type Default R/W 0x0000 Note Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: AA BB in the MSW CC DD in the LSW. Table 6.950 Global NVR Interface 5: Address 1E.104 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.15 Global NVR Interface 6: Address 1E.105 Bit Name F:0 NVR Data LSW [F:0] Description NVR data LSW bits [F:0] Type Default Note R/W 0x0000 Data is stored and read-out from these registers in little-endian format for operations such as FLASH device ID, and for programming the processor. AQR405 Revision 0.11 - January 5, 2015 For instance the 64K Atmel device code reads out as two bytes 0x651F into the LSW register, whereas the datasheet indicates that 1F is the first byte read, followed by 65 as the second byte. To burst read and write these 4 bytes in the correct order (where DD is written to address x), they should be stored as: AA BB in the MSW CC DD in the LSW. Table 6.951 Global NVR Interface 6: Address 1E.105 6.11.16 Global Mailbox Interface 1: Address 1E.200 Bit Name Description Type Default Note uP Mailbox Execute Operation 1 = Start of mailbox Operation R/W SC 0 Indicates mailbox is loaded and ready E uP Mailbox Write Mode 1 = Write 0 = Read R/W 0 Mailbox direction D Reserved Internal reserved - do not modify Table 6.952 Global Mailbox Interface 1: Address 1E.200 557 F Bit C AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential B:9 8 7:0 Name Description Reset uP Mailbox CRC 1 = Reset uP mailbox CRC calculation register Reserved Internal reserved - do not modify uP Mailbox Busy 1 = uP mailbox busy 0 = uP mailbox ready Reserved Internal reserved - do not modify Type Default R/W SC 0 RO Note In general the uP will respond within a few processor cycles to any PIF slave request, much faster than the MDIO. If the busy is asserted over multiple MDIO polling cycles, then a H/W error may have occurred and a Global S/W reset or uP reset is required. Table 6.952 Global Mailbox Interface 1: Address 1E.200 6.11.17 Global Mailbox Interface 2: Address 1E.201 Bit F:0 Name uP Mailbox CRC [F:0] Description The running CRC-16 of everything passing through the mailbox interface Type Default RO Table 6.953 Global Mailbox Interface 2: Address 1E.201 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.18 Global Mailbox Interface 3: Address 1E.202 Bit F:0 Name uP Mailbox Address MSW [1F:10] Description uP Mailbox MSW address Type Default Note R/W 0x0000 The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.AQR405 Table 6.954 Global Mailbox Interface 3: Address 1E.202 6.11.19 Global Mailbox Interface 4: Address 1E.203 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note 0x0000 The address of where to read and write from in the Microcontroller Mailbox. This is self-incrementing and automatically increments after each read and write operation.AQR405 F:2 uP Mailbox Address LSW [F:2] uP LSW Mailbox address [F:2] R/W 1:0 uP Mailbox Address LSW Don't Care [1:0] Least significant uP LSW Mailbox address bits [1:0] RO These bits are always set to 0 since each memory access is on a 4-byte boundary. Table 6.955 Global Mailbox Interface 4: Address 1E.203 6.11.20 Global Mailbox Interface 5: Address 1E.204 Name F:0 uP Mailbox Data MSW [1F:10] Description uP Mailbox data MSW Type Default R/W 0x0000 Table 6.956 Global Mailbox Interface 5: Address 1E.204 Note 559 Bit 6.11.21 Global Mailbox Interface 6: Address 1E.205 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:0 uP Mailbox Data LSW [F:0] Description uP Mailbox data LSW Type Default R/W 0x0000 Note Table 6.957 Global Mailbox Interface 6: Address 1E.205 6.11.22 Global Mailbox Interface 7: Address 1E.206 Bit F:2 Name Description Reserved Internal reserved - do not modify 1 uP Mailbox CRC Read Enable 1 = Update uP mailbox CRC on read 0 Reserved Internal reserved - do not modify Type Default R/W 0 Note Table 6.958 Global Mailbox Interface 7: Address 1E.206 6.11.23 Global Microprocessor Scratch Pad 1: Address 1E.300 Bit F:0 Name Scratch Pad 1[F:0] Description General Purpose Scratch Pad Type Default R/W 0x0000 Table 6.959 Global Microprocessor Scratch Pad 1: Address 1E.300 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.24 Global Microprocessor Scratch Pad 2: Address 1E.301 Bit F:0 Name Scratch Pad 2 [F:0] Description General Purpose Scratch Pad Type Default R/W 0x0000 Note Table 6.960 Global Microprocessor Scratch Pad 2: Address 1E.301 6.11.25 Global Control 1: Address 1E.C000 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 Table 6.961 Global Control 1: Address 1E.C000 6.11.26 Global Control 2: Address 1E.C001 Bit Name Description F uP Reset 1 = Reset E:7 Reserved Internal reserved - do not modify uP Run Stall Override 0 = uP Run Stall from "MDIO Boot Load" pin. 1 = uP Run Stall from "uP Run Stall" bit 6 Type Default Note R/W 0 Resets the uP and the PIF master and slave bus. Will be active for a minimum of 100 microseconds. R/W 0 This bit selects the uP Run Stall from either the "MDIO Boot Load" pin or the "uP Run Stall" bit. Pin no longer brought out as deprecated. 561 Table 6.962 Global Control 2: Address 1E.C001 Bit 5:1 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 0 Name Description Reserved Internal reserved - do not modify uP Run Stall 1 = uP Run Stall 0 = uP normal mode Type Default R/W 0 Note Deactivates the uP. Table 6.962 Global Control 2: Address 1E.C001 6.11.27 Global Reset Control: Address 1E.C006 Bit Name Description F Reserved Internal reserved - do not modify E Global MMD Reset Disable 1 = Disable the S/W reset to the Global MMD registers 0 = Enable the S/W reset to the Global MMD registers Reserved Internal reserved - do not modify D:0 Type Default R/W PD 0 Note Setting this bit prevents a Global S/W reset or Global S/W reset from resetting the Global MMD registers Table 6.963 Global Reset Control: Address 1E.C006 6.11.28 Global Diagnostic Provisioning: Address 1E.C400 Bit F E:0 Name Description Enable Diagnostics 1 = Chip performs diagnostics on power-up Reserved Internal reserved - do not modify Type Default R/W PD 1 Table 6.964 Global Diagnostic Provisioning: Address 1E.C400 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.29 Global Thermal Provisioning 1: Address 1E.C420 Bit Name F:0 Reserved 0 [F:0] Description Internal reserved - do not modify Type Default R/W PD 0x0000 Note Table 6.965 Global Thermal Provisioning 1: Address 1E.C420 6.11.30 Global Thermal Provisioning 2: Address 1E.C421 Bit F:0 Name AQR405 Revision 0.11 - January 5, 2015 High Temp Failure Threshold [F:0] Description [F:0] of high temperature failure threshold Type Default R/W PD 0x4600 Note 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 70C. In XENPAK mode, F/W will use the XENPAK register 1.A000 - 1.A001: instead of this register. NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). Table 6.966 Global Thermal Provisioning 2: Address 1E.C421 563 6.11.31 Global Thermal Provisioning 3: Address 1E.C422 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Low Temp Failure Threshold [F:0] Description [F:0] of low temperature failure threshold Type Default R/W PD 0x0000 Note 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 0C. In XENPAK mode, F/W will use the XENPAK register 1.A002 - 1.A003: instead of this register. NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). Table 6.967 Global Thermal Provisioning 3: Address 1E.C422 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.32 Global Thermal Provisioning 4: Address 1E.C423 Bit F:0 Name High Temp Warning Threshold [F:0] Description [F:0] of high temperature warning threshold Type R/W PD Default 0x3C00 Note 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD008. Default is 60C. In XENPAK mode, F/W will use the XENPAK register 1.A004 - 1.A005: instead of this register. AQR405 Revision 0.11 - January 5, 2015 NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). Table 6.968 Global Thermal Provisioning 4: Address 1E.C423 565 6.11.33 Global Thermal Provisioning 5: Address 1E.C424 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Description Low Temp Warning Threshold [F:0] [F:0] of low temperature warning threshold Type Default R/W PD 0x0A00 Note 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 10C. In XENPAK mode, F/W will use the XENPAK register 1.A006 - 1.A007: instead of this register. NOTE! All Thresholds are orthogonal and can be set to any value regardless the value of the other thresholds. i.e. High-Temperature-Warning (1E.C423) could be higher than High-Temperature-Failure (1E.C421). Table 6.969 Global Thermal Provisioning 5: Address 1E.C424 6.11.34 Global LED Provisioning 1: Address 1E.C430 Bit Name F LED #0 5 Gb/s Link Established E D:9 Description Type Default 1 = LED is on when link connects at 5 Gb/s R/W PD 0 LED #0 2.5 Gb/s Link Established 1 = LED is on when link connects at 2.5 Gb/s R/W PD 0 Reserved Provisioning C430 [4:0] Reserved for future use R/W PD 0x00 Table 6.970 Global LED Provisioning 1: Address 1E.C430 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 8 LED #0 Manual Set 7 Description AQR405 Revision 0.11 - January 5, 2015 Type Default 1 = LED On R/W PD 0 LED #0 10 Gb/s Link Established 1 = LED is on when link connects at 10 Gb/s R/W PD 0 6 LED #0 1 Gb/s Link Established 1 = LED is on when link connects at 1 Gb/s R/W PD 0 5 LED #0 100 Mb/s Link Established 1 = LED is on when link connects at 100 Mb/s. R/W PD 0 4 LED #0 Connecting 1 = LED is on when attempting to connect. R/W PD 0 3 LED #0 Receive Activity 1 = LED toggles on receive activity R/W PD 0 2 LED #0 Transmit Activity 1 = LED toggles on transmit activity R/W PD 0 1:0 LED #0 Activity Stretch [1:0] [1:0] 0x3 = stretch activity by 100 ms 0x2 = stretch activity by 60 ms 0x1 = stretch activity by 28 ms 0x0 = no stretching R/W PD 0x3 Note Table 6.970 Global LED Provisioning 1: Address 1E.C430 567 6.11.35 Global LED Provisioning 2: Address 1E.C431 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F LED #1 5 Gb/s Link Established E D:9 Description Type Default 1 = LED is on when link connects at 5 Gb/s R/W PD 0 LED #1 2.5 Gb/s Link Established 1 = LED is on when link connects at 2.5 Gb/s R/W PD 0 Reserved Provisioning C431 [4:0] Reserved for future use R/W PD 0x00 Table 6.971 Global LED Provisioning 2: Address 1E.C431 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 8 LED #1 Manual Set 7 Description AQR405 Revision 0.11 - January 5, 2015 Type Default 1 = LED On R/W PD 0 LED #1 10 Gb/s Link Established 1 = LED is on when link connects at 10 Gb/s R/W PD 0 6 LED #1 1 Gb/s Link Established 1 = LED is on when link connects at 1 Gb/s R/W PD 0 5 LED #1 100 Mb/s Link Established 1 = LED is on when link connects at 100 Mb/s. R/W PD 0 4 LED #1 Connecting 1 = LED is on when attempting to connect. R/W PD 0 3 LED #1 Receive Activity 1 = LED toggles on receive activity R/W PD 0 2 LED #1 Transmit Activity 1 = LED toggles on transmit activity R/W PD 0 1:0 LED #1 Activity Stretch [1:0] [1:0] 0x3 = stretch activity by 100 ms 0x2 = stretch activity by 60 ms 0x1 = stretch activity by 28 ms 0x0 = no stretching R/W PD 0x3 Note Table 6.971 Global LED Provisioning 2: Address 1E.C431 569 6.11.36 Global LED Provisioning 3: Address 1E.C432 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F LED #2 5 Gb/s Link Established E D:9 Description Type Default 1 = LED is on when link connects at 5 Gb/s R/W PD 0 LED #2 2.5 Gb/s Link Established 1 = LED is on when link connects at 2.5 Gb/s R/W PD 0 Reserved Provisioning C432 [4:0] Reserved for future use R/W PD 0x00 Table 6.972 Global LED Provisioning 3: Address 1E.C432 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name 8 LED #2 Manual Set 7 Description AQR405 Revision 0.11 - January 5, 2015 Type Default 1 = LED On R/W PD 0 LED #2 10 Gb/s Link Established 1 = LED is on when link connects at 10 Gb/s R/W PD 0 6 LED #2 1 Gb/s Link Established 1 = LED is on when link connects at 1 Gb/s R/W PD 0 5 LED #2 100 Mb/s Link Established 1 = LED is on when link connects at 100 Mb/s. R/W PD 0 4 LED #2 Connecting 1 = LED is on when attempting to connect. R/W PD 0 3 LED #2 Receive Activity 1 = LED toggles on receive activity R/W PD 0 2 LED #2 Transmit Activity 1 = LED toggles on transmit activity R/W PD 0 1:0 LED #2 Activity Stretch [1:0] [1:0] 0x3 = stretch activity by 100 ms 0x2 = stretch activity by 60 ms 0x1 = stretch activity by 28 ms 0x0 = no stretching R/W PD 0x3 Note Table 6.972 Global LED Provisioning 3: Address 1E.C432 6.11.37 Global LED Provisioning 4: Address 1E.C433 Bit Reserved Description Type Default Internal reserved - do not modify Table 6.973 Global LED Provisioning 4: Address 1E.C433 Note 571 F:0 Name 6.11.38 Global LED Provisioning 5: Address 1E.C434 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.974 Global LED Provisioning 5: Address 1E.C434 6.11.39 Global LED Provisioning 6: Address 1E.C435 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.975 Global LED Provisioning 6: Address 1E.C435 6.11.40 Global LED Provisioning 7: Address 1E.C436 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.976 Global LED Provisioning 7: Address 1E.C436 6.11.41 Global LED Provisioning 8: Address 1E.C437 Bit F:1 0 Name Description Reserved Internal reserved - do not modify LED Operation Mode 1 = LED link activity in Mode #2 0 = LED link activity in Aquantia classic mode Type Default R/W PD 0 Note When set to 1, the LED blinking rate is based on Mode #2 algorithm. When set to 0, the LED blinking rate is based on the classic Aquantia algorithm. Table 6.977 Global LED Provisioning 8: Address 1E.C437 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.42 Global LED Provisioning 15: Address 1E.C43E Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.978 Global LED Provisioning 15: Address 1E.C43E 6.11.43 Global General Provisioning 1: Address 1E.C440 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 Table 6.979 Global General Provisioning 1: Address 1E.C440 6.11.44 Global General Provisioning 2: Address 1E.C441 Bit Name Description Type Default Note F Reserved Internal reserved - do not modify E MDIO Broadcast Mode Enable 1 = Enable broadcast on address set in 1E.C446 0 = Disable broadcast on n address set in 1E.C446 R/W PD 0 When enabled, writes and load MMD address opcodes are supported. Read opcodes are ignored. D MDIO Read MSW First Enable 1 = MSW of counter must be read first 0 = LSW of counter must be read first R/W PD 0 This bit configures whether the MSW or LSW must be read first for counters greater than 16 bits. Reserved Internal reserved - do not modify C:5 573 Table 6.980 Global General Provisioning 2: Address 1E.C441 Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 4 MDIO Drive Configuration 0 = MDIO driver is in normal mode 1 = MDIO driver is in open drain mode R/W PD 0 3 MDIO Preamble Detection Disable 1 = Suppress preamble detection on MDIO 0 = Enable preamble detection on MDIO R/W PD 0 2 Reserved Internal reserved - do not modify 1:0 Reserved Internal reserved - do not modify Note When the MDIO driver is in open drain mode during a read cycle, "0" data will be actively driven out of the MDIO, "1" data will set the MDIO driver in high impedance state and an external pullup will set the MDIO line to "1". The Turn-Around "0" will also be actively driven out of the MDIO, therefore in open drain mode, the Turn-Around is still "Z0". Table 6.980 Global General Provisioning 2: Address 1E.C441 6.11.45 Global General Provisioning 3: Address 1E.C442 Bit F:1 0 Name Description Reserved Internal reserved - do not modify Daisy Chain Reset 1 = Reset the daisy chain Type Default R/W 0 Note Toggling this bit from 0 to 1 will reload the IRAM and DRAM and reset the uP. The uP will be in uP run stall during the reload process. After the reload process, uP run stall will be de-asserted and the uP reset will be asserted. Note that before setting this bit, the "Soft Reset" bit needs to be de-asserted. Table 6.981 Global General Provisioning 3: Address 1E.C442 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.46 Global General Provisioning 4: Address 1E.C443 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.982 Global General Provisioning 4: Address 1E.C443 6.11.47 Global General Provisioning 5: Address 1E.C444 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify AQR405 Revision 0.11 - January 5, 2015 Table 6.983 Global General Provisioning 5: Address 1E.C444 6.11.48 Global General Provisioning 6: Address 1E.C445 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.984 Global General Provisioning 6: Address 1E.C445 6.11.49 Global General Provisioning 7: Address 1E.C446 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.985 Global General Provisioning 7: Address 1E.C446 575 6.11.50 Global General Provisioning 8: Address 1E.C447 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F:5 Reserved Internal reserved - do not modify 4:0 MDIO Broadcast Address Configuration [4:0] Broadcast address Type Default R/W PD 0x1F Note Allows setting the broadcast address. By default this is set to 0x1F Table 6.986 Global General Provisioning 8: Address 1E.C447 6.11.51 Global General Provisioning 9: Address 1E.C448 Bit F:0 Name Reserved Description Type Default Note Internal reserved - do not modify Table 6.987 Global General Provisioning 9: Address 1E.C448 6.11.52 Global General Provisioning 10: Address 1E.C449 Bit Name Description F:7 Reserved Internal reserved - do not modify 6:0 MDIO Preamble Length [6:0] MDIO Preamble Length Type Default R/W 0x02 Table 6.988 Global General Provisioning 10: Address 1E.C449 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.53 Global NVR Provisioning 1: Address 1E.C450 Bit Name Description AQR405 Revision 0.11 - January 5, 2015 F:B Reserved Internal reserved - do not modify A:8 NVR Data Length [2:0] NVR data length ranges from 0 bytes to 4 bytes Reserved Internal reserved - do not modify 6:4 NVR Dummy Length [2:0] NVR dummy length ranges from 0 bytes to 4 bytes 3:2 Reserved Internal reserved - do not modify 1:0 NVR Address Length [1:0] NVR address length ranges from 0 bytes up to 3 bytes 7 Type Default Note R/W PD 0x4 This sets the length of the data burst used in read and write operations. R/W PD 0x0 This sets the length of the dummy field used in some manufacturer's read status and write status operations. R/W PD 0x2 This sets the length of the address field used in read and write operations. Use of this field is enabled via Bit 8 of "Global NVR Provisioning 2: Address 1E.C451" on page 578. Table 6.989 Global NVR Provisioning 1: Address 1E.C450 577 6.11.54 Global NVR Provisioning 2: Address 1E.C451 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:9 8 7:0 Name Description Type Default Reserved Internal reserved - do not modify NVR Address Length Override 0 = NVR address length is based on the "NVR_SIZE" pin. 1 = NVR address length is based on the "NVR Address Length [1:0]" register R/W PD 0 NVR Clock Divide [7:0] NVR clock divide. Clock frequency is divided by the NVR clock divide + 1 R/W PD 0xA0 Note When this bit = 0 and NVR_SIZE pin = 0, the NVR address length is 2 bytes. When this bit = 0 and the NVR_SIZE pin = 1, the NVR address length is 3 bytes. When this bit = 1 the NVR address length is from the "NVR Address Length [1:0]" Table 6.990 Global NVR Provisioning 2: Address 1E.C451 6.11.55 Global NVR Provisioning 3: Address 1E.C452 Bit F:2 Name Description Type Default Note Reserved Internal reserved - do not modify 1 NVR Daisy Chain Clock Divide Override 1 = Override NVR clock divide when in daisy chain master mode R/W 0 When in daisy chain master mode, the clock divide configuration is received from the FLASH. This bit will override the clock divide configuration from the FLASH with the "NVR Clock Divide [7:0]" . 0 NVR Daisy Chain Disable 1 = Disable the Daisy Chain R/W 0 When in daisy chain master mode, the daisy chain and MDIO can both access the SPI. Setting this bit to 1 will disable the daisy chain from accessing the SPI and force it into a reset state. Table 6.991 Global NVR Provisioning 3: Address 1E.C452 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.56 Global NVR Provisioning 4: Address 1E.C453 Bit F:5 4 3:0 Name Description Reserved Internal reserved - do not modify NVR Reset 1 = Reset SPI Reserved Internal reserved - do not modify Type Default R/W 0 Note Table 6.992 Global NVR Provisioning 4: Address 1E.C453 AQR405 Revision 0.11 - January 5, 2015 579 6.11.57 Global Reserved Provisioning 1: Address 1E.C470 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:D Name Description Type Default Diagnostics Select 1 = Provide Extended MDI Diagnostics Information. 0 = Provide normal cable diagnostics R/W PD 0 Extended MDI Diagnostics Select [1:0] 0x0 = TDR Data 0x1 = RFI Channel PSD 0x2 = Noise PSD while the local Tx is Off 0x3 = Noise PSD while the local Tx is On R/W PD 0x0 Note These bits select what sort of cable diagnostics to perform. For regular cable diagnostics, Bit F is set to zero, and the diagnostics are triggered by setting Bit 4. For extended diagnostics, Bit F is set to 1, and the desired extended diagnostics are selected by Bits E:D. The routine is then triggered by setting Bit 4. Each of the extended diagnostic routines present data for all for MDI pairs (A, B, C, D) consecutively, and after the data for each channel is gathered Bits F:D are reset. To get the data for the next pair, Bits F:D must be set back to the desired value (which must be the same as the initial channel). This continues until the data for all channels has been gathered. The address in memory where the data is stored is given in 1E.C802 and 1E.C804. For the case of PSD, the structure is as follows: Int32 info Int16 data[Len] Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.) For TDR: Int32 info Int16 tdr_A[Len] Int16 tdr_B[Len] Int16 tdr_C[Len] Int16 tdr_D[Len] Info = Len << 16 | Channel TDR data is from the current pair to all other pairs. At the end of retrieving extended MDI diag data, the part will be reset. Conversely the only way to exit this routine once it starts is to issue a PMA reset. Table 6.993 Global Reserved Provisioning 1: Address 1E.C470 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description C:8 Reserved Internal reserved - do not modify 7 Trigger Diagnostic Interrupt 1 = Trigger Diagnostic Interrupt 6:5 Reserved Internal reserved - do not modify Initiate Cable Diagnostics 1 = Perform cable diagnostics 4 Type Default R/W SC 0 R/W SC 0 Note Perform cable diagnostics regardless of link state. If link is up, setting this bit will cause the link to drop while diagnostics are performed. This bit is self-clearing upon completion of the cable diagnostics. AQR405 Revision 0.11 - January 5, 2015 NOTE!! This is a processor intensive operation. Completion of this operation can also be monitored via 1E.C831.F 3:0 Reserved Internal reserved - do not modify Table 6.993 Global Reserved Provisioning 1: Address 1E.C470 6.11.58 Global Reserved Provisioning 2: Address 1E.C471 Bit F:7 6 5:0 Name Description Type Default Internal reserved - do not modify Enable Daisy-Chain Hop-Count Override 1 = Hop-count is set by Bits 5:0 0 = Hop-count is determined by the daisy-chain R/W uP 0 Daisy-Chain Hop-Count Override Value [5:0] The value to use for the PHY's daisy-chain hop-count. Valid values are from 0 -> 47 R/W uP 0x00 Daisy-Chain Hop-Count Override should be used during MDIO boot-load operation, as the daisy-chain hop-count does not function when the daisy-chain is disabled (1E.C452.0). Setting this bit tells the processor where in the daisy-chain it is, so that the provisioning operation will function correctly. Table 6.994 Global Reserved Provisioning 2: Address 1E.C471 581 Reserved Note 6.11.59 Global Reserved Provisioning 3: Address 1E.C472 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default R/W PD 0 This bit controls whether the PHY attempts to tune the external VDD power supply via the SMBus. This bit is only operational if the external supply is present. (See 1E.C472.6) This bit must be set if tuning of external power supply is desired. F Reserved Internal reserved - do not modify E Enable VDD Power Supply Tuning 1 = Enable external VDD power supply tuning 0 = Disable external VDD power supply tuning is disabled Reserved Internal reserved - do not modify Tunable External VDD Power Supply Present 1 = Tunable external VDD power supply present 0 = No tunable external VDD power supply present R/W PD 0 5:2 External VDD Change Request [3:0] The amount of VDD change requested by firmware, in mV (2's complement value). R/W PD 0x0 1 Enable XENPAK Register Space 1 = XENPAK register space enabled 0 = XENPAK register space disabled R/W PD uP 0 0 Enable 5th Channel RFI Cancellation 1 = 5th channel and RFI cancellers operation enabled 0 = 5th channel AFE is powered down, 5th channel digital is clock gated, RFI cancellers are disabled R/W PD uP 0 D:7 6 Note Note: The value of this bit at the time of Autonegotiation sets the local PHY behavior until the next time Autonegotiation occurs. Table 6.995 Global Reserved Provisioning 3: Address 1E.C472 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.60 Global Reserved Provisioning 4: Address 1E.C473 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 F:B Reserved Internal reserved - do not modify A:8 Rate Transition Request [2:0] 0 = No Transition 1 = Reserved 2 = Reserved 3 = Retrain at 10G 4 = Retrain at 5G 5 = Retrain at 2.5G 6 = Retrain at 1G 7 = Reserved R/W PD 0x0 7:0 Training SNR [7:0] SNR during 10G training on the worst channel. SNR is in steps of 0.1dB R/W PD 0x00 Note The SNR margin that is enjoyed by the worst channel, over and above the minimum SNR required to operate at a BER of 10-12. It is reported with 0.1 dB of resolution to an accuracy of 0.5 dB within the range of -12.7 dB to 12.7 dB. The number is in offset binary, with 0.0 dB represented by 0x8000. Table 6.996 Global Reserved Provisioning 4: Address 1E.C473 583 6.11.61 Global Reserved Provisioning 5: Address 1E.C474 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default F:1 Reserved Provisioning 5 [F:1] Reserved for future use R/W PD 0x0000 0 NVR Daisy Chain Kickstart 1 = Kickstart the Daisy Chain R/W 0 Note When in daisy chain master mode, the PHY0 can kickstart the daisy chain. The kickstart will not reload the IRAM/DRAM or reset the uP for PHY0. It will just read the FLASH and transfer the FLASH data to the daisy chain. Table 6.997 Global Reserved Provisioning 5: Address 1E.C474 6.11.62 Global Reserved Provisioning 6: Address 1E.C475 Bit F:E Name Description Type Default Reserved Internal reserved - do not modify D Smart Power-Down Status 1 = Smart Power-Down Active 0 = Smart Power-Down Inactive R/W PD 0 C Reserved Provisioning 6 Internal reserved - do not modify R/W PD 0 B CFR LP Disable Timer 1 = Link partner requires cfr_disable timer 0 = Link partner does not require cfr_disable timer R/W PD 0 Table 6.998 Global Reserved Provisioning 6: Address 1E.C475 Note Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 A CFR LP Extended Maxwait 1 = Link partner requires extended maxwait 0 = Link partner does not require extended maxwait R/W PD 0 9 CFR LP THP 1 = Link partner requires local PHY to enable THP 0 = Link partner does not require local PHY to enable THP R/W PD 0 8 CFR LP Support 1 = Link partner supports Cisco Fast Retrain 0 = Link partner does support Cisco Fast Retrain R/W PD 0 7 CFR Disable Timer 1 = Local PHY requires cfr_disable timer 0 = Local PHY does not require cfr_disable timer R/W PD 0 6 CFR Extended Maxwait 1 = Local PHY requires extended maxwait 0 = Local PHY does not require extended maxwait R/W PD 0 5 CFR THP 1 = Local PHY requires local PHY to enable THP 0 = Local PHY does not require local PHY to enable THP R/W PD 0 585 Table 6.998 Global Reserved Provisioning 6: Address 1E.C475 Note Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 4 CFR Support 1 = Local PHY supports Cisco Fast Retrain 0 = Local PHY does support Cisco Fast Retrain R/W PD 0 3 Deadlock Avoidance Enable 1 = SPD with deadlock avoidance: PHY transmits autonegotiation pulses (FLPs) at a slower rate (~ 1 FLP/ 100ms) than specified by autonegotiation standard (~1 FLP / 8.25ms). Receiver is active and able to detect the pulses. 0 = SPD without deadlock avoidance: PHY transmitter is shut down, no autonegotiation pulses are sent on the line but the receiver is active and able to detect the pulses R/W PD 0 2 Smart Power-Down Enable 1 = Enable smart power down mode 0 = Smart power-down mode disabled R/W PD 0 Reserved Internal reserved - do not modify 1:0 Note Smart power down (SPD) is the lowest power mode at which PHY is able to autonegotiate. SPD can be enabled with bit 1E.C475.2 Table 6.998 Global Reserved Provisioning 6: Address 1E.C475 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.63 Global Reserved Provisioning 9: Address 1E.C478 Bit F Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 DTE Enable 1 = Enable DTE 0 = Disable DTE R/W PD 0 E:B DTE Drop Reporting Timer [3:0] Number of seconds between loss of link partner filter and assertion of no-power-needed state, in 5 second increments (e.g. 0x4 = 20 seconds). R/W PD 0x0 A:0 Reserved Provisioning 9 [A:0] Reserved for future use R/W PD 0x000 Note These bits are used to set how long the PHY waits after it no longer detects the link partner filter before declaring that power is not needed. Table 6.999 Global Reserved Provisioning 9: Address 1E.C478 6.11.64 Global Reserved Provisioning 10: Address 1E.C479 Bit Name Description Type Default F Power Up Stall 1 = Stall FW at Power Up 0 = Unstall the FW R/W PD 0 E:0 Reserved Provisioning 10 [E:0] Reserved for future use R/W PD 0x0000 Note This bit needs to be provisioned in Power Up Init for firmware to stall. Table 6.1000 Global Reserved Provisioning 10: Address 1E.C479 587 6.11.65 Global Reserved Provisioning 11: Address 1E.C47A AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:B A:6 Name Loopback Control [4:0] Reserved Provisioning 11 [4:0] Description Type Default 0x00 = No loopback 0x01 = System Interface - System Loopback 0x02 = System Interface - System Loopback with Passthrough 0x03 = System Interface - Network Loopback 0x04 = System Interface - Network Loopback with Passthrough 0x05 = System Interface - Network Loopback with Passthrough and Merge 0x06 = System Interface - Peer-to-peer loopback 0x07 - 0x08 = Reserved 0x09 = Network Interface - System Loopback 0x0A = Network Interface - System Loopback with Passthrough 0x0B = Network Interface - Network Loopback 0x0C = Network Interface - Network Loopback with Passthrough 0x0D = Network Interface - Peer-to-peer loopback 0x0E - 0x0F = Reserved 0x10 = Cross-connect System Loopback 0x11 = Cross-connect Network Loopback 0x12 - 0x13 = Reserved 0x14 = Network Interface - System Loopback via Loopback Plug 0x15 - 0x1F = Reserved R/W PD 0x00 Reserved for future use R/W PD Note These bits, in conjunction with the chip configuration and the rate (Bits 1:0), select the loopback to configure for the chip. Setting one of these loopbacks provisions the chip for the specified loopback. Upon clearing the loopback, the chip returns to it's configuration prior to entering loopback (irregardless of whether other loopbacks were selected after the initial loopback). NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F. The controls in this register are identical to, and mirrored with, the controls in 4.C444. 0x00 Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 5 Name MDI Packet Generation Description Type Default 1 = CRPAT packet generation out MDI interface 0 = No CRPAT packet generation out MDI interface R/W PD 0 Note Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on the MDI interface at the selected rate. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F The controls in this register are identical to, and mirrored with, the controls in 4.C444. 4 AQR405 Revision 0.11 - January 5, 2015 Look-Aside Port Packet Generation 1 = CRPAT packet generation out 10G look-aside interface (KR0) 0 = No CRPAT packet generation out 10G look-aside interface (KR0) R/W PD 0 Selecting this mode of operation causes the CRPAT packet generator in the PHY to output on KR0. NOTE!! This only functions if KR1 (SERDES2) is selected as the system interface in (4.C441.F:E). NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F The controls in this register are identical to, and mirrored with, the controls in 4.C444. Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A 589 Bit 3 Name AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential System I/F Packet Generation Description Type Default 1 = CRPAT packet generation out 10G system interface 0 = No CRPAT packet generation out 10G system interface R/W PD 0 Note Selecting this mode of operation causes the CRPAT packet generator in the PHY to output CRPAT packets on the selected 10G system interface (4.C441.F:E) NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F The controls in this register are identical to, and mirrored with, the controls in 4.C444. 2:0 Rate [2:0] 0x7 - 0x6 = reserved 0x5 = 5G 0x4 = 2.5G 0x3 = 10G 0x2 = 1G 0x1 = 100M 0x0 = reserved R/W PD 0x0 These bits select the rate for the loopback and packet generation. SERDES configuration, as well autonegotiation is controlled accordingly when a loopback is selected. For instance, if 100M system loopback on the network interface is selected, SGMII on the system interface is enabled to connect at 100M, and if passthrough is enabled 100BASE-TX will be the only advertised rate and will force a re-autonegotiation if not already connected at 100M. NOTE!! This is a processor intensive operation. Completion of this operation can be monitored via 1E.C831.F The controls in this register are identical to, and mirrored with, the controls in 4.C444. Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.66 Global Reserved Provisioning 12: Address 1E.C47B Bit Name Description Type Default Note F:2 Reserved Provisioning 12 [D:0] Reserved for future use R/W PD 0x0000 1 Enable MACSec 1 = MACSec functionality is enabled 0 = MACSec functionality is disabled R/W PD 0 If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. 0 Enable PTP 1 = PTP functionality is enabled 0 = PTP functionality is disabled R/W PD 0 If this bit is 1, the PTP/SEC block will be included in the data path, regardless of operating mode. AQR405 Revision 0.11 - January 5, 2015 Table 6.1002 Global Reserved Provisioning 12: Address 1E.C47B 6.11.67 PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C Bit F:0 Name PIF Mailbox Address [F:0] Description The least 16 bits of the PIF address to read or write. Type Default R/W PD uP 0x0000 Note Table 6.1003 PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C 6.11.68 PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D Name F:0 PIF Mailbox Data [F:0] Description Type Default The data to be written, or that had been read. R/W PD uP 0x0000 Note Table 6.1004 PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D 591 Bit 6.11.69 PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name F:C Reserved PIF Mailbox Control 3 [3:0] B:8 7:0 Description Type Default Reserved for future use R/W PD 0x0 PIF Mailbox Command Type [3:0] 0 = No Action 1 = Read 2 = Write R/W PD uP 0x0 PIF Mailbox MMD [7:0] MMD (upper 8 bits) of the PID address to read or write. R/W PD uP 0x00 Note System SW writes non-zero value to start a PIF command. Table 6.1005 PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E 6.11.70 PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F Bit Name F:4 Reserved PIF Mailbox Control 4 [B:0] 3:0 PIF Mailbox Command Status [3:0] Description Type Default Reserved for future use R/W PD 0x000 0 = Idle 1 = Command completed 2 = Command did not complete R/W PD uP 0x0 Note System SW should write 0 before writing Command Type to clear completion status Table 6.1006 PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.71 Global SMBus 0 Provisioning 6: Address 1E.C485 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:1 SMB 0 Slave Address [7:1] SMB slave address configuration Reserved Internal reserved - do not modify 0 Type Default R/W 0x00 Note Table 6.1007 Global SMBus 0 Provisioning 6: Address 1E.C485 6.11.72 Global SMBus 1 Provisioning 6: Address 1E.C495 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description F:8 Reserved Internal reserved - do not modify 7:1 SMB 1 Slave Address [7:1] SMB slave address configuration Reserved Internal reserved - do not modify 0 Type Default R/W 0x00 Note Table 6.1008 Global SMBus 1 Provisioning 6: Address 1E.C495 6.11.73 Global EEE Provisioning 1: Address 1E.C4A0 Bit Name Description F:1 Reserved Internal reserved - do not modify 0 EEE Mode 1 = EEE mode of operation Default R/W PD 0 Note EEE mode of operation (0=disable, 1=enable, default:0) Table 6.1009 Global EEE Provisioning 1: Address 1E.C4A0 593 Type 6.11.74 Global Cable Diagnostic Status 1: Address 1E.C800 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:C B A:8 7 6:4 Name Description Reserved Internal reserved - do not modify Pair A Status [2:0] [F:D] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 011= Connected to Pair D 010= Connected to Pair C 001= Connected to Pair B 000= OK Reserved Internal reserved - do not modify Pair B Status [2:0] [C:A] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 011= Connected to Pair A 010= Connected to Pair D 001= Connected to Pair C 000= OK Reserved Internal reserved - do not modify Pair C Status [2:0] [9:7] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 011= Connected to Pair B 010= Connected to Pair A 001= Connected to Pair D 000= OK Type Default Note RO This register summarizes the worst impairment on Pair A. RO This register summarizes the worst impairment on Pair B. RO This register summarizes the worst impairment on Pair C. Table 6.1010 Global Cable Diagnostic Status 1: Address 1E.C800 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 3 2:0 Name Description Reserved Internal reserved - do not modify Pair D Status [2:0] [6:4] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 011= Connected to Pair C 010= Connected to Pair B 001= Connected to Pair A 000= OK Type Default RO Note This register summarizes the worst impairment on Pair D. Table 6.1010 Global Cable Diagnostic Status 1: Address 1E.C800 AQR405 Revision 0.11 - January 5, 2015 6.11.75 Global Cable Diagnostic Status 2: Address 1E.C801 Bit Name Description Type F:8 Pair A Reflection #1 [7:0] The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair A RO 7:0 Pair A Reflection #2 [7:0] The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair A RO Default Note The distance to this reflection is given in "Global Cable Diagnostic Impedance 1: Address 1E.C880" . A value of zero indicates that this reflection does not exist or was not computed. Table 6.1011 Global Cable Diagnostic Status 2: Address 1E.C801 595 6.11.76 Global Cable Diagnostic Status 3: Address 1E.C802 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Impulse Response MSW [F:0] Description The MSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type in 1E.C470.E:D Type Default RO Note See 1E.C470 for more information Table 6.1012 Global Cable Diagnostic Status 3: Address 1E.C802 6.11.77 Global Cable Diagnostic Status 4: Address 1E.C803 Bit Name Description Type F:8 Pair B Reflection #1 [7:0] The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair B RO 7:0 Pair B Reflection #2 [7:0] The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair B RO Default Note The distance to this reflection is given in "Global Cable Diagnostic Impedance 2: Address 1E.C881" . A value of zero indicates that this reflection does not exist or was not computed. Table 6.1013 Global Cable Diagnostic Status 4: Address 1E.C803 6.11.78 Global Cable Diagnostic Status 5: Address 1E.C804 Bit F:0 Name Impulse Response LSW [F:0] Description The LSW of the memory location that contains the start of the impulse response data for the Extended Diagnostic type specified in 1E.C470.E:D Type RO Default Note See 1E.C470 for more information Table 6.1014 Global Cable Diagnostic Status 5: Address 1E.C804 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.79 Global Cable Diagnostic Status 6: Address 1E.C805 Bit Name Description Type F:8 Pair C Reflection #1 [7:0] The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair C RO 7:0 Pair C Reflection #2 [7:0] The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair C RO Default Note The distance to this reflection is given in "Global Cable Diagnostic Impedance 3: Address 1E.C882" . A value of zero indicates that this reflection does not exist or was not computed. Table 6.1015 Global Cable Diagnostic Status 6: Address 1E.C805 AQR405 Revision 0.11 - January 5, 2015 6.11.80 Global Cable Diagnostic Status 7: Address 1E.C806 Bit F:0 Name Reserved 1 [F:0] Description Reserved for future use Type Default Note RO Table 6.1016 Global Cable Diagnostic Status 7: Address 1E.C806 6.11.81 Global Cable Diagnostic Status 8: Address 1E.C807 Name Description Type F:8 Pair D Reflection #1 [7:0] The distance in meters, accurate to 1m, of the first of the four worst reflections seen by the PHY on Pair D RO 7:0 Pair D Reflection #2 [7:0] The distance in meters, accurate to 1m, of the second of the four worst reflections seen by the PHY on Pair D RO Default Note The distance to this reflection is given in "Global Cable Diagnostic Impedance 4: Address 1E.C883" . A value of zero indicates that this reflection does not exist or was not computed. Table 6.1017 Global Cable Diagnostic Status 8: Address 1E.C807 597 Bit 6.11.82 Global Thermal Status 1: Address 1E.C820 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F:0 Name Temperature [F:0] Description [F:0] of temperature Type Default RO Note 2's complement value with the LSB representing 1/256 of a degree Celsius. This corresponds to -40C = 0xD800. Default is 70C. This is a mirror of the XENPAK register 1.A060 - 1.A061. The mirror is performed in H/W. Table 6.1018 Global Thermal Status 1: Address 1E.C820 6.11.83 Global Thermal Status 2: Address 1E.C821 Bit F:1 0 Name Description Reserved Internal reserved - do not modify Temperature Ready 1 = Temperature measurement is valid Type Default RO Note This is a mirror of the XENPAK register 1.A06E. Table 6.1019 Global Thermal Status 2: Address 1E.C821 6.11.84 Global General Status 1: Address 1E.C830 Bit Name Description F Reserved Internal reserved - do not modify E High Temperature Failure State 1 = High temperature failure threshold has been exceeded Type Default Note 0 RO In XENPAK mode, F/W will copy this register to the 1.A070.7 register. Table 6.1020 Global General Status 1: Address 1E.C830 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 D Low Temperature Failure State 1 = Low temperature failure threshold has been exceeded RO In XENPAK mode, F/W will copy this register to the 1.A070.6 register. C High Temperature Warning State 1 = High temperature warning threshold has been exceeded RO In XENPAK mode, F/W will copy this register to the 1.A074.7 register. B Low Temperature Warning State 1 = Low temperature warning threshold has been exceeded RO In XENPAK mode, F/W will copy this register to the 1.A074.6 register. Reserved Internal reserved - do not modify A:0 Table 6.1020 Global General Status 1: Address 1E.C830 599 6.11.85 Global General Status 2: Address 1E.C831 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description F Processor Intensive MDIO Operation InProgress 1 = PHY microprocessor is busy with a processor-intensive MDIO operation 0 = Processor-intensive MDIO operation completed Type RO Default Note This bit should may be used with certain processor-intensive MDIO commands (such as Loopbacks, Test Modes, Low power modes, Tx-Disable, Restart autonegotiation, Cable Diagnostics, etc.) that take longer than an MDIO cycle to complete. Upon receiving an MDIO command that involves the PHY's microprocessor, this bit is set, and when the command is completed, this bit is cleared. NOTE!!! This bit should be checked only after 1 ms of issuing a processor-intensive MDIO operation. The list of operations that set this bit are as follows: AQR405 Revision 0.11 - January 5, 2015 E:0 Reserved Internal reserved - do not modify Table 6.1021 Global General Status 2: Address 1E.C831 601 1.0.0, PMA Loopback 1.0.B, Low power mode 1.9.4:0, Tx Disable 1.84, 10G Test modes 1.8000.5, XENPAK Control 1.9000, XENPAK Rx Fault Enable 1.9002, XENPAK Alarm Enable 1.E400.F, External loopback 3.0.B, Low power mode 3.0.E, System PCS loopback 3.C471.5, PRBS Test 3.C471.6, PRBS Test 3.E471.5, PRBS Test 3.E471.6, PRBS Test 4.0.B, Low power mode 4.0.E, PHY-XS network loopback 4.C440, Output clock control, Load SERDES parameters 4.F802.E, System loopback 4.C444.F:B, Loopback Control 4.C444.4:2, Packet generation 4.C445.C, SERDES calibration 7.0.9, Restart autonegotiation 1D.C280, 1G/100M Network loopback 1D.C500, 1G System loopback 1D.C501, 1G / 100M Test modes 1E.C470.4, Cable diagnostics 1E.C47A.F:B, Loopback Control 1E.C47A.4:2, Packet generation 6.11.86 Global Pin Status: Address 1E.C840 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description F Reserved Internal reserved - do not modify E Reserved Internal reserved - do not modify D DC_MASTER_ N Value of DC_MASTER_N pin: Type Default Note RO 0x1 = PHY Slave Daisy Chain Boot 0x0 = PHY Master Daisy Chain Boot from FLASH C:A Reserved Internal reserved - do not modify 9 Package Connectivity Value of the package connection pin 8 Reserved Internal reserved - do not modify 7 Tx Enable Current Value of Tx Enable pin 6 Reserved Internal reserved - do not modify LED Pullup State [5:0] 1 = LED output pin is pulled high 0 = LED output pin is pulled low 5:0 RO RO 0 = Disable Transmitter RO Table 6.1022 Global Pin Status: Address 1E.C840 6.11.87 Global Daisy Chain Status 2: Address 1E.C842 Bit Name F:0 Rx Daisy Chain Calculated CRC [F:0] Description Rx Daisy Chain Calculated CRC Type RO Default Note This is the calculated daisy chain CRC. Table 6.1023 Global Daisy Chain Status 2: Address 1E.C842 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.88 Global Fault Message: Address 1E.C850 Bit Name Description F:0 Message [F:0] Error code describing fault Type RO Default Note AQR405 Revision 0.11 - January 5, 2015 Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when firmware compiled for a different microprocessor core is loaded. Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to lock: this is not possible to trigger. Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this is not possible to trigger. Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the internal E-Fuse registers in not valid: this is not possible to trigger. Code 0x8006: Computed checksum does not match expected checksum. This occurs when the FLASH checksum check performed at boot time fails. This only occurs when the system boots from FLASH. Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static regions. Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts to execute an illegal instruction. To trigger this, write an illegal instruction to program memory. It's possible that the bit error check will trigger before the illegal instruction is executed. Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during instruction fetch: this is not possible to trigger. Code 0xC003 Load Store Error. Internal physical address or data error during load store operation: this is not possible to trigger.. Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without sufficient privilege: this is not possible to trigger. Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address which cannot be handled due to alignment: this is not possible to trigger. Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger. Code 0xC007 Data load from prohibited space: this is not possible to trigger. Code 0xC008 Data store into prohibited space: this is not possible to trigger. Table 6.1024 Global Fault Message: Address 1E.C850 603 6.11.89 Global Cable Diagnostic Impedance 1: Address 1E.C880 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:C B A:8 7 6:4 Name Description Type Reserved 1 Reserved RO Pair A Reflection #1 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 2 Reserved RO Pair A Reflection #2 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 3 Reserved RO Pair A Reflection #3 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Default Note The impedance of the first worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 1: Address 1E.C800" The impedance of the second worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 1: Address 1E.C800" The impedance of the third worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 1: Address 1E.C800" Table 6.1025 Global Cable Diagnostic Impedance 1: Address 1E.C880 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 3 2:0 Name Description Type Reserved 4 Reserved RO Pair A Reflection #4 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Default Note The impedance of the fourth worst reflection on Pair A. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 1: Address 1E.C800" Table 6.1025 Global Cable Diagnostic Impedance 1: Address 1E.C880 6.11.90 Global Cable Diagnostic Impedance 2: Address 1E.C881 AQR405 Revision 0.11 - January 5, 2015 Bit F E:C B A:8 Description Type Reserved 5 Reserved RO Pair B Reflection #1 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 6 Reserved RO Pair B Reflection #2 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 7 Reserved RO Default Note The impedance of the first worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 2: Address 1E.C801" The impedance of the second worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 2: Address 1E.C801" Table 6.1026 Global Cable Diagnostic Impedance 2: Address 1E.C881 605 7 Name Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name 6:4 Pair B Reflection #3 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 8 Reserved RO Pair B Reflection #4 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO 3 2:0 Description Type Default Note The impedance of the third worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 2: Address 1E.C801" The impedance of the fourth worst reflection on Pair B. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 2: Address 1E.C801" Table 6.1026 Global Cable Diagnostic Impedance 2: Address 1E.C881 6.11.91 Global Cable Diagnostic Impedance 3: Address 1E.C882 Bit F E:C B Name Description Type Reserved 9 Reserved RO Pair C Reflection #1 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 10 Reserved RO Default Note The impedance of the first worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 3: Address 1E.C802" Table 6.1027 Global Cable Diagnostic Impedance 3: Address 1E.C882 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name A:8 Pair C Reflection #2 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 11 Reserved RO Pair C Reflection #3 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 12 Reserved RO Pair C Reflection #4 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO 7 6:4 3 2:0 Description Type Default Note The impedance of the second worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 3: Address 1E.C802" The impedance of the third worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 3: Address 1E.C802" The impedance of the fourth worst reflection on Pair C. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 3: Address 1E.C802" Table 6.1027 Global Cable Diagnostic Impedance 3: Address 1E.C882 607 6.11.92 Global Cable Diagnostic Impedance 4: Address 1E.C883 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit F E:C B A:8 7 6:4 Name Description Type Reserved 13 Reserved RO Pair D Reflection #1 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 14 Reserved RO Pair D Reflection #2 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Reserved 15 Reserved RO Pair D Reflection #3 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Default Note The impedance of the first worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 4: Address 1E.C803" The impedance of the second worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 4: Address 1E.C803" The impedance of the third worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 4: Address 1E.C803" Table 6.1028 Global Cable Diagnostic Impedance 4: Address 1E.C883 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit 3 2:0 Name Description Type Reserved 16 Reserved RO Pair D Reflection #4 [2:0] 111 = Open Circuit (> 300) 110 = High Mismatch (> 115) 101 = Low Mismatch (< 85) 100 = Short Circuit (< 30) 0xx= No information available RO Default Note The impedance of the fourth worst reflection on Pair D. The corresponding length of this reflection from the PHY is given in "Global Cable Diagnostic Status 4: Address 1E.C803" Table 6.1028 Global Cable Diagnostic Impedance 4: Address 1E.C883 6.11.93 Global Status: Address 1E.C884 AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type F:8 Reserved Status 0 [7:0] Reserved RO 7:0 Cable Length [7:0] The estimated length of the cable in meters RO Default Note The length of the cable shown here is estimated from the cable diagnostic engine and should be accurate to +/-1m. Table 6.1029 Global Status: Address 1E.C884 609 6.11.94 Global Reserved Status 1: Address 1E.C885 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note F:A Nearly Seconds MSW[5:0] Bits 16 to 21 of the 22 bit "Nearly Seconds" uptime counter. RO 9:8 XENPAK NVR Status [1:0] Status of XENPAK NVR: 0: NVR not enabled 1: Last NVR operation succeeded 2: Last NVR operation failed 3: Reserved ROS PD 0x0 XENPAK register space is mirrored in NVR (SPI ROM). This register indicates the status of the last NVR operation. 7:4 Firmware Build ID [3:0] Firmware Build ID ROS PD 0x00 Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. 3:0 Provisioning ID [3:0] Provisioning ID ROS PD 0x00 Customers may receive multiple ROM images that differ only in their provisioning. This field is used to differentiate those images. This field is used in conjunction with the firmware major and minor revision numbers to uniquely identify ROM images. The "Nearly Seconds" counter is incremented every 1024 milliseconds. Table 6.1030 Global Reserved Status 1: Address 1E.C885 6.11.95 Global Reserved Status 2: Address 1E.C886 Bit Name F:0 Nearly Seconds LSW [F:0] Description Bits 0 to 15 of the 22 bit "Nearly Seconds" uptime counter Type RO Default Note The "Nearly Seconds" counter is incremented every 1024 milliseconds. Table 6.1031 Global Reserved Status 2: Address 1E.C886 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.96 Global Reserved Status 3: Address 1E.C887 Bit Name Description Type Default F DTE Status 1 = Need power 0 = Don't need power ROS 0 E Power Up Stall Status 1 = FW is stalled at power up 0 = Firmware is unstalled ROS 0 Reserved Status 3 [D:0] Reserved for future use RO D:0 Note Table 6.1032 Global Reserved Status 3: Address 1E.C887 AQR405 Revision 0.11 - January 5, 2015 611 6.11.97 Global Reserved Status 4: Address 1E.C888 Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default F:B Loopback Status [4:0] 0x00 = No loopback 0x01 = System Interface - System Loopback 0x02 = System Interface - System Loopback with Passthrough 0x03 = System Interface - Network Loopback 0x04 = System Interface - Network Loopback with Passthrough 0x05 = System Interface - Network Loopback with Passthrough and Merge 0x06 = System Interface - Peer-to-peer loopback 0x07 - 0x08 = Reserved 0x09 = Network Interface - System Loopback 0x0A = Network Interface - System Loopback with Passthrough 0x0B = Network Interface - Network Loopback 0x0C = Network Interface - Network Loopback with Passthrough 0x0D = Network Interface - Peer-to-peer loopback 0x0E - 0x0F = Reserved 0x10 = Cross-connect System Loopback 0x11 = Cross-connect Network Loopback 0x12 - 0x13 = Reserved 0x14 = Network Interface - System Loopback via Loopback Plug 0x15 - 0x1F = Reserved RO 0x00 A:6 Reserved Status 4 [4:0] Reserved for future use RO 0x00 Note These bits, in conjunction with the chip configuration and the rate (Bits 1:0), report the selected loopback. Table 6.1033 Global Reserved Status 4: Address 1E.C888 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 5 MDI Packet Generation Status 1 = CRPAT packet generation out MDI interface 0 = No CRPAT packet generation out MDI interface RO 0 Reports whether the CRPAT packet generator in the PHY outputs on the MDI interface at the selected rate. 4 Look-Aside Port Packet Generation Status 1 = CRPAT packet generation out 10G look-aside interface (KR0) 0 = No CRPAT packet generation out 10G look-aside interface (KR0) RO 0 Reports whether the CRPAT packet generator in the PHY outputs on the KR0 interface at the selected rate. 3 System I/F Packet Generation Status 1 = CRPAT packet generation out 10G system interface 0 = No CRPAT packet generation out 10G system interface RO 0 Reports whether the CRPAT packet generator in the PHY outputs on the selected system interface at the selected rate. Rate [2:0] 0x7 - 0x6 = reserved 0x5 = 5G 0x4 = 2.5G 0x3 = 10G 0x2 = 1G 0x1 = 100M 0x0 = invalid RO 0x0 These bits report the selected rate for the loopback and packet generation. 2:0 Table 6.1033 Global Reserved Status 4: Address 1E.C888 6.11.98 Global Alarms 1: Address 1E.CC00 Bit F Name Reserved Description Internal reserved - do not modify Type Default Note 0 613 Table 6.1034 Global Alarms 1: Address 1E.CC00 Bit Name Description Type Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 E High Temperature Failure 1 = High temperature failure threshold has been exceeded LH D Low Temperature Failure 1 = Low temperature failure threshold has been exceeded LH C High Temperature Warning 1 = High temperature warning threshold has been exceeded LH B Low Temperature Warning 1 = Low temperature warning threshold has been exceeded LH Reserved Internal reserved - do not modify 6 Reset completed 1 = Chip wide reset completed 5 Reserved Internal reserved - do not modify 4 Device Fault 3 A:7 Default Note These bits mirror the matching bit in 1.A070 and 1.A074. These bits are driven by Bits E:B in "Global General Status 1: Address 1E.C830" on page 598. LH This bit is set by the microprocessor when it has completed it's initialization sequence. This bit is mirrored in 1.CC02.0 1 = Fault LH When set, a fault has been detected by the uP and the associated 16 bit error code is visible in Global Fault Message: Address 1E.C850 Reserved Alarm A Reserved for future use LH 2 Reserved Alarm B Reserved for future use LH 1 Reserved Alarm C Reserved for future use LH 0 Reserved Alarm D Reserved for future use LH Table 6.1034 Global Alarms 1: Address 1E.CC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 6.11.99 Global Alarms 2: Address 1E.CC01 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F Reserved Internal reserved - do not modify E Smart Power-Down Entered 1 = Smart Power-Down State Entered LH D XENPAK Alarm 1 = XENPAK Alarm RO C IP Phone Detect 1 = IP Phone Detect LH Assertion of this bit means that the presence of an IP Phone has been detected. B DTE Status Change 1 = DTE status change LH Change in 1E.C887[F]. A:8 Reserved Alarms [2:0] Reserved LH 7 MDIO Command Handling Overflow 1 = PHY was issued more MDIO requests than it could service in it's request buffer LH Assertion of this bit means that more MDIO commands were issued than FW could handle. Reserved Internal reserved - do not modify Diagnostic Alarm 1 = Alarm triggered by a write to 1E.C470.7 LH A diagnostic alarm use to test system alarm circuitry. 6:1 0 When this bit is set, it indicates that the Smart Power-Down state was entered Table 6.1035 Global Alarms 2: Address 1E.CC01 615 6.11.100 Global Alarms 3: Address 1E.CC02 AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note F NVR Operation Complete 1 = NVR operation is complete LH NVR interface is ready interrupt for registers Global NVR Interface 1: Address 1E.100 Global NVR Interface 5: Address 1E.104. E Mailbox Operation: Complete 1 = Mailbox operation is complete LH Mailbox interface is ready interrupt for registers Global Mailbox Interface 1: Address 1E.200 - Global Mailbox Interface 5: Address 1E.204 Reserved Internal reserved - do not modify A uP DRAM Parity Error 1 = Parity error detected in the uP DRAM LH 9:8 uP IRAM Parity Error [1:0] 1 = Parity error detected in the uP IRAM LH 7:6 Reserved Internal reserved - do not modify Tx Enable State Change 1 = TX_EN pin has changed state Reserved Internal reserved - do not modify 2 MDIO MMD Error 1 = Invalid MMD address detected LH 1 MDIO Timeout Error 1 = MDIO timeout detected LH 0 Watchdog Timer Alarm 1 = Watchdog timer alarm LH D:B 5 4:3 Bit 0 indicates a parity error was detected in the uP IRAM but was corrected. Bit 1 indicates a multiple parity errors were detected in the uP IRAM and could not be corrected. The uP IRAM is protected with ECC. LRF Table 6.1036 Global Alarms 3: Address 1E.CC02 6.11.101 Global Interrupt Mask 1: Address 1E.D400 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Typ e Default AQR405 Revision 0.11 - January 5, 2015 F Reserved Internal reserved - do not modify E High Temperature Failure Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 D Low Temperature Failure Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 C High Temperature Warning Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 B Low Temperature Warning Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify 6 Reset completed Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 5 Reserved Internal reserved - do not modify 4 Device Fault Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 3 Reserved Alarm A Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 2 Reserved Alarm B Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 A:7 Note Table 6.1037 Global Interrupt Mask 1: Address 1E.D400 617 Bit Name Description Typ e Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 Reserved Alarm C Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 Reserved Alarm D Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Note Table 6.1037 Global Interrupt Mask 1: Address 1E.D400 6.11.102 Global Interrupt Mask 2: Address 1E.D401 Bit Name Description Type Default F Reserved Internal reserved - do not modify E Smart Power-Down Entered Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 D XENPAK Alarm Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 C IP Phone Detect Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 B DTE Status Change Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 A:8 Reserved Alarms Mask [2:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 7 MDIO Command Handling Overflow Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.1038 Global Interrupt Mask 2: Address 1E.D401 Note Bit 6:1 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential 0 Name Description Reserved Internal reserved - do not modify Diagnostic Alarm Mask 1 = Enable interrupt generation 0 = Disable interrupt generation Type Default R/W PD 0 Note Table 6.1038 Global Interrupt Mask 2: Address 1E.D401 6.11.103 Global Interrupt Mask 3: Address 1E.D402 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F NVR Operation Complete Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 NVR interface is ready interrupt for registers Global NVR Interface 1: Address 1E.100 Global NVR Interface 5: Address 1E.104 E Mailbox Operation Complete Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Mailbox interface is ready interrupt for registers Global Mailbox Interface 1: Address 1E.200 - Global Mailbox Interface 5: Address 1E.204 Reserved Internal reserved - do not modify A uP DRAM Parity Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 9:8 uP IRAM Parity Error Mask [1:0] 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0x0 7:6 Reserved Internal reserved - do not modify Tx Enable State Change Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify D:B 5 4:3 619 Table 6.1039 Global Interrupt Mask 3: Address 1E.D402 Bit Name Description Type Default AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 2 MDIO MMD Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 MDIO Timeout Error Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 Watchdog Timer Alarm Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 1 Note Table 6.1039 Global Interrupt Mask 3: Address 1E.D402 6.11.104 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 Bit Name Description Type Default Note F PMA Standard Alarm 1 Interrupt 1 = Interrupt in PMA standard alarms 1 RO An interrupt was generated from bit 1.1.2. An interrupt was generated from status register (See "PMA Standard Status 1: Address 1.1" on page 94.) and the corresponding mask register. (See "PMA Transmit Standard Interrupt Mask 1: Address 1.D000" on page 220.) E PMA Standard Alarm 2 Interrupt 1 = Interrupt in PMA standard alarms 2 RO An interrupt was generated from either bit 1.8.B or 1.8.A. An interrupt was generated from status register (See "PMA Standard Status 2: Address 1.8" on page 99.) and the corresponding mask register. (See "PMA Transmit Standard Interrupt Mask 2: Address 1.D001" on page 221.) Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 Bit Name Description Type Default Note D PCS Standard Alarm 1 Interrupt 1 = Interrupt in PCS standard alarms 1 RO An interrupt was generated from status register (See "PCS Standard Status 1: Address 3.1" on page 229.) and the corresponding mask register. (See "PCS Standard Interrupt Mask 1: Address 3.D000" on page 294.) C PCS Standard Alarm 2 Interrupt 1 = Interrupt in PCS standard alarms 2 RO An interrupt was generated from status register (See "PCS Standard Status 2: Address 3.8" on page 233.) and the corresponding mask register. (See "PCS Standard Interrupt Mask 2: Address 3.D001" on page 295.) B PCS Standard Alarm 3 Interrupt 1 = Interrupt in PCS standard alarms 3 RO An interrupt was generated from status register (See "PCS 10G Status 2: Address 3.21" on page 237.) and the corresponding mask register. (See "PCS Standard Interrupt Mask 3: Address 3.D002" on page 296.) A PHY XS Standard Alarms 1 Interrupt 1 = Interrupt in PHY XS standard alarms 1 RO An interrupt was generated from the status register (See "PHY XS Standard Status 1: Address 4.1" on page 382.) and the corresponding mask register. (See "PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000" on page 409.) 9 PHY XS Standard Alarms 2 Interrupt 1 = Interrupt in PHY XS standard alarms 2 RO An interrupt was generated from the status register (See "PHY XS Standard Status 2: Address 4.8" on page 386.) and the corresponding mask register. (See "PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001" on page 410.) Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 621 Bit Name Description Type Default Note Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 8 Autonegotiation Standard Alarms 1 Interrupt 1 = Interrupt in Autonegotiation standard alarms 1 RO An interrupt was generated from status register (See "Autonegotiation Standard Status 1: Address 7.1" on page 434.) and the corresponding mask register. (See "Autonegotiation Standard Interrupt Mask 1: Address 7.D000" on page 478.) 7 Autonegotiation Standard Alarms 2 Interrupt 1 = Interrupt in Autonegotiation standard alarms 2 RO An interrupt was generated from status register (See "Autonegotiation 10GBASE-T Status Register: Address 7.21" on page 446.) and the corresponding mask register. (See "Autonegotiation Standard Interrupt Mask 2: Address 7.D001" on page 479.) 6 GbE Standard Alarms Interrupt 1 = Interrupt in GbE standard alarms RO An interrupt was generated from the TGE core. Reserved Internal reserved - do not modify All Vendor Alarms Interrupt 1 = Interrupt in all vendor alarms RO An interrupt was generated from status register (See "Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01" on page 623.) and the corresponding mask register. (See "Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01" on page 625.) 5:1 0 Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 6.11.105 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 F PMA Vendor Alarm Interrupt 1 = Interrupt in PMA vendor specific alarm RO A PMA alarm was generated. (See "PMA Vendor Global Interrupt Flags 1: Address 1.FC00" on page 224.) E PCS Vendor Alarm Interrupt 1 = Interrupt in PCS vendor specific alarm RO A PCS alarm was generated. (See "PCS Vendor Global Interrupt Flags 1: Address 3.FC00" on page 378.) D PHY XS Vendor Alarm Interrupt 1 = Interrupt in PHY XS vendor specific alarm RO A PHY XS alarm was generated. (See "PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00" on page 431.) C Autonegotiation Vendor Alarm Interrupt 1 = Interrupt in Autonegotiation vendor specific alarm RO An Autonegotiation alarm was generated. (See "Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00" on page 488.) B GbE Vendor Alarm Interrupt 1 = Interrupt in GbE vendor specific alarm RO A GbE alarm was generated. (See "GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00" on page 547.) Reserved Internal reserved - do not modify Global Alarms 1 Interrupt 1 = Interrupt in Global alarms 1 RO An interrupt was generated from status register (See "Global Alarms 1: Address 1E.CC00" on page 613.) and the corresponding mask register. (See "Global Interrupt Mask 1: Address 1E.D400" on page 617.) A:3 2 Table 6.1041 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 623 Bit Name Description Type Default Note AQR405 Revision 0.11 - January 5, 2015 Aquantia Corp. - Strictly Confidential 1 Global Alarms 2 Interrupt 1 = Interrupt in Global alarms 2 RO An interrupt was generated from status register (See "Global Alarms 2: Address 1E.CC01" on page 615.) and the corresponding mask register. (See "Global Interrupt Mask 2: Address 1E.D401" on page 618.) 0 Global Alarms 3 Interrupt 1 = Interrupt in Global alarms 3 RO An interrupt was generated from status register (See "Global Alarms 3: Address 1E.CC02" on page 616.) and the corresponding mask register. (See "Global Interrupt Mask 3: Address 1E.D402" on page 619.) Table 6.1041 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 6.11.106 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 Bit Name Description Type Default F PMA Standard Alarm 1 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 E PMA Standard Alarm 2 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 D PCS Standard Alarm 1 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 C PCS Standard Alarm 2 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 B PCS Standard Alarm 3 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.1042 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 Note Bit Name Description Type Default Use pursuant to Company instructions Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 A PHY XS Standard Alarms 1 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 9 PHY XS Standard Alarms 2 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 8 Autonegotiation Standard Alarms 1 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 7 Autonegotiation Standard Alarms 2 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 6 Gbe Standard Alarms Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify All Vendor Alarms Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 1 5:1 0 Note Table 6.1042 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 6.11.107 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01 Bit Name Description Type Default PMA Vendor Alarm Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 E PCS Vendor Alarm Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 D PHY XS Vendor Alarm Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Table 6.1043 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01 625 F Note Bit Name Description Type Default Aquantia Corp. - Strictly Confidential AQR405 Revision 0.11 - January 5, 2015 C Autonegotiation Vendor Alarm Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 B GbE Vendor Alarm Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 Reserved Internal reserved - do not modify 2 Global Alarms 1 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 1 Global Alarms 2 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 0 0 Global Alarms 3 Interrupt Mask 1 = Enable interrupt generation 0 = Disable interrupt generation R/W PD 1 A:3 Table 6.1043 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01 Note References: "XENPAK 10 Gigabit Ethernet MSA", XENPAK MSA Rev. 3.0, Issue 3.0, September 18, 2002. [2] "X2 MSA Specification", X2 MSA Issue 2.0b, April 7, 2005. [3] "Part 3: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications", 802.3 - 2008, IEEE Computer Society, The Institute of Electrical and Electronics Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, December 26, 2008. [4] "Fibre Channel 10 Gigabit (10GFC) Rev. 4.0", INCITS 364-2002 T11/Project 1413-D/Rev 4.0, INCITS working draft proposed American National Standard for Information Technology, April 1, 2004. [5] "The Test Access Port and Boundary-Scan Architecture", IEEE STD-1149.1 -2001, IEEE Standards Office, The Institute of Electrical and Electronics Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, October 25, 2001. [6] "The Test Access Port and Boundary-Scan Architecture", IEEE STD-1149.6 -2003, IEEE Standards Office, The Institute of Electrical and Electronics Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, April 17, 2003. [7] "Media Access Control (MAC) Security", IEEE STD-802.AE-2006, IEEE Standards Office, The Institute of Electrical and Electronics Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, April 17, 2003. [8] "Doxygen", http://www.stack.nl/~dimitri/doxygen, Dimitri van Heesch, November 2006. Co nfi d Str ict ly [9] en tia l [1] "Microsoft Network Device Class Specification", http://www.microsoft.com/whdc/resources/respec/specs/pmref/PMnetwork.ms px, Version 2.0 October 12, 2000. [10] "Serial-GMII Specification Version 1.8", Document ENG-46158, Cisco Systems, April 27, 2005. [11] "Information Technology - Generic cabling for customer premises", ISO/IEC 11801, Second edition 2002-09. [12] "API", Aquantia Corporation. [13] "Hardware Design Guide", Aquantia Corporation. 627 Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 en tia l Co nfi d Str ict ly Aquantia Corp. - Strictly Confidential Use pursuant to Company instructions AQR405 Revision 0.11 - January 5, 2015 AQR405 10GBASE-T Ethernet PHY Transceiver Str i ctl yC on fid e nti al Data Sheet January 2015 For additional information, contact your Aquantia Account Manager or the following: INTERNET: Home: http://www.aquantia.com E-MAIL: sales@aquantia.com ADDRESS: Aquantia Corp., 700 Tasman Drive, Milpitas, CA 95035 408-228-8300, FAX 408-228-1190 PROPRIETARY AND CONFIDENTIAL: All of the information included herein, as well as any oral or written discussions regarding such information and any materials generated as a result of such discussions, is confidential information that is proprietary to Aquantia Corporation and should be used by its recipient solely as authorized by Aquantia Corporation under written non-disclosure agreement. Aquantia Corp. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Aquantia is a registered trademark of Aquantia Corp. Aquantia and the Aquantia logo are trademarks of Aquantia Corp. Consult the current Release Notes for the AQR405 to obtain a list of all currently known issues and errata associated with the AQR405. Copyright (c) 2015 Aquantia Corp. All Rights Reserved Strictly Confidential AQR405 Revision 0.11 - January 5, 2015