AQN-107-104-SFA - Aquantia Corp.

Strictly Confidential

Preliminary Datasheet

January 2015

AQR405

10GBASE-T Ethernet PHY Transceiver

AQR405 Revision 0.11 - January 5, 2015

Strictly Confidential

General Description

The AQR405 is a complete quad port low-power, full-reach, AQRate™, five-speed 10GBASE-T /

5G / 2.5G / 1000BASE-T / 100BASE-TX PHY transceiver. The device performs all the physical

layer functions required to implement AQRate™ and 10GBASE-T / 1000BASE-T / 100BASE-TX

transmission over 100+m of twisted pair cabling.

Features Benefits

•High-Density 25mm Quad, Pin + Software Compatible with AQ1402 •Allows seamless upgrade of existing designs to the latest

low-power technology

•Full-spec 10GBASE-T performance

o100m on Augmented Cat 6 (Cat 6A) and Cat 7

o55m on Cat 6 and best-effort on Cat 5e

•Ability to support worst case channels while reducing power and

latency when channel characteristics permit

•AQRate™ Adaptive Rate Operation

oStandard 130m 1000Base-T and 100Base-TX operation

•Super-speed (5G and 2.5G) operation over legacy infrastructure,

plus full inter-operability with existing equipment

•2.9 W full-reach typical operating power per port

o2.4 W short-reach (IEEE 30m mode) typical operating power

o1.9 W data-center (10m) mode typical operating power

•Enables high-density 10GBASE-T switching applications

•Integrated MACsec, 1588, and EEE support

oFull support for AES-256 and stand-alone operation

•Enables refresh of legacy switches without spinning ASICs

•Integrated Wake-On-LAN Support

oCompliant to Microsoft Network Device Class specification

•Integrated packet filtering allows sub-1W support in 100BASE-TX

mode

•Built-in thermal management capabilities

oOn-die thermal sensor with alarm and warning thresholds

•Enables deployment in thermally constrained environments

•25 x 25 mm flip-chip 576-ball BGA package

o1mm ball pitch

oLow thermal resistance ( )

•Low cost

•Flexible heat-sinking

•Compatible with volume PCB manufacturing

•IEEE ® 802.3an-2008 compliant autonegotiation •Interoperability with existing Ethernet infrastructure

•External SPI FLASH interface with optional FLASH-less operation

oAt-manufacture FLASH burn capability

oDaisy-chain mode allows a single FLASH for multiple devices

•Reduces BOM cost as one or no FLASH devices required

•Enables firmware download/upgrade and FLASH image loading

during manufacturing

•50 MHz Differential Clock Operation

oIntegrated ultra-low phase noise synthesizer

•Outputs primary and secondary 50 MHz received reference for

synchronous Ethernet

•Advanced Cable Diagnostics

oOn-chip high-resolution cable analyzer

•Enables the deployment of meaningful cable analysis tools for

debugging installation problems

•High-Performance full KR (with autonegotiation) / XFI / USXGMII /

RXAUI / 2500BASE-X / SGMII I/F w/ AC-JTAG

o2nd KR / SGMII interface for optical dual-media capability

•Ensures trouble-free operation over a range of interconnect

scenarios

•Advance Loopback and Diagnostic Capability

oFlexible on-chip BERT

oSupports numerous loopbacks

oFull 1 second packet counters and CRC-32 checkers

•Enables extensive system test and debug with remote loopback

control

•Integrated MDI Filter and Advanced RFI Cancellation

oEliminates external filter components

•Patented RFI technology provides error-free performance in the

presence of RF interference

θjc

Strictly Confidential

ii Aquantia Corp.

Preliminary Datasheet

January 2015

10GBASE-T Ethernet PHY Transceiver

AQR405

AQR405 Revision 0.11 - January 5, 2015

Strictly Confidential

Detailed Description

A block diagram of the AQR405 is shown in Figure 1. Each port utilizes a common analog front-end for all 5 modes

of operation, and a common system interface (configurable as dual KR, RXAUI in 10G, 2500BASE-X in 2.5G, and

dual SGMII in 1G / 100M, or all rates via USXGMII)†. In the transmit direction in 10G, 5G, and 2.5G modes, data

from the system interface is equalized and received. This data is then mapped into a virtual internal XGMII

interface where blocks of two XGMII frames (32 bits of data + 4 bits of control) are encoded into a single 65B block,

using the 64B/65B encoding scheme specified in Clause 55. In 10G mode, fifty of these 65B blocks are aggregated

together, along with a prepended auxiliary bit, and an appended CRC-8 to form the 3259-bit 10GBASE-T

transmission frame payload. This payload is encoded using a combination of LDPC encoding and coset

partitioning, with the LDPC encoding adding an additional 325 systematic check bits to produce a 3584-bit

10GBASE-T transmission frame. The coset partitioning effectively divides the frame up into 512 7-bit symbols,

where the upper 3 bits are uncoded and describe the coset, while the lower 4 bits are coded and identify an

element within the coset. These 8 cosets are then mapped onto a 128-DSQ constellation (a 16 x 16 checkerboard

pattern) which is physically encoded as two back-to-back PAM-16 symbols. These symbols are then THP

precoded, filtered, and sent out over the four twisted pairs in the cable. AQRate 5G transmission is done in a

similar fashion, but uses a fully LDPC encoded 320 ns PAM-16 frame containing twenty-five 65B blocks. AQRate

2.5G transmission is also similar, but uses a 640 ns frame containing twenty-five 65B blocks.

In the receive direction in 10G, 5G, and 2.5G modes, PAM-16 coded symbols enter the AQR405 from the line

interface and pass through the hybrid, which provides transmit / receive isolation. These symbols are then filtered

and amplified prior to being sampled by four high-speed, high-precision A/D converters. The outputs of these A/D

converters are then passed through an extensive set of adaptive equalizers which provide both cross-talk and echo

cancellation. After timing is recovered, the data from the four channels is aligned and merged together to form the

Figure 1 AQR405 block diagram

†. The line facing (Lookaside/Dual Media mode) SERDES lanes are shown in grey. The inactive PCS block items (i.e. XAUI) are shown in grey.

RST_OUT_N

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

Hybrid

COMMON

MDIO

Management

P[3:0]_MDC

P[3:0]_MDIO

P[3:0]_INT_N

P[3:0]_[D:A]_P,N

MDIO

Power

Supply

VDD

P[3:0]_VA22

VA12

AVSS/VSS

Power

LED I/F P[3:0]_LED[2:0]

LED

LINE

RST_N JTAG

TDI

TDO

TCK

TMS

JTAG

TRST_N

RREF_BG[3:0]

Band-

gap

ADDR[4:2]

Timing

RAM

MDIO

Registers

Config

VDD_SENSE

Autonegotiation

P[3:0]_WAKE

SMB_CLK

SMB_DAT

P[3:0]_PRST*

AQRate 25mm Quad

THP

Precoder

THP

Precoder

THP

Precoder

DAC /

Driver

A/D

THP

Precoder

THP

Precoder

A/D

VGA &

Filter

THP

Precoder

THP

Precoder

VGA &

Filter

DSP

TDIO_P[3,0]

Thermal

Diodes

TDIO_N[3,0]

P[3:0]_CM_P,N

SMBus

WoL

PController

Control

DC_MASTER_N

SCLK

SIN

SOUT

CE_N

Serial

FLASH

I/F

RX_DC_CLK

RX_DC_DATA

RX_DC_SOF

RX_DC_RST_N

TX_DC_CLK

TX_DC_DATA

TX_DC_SOF

TX_DC_RST_N

Daisy-Chain

I/F

FLASH / Daisy Chain

Boot Loader

REPLICATED FOUR TIMES

SRDS0

10G

SRDS2

10G

SERDES

INV_ADDR[1:0]

CLKO_50M_A,B

Timing

50 MHz

CLK_P

CLK_N

CLK_1588_P,N

1588_SYNC

System I/F

P[3:0]_TX_LN0_P,N

P[3:0]_RX_LN0_P,N

P[3:0]_TX_LN2_P,N

P[3:0]_RX_LN2_P,N

Lookaside

MACSEC

5G PCS

1G PCS

100M PCS

KR/USXGMII

PCS 1

SGMII

PCS 1

SGMII

PCS 0

KR/USXGMII

PCS 0

10G PCS

2.5G PCS

XAUI/RXAUI

PCS

AQR405Strictly

Aquantia Corp. iii

Preliminary Datasheet

January 2015 10GBASE-T Ethernet PHY Transceiver

AQR405

AQR405 Revision 0.11 - January 5, 2015

Strictly Confidential

original, but noisy transmission frames. In all three modes, the data is decoded using an LDPC decoder. However,

in 10G mode the data is further sliced using knowledge of the coset partitioning and 128-DSQ mapping to produce

the original 10GBASE-T transmission frame payload. The CRC-8 over this payload is then checked to ensure

integrity of the uncoded bits. Finally, in all schemes, the auxiliary bit is stripped, the 65B blocks remapped into

XGMII blocks, and the received Ethernet data transmitted out the MAC interface.

When operating in 1G or 100M modes, receive data from the analog front-end is routed to either the 1G or 100M

PCS where timing is recovered and equalization performed. In 1G mode, Viterbi decoding is also done. From here,

the data passes across a virtual GMII interface to the system interface which is either SGMII, or USXGMII mode on

logical Lane 0. In the transmit direction, 1G or 100M data is received on either the SGMII, or USXGMII interface,

passed through the 1G or 100M PCS and then transmitted by the common analog front-end.

Figure 2 shows a typical system-level block diagram of a 10GBASE-T channel with an optional dual-media

interface built using the AQR405. On the line side of the AQR405, a robust interface providing good

common-mode rejection and electrical protection against cable discharge is implemented. On the MAC side, the

AQR405 provides a robust SERDES interface with configurable pre-emphasis and receive equalization. For test

coverage, this interface also incorporates AC JTAG.

Control over the chip is done via an external C-language application program interface (API) which provides an

easy-to-use abstraction of the AQR405, and via an MDIO interface which provides the standard Clause 45 register

set for control of 10GBASE-T devices. On-chip, the AQR405 contains a 32-bit microcontroller which manages the

state machines and operation of the various elements within the chip. Consequently, there is a great deal of

flexibility afforded to the end user because of the presence of this microcontroller, and as such the AQR405 offers

a high degree of control and flexibility. The image for the microcontroller is stored either in an optional external SPI

FLASH (which can be daisy-chained over multiple devices), or loaded at boot time via the MDIO interface (MDIO

boot-load). This interface also provides the user the capability of directly programming the FLASH during

manufacturing.

In addition to the Ethernet interfaces, the AQR405 provides three 20 mA LED outputs per port which are

configurable via software to respond to a variety of conditions such as link activity and connection status. Clocking

for the AQR405 is provided from a 50 MHz differential clock.

Power for the AQR405 is provided from three supply voltages, with configurable I/O voltage levels. In order to

assist the system designer in deploying the AQR405, a reference design (part numbers, schematics, and layout) is

provided which is optimized for performance, efficiency and cost.

Figure 2 AQR405 system block interconnect

MAC I/F

Line XFMR

Serial

FLASH

SPI

RJ-45

Power

Supply

MDIO & Control

MAC Line

SFP+

Line

Common

FLASH Dai sy

Chain

PHY Slice

Strictly Confidential

AQR405 Revision 0.11 - January 5, 2015

Preliminary Datasheet

January 2015

10GBASE-T Ethernet PHY Transceiver

AQR405

PROPRIETARY AND CONFIDENTIAL: All of the information included herein, as well as any oral or written discussions regarding such information and any materials generated as a result of

such discussions, is confidential information that is proprietary to Aquantia Corporation and should be used by its recipient solely as authorized by Aquantia Corporation under written non-dis-

closure agreement.

Aquantia Corp. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Aquantia is a

registered trademark of Aquantia Corp. Aquantia and the Aquantia logo are trademarks of Aquantia Corp. Consult the current Release Notes for the AQR405 to obtain a list of all currently

known issues and errata associated with the AQR405.

For additional information, contact your Aquantia Account Manager or the following:

INTERNET: Home: http://www.aquantia.com

E-MAIL: sales@aquantia.com

ADDRESS: Aquantia Corp., 700 Tasman Drive, Milpitas, CA 95035

408-228-8300, FAX 408-228-1190

IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.

Package Information

The AQR405 is packaged in a 25 x 25 mm flip-chip BGA with 576 balls (24 rows x 24 columns). The

package is marked as follows: Release Notes

The AQR405 Release Notes must be consulted for a full list of known issues and errata associated with

AQR405.

Ordering Information

Figure 3 Part marking

Part Number Description Ordering Part Number

AQR405 Silicon Rev. B1 10GBASE-T PHY RoHS 6/6 Matte Tin Balls1

1. Lead-free bump and lead-free BGA balls

AQR405-B1-EG-Y

Strictly Confidential

Table of Contents

Section Page

AQR405 Revision 0.11 - January 5, 2015

Strictly Confidential

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Deployment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Power-on Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SERDES Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Power-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Cable Diagnostics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Wake-On-LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Debug and Diagnostics Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

API & Programming Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MACsec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ingress Lookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

MACsec Ingress Post-Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Egress Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

MACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Precision Time Protocol (PTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2 Hardware Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

SPI FLASH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Daisy-chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Boot-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Provisionable Default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Gang-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

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SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SERDES Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SERDES System I/F Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

10G Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1000BASE-X Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

XSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

USXGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

All-Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

XSGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

USXGMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

MDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Reference Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Metrology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Wake-On-LAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

MDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SPI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Daisy-chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

RXAUI Transmit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

RXAUI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SGMII Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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SGMII Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

KR Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

KR Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2500BASE-X Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2500BASE-X Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Full-Reach Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Full-Reach VA22 and VA12 Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Full-Reach VDD Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Other Power Supplies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

VDD_IO and VDD_FLASH Supply Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Serial FLASH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Line (MDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Reference Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Input Clock Pins CLK_P and CLK_N - LVDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Input Clock Pins CLK_1588_P and CLK_1588_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Reference Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

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Theta J’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Format and Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Registers and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

PMA Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PMA Standard Control 1: Address 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PMA Standard Status 1: Address 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

PMA Standard Device Identifier 1: Address 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PMA Standard Device Identifier 2: Address 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PMA Standard Speed Ability: Address 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

PMA Standard Devices in Package 1: Address 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

PMA Standard Devices in Package 2: Address 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

PMA Standard Control 2: Address 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

PMA Standard Status 2: Address 1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PMD Standard Transmit Disable Control: Address 1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PMD Standard Signal Detect: Address 1.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PMD Standard 10G Extended Ability Register: Address 1.B . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PMA Standard Package Identifier 1: Address 1.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

PMA Standard Package Identifier 2: Address 1.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMA 10GBASE-T Status: Address 1.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 . . . . . . . . . . . . . . . . . . . . . . . . 104

PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 . . . . . . . . . . . . . 105

PMA 10GBASE-T Test Modes: Address 1.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85 . . . . . . . . . . . . . . . . . . . . 107

PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86 . . . . . . . . . . . . . . . . . . . . 107

PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 . . . . . . . . . . . . . . . . . . . . 108

PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 . . . . . . . . . . . . . . . . . . . . 108

PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 . . . . . . . . . . . . . 109

PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A . . . . . . . . . . . . 109

PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B . . . . . . . . . . . . 110

PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C . . . . . . . . . . . . 110

PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 . . . . . . . . . . . . . . . . . . . . . 112

PMA 10GBASE-T Skew Delay 1: Address 1.91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

PMA 10GBASE-T Skew Delay 2: Address 1.92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PMA 10GBASE-T Fast Retrain Status and Control: Address 1.93 . . . . . . . . . . . . . . . . . . . . . . 114

TimeSync PMA Capability: Address 1.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 . . . . . . . . . . . . . . . . . . . . . . . . . 116

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TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 . . . . . . . . . . . . . . . . . . . . . . . . . 116

TimeSync PMA Receive Path Data Delay 1: Address 1.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . 116

TimeSync PMA Receive Path Data Delay 2: Address 1.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TimeSync PMA Receive Path Data Delay 3: Address 1.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TimeSync PMA Receive Path Data Delay 4: Address 1.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . 117

XENPAK Control: Address 1.8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 . . . . . . . . . . . . . . . . . . 119

XENPAK Header - NVR Size 1: Address 1.8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

XENPAK Header - NVR Size 2: Address 1.8009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

XENPAK Header - Memory Used 1: Address 1.800A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Memory Used 2: Address 1.800B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Basic Memory Start Address: Address 1.800C . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Customer Memory Offset: Address 1.800D . . . . . . . . . . . . . . . . . . . . . . . . . 121

XENPAK Header - Vendor Memory Start Address: Address 1.800E . . . . . . . . . . . . . . . . . . . . . 121

XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F . . . . . . . . . . . . . . . . . 121

XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Reserved 0x11: Address 1.8011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Transceiver Type: Address 1.8012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Connector Type: Address 1.8013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

XENPAK Basic - Encoding: Address 1.8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

XENPAK Basic - Bit Rate 0: Address 1.8015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Bit Rate 1: Address 1.8016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Protocol: Address 1.8017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Standards Compliance Codes: Address 1.8018 . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 1: Address 1.8019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 2: Address 1.801A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 3: Address 1.801B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 4: Address 1.801C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 5: Address 1.801D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 6: Address 1.801E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 7: Address 1.801F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 8: Address 1.8020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 9: Address 1.8021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 10: Address 1.8022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 11: Address 1.8023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 12: Address 1.8024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 13: Address 1.8025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 14: Address 1.8026 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 15: Address 1.8027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 16: Address 1.8028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 17: Address 1.8029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 18: Address 1.802A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 19: Address 1.802B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 20: Address 1.802C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 21: Address 1.802D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 22: Address 1.802E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 23: Address 1.802F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 24: Address 1.8030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Reserved 0x19 25: Address 1.8031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 1: Address 1.8032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 2: Address 1.8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 3: Address 1.8034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

XENPAK Basic - Package Identifier 4: Address 1.8035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

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XENPAK Basic - Vendor Identifier 1: Address 1.8036 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

XENPAK Basic - Vendor Identifier 2: Address 1.8037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Identifier 3: Address 1.8038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Identifier 4: Address 1.8039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Name 1: Address 1.803A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Name 2: Address 1.803B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

XENPAK Basic - Vendor Name 3: Address 1.803C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

XENPAK Basic - Vendor Name 4: Address 1.803D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

XENPAK Basic - Vendor Name 5: Address 1.803E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 6: Address 1.803F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 7: Address 1.8040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 8: Address 1.8041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 9: Address 1.8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 10: Address 1.8043 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 11: Address 1.8044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 12: Address 1.8045 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 13: Address 1.8046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 14: Address 1.8047 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Name 15: Address 1.8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Name 16: Address 1.8049 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Part Number 1: Address 1.804A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 2: Address 1.804B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 3: Address 1.804C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 4: Address 1.804D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 5: Address 1.804E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 6: Address 1.804F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 7: Address 1.8050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 8: Address 1.8051 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 9: Address 1.8052 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 10: Address 1.8053 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 11: Address 1.8054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 12: Address 1.8055 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 13: Address 1.8056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 14: Address 1.8057 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 15: Address 1.8058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 16: Address 1.8059 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Serial Number 1: Address 1.805C . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 2: Address 1.805D . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 3: Address 1.805E . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 4: Address 1.805F . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 5: Address 1.8060 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 6: Address 1.8061 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 7: Address 1.8062 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 8: Address 1.8063 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 9: Address 1.8064 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 10: Address 1.8065 . . . . . . . . . . . . . . . . . . . . . . . . . . 150

XENPAK Basic - Vendor Serial Number 11: Address 1.8066 . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

XENPAK Basic - Vendor Serial Number 12: Address 1.8067 . . . . . . . . . . . . . . . . . . . . . . . . . . 150

XENPAK Basic - Vendor Serial Number 13: Address 1.8068 . . . . . . . . . . . . . . . . . . . . . . . . . . 151

XENPAK Basic - Vendor Serial Number 14: Address 1.8069 . . . . . . . . . . . . . . . . . . . . . . . . . . 151

XENPAK Basic - Vendor Serial Number 15: Address 1.806A . . . . . . . . . . . . . . . . . . . . . . . . . . 151

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XENPAK Basic - Vendor Serial Number 16: Address 1.806B . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 1: Address 1.806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 2: Address 1.806D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 3: Address 1.806E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 4: Address 1.806F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 5: Address 1.8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 6: Address 1.8071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 7: Address 1.8072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 8: Address 1.8073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 9: Address 1.8074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 10: Address 1.8075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

XENPAK Basic - 5V Loading: Address 1.8076 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

XENPAK Basic - 3.3V Loading: Address 1.8077 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

XENPAK Basic - APS Loading: Address 1.8078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

XENPAK Basic - APS Voltage: Address 1.8079 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

XENPAK Basic - DOM Capability: Address 1.807A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

XENPAK Basic - Low-Power Startup Capability: Address 1.807B . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Basic - Reserved 0x7C: Address 1.807C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Basic - Checksum: Address 1.807D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Customer - Reserved 0x7E 1: Address 1.807E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 2: Address 1.807F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 3: Address 1.8080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 4: Address 1.8081 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 5: Address 1.8082 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 6: Address 1.8083 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 7: Address 1.8084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 8: Address 1.8085 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 9: Address 1.8086 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 10: Address 1.8087 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 11: Address 1.8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 12: Address 1.8089 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 13: Address 1.808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 14: Address 1.808B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 15: Address 1.808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 16: Address 1.808D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

XENPAK Customer - Reserved 0x7E 17: Address 1.808E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

XENPAK Customer - Reserved 0x7E 18: Address 1.808F . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

XENPAK Customer - Reserved 0x7E 19: Address 1.8090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 20: Address 1.8091 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 21: Address 1.8092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 22: Address 1.8093 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 23: Address 1.8094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 24: Address 1.8095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 25: Address 1.8096 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 26: Address 1.8097 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 27: Address 1.8098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 28: Address 1.8099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 29: Address 1.809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 30: Address 1.809B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 31: Address 1.809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 32: Address 1.809D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 33: Address 1.809E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 34: Address 1.809F . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

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XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 45: Address 1.80AA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 46: Address 1.80AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Customer - Reserved 0x7E 47: Address 1.80AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Customer - Reserved 0x7E 48: Address 1.80AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 19: Address 1.80C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 20: Address 1.80C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 21: Address 1.80C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

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XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Rx_Alarm - Control: Address 1.9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Tx_Alarm - Control: Address 1.9001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

XENPAK LASI - Control: Address 1.9002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

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XENPAK Rx_Alarm - Status: Address 1.9003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

XENPAK Tx_Alarm - Status: Address 1.9004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

XENPAK LASI - Status: Address 1.9005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

XENPAK DOM - Tx Control: Address 1.9006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 . . . . . . . . . . . . . . 210

XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 . . . . . . . . . . . . . . 211

XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002 . . . . . . . . . . . . . . . 211

XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 . . . . . . . . . . . . . . 212

XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 . . . . . . . . . . . . 212

XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 . . . . . . . . . . . . 213

XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006 . . . . . . . . . . . . . 213

XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 . . . . . . . . . . . . 214

XENPAK DOM - Temperature LSW: Address 1.A060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

XENPAK DOM - Temperature MSW: Address 1.A061 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Status: Address 1.A06E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Capability: Address 1.A06F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Alarms 1: Address 1.A070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

XENPAK DOM - Alarms 2: Address 1.A071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

XENPAK DOM - Alarms 3: Address 1.A072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Alarms 4: Address 1.A073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Alarms 5: Address 1.A074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 . . . 218

PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412 . . . . . . . . . . . . . . . . . . . . . . 218

PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413 . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 1: Address 1.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 2: Address 1.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 3: Address 1.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

PMA Transmit Standard Interrupt Mask 1: Address 1.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

PMA Transmit Standard Interrupt Mask 2: Address 1.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400 . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401 . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402 . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor Debug 1: Address 1.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 . . . . . . . . . . . . . . . . . . . . . . . 222

PMA Receive Vendor State 1: Address 1.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

PMA Receive Reserved Vendor State 1: Address 1.E810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

PMA Receive Reserved Vendor State 2: Address 1.E811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

PMA Vendor Global Interrupt Flags 1: Address 1.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

PCS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

PCS Standard Control 1: Address 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

PCS Standard Status 1: Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

PCS Standard Device Identifier 1: Address 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

PCS Standard Device Identifier 2: Address 3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

PCS Standard Speed Ability: Address 3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

PCS Standard Devices in Package 1: Address 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

PCS Standard Devices in Package 2: Address 3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

PCS Standard Control 2: Address 3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

PCS Standard Status 2: Address 3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

PCS Standard Package Identifier 1: Address 3.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS Standard Package Identifier 2: Address 3.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS EEE Capability Register : Address 3.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

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PCS 10G Status 1: Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

PCS 10G Status 2: Address 3.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B . . . . . . . . . . . . . . . . . . . . . . 241

TimeSync PCS Capability: Address 3.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

TimeSync PCS Transmit Path Data Delay 1: Address 3.1801 . . . . . . . . . . . . . . . . . . . . . . . . . 242

TimeSync PCS Transmit Path Data Delay 2: Address 3.1802 . . . . . . . . . . . . . . . . . . . . . . . . . 242

TimeSync PCS Transmit Path Data Delay 3: Address 3.1803 . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Transmit Path Data Delay 4: Address 3.1804 . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Receive Path Data Delay 1: Address 3.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Receive Path Data Delay 2: Address 3.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . 244

TimeSync PCS Receive Path Data Delay 3: Address 3.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . 244

TimeSync PCS Receive Path Data Delay 4: Address 3.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . 244

PCS Transmit Vendor Provisioning 1: Address 3.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit Vendor Provisioning 2: Address 3.C401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410 . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit XFI Vendor Provisioning 1: Address 3.C455 . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 2: Address 3.C456 . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 3: Address 3.C457 . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 4: Address 3.C458 . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 5: Address 3.C459 . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 . . . . . . . . . . . . . . . . . . . . . . . . . . 249

PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . 250

PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . 250

PCS USX0 Memory Control Register: Address 3.C4C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

PCS USX0 Control Register 1: Address 3.C4C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

PCS USX0 Local fault Control Register: Address 3.C4C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

PCS USX0 MAC Local fault Control Register: Address 3.C4C3 . . . . . . . . . . . . . . . . . . . . . . . . 254

PCS USX0 Auto-Neg Control Register: Address 3.C4C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

PCS USX0 PTP Control Register: Address 3.C4C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

PCS USX0 PKT Info Message Register-0: Address 3.C4C6 . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 PKT Info Message Register-1: Address 3.C4C7 . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 PKT Info Message Register-2: Address 3.C4C8 . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 link Fill Data Register-0: Address 3.C4C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 link Fill Data Register-1: Address 3.C4CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 Link FIFO Control Register: Address 3.C4CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 TX FIFO Control Register: Address 3.C4CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

PCS USX0 Local Advertisement Register: Address 3.C4CD . . . . . . . . . . . . . . . . . . . . . . . . . . 259

PCS USX1 Memory Control Register: Address 3.C4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

PCS USX1 Control Register 1: Address 3.C4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

PCS USX1 Local fault Control Register: Address 3.C4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

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PCS USX1 MAC Local fault Control Register: Address 3.C4E3 . . . . . . . . . . . . . . . . . . . . . . . . 262

PCS USX1 Auto-Neg Control Register: Address 3.C4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

PCS USX1 PTP Control Register: Address 3.C4E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

PCS USX1 PKT Info Message Register-0: Address 3.C4E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

PCS USX1 PKT Info Message Register-1: Address 3.C4E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 PKT Info Message Register-2: Address 3.C4E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 link Fill Data Register-0: Address 3.C4E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 link Fill Data Register-1: Address 3.C4EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

PCS USX1 Link FIFO Control Register: Address 3.C4EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

PCS USX1 TX FIFO Control Register: Address 3.C4EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

PCS USX1 Local Advertisement Register: Address 3.C4ED . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

PCS SERDES MUX Swap TXRX Register: Address 3.C4F0 . . . . . . . . . . . . . . . . . . . . . . . . . . 269

PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 . . . . . . . . . . . . . . . . . 270

PCS Transmit Vendor FCS No Error Frame Counter 2: Address 3.C821 . . . . . . . . . . . . . . . . . 270

PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit XFI0 Vendor State 1: Address 3.C860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit XFI0 Vendor State 2: Address 3.C861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

PCS Transmit XFI0 Vendor State 3: Address 3.C862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

PCS Transmit XFI0 Vendor State 4: Address 3.C863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

PCS Transmit XFI1 Vendor State 1: Address 3.C870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 2: Address 3.C871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 3: Address 3.C872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 4: Address 3.C873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

PCS Transmit XGS Vendor State 1: Address 3.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

PCS Transmit XGS Vendor State 2: Address 3.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

PCS Transmit XGS Vendor State 3: Address 3.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS Transmit XGS Vendor State 4: Address 3.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS Transmit XGS Vendor State 5: Address 3.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS USX0 Transmit Status : Address 3.C8C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

PCS Transmit Vendor System Interface State 1: Address 3.C8F0 . . . . . . . . . . . . . . . . . . . . . . 277

PCS PTP Vendor State 1: Address 3.C900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

PCS PTP Vendor State 2: Address 3.C901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 3: Address 3.C902 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 4: Address 3.C903 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 5: Address 3.C904 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 6: Address 3.C905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 7: Address 3.C906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 8: Address 3.C907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 9: Address 3.C908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 10: Address 3.C909 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 11: Address 3.C90A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 12: Address 3.C90B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 13: Address 3.C90C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 14: Address 3.C90D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 15: Address 3.C90E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 16: Address 3.C90F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 17: Address 3.C910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 18: Address 3.C911 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 19: Address 3.C912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 20: Address 3.C913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PCS PTP Vendor State 21: Address 3.C914 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

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PCS PTP Vendor State 22: Address 3.C915 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PCS PTP Vendor State 23: Address 3.C916 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 24: Address 3.C917 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 25: Address 3.C918 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 26: Address 3.C919 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PCS PTP Vendor State 27: Address 3.C91A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PCS PTP Vendor State 28: Address 3.C91B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PCS PTP Vendor State 29: Address 3.C91C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 31: Address 3.C91E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 32: Address 3.C91F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 33: Address 3.C920 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 34: Address 3.C921 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 35: Address 3.C922 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Egress Vendor State 1: Address 3.C930 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Egress Vendor State 2: Address 3.C931 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Egress Vendor State 3: Address 3.C932 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

PCS PTP Egress Vendor State 4: Address 3.C933 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

PCS PTP Egress Vendor State 5: Address 3.C934 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS PTP Egress Vendor State 6: Address 3.C935 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS PTP Egress Vendor State 7: Address 3.C936 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS Transmit Vendor Alarms 1: Address 3.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

PCS Transmit Vendor Alarms 2: Address 3.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Transmit Vendor Alarms 3: Address 3.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Transmit Vendor Alarms 4: Address 3.CC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Standard Interrupt Mask 1: Address 3.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

PCS Standard Interrupt Mask 2: Address 3.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

PCS Standard Interrupt Mask 3: Address 3.D002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Debug 1: Address 3.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

PCS Receive Vendor Provisioning 1: Address 3.E400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

PCS Receive XFI0 Provisioning 1: Address 3.E460 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

PCS Receive XFI0 Provisioning 2: Address 3.E461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

PCS Receive XFI1 Provisioning 1: Address 3.E470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

PCS Receive XFI1 Provisioning 2: Address 3.E471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

PCS USX0 RX Control Register: Address 3.E4D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

PCS USX0 RX FIFO Control Register: Address 3.E4D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

PCS USX0 SM Control Register: Address 3.E4D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

PCS USX0 Link Timer Control Register: Address 3.E4D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

PCS USX0 RX Fault Control Register: Address 3.E4D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

PCS USX1 RX Control Register: Address 3.E4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

PCS USX1 RX FIFO Control Register: Address 3.E4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

PCS USX1 SM Control Register: Address 3.E4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

PCS USX1 Link Timer Control Register: Address 3.E4E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

PCS USX1 RX Fault Control Register: Address 3.E4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

PCS PTP Ingress Vendor Provisioning 1: Address 3.E600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

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PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

PCS Receive Vendor State 1: Address 3.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810 . . . . . . . . . . . . . . . . . . . . . . . . 332

PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811 . . . . . . . . . . . . . . . . . . . . . . . . 333

PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 . . . . . . . . . . . . . . . . . . 333

PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 . . . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 . . . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 . . . . . . . . . . . . . . . . . . . 335

PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 . . . . . . . . . . . . . . . . . . . 335

PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 . . . . . . . . . . . . 336

PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 . . . . . . . . . . . . 336

PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 . . . . . . . . . . . . 337

PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 . . . . . . . . . . . . 337

PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 . . . . . . . . . . . . 338

PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 . . . . . . . . . . . . 338

PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 . . . . . . . . . . . . 339

PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 . . . . . . . . . . . . 339

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PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 . . . . . . . . . . . . 340

PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 . . . . . . . . . . . . 340

PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 . . . . . . . . . . . . . 341

PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 . . . . . . . . . . . . . 341

PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 . . . . . . . . . . . . . 341

PCS Receive XFI0 Vendor State 1: Address 3.E860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 2: Address 3.E861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 3: Address 3.E862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 4: Address 3.E863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 5: Address 3.E864 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 6: Address 3.E865 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 7: Address 3.E866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 1: Address 3.E870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 2: Address 3.E871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 3: Address 3.E872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 4: Address 3.E873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 5: Address 3.E874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 6: Address 3.E875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

PCS Receive XFI1 Vendor State 7: Address 3.E876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 . . . . . . . . . . . . . . . . . . . . . 346

PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Unidata and SM status Register: Address 3.E8D4 . . . . . . . . . . . . . . . . . . . . . . . . . 348

PCS USX0 Receive Status Register: Address 3.E8D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 349

PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 . . . . . . . . . . . . . . . . . . . . . 350

PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Unidata and SM status Register: Address 3.E8E4 . . . . . . . . . . . . . . . . . . . . . . . . . 352

PCS USX1 Receive Status Register: Address 3.E8E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 353

PCS Receive Vendor Alarms 1: Address 3.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

PCS Receive Vendor Alarms 2: Address 3.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 3: Address 3.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 4: Address 3.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 5: Address 3.EC04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 6: Address 3.EC05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

PCS Receive Vendor Alarms 7: Address 3.EC06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

PCS Receive Vendor Alarms 10: Address 3.EC09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

PCS Receive Vendor Alarms 14: Address 3.EC0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

PCS Receive Vendor Alarms 15: Address 3.EC0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

PCS Receive Vendor Alarms 16: Address 3.EC0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

PCS Receive Vendor Alarms 17: Address 3.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

PCS Receive Vendor Internal Alarms : Address 3.ED0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

PCS Receive Vendor Internal Alarms : Address 3.ED0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

PCS Receive Vendor Internal Alarms : Address 3.ED0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

PCS Receive Vendor Internal Alarms : Address 3.ED10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

PCS Receive Vendor Interrupt Mask 1: Address 3.F400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

PCS Receive Vendor Interrupt Mask 2: Address 3.F401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

PCS Receive Vendor Interrupt Mask 3: Address 3.F402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

PCS Receive Vendor Interrupt Mask 4: Address 3.F403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

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PCS Receive Vendor Interrupt Mask 5: Address 3.F404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

PCS Receive Vendor Interrupt Mask 6: Address 3.F405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

PCS Receive Vendor Interrupt Mask 7: Address 3.F406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

PCS Receive Vendor Debug 1: Address 3.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

PCS Vendor Global Interrupt Flags 1: Address 3.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

PCS Vendor Global Interrupt Flags 3: Address 3.FC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

PHY XS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

PHY XS Standard Control 1: Address 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

PHY XS Standard Status 1: Address 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

PHY XS Standard Device Identifier 1: Address 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Device Identifier 2: Address 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Speed Ability: Address 4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Devices in Package 1: Address 4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

PHY XS Standard Devices in Package 2: Address 4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

PHY XS Standard Status 2: Address 4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

PHY XS Standard Package Identifier 1: Address 4.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

PHY XS Standard Package Identifier 2: Address 4.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

PHY XS EEE Capability Register: Address 4.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

PHY XS EEE Wake Error Counter: Address 4.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

PHY XS Standard XGXS Lane Status: Address 4.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

PHY XS Standard XGXS Test Control: Address 4.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

TimeSync PHY XS Capability: Address 4.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 . . . . . . . . . . . . . . . . . . . . . . . 393

TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 . . . . . . . . . . . . . . . . . . . . . . . 393

PHY XS SERDES Configuration 1: Address 4.C180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . 394

PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 . . . . . . . . . . . . . . . . . . . . . . . . . . 394

PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS SERDES LUT 256: Address 4.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 . . . . . . . . . . . 396

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 . . . . . . . . . . . 398

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 . . . . . . . . . . . 400

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 . . . . . . . . . . . 401

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 . . . . . . . . . . . 402

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 . . . . . . . . . . . . . . . . . 406

PHY XS Transmit (XAUI Rx) Reserved Vendor State 3: Address 4.C822 . . . . . . . . . . . . . . . . . 406

PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 . . . . . . . . . . . . . . . . . . . . . . . 407

PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 . . . . . . . . . . . . . . . . . . . . . . . 407

PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 . . . . . . . . . . . . . . . . . . . . . . . 409

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. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 . . . . . . . . . . . . . . . . 409

PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 . . . . . . . . . . . . . . . . 410

PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400 . . . . . . . . . . . . . . . . . 410

PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401 . . . . . . . . . . . . . . . . . 411

PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402 . . . . . . . . . . . . . . . . . 412

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 . . . . . . . . . . . . . . . . . . . . . . . . 413

PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 . . . . . . . . . . . . . . . . . . . . . . . . 414

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 . . . . . . . . . . . . . . 415

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 . . . . . . . . . . . . . . 415

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 . . . . . . . . . . . . . . 416

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 . . . . . . . . . . . . . . 416

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 . . . . . . . . . . . . . . 417

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 . . . . . . . . . . . . 417

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 . . . . . . . . . . . . 418

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 . . . . . . . . . . . . 419

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 . . . . . . . . . . . . 420

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 . . . . . . . . . . . . 420

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 . . . . . . . . . . . . 421

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 7: Address 4.E416 . . . . . . . . . . . . 421

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 . . . . . . . . . . . . 422

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 . . . . . . . . . . . . 422

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810 . . . . . . . . . . . . . . . . . 424

PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>:

Address 4.E812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 . . . . . . . . . . . . . . . . . . . . . . . . 426

PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 . . . . . . . . . . . . . . . . . . . . . . . . 427

PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400 . . . . . . . . . . . . . . . . . . 428

PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401 . . . . . . . . . . . . . . . . . . 429

PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 . . . . . . . . . . . . . . . . . . . . . . . . 430

PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 . . . . . . . . . . . . . . . . . . . . . . . . 430

PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 . . . . . . . . . . . . . . . . . . . . . . . . 431

PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Autonegotiation Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Autonegotiation Standard Control 1: Address 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Autonegotiation Standard Status 1: Address 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Autonegotiation Standard Device Identifier 1: Address 7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Autonegotiation Standard Device Identifier 2: Address 7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Autonegotiation Standard Devices in Package 1: Address 7.5 . . . . . . . . . . . . . . . . . . . . . . . . . 436

Autonegotiation Standard Devices in Package 2: Address 7.6 . . . . . . . . . . . . . . . . . . . . . . . . . 437

Autonegotiation Standard Status 2: Address 7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Autonegotiation Standard Package Identifier 1: Address 7.E . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Autonegotiation Standard Package Identifier 2: Address 7.F . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Autonegotiation Advertisement Register: Address 7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

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Autonegotiation Link Partner Base Page Ability Register: Address 7.13 . . . . . . . . . . . . . . . . . . 440

Autonegotiation Extended Next Page Transmit Register: Address 7.16 . . . . . . . . . . . . . . . . . . 442

Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 . . . . . . . . . 443

Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 . . . . . . . . . 443

Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 . . . . . . . . . . 443

Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A 444

Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B 445

Autonegotiation 10GBASE-T Control Register: Address 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Autonegotiation 10GBASE-T Status Register: Address 7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Autonegotiation EEE Advertisement Register: Address 7.3C . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Autonegotiation EEE Link Partner Ability Register: Address 7.3D . . . . . . . . . . . . . . . . . . . . . . . 448

KR0 Autonegotiation Control: Address 7.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

KR0 Autonegotiation Status: Address 7.C201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

KR0 Autonegotiation Advertisement Word 1: Address 7.C210 . . . . . . . . . . . . . . . . . . . . . . . . . 452

KR0 Autonegotiation Advertisement Word 2: Address 7.C211 . . . . . . . . . . . . . . . . . . . . . . . . . 453

KR0 Autonegotiation Advertisement Word 3: Address 7.C212 . . . . . . . . . . . . . . . . . . . . . . . . . 454

KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 . . . . . . . . . . . . . . . 454

KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 . . . . . . . . . . . . . . . 456

KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 . . . . . . . . . . . . . . . 457

KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216 . . . . . . . . 457

KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217 . . . . . . . . 458

KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218 . . . . . . . . 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B 459

KR1 Autonegotiation Control: Address 7.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

KR1 Autonegotiation Status: Address 7.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

KR1 Autonegotiation Advertisement Word 1: Address 7.C310 . . . . . . . . . . . . . . . . . . . . . . . . . 461

KR1 Autonegotiation Advertisement Word 2: Address 7.C311 . . . . . . . . . . . . . . . . . . . . . . . . . 462

KR1 Autonegotiation Advertisement Word 3: Address 7.C312 . . . . . . . . . . . . . . . . . . . . . . . . . 463

KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 . . . . . . . . . . . . . . . 463

KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 . . . . . . . . . . . . . . . 465

KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 . . . . . . . . . . . . . . . 466

KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316 . . . . . . . . 466

KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317 . . . . . . . . 467

KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318 . . . . . . . . 467

KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 467

KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A 467

KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B 468

Autonegotiation Vendor Provisioning 1: Address 7.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 . . . . . . . . . . . . . . . . . . . . . 470

Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 . . . . . . . . . . . . . . . . . . . . . 472

Autonegotiation Vendor Status 1: Address 7.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Autonegotiation Reserved Vendor Status 1: Address 7.C810 . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Autonegotiation Reserved Vendor Status 2: Address 7.C811 . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Autonegotiation Reserved Vendor Status 3: Address 7.C812 . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Reserved Vendor Status 4: Address 7.C813 . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Reserved Vendor Status 5: Address 7.C814 . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Autonegotiation Standard Interrupt Mask 1: Address 7.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Autonegotiation Standard Interrupt Mask 2: Address 7.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 . . . . . . . . . . . . . . . . . . . . 479

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Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 . . . . . . . . . . . . . . . . . . . . 480

Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 . . . . . . . . . . . . . . . . . . . . 480

Autonegotiation Receive Link Partner Status 1: Address 7.E820 . . . . . . . . . . . . . . . . . . . . . . . 481

Autonegotiation Receive Link Partner Status 2: Address 7.E821 . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Link Partner Status 3: Address 7.E822 . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Link Partner Status 4: Address 7.E823 . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 . . . . . . . . . . . . . . . . . . . 483

Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 . . . . . . . . . . . . . . . . . . . 483

Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 . . . . . . . . . . . . . . . . . . . 484

Autonegotiation Receive Vendor Alarms 1: Address 7.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Autonegotiation Receive Vendor Alarms 2: Address 7.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Autonegotiation Receive Vendor Alarms 3: Address 7.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Autonegotiation Receive Vendor Alarms 4: Address 7.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 . . . . . . . . . . . . . . . . . . . . . 487

Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 . . . . . . . . . . . . . . . . . . . . . 487

Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 . . . . . . . . . . . . . . . . . . . . . . 488

100BASE-TX and 1000BASE-T Registers . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Device Identifier 1: Address 1D.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Device Identifier 2: Address 1D.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Devices in Package 1: Address 1D.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Vendor Devices in Package 2: Address 1D.6 . . . . . . . . . . . . . . . . . . . . . . . . . . 492

GbE Standard Status 2: Address 1D.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

GbE Standard Package Identifier 1: Address 1D.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

GbE Standard Package Identifier 2: Address 1D.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

GbE PHY SGMII Test Control : Address 1D.C282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

GbE PHY WoL Control 1: Address 1D.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

GbE PHY WoL Control 2: Address 1D.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 3: Address 1D.C302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 4: Address 1D.C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 5: Address 1D.C304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 6: Address 1D.C305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

GbE PHY WoL Control 7: Address 1D.C306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

GbE PHY WoL Control 8: Address 1D.C307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

GbE PHY WoL Control 9: Address 1D.C308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 10: Address 1D.C309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 11: Address 1D.C30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 12: Address 1D.C30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 13: Address 1D.C30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 14: Address 1D.C30D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 15: Address 1D.C30E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 16: Address 1D.C30F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 17: Address 1D.C310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 18: Address 1D.C311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 19: Address 1D.C312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 20: Address 1D.C313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 21: Address 1D.C314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 22: Address 1D.C315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 23: Address 1D.C316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 24: Address 1D.C317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

GbE PHY WoL Control 25: Address 1D.C318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

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GbE PHY WoL Control 26: Address 1D.C319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

GbE PHY WoL Control 27: Address 1D.C31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 28: Address 1D.C31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 29: Address 1D.C31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 30: Address 1D.C31D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 31: Address 1D.C31E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 32: Address 1D.C31F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 33: Address 1D.C320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 34: Address 1D.C321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 35: Address 1D.C322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 36: Address 1D.C323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 37: Address 1D.C324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 38: Address 1D.C325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 39: Address 1D.C326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

GbE PHY WoL Control 40: Address 1D.C327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

GbE PHY WoL Control 41: Address 1D.C328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

GbE PHY WoL Control 42: Address 1D.C329 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 43: Address 1D.C32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 44: Address 1D.C32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 45: Address 1D.C32C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 46: Address 1D.C32D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 47: Address 1D.C32E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 48: Address 1D.C32F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 49: Address 1D.C330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 50: Address 1D.C331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 51: Address 1D.C332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 52: Address 1D.C333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 53: Address 1D.C334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 54: Address 1D.C335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 55: Address 1D.C336 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 56: Address 1D.C337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 57: Address 1D.C338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 58: Address 1D.C339 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 59: Address 1D.C33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 60: Address 1D.C33B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 1: Address 1D.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 2: Address 1D.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 3: Address 1D.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 4: Address 1D.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 5: Address 1D.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 6: Address 1D.C425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 7: Address 1D.C426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 8: Address 1D.C427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 9: Address 1D.C428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 10: Address 1D.C429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 11: Address 1D.C42A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 12: Address 1D.C42B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 13: Address 1D.C42C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 14: Address 1D.C42D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 15: Address 1D.C42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 16: Address 1D.C42F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 17: Address 1D.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 18: Address 1D.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

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GbE PHY Extended WoL Control 19: Address 1D.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

GbE PHY Extended WoL Control 20: Address 1D.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

GbE PHY Extended WoL Control 21: Address 1D.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

GbE PHY Extended WoL Control 22: Address 1D.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

GbE PHY Extended WoL Control 23: Address 1D.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

GbE PHY Extended WoL Control 24: Address 1D.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 25: Address 1D.C438 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 26: Address 1D.C439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 27: Address 1D.C43A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 28: Address 1D.C43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 29: Address 1D.C43C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 30: Address 1D.C43D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

GbE Reserved Provisioning 1: Address 1D.C500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

GbE Reserved Provisioning 2: Address 1D.C501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

GbE PHY SGMII1 Rx Status 1: Address 1D.D280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

GbE PHY SGMII1 Rx Status 2: Address 1D.D281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 7: Address 1D.D286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 8: Address 1D.D287 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

GbE PHY SGMII1 Rx Status 9: Address 1D.D288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

GbE PHY SGMII0 Rx Status 1: Address 1D.D290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

GbE PHY SGMII0 Rx Status 2: Address 1D.D291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

GbE PHY SGMII0 Rx Status 3: Address 1D.D292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

GbE PHY SGMII0 Rx Status 4: Address 1D.D293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 5: Address 1D.D294 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 6: Address 1D.D295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 7: Address 1D.D296 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII0 Rx Status 8: Address 1D.D297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII0 Rx Status 9: Address 1D.D298 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII1 WoL Status: Address 1D.D302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

GbE PHY SGMII1 Tx Status 1: Address 1D.D303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Tx Status 2: Address 1D.D304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Tx Status 3: Address 1D.D305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Tx Status 4: Address 1D.D306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 5: Address 1D.D307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 6: Address 1D.D308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 7: Address 1D.D309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 8: Address 1D.D30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 9: Address 1D.D30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 10: Address 1D.D30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

SGMII0 WoL Status : Address 1D.D312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

GbE PHY SGMII0 Tx Status 1: Address 1D.D313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

GbE PHY SGMII0 Tx Status 2: Address 1D.D314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 3: Address 1D.D315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 4: Address 1D.D316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 5: Address 1D.D317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 6: Address 1D.D318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 7: Address 1D.D319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 8: Address 1D.D31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

GbE PHY SGMII0 Tx Status 9: Address 1D.D31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

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GbE PHY SGMII0 Tx Status 10: Address 1D.D31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

GbE PHY SGMII WoL Status: Address 1D.D322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . 547

Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Global Standard Control 1: Address 1E.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Global Standard Device Identifier 1: Address 1E.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Global Standard Device Identifier 2: Address 1E.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Global Standard Devices in Package 1: Address 1E.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Global Standard Vendor Devices in Package 2: Address 1E.6 . . . . . . . . . . . . . . . . . . . . . . . . . 551

Global Standard Status 2: Address 1E.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Standard Package Identifier 1: Address 1E.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Standard Package Identifier 2: Address 1E.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Firmware ID: Address 1E.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Global NVR Interface 1: Address 1E.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Global NVR Interface 2: Address 1E.101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Global NVR Interface 3: Address 1E.102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Global NVR Interface 4: Address 1E.103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Global NVR Interface 5: Address 1E.104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

Global NVR Interface 6: Address 1E.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Global Mailbox Interface 1: Address 1E.200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Global Mailbox Interface 2: Address 1E.201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Global Mailbox Interface 3: Address 1E.202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 4: Address 1E.203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 5: Address 1E.204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 6: Address 1E.205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Mailbox Interface 7: Address 1E.206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Microprocessor Scratch Pad 1: Address 1E.300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Microprocessor Scratch Pad 2: Address 1E.301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Global Control 1: Address 1E.C000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Global Control 2: Address 1E.C001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Global Reset Control: Address 1E.C006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Global Diagnostic Provisioning: Address 1E.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Global Thermal Provisioning 1: Address 1E.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Global Thermal Provisioning 2: Address 1E.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Global Thermal Provisioning 3: Address 1E.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

Global Thermal Provisioning 4: Address 1E.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Global Thermal Provisioning 5: Address 1E.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Global LED Provisioning 1: Address 1E.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Global LED Provisioning 2: Address 1E.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Global LED Provisioning 3: Address 1E.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Global LED Provisioning 4: Address 1E.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

Global LED Provisioning 5: Address 1E.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 6: Address 1E.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 7: Address 1E.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 8: Address 1E.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 15: Address 1E.C43E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Global General Provisioning 1: Address 1E.C440 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Global General Provisioning 2: Address 1E.C441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

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Global General Provisioning 3: Address 1E.C442 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

Global General Provisioning 4: Address 1E.C443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 5: Address 1E.C444 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 6: Address 1E.C445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 7: Address 1E.C446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 8: Address 1E.C447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global General Provisioning 9: Address 1E.C448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global General Provisioning 10: Address 1E.C449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global NVR Provisioning 1: Address 1E.C450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Global NVR Provisioning 2: Address 1E.C451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Global NVR Provisioning 3: Address 1E.C452 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Global NVR Provisioning 4: Address 1E.C453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Global Reserved Provisioning 1: Address 1E.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

Global Reserved Provisioning 2: Address 1E.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Global Reserved Provisioning 3: Address 1E.C472 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Global Reserved Provisioning 4: Address 1E.C473 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Global Reserved Provisioning 5: Address 1E.C474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Global Reserved Provisioning 6: Address 1E.C475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Global Reserved Provisioning 9: Address 1E.C478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Global Reserved Provisioning 10: Address 1E.C479 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Global Reserved Provisioning 11: Address 1E.C47A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Global Reserved Provisioning 12: Address 1E.C47B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C . . . . . . . . . . . . . 591

PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D . . . . . . . . . . . . . 591

PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E . . . . . . . . . . . . . 592

PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F . . . . . . . . . . . . . 592

Global SMBus 0 Provisioning 6: Address 1E.C485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global SMBus 1 Provisioning 6: Address 1E.C495 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global EEE Provisioning 1: Address 1E.C4A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global Cable Diagnostic Status 1: Address 1E.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Global Cable Diagnostic Status 2: Address 1E.C801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Global Cable Diagnostic Status 3: Address 1E.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 4: Address 1E.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 5: Address 1E.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 6: Address 1E.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Cable Diagnostic Status 7: Address 1E.C806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Cable Diagnostic Status 8: Address 1E.C807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Thermal Status 1: Address 1E.C820 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global Thermal Status 2: Address 1E.C821 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global General Status 1: Address 1E.C830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global General Status 2: Address 1E.C831 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

Global Pin Status: Address 1E.C840 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Global Daisy Chain Status 2: Address 1E.C842 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Global Fault Message: Address 1E.C850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Global Cable Diagnostic Impedance 1: Address 1E.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

Global Cable Diagnostic Impedance 2: Address 1E.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Global Cable Diagnostic Impedance 3: Address 1E.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Global Cable Diagnostic Impedance 4: Address 1E.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

Global Status: Address 1E.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Global Reserved Status 1: Address 1E.C885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Global Reserved Status 2: Address 1E.C886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Global Reserved Status 3: Address 1E.C887 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Global Reserved Status 4: Address 1E.C888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

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Global Alarms 1: Address 1E.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Global Alarms 2: Address 1E.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Global Alarms 3: Address 1E.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Global Interrupt Mask 1: Address 1E.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

Global Interrupt Mask 2: Address 1E.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

Global Interrupt Mask 3: Address 1E.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . 620

Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 . . . . . . . . . . . . . . . . . . . . . . . . . 624

Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

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AQR405 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

AQR405 system block interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii

Part marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv

Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Ethertype and VLAN parsing algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 11

User priority resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MDIO bus turn-around during Read operations . . . . . . . . . . . . . . . . . . . 25

SPI Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SPI Burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SPI burst write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Daisy-chain operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Daisy-chain signals and direction of flow . . . . . . . . . . . . . . . . . . . . . . . . 33

AQR405 operational blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

AQR405 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

MDIO setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Daisy-chain timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

RXAUI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

RXAUI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SGMII transmit timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SGMII receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

KR transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

KR receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2500BASE-X transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2500BASE-X receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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50 MHz input timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

50.000 MHz phase noise mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

50 MHz reference clock output timing diagram. . . . . . . . . . . . . . . . . . . 69

JTAG timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Power versus time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

AQR405 package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Functional view of AQR405. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

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Additional ingress MACsec statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional egress MACsec statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

“Per SCI” 32-bit mapping table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

MAC statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Management Interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

MDIO frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-on reset thresholds for core supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Serial FLASH signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

DC_MASTER_N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SERDES signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

KR diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

RXAUI/XAUI diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SGMII diagnostic pattern capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

SERDES lane assignments for different operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

XSGMII base page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

USXGMII base page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

MDI signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Timing signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

LED signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Reference Resistors signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Metrology signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Wake-On-LAN signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Debug signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Reserved signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

MDIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Daisy-chain timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

SERDES receiver jitter tolerance specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

SERDES transmit jitter tolerance specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

RXAUI transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

RXAUI receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

SGMII transmit timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SGMII receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

KR transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

KR receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

2500BASE-X transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

2500BASE-X receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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50.000 MHz input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

50 MHz reference clock output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

JTAG timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

AQR405 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

AQR405 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Full-reach VA22 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Full-reach VA12 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Full-reach VDD fixed supply electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

VDD_IO electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

VDD_FLASH electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.2V mode MDIO electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

I/O pin electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

70% / 30% VDD_IO mode MDIO electrical interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 77

SPI pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SPI DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SERDES transmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

SERDES receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

MDI electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

LVDS 50MHz input electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

CLK_1588 input electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Bandgap reference resistor electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Theta J’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

MMD device addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Field types within the MDIO register space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Terms used within the register layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

PMA Standard Control 1: Address 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

PMA Standard Status 1: Address 1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

PMA Standard Device Identifier 1: Address 1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PMA Standard Device Identifier 2: Address 1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

PMA Standard Speed Ability: Address 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96

PMA Standard Devices in Package 1: Address 1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

PMA Standard Devices in Package 2: Address 1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

PMA Standard Control 2: Address 1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

PMA Standard Status 2: Address 1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

PMD Standard Transmit Disable Control: Address 1.9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PMD Standard Signal Detect: Address 1.A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

PMD Standard 10G Extended Ability Register: Address 1.B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

PMA Standard Package Identifier 1: Address 1.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

PMA Standard Package Identifier 2: Address 1.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMA 10GBASE-T Status: Address 1.81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

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PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82 . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83 . . . . . . . . . . . . . . . . 105

PMA 10GBASE-T Test Modes: Address 1.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85. . . . . . . . . . . . . . . . . . . . . . . . 107

PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86. . . . . . . . . . . . . . . . . . . . . . . . 107

PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87 . . . . . . . . . . . . . . . . . . . . . . . 108

PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88 . . . . . . . . . . . . . . . . . . . . . . . 108

PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89 . . . . . . . . . . . . . . . . 109

PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A. . . . . . . . . . . . . . . . 109

PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B . . . . . . . . . . . . . . . 110

PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C . . . . . . . . . . . . . . . 110

PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D . . . . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E . . . . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F . . . . . . . . . . . . . . . . . . . . . . . . 111

PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90 . . . . . . . . . . . . . . . . . . . . . . . . 112

PMA 10GBASE-T Skew Delay 1: Address 1.91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

PMA 10GBASE-T Skew Delay 2: Address 1.92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

PMA 10GBASE-T Fast Retrain Status and Control : Address 1.93 . . . . . . . . . . . . . . . . . . . . . . . . . 114

TimeSync PMA Capability: Address 1.1800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 1: Address 1.1801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 2: Address 1.1802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

TimeSync PMA Transmit Path Data Delay 3: Address 1.1803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

TimeSync PMA Transmit Path Data Delay 4: Address 1.1804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

TimeSync PMA Receive Path Data Delay 1: Address 1.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

TimeSync PMA Receive Path Data Delay 2: Address 1.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TimeSync PMA Receive Path Data Delay 3: Address 1.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

TimeSync PMA Receive Path Data Delay 4: Address 1.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

XENPAK Control: Address 1.8000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

XENPAK Header - XENPAK MSA Version Supported: Address 1.8007 . . . . . . . . . . . . . . . . . . . . . 119

XENPAK Header - NVR Size 1: Address 1.8008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

XENPAK Header - NVR Size 2: Address 1.8009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

XENPAK Header - Memory Used 1: Address 1.800A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Memory Used 2: Address 1.800B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Basic Memory Start Address: Address 1.800C . . . . . . . . . . . . . . . . . . . . . . . . . 120

XENPAK Header - Customer Memory Offset: Address 1.800D. . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

XENPAK Header - Vendor Memory Start Address: Address 1.800E . . . . . . . . . . . . . . . . . . . . . . . . 121

XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F . . . . . . . . . . . . . . . . . . . . 121

XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010 . . . . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Reserved 0x11: Address 1.8011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Transceiver Type: Address 1.8012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

XENPAK Basic - Connector Type: Address 1.8013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

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XENPAK Basic - Encoding: Address 1.8014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

XENPAK Basic - Bit Rate 0: Address 1.8015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Bit Rate 1: Address 1.8016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Protocol: Address 1.8017 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

XENPAK Basic - Standards Compliance Codes: Address 1.8018 . . . . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 1: Address 1.8019 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 2: Address 1.801A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

XENPAK Basic - Reserved 0x19 3: Address 1.801B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 4: Address 1.801C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 5: Address 1.801D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

XENPAK Basic - Reserved 0x19 6: Address 1.801E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 7: Address 1.801F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 8: Address 1.8020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

XENPAK Basic - Reserved 0x19 9: Address 1.8021 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 10: Address 1.8022 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 11: Address 1.8023 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

XENPAK Basic - Reserved 0x19 12: Address 1.8024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 13: Address 1.8025 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 14: Address 1.8026 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

XENPAK Basic - Reserved 0x19 15: Address 1.8027 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 16: Address 1.8028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 17: Address 1.8029 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

XENPAK Basic - Reserved 0x19 18: Address 1.802A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 19: Address 1.802B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 20: Address 1.802C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

XENPAK Basic - Reserved 0x19 21: Address 1.802D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 22: Address 1.802E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 23: Address 1.802F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

XENPAK Basic - Reserved 0x19 24: Address 1.8030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Reserved 0x19 25: Address 1.8031 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 1: Address 1.8032 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 2: Address 1.8033 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

XENPAK Basic - Package Identifier 3: Address 1.8034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

XENPAK Basic - Package Identifier 4: Address 1.8035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

XENPAK Basic - Vendor Identifier 1: Address 1.8036 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

XENPAK Basic - Vendor Identifier 2: Address 1.8037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Identifier 3: Address 1.8038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Identifier 4: Address 1.8039 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Name 1: Address 1.803A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

XENPAK Basic - Vendor Name 2: Address 1.803B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

XENPAK Basic - Vendor Name 3: Address 1.803C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

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XENPAK Basic - Vendor Name 4: Address 1.803D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

XENPAK Basic - Vendor Name 5: Address 1.803E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 6: Address 1.803F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 7: Address 1.8040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

XENPAK Basic - Vendor Name 8: Address 1.8041 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 9: Address 1.8042 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 10: Address 1.8043 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

XENPAK Basic - Vendor Name 11: Address 1.8044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 12: Address 1.8045 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 13: Address 1.8046 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

XENPAK Basic - Vendor Name 14: Address 1.8047 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Name 15: Address 1.8048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Name 16: Address 1.8049 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

XENPAK Basic - Vendor Part Number 1: Address 1.804A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 2: Address 1.804B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 3: Address 1.804C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

XENPAK Basic - Vendor Part Number 4: Address 1.804D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 5: Address 1.804E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 6: Address 1.804F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

XENPAK Basic - Vendor Part Number 7: Address 1.8050. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 8: Address 1.8051. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 9: Address 1.8052. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

XENPAK Basic - Vendor Part Number 10: Address 1.8053. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 11: Address 1.8054. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 12: Address 1.8055. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

XENPAK Basic - Vendor Part Number 13: Address 1.8056. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 14: Address 1.8057. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 15: Address 1.8058. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

XENPAK Basic - Vendor Part Number 16: Address 1.8059. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A . . . . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B . . . . . . . . . . . . . . . . . . . . . . . . 146

XENPAK Basic - Vendor Serial Number 1: Address 1.805C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 2: Address 1.805D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 3: Address 1.805E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

XENPAK Basic - Vendor Serial Number 4: Address 1.805F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 5: Address 1.8060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 6: Address 1.8061 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

XENPAK Basic - Vendor Serial Number 7: Address 1.8062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 8: Address 1.8063 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 9: Address 1.8064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

XENPAK Basic - Vendor Serial Number 10: Address 1.8065 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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XENPAK Basic - Vendor Serial Number 11: Address 1.8066. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

XENPAK Basic - Vendor Serial Number 12: Address 1.8067. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

XENPAK Basic - Vendor Serial Number 13: Address 1.8068. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

XENPAK Basic - Vendor Serial Number 14: Address 1.8069. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

XENPAK Basic - Vendor Serial Number 15: Address 1.806A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

XENPAK Basic - Vendor Serial Number 16: Address 1.806B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 1: Address 1.806C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 2: Address 1.806D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

XENPAK Basic - Vendor Date Code 3: Address 1.806E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 4: Address 1.806F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 5: Address 1.8070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 6: Address 1.8071 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

XENPAK Basic - Vendor Date Code 7: Address 1.8072 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 8: Address 1.8073 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 9: Address 1.8074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

XENPAK Basic - Vendor Date Code 10: Address 1.8075 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

XENPAK Basic - 5V Loading: Address 1.8076. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

XENPAK Basic - 3.3V Loading: Address 1.8077 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

XENPAK Basic - APS Loading: Address 1.8078 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

XENPAK Basic - APS Voltage: Address 1.8079. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

XENPAK Basic - DOM Capability: Address 1.807A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

XENPAK Basic - Low-Power Startup Capability: Address 1.807B . . . . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Basic - Reserved 0x7C: Address 1.807C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Basic - Checksum: Address 1.807D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

XENPAK Customer - Reserved 0x7E 1: Address 1.807E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 2: Address 1.807F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 3: Address 1.8080. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

XENPAK Customer - Reserved 0x7E 4: Address 1.8081. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 5: Address 1.8082. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 6: Address 1.8083. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

XENPAK Customer - Reserved 0x7E 7: Address 1.8084. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 8: Address 1.8085. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 9: Address 1.8086. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

XENPAK Customer - Reserved 0x7E 10: Address 1.8087. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 11: Address 1.8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 12: Address 1.8089. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

XENPAK Customer - Reserved 0x7E 13: Address 1.808A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 14: Address 1.808B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 15: Address 1.808C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

XENPAK Customer - Reserved 0x7E 16: Address 1.808D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

XENPAK Customer - Reserved 0x7E 17: Address 1.808E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

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XENPAK Customer - Reserved 0x7E 18: Address 1.808F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

XENPAK Customer - Reserved 0x7E 19: Address 1.8090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 20: Address 1.8091 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 21: Address 1.8092 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

XENPAK Customer - Reserved 0x7E 22: Address 1.8093 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 23: Address 1.8094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 24: Address 1.8095 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

XENPAK Customer - Reserved 0x7E 25: Address 1.8096 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 26: Address 1.8097 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 27: Address 1.8098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

XENPAK Customer - Reserved 0x7E 28: Address 1.8099 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 29: Address 1.809A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 30: Address 1.809B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

XENPAK Customer - Reserved 0x7E 31: Address 1.809C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 32: Address 1.809D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 33: Address 1.809E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

XENPAK Customer - Reserved 0x7E 34: Address 1.809F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

XENPAK Customer - Reserved 0x7E 35: Address 1.80A0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

XENPAK Customer - Reserved 0x7E 36: Address 1.80A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

XENPAK Customer - Reserved 0x7E 37: Address 1.80A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 38: Address 1.80A3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 39: Address 1.80A4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

XENPAK Customer - Reserved 0x7E 40: Address 1.80A5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 41: Address 1.80A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 42: Address 1.80A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

XENPAK Customer - Reserved 0x7E 43: Address 1.80A8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 44: Address 1.80A9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 45: Address 1.80AA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

XENPAK Customer - Reserved 0x7E 46: Address 1.80AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Customer - Reserved 0x7E 47: Address 1.80AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Customer - Reserved 0x7E 48: Address 1.80AD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

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XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 83: Address 1.8100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 84: Address 1.8101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

XENPAK Vendor - Reserved 0xAE 85: Address 1.8102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 86: Address 1.8103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 87: Address 1.8104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

XENPAK Vendor - Reserved 0xAE 88: Address 1.8105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Vendor - Reserved 0xAE 89: Address 1.8106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Rx_Alarm - Control: Address 1.9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

XENPAK Tx_Alarm - Control: Address 1.9001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

XENPAK LASI - Control: Address 1.9002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

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XENPAK Rx_Alarm - Status: Address 1.9003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

XENPAK Tx_Alarm - Status: Address 1.9004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

XENPAK LASI - Status: Address 1.9005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

XENPAK DOM - Tx Control: Address 1.9006. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000 . . . . . . . . . . . . . . . . . 210

XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001 . . . . . . . . . . . . . . . . . 211

XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002. . . . . . . . . . . . . . . . . . 211

XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003 . . . . . . . . . . . . . . . . . 212

XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004 . . . . . . . . . . . . . . . 212

XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005 . . . . . . . . . . . . . . . 213

XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006. . . . . . . . . . . . . . . . 213

XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007 . . . . . . . . . . . . . . . 214

XENPAK DOM - Temperature LSW: Address 1.A060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

XENPAK DOM - Temperature MSW: Address 1.A061. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Status: Address 1.A06E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Capability: Address 1.A06F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

XENPAK DOM - Alarms 1: Address 1.A070. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

XENPAK DOM - Alarms 2: Address 1.A071. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

XENPAK DOM - Alarms 3: Address 1.A072. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Alarms 4: Address 1.A073. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Alarms 5: Address 1.A074. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100 . . . . . . 218

PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412. . . . . . . . . . . . . . . . . . . . . . . . . . 218

PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413. . . . . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 1: Address 1.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 2: Address 1.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

PMA Transmit Vendor Alarms 3: Address 1.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

PMA Transmit Standard Interrupt Mask 1: Address 1.D000. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

PMA Transmit Standard Interrupt Mask 2: Address 1.D001. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400. . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401. . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402. . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

PMA Transmit Vendor Debug 1: Address 1.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

PMA Receive Reserved Vendor Provisioning 1: Address 1.E400 . . . . . . . . . . . . . . . . . . . . . . . . . . 222

PMA Receive Vendor State 1: Address 1.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

PMA Receive Reserved Vendor State 1: Address 1.E810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

PMA Receive Reserved Vendor State 2: Address 1.E811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

PMA Vendor Global Interrupt Flags 1: Address 1.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

PCS Standard Control 1: Address 3.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227

PCS Standard Status 1: Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

PCS Standard Device Identifier 1: Address 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

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PCS Standard Device Identifier 2: Address 3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

PCS Standard Speed Ability: Address 3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

PCS Standard Devices in Package 1: Address 3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

PCS Standard Devices in Package 2: Address 3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

PCS Standard Control 2: Address 3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

PCS Standard Status 2: Address 3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

PCS Standard Package Identifier 1: Address 3.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS Standard Package Identifier 2: Address 3.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS EEE Capability Register : Address 3.14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

PCS EEE Wake Error Counter: Address 3.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

PCS 10G Status 2: Address 3.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B . . . . . . . . . . . . . . . . . . . . . . . . . 241

TimeSync PCS Capability: Address 3.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

TimeSync PCS Transmit Path Data Delay 1: Address 3.1801. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

TimeSync PCS Transmit Path Data Delay 2: Address 3.1802. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

TimeSync PCS Transmit Path Data Delay 3: Address 3.1803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Transmit Path Data Delay 4: Address 3.1804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Receive Path Data Delay 1: Address 3.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

TimeSync PCS Receive Path Data Delay 2: Address 3.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

TimeSync PCS Receive Path Data Delay 3: Address 3.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

TimeSync PCS Receive Path Data Delay 4: Address 3.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

PCS Transmit Vendor Provisioning 1: Address 3.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit Vendor Provisioning 2: Address 3.C401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410. . . . . . . . . . . . . . . . . . . . . . . . . . 245

PCS Transmit XFI Vendor Provisioning 1: Address 3.C455. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 2: Address 3.C456. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 3: Address 3.C457. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

PCS Transmit XFI Vendor Provisioning 4: Address 3.C458. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 5: Address 3.C459. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

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PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250

PCS USX0 Memory Control Register: Address 3.C4C0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

PCS USX0 Control Register 1: Address 3.C4C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

PCS USX0 Local fault Control Register: Address 3.C4C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

PCS USX0 MAC Local fault Control Register: Address 3.C4C3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

PCS USX0 Auto-Neg Control Register: Address 3.C4C4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

PCS USX0 PTP Control Register: Address 3.C4C5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

PCS USX0 PKT Info Message Register-0: Address 3.C4C6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 PKT Info Message Register-1: Address 3.C4C7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 PKT Info Message Register-2: Address 3.C4C8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

PCS USX0 link Fill Data Register-0: Address 3.C4C9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 link Fill Data Register-1: Address 3.C4CA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 Link FIFO Control Register: Address 3.C4CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

PCS USX0 TX FIFO Control Register: Address 3.C4CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

PCS USX0 Local Advertisement Register: Address 3.C4CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259

PCS USX1 Memory Control Register: Address 3.C4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

PCS USX1 Control Register 1: Address 3.C4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

PCS USX1 Local fault Control Register: Address 3.C4E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

PCS USX1 MAC Local fault Control Register: Address 3.C4E3. . . . . . . . . . . . . . . . . . . . . . . . . . . . 262

PCS USX1 Auto-Neg Control Register: Address 3.C4E4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

PCS USX1 PTP Control Register: Address 3.C4E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

PCS USX1 PKT Info Message Register-0: Address 3.C4E6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

PCS USX1 PKT Info Message Register-1: Address 3.C4E7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 PKT Info Message Register-2: Address 3.C4E8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 link Fill Data Register-0: Address 3.C4E9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

PCS USX1 link Fill Data Register-1: Address 3.C4EA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

PCS USX1 Link FIFO Control Register: Address 3.C4EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

PCS USX1 TX FIFO Control Register: Address 3.C4EC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

PCS USX1 Local Advertisement Register: Address 3.C4ED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

PCS SERDES MUX Swap TXRX Register: Address 3.C4F0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269

PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820 . . . . . . . . . . . . . . . . . . . . 270

PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . . . . 270

PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822 . . . . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823 . . . . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit XFI0 Vendor State 1: Address 3.C860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

PCS Transmit XFI0 Vendor State 2: Address 3.C861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

PCS Transmit XFI0 Vendor State 3: Address 3.C862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

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PCS Transmit XFI0 Vendor State 4: Address 3.C863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

PCS Transmit XFI1 Vendor State 1: Address 3.C870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 2: Address 3.C871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 3: Address 3.C872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

PCS Transmit XFI1 Vendor State 4: Address 3.C873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

PCS Transmit XGS Vendor State 1: Address 3.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274

PCS Transmit XGS Vendor State 3: Address 3.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS Transmit XGS Vendor State 4: Address 3.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS Transmit XGS Vendor State 5: Address 3.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

PCS USX0 Transmit Status : Address 3.C8C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

PCS USX1 Transmit Status : Address 3.C8D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

PCS PTP Vendor State 1: Address 3.C900 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

PCS PTP Vendor State 2: Address 3.C901 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 3: Address 3.C902 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 4: Address 3.C903 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

PCS PTP Vendor State 5: Address 3.C904 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 6: Address 3.C905 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 7: Address 3.C906 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

PCS PTP Vendor State 8: Address 3.C907 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 9: Address 3.C908 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 10: Address 3.C909 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

PCS PTP Vendor State 11: Address 3.C90A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 12: Address 3.C90B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 13: Address 3.C90C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

PCS PTP Vendor State 14: Address 3.C90D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 15: Address 3.C90E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 16: Address 3.C90F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

PCS PTP Vendor State 17: Address 3.C910 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 18: Address 3.C911 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 19: Address 3.C912 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

PCS PTP Vendor State 20: Address 3.C913 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PCS PTP Vendor State 21: Address 3.C914 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PCS PTP Vendor State 22: Address 3.C915 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

PCS PTP Vendor State 23: Address 3.C916 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 24: Address 3.C917 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 25: Address 3.C918 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

PCS PTP Vendor State 26: Address 3.C919 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PCS PTP Vendor State 27: Address 3.C91A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

PCS PTP Vendor State 28: Address 3.C91B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

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PCS PTP Vendor State 29: Address 3.C91C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 31: Address 3.C91E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287

PCS PTP Vendor State 32: Address 3.C91F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 33: Address 3.C920 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 34: Address 3.C921 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

PCS PTP Vendor State 35: Address 3.C922 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Vendor State 30: Address 3.C91D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Egress Vendor State 2: Address 3.C931 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

PCS PTP Egress Vendor State 3: Address 3.C932 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

PCS PTP Egress Vendor State 4: Address 3.C933 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

PCS PTP Egress Vendor State 5: Address 3.C934 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS PTP Egress Vendor State 6: Address 3.C935 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS PTP Egress Vendor State 7: Address 3.C936 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291

PCS Transmit Vendor Alarms 1: Address 3.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

PCS Transmit Vendor Alarms 2: Address 3.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Transmit Vendor Alarms 3: Address 3.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Transmit Vendor Alarms 4: Address 3.CC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

PCS Standard Interrupt Mask 1: Address 3.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

PCS Standard Interrupt Mask 2: Address 3.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

PCS Standard Interrupt Mask 3: Address 3.D002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

PCS Transmit Vendor Interrupt Mask 1: Address 3.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296

PCS Transmit Vendor Interrupt Mask 2: Address 3.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Interrupt Mask 3: Address 3.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Interrupt Mask 4: Address 3.D403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

PCS Transmit Vendor Debug 1: Address 3.D800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

PCS Receive Vendor Provisioning 1: Address 3.E400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

PCS Receive XFI0 Provisioning 1: Address 3.E460. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

PCS Receive XFI0 Provisioning 2: Address 3.E461. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

PCS Receive XFI1 Provisioning 1: Address 3.E470. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

PCS Receive XFI1 Provisioning 2: Address 3.E471. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

PCS USX0 RX Control Register: Address 3.E4D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

PCS USX0 RX FIFO Control Register: Address 3.E4D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

PCS USX0 SM Control Register: Address 3.E4D2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

PCS USX0 Link Timer Control Register: Address 3.E4D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

PCS USX0 RX Fault Control Register: Address 3.E4D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

PCS USX1 RX Control Register: Address 3.E4E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

PCS USX1 RX FIFO Control Register: Address 3.E4E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

PCS USX1 SM Control Register: Address 3.E4E2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

PCS USX1 Link Timer Control Register: Address 3.E4E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

PCS USX1 RX Fault Control Register: Address 3.E4E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

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PCS USX1 RX Control Register: Address 3.E4E0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309

PCS PTP Ingress Vendor Provisioning 2: Address 3.E601 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311

PCS PTP Ingress Vendor Provisioning 3: Address 3.E602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312

PCS PTP Ingress Vendor Provisioning 4: Address 3.E603 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

PCS PTP Ingress Vendor Provisioning 5: Address 3.E604 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

PCS PTP Ingress Vendor Provisioning 6: Address 3.E605 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 7: Address 3.E606 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 8: Address 3.E607 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

PCS PTP Ingress Vendor Provisioning 9: Address 3.E608 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 10: Address 3.E609 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315

PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 17: Address 3.E610 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317

PCS PTP Ingress Vendor Provisioning 18: Address 3.E611 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 19: Address 3.E612 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 20: Address 3.E613 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

PCS PTP Ingress Vendor Provisioning 21: Address 3.E614 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

PCS PTP Ingress Vendor Provisioning 22: Address 3.E615 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319

PCS PTP Ingress Vendor Provisioning 23: Address 3.E616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

PCS PTP Ingress Vendor Provisioning 24: Address 3.E617 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320

PCS PTP Ingress Vendor Provisioning 25: Address 3.E618 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

PCS PTP Ingress Vendor Provisioning 26: Address 3.E619 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

PCS PTP Ingress Vendor Provisioning 33: Address 3.E620 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

PCS PTP Ingress Vendor Provisioning 34: Address 3.E621 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

PCS PTP Ingress Vendor Provisioning 35: Address 3.E622 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

PCS PTP Ingress Vendor Provisioning 36: Address 3.E623 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

PCS PTP Ingress Vendor Provisioning 37: Address 3.E624 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

PCS PTP Ingress Vendor Provisioning 38: Address 3.E625 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

PCS PTP Ingress Vendor Provisioning 39: Address 3.E626 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

PCS PTP Ingress Vendor Provisioning 40: Address 3.E627 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

PCS PTP Ingress Vendor Provisioning 41: Address 3.E628 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

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PCS Receive Vendor State 1: Address 3.E800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810. . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811. . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812 . . . . . . . . . . . . . . . . . . . . . 333

PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813 . . . . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814 . . . . . . . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815 . . . . . . . . . . . . . . . . . . . . . . . . 334

PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820 . . . . . . . . . . . . . . . . . . . . . . 335

PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821 . . . . . . . . . . . . . . . . . . . . . . 335

PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840 . . . . . . . . . . . . . . . 336

PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841 . . . . . . . . . . . . . . . 336

PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842 . . . . . . . . . . . . . . . 337

PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843 . . . . . . . . . . . . . . . 337

PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844 . . . . . . . . . . . . . . . 338

PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845 . . . . . . . . . . . . . . . 338

PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846 . . . . . . . . . . . . . . . 339

PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847 . . . . . . . . . . . . . . . 339

PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848 . . . . . . . . . . . . . . . 340

PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849 . . . . . . . . . . . . . . . 340

PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850 . . . . . . . . . . . . . . . . . 341

PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851 . . . . . . . . . . . . . . . . . 341

PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852 . . . . . . . . . . . . . . . . . 341

PCS Receive XFI0 Vendor State 1: Address 3.E860 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 2: Address 3.E861 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 3: Address 3.E862 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342

PCS Receive XFI0 Vendor State 4: Address 3.E863 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 5: Address 3.E864 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 6: Address 3.E865 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343

PCS Receive XFI0 Vendor State 7: Address 3.E866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 1: Address 3.E870 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 2: Address 3.E871 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

PCS Receive XFI1 Vendor State 3: Address 3.E872 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 4: Address 3.E873 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 5: Address 3.E874 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

PCS Receive XFI1 Vendor State 6: Address 3.E875 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

PCS Receive XFI1 Vendor State 7: Address 3.E876 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0 . . . . . . . . . . . . . . . . . . . . . . . . 346

PCS USX0 Receive Packet Info Message-0: Address 3.E8D1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Receive Packet Info Message-1: Address 3.E8D2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Receive Packet Info Message-2: Address 3.E8D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

PCS USX0 Unidata and SM status Register: Address 3.E8D4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

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PCS USX0 Receive Status Register: Address 3.E8D5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6 . . 349

PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0 . . . . . . . . . . . . . . . . . . . . . . . . 350

PCS USX1 Receive Packet Info Message-0: Address 3.E8E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Receive Packet Info Message-1: Address 3.E8E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Receive Packet Info Message-2: Address 3.E8E3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

PCS USX1 Unidata and SM status Register: Address 3.E8E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

PCS USX1 Receive Status Register: Address 3.E8E5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6 . . 353

PCS Receive Vendor Alarms 1: Address 3.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

PCS Receive Vendor Alarms 2: Address 3.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 3: Address 3.EC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 4: Address 3.EC03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 5: Address 3.EC04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

PCS Receive Vendor Alarms 6: Address 3.EC05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

PCS Receive Vendor Alarms 7: Address 3.EC06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357

PCS Receive Vendor Alarms 10: Address 3.EC09 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

PCS Receive Vendor Alarms 14: Address 3.EC0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360

PCS Receive Vendor Alarms 15: Address 3.EC0E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

PCS Receive Vendor Alarms 16: Address 3.EC0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

PCS Receive Vendor Alarms 17: Address 3.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

PCS Receive Vendor Internal Alarms : Address 3.ED0D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

PCS Receive Vendor Internal Alarms : Address 3.ED0E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

PCS Receive Vendor Internal Alarms : Address 3.ED0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

PCS Receive Vendor Internal Alarms : Address 3.ED10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371

PCS Receive Vendor Interrupt Mask 1: Address 3.F400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

PCS Receive Vendor Interrupt Mask 2: Address 3.F401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

PCS Receive Vendor Interrupt Mask 3: Address 3.F402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

PCS Receive Vendor Interrupt Mask 4: Address 3.F403 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374

PCS Receive Vendor Interrupt Mask 5: Address 3.F404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

PCS Receive Vendor Interrupt Mask 6: Address 3.F405 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375

PCS Receive Vendor Interrupt Mask 7: Address 3.F406 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

PCS Receive Vendor Debug 1: Address 3.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

PCS Vendor Global Interrupt Flags 1: Address 3.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

PCS Vendor Global Interrupt Flags 3: Address 3.FC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

PHY XS Standard Control 1: Address 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381

PHY XS Standard Status 1: Address 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

PHY XS Standard Device Identifier 1: Address 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Device Identifier 2: Address 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Speed Ability: Address 4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384

PHY XS Standard Devices in Package 1: Address 4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

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PHY XS Standard Devices in Package 2: Address 4.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

PHY XS Standard Status 2: Address 4.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386

PHY XS Standard Package Identifier 1: Address 4.E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

PHY XS Standard Package Identifier 2: Address 4.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

PHY XS EEE Capability Register: Address 4.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

PHY XS EEE Wake Error Counter: Address 4.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

PHY XS Standard XGXS Lane Status: Address 4.18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

PHY XS Standard XGXS Test Control: Address 4.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

TimeSync PHY XS Capability: Address 4.1800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801 . . . . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802 . . . . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803 . . . . . . . . . . . . . . . . . . . . . . . . . . 391

TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804 . . . . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805 . . . . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806 . . . . . . . . . . . . . . . . . . . . . . . . . . 392

TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807 . . . . . . . . . . . . . . . . . . . . . . . . . . 393

TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808 . . . . . . . . . . . . . . . . . . . . . . . . . . 393

PHY XS SERDES Configuration 1: Address 4.C180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394

PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS SERDES LUT 256: Address 4.C200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440 . . . . . . . . . . . . . . 396

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441 . . . . . . . . . . . . . . 398

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442 . . . . . . . . . . . . . . 400

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443 . . . . . . . . . . . . . . 401

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444 . . . . . . . . . . . . . . 402

PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445 . . . . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820 . . . . . . . . . . . . . . . . . . . . 405

PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821 . . . . . . . . . . . . . . . . . . . . 406

PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . 407

PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . 407

PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . 409

PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000 . . . . . . . . . . . . . . . . . . . 409

PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001 . . . . . . . . . . . . . . . . . . . 410

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PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400. . . . . . . . . . . . . . . . . . . . . 410

PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401. . . . . . . . . . . . . . . . . . . . . 411

PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402. . . . . . . . . . . . . . . . . . . . . 412

PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800 . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801 . . . . . . . . . . . . . . . . . . . . . . . . . . . 414

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810 . . . . . . . . . . . . . . . . . 415

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811 . . . . . . . . . . . . . . . . . 415

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812 . . . . . . . . . . . . . . . . . 416

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813 . . . . . . . . . . . . . . . . . 416

PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814 . . . . . . . . . . . . . . . . . 417

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410 . . . . . . . . . . . . . . . 417

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411 . . . . . . . . . . . . . . . 418

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412 . . . . . . . . . . . . . . . 419

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413 . . . . . . . . . . . . . . . 420

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414 . . . . . . . . . . . . . . . 420

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415 . . . . . . . . . . . . . . . 421

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417 . . . . . . . . . . . . . . . 422

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418 . . . . . . . . . . . . . . . 422

PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419 . . . . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423

PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424

PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810. . . . . . . . . . . . . . . . . . . . . 424

PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>:

Address 4.E812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . 427

PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400. . . . . . . . . . . . . . . . . . . . . . 428

PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401. . . . . . . . . . . . . . . . . . . . . . 429

PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

Autonegotiation Standard Control 1: Address 7.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Autonegotiation Standard Status 1: Address 7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434

Autonegotiation Standard Device Identifier 1: Address 7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Autonegotiation Standard Device Identifier 2: Address 7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435

Autonegotiation Standard Devices in Package 1: Address 7.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

Autonegotiation Standard Devices in Package 2: Address 7.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

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Autonegotiation Standard Status 2: Address 7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

Autonegotiation Standard Package Identifier 1: Address 7.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Autonegotiation Standard Package Identifier 2: Address 7.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Autonegotiation Advertisement Register: Address 7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Autonegotiation Link Partner Base Page Ability Register: Address 7.13 . . . . . . . . . . . . . . . . . . . . . 440

Autonegotiation Extended Next Page Transmit Register: Address 7.16 . . . . . . . . . . . . . . . . . . . . . 442

Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17 . . . . . . . . . . . . 443

Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18 . . . . . . . . . . . . 443

Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19 . . . . . . . . . . . . . 443

Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A . . 444

Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B . . 445

Autonegotiation 10GBASE-T Control Register: Address 7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Autonegotiation 10GBASE-T Status Register: Address 7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446

Autonegotiation EEE Advertisement Register: Address 7.3C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Autonegotiation EEE Link Partner Ability Register: Address 7.3D . . . . . . . . . . . . . . . . . . . . . . . . . . 448

KR0 Autonegotiation Control: Address 7.C200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

KR0 Autonegotiation Status: Address 7.C201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

KR0 Autonegotiation Advertisement Word 1: Address 7.C210. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452

KR0 Autonegotiation Advertisement Word 2: Address 7.C211. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

KR0 Autonegotiation Advertisement Word 3: Address 7.C212. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454

KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213 . . . . . . . . . . . . . . . . . . 454

KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214 . . . . . . . . . . . . . . . . . . 456

KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215 . . . . . . . . . . . . . . . . . . 457

KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216. . . . . . . . . . . . 457

KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217. . . . . . . . . . . . 458

KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218. . . . . . . . . . . . 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219 . 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A . 458

KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B . 459

KR1 Autonegotiation Control: Address 7.C300. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

KR1 Autonegotiation Status: Address 7.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

KR1 Autonegotiation Advertisement Word 1: Address 7.C310. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

KR1 Autonegotiation Advertisement Word 2: Address 7.C311. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462

KR1 Autonegotiation Advertisement Word 3: Address 7.C312. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463

KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313 . . . . . . . . . . . . . . . . . . 463

KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314 . . . . . . . . . . . . . . . . . . 465

KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315 . . . . . . . . . . . . . . . . . . 466

KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316. . . . . . . . . . . . 466

KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317. . . . . . . . . . . . 467

KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318. . . . . . . . . . . . 467

KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319 . 467

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KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A . 467

KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B . 468

Autonegotiation Vendor Provisioning 1: Address 7.C400. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468

Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410 . . . . . . . . . . . . . . . . . . . . . . . . 470

Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411 . . . . . . . . . . . . . . . . . . . . . . . . 472

Autonegotiation Vendor Status 1: Address 7.C800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

Autonegotiation Reserved Vendor Status 1: Address 7.C810 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Autonegotiation Reserved Vendor Status 2: Address 7.C811 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

Autonegotiation Reserved Vendor Status 3: Address 7.C812 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Reserved Vendor Status 4: Address 7.C813 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Reserved Vendor Status 5: Address 7.C814 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

Autonegotiation Standard Interrupt Mask 1: Address 7.D000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

Autonegotiation Standard Interrupt Mask 2: Address 7.D001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400 . . . . . . . . . . . . . . . . . . . . . . . 479

Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401 . . . . . . . . . . . . . . . . . . . . . . . 480

Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402 . . . . . . . . . . . . . . . . . . . . . . . 480

Autonegotiation Receive Link Partner Status 1: Address 7.E820 . . . . . . . . . . . . . . . . . . . . . . . . . . 481

Autonegotiation Receive Link Partner Status 2: Address 7.E821 . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Link Partner Status 3: Address 7.E822 . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Link Partner Status 4: Address 7.E823 . . . . . . . . . . . . . . . . . . . . . . . . . . 482

Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830 . . . . . . . . . . . . . . . . . . . . . . 483

Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831 . . . . . . . . . . . . . . . . . . . . . . 483

Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832 . . . . . . . . . . . . . . . . . . . . . . 484

Autonegotiation Receive Vendor Alarms 1: Address 7.EC00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484

Autonegotiation Receive Vendor Alarms 2: Address 7.EC01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Autonegotiation Receive Vendor Alarms 3: Address 7.EC02. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

Autonegotiation Receive Vendor Alarms 4: Address 7.EC03. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400 . . . . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401 . . . . . . . . . . . . . . . . . . . . . . . . 486

Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402 . . . . . . . . . . . . . . . . . . . . . . . . 487

Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403 . . . . . . . . . . . . . . . . . . . . . . . . 487

Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . 488

GbE Standard Device Identifier 1: Address 1D.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Device Identifier 2: Address 1D.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Devices in Package 1: Address 1D.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491

GbE Standard Vendor Devices in Package 2: Address 1D.6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492

GbE Standard Status 2: Address 1D.8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

GbE Standard Package Identifier 1: Address 1D.E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

GbE Standard Package Identifier 2: Address 1D.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

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GbE PHY SGMII Test Control : Address 1D.C282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

GbE PHY WoL Control 1: Address 1D.C300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

GbE PHY WoL Control 2: Address 1D.C301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 3: Address 1D.C302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 4: Address 1D.C303 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 5: Address 1D.C304 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495

GbE PHY WoL Control 6: Address 1D.C305 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

GbE PHY WoL Control 7: Address 1D.C306 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496

GbE PHY WoL Control 9: Address 1D.C308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 10: Address 1D.C309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 11: Address 1D.C30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497

GbE PHY WoL Control 12: Address 1D.C30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 13: Address 1D.C30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 14: Address 1D.C30D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

GbE PHY WoL Control 15: Address 1D.C30E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 16: Address 1D.C30F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 17: Address 1D.C310 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

GbE PHY WoL Control 18: Address 1D.C311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 19: Address 1D.C312 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 20: Address 1D.C313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500

GbE PHY WoL Control 21: Address 1D.C314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 22: Address 1D.C315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 23: Address 1D.C316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

GbE PHY WoL Control 24: Address 1D.C317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

GbE PHY WoL Control 25: Address 1D.C318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

GbE PHY WoL Control 26: Address 1D.C319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

GbE PHY WoL Control 27: Address 1D.C31A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 28: Address 1D.C31B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 29: Address 1D.C31C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503

GbE PHY WoL Control 30: Address 1D.C31D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 31: Address 1D.C31E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 32: Address 1D.C31F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504

GbE PHY WoL Control 33: Address 1D.C320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 34: Address 1D.C321 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 35: Address 1D.C322 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505

GbE PHY WoL Control 36: Address 1D.C323 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 37: Address 1D.C324 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 38: Address 1D.C325 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506

GbE PHY WoL Control 39: Address 1D.C326 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

GbE PHY WoL Control 40: Address 1D.C327 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

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GbE PHY WoL Control 41: Address 1D.C328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507

GbE PHY WoL Control 42: Address 1D.C329 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 43: Address 1D.C32A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 44: Address 1D.C32B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508

GbE PHY WoL Control 45: Address 1D.C32C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 46: Address 1D.C32D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 47: Address 1D.C32E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509

GbE PHY WoL Control 48: Address 1D.C32F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 49: Address 1D.C330 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 50: Address 1D.C331 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510

GbE PHY WoL Control 51: Address 1D.C332 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 52: Address 1D.C333 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 53: Address 1D.C334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

GbE PHY WoL Control 54: Address 1D.C335 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 55: Address 1D.C336 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 56: Address 1D.C337 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

GbE PHY WoL Control 57: Address 1D.C338 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 58: Address 1D.C339 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 59: Address 1D.C33A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

GbE PHY WoL Control 60: Address 1D.C33B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 1: Address 1D.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 2: Address 1D.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

GbE PHY Extended WoL Control 3: Address 1D.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 4: Address 1D.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 5: Address 1D.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

GbE PHY Extended WoL Control 6: Address 1D.C425 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 7: Address 1D.C426 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 8: Address 1D.C427 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

GbE PHY Extended WoL Control 9: Address 1D.C428 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 10: Address 1D.C429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 11: Address 1D.C42A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517

GbE PHY Extended WoL Control 12: Address 1D.C42B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 13: Address 1D.C42C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 14: Address 1D.C42D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518

GbE PHY Extended WoL Control 15: Address 1D.C42E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 16: Address 1D.C42F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 17: Address 1D.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

GbE PHY Extended WoL Control 18: Address 1D.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

GbE PHY Extended WoL Control 19: Address 1D.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

GbE PHY Extended WoL Control 20: Address 1D.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

GbE PHY Extended WoL Control 21: Address 1D.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

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GbE PHY Extended WoL Control 22: Address 1D.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

GbE PHY Extended WoL Control 23: Address 1D.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

GbE PHY Extended WoL Control 24: Address 1D.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 25: Address 1D.C438 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 26: Address 1D.C439 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

GbE PHY Extended WoL Control 27: Address 1D.C43A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 28: Address 1D.C43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 29: Address 1D.C43C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523

GbE PHY Extended WoL Control 30: Address 1D.C43D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

GbE Reserved Provisioning 1: Address 1D.C500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

GbE Reserved Provisioning 2: Address 1D.C501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525

GbE PHY SGMII1 Rx Status 1: Address 1D.D280 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526

GbE PHY SGMII1 Rx Status 2: Address 1D.D281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527

GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 7: Address 1D.D286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

GbE PHY SGMII1 Rx Status 8: Address 1D.D287 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

GbE PHY SGMII1 Rx Status 9: Address 1D.D288 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529

GbE PHY SGMII0 Rx Status 1: Address 1D.D290 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

GbE PHY SGMII0 Rx Status 2: Address 1D.D291 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

GbE PHY SGMII0 Rx Status 3: Address 1D.D292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

GbE PHY SGMII0 Rx Status 4: Address 1D.D293 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 5: Address 1D.D294 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 6: Address 1D.D295 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

GbE PHY SGMII0 Rx Status 7: Address 1D.D296 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII0 Rx Status 8: Address 1D.D297 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII0 Rx Status 9: Address 1D.D298 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

GbE PHY SGMII1 WoL Status: Address 1D.D302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

GbE PHY SGMII1 Rx Status 3: Address 1D.D282 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Rx Status 4: Address 1D.D283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Rx Status 5: Address 1D.D284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535

GbE PHY SGMII1 Rx Status 6: Address 1D.D285 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 5: Address 1D.D307 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 6: Address 1D.D308 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

GbE PHY SGMII1 Tx Status 7: Address 1D.D309 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 8: Address 1D.D30A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 9: Address 1D.D30B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

GbE PHY SGMII1 Tx Status 10: Address 1D.D30C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

SGMII0 WoL Status : Address 1D.D312. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

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GbE PHY SGMII0 Tx Status 1: Address 1D.D313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

GbE PHY SGMII0 Tx Status 2: Address 1D.D314 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 3: Address 1D.D315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 4: Address 1D.D316 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539

GbE PHY SGMII0 Tx Status 5: Address 1D.D317 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 6: Address 1D.D318 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 7: Address 1D.D319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540

GbE PHY SGMII0 Tx Status 8: Address 1D.D31A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

GbE PHY SGMII0 Tx Status 9: Address 1D.D31B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

GbE PHY SGMII0 Tx Status 10: Address 1D.D31C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541

GbE PHY SGMII WoL Status: Address 1D.D322. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

GbE PHY SGMII Rx Alarms 1: Address 1D.EC10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

GbE PHY SGMII Tx Alarms 1: Address 1D.EC20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544

GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545

GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547

Global Standard Control 1: Address 1E.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Global Standard Device Identifier 1: Address 1E.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549

Global Standard Device Identifier 2: Address 1E.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Global Standard Devices in Package 1: Address 1E.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550

Global Standard Vendor Devices in Package 2: Address 1E.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551

Global Standard Status 2: Address 1E.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Standard Package Identifier 1: Address 1E.E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Standard Package Identifier 2: Address 1E.F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

Global Firmware ID: Address 1E.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Global NVR Interface 1: Address 1E.100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553

Global NVR Interface 2: Address 1E.101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

Global NVR Interface 3: Address 1E.102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Global NVR Interface 4: Address 1E.103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

Global NVR Interface 5: Address 1E.104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

Global NVR Interface 6: Address 1E.105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Global Mailbox Interface 1: Address 1E.200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

Global Mailbox Interface 2: Address 1E.201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558

Global Mailbox Interface 3: Address 1E.202 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 4: Address 1E.203 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 5: Address 1E.204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

Global Mailbox Interface 6: Address 1E.205 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Mailbox Interface 7: Address 1E.206 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Microprocessor Scratch Pad 1: Address 1E.300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

Global Microprocessor Scratch Pad 2: Address 1E.301 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Global Control 1: Address 1E.C000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

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Global Control 2: Address 1E.C001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

Global Reset Control: Address 1E.C006 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Global Diagnostic Provisioning: Address 1E.C400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562

Global Thermal Provisioning 1: Address 1E.C420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Global Thermal Provisioning 2: Address 1E.C421 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

Global Thermal Provisioning 3: Address 1E.C422 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

Global Thermal Provisioning 4: Address 1E.C423 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

Global Thermal Provisioning 5: Address 1E.C424 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Global LED Provisioning 1: Address 1E.C430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

Global LED Provisioning 2: Address 1E.C431 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

Global LED Provisioning 3: Address 1E.C432 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

Global LED Provisioning 4: Address 1E.C433 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

Global LED Provisioning 5: Address 1E.C434 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 6: Address 1E.C435 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 7: Address 1E.C436 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 8: Address 1E.C437 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

Global LED Provisioning 15: Address 1E.C43E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Global General Provisioning 1: Address 1E.C440 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Global General Provisioning 2: Address 1E.C441 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

Global General Provisioning 3: Address 1E.C442 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

Global General Provisioning 4: Address 1E.C443 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 5: Address 1E.C444 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 6: Address 1E.C445 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 7: Address 1E.C446 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

Global General Provisioning 8: Address 1E.C447 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global General Provisioning 9: Address 1E.C448 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global General Provisioning 10: Address 1E.C449 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

Global NVR Provisioning 1: Address 1E.C450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

Global NVR Provisioning 2: Address 1E.C451 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Global NVR Provisioning 3: Address 1E.C452 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578

Global NVR Provisioning 4: Address 1E.C453 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579

Global Reserved Provisioning 1: Address 1E.C470 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580

Global Reserved Provisioning 2: Address 1E.C471 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

Global Reserved Provisioning 3: Address 1E.C472 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582

Global Reserved Provisioning 4: Address 1E.C473 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583

Global Reserved Provisioning 5: Address 1E.C474 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Global Reserved Provisioning 6: Address 1E.C475 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584

Global Reserved Provisioning 9: Address 1E.C478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Global Reserved Provisioning 10: Address 1E.C479 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

Global Reserved Provisioning 11: Address 1E.C47A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

Global Reserved Provisioning 12: Address 1E.C47B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

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PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C . . . . . . . . . . . . . . . . 591

PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D . . . . . . . . . . . . . . . . 591

PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E . . . . . . . . . . . . . . . . 592

PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F . . . . . . . . . . . . . . . . 592

Global SMBus 0 Provisioning 6: Address 1E.C485 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global SMBus 1 Provisioning 6: Address 1E.C495 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global EEE Provisioning 1: Address 1E.C4A0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

Global Cable Diagnostic Status 1: Address 1E.C800. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594

Global Cable Diagnostic Status 2: Address 1E.C801. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

Global Cable Diagnostic Status 3: Address 1E.C802. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 4: Address 1E.C803. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 5: Address 1E.C804. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596

Global Cable Diagnostic Status 6: Address 1E.C805. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Cable Diagnostic Status 7: Address 1E.C806. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Cable Diagnostic Status 8: Address 1E.C807. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

Global Thermal Status 1: Address 1E.C820. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global Thermal Status 2: Address 1E.C821. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global General Status 1: Address 1E.C830 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598

Global General Status 2: Address 1E.C831 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601

Global Pin Status: Address 1E.C840 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Global Daisy Chain Status 2: Address 1E.C842 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

Global Fault Message: Address 1E.C850 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603

Global Cable Diagnostic Impedance 1: Address 1E.C880 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

Global Cable Diagnostic Impedance 2: Address 1E.C881 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

Global Cable Diagnostic Impedance 3: Address 1E.C882 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606

Global Cable Diagnostic Impedance 4: Address 1E.C883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

Global Status: Address 1E.C884 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609

Global Reserved Status 1: Address 1E.C885 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Global Reserved Status 2: Address 1E.C886 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

Global Reserved Status 3: Address 1E.C887 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611

Global Reserved Status 4: Address 1E.C888 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

Global Alarms 1: Address 1E.CC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

Global Alarms 2: Address 1E.CC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

Global Alarms 3: Address 1E.CC02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

Global Interrupt Mask 1: Address 1E.D400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

Global Interrupt Mask 2: Address 1E.D401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

Global Interrupt Mask 3: Address 1E.D402 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

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Overview 1-

1.1 Introduction

The AQR405 is a quad port 28 nm CMOS 10GBASE-T / 5G / 2.5G / 1000BASE-T

/ 100BASE-TX five-speed PHY that is designed to be a low-power, stand-alone

solution for all NIC, switch, and LAN-on-Motherboard applications that require

10GBASE-T capability.

This chapter is intended to provide an overview of the AQR405 and its operating

modes.

1.2 General Deployment

This section briefly touches on the hardware implementation. For more detailed

hardware design information, please see the Hardware Design Guide[13].

1.2.1 Mechanical

The AQR405 is packaged in a 25 mm x 25 mm flip-chip 576 pin BGA (24 rows x

24 rows). Consequently, the is a low 0.42°C/W. Meanwhile, the die is rated to

operate up to 105°C junction temperature, so engineering an appropriate thermal

solution for the target system is a straightforward task.

1.2.2 Power Supplies

The AQR405 utilizes three power supplies: a 0.85V digital supply (VDD), and 1.2V

and 2.1V analog supplies (VA12 and VA22 respectively). All supplies should come

up within 100ms from the first rail rising to the last rail reaching its 70% voltage

level. The power up sequence requires that the VDD and 1.2V rails reach their

nominal voltage levels in any order first and then followed by the other power rails

in any order. The same order must be followed for power down sequence.

For the I/O, the AQR405 offers a separate VDD_IO supply, which will set the logic

thresholds for the I/O at 70% / 30% of its voltage. In addition to the VDD_IO supply

voltages of 2.1V and 2.5V, a separate control pin (MDIO_1P2_SELECT_N when

pulled low) allows pins MDC, MDIO, INT_N, and RST_N to operate at 1.2V logic

levels, regardless of the voltage on VDD_IO.

AVSS, VSS, and VSS_SRDS must be tied to the same ground plane.

1.2.3 Reset

The AQR405 supports on-chip power-on reset generation and it is also capable of

supplying this reset to the rest of the system via a RST_OUT_N pin.

θjc

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1.2.4 Clocks

The AQR405 uses a 50 MHz differential clock to synthesize all of the required

clocks. For Synchronous Ethernet (Sync-E) applications, the AQR405 is capable

of outputting to the system primary and secondary 50 MHz clocks phase-locked to

the line clocks of any of the PHYs in the package.

1.2.5 FLASH

The AQR405 is capable of operating with a 512 KByte (4 Mbit) or larger SPI serial

FLASH for autonomous operation, or of being boot-loaded via the MDIO interface.

In both cases, the image stored in FLASH and the MDIO boot-load image are

identical. If autonomous operation is not a requirement, and the target system is

capable of providing the boot-load image, the FLASH can be eliminated. To support

configurations such as switches, where multiple PHYs are deployed on the same

board, a daisy-chain mechanism exists within the PHY that allows one FLASH

device to contain the images for all of the PHYs. The PHY with the FLASH device

is designated as being the daisy-chain master, and it broadcasts the image to all of

the other PHYs using a serial bus.

For the FLASH I/O, the AQR405 offers a separate VDD_FLASH supply that is used

to run the FLASH interface. VDD_FLASH requires 2.5V.

If boot-loading is desired, it is possible to gang-load multiple parts via a broadcast

MDIO address in the AQR405.

1.2.6 Power-on Default Values

The AQR405 has a fixed set of hardware default values that exist in the chip for all

configurable registers. However, the firmware is capable of storing in its boot image

any change to these defaults for up to 48 PHYs within a single image, effectively

allowing the user to configure the chip to come out of reset in the desired operating

state. This can be done by using the Aquantia web-provisioning tool to alter the

boot image.

1.2.7 SERDES Configuration

The AQR405 is capable of routing any logical SERDES lane to any physical

SERDES lane, as well as performing polarity inversions†. On the line side, in

addition to supporting MDI / MDI-X and automatic polarity correction, the AQR405

supports lane swapping of the ABCD pairs to enable easy board routing with

different magnetics pin-outs.

†Note that polarity inversion is also referred to as “Lane Invert” in the register map.

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1.3 SERDES

The AQR405 is designed to be used in conjunction with a five-speed MAC chip.

The AQR405’s interface to the system for 10G operation is KR and RXAUI, and for

1G / 100M operation is SGMII / USXGMII on SERDES logical Lane 0†. The

AQR405 is capable of being configured so that the MAC interface can start in one

of the following modes:

1) Start with the 10G interface on (KR, RXAUI).

2) Start with the 1000BASE-X interface on (SGMII without autonegotiation).

3) Start with extended SGMII autonegotiation (USXGMII)‡ enabled.

4) Start with all interfaces off.

Once a connection to a link partner has been established, the interface will then

switch to the correct MAC interface speed. More information on this can be found

in Section 2.5

1.4 Power-On

The AQR405 is designed to perform the following operations at boot:

1) Power-up calibration of internal VCOs and variable power supplies (if

variable supply operation is enabled)

2) Provision stored default values*

3) Calibration of the analog front-end

4) Autonegotiation

5) Perform training (as required)

†Note that the AQR405 internally has 4 SERDES per PHY, but only physical Lanes 0 and

2 are connected. Consequently, the register map contains information for XAUI and for

Lanes 1 and 3, but these cannot be used in the AQR405.

‡Note that USXGMII operation and autonegotiation is identical to SGMII operation and

autonegotiation when 2.5G/5G/10G operation is not enabled.

*The AQR405 is capable of storing in its firmware image a list of registers whose default

values should be overwritten with a user-specified value on power up. This is done using

the web-based Aquantia Firmware Provisioning Tool, and allows the PHY to be person-

alized for certain modes of operation.

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6) Verify error-free operation

7) Enter steady state

1.5 Cable Diagnostics

The AQR405 implements a powerful cable diagnostic algorithm to accurately

measure all of the TDR and TDT† sequences within the group of four channels.

The algorithm used transmits a pseudo-noise sequence with an amplitude of less

than 300 mV for a brief period of time, and from this converges the 10GBASE-T

equalizers on all of the other channels. From the results of this measurement, the

length of each pair, the top impairment along the pair, and the impedance of the

cable are flagged. These measurements are reported to an accuracy to ±1m using

a cable propagation characteristics[11] of 4.83 ns/m and are presented in the

Global MMD register map.

1.6 Wake-On-LAN

The AQR405 has an integrated Wake-On-LAN filter compliant to the Microsoft

Network Device Class Version 2.0 specification[9]. This filter is capable of detecting

a wake-up sequence / frame in 100BASE-TX and 1000BASE-T mode and driving

a WAKE signal high upon receiving the appropriate magic packet or magic frame.

In this mode, the AQR405 operating power in 100BASE-TX mode is less than 1W,

with only the MDIO interface and the receive 100 Mb/s interface operational.

The AQR405 can support up to 8 programmable magic frame types. Each frame

type has a 128-bit mask field that corresponds to the first 128 bytes of the wakeup

frame and a programmable CRC-32‡. This CRC-32 is calculated over the selected

bytes in the frame and is used as a signature to determine reception of a magic

packet. Each bit selects whether the corresponding byte is included in the CRC-32.

To support magic packets, the AQR405 will hunt for an occurrence of the

synchronization stream, which is defined by 6 bytes of 0xFF. Then it will check to

see if this sequence is followed by 16 duplications of a programmable MAC

address.

1.7 Debug and Diagnostics Tools

The AQR405 supports a full suite of network and system loopbacks at all three

rates. The loopbacks are shown below.

†The cross-channel impulse responses.

‡The CRC-32 chosen is the same one that is used for the Ethernet packet frame check

sequence (i.e. CCITT-32) in the 802.3 standard[3].

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In addition to the loopbacks, the AQR405 supports CRC-32 packet checking on

both the receive and transmit traffic at all three rates, and maintains 1 second

interval packet counters for both errored and good packets.

Finally, the AQR405 is able to generate all of the IEEE test mode patterns, as well

as CRPAT generation and checking in both line and system directions. It also

supports (via the API) the ability to generate an eye diagram for each of the receive

lanes.

RXAUI and On the KR interfaces, the AQR405 supports x9, x31, square wave, and

pseudo-noise generation and checking, as well as CRPAT generation and

checking.

1.8 API & Programming Tools

Associated with the AQR405 are the following software tools:

Figure 1.1 Loopbacks

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

Hybrid

MDIO

Management

MDIO MDIO

Registers

AQRate 25mm Quad

THP

Precoder

THP

Precoder

THP

Precoder

DAC /

Driver

A/D

THP

Precoder

THP

Precoder

A/D

VGA &

Filter

THP

Precoder

THP

Precoder

VGA &

Filter

DSP

SERDES

SRDS0

10G

SRDS2

10G

System I/F

LINE

MACSEC

5G PCS

1G PCS

100M PCS

KR/USXGMII

PCS 1

SGMII

PCS 1

SGMII

PCS 0

KR/USXGMII

PCS 0

10G PCS

2.5G PCS

XAUI/RXAUI

PCS

System Interface – System Loopback

PCS Loopback

System Interface – Network Loopback

PHY-XS Loopback

System Interface – Network Loopback

PMA Loopback

A-B / C-D Cable Loopback

Network Interface – Network Loopback

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1) A set of ANSI C register structures for each MMD that provide bit level

and word level access to all of the AQR405 registers. Documentation for

these structures are found in the API document[12].

2) An ANSI C API that provides a set of structures and associated Set / Get

functions to implement all normal PHY operations. This API is written

with register name abstraction so the registers are visible, and it is

documented using Doxygen, which allows users to view the code and

click on a variable to get the datasheet definition. This API also contains

functions to burn new FLASH images, as well as perform MDIO

boot-load operations, etc. Documentation for this is found in the API

document[12].

1.9 MACsec

The AQR405 supports integrated MACsec at all rates. It supports two modes of

operation:

1) Autonomous Operation: In this mode, the AQR405 does all of the gap

insertion, etc. required to add the MACsec headers and integrity check

values (ICVs). It does this via two integrated MACs and 64KB of buffering

in each direction. These MACs monitor the buffer fill-depths, and

generates port-based PAUSE frames in either direction as required. It

also responds to port-based PAUSE frames. 802.1Qbb class-based

PAUSE frames are passed through.

2) Cut-through Operation: In this mode, the AQR405 expects to receive

packets from the system pre-gapped, and all the AQR405 does is insert

the MACsec headers and ICVs.

3) Bypass Operation: In this mode the MACsec block is completely

bypassed, in scenarios where MACsec in the PHY is not necessary.

1.9.1 General Features

The MACsec supports the following general features:

1) AES-256, AES-128, and clear operation with simultaneous mixed usage,

where the encryption and decryption are decided on a per-packet basis

based on an access control list (ACL) that looks either at the MACsec

header or fields in the packet header (explicit or implicit secure channel

identification).

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2) 16 secure channels (SCs), with two security associations (SAs) per SC

with automatic roll-over between SAs on a programmable packet

number (PN) value.

3) Full support of the 802.1AE[7] MIB

4) Per packet Galois counter mode (GCM) authentication on the ICV (16 or

32 byte).

5) Strict and out-of-order replay checking with a per SC programmable

32-bit (i.e from 0 to 231-1 packets) replay window for out-of-order mode.

6) A programmable confidentiality offset per SA of between 0 and 127 bytes

offset.

7) A MIB containing the following additional statistics counters:

Per SA Name Description

Ingress Control Packets The number of ingress control

packets received

Ingress Untagged Hit Packets The number of ingress untagged

packets received that passed the

implicit SCI lookup

Ingress Untagged Miss Packets The number of ingress untagged

packets received that had no

implicit SCI lookup

Ingress Hit Packets Dropped The number of ingress packets that

passed the SCI lookup, but were

tagged for Drop

Ingress Tagged Packets The number of ingress packets

with a MACsec header

Ingress Tagged Packets Bad Tag The number of ingress packets

with an invalid SecTag or packet

number (PN).

Ingress Tagged Packets SCI Miss The number of ingress tagged

packets with a missing SCI or an

SCI that was not in the table.

Ingress Tagged Packets

Non-Operational SA

The number of ingress packets

with an identified, but

non-operational SA.

Table 1.1 Additional ingress MACsec statistics

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1.9.2 Ingress Lookup

On ingress, the MACsec block can:

1) Remove the MACsec header

2) Strip zero-padded bytes for runt packets

3) Corrupt the FCS for any failed packets

Ingress Packets Authentication

Fail

The number of ingress packets that

fail authentication

Ingress Packets Replay Fail The number of ingress packets that

fail the replay check

Ingress Packets Late The number of ingress packets that

fail the replay check because they

are late

Ingress Packets OK The number of ingress packets that

pass all checks

Ingress Reserved Counter 0

Ingress Reserved Counter 1

Ingress Reserved Counter 2

Ingress Reserved Counter 3

Per SA Name Description

Egress Control Packets The number of egress control

packets transmitted

Egress Packets Unknown SA The number of egress packets

transmitted with an unknown SA

(Table Miss and Untagged)

Egress Untagged Packets The number of egress packets

transmitted without a MACsec

header

Egress Protected Packets The number of egress packets

transmitted with a valid ICV

(authenticated + encrypted)

Table 1.2 Additional egress MACsec statistics

Per SA Name Description

Table 1.1 Additional ingress MACsec statistics

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4) Run a consistency check against another ACL

5) Count control packets

6) Enforce maximum MTU sizes via either truncation or FCS corruption.

7) Generate an interrupt on security failure

8) Lookup up the implicit SCI based on the following fields:

a) MAC DA - 48 bits

b) MAC SA - 48 bits

c) Payload Ether-Type - 16 bits

d) QTAG_VLD and STAG_VLD (Ingress Consistency Check only)

e) TCI / AN - 8 bits (Note TCI needs preprocessing as per Clause

9.1.2)

f) SCI - 64 bits

g) VLAN - 12 bits (Ingress Consistency Check only)

h) Any four programmable bytes within the first 64 bytes of the packet

i) Origin (loopback versus front panel) - ingress table only

j) Valid bit

9) Lookup up the implicit SCI based on the following fields:

The MACsec block for the AQR405 shall support the ability to calculate

the Ethertype, VLAN, and User-Priority of a packet using a 32 bit

mapping table that is provided with each entry in the SCI lookup. There

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is one mapping table per port. The mapping table contains the following

fields:

Ethertype, VLAN, and User-Priority of a packet are determined as follows

(using this mapping table):

Bit Name Function

31 PARSE_QTAG Enable parsing 802.1Q VLAN tags

30 PARSE_STAG Enable parsing 802.1Q MST tags

29 PARSE_QINQ Enable Q-in-Q parsing

28 QTAG_UP_EN Enable the use of the 802.1Q

priority

27 STAG_UP_EN Enable the use of the 802.1S

priority

26:24 DEF_UP Default user-priority

23:0 MAP_TBL Priority mapping for 802.1Q priority

tags

Table 1.3 “Per SCI” 32-bit mapping table

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a) Ethertype and VLAN resolution is determined as shown in Figure

1.2. Here the 802.1S and 802.1Q EtherTypes are provisionable per

port.

b) User priority is resolved as shown in Figure 1.3:

10)Support a provisioned definition of the 802.1Q and 802.1S Ethertype

tags.

11)Support the following actions from the SCI lookup:

a) Decrypt / Authenticate (provisioned per SA)

b) Drop

Figure 1.2 Ethertype and VLAN parsing algorithm

(ETH_TYP == 802.1Q)

&& PARSE_QTAG

QTAG_VLD = 1

TMP_UP = 802.1Q PCP

VLAN = 802.1Q VID

ETH_TYP = Next Ethertype

STAG_VLD = 1

TMP_UP = 802.1Q PCP

VLAN = 802.1Q VID

ETH_TYP = Next Ethertype

(ETH _TYP == 802.1S)

&& PARSE_STAG

Yes

Done

((ETH_TYP == 802.1S)

&& PARSE_STAG) ||

((ETH_TYP == 802.1Q)

&& PARSE_QTAG)

Done

ETH_TYP = Next Ethertype

Done

((ETH_TYP == 802.1S)

&& PARSE_STAG) ||

((ETH_TYP == 802.1Q)

&& PARSE_QTAG)

Done

ETH_TYP = Next Ethertype

Done

ETH_TYP = Ethertype

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c) Bypass

d) Re-direct (capture to debug)

12)Support globally changing the action for the lookup on a table basis (for

allowing rapid debug).

1.9.3 MACsec Ingress Post-Processing

After decryption during post-processing, the MACsec block can:

1) Remove or leave the MACsec header

2) Over-write the PN field of the MACsec header with provisionable data

when operating in MACsec header non-removal mode.

3) Strip zero-padding bytes from the packet according to the MACsec

header short-length (SL) field.

4) Grow short packets that are not SL stripped back to 64-bytes (i.e.

MACsec packet is >= 64 bytes, but after removal of the MACsec, the

packet is sub-64 bytes).

5) Support the corruption of the FCS on packets which fail any enabled

security check in both the ingress and egress directions.

6) Support a 32 entry per port consistency check after decryption based on:

Figure 1.3 User priority resolution

STAG_VLD &&

S TAG _U P_ EN

Yes

QTAG_VLD &&

QTAG_UP_EN

Yes

UP = MAP_TBL >> (3*TMP_UP) & 0x7

Done

UP = TMP_UP

Done

UP = DEF_UP

Done

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a) SAI_HIT

b) SAI[3:0]

c) VLAN[11:0]

d) VLAN_VLD

e) ETYPE_VLD (Ethertype > Programmable max length)

f) Payload Ethertype[15:0]

g) Each of these fields shall be maskable and have a single action bit

indicating whether to drop the packet or not.

h) The port shall also support a 33rd entry indicating what to do with

a miss.

7) Generate an interrupt on security failure

1.9.4 Egress Processing

On egress, the MACsec block can:

1) Support the same lookup and mapping mechanism as is used in the

ingress direction.

2) Support the ability to perform lookup with and without the presence of a

MACsec header.

3) Zero pad short packets and mark the SL field in the MACsec header

accordingly.

4) Fill in the remainder of the MACsec header, given provided TCI and SL

fields. This means that the MACsec EtherType (88_E5), AN, PN, and

optional SCI are filled in by the PHY.

5) Support the following actions from the SCI lookup:

a) Encrypt / Authenticate (provisioned per SA)

b) Drop

c) Bypass

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d) Re-direct (loopback or capture to debug)

6) Count control packets

7) Enforce maximum MTU sizes via either truncation or FCS corruption.

8) Support globally changing the action for the lookup on a table basis (for

allowing rapid debug).

9) Generate an interrupt on security failure

1.9.5 MACs

The MACs in the MACsec block can:

1) Support ingress and egress MIBs with per-Ethertype 40-bit counters and

RMONs (packet drop and packet pass-through).

2) In store-and-forward mode shall support port-based PAUSE flow-control

in both directions, with programmable thresholds and hysteresis.

3) Ignore 802.1Qbb class-based PAUSE frames and pass them through the

PHY.

4) Support programmable ingress and egress inter-packet gap (IPG) of

between 4 and 63 bytes†.

5) Support processor access to the MAC buffers for debug.

6) Support the ability to recognize control packets via the following criteria:

a) MAC_DA[47:4] = 01_80_C2_00_00_0

b) MAC_DA[47:4] = 01_00_0C_CC_CC_CC

c) 8 per port programmable MAC_DA addresses

d) 8 per port programmable Ethertype matches

e) 1 per port programmable MAC_DA with Don’t Care mask

†With each packet having a fixed 7-byte preamble and 1-byte start-of frame delimiter

(SFD).

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f) 2 sets of per port programmable MAC_DA and Ethertype

combinations

These shall be provisionable on a port by port basis.

7) Support sending and receiving up to 512 byte packets in both the ingress

and egress directions.

Both the ingress and egress ports shall each support a programmable

MAC address, and the ability to disable operation of these ports.

8) Support a non-destructive L2 system loopback, with a programmable

MAC address and an enable. This loopback FIFO shall be 512 bytes in

size and shall support head and tail drop (provisionable). This FIFO shall

be capable of being stopped at any time (on a packet by packet

granularity) and the packet(s) within read out. The depth of this FIFO

shall be programmable. Packets larger than a programmable size can be

dropped or truncated (programmable). Packets which are dropped due

to overflow must be counted on a per SA basis using an 8-bit counter

(saturating, clear-on-read). These looped-back packets must be

accounted for in a similar set of counters to the ingress MAC, as they are

not accounted for there (i.e. loopback after ingress MAC).

9) Enforcing a per priority, programmable maximum MTU size with an

option for either truncation or FCS corruption.

10)Support the following statistics on ingress and egress:

Egress Ingress Per

Priority

Name Description

 Total Packets The total number of packets (good

+ bad)

Total Packets (per priority) The total number of packets (good

+ bad) (per priority)

 Dropped Packets Packets dropped for any reason

Dropped Packets (per priority) Packets dropped for any reason

(per priority)

 Bytes Total frame octets

Bytes (per priority) Total frame octets (per priority)

Table 1.4 MAC statistics

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 Broadcast Packets Total broadcast packets with a

good FCS

 Multicast Packets Total multicast packets with a good

FCS

 Fragments Frames < 64 bytes with a bad FCS

 Jabbers Frames > MTUMAX with a bad FCS

CRC Align Errors Frames with a bad FCS that are

neither fragments nor jabbers

in-the-clear

Bad Packets Frames with a bad FCS

Good Packets Frames with a good FCS

Undersize Packets Frames with a good FCS less than

64 bytes

 64 Byte Packets The total number of packets (good

+ bad) of 64 byte length

 65 To 127 Byte Packets The total number of packets (good

+ bad) between 65 and 127 byte

length

 128 To 255 Byte Packets The total number of packets (good

+ bad) between 128 and 255 byte

length

 256 To 511 Byte Packets The total number of packets (good

+ bad) between 256 and 511 byte

length

 512 To 1023 Byte Packets The total number of packets (good

+ bad) between 512 and 1023 byte

length

 1024 To 1518 Byte Packets The total number of packets (good

+ bad) between 1024 and 1518

byte length

 1519 To 1522 Byte Packets The total number of packets (good

+ bad) between 1519 and 1522

byte length

 1523 To 1548 Byte Packets The total number of packets (good

+ bad) between 1523 and 1548

byte length

Egress Ingress Per

Priority

Name Description

Table 1.4 MAC statistics

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11)Count MAC control packets that are either secured, unsecured, or both.

1.10 Energy Efficient Ethernet

The AQR405 provides support for EEE on KR, RXAUI, 10GBASE-T, 5G, 2.5G, and

1000BASE-T interfaces. It is also capable of running in both normal operating

mode, where the system controls entering and exiting from the EEE state, and

autonomous operation on the line, where the PHY will control entering and exiting

EEE operation via a provisionable “no-traffic” timer. If no traffic is seen within a

certain period of time, the PHY will go to sleep on the line if connected at either 10G

or 1G rates. This mode of operation requires the MACsec buffers and MACs to be

in operation, as rate pacing during startup is done via PAUSE frames.

1.11 Precision Time Protocol (PTP)

The AQR405 provides support for PTP and related protocols. Specifically it

supports the following protocols (running both over MACsec or in the clear):

1) 1588 Version 1 (1 step and 2 step)

 1549 To 2000 Byte Packets The total number of packets (good

+ bad) between 1549 and 2000

byte length

 2001 To 2500 Byte Packets The total number of packets (good

+ bad) between 2001 and 2500

byte length

 2501 To MTU Byte Packets The total number of packets (good

+ bad) between 2501 and MTU

byte length in-the-clear

 1549 To MTU Byte Packets The total number of packets (good

+ bad) between 1549 and MTU

byte length in-the-clear

Oversize Packets (per priority) The total number of packets of

length greater than MTU bytes and

a good FCS in-the-clear

 MAC Control Packets MAC Control Frames with

EtherType 88_08 in-the-clear or

secured (option for both)

Errored Packets Packets with Code or Symbol

Errors

Egress Ingress Per

Priority

Name Description

Table 1.4 MAC statistics

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2) 1588 Version 2 (1 step and 2 step)

3) NTP Version 3

4) NTP Version 4

5) SNTP Version 4

To support these protocols, the AQR405 has the following counters:

1) A 48-bit seconds counter

2) A 32-bit nanoseconds counter. Note that since 109 = 0x3B9ACA00, only

30 bits of this counter actually count.

3) A 32-bit fractional nanoseconds counter (LSbit = 2-32 ns)

4) A programmable increment sufficient to add the correct amount of

nanoseconds and fractional nanoseconds to the counter each reference

clock cycle. (i.e. if you are running on a 200 MHz clock, the increment

should nominally be 5 ns per cycle, hence only 3 nanosecond bits and

32 fractional nanosecond bits are required).

All of these counters support the ability to be hitlessly altered.

Ingress timestamping accuracy in the AQR405 is rounded to 16 fractional

nanosecond bits (48 + 32 + 16 = 96 bits). This timestamp is appended to the packet

(or placed in the packet preamble when operating in USXGMII mode) and the

packet’s header and FCS are altered accordingly. The packet can then be passed

to the system interface, or placed in a 512 byte FIFO that can be accessed from

the MDIO registers space. A similar FIFO in the egress direction supports the

ability to send sync packets into the data stream. The MACsec buffers and

associated MACS must be operating for this to work.

In order to support asymmetry between the Tx and Rx path, the AQR405 supports

a correction register to offset the timestamps by the required amount.

The AQR405 also supports the following PTP features:

1) Running the PTP clocks from the received line clock

2) Running the PTP clocks from an external (up to) 400 MHz LVDS clock

input.

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3) Transparent clock mode

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Hardware Interfaces†2-

2.1 Management Interface

†Table Conventions: any signal name that ends with “*” or pin name that ends with “_N”

are active low.

Signal Name Pin Name(s) Pin Number(s) Type Description

Interrupt* INT_N K18 OD The 2.5V tolerant open-drain

interrupt signal from PHY 0 of

the AQR405. On reset this is

set high. This input can be

driven to work at 1.2V via the

MDIO_1P2_SELECT_N pin,

regardless of the voltage on

VDD_IO.

This open-drain 20 mA output

is on the VDD_IO domain.

MDIO

Address

ADDR0, ADDR1,

ADDR2, ADDR3,

ADDR4

K15, J15, J16,

H16, G17

I The logic inputs to set the

MDIO PHY address of the

AQR405.

These inputs are on the

VDD_IO domain and have

pull-ups associated with them.

MDIO Clock MDC J18 I The MDIO clock input for the

AQR405.

This input is on the VDD_IO

domain.

MDIO Data MDIO L18 I/O The MDIO data line (w/

Schmitt triggered logic levels)

for the AQR405. On reset this

is set to high-impedance.

This tri-state 20 mA I/O is on

the VDD_IO domain.

Table 2.1 Management Interface signals

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The management interface on the AQR405 is a two wire interface with a

unidirectional MDC clock and a bidirectional MDIO data. The MDIO interface on the

AQR405 is a robust implementation of this standard. It is designed to operate up

to 10.5 MHz† and is capable of withstanding voltages up to double the operating

voltage (the theoretical worst-case maximum reflection on an unterminated bus). It

utilizes a Schmitt-trigger in conjunction with a debounce state machine to

debounce the signals, and is capable of hot-insertion. The

Reset Out* RST_OUT_N H3 OD The open-drain reset output

from the AQR405. This may

be used to drive the power-up

reset signal for a board, as it

outputs the on-chip power-up

reset signal from the AQR405.

This open-drain 20 mA output

is on the VDD_IO domain.

Reset* RST_N J4 I The hard reset input (w/

Schmitt triggered logic levels)

for the AQR405. This input

can be driven to work at 1.2V

via the

MDIO_1P2_SELECT_N pin,

regardless of the voltage on

VDD_IO.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Tx Enable TX_EN F5 I When pulled low, this input

disables the output line drivers

on the AQR405, and

guarantees less than -53 dBm

output power. This input can

be driven to work at 1.2V via

the MDIO_1P2_SELECT_N

pin, regardless of the voltage

on VDD_IO.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

†This is a function of whether the output is set to push-pull or open-drain mode, and on

the capacitance of the bus.

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.1 Management Interface signals

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data line is capable of pulling low a 280 Ω load tied to 1.2V, and may be configured

to support either open-drain, or push-pull operation in "Global General Provisioning

2: Address 1E.C441". Push-pull is the default operating mode.

In order to provide flexibility to the implementation, the AQR405 utilizes a

programmable I/O voltage. The logic thresholds for the I/O are set at 70% and 30%

of VDD_IO for VIH/VOH and VIL/VOL respectively. For 1.2V MDIO operation (affects

MDC, MDIO, INT_N, RST_N) a separate signal called MDIO_1P2_SELECT_N is

provided that will force 1.2V operation on these signals, regardless of the VDD_IO

voltage.

The management interface allows communication between the Station

Management (STA) and a physical layer device (PHY). The STA is the external

host controller which is the master of the management interface bus.

Consequently, it always sources the MDC clock. When the MDIO is sourced by the

STA, the PHY will sample the MDIO at the rising edge of MDC. When the MDIO is

sourced by the PHY during read operations, the STA will sample the MDIO at the

rising edge.

Table 2.2 shows the management interface frame format (802.3-2005 45.3). The

fields are described below:

IDLE (idle condition):

The idle condition on the management interface is a high-impedance

state. All tri-state drivers are disabled and the pull-up resistor(s) on the

MDIO bus will pull the MDIO line to a one.

Frame PRE ST OP PHYAD MMDAD TA Data IDLE

Address 1...1 00 00 PPPPP EEEEE 10 AAAAAAAAAAAAAAAA Z

Write 1...1 00 01 PPPPP EEEEE 10 DDDDDDDDDDDDDDDD Z

Read 1...1 00 11 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z

Post-read

increment

address

1...1 00 10 PPPPP EEEEE Z0 DDDDDDDDDDDDDDDD Z

Table 2.2 MDIO frame format

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PRE (preamble):

Normal Operation:

At the beginning of each transaction, the station management entity will

send a sequence of 32 contiguous ones on the MDIO data line, along

with 32 corresponding cycles on the MDC to provide the MMD with a

pattern that it can use to establish synchronization. Each MMD will

observe a sequence of 32 contiguous one bits on MDIO with 32

corresponding cycles on MDC before it responds to any transaction.

Preamble Suppression:

The MDIO interface can optionally disable preamble detection by setting

the "MDIO Preamble Detection Disable" bit in "Global General

Provisioning 2: Address 1E.C441". In this mode of operation, one or

more preamble bit are required followed by the 0x0 start of frame ST bits.

ST (start of frame):

The start of frame for indirect access cycles is indicated by the <00>

pattern. This pattern assures a transition from the default one and

identifies the frame as an indirect access. Frames that contain the

ST=<01> pattern defined in Clause 22 will be ignored by the MMDs

within the AQR405.

OP (operation code):

The operation code field indicates the type of transaction being

performed by the frame. A <00> pattern indicates that the frame payload

contains the address of the register to access. A <01> pattern indicates

that the frame payload contains data to be written to the register whose

address was provided in the previous address frame. A <11> pattern

indicates that the frame is read operation. A <10> pattern indicates that

the frame is a post-read increment address operation.

PHYAD (PHY address):

The PHY address is five bits, allowing for 32 unique PHY addresses, and

hence up to 32 PHYs on an MDIO bus. (The address of the PHY is

determined from the ADDR[4:2] pins). The first PHY address bit to be

transmitted and received is the MSB of the address. The station

management entity must have a priori knowledge of the appropriate PHY

address for each PHY to which it is attached, whether connected to a

single PHY or to multiple PHYs.

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MMDAD (MMD address):

The MMD address is five bits, allowing for 32 unique MMDs per PHY.

The first MMD address bit transmitted and received is the MSB of the

address.

In addition the AQR405 supports a broadcast mode when the PHYAD is

0x00. Only the write and load address opcodes are supported in

broadcast mode. Read and post-read increment opcodes are ignored in

broadcast mode. This mode of operation can be enabled via the "MDIO

Broadcast Mode Enable"bits ("Global General Provisioning 2: Address

1E.C441".

TA (turnaround):

The turnaround time is a 2-bit time spacing between the MMD address

field and the data field of a management frame to avoid contention during

a read transaction. For a read or post-read increment address

transaction, both the STA and the MMD remain in a high-impedance

state for the first bit time of the turnaround. The MMD then drives a zero

bit during the second bit time of the turnaround of a read or post-read

increment address transaction. During a write or address transaction, the

STA transmits a one for the first bit time of the turnaround and a zero for

the second bit time of the turnaround. This behavior is shown in Figure

2.1:

ADDRESS / DATA:

The address/data field is 16 bits. For an address cycle, it contains the

address of the register to be accessed on the next cycle. For the data

cycle of a write frame, the field contains the data to be written to the

Figure 2.1 MDIO bus turn-around during Read operations

VIH

VIL

MDC*

VIH

VIL

VIH

VIL

MDC*

VIH

VIL

MDIO Line

VIH

VIL

VIH

VIL

MDIO Line

<MMD Address[0]><MMD Address[1]> <Z> <0> Data[15]

MDIO Driven by STA MDIO Driven by PHY MMD

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contains the contents of the register. The first bit transmitted and

received shall be bit 15.

For counters that are greater than 16-bits, the LSW must be read first,

then the MSW must be read immediately afterwards. When the LSW is

read, the counter is cleared and the MSW is stored in a shadow register.

Reading the MSW actually reads the shadow register.

Optionally the host may read the MSW first, then the LSW immediately

afterwards by setting the "MDIO Read MSW First Enable"bit in "Global

General Provisioning 2: Address 1E.C441".

2.1.1 Interrupt

The AQR405 supports an open-drain interrupt pin per PHY. This signal conforms

to the XENPAK LASI signal requirements.

2.1.2 Reset

The AQR405 supports an active-low reset input that conforms to the XENPAK

Reset* requirements.

In addition to this, the AQR405 is capable of generating a RST_OUT_N signal from

its internal power-on reset generation circuitry that can be used by the external

board circuitry.

Operation of the reset machinery is as follows:

1) Release from the Reset state begins when the RST_N input is high†, and

all of the core power supplies are above their required thresholds. These

thresholds are listed below:

2) Once all of the conditions for release from Reset are true, a 20ms timer

will engage, the purpose of which is to allow the supplies to settle prior

to allowing the PHY to boot

3) After the 20ms timer has completed, hardware state machines designed

to guarantee PLL and band-gap stability engage.

4) After the PLLs and band-gap are locked and functioning properly, the

processor and digital circuitry are released from reset.

†Note that there are no timing requirements on issuance of reset relative to the clock

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5) The PHY image is then loaded (either via the daisy-chain, or through

MDIO boot-load) and the processor boots.

6) After the processor boots, any provisioned register values are set, and

the PHY enters the provisioned operating state.

7) Once this is complete, the processor raises the MMD reset bits and sets

the Reset Completed alarm, indicating it has completed reset and is

ready for operation.

2.1.3 Configuration

The AQR405 contains a number of static configuration pins which are used to set

the power-up operation of the AQR405. These signals are:

1) MDIO Address (ADDR[4:2])

In the AQR405 package, the MDIO addressing is tied off internally so that the LSBs

increment according to the PHY number in the package. This MDIO address can

either be overridden via a register in the Global MMD via provisioning, or the

incrementation order can be altered via the INV_ADDR[1:0] pins which are

exclusive OR’d with their respective address pins.

2.2 Serial FLASH

The AQR405 is capable of three modes of boot operation:

1) Daisy-chain master

2) Daisy-chain slave

3) MDIO boot-load

Supply Parameter Min Max Units

VA22 Power-on reset

threshold for VA22

DC supply

1.70 1.80 V

VA12 Power-on reset

threshold for VA12

DC supply

0.93 0.99 V

VDD Power-on reset

threshold for VDD

DC supply

0.56 0.60 V

Table 2.3 Power-on reset thresholds for core supply voltages

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Signal Name Pin Name(s) Pin Number(s) Type Description

Daisy-chain

Clock Input

RX_DC_CLK J1 I The daisy chain receive serial

clock. This signal travels away

from FLASH.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

Daisy-chain

Clock Output

TX_DC_CLK N18 O The daisy chain transmit serial

clock. This signal travels away

from FLASH.

This 20 mA output is on the

VDD_IO domain.

Daisy-chain

Data Input

RX_DC_DATA H1 I The daisy chain receive serial

data. This signal travels away

from FLASH.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

Daisy-chain

Data Output

TX_DC_DATA M17 O The daisy chain transmit serial

data. This signal travels away

from FLASH.

This 20 mA output is on the

VDD_IO domain.

Daisy-chain

Master*

DC_MASTER_N E1 I The daisy-chain mode control:

0 = Daisy Chain Master, 1 =

Daisy Chain Slave.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Daisy-chain

Reset* Input

RX_DC_RST_N N17 I The daisy chain receive reset.

This signal travels towards

FLASH.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Daisy-chain

Reset*

Output

TX_DC_RST_N H2 O The daisy chain transmit reset.

This signal travels towards

FLASH.

This 20 mA output is on the

VDD_IO domain.

Table 2.4 Serial FLASH signals

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When functioning in Daisy-chain master mode, the AQR405 has an attached SPI

FLASH, and the PHY’s firmware image is loaded from the FLASH. When

functioning in Daisy-chain slave mode (see Section 2.2.1), a series of PHYs are

strung together in a daisy-chain, with one functioning as the master with an

attached FLASH device, and the others (the Daisy-chain slaves) receiving their

firmware image from the Daisy-chain master. In both cases, integrity checking of

the loaded image is performed in hardware via a CRC embedded in the image, and

Daisy-chain

Start-of-Fram

e Input

RX_DC_SOF J2 I The daisy chain receive start of

frame. This signal travels

away from FLASH.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

Daisy-chain

Start-of-Fram

e Output

TX_DC_SOF M18 O The daisy chain transmit start

of frame. This signal travels

away from FLASH.

This 20 mA output is on the

VDD_IO domain.

SPI Chip

Enable*

CE_N G2 O The SPI CE* signal from the

AQR405 to the serial FLASH.

On reset this is set high.

This 20 mA output is on the

VDD_FLASH domain.

SPI Serial

Clock

SCLK G1 O The SPI clock from the

AQR405 to the serial FLASH.

On reset this is set low.

This 20 mA output is on the

VDD_FLASH domain.

SPI Serial

Input Data

SIN F1 I The SPI input data from the

serial FLASH to the AQR405.

This input is on the

VDD_FLASH domain and has

a pull-up associated with it.

SPI Serial

Output Data

SOUT F2 O The SPI output data from the

AQR405 to the serial FLASH.

On reset this is set low.

This 20 mA output is on the

VDD_FLASH domain.

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.4 Serial FLASH signals

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if there is an error, a reload is automatically requested. When functioning in MDIO

boot-load mode, no FLASH device is required. Instead, the firmware image is

loaded via the MDIO interface, and integrity checking of the loaded image is

performed via a hardware CRC function on the memory interface. In order to use

MDIO boot-load, the boot-load functions from the API should be carefully studied,

or utilized verbatim.

2.2.1 SPI FLASH Interface

The SPI interface is responsible for connecting the AQR405 to the external FLASH

memory device. The microcontroller on the AQR405 will access the boot code and

AQR405 default register values from the FLASH memory after power-on reset.

This FLASH memory is also accessible via the MDIO interface for firmware

updates and manufacturing burn via the API, or via the registers in the Global

MMD.

The SPI interface is a four wire, unidirectional, serial bus as shown in Figure 2.2. It

is composed of a serial clock output “SCLK”, a serial data output “SOUT”, a serial

data input “SIN”, and a chip-select “CE*”. All the signals are unidirectional.

The AQR405 is set up to function as a Mode 0 (0,0) SPI device, which means that

the clock defaults to zero when not bursting. Data on this interface, for both SIN

and SOUT, is always sourced on the falling edge of SCLK, and sampled on the

rising edge of SCLK.

Figures 2.3 - Figures 2.5 show typical read, burst read, and write operations for the

AQR405. In all of these scenarios, the API or the NVR interface in the Global MMD

is used to access the FLASH.

The NVR interface in the AQR405 is designed to be able to output any arbitrary

opcode, followed by a programmable zero to three address bytes, followed by a

programmable zero to four data bytes. This allows any variation of opcodes to be

Figure 2.2 SPI Interface Block Diagram

SCLK

SOUT

CE*

SIN

PHY NVR

CS*

SCK

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output to the attached FLASH device. This interface also supports a burst read and

write mode, which keeps the CS* line pulled low to enable back-to-back reads and

writes. To support this, the NVR interface supports two 16-bit address registers and

two 16-bit data registers, which allows up to 4 data bytes in a burst over the SPI

interface. In order to extend this to longer bursts, the AQR405 halts the clock after

the last bit in the data burst allowing the host processor to load another block of

data to / from the NVR interface. This is shown in Figures 2.4 - 2.5 and allows the

data burst to be extended by as many bytes as necessary, without outstripping the

MDIO’s I/O capabilities.Note that typical NVRs require that writing be performed on

a block basis, and thus the addresses usually wrap within the block being

programmed. As such, it is desirable from a speed and efficiency perspective to

attempt to write entire blocks, versus pieces of blocks.

In order to assure that no polling is required on NVR interface, it is recommended

that the NVR clock speed be set to at least†:

Figure 2.3 SPI read

Figure 2.4 SPI Burst read

Figure 2.5 SPI burst write

012345678

Mode 0

15 16 23 24 31 32 39 40 47 48 55 56 63

CS*

SCLK

SIN

SOUT

A2 A1 A0

DnDn+1 Dn+3

Opcode = 0x3

000000

Dn+2

Gap

Dn+4

Bit 7 6

64 65 66

012345678

Mode 0

15 16 23 24 31 32 39 40 47 48 55 56 63

CS*

SCLK

SIN

SOUT

A2 A1 A0

DnDn+1 Dn+3

Opcode = 0x3

000000

Dn+2

078

Mode 0

15 16 23 24 31 32 39 40 47 48 55 56 63

CS*

SCLK

SIN

SOUT

A2 A1 A0 DnDn+1 Dn+3

PGM

Dn+2

0?2

Gap

Dn+4

Bit 7 6

64 65 66

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The desired FLASH memory should be chosen to be at least 512K bytes in size,

and must be capable of interfacing to a 2.5V CMOS SPI.

2.2.2 Daisy-chain Operation

In an effort to reduce BOM costs and have multiple chips share a single FLASH

device, the AQR405 supports the direct loading of firmware from a daisy-chained

FLASH image to the PHYs internal instruction and data RAM. Operation of the

FLASH daisy-chain is shown in Figure 2.6. Here, the FLASH image from a

daisy-chain master chip, which has an external FLASH device attached, is

streamed along a daisy-chain to slave chips which do not have an external FLASH.

These slave chips will directly load their local processor’s IRAM and DRAM from

the streaming FLASH image as it is received, while at the same time forwarding the

image to the next slave chip in the chain. On a micro-scale each chip contains a

primary and secondary PHY. Only the primary PHY on the master chip is

connected to the FLASH device. The secondary PHY is always daisy-chained to

the primary PHY.

The daisy-chain bus consists of a clock, data, and start of frame (SOF) signal. In

the reverse direction, a daisy-chain reset signal is provided so that when a slave

chip is reset, it has the ability to send a rebroadcast request to the daisy-chain

master chip. The master chip will then reread the FLASH and re-stream the image

onto the daisy-chain bus.

When DC_MASTER_N is pulled low, the AQR405 will be in daisy-chain master

†This is derived from the fact that the longest burst instruction on the SPI is 64 bits, at one

bit per clock, whereas to write a register on the MDIO takes 64 clocks, and the data is

not written until the last bit - hence the 63.

Figure 2.6 Daisy-chain operation

SCLK

------fMDIO

⋅>

Master PHY

FLASH

Slave PHY Slave PHY

Data

Daisy-chain

Reset

Daisy-chain

Reset

Clock Data

Clock

SoF SoF

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mode. In this mode, the AQR405 will load the FLASH image directly into PHY’s

IRAM and DRAM, while at the same time, streaming the FLASH image onto the

daisy-chain bus to other PHYs which are configured as a daisy-chain slaves

(DC_MASTER_N = 1).

In addition, each daisy-chain slave AQR405 will have the ability to assert its

daisy-chain reset signal (which is AND’ed with the incoming daisy-chain reset

signal) which travels in the reverse direction back to the daisy-chain master. This

will cause the daisy-chain master chip to re-stream the FLASH image back onto

the daisy-chain bus. The daisy-chain slave chip must assert the daisy-chain reset

for a minimum of 100 ns. If a daisy-chain reset occurs in the middle of streaming a

FLASH image, the daisy-chain master chip will complete streaming the image and

then when it is finished, re-stream the image again. Load integrity of the image is

guaranteed via a CCITT-16 CRC which is broadcast in the daisy-chain header

data. Also contained in this header is a hop counter (PHY0 is the daisy-chain

master and is hop-count #0, the second PHY in the daisy-chain is hop-count #1,

on so on...) which is used to disambiguate devices in the Daisy-chain for firmware

provisioning.

In order to ensure that the daisy-chain bus and SPI FLASH interface are in

synchronization, the SPI FLASH interface is rate paced so that it doesn’t overrun

the daisy-chain streaming rate. Similarly, the daisy-chain clock is gated to ensure

that is does not outpace the read-rate of the FLASH. Granularity for rate-pacing is

in blocks of 32 bits.

Figure 2.7 Daisy-chain signals and direction of flow

DC_MASTER_N Description

0x0 Daisy-chain master mode: indicates that this AQR405 has the

attached FLASH and will stream the image when requested.

0x1 Daisy-chain slave mode: indicates that this AQR405 has no

attached FLASH and will boot-load its image from the image

streamed over the daisy-chain bus.

Table 2.5 DC_MASTER_N

RX_DC_CLK

RX_DC_DATA

RX_DC_SOF

TX_DC_CLK

TX_DC_DATA

TX_DC_SOF

RX_DC_RST_NTX_DC_RST_N

Rebroadcast Request

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2.2.3 Boot-load

Regardless of whether the PHY is a daisy-chain master or slave, a new image can

always be boot-loaded into the PHY’s IRAM and DRAM via the MDIO interface. As

well, if boot-load operation is desired as the product’s standard operating mode,

the FLASH can be depopulated, and the image always loaded on power up. For

more information on this mode of operation, please consult the API documentation.

2.3 Firmware

The AQR405 contains a 32-bit microcontroller. This microcontroller is designed to

have it’s IRAM and DRAM either loaded on power-up / reset from the attached

FLASH, via the daisy-chain loading mechanism described in Section 2.2, or to

have its boot image loaded by the host processor via the MDIO interface.

Programming of the FLASH on the daisy-chain master device is done via the

appropriate function in the API.

2.3.1 Provisionable Default

Another feature of the AQR405 is the ability to change and store the default values

of any field marked as “PD”. A delta list of all defaults that are different from the

hardware defaults are stored in the image, and upon power-up, the PHY’s

microprocessor will overwrite the hardware defaults with these new values.

Provisioning these new default values is done using the Aquantia Default

Provisioning tool, and PHYs are identified by hop count along the daisy-chain bus,

allowing each PHY to be uniquely provisioned.

2.3.2 Gang-load

In order to save time on MDIO boot-loading operations, the AQR405 supports a

gang-load feature, whereby multiple AQR405 chips on a single MDIO bus may be

simultaneously loaded with boot images. This is done by temporarily setting all of

the device’s MDIO addresses to be the same, loading the boot image, and then

toggling the MDIO Address Reset bit in the Global register MMD. Again this can

also be handled via the API. Another option is to enable MDIO broadcast on

address 0.

2.4 SERDES

The AQR405 SERDES interface is both robust and flexible, and provides

numerous loopback and diagnostic capabilities which ease system interface-PHY

board design and bring-up, as well as AC JTAG. The interface is capable of

providing arbitrary lane swapping and inversion. In the transmit direction, there is

a programmable 3 taps equalizer (1 precursor and 1 postcursor tap), as well as the

ability to program the Tx drive strength, and Tx termination. In the receive direction,

there is programmable gain and programmable boost.

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In SGMII mode, the interface operates at 1.25 Gb/s over SERDES logical Lane 0

Signal Name Pin Name(s) Pin Number(s) Type Description

Lane 0 Rx RX_LN0_P,

RX_LN0_N

P2, P1 I Physical Lane 0 differential Rx

of the AQR405 SERDES

interface. This lane can

operate in KR, RXAUI, XAUI,

and SGMII mode.

Lane 0 Tx TX_LN0_P,

TX_LN0_N

T2, T1 O Physical Lane 0 differential Tx

of the AQR405 SERDES

interface. This lane can

operate in KR, RXAUI, XAUI,

and SGMII mode.

Lane 1 Rx RX_LN1_P,

RX_LN1_N

U2, V2 I Physical Lane 1 differential Rx

of the AQR405 SERDES

interface. This lane can

operate in XAUI, and SGMII

mode.

Lane 1 Tx TX_LN1_P,

TX_LN1_N

U3, V3 O Physical Lane 1 differential Tx

of the AQR405 SERDES

interface. This lane can

operate in XAUI, and SGMII

mode.

Lane 2 Rx RX_LN2_P,

RX_LN2_N

U4, V4 I Physical Lane 2 differential Rx

of the AQR405 SERDES

interface. This lane can

operate in KR, RXAUI, XAUI,

and SGMII mode.

Lane 2 Tx TX_LN2_P,

TX_LN2_N

U6, V6 O Physical Lane 2 differential Tx

of the AQR405 SERDES

interface. This lane can

operate in KR, RXAUI, XAUI,

and SGMII mode.

Lane 3 Rx RX_LN3_P,

RX_LN3_N

U7, V7 I Physical Lane 3 differential Rx

of the AQR405 SERDES

interface. This lane can

operate in XAUI, and SGMII

mode.

Lane 3 Tx TX_LN3_P,

TX_LN3_N

U8, V8 O Physical Lane 3 differential Tx

of the AQR405 SERDES

interface. This lane can

operate in XAUI, and SGMII

mode.

Table 2.6 SERDES signals

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and is compliant to the Cisco SGMII specification[10]. In 2500BASE-X mode, the

interface operates at 3.125 Gb/s over any of the lanes. In RXAUI mode, the

interface operates over Lanes 0 and 2 and is compliant to Marvell and Dune

specifications. Since RXAUI is essentially a front-end MUX for XAUI, the XAUI

registers are reused in RXAUI mode. In KR mode, two separate 10G interfaces are

provided operating over Lanes 0 and 2†.

The SERDES interface on the AQR405 also contains diagnostic pattern generation

and checking functionality that is listed below:

†The Lane 0 KR interface is dedicated to the optics lookaside port (i.e. facing towards the

network), and the Lane 2 KR interface is dedicated to the system interface. Note that

these are the only lanes that are connected in the AQR405. As such there are still

references to Lanes 1 and 3 as well as XAUI in the register map, but these are not

operational in the AQR405.

Test Description Generate Check Invert

x9 PRBS 

x31 PRBS 

Square Wave

Clause 49.2.12 

Pseudo-Noise 

CRPAT IEEE 802.3 Annex48A.4 

Table 2.7 KR diagnostic pattern capabilities

Test Description Generate Check Invert

x7 PRBS 

x15 PRBS 

x23 PRBS 

x31 PRBS 

CRPAT IEEE 802.3 Annex48A.4 

CJPAT IEEE 802.3 Annex48A.5 

Table 2.8 RXAUI/XAUI diagnostic pattern capabilities

x9x51++

x31 x28 1++

x7x61++

x15 x14 1++

x23 x18 1++

x31 x28 1++

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Another feature the AQR405 SERDES interface can provide is the eye-diagram

mode, which allows the user to create an eye-diagram. To use this functionality, the

appropriate API functions must be called.

All of the parameters associated with the SERDES interface have provisionable

default values, which means that the AQR405 SERDES interface can be tailored

to power-up with the optimal settings for any given application.

2.5 SERDES Operating Modes

For the purposes of this discussion, the AQR405 can be viewed as a set of blocks

as shown below:

On the left side of the diagram is the system interface, which consists of the two

SERDES lanes. Lanes 0 and 2 have the ability to run at rates from 1.25 Gb/s to

10.3125 Gb/s. These lanes support SGMII, 2500BASE-X, RXAUI, and KR. In the

AQR405 only two of the four SERDES lanes on the chip are actually run out, but

these lanes are still referred to as Lane 0 and Lane 2. At the PCS layer, there are

two SGMII cores, two KR cores, and one RXAUI core, even though only the two

SGMII and KR cores are used.

From a system perspective, the two SGMII and KR PCS cores (designated SGMII0

/ SGMII1 and KR0 / KR1 respectively) allow the chip to support a “look-aside”

optical port. What this does is allow a common system interface with the ability to

either go out on the MDI interface (copper) or go out the chip on the second KR

interface (optical). This mode is shown below.

Test Description Generate Check Invert

CRPAT IEEE 802.3 Annex48A.4 

Table 2.9 SGMII diagnostic pattern capabilities

Figure 2.8 AQR405 operational blocks

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

Hybrid

MDIO

Management

MDIO

Registers

THP

Precoder

THP

Precoder

THP

Precoder

DAC /

Driver

A/D

THP

Precoder

THP

Precoder

A/D

VGA &

Filter

THP

Precoder

THP

Precoder

VGA &

Filter

DSP

SERDES

SRDS0

10G

SRDS2

10G

System I/F

LINE

MACSEC

5G PCS

1G PCS

100M PCS

KR/USXGMII

PCS 1

SGMII

PCS 1

SGMII

PCS 0

KR/USXGMII

PCS 0

10G PCS

2.5G PCS

XAUI/RXAUI

PCS

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NOTE!! The SGMII0 and KR0 cores are exclusively dedicated to the lookaside

interface, and SGMII1 and KR1 cores are exclusively dedicated to the system

interface.

These different SERDES operating modes are summarized in Table 2.10.

2.6 SERDES System I/F Start-Up

In start-up on the system interface side, there are four different operating scenarios

for the SERDES I/F:

a) 10G mode (KR or RXAUI)

b) 1000BASE-X mode

c) XSGMII mode†

d) USXGMII mode

e) All-off mode

These different modes affect only the system interface, and function independently

of whether the MDI or KR-look-aside interface is selected.

Interface Operating Mode

/ Core Used

Lane 0 Lane 1 Lane 2 Lane 3

System

SGMII1 X

RXAUI X X

KR1 X

Line

SGMII0 X

KR0 X

Table 2.10 SERDES lane assignments for different operating modes

†XSGMII is an extension of the Cisco SGMII protocol which informs the system interface

what the PHY has autonegotiated as a rate. The XSGMII extension as proposed by

Aquantia uses this same mechanism, but also informs of a 10G connection. After

receiving acknowledgement of a 10G connection, the PHY will switch to the

pre-configured 10G mode. For more details see “XSGMII” on page 42.

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2.6.1 10G Mode

1) In this mode, which is the hardware default, the AQR405 comes up in the

pre-configured 10G mode (KR or RXAUI) and transmits Local Faults /

Idles, and remains in this state until a connection to a link partner is

established.

2) After connection to a link partner has been established, the AQR405 will

either stay in the pre-configured 10G mode, or switch to 1000BASE-X

mode, or 100M SGMII mode depending on that the autonegotiated line

rate was.

3) Once the SERDES I/F has synchronized, traffic flows.

4) If the link fails and the system interface was in 10G mode, the AQR405

generates a Local Fault message towards the system I/F, effectively

restarting. If the link had transitioned to 1G operation, the SERDES is

restarted in 10G mode generating Local Faults / Idles.

5) Autonegotiation restarts after the link break timer expires.

2.6.2 1000BASE-X Mode

1) In this mode the AQR405 comes up in 1000BASE-X mode and transmits

idles, and remains in this state until a connection to a link partner is

established.

2) After a connection to a link partner has been established, the AQR405

will either stay in 1000BASE-X mode, or switch to the pre-configured

10G mode, or 100M SGMII mode depending on that the autonegotiated

line rate was.

3) Once the SERDES I/F has synchronized, traffic flows.

4) If the link fails and the system interface was in the pre-configured 10G

mode (KR or RXAUI), the AQR405 generates a Local Fault message

towards the system I/F, and effectively restarts in 1000BASE-X mode,

generating Idles. Otherwise the link just stays in 1000BASE-X mode

generating Idles.

5) Autonegotiation restarts after the link break timer expires.

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2.6.3 XSGMII Mode

1) In this mode the AQR405 comes up in XSGMII mode. After sending and

receiving an ACK on an XSGMII link-down autonegotiation message

(see Table 2.11), the SERDES transmits Idles, and remains in this state

until connection to a link partner is established.

2) After a connection to a link partner has been established, the AQR405

will send an XSGMII Link Up autonegotiation message with the

appropriate rate† (see Table 2.11) and receive an ACK.

3) Upon receiving the acknowledge from the system interface, the AQR405

will either switch to 100M SGMII mode, stay in 1G SGMII mode

(essentially 1000BASE-X), or switch to the pre-configured 10G mode

(KR or RXAUI), depending on whether the autonegotiated line rate was

1G / 100M or 10G.

4) Once the SERDES I/F has synchronized, traffic flows.

5) If the link fails and the AQR405 was in the pre-configured 10G mode, the

AQR405 generates a Local Fault message towards the system I/F and

then transitions back to XSGMII mode, where it sends and receives an

ACK on an XSGMII link-down autonegotiation message and then

resumes transmitting Idles. If the link fails and the AQR405 was in 1G

SGMII mode, the AQR405 first sends and receives an ACK on an

XSGMII link-down autonegotiation message and then resumes

transmitting Idles, with no interruption in SERDES operation. If the

system I/F was in 100M SGMII mode, the SERDES transitions back to

XSGMII mode, where it sends and receives an ACK on an XSGMII

link-down autonegotiation message and then resumes transmitting Idles.

6) Autonegotiation restarts after the link break timer expires.

2.6.4 USXGMII Mode

1) In this mode the AQR405 comes up in USXGMII mode. After sending

and receiving an ACK on an USXGMII link-down autonegotiation

message (see Table 2.12), the SERDES transmits Idles, and remains in

this state until connection to a link partner is established.

†The SGMII autonegotiation machinery was derived from 1000BASE-X and involves

exchanging 16 bit control words via /C and /I ordered sets. It was adopted for SGMII to

solve the issue of how a copper SFP module would inform the system interface what

rate it had autonegotiated on the line, without having an MDIO interface (SFP only

supports ).

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2) After a connection to a link partner has been established, the AQR405

will send an USXGMII Link Up autonegotiation message with the

appropriate rate† (see Table 2.12) and receive an ACK.

3) Upon receiving the acknowledge from the system interface, the AQR405

will either switch to the desired rate, depending on whether the

autonegotiated line rate was 100M, 1G, 2.5G, 5G, or 10G.

4) Once the SERDES I/F has synchronized, traffic flows.

5) If the link fails, the AQR405 generates a Local Fault message towards

the system I/F and then transitions back to USXGMII Idle mode, where

it sends and receives an ACK on an USXGMII link-down autonegotiation

message and then resumes transmitting Idles.

6) Autonegotiation restarts after the link break timer expires.

2.6.5 All-Off Mode

1) In this mode the AQR405 comes up with the system interface off, and

remains in this state until connection to a link partner is established.

2) After connection to a link partner has been established, the AQR405 will

either turn on 1000BASE-X, or turn on the pre-configured 10G mode (KR

or RXAUI), or 100M SGMII mode depending on that the autonegotiated

line rate was.

3) Once the SERDES I/F has synchronized, traffic flows.

4) If the link fails and was in the pre-configured 10G mode, the AQR405

generates a Local Fault message towards the system I/F and shuts off.

Otherwise the system interface just shuts off.

5) Autonegotiation restarts after the link break timer expires.

2.6.6 Interrupts

In all of these modes, the processor has the ability to generate an interrupt upon

completing autonegotiation.

†The SGMII autonegotiation machinery was derived from 1000BASE-X and involves

exchanging 16 bit control words via /C and /I ordered sets. It was adopted for SGMII to

solve the issue of how a copper SFP module would inform the system interface what

rate it had autonegotiated on the line, without having an MDIO interface (SFP only

supports ).

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2.6.7 XSGMII

XSGMII is an extension of the SGMII interface and provides the signaling and

control for moving to a 10G connection mode in addition to the SGMII rates of 1G,

100M, and 10M.

XSGMII builds upon the existing specification for SGMII[10], and existing 10GE

specifications defined in 802.3-2005[3].

The creation of XSGMII requires a minimal change to the existing SGMII

specification: namely the addition of a 10G connect rate. Thus:

1) System interface and PHY connect and synchronize the SGMII 1.25

Gb/s 8B/10B SERDES link.

2) PHY uses Clause 28 autonegotiation over the MDI to establish a

connection with the remote PHY, constrained by the abilities the local

system interface communicated during 1, above.

3) PHY uses SGMII (Clause 37) autonegotiation to inform the system

interface which rate it is selecting.

4) If a 10G connection is established, after receiving the acknowledgement

from the system interface, the PHY switches over to 10G operation and

traffic begins to flow after the 10GBASE-T training sequence is

completed.

5) If a 100M or 1G connection is established, after receiving the

acknowledgement from the system interface, the PHY stays in SGMII

mode and traffic begins to flow after the link is established.

The above sequence requires the modifications to Table 1 of the SGMII

specification as shown in Table 2.11, with the modification indicated in red.

2.6.8 USXGMII

USXGMII is an extension of the XFI interface and provides the signaling and

control for moving to a 100M, 1G, 2.5G, and 5G connection mode in addition to the

XFI rates of 10G.

USXGMII builds upon the existing specification for XFI and existing 10GE

specifications defined in 802.3-2005[3].

The creation of USXGMII requires a minimal change to the existing XFI

specification: namely the addition of 100M, 1G, 2.5G, and 5G connection rates.

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Thus:

1) System interface and PHY connect and synchronize the XFI 10.3125

Gb/s 64B/66B SERDES link.

2) PHY uses Clause 28 autonegotiation over the MDI to establish a

connection with the remote PHY, constrained by the abilities the local

system interface communicated during 1, above.

3) PHY uses SGMII (Clause 37) autonegotiation to inform the system

interface which rate it is selecting.

4) If a 10G connection is established, after receiving the acknowledgement

from the system interface, the PHY switches over to 10G operation and

traffic begins to flow after the 10GBASE-T training sequence is

completed.

5) If a 100M, 1G, 2.5G, or 5G connection is established, after receiving the

acknowledgement from the system interface, the PHY stays in SGMII

mode and traffic begins to flow after the link is established.

Table 2.12 shows the USXGMII base page..

2.7 MDI

In 10G mode, the line interface on the AQR405 is capable of driving up to 100 m

of CAT-6a unshielded twisted pair or 100 m of CAT-7 shielded cable (100 Ω

Bit

Number

tx_config_Reg[15:0] sent from the PHY to the

system interface

tx_config_Reg[15:0] sent from the

system interface to the PHY

15 Link: 1 = link up, 0 = link down 0: Reserved for future use

14 Reserved for Auto-Negotiation acknowledge

as specified in 802.3z

13 0: Reserved for future use 0: Reserved for future use

12 Duplex mode: 1 = full duplex (required) 0: Reserved for future use

11:10 Speed: Bit 11, 10

1 1 = 10 Gbps: 10GBASE-T, 10GBASE-R

1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X

0 1 = 100Mbps: 100BASE-TX, 100BASE-FX

0 0 = 10Mbps: 10BASET, 10BASE2, 10BASE5

0: Reserved for future use

9:1 0: Reserved for future use 0: Reserved for future use

00 1

Table 2.11 XSGMII base page

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Bit

Number

usxgmiiChannelInfo[15:0] sent from the PHY to

the system interface

usxgmiiChannelInfo[15:0] sent from the system

interface to the PHY

15 Link: 1 = link up, 0 = link down 0: Reserved for future use

14 Reserved for Auto-Negotiation acknowledge 1

13 0: Reserved for future use 0: Reserved for future use

12 Duplex mode: 1 = full duplex (required) 0 = half

duplex

0: Reserved for future use

11:9 Speed: Bit 11, 10, 9

0 0 0 = 10Mbps: 10BASET, 10BASE2, 10BASE5

0 0 1 = 100Mbps: 100BASE-TX, 100BASE-FX

0 1 0 = 1000 Mbps: 1000BASE-TX, 1000BASE-X

0 1 1 = 10 Gbps: 10GBASE-T, 10GBASE-R

1 0 0 = 2500 Mbps: AQRATE 2.5G

1 0 1 = 5000 Mbps: AQRATE 5G

1 1 0 = Reserved

1 1 1 = Reserved

0: Reserved for future use

8 EEE capability: 1= supported, 0 = not supported 0: Reserved for future use

7 EEE clock stop capability: 1= supported, 0 = not

supported

0: Reserved for future use

6:1 0: Reserved for future use 0: Reserved for future use

0 1 = USXGMII supported device 1

Table 2.12 USXGMII base page

Signal Name Pin Name(s) Pin Number(s) Type Description

CMS CM_P, CM_N E8, D8 I Common Mode Sense Input.

Pair A A_P, A_N B2, A2 I/O Pair A of the AQR405 line

interface. These should

connect to the Pair A inputs of

the transformer, with

capacitive bypassing via the

center-tap. On reset this is set

to high-impedance.

Pair B B_P, B_N B4, A4 I/O Pair B of the AQR405 line

interface. These should

connect to the Pair B inputs of

the transformer, with

capacitive bypassing via the

center-tap. On reset this is set

to high-impedance.

Table 2.13 MDI signals

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differential impedance). It can also drive 55 m of CAT-6 cable, and a lesser distance

of CAT-5e cable†. In 2.5G and 5G mode, it can drive 100m of CAT-5e (or better)

cable. In 1G and 100M modes, it can drive 130m of CAT-5e (or better) cable. It is

designed to drive this via a quad, 50 Ω, center-tapped 1:1 transformer connected

to an RJ-45 PCB-mount jack.

The line interface on the AQR405 supports automatic A/B and C/D pair swaps,

inversions (auto-X), and semi-cross (A/B or C/D only). It also supports

provisionable ABCD to DCBA pair reversal for ease of routing with stack-jacks via

bit 1.E400.0. Note that this reversal does not swap polarities, thus A+ maps to D+,

etc.

Pair C C_P, C_N B6, A6 I/O Pair C of the AQR405 line

interface. These should

connect to the Pair C inputs of

the transformer, with

capacitive bypassing via the

center-tap. On reset this is set

to high-impedance.

Pair D D_P, D_N B8, A8 I/O Pair D of the AQR405 line

interface. These should

connect to the Pair D inputs of

the transformer, with

capacitive bypassing via the

center-tap. On reset this is set

to high-impedance.

†This distance is indeterminate because CAT-5e cable performance is not specified past

100 MHz[11].

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.13 MDI signals

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2.8 Timing

Signal Name Pin Name(s) Pin Number(s) Type Description

50 MHz

Clock

Termination

50M_CLK_TERM G13 I Selects whether PHY provides

100 differential termination for

50 MHz clock input: 1 =

Terminated, 0 = Open.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Clock Source

Select

XTAL_SELECT_N F17 I The 50 MHz reference clock

source selector for the

AQR405. When

XTAL_SELECT_N is pulled

low, these XTAL_I and

XTAL_O pins operate in

crystal mode, otherwise they

operate in LVDS oscillator

input mode.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Crystal Input XTAL_I F18 I The 50 MHz reference clock

input for the AQR405. When

XTAL_SELECT_N is pulled

low, these pins operate in

crystal mode, otherwise they

are the differential LVDS

inputs for an external

oscillator, with XTAL_I being

the positive input and XTAL_O

being the negative input. In

oscillator mode, this

DC-coupled input has an

internal 100Ω termination

resistor associated with it.

Crystal

Output

XTAL_O G18 I The 50 MHz crystal oscillator

output of the AQR405. This

connects to the output of an

inverting amplifier. In XO

mode, this is high-impedance.

Table 2.14 Timing signals

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The AQR405 contains a high-performance synthesizer, which is capable of

producing all of the clocks required internally, as well as sourcing the recovered 50

MHz CMOS clock for use by other components in the system. This synthesizer

operates from a differential 50 MHz clock. The 50 MHz CMOS clock output is

synchronized to the recovered clock and is thus capable of being used in a

synchronous Ethernet application. Enabling and selection of these clocks is done

via the Global MMD.

2.9 LED

The AQR405 supports three 20 mA open-drain CMOS LED outputs. Configuration

of the LEDs is done via the API.

2.10 Reference Resistors

The AQR405 relies on 1% precision resistors to calibrate its internal voltage levels.

PTP / 1588

Sync

1588_SYNC N15 I The PTP sync input used to

align the PTP clocks on

multiple PHYs on a platform to

have the same time. The PHY

timestamps the rising edge of

this input and this timestamp

can then be used on each of

the PHYs to perform the

alignment.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

PTP External

Clock

CLK_1588_P,

CLK_1588_N

D1, C1 I The PTP differential LVDS

clock input. This input has a

100Ω termination associated

with it, and will operate in the

frequency range of 40 MHz to

160 MHz. This pin should be

AC coupled.

Sync-E

Primary

Clock

CLKO_50M_A D2 O The primary recovered clock

output used for synchronous

Ethernet (Sync-E).

This 20 mA output is on the

VDD_IO domain.

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.14 Timing signals

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Signal Name Pin Name(s) Pin Number(s) Type Description

LED [2:0] LED0, LED1, LED2 K1, L1, M1 OD The 2.5V tolerant, open-drain

LED outputs for PHY.

These open-drain 20 mA

outputs are on the VDD_IO

domain.

Table 2.15 LED signals

Signal Name Pin Name(s) Pin Number(s) Type Description

Bandgap

Reference

Resistor

RREF_BG A10 Analog The connection point for the

bandgap reference resistor.

This should be a precision 1%,

2.00 kΩ resistor tied to ground.

Table 2.16 Reference Resistors signals

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2.11 Test

The AQR405 supports a IEEE 1149.1 compliant JTAG interface, with 1149.6 AC

JTAG support on the SERDES interface. Note that for normal operation, TRST_N

should be held low.

2.12 Metrology

The AQR405 contains two thermal diodes which can be used to monitor the die

temperature without going through the MDIO registers. The “P” indicates the anode

Signal Name Pin Name(s) Pin Number(s) Type Description

JTAG Clock TCK K14 I The JTAG clock input.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

JTAG Data

Input

TDI L14 I The JTAG data input signal.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

JTAG Data

Output

TDO L15 O The JTAG data output signal.

This 20 mA output is on the

VDD_IO domain.

JTAG Reset TRST_N M15 I The JTAG reset signal. If

JTAG is not used, this pin must

be pulled low.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

JTAG Test

Mode State

TMS M16 I The JTAG test mode state

signal.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

Table 2.17 Test signals

Signal Name Pin Name(s) Pin Number(s) Type Description

Thermal

Diode

TDIO_P, TDIO_N G3, F3 Analog Thermal diode terminals.

Table 2.18 Metrology signals

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terminal (i.e. current input) of the thermal diode.

2.13 Wake-On-LAN

For Wake-On-LAN functionality, the AQR405 uses the PRST* input to sense the

state of the PCI Express PERST# signal which is low when the main power is

turned off (i.e. the processor is in the S3 state). It uses WAKE to drive the PCI

Express WAKE# wake-up signal through an external open-drain buffer.

2.14 Debug

The AQR405 supports a side-access port to the MDIO register space via a slave

SMBus. Addressing for this SMBus is provisioned on a per PHY basis. It is

Signal Name Pin Name(s) Pin Number(s) Type Description

PERST* PERST_N L3 I PCI-Express Reset* input.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

Wake WAKE K3 O Wake signal.

This 20 mA output is on the

VDD_IO domain.

Table 2.19 Wake-On-LAN signals

Signal Name Pin Name(s) Pin Number(s) Type Description

SMBus Clock SMB_CLK H17 I Clock signal for slave SMBus

used for debug port into PHY

MDIO register space. This

signal requires a pull-up to

VDD_IO.

This input is on the VDD_IO

domain and has a pull-down

associated with it.

SMBus Data SMB_DAT H18 I/O Data signal for slave SMBus

used for debug port into PHY

MDIO register space. This

signal requires a pull-up to

VDD_IO.

This 20 mA I/O is on the

VDD_IO domain and has a

pull-down associated with it.

Table 2.20 Debug signals

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recommended that every design connect these SMBus pins to a header to allow

in-system debug. This obviates the need to disconnect the MDIO lines, and allows

for normal system operation during debug.

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2.15 Power

Signal Name Pin Name(s) Pin Number(s) Type Description

AVDD VA12 D4, D6, E5, E7,

Supply 1.2V analog supply.

AVDD22 VA22 A3, A5, A7, A9,

C3, C5, C7, C9

Supply 2.1V analog supply.

AVSS AVSS B3, B5, B7, B9,

B12, B14, B16,

C2, C4, C6, C8,

C11, C13, C15,

C17, D3, D5,

D7, D9, D12,

D14, D16, D18,

E4, E11, E13,

E15, E17, F6,

F8, F10, F12,

G5, G7, G9,

G11, H6, H8,

H10, H12

Supply Analog ground.

AVSS PLL AVSS_PLL E6 Supply Analog ground for PHY PLL.

Analog VDD AFE_DVDD E10 Supply 0.85V supply for digital

circuitry in the AFE.

VCC Crystal VA22_XTAL E18 Supply 2.1V supply for the crystal

oscillator.

VDD VDD J6, J8, J10,

J12, K5, K7,

K9, K11, K13,

L6, L8, L10,

L12, M7, M9,

M11, M13, N6,

N8, N10, N12,

P5, P7, P9,

P11, P13, R8,

R10, R12

Supply 0.85V digital supply.

VDD FLASH VDD_FLASH E3 Supply FLASH I/O Power Supply

(2.5V).

VDD IO

Power

Supply

VDD_IO J3, K4, K16,

L16

Supply The power supply for the

general I/O on the AQR405.

High and low logic levels are

scaled to 70% and 30% of the

supply voltage respectively.

Table 2.21 Power signals

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The AQR405 utilizes three separate power supplies to minimize power

consumption:

1) VDD

2) 1.2V

3) 2.1V

VDD IO

Select

MDIO_1P2_SELE

CT_N

H4 I When pulled low, this signal

sets the I/O voltages for MDC,

MDIO, and RST_N to 1.2V

levels, regardless of the

VDD_IO voltage.

This input is on the VDD_IO

domain and has a pull-up

associated with it.

VDD

SERDES

VDD_SRDS R5, T8, T10,

T12

Supply SERDES 0.85V digital supply.

VDD22

SERDES

V22_SRDS P4, R3 Supply SERDES 2.1V supply.

VREG

SERDES

P0_VREG_SRDS T4, T6 Supply 1.8V SERDES regulator

output used for decoupling and

monitoring.

VSS VSS J5, J7, J9, J11,

J13, K6, K8,

K10, K12, L7,

L9, L11, L13,

M6, M8, M10,

M12, N5, N7,

N9, N11, N13,

P6, P8, P10,

P12, R7, R9,

R11, R13

Supply Digital ground.

VSS

SERDES

VSS_SRDS,

VSS_SRDS

P18, P17, , , ,

U18, N1, N2,

P3, R1, R2, R4,

R6, R14, T3,

T5, T7, T9,

T11, T13, U1,

U5, U9, U11,

V5, V9, V11

VSS_

SRDS

SERDES ground.

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.21 Power signals

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As mentioned earlier, in order to provide maximum flexibility to the implementation,

the AQR405 utilizes a programmable I/O voltage. The logic thresholds for the I/O

are set at 70% and 30% of VDD_IO for VIH/VOH and VIL/VOL respectively. For 1.2V

MDIO operation (affects MDC, MDIO, RST_N), a separate signal called

MDIO_1P2_SELECT_N is provided that will force 1.2V operation on these signals,

regardless of the VDD_IO voltage.

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2.16 Reserved

Signal Name Pin Name(s) Pin Number(s) Type Description

Floating NC A11, A12, A13,

A14, A15, A16,

A17, B10, B11,

B13, B15, B17,

B18, C12, C14,

C16, C18, D11,

D13, D15, D17,

E12, E14, E16,

F7, F9, F11,

F14, G6, G8,

G10, G12,

G15, H5, H7,

H9, H11, H13,

J17, K2, K17,

L2, L17, M2,

M3, N3, P15,

R15, R16, R17,

R18, T16, T17,

T18, U10, U12,

U13, U14, U15,

U17, V10, V12,

V13, V14, V15,

V17

n/a These pins are floating in the

package and can be

connected as convenience

dictates.

Reserved

Ground

RG_L4, RG_A1,

RG_A18

L4, A1, A18 I Reserved ground signal.

These pins must be connected

to digital ground in the PCB

design.

These inputs are on the

VDD_IO domain and have

pull-downs associated with

them.

Table 2.22 Reserved signals

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2.17 Pin-Out

The pin-out for the AQR405 is shown on the next page. The signals are color coded

to group similar functionalities together. The view is looking from the top of the chip.

Reserved No

Connect

RNC_E2,

RNC_T14,

RNC_B1,

RNC_F13,

RNC_G14,

RNC_N4,

RNC_M4,

RNC_F4,

RNC_G4,

RNC_C10,

RNC_D10,

RNC_F15,

RNC_G16,

RNC_H15,

RNC_H14,

RNC_J14,

RNC_P14,

RNC_M14,

RNC_N14,

RNC_N16,

RNC_P16,

RNC_V18,

RNC_F16,

RNC_V1,

RNC_M5, RNC_L5

E2, T14, B1,

F13, G14, N4,

M4, F4, G4,

C10, D10, F15,

G16, H15, H14,

J14, P14, M14,

N14, N16, P16,

V18, F16, V1,

M5, L5

n/a Reserved no-connect signal.

These pins must be left

unconnected in the PCB

design.

Signal Name Pin Name(s) Pin Number(s) Type Description

Table 2.22 Reserved signals

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Figure 2.9 AQR405 pin-out

123456789101112131415161718192021222324

RG_A1 P0_VA22 P0_A_N P0_VA22 P0_C_N P0_VA22 P0_CM_N P1_VA22 P1_B_N P1_VA22 P1_D_N RREF_BG0 RREF_BG3 P2_A_N P2_VA22 P2_C_N P2_VA22 P3_CM_N P3_VA22 P3_B_N P3_VA22 P3_D_N P3_VA22 RG_A24

RNC_B1 AVSS P0_A_P AVSS P0_C_P AVSS P0_CM_P AVSS P1_B_P AVSS P1_D_P RREF_BG1 RREF_BG2 P2_A_P AVSS P2_C_P AVSS P3_CM_P AVSS P3_B_P AVSS P3_D_P AVSS RNC_B24

AVSS P0_VA22 AVSS P0_VA22 AVSS P1_VA22 AVSS P1_VA22 AVSS P1_VA22 AVSS RNC_C12 RNC_C13 AVSS P2_VA22 AVSS P2_VA22 AVSS P2_VA22 AVSS P3_VA22 AVSS P3_VA22 SMB_DAT

VA22_XTAL AVSS P0_B_N AVSS P0_D_N AVSS P1_CM_N AVSS P1_A_N AVSS P1_C_N RNC_D12 RNC_D13 P2_B_N AVSS P2_D_N AVSS P2_CM_N AVSS P3_A_N AVSS P3_C_N AVSS SMB_CLK

AVSS AVSS P0_B_P AVSS P0_D_P AVSS P1_CM_P AVSS P1_A_P AVSS P1_C_P AVSS AVSS P2_B_P AVSS P2_D_P AVSS P2_CM_P AVSS P3_A_P AVSS P3_C_P AVSS AVSS

CLK_P VA12_A AVSS VA12_A AVSS VA12_A AVSS VA12_A AVSS VA12_A AVSS AFE_DVDD_A AVSS AVSS VA12_B AVSS VA12_B AVSS VA12_B AVSS VA12_B AVSS VA12_B VA12_B

CLK_N AVSS VA12_A P0_AVSS_PLL VA12_A AVSS VA12_A P1_AVSS_PLL VA12_A AVSS VA12_A AVSS AFE_DVDD_B VA12_B P2_AVSS_PLL VA12_B AVSS VA12_B P3_AVSS_PLL VA12_B AVSS VA12_B AVSS AVSS

DC_MASTER_

NCLK_1588_P CLK_1588_N CLKO_50M_B AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS P3_LED0 TDIO_N_3 TDIO_P_3 VDD_IO RNC_H24

SIN SOUT RG_J3 RNC_J4 RNC_J5 AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS P3_WAKE ADDR4 ADDR3 ADDR2

SCLK CE_N RG_K3 RNC_K4 RNC_K5 NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS P3_LED1 P1_MDC P0_MDC P2_MDC P3_MDC

CLKO_50M_A RST_OUT_N P0_WAKE VDD_IO MDIO_1P2_SE

LECT_N AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC AVSS NC P3_LED2 P1_INT_N P0_INT_N P2_INT_N P3_INT_N

RX_DC_DATA TX_DC_RST_

NVDD_FLASH TDIO_N_0 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS P3_PERST_N P1_MDIO P0_MDIO P2_MDIO P3_MDIO

RX_DC_CLK RX_DC_SOF P0_PERST_N TDIO_P_0 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD P2_LED2 P2_WAKE P2_PERST_N TX_DC_DATA TX_DC_SOF

P1_LED0 P1_LED1 P1_LED2 P1_WAKE VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD RNC_P19 P2_LED1 RNC_P21 RNC_P22 RX_DC_RST_

NTX_DC_CLK

P0_LED0 P0_LED1 P0_LED2 INV_ADDR1 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS RNC_R19 P2_LED0 RNC_R21 TCK NC VDD_IO

RST_N INV_ADDR0 P1_PERST_N RNC_T4 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS 1588_SYNC TDI TDO TRST_N TMS

VSS_SRDS VSS_SRDS VDD_IO RNC_U4 VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD_SENS

ERNC_U21 RNC_U22 VSS_SRDS VSS_SRDS

P0_RX_LN0_N P0_RX_LN0_P VSS_SRDS VDD_SRDS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD_SRDS VSS_SRDS P3_TX_LN2_P P3_TX_LN2_N

VSS_SRDS VSS_SRDS V22_SRDS VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS VSS_SRDS V22_SRDS VSS_SRDS VSS_SRDS

P0_TX_LN0_N P0_TX_LN0_P VSS_SRDS VDD_SRDS VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VSS_SRDS NC VDD_SRDS RNC_Y22 P3_RX_LN2_P P3_RX_LN2_N

VSS_SRDS VSS_SRDS V22_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS VDD_SRDS VSS_SRDS V22_SRDS VSS_SRDS VSS_SRDS

P0_RX_LN2_N P0_RX_LN2_P RNC_AB3 P0_VREG_

SRDS VSS_SRDS P0_VREG_

SRDS RNC_AB7 P1_VREG_

SRDS VSS_SRDS P1_VREG_

SRDS VSS_SRDS V22_SRDS VSS_SRDS V22_SRDS P2_VREG_

SRDS VSS_SRDS P2_VREG_

SRDS RNC_AB18 P3_VREG_

SRDS VSS_SRDS P3_VREG_

SRDS VSS_SRDS P3_TX_LN0_P P3_TX_LN0_N

VSS_SRDS VSS_SRDS P0_TX_LN2_P VSS_SRDS P1_RX_LN0_P VSS_SRDS P1_TX_LN0_P VSS_SRDS P1_RX_LN2_P VSS_SRDS P1_TX_LN2_P VSS_SRDS VSS_SRDS P2_RX_LN0_P VSS_SRDS P2_TX_LN0_P VSS_SRDS P2_RX_LN2_P VSS_SRDS P2_TX_LN2_P VSS_SRDS P3_RX_LN0_P VSS_SRDS VSS_SRDS

RG_AD1 VSS_SRDS P0_TX_LN2_N VSS_SRDS P1_RX_LN0_N VSS_SRDS P1_TX_LN0_N VSS_SRDS P1_RX_LN2_N VSS_SRDS P1_TX_LN2_N VSS_SRDS VSS_SRDS P2_RX_LN0_N VSS_SRDS P2_TX_LN0_N VSS_SRDS P2_RX_LN2_N VSS_SRDS P2_TX_LN2_N VSS_SRDS P3_RX_LN0_N VSS_SRDS RG_AD24

123456789101112131415161718192021222324

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Timing 3-

3.1 MDIO

Data is sampled on the rising edge of MDC at the PHY, and at the STA.

Figure 3.1 MDIO setup and hold times

Symbol Parameter Test Condition Min Typ Max Units

fMDC MDC Frequency 10.5 MHz

tLMDC Low Time 20 ns

tHMDC High Time 20 ns

tSETUP Input Setup Time 8 ns

tHOLD_IN Input Hold Time 10 ns

tHOLD_OUT Output Hold Time 29 38 ns

Table 3.1 MDIO timing

1/ fMDC

VIH

VIL

MDC

VIH

VIL

VIH

VIL

MDC

tSETUP tHOLD_IN

VIH

VIL

MDIO Input

VIH

VIL

VIH

VIL

MDIO Input

VIH

VIL

MDC

VIH

VIL

VIH

VIL

MDC

VIH

VIL

MDIO Output

VIH

VIL

VIH

VIL

MDIO Output

tHOLD_OUT

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3.2 Interrupt

3.3 Reset

Figure 3.2 Interrupt timing diagram

Symbol Parameter Test Condition Min Typ Max Units

tFFall Time 1 ns

tRRise Time 1 ns

tINT Interrupt Time n/a1

1. INT* stays low until the interrupt is serviced

Table 3.2 Interrupt timing

Figure 3.3 Reset timing diagram

Symbol Parameter Test Condition Min Typ Max Units

tRESET Reset Time 100 ms

tFFall Time 1 ns

tRRise Time 1 ns

tRESET_OUT Reset Out Time fC = 50.00 MHz 20 ms

Table 3.3 Reset timing

tINT

VIH

VIL

MD_IN T*

VIH

VIL

VIH

VIL

MD_IN T*

tFtR

tRESET

VIH

VIL

RST*

VIH

VIL

VIH

VIL

RST*

tRESET_OUT

VIH

VIL

RST_OUT*

VIH

VIL

VIH

VIL

RST_OUT*

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3.4 SPI

Figure 3.4 SPI timing diagram

Symbol Parameter Test Conditions Min Typ Max Units

fSCLK SCLK Clock

Frequency1

1. An attached FLASH device which supports 40 MHz operation, must have a tV

(output valid time) of less than 12.5 ns.

050.0MHz

tHSCLK High Time 12 ns

tLSCLK Low Time 12 ns

tCE CE* High Time 50 ns

tCES CE* Setup Time 25 ns

tCEH CE* Hold Time 25 ns

tSU SIN Setup Time 14 ns

tHI SIN Hold Time -4 ns

tVSOUT Output Valid 4 ns

tHO SOUT Hold Time -4 ns

Table 3.4 SPI timing

CE*

SCLK

SIN

SOUT

CEH

CES

VALID IN

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3.5 Daisy-chain

Figure 3.5 Daisy-chain timing diagram

Symbol Parameter Test Conditions Min Typ Max Units

fDC_CLK Daisy-chain Clock

Frequency

020MHz

tHSCLK High Time 22 ns

tLSCLK Low Time 22 ns

tOUT Daisy-chain Output 0 4 ns

tSETUP Daisy-chain Input

Setup

4ns

tHOLD Daisy-chain Input

Hold

2ns

tRST_N Daisy-chain Reset15ns

Table 3.5 Daisy-chain timing

1/ fDC_CLK

VIH

VIL

TX_DC_CLK

VIH

VIL

VIH

VIL

TX_DC_CLK

tOUT

VIH

VIL

TX_DC_SOF

VIH

VIL

VIH

VIL

TX_DC_SOF

VIH

VIL

TX_DC_DATA

VIH

VIL

VIH

VIL

TX_DC_DATA

VIH

VIL

TX_DC_RST_N

VIH

VIL

VIH

VIL

TX_DC_RST_N

tRST_N

VIH

VIL

RX_DC_CLK

VIH

VIL

VIH

VIL

RX_DC_CLK

tSETUP tHOLD

VIH

VIL

RX_DC_SOF

VIH

VIL

VIH

VIL

RX_DC_SOF

VIH

VIL

RX_DC_DATA

VIH

VIL

VIH

VIL

RX_DC_DATA

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3.6 SERDES

The measurement BW for these specs is from to , as the tracking

bandwidth of the PLL for the SERDES is up to . For instance, for KR, the

symbol rate is 10.3125 GHz, so . Thus the measurement BW for

the integrated jitter is from roughly 6 MHz to infinity.

1. TX_DC_RST_N stays low until the slave(s) finish loading. Also - note that this

is an asynchronous input.

Maximum

Total Jitter

(TJMAX)

Maximum

Random

Jitter

(RJMAX)

Maximum

Data

Dependent

Jitter

(DDJMAX)

Maximum

Deterministi

c Jitter

(DJMAX)

Maximum

Periodic

Jitter

(PJMAX)Units

1.00 0.25 0.55 0.10 0.10 UIpp

Table 3.6 SERDES receiver jitter tolerance specifications

Maximum Total

Jitter (TJMAX)

Maximum

Random Jitter

(RJMAX)

Maximum

Deterministic

Jitter (DJMAX)

Maximum

Periodic Jitter

(PJMAX)Units

0.25 0.15 0.05 0.05 UIpp

Table 3.7 SERDES transmit jitter tolerance specifications

SYMBOL

1667

-------------------- ∞

SYMBOL

1667

--------------------

SYMBOL

1667

-------------------- 6 MHZ≅

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3.7 RXAUI Transmit

3.8 RXAUI Receive

Figure 3.6 RXAUI transmit timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fSSymbol Rate 6.25 GS/s

tSKEW_TX Transmit Skew Between any

two channels

TBD TBD Symbols

Table 3.8 RXAUI transmit timing

Figure 3.7 RXAUI receive timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fRX Receive Symbol Rate 6.25 GS/s

ΔfFrequency Tolerance -300 300 ppm

tSKEW_RX Receiver Skew Tolerance Between any

two channels

TBD Symbols

Table 3.9 RXAUI receive timing

1/fS

VIH-DIFF

VIL-DIFF

VIH-DIFF

VIL-DIFF

Lane 0 Tx

tj_TX

VIH-DIFF

VIL-DIFF

VIH-DIFF

VIL-DIFF

Lane n Tx

tSKEW_TX

1/(fRX+Δf)

VIH-DIFF

VIL-DIFF

VIH-DIFF

VIL-DIFF

Lane 0 Rx

tj_TOL

VIH-DIFF

VIL-DIFF

VIH-DIFF

VIL-DIFF

Lane n Rx

tSKEW_RX

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3.9 SGMII Transmit

3.10 SGMII Receive

Figure 3.8 SGMII transmit timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fSSymbol Rate 1.25 GS/s

Table 3.10 SGMII transmit timing

Figure 3.9 SGMII receive timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fRX Receive Symbol Rate 1.25 GS/s

ΔfFrequency Tolerance -300 300 ppm

Table 3.11 SGMII receive timing

1/fS

VIH- DI FF

VIL-DIFF

VIH- DI FF

VIL-DIFF

SGMII Tx

tj_TX

1/(fRX+Δf)

VIH- D IF F

VIL-DIFF

VIH- D IF F

VIL-DIFF

SGMII Rx

tj_TOL

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3.11 KR Transmit

3.12 KR Receive

Figure 3.10 KR transmit timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fSSymbol Rate 10.3125 GS/s

Table 3.12 KR transmit timing

Figure 3.11 KR receive timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fRX Receive Symbol Rate 10.3125 GS/s

ΔfFrequency Tolerance -50 50 ppm

Table 3.13 KR receive timing

1/f

IH-DIFF

IL-DIFF

KR Tx

j_TX

1/(f

+'f)

IH-DIFF

IL-DIFF

KR Rx

j_TOL

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3.13 2500BASE-X Transmit

3.14 2500BASE-X Receive

Figure 3.12 2500BASE-X transmit timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fSSymbol Rate 3.125 GS/s

Table 3.14 2500BASE-X transmit timing

Figure 3.13 2500BASE-X receive timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fRX Receive Symbol Rate 3.125 GS/s

ΔfFrequency Tolerance -300 300 ppm

Table 3.15 2500BASE-X receive timing

1/f

IH-DIFF

IL-DIFF

2500BASE-X Tx

j_TX

1/(f

+'f)

IH-DIFF

IL-DIFF

2500BASE-X Rx

j_TOL

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3.15 Clocks

3.15.1 Input

The phase noise of the 50 MHz input clock should be at least as good as the mask

shown below:

Figure 3.14 50 MHz input timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fCClock Frequency 50.0 MHz

ΔfFrequency Tolerance -50 50 ppm

tjRMS Jitter1

1. This includes all period jitter and tones

12 kHz - 20 MHz 1.0 ps

DC Duty Cycle 45 55 %

Table 3.16 50.000 MHz input timing

Figure 3.15 50.000 MHz phase noise mask

VIH

VIL

Oscillator

Clock Input

VIH

VIL

VIH

VIL

Oscillator

Clock Input

1/(fC+Δf)

10 1,000 100,000 10,000,000

Frequency (Hz)

Phase Noise (dBc/Hz)

-20

-40

-60

-80

-100

-120

-140

-160

-180

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3.15.2 Output

The timing information for the AQR405 output clocks (CLKO_50M_A and

CLKO_50M_B) are shown below. Note that the 50 MHz clock is phase-locked to

the incoming receive signal in 1G and 10G slave mode. The result is that their

frequency accuracy in these modes is a function of the far-end device’s clock

accuracy.

Figure 3.16 50 MHz reference clock output timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fCClock Frequency 50.000 MHz

ΔfFrequency Tolerance -50 50 ppm

tjRMS Period Jitter 1 ps

tLClock Low Time 8 12 ns

tHClock High Time 8 12 ns

tR / tFClock Rise / Fall Time 6 pF load 2 ns

DC Duty Cycle 45 55 %

Table 3.17 50 MHz reference clock output timing

VIH

VIL

Ref_CLK

Output

VIH

VIL

VIH

VIL

Ref_CLK

Output

1/(fC+Δf)

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3.16 JTAG

Figure 3.17 JTAG timing diagram

Symbol Parameter Test Condition Min Typ Max Units

fTCK Clock Frequency 20 MHz

tLClock Low Time 20 ns

tHClock High Time 20 ns

tSETUP Input Setup Time 5 ns

tHOLD_IN Input Hold Time 15 ns

tHOLD_OUT Output Hold Time 10 22 ns

Table 3.18 JTAG timing

1/ fTCK

VIH

VIL

TCK

VIH

VIL

VIH

VIL

TCK

tSETUP tHOLD_IN

VIH

VIL

VIH

VIL

TDI

TMS

VIH

VIL

TDO

VIH

VIL

VIH

VIL

TDO

tHOLD_OUT

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Electrical Specifications 4-

4.1 Absolute Maximum Ratings

4.2 Recommended Operating Conditions

4.3 Power

The AQR405 automatically adjusts is power consumption based on the length of

the channel: consequently there is no explicit “short reach mode”†. However the

Symbol Parameter Test Condition Min Max Units

VDD 0.85V Digital Supply -0.5 0.935 V

VA12 1.2V Analog Supply -0.5 1.32 V

VA22 2.1V Analog Supply -0.5 2.31 V

VDD_IO

2.1V VDD General I/O Supply -0.5 2.75 V

2.5V VDD General I/O Supply -0.5 2.75 V

VDD_FLASH 2.5V FLASH I/O Supply -0.5 2.75 V

VESD ESD on all pins except Line

HBM 2 kV

CDM 500 V

MM 200 V

VCO Cable discharge on Line 100 m cable 2 kV

TSTORE Storage Temperature -50 150 °C

Table 4.1 AQR405 absolute maximum ratings

Symbol Parameter Test Condition Min Max Units

TJJunction Temperature 0 108 °C

TJST Short-Term Junction Temperature1

1. In order to not degrade the life of the part, the AQR405 should not be operated at this

temperature for more than 1 week / year.

0110°C

Table 4.2 AQR405 recommended operating conditions

†Thus when PHY power consumption is characterized at 30m, it is simply what the power

consumption of the PHY is when operating on a 30m link.

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power consumption of the AQR405 can be characterized over the IEEE 30m

short-reach channel. The following tables specify the power-supply requirements

and operating power per port for the AQR405 in both full-reach and short reach

operation.

4.3.1 Operating Modes

The AQR405 has several different operating regimes that each use different

amounts of power. These regimes are listed below, and power consumption for

each of these regimes is given in Table 4.4.

1) Low power (LP): In this mode, everything is shut off except the internal

microprocessor and the MDIO interface. It is designed for out-of-service

ports, and is the lowest power operating mode.

2) Autonegotiation (ANEG): In this mode, the AQR405 is attempting to

autonegotiate with the far-end PHY and is sending and trying to receive

link pulses. This is the second lower operating power mode, and usually

last between 1.6 and 1.8 seconds†.

3) 10G Training (TRNG): This is the highest power mode, and occurs at

the beginning of a 10GBASE-T session. This training mode lasts for a

maximum of 2 seconds. This sets the maximum requirements for the

VA12, VA22, and VDD power supplies.

4) 10G Steady-state Operation (10GSS): This is the second highest

power mode, and occurs during normal 10GBASE-T operation. This sets

the maximum requirements for the thermal design, and the maximum for

the VDD power supply.

5) 5G Steady-state Operation (5GSS): This is the power seen during

normal 5G AQRate operation

6) 2.5G Steady-state Operation (2.5GSS): This is the power seen during

normal 2.5G AQRate operation.

7) 1G Steady-state Operation (1GSS): This is the power seen during

normal 1000BASE-T operation.

8) 100M Steady-state Operation (100MSS): This is the power seen during

normal 100BASE-TX operation.

†This autonegotiation time assumes that an active link-partner is present. If one is not

present, the AQR405 will continue attempting to autonegotiate until a PHY is connected.

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An example of the power consumption versus time for some of these modes in 10G

operation is shown in Figure 4.1. In this figure, the device starts off in low-power

mode, and then at time t, the AQR405 is enabled, and autonegotiation begins. After

10GBASE-T is agreed on as the connection rate, 10GBASE-T training starts, and

then after 2 seconds, 10GBASE-T steady-state is entered into.

4.4 Full-Reach Power Supplies

4.4.1 Full-Reach VA22 and VA12 Supply Specifications

The following tables provide the per port analog VA22 and VA12 power supply

requirements for the AQR405 operating in full-reach mode.

VA22 includes the following supplies: Px_VA22, VA22_XTAL and V22_SRDS.

Figure 4.1 Power versus time

t+1 t+2 t+3 t

Time (seconds)

Power

0 t+4

Low Power

Autonegotiation

~1.6 seconds

PHY is enabled

10G Training

~2 seconds

Steady

State

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VA12 includes the follwoing supplies: VA12_A and VA12_B..

4.4.2 Full-Reach VDD Supply Specifications

The following tables provide the per port digital VDD power supply requirements

for the AQR405 operating in full-reach mode with a fixed supply.

VDD includes the following supplies: VDD_SRDS, AFE_DVDD_A, AFE_DVDD_B

and the core supply..

Symbol Parameter Test Condition Min Typ Max Units

VA22 TOTAL Input Voltage1

1. The input voltage is specified as DC accuracy.

2.037 2.10 2.163 V

VA22 RIPPLE Input Voltage Ripple Peak to Peak 0 13 mV

IVA22 TOTAL Input Current 10G Training2

2. This assumes KR start-up

510 mA

IVA22 TOTAL Input Current 10G

Steady-State

480 mA

Table 4.3 Full-reach VA22 electrical parameters

Symbol Parameter Test Condition Min Typ Max Units

VA12 TOTAL Input Voltage1

1. The input voltage is specified as DC accuracy.

1.164 1.20 1.236 V

VA12 RIPPLE Input Voltage Ripple Peak to Peak 0 48 mV

IVA12 TOTAL Input Current 10G Training2

2. This assumes KR start-up

350 mA

IVA12 TOTAL Input Current 10G

Steady-State

300 mA

Table 4.4 Full-reach VA12 electrical parameters

Symbol Parameter Test Condition Min Typ Max Units

VVDD TOTAL Input Voltage10.8245 0.850 0.8755 V

VVDD RIPPLE Input Voltage Ripple Peak to Peak 0 34 mV

IVDD TOTAL Input Current 10G Training23670 mA

IVDD TOTAL Input Current 10G

Steady-State

3050 mA

Table 4.5 Full-reach VDD fixed supply electrical parameters

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4.5 Other Power Supplies

4.5.1 VDD_IO and VDD_FLASH Supply Specifications

The following tables provide power supply requirements for the VDD_IO and

VDD_FLASH power supplies for the AQR405.

VDD_IO operates on 2.1V or 2.5V.

VDD_FLASH only operates on 2.5V. .

1. The input voltage is specified as DC accuracy.

2. This assumes KR start-up

Symbol Parameter Test Condition Min Typ Max Units

VDD_IO TOTAL 2.1 V Input

Voltage1The input

voltage is specified

as DC accuracy.

1. The input voltage is specified as DC accuracy.

2.037 2.10 2.163 V

VDD_IO RIPPLE 2.1V Input Voltage

Ripple

Peak to Peak 0 84 mV

IVDD_IO TOTAL 2.1V Input Current 10G Training2

2. This assumes KR start-up

TBD mA

IVDD_IO TOTAL 2.1V Input Current 10G

Steady-State

TBD mA

VDD_IO TOTAL 2.5 V Input Voltage1 2.425 2.50 2.575 V

VDD_IO RIPPLE 2.5V Input Voltage

Ripple

Peak to Peak 0 100 mV

IVDD_IO TOTAL 2.5V Input Current 10G Training2TBD mA

IVDD_IO TOTAL 2.5V Input Current 10G

Steady-State

TBD mA

Table 4.6 VDD_IO electrical parameters

Symbol Parameter Test Condition Min Typ Max Units

VDD_FLASH TOTAL Input Voltage12.425 2.50 2.575 V

Table 4.7 VDD_FLASH electrical parameters

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4.6 Management Interface

The management interface includes the following signals:

1) MDC

2) MDIO

3) RST_N

VDD_FLASH RIPPLE Input Voltage Ripple Peak to Peak 0 100 mV

IVDD_FLASH TOTAL Input Current 10G Training220 mA

IVDD_FLASH TOTAL Input Current 10G

Steady-State

20 mA

1. The input voltage is specified as DC accuracy.

2. This assumes KR start-up

Symbol Parameter Test Condition Min Typ Max Units

VIL Input low voltage 0.36 V

VIH Input high voltage 0.84 V

VOL Output low voltage IOL = -4 mA 0.0 0.2 V

VOH Output high voltage

IOH =0 mA 1.0 1.5 V

IOH = 10 mA 0.96 1.5 V

IOH = 20 mA 0.9 1.5 V

IOL Output low current VOL = 0.2 V 4 mA

IOH1

1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line)

Output high current VOH = 1.0 V 0 mA

ILKG Tristate Leakage VIN = 0 V or VCC -10 10 μA

CiInput capacitance 10 pF

CLMaximum capacitive load 470 pF

Table 4.8 1.2V mode MDIO electrical interface characteristics

Symbol Parameter Test Condition Min Typ Max Units

Table 4.7 VDD_FLASH electrical parameters

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4.7 I/O

All of the non-management interface I/O on the AQR405 run from either VDD_IO

or VDD_FLASH and use the same I/O cell that has the following characteristics:

Symbol Parameter Test Condition Min Typ Max Units

VIL Input low voltage 30 %VDD_IO

VIH Input high voltage 70 %VDD_IO

VOL Output low voltage IOL = -4 mA 0 20 %VDD_IO

VOH Output high voltage IOH =0 mA 80 120 %VDD_IO

IOH = 20 mA 80 120 %VDD_IO

IOL Output low current VOL = 20% VDD_IO 4 mA

IOH1Output high current VOH = 80% VDD_IO 0 mA

ILKG Tristate Leakage VIN = 0 V or VCC -10 10 μA

CiInput capacitance 10 pF

CLMaximum capacitive

load

120 pF

Table 4.9 70% / 30% VDD_IO mode MDIO electrical interface characteristics

1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line)

Symbol Parameter Test Condition Min Typ Max Units

VIL Input low voltage 30 %VDD_IO

VIH Input high voltage 70 %VDD_IO

VOL Output low voltage IOL = -4 mA 0 20 %VDD_IO

VOH Output high voltage IOH =0 mA 80 120 %VDD_IO

IOH = 20 mA 80 120 %VDD_IO

IOL Output low current VOL = 20%

VDD_IO

4mA

IOH1Output high current VOH = 80%

VDD_IO

0mA

Table 4.10 I/O pin electrical parameters

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4.8 Serial FLASH

The SPI interface is 2.5 V tolerant.

ILKG Tristate Leakage VIN = 0 V or

VCC

-10 10 μA

CiInput capacitance 10 pF

CLMaximum capacitive load 120 pF

1. IOH parameter is not applicable to open drain drivers (i.e. MDIO data line)

Symbol Parameter Test Condition Max Units

COUT Output Capacitance (SCLK, CS*, SOUT) VOUT = 0 V 5 pF

CIN Input Capacitance (SIN) VIN = 0 V 5 pF

Table 4.11 SPI pin capacitance

Symbol Parameter Test Condition Min Typ Max Units

ILKG Tristate Leakage VIN = 0 V or VCC -10 10 μA

VIL Input Low Voltage 20 %VDD_FLASH

VIH Input High Voltage 80 %VDD_FLASH

VOL Output Low Voltage IOL = 4 mA 20 %VDD_FLASH

VOH Output High Voltage IOH = -4 mA 80 %VDD_FLASH

IOL Output low current 4 mA

IOH Output high current -4 mA

Table 4.12 SPI DC Characteristics

Symbol Parameter Test Condition Min Typ Max Units

Table 4.10 I/O pin electrical parameters

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4.9 SERDES

4.10 Line (MDI)

The AQR405 uses a voltage-mode driver to drive the MDI, so only decoupling is

required on the transformer center-tap.

Parameter Test Condition Min Typ Max Units

Output Voltage1

1. Near end programmable output range

Peak-to-peak differential 400 1400 mV

Transmit Common Mode Voltage 200 700 mV

Differential Output Impedance Programmable 80 100 120 Ω

Common Mode Output Impedance 20 25 30 Ω

Table 4.13 SERDES transmitter characteristics

Parameter Test Condition Min Typ Max Units

Input Voltage Peak-to-peak differential 50 2000 mV

Input Common Mode Voltage Peak-to-peak differential 650 1000 mV

Input Loss of Signal Voltage Peak-to-peak differential 75 120 175 mV

Differential Input Impedance1

1. This is programmable to ±10%

Programmable 80 120 Ω

Common Mode Input Impedance 20 25 27.5 Ω

Receiver Differential Return Loss DC -20 dB

5 GHz -5 dB

Receiver Common-Mode Return

Loss

DC -10 dB

5 GHz -6 dB

Table 4.14 SERDES receiver characteristics

Symbol Parameter Test Condition Min Typ Max Units

VOH-DIFF Differential Output Voltage 2.0 Vpk-pk

CIN Input Capacitance 2.5 pF

RIN Input Resistance 48 50 52 Ω

Table 4.15 MDI electrical parameters

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4.11 Reference Clocks

4.11.1 Input Clock Pins CLK_P and CLK_N - LVDS

4.11.2 Input Clock Pins CLK_1588_P and CLK_1588_N

Symbol Parameter Min Typ Max Units

VSWING Single-Ended Input Voltage Swing 0.35 V

VCOMMON Common-Mode Voltage Level 1.2 V

VIH Input High 1.375 V

VIL Input Low 1.025 V

CIN Input Capacitance 1 pF

ZIN-DIFF Input Impedance 100 Ω

RIN-DIFF Input Termination 100 Ω

Table 4.16 LVDS 50MHz input electrical parameters

Symbol Parameter Min Typ Max Units

VSWING Single-Ended Input Voltage Swing -0.175 V

VCOMMON Common-Mode Voltage Level1

1. CLK_1588 support AC-coupled LVDS and LVPECL clock

0.175 V

VIH Input High 1.35 1.45 1.1025 V

VIL Input Low 0.55 0.65 0.75 V

fCLK_1588 Operating Frequency 40 160 MHz

CIN Input Capacitance 1 pF

ZIN-DIFF Input Impedance 100 Ω

RIN-DIFF Input Termination 100 Ω

Table 4.17 CLK_1588 input electrical parameters

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4.12 Reference Resistors

Parameter Test Condition Min Typ Max Units

Reference Resistance Tied to 0V 2.00 kΩ

Resistor Accuracy 1 %

Maximum Power 5 mW

Temperature Variation 50 ppm/°C

Table 4.18 Bandgap reference resistor electrical parameters

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Package 5-

5.1 Mechanical

The AQR405 is packaged in a 25 mm x 25 mm flip-chip 576 pin FCBGA (24 rows

x 24 rows), with a thermal heat spreader. The mechanical drawings of this package

are shown in Figure 5.1.

Figure 5.1 AQR405 package drawing

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5.2 Thermal

5.2.1 Theta J’s

The AQR405 utilizes an copper heat spreader that is directly attached to the back

of the die with thermal epoxy. The result is a low θJC path to the top of the package,

and a relatively low θJB to the board. The values of the various θJ’s are given in

Table 5.1:

5.2.2 Thermal Model

For the AQR405, Aquantia supplies a Flotherm® PDML model.

Name Thermal

Coefficient

Test Condition Value Units

Theta Junction to Ambient

(no PCB thermal vias) θJA Still air at 55°C 11.1 °C/W

Theta Junction to Ambient

(PCB thermal vias) θJA Still air at 55°C 9.98 °C/W

Theta Junction to Board θJB JEDEC 2s2p1

1. Top/bottom trace 2 oz. copper

Middle planes 1 oz. copper

Equivalent 20% 2 oz. copper coverage adjacent to package

Bottom copper 2 oz. 20% coverage

4.69 °C/W

Theta Junction to Case θJC MIL STD 883e 0.42 °C/W

Table 5.1 Theta J’s

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6.1 Introduction

The AQR405 is internally divided into a series of MDIO Manageable Devices

(MMDs), each of which performs a logical function as per the 10GBASE-T

standard. A block diagram of this partitioning is shown below Here the MMD #1

contains the PMA, which is basically the analog front-end of the chip. This is

connected to MMD #3, which contains the PCS, which handles the 10GBASE-T

Figure 6.1 Functional view of AQR405

MMD #30: Global

MMD #7: Autonegotiation

MMD #4:

PHY XS

MMD #3: PCS

MMD #1: PMA

MMD #29:

Clause 22 Extension

RST_OUT_N

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

THP

Precoder

Hybrid

COMMON

MDIO

Management

P[3:0]_MDC

P[3:0]_MDIO

P[3:0]_INT_N

P[3:0]_[D:A]_P,N

MDIO

Power

Supply

VDD

P[3:0]_VA22

VA12

AVSS/VSS

Power

LED I/F

P[3:0]_LED[2:0]

LED

LINE

RST_N

JTAG

TDI

TDO

TCK

TMS

JTAG

TRST_N

RREF_BG[3:0]

Band-

gap

ADDR[4:2]

Timing

RAM

MDIO

Registers

Config

VDD_SENSE

P[3:0]_WAKE

SMB_CLK

SMB_DAT

P[3:0]_PRST*

AQRate 25mm Quad

THP

Precoder

THP

Precoder

THP

Precoder

DAC /

Driver

A/D

THP

Precoder

THP

Precoder

A/D

VGA &

Filter

THP

Precoder

THP

Precoder

VGA &

Filter

DSP

TDIO_P[3,0]

Thermal

Diodes

TDIO_N[3,0]

P[3:0]_CM_P,N

SMBus

WoL

PController

Control

DC_MASTER_N

SCLK

SIN

SOUT

CE_N

Serial

FLASH

I/F

RX_DC_CLK

RX_DC_DATA

RX_DC_SOF

RX_DC_RST_N

TX_DC_CLK

TX_DC_DATA

TX_DC_SOF

TX_DC_RST_N

Daisy-Chain

I/F

FLASH / Daisy Chain

Boot Loader

SRDS0

10G

SRDS2

10G

SERDES

INV_ADDR[1:0]

CLKO_50M_A,B

Timing

50 MHz

CLK_P

CLK_N

CLK_1588_P,N

1588_SYNC

System I/F

P[3:0]_TX_LN0_P,N

P[3:0]_RX_LN0_P,N

P[3:0]_TX_LN2_P,N

P[3:0]_RX_LN2_P,N

Lookaside

5G PCS

1G PCS

100M PCS

KR/USXGMII

PCS 1

SGMII

PCS 1

SGMII

PCS 0

KR/USXGMII

PCS 0

10G PCS

2.5G PCS

XAUI/RXAUI

PCS

REPLICATED

FOUR TIMES

Autonegotiation

MACSEC

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transmission frame coding and decoding, including the 128-DSQ and LDPC work.

This block is in turn connected to MMD #4, which contains the XAUI interface. In

addition to these MMDs, there are three others: MMD #7, which contains the

autonegotiation function, MMD #29, which contains the controls for the GbE and

100M PCS machinery, and MMD# 30, which contains the global control

functionality for the AQR405. Not shown, but present within the AQR405, is

another MMD, #31, which is used for proprietary purposes as an adjunct to the

PMA.

6.2 Register Structure

A map of these regions is shown in Table 6.1. Any attempt to read from the

reserved MMD addresses will return a value of 0x00, and any writes to these

addresses will have no effect.

6.3 Format and Nomenclature

Registers within the device are referenced in the format:

Region . Register . Bit

where Region corresponds to the MMD region being addressed, Register

corresponds to the register within the MMD region, and Bit is the bit within the

5 bit Device

Address (Hex)

MMD Name

0reserved

1 PMA/PMD (128 DSQ)

2reserved

3 PCS (64/65B coder/decoder)

4 PHY XS (XAUI)

5 → 6 reserved

7 Auto-negotiation

8 → 1C reserved

1D Clause 22 Extension

1E Global

1F Aquantia Proprietary

Table 6.1 MMD device addresses

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All read and write operation are word based, which means that the entire 16 bit

there are several different bit types. A list of these bit types are found in Table 6.2.

6.4 Structure

The following structure is used for registers:

1) All Clause 45 registers (registers defined in Clause 45) are placed in their

respective areas within the MMDs as specified.

Abbreviation Type Description

LL Latching Low If the condition the bit is monitoring goes low, this bit

latches low, generates a maskable interrupt, and stays low

until read. Reading this bit resets it to one. This bit is

read-only.

LH Latching High If the condition the bit is monitoring goes high, this bit

latches high, generates a maskable interrupt, and stays

high until read. Reading this bit resets it to zero. This bit is

read-only.

LRF Latch Rising or

Falling

Set high on either a rising or falling edge. If a transition

occurs, this bit latches high, generates a maskable

interrupt, and stays high until read. Reading this bit resets

it to zero. This bit is read-only.

PD Provisionable

Defaults

Indicates that the default value associated with this field is

provisionable.

RO Read Only Read-only field. Writes are ignored.

R/W Read / Write Field can be both read from and written to.

SC Self-Clearing A read/write register which resets itself upon completion of

an action.

SCT Saturating

Counter

A read-only counter that saturates at the limit, and is

cleared on read.

SCTL Saturating

Counter LSW

The Least Significant Word of a Saturating Counter. This

mate MSW to shadow memory, awaiting read.

SCTM Saturating

Counter MSW

The Most Significant Word of a Saturating Counter.

Reading this completes the read process of the register

pair.

Table 6.2 Field types within the MDIO register space

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2) XENPAK / X2 registers are placed in MMD #1

3) Aquantia specific registers associated with each of the Clause 45 MMDs

are placed in the Aquantia specific area beginning at 0xC000, according

to the register map shown in Table 6.3.

The table is split into a transmit portion, and a receive portion, with the

transmit portion also containing any overall Aquantia specific registers

for the MMD. In this table, the following definitions apply:

Base Offset

(Hex)

Description

C000 Tx & Overall MMD Control

C400 Tx & Overall MMD Provisioning

C800 Tx & Overall MMD State

CC00 Tx & Overall MMD Alarms

D000 Standard Interrupt Mask

D400 Tx & Overall MMD Interrupt Mask

D800 Tx & Overall MMD Debug

DC00 reserved

E000 Rx Control

E400 Rx Provisioning

E800 Rx State

EC00 Rx Alarms

F000 Standard Interrupt Mask

F400 Rx Interrupt Mask

F800 Rx Debug

FC00 Global Interrupt Flags

Table 6.3 Register layout

Term Definition

Control Action bits that affect the operation of the MMD, such as reset.

Provisioning Static provisioning bits that control the behavior of the MMD.

State Bits that reflect the state of the MMD.

Table 6.4 Terms used within the register layout

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4) Interrupts are handled in an hierarchical fashion, with the top level

interrupt indication being the INT* interrupt pin on the AQR405. Below

this are two maskable interrupt trees: one composed of standard

interrupts, and one composed of Aquantia defined interrupts. The top

level summary register for these trees resides at the end of the register

space in MMD #30 - the Aquantia Global MMD (1E.FC00). Feeding this

are interrupt registers from each of the individual MMDs.

a) The standard interrupt tree is designed so that the source of any

interrupt can be determined in a maximum of two reads.

b) The Aquantia defined interrupt tree requires at most three reads to

determine the source of an interrupt.

c) All interrupts are maskable, whether they are from the Standard

interrupt tree, or from the Aquantia Specific interrupt tree.

6.5 Registers and Documentation

The registers for the AQR405 are provided in the following tables, listed by the

numerical order of their MMD address. Associated with these registers is a set of

C-language header files and associated Doxygen[8] documentation for them.

These header files contain all of the appropriate C-structures to access the

registers and fields within the registers.

Alarm Bits that can generate maskable interrupts.

Standard Interrupt

Mask

Interrupt masks for alarm bits defined in the Clause 45 register set.

Aquantia Specific

Interrupt Mask

Interrupt masks for Aquantia Specific alarms.

Term Definition

Table 6.4 Terms used within the register layout

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6.6 PMA Registers

6.6.1 PMA Standard Control 1: Address 1.0

Bit Name Description Type Default Note

F Reset 1 = PMA reset

0 = Normal operation

R/W

1 The reset bit is automatically cleared upon

completion of the reset sequence by the

microcontroller. This bit is set to 1 during reset.

The reset is internally stretched by

approximately 1.7 us. Therefore the MDIO or

uP should allow for 1.7 us before writing any

PMA registers after this bit is set.

E Reserved Internal reserved - do not modify

D Speed Selection

LSB

{6,D}

1 1 = Speed set by Bits [5:2]

1 0 = 1000 Mb/s

0 1 = 100 Mb/s

0 0 = 10 Mb/s

R/W

C Reserved Internal reserved - do not modify

B Low Power 1 = Low-power mode

0 = Normal operation

R/W

0 A one written to this register causes the PMA

to enter low-power mode. If a global chip

low-power state is desired, use Bit B in "Global

Standard Control 1: Address 1E.0"

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

A:7 Reserved Internal reserved - do not modify

Table 6.5 PMA Standard Control 1: Address 1.0

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6.6.2 PMA Standard Status 1: Address 1.1

6 Speed Selection

MSB

{6,D}

1 1 = Speed set by Bits [5:2]

1 0 = 1000 Mb/s

0 1 = 100 Mb/s

0 0 = 10 Mb/s

R/W

5:2 10G Speed

Selection [3:0]

1 x x x = Reserved

x 1 x x = Reserved

x x 1 x = Reserved

x x x 1 = 10PASS-TS / 2BASE-TL

0 0 0 0 = 10 Gb/s

ROS 0x0

1 Reserved Internal reserved - do not modify

0 Loopback 1 = Enable loopback mode

0 = Normal operation

R/W

0 This enables the PMA Analog System

Loopback.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Fault 1 = Fault condition detected

0 = No fault detected

RO This is the top-level fault indicator flag for the

PMA. This bit is set if either of the two bits

1.8.B or 1.8.A are set.

6:3 Reserved Internal reserved - do not modify

Table 6.6 PMA Standard Status 1: Address 1.1

Bit Name Description Type Default Note

Table 6.5 PMA Standard Control 1: Address 1.0

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6.6.3 PMA Standard Device Identifier 1: Address 1.2

6.6.4 PMA Standard Device Identifier 2: Address 1.3

2 PMA Receive

Link Status

Status of the PMA receive link

1 = Link up

0 = Link lost since last read

LL This indicates the status of the PMA receive

link. This is the latch version of 1.E800.0. Note

that this is latching low, so it can only be used

to detect link drops, and not the current status

of the link without performing back-to-back

reads.

1Low Power

Ability

1 = PMA supports low-power mode

0 = no low-power mode supported

ROS 1 Indicates whether the PHY supports a

low-power mode

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.7 PMA Standard Device Identifier 1: Address 1.2

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.8 PMA Standard Device Identifier 2: Address 1.3

Bit Name Description Type Default Note

Table 6.6 PMA Standard Status 1: Address 1.1

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6.6.5 PMA Standard Speed Ability: Address 1.4

6.6.6 PMA Standard Devices in Package 1: Address 1.5

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 PMA 10M

Capable

1 = PMA is 10 Mb/s capable

0 = PMA is not 10 Mb/s capable

ROS 0 This is always set to 0 in the AQR405.

5 PMA 100M

Capable

1 = PMA is 100 Mb/s capable

0 = PMA is not 100 Mb/s capable

ROS 1 This is always set to 1 in the AQR405.

4PMA 1G

Capable

1 = PMA is 1 Gb/s capable

0 = PMA is not 1 Gb/s capable

ROS 1 This is always set to 1 in the AQR405.

3 Reserved Internal reserved - do not modify

2 10PASS-TS

Capable

1 = PMA is 10PASS-TS capable

0 = PMA is not 10PASS-TS capable

ROS 0 This is always set to 0 in the AQR405.

1 2BASE-TL

Capable

1 = PMA is 2BASE-TL capable

0 = PMA is not 2BASE-TL capable

ROS 0 This is always set to 0 in the AQR405.

0PMA 10G

Capable

1 = PMA is 10 Gb/s capable

0 = PMA is not 10 Gb/s capable

ROS 1 This is always set to 1 in the AQR405.

Table 6.9 PMA Standard Speed Ability: Address 1.4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

Table 6.10 PMA Standard Devices in Package 1: Address 1.5

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6.6.7 PMA Standard Devices in Package 2: Address 1.6

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no DTE

XAUI interface in the AQR405.

4 PHY XS Present 1 = PHY XS is present in package

0 = PHY XS is not present in package

ROS 1 This is always set to 1 as there is a PHY XS

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the Global registers.

Table 6.11 PMA Standard Devices in Package 2: Address 1.6

Bit Name Description Type Default Note

Table 6.10 PMA Standard Devices in Package 1: Address 1.5

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6.6.8 PMA Standard Control 2: Address 1.7

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the GbE registers.

C:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:0 PMA Device

Type [3:0]

[3:0]

3 2 1 0

1 1 1 1 = 10BASE-T PMA/PMD type

1 1 1 0 = 100BASE-TX PMA/PMD type

1 1 0 1 = 1000BASE-KX PMA/PMD type

1 1 0 0 = 1000BASE-T PMA/PMD type

1 0 1 1 = 10GBASE-KR PMA/PMD type

1 0 1 0 = 10GBASE-KX4 PMA/PMD type

1 0 0 1 = 10GBASE-T PMA type

1 0 0 0 = 10GBASE-LRM PMA/PMD type

0 1 1 1 = 10GBASE-SR PMA/PMD type

0 1 1 0 = 10GBASE-LR PMA/PMD type

0 1 0 1 = 10GBASE-ER PMA/PMD type

0 1 0 0 = 10GBASE-LX4 PMA/PMD type

0 0 1 1 = 10GBASE-SW PMA/PMD type

0 0 1 0 = 10GBASE-LW PMA/PMD type

0 0 0 1 = 10GBASE-EW PMA/PMD type

0 0 0 0 = 10GBASE-CX4 PMA/PMD type

ROS 0x9 This is always set to 0x9 as the AQR405 is

a 10GBASE-T device.

Table 6.12 PMA Standard Control 2: Address 1.7

Bit Name Description Type Default Note

Table 6.11 PMA Standard Devices in Package 2: Address 1.6

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6.6.9 PMA Standard Status 2: Address 1.8

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 0x2, as the

PMA is present in the AQR405.

D Transmit Fault

Location Ability

1 = PMA has the capability to detect a fault

condition on the transmit path

0= PMA does not have the capability to detect a

fault condition on the transmit path

ROS 1 This bit indicates whether the PMA

has the ability to locate faults along the

transmit path.

C Receive Fault

Location Ability

1 = PMA has the capability to detect a fault

condition on the receive path

0= PMA does not have the capability to detect a

fault condition on the receive path

ROS 1 This bit indicates whether the PMA

has the ability to locate faults along the

receive path.

B Transmit Fault 1 = Fault condition on transmit path

0 = No fault condition on transmit path

LH This bit indicates whether there is a

fault somewhere along the transmit

path. This is a hardware fault and

should never occur during normal

operation.

A Receive Fault 1 = Fault condition on receive path

0 = No fault condition on receive path

LH This bit indicates whether there is a

fault somewhere along the receive

path.This is a hardware fault and

should never occur during normal

operation.

9 Extended

Abilities

1 = PMA has extended abilities listed in regsister

1.11

0= PMA does not have extended abilities

ROS 1 This field is set to 1, as the PMA in

AQR405 has extended abilities.

8 PMD Transmit

Disable Ability

1 = PMD has the capability of disabling the

transmitter

0= PMD does not have the capability of disabling

the transmitter

ROS 1 This bit indicates whether the PMD

has the capability of disabling its

transmitter. This field is always set to

0x1, as the PMD in the AQR405 has

this ability.

Table 6.13 PMA Standard Status 2: Address 1.8

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7PMA

10GBASE-SR

Capable

1 = PMA supports 10GBASE-SR

0 = PMA does not support 10GBASE-SR

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

6PMA

10GBASE-LR

Capable

1 = PMA supports 10GBASE-LR

0 = PMA does not support 10GBASE-LR

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

5PMA

10GBASE-ER

Capable

1 = PMA supports 10GBASE-ER

0 = PMA does not support 10GBASE-ER

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

4PMA

10GBASE-LX4

Capable

1 = PMA supports 10GBASE-LX4

0 = PMA does not support 10GBASE-LX4

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

3PMA

10GBASE-SW

Capable

1 = PMA supports 10GBASE-SW

0 = PMA does not support 10GBASE-SW

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

2PMA

10GBASE-LW

Capable

1 = PMA supports 10GBASE-LW

0 = PMA does not support 10GBASE-LW

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

1PMA

10GBASE-EW

Capable

1 = PMA supports 10GBASE-EW

0 = PMA does not support 10GBASE-EW

ROS 0 This field is always set to 0, as the

PMA in the AQR405 only supports

10GBASE-T.

0 PMA Loopback

Ability

1 = PMA supports loopback

0 = PMA does not support loopback

ROS 1 This is always set to 1, as the PMA in

the AQR405 supports loopback.

Bit Name Description Type Default Note

Table 6.13 PMA Standard Status 2: Address 1.8

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6.6.10 PMD Standard Transmit Disable Control: Address 1.9

6.6.11 PMD Standard Signal Detect: Address 1.A

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4 PMD Channel 3

Transmit Disable

1 = Disable output on transmit channel 3

0 = Normal operation

R/W

When disabled, the average launch power on

a pair is set to less than -53 dBm

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

3 PMD Channel 2

Transmit Disable

1 = Disable output on transmit channel 2

0 = Normal operation

R/W

2 PMD Channel 1

Transmit Disable

1 = Disable output on transmit channel 1

0 = Normal operation

R/W

1 PMD Channel 0

Transmit Disable

1 = Disable output on transmit channel 0

0 = Normal operation

R/W

0 PMD Global

Transmit Disable

1 = Disable output on all channels

0 = Normal operation

R/W

0 When set, this bit disables (and overrides) all

four channels, and sets the average launch

power on all pairs to less than -53 dBm

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Table 6.14 PMD Standard Transmit Disable Control: Address 1.9

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

Table 6.15 PMD Standard Signal Detect: Address 1.A

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6.6.12 PMD Standard 10G Extended Ability Register: Address 1.B

4 PMD Channel 3

Signal Detect

1 = Signal detected on receive channel 3

0 = No signal detected

These bits are used to indicate the presence of

signals on a given pair. A signal is defined as

an autonegotiation pulse or Ethernet signals.

3 PMD Channel 2

Signal Detect

1 = Signal detected on receive channel 2

0 = No signal detected

2 PMD Channel 1

Signal Detect

1 = Signal detected on receive channel 1

0 = No signal detected

1 PMD Channel 0

Signal Detect

1 = Signal detected on receive channel 0

0 = No signal detected

0 PMD Global

Signal Detect

1 = Signals detected on all required

channels

0 = No signal detected

RO This bit is marked when all required, valid

Ethernet signals to create a connection are

present on the line.

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 PMA 10BASE-T

Capable

1 = PMA capable of 10BASE-T

0 = PMA incapable of 10BASE-T

ROS 0 This field is always set to 0, as the PMA

in the AQR405 does not support

10BASE-TX.

7PMA

100BASE-TX

Capable

1 = PMA capable of 100BASE-TX

0 = PMA incapable of 100BASE-TX

ROS 1 This field is always set to 1, as the PMA

in the AQR405 supports 100BASE-TX.

6PMA

1000BASE-KX

Capable

1 = PMA capable of 1000BASE-KX

0 = PMA incapable of 1000BASE-KX

ROS 1 This field is always set to 1, as the PMA

in the AQR405 supports 1000BASE-KX.

Table 6.16 PMD Standard 10G Extended Ability Register: Address 1.B

Bit Name Description Type Default Note

Table 6.15 PMD Standard Signal Detect: Address 1.A

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6.6.13 PMA Standard Package Identifier 1: Address 1.E

5PMA

1000BASE-T

Capable

1 = PMA capable of 1000BASE-T

0 = PMA incapable of 1000BASE-T

ROS 1 This field is set to 1, as the PMA in the

AQR405 supports 1000BASE-T.

4PMA

10GBASE-KR

Capable

1 = PMA capable of 10GBASE-KR

0 = PMA incapable of 10GBASE-KR

ROS 1 This field is set to 1, as the PMA in the

AQR405 supports 10GBASE-KR

3PMA

10GBASE-KX4

Capable

1 = PMA capable of 10GBASE-KX4

0 = PMA incapable of 10GBASE-KX4

ROS 1 This field is set to 1, as the PMA in the

AQR405 supports 10GBASE-KX4

2PMA

10GBASE-T

Capable

1 = PMA capable of 10GBASE-T

0 = PMA incapable of 10GBASE-T

ROS 1 This field is set to 1, as the PMA in the

AQR405 supports 10GBASE-T

1PMA

10GBASE-LRM

Capable

1 = PMA capable of 10GBASE-LRM

0 = PMA incapable of 10GBASE-LRM

ROS 0 This field is always set to 0, as the PMA

in the AQR405 does not support

10GBASE-LRM.

0PMA

10GBASE-CX4

Capable

1 = PMA capable of 10GBASE-CX4

0 = PMA incapable of 10GBASE-CX4

ROS 0 This field is always set to 0, as the PMA

in the AQR405 does not support

10GBASE-CX4.

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.17 PMA Standard Package Identifier 1: Address 1.E

Bit Name Description Type Default Note

Table 6.16 PMD Standard 10G Extended Ability Register: Address 1.B

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6.6.14 PMA Standard Package Identifier 2: Address 1.F

6.6.15 PMA 10GBASE-T Status: Address 1.81

6.6.16 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.18 PMA Standard Package Identifier 2: Address 1.F

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Link Partner

Information Valid

1 = 10GBASE-T Link Partner

information is valid

0 = 10GBASE-T Link Partner

information is not valid

RO When set, this bit indicates that the startup

protocol (55.4.2.5) has completed.

Table 6.19 PMA 10GBASE-T Status: Address 1.81

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 Pair Polarity

[3:0]

1 = Polarity of Pair is reversed

0 = Polarity of Pair is normal

[3] = Pair D Polarity

[2] = Pair C Polarity

[1] = Pair B Polarity

[0] = Pair A Polarity

RO When set, this bit indicates that the wires on

the respective pair are reversed.

Table 6.20 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82

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6.6.17 PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83

7:2 Reserved Internal reserved - do not modify

1:0 MDI / MD-X

Connection

State [1:0]

[1:0]

1 1 = No crossover

1 0 = Pair A / B crossover

0 1 = Pair C / D crossover

0 0 = Pair A / B and C / D crossover

RO These two bits indicate the current status of

pair swaps at the MDI / MD-X

Bit Name Description Type Default Note

F:D Link Partner Tx

Power Backoff

[2:0]

[F:D]

0x7 = 14 dB

0x6 = 12 dB

0x5 = 10 dB

0x4 = 8 dB

0x3 = 6 dB

0x2 = 4 dB

0x1 = 2 dB

0x0 = 0 dB

RO The power backoff of the link partner

C:A Tx Power

Backoff [2:0]

[C:A]

0x7 = 14 dB

0x6 = 12 dB

0x5 = 10 dB

0x4 = 8 dB

0x3 = 6 dB

0x2 = 4 dB

0x1 = 2 dB

0x0 = 0 dB

RO The power backoff of the PMA

9:1 Reserved Internal reserved - do not modify

0 Short Reach

Mode

1 = Set PMA to operate in short-reach

mode

0 = PMA is in normal operation

R/W

0 When set, this bit places the PMA into

short-reach mode

Table 6.21 PMA 10GBASE-T Tx Power Backoff and Short Reach Setting: Address 1.83

Bit Name Description Type Default Note

Table 6.20 PMA 10GBASE-T Pair Swap and Polarity Status: Address 1.82

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6.6.18 PMA 10GBASE-T Test Modes: Address 1.84

Bit Name Description Type Default Note

F:D Test Mode

Control [2:0]

[F:D]

0x7 = Pseudo random test mode for BER

Monitor

0x6 = Transmitter Droop test

0x5 = PSD and power level test

0x4 = Transmitter distortion test

0x3 = Slave mode jitter test

0x2 = Master mode jitter test

0x1 = Master source for slave mode jitter test

0x0 = Normal operation

R/W

0x0 Test mode control for the PMA as

defined in Section 55.5.2 of 802.3an.

NOTE!! This is a processor intensive

operation. Completion of this operation

can be monitored via 1E.C831.F

C:A Transmitter Test

Frequencies

[2:0]

[C:A]

0x7 = Reserved

0x6 = Dual Tone #5

0x5 = Dual Tone #4

0x4 = Dual Tone #3

0x3 = Reserved

0x2 = Dual Tone #2

0x1 = Dual Tone #1

0x0 = Reserved

R/W

0x0 The test frequencies associated with

Test Mode #4 in [F:D].

9:0 Reserved Internal reserved - do not modify

Table 6.22 PMA 10GBASE-T Test Modes: Address 1.84

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6.6.19 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85

6.6.20 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86

Bit Name Description Type Default Note

F:0 Channel A

Operating

Margin [F:0]

Operating margin (dB) of Channel A RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.23 PMA 10GBASE-T SNR Operating Margin Channel A: Address 1.85

Bit Name Description Type Default Note

F:0 Channel B

Operating

Margin [F:0]

Operating margin (dB) of Channel B RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.24 PMA 10GBASE-T SNR Operating Margin Channel B: Address 1.86

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6.6.21 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87

6.6.22 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88

Bit Name Description Type Default Note

F:0 Channel C

Operating

Margin [F:0]

Operating margin (dB) of Channel C RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.25 PMA 10GBASE-T SNR Operating Margin Channel C: Address 1.87

Bit Name Description Type Default Note

F:0 Channel D

Operating

Margin [F:0]

Operating margin (dB) of Channel D RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.26 PMA 10GBASE-T SNR Operating Margin Channel D: Address 1.88

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6.6.23 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89

6.6.24 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A

Bit Name Description Type Default Note

F:0 Channel A

Minimum

Operating

Margin [F:0]

Minimum operating margin (dB) of Channel A

since last link up

RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.27 PMA 10GBASE-T SNR Minimum Operating Margin Channel A: Address 1.89

Bit Name Description Type Default Note

F:0 Channel B

Minimum

Operating

Margin [F:0]

Minimum operating margin (dB) of Channel B

since last link up

RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.28 PMA 10GBASE-T SNR Minimum Operating Margin Channel B: Address 1.8A

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6.6.25 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B

6.6.26 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C

Bit Name Description Type Default Note

F:0 Channel C

Minimum

Operating

Margin [F:0]

Minimum operating margin (dB) of Channel C

since last link up

RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.29 PMA 10GBASE-T SNR Minimum Operating Margin Channel C: Address 1.8B

Bit Name Description Type Default Note

F:0 Channel D

Minimum

Operating

Margin [F:0]

Minimum operating margin (dB) of Channel D

since last link up

RO The excess SNR that is enjoyed by the

channel, over and above the minimum

SNR required to operate at a BER of

10-12. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -12.7 dB to 12.7 dB.

The number is in offset binary, with 0.0

dB represented by 0x8000.

Table 6.30 PMA 10GBASE-T SNR Minimum Operating Margin Channel D: Address 1.8C

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6.6.27 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D

6.6.28 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E

6.6.29 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F

Bit Name Description Type Default Note

F:0 Channel A

Received Signal

Power [F:0]

Received signal power (dBm) for Channel A RO The received signal power on the

channel. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -20.0 dB to +5.5dB.

The number is in offset two’s

complement notation, with 0.0 dB

represented by 0x8000.

Table 6.31 PMA 10GBASE-T Receive Signal Power Channel A: Address 1.8D

Bit Name Description Type Default Note

F:0 Channel B

Received Signal

Power [F:0]

Received signal power (dBm) for Channel B RO The received signal power on the

channel. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -20.0 dB to +5.5dB.

The number is in offset two’s

complement notation, with 0.0 dB

represented by 0x8000.

Table 6.32 PMA 10GBASE-T Receive Signal Power Channel B: Address 1.8E

Bit Name Description Type Default Note

F:0 Channel C

Received Signal

Power [F:0]

Received signal power (dBm) for Channel C RO The received signal power on the

channel. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -20.0 dB to +5.5dB.

The number is in offset two’s

complement notation, with 0.0 dB

represented by 0x8000.

Table 6.33 PMA 10GBASE-T Receive Signal Power Channel C: Address 1.8F

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6.6.30 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90

6.6.31 PMA 10GBASE-T Skew Delay 1: Address 1.91

Bit Name Description Type Default Note

F:0 Channel D

Received Signal

Power [F:0]

Received signal power (dBm) for Channel D RO The received signal power on the

channel. It is reported with 0.1 dB of

resolution to an accuracy of 0.5 dB

within the range of -20.0 dB to +5.5dB.

The number is in offset two’s

complement notation, with 0.0 dB

represented by 0x8000.

Table 6.34 PMA 10GBASE-T Receive Signal Power Channel D: Address 1.90

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:8 Skew Delay B

[6:0]

Skew delay for pair B RO The skew delay reports the current skew delay

on each of the pair with respect to physical pair

A. It is reported with 1.25 ns resolution to an

accuracy of 2.5 ns. The number is in two’s

complement notation with positive values

representing delay and negative values

representing advance with respect to physical

pair A. If the delay exceed the maximum

amount that can be represented by the range

(-80 ns to +78.75 ns), the field displays the

maximum respective value.

7:0 Reserved Internal reserved - do not modify

Table 6.35 PMA 10GBASE-T Skew Delay 1: Address 1.91

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6.6.32 PMA 10GBASE-T Skew Delay 2: Address 1.92

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:8 Skew Delay D

[6:0]

Skew delay for pair D RO The skew delay reports the current skew delay

on each of the pair with respect to physical pair

A. It is reported with 1.25 ns resolution to an

accuracy of 2.5 ns. The number is in two’s

complement notation with positive values

representing delay and negative values

representing advance with respect to physical

pair A. If the delay exceed the maximum

amount that can be represented by the range

(-80 ns to +78.75 ns), the field displays the

maximum respective value.

7 Reserved Internal reserved - do not modify

6:0 Skew Delay C

[6:0]

Skew delay for pair C RO The skew delay reports the current skew delay

on each of the pair with respect to physical pair

A. It is reported with 1.25 ns resolution to an

accuracy of 2.5 ns. The number is in two’s

complement notation with positive values

representing delay and negative values

representing advance with respect to physical

pair A. If the delay exceed the maximum

amount that can be represented by the range

(-80 ns to +78.75 ns), the field displays the

maximum respective value.

Table 6.36 PMA 10GBASE-T Skew Delay 2: Address 1.92

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6.6.33 PMA 10GBASE-T Fast Retrain Status and Control: Address 1.93

Bit Name Description Type Default Note

F:B LP Fast Retrain

Count [4:0]

Counts the number of fast retrains

requested by the link partner

SCT 0x00 Saturating clear on read counter.

A:6 LD Fast Retrain

Count [4:0]

Counts the number of fast retrains

requested by the local device

SCT 0x00 Saturating clear on read counter.

5 Reserved Internal reserved - do not modify

4 Fast Retrain

Ability

1 = Fast retrain capability is supported

0 = Fast retrain capability is not

supported

3 Fast Retrain

Negotiated

1 = Fast retrain capability was

negotiated

0 = Fast retrain capability was not

negotiated

2:1 Fast Retrain

Signal Type [1:0]

11 = Reserved

10 = PHY signals Link Interruption

during fast retrain

01 = PHY signals Local Fault during fast

retrain

00 = PHY signals IDLE during fast

retrain

R/W 0x0

0 Fast Retrain

Enable

1 = Fast retrain capability is enabled

0 = Fast retrain capability is disabled

R/W 0

Table 6.37 PMA 10GBASE-T Fast Retrain Status and Control : Address 1.93

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6.6.34 TimeSync PMA Capability: Address 1.1800

6.6.35 TimeSync PMA Transmit Path Data Delay 1: Address 1.1801

6.6.36 TimeSync PMA Transmit Path Data Delay 2: Address 1.1802

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 TimeSync

Transmit Path

Data Delay

1 = PMA provides information on

transmit path data delay in registers

1.1801 through 1.1804

0 = PMA does not provide information on

transmit path data delay

0 TimeSync

Receive Path

Data Delay

1 = PMA provides information on receive

path data delay in registers 1.1805

through 1.1808

0 = PMA does not provide information on

receive path data delay

Table 6.38 TimeSync PMA Capability: Address 1.1800

Bit Name Description Type Default Note

F:0 Maximum PMA

Transmit Path

Data Delay LSW

[F:0]

LSW of maximum PMA transmit delay in

nanoseconds

Table 6.39 TimeSync PMA Transmit Path Data Delay 1: Address 1.1801

Bit Name Description Type Default Note

F:0 Maximum PMA

Transmit Path

Data Delay

MSW [F:0]

MSW of maximum PMA transmit delay

in nanoseconds

Table 6.40 TimeSync PMA Transmit Path Data Delay 2: Address 1.1802

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6.6.37 TimeSync PMA Transmit Path Data Delay 3: Address 1.1803

6.6.38 TimeSync PMA Transmit Path Data Delay 4: Address 1.1804

6.6.39 TimeSync PMA Receive Path Data Delay 1: Address 1.1805

Bit Name Description Type Default Note

F:0 Minimum PMA

Transmit Path

Data Delay LSW

[F:0]

LSW of minimum PMA transmit delay in

nanoseconds

Table 6.41 TimeSync PMA Transmit Path Data Delay 3: Address 1.1803

Bit Name Description Type Default Note

F:0 Minimum PMA

Transmit Path

Data Delay

MSW [F:0]

MSW of minimum PMA transmit delay in

nanoseconds

Table 6.42 TimeSync PMA Transmit Path Data Delay 4: Address 1.1804

Bit Name Description Type Default Note

F:0 Maximum PMA

Receive Path

Data Delay LSW

[F:0]

LSW of maximum PMA receive delay in

nanoseconds

Table 6.43 TimeSync PMA Receive Path Data Delay 1: Address 1.1805

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6.6.40 TimeSync PMA Receive Path Data Delay 2: Address 1.1806

6.6.41 TimeSync PMA Receive Path Data Delay 3: Address 1.1807

6.6.42 TimeSync PMA Receive Path Data Delay 4: Address 1.1808

Bit Name Description Type Default Note

F:0 Maximum PMA

Receive Path

Data Delay

MSW [F:0]

MSW of maximum PMA receive delay in

nanoseconds

Table 6.44 TimeSync PMA Receive Path Data Delay 2: Address 1.1806

Bit Name Description Type Default Note

F:0 Minimum PMA

Receive Path

Data Delay LSW

[F:0]

LSW of minimum PMA receive delay in

nanoseconds

Table 6.45 TimeSync PMA Receive Path Data Delay 3: Address 1.1807

Bit Name Description Type Default Note

F:0 Minimum PMA

Receive Path

Data Delay

MSW [F:0]

MSW of minimum PMA receive delay in

nanoseconds

Table 6.46 TimeSync PMA Receive Path Data Delay 4: Address 1.1808

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6.6.43 XENPAK Control: Address 1.8000

Bit Name Description Type Default Note

F:9 Vendor Specific [6:0] Reserved R/W 0x00

8:6 Reserved Internal reserved - do not modify

5 Command 1 = Read NVR

0 = Write NVR

R/W 0 Writing to this register initiates the

command indicated by the value that is

written. These commands are used in

conjunction with regular MDIO reads and

writes to burn the value permanently into

the NVR, versus just altering a volatile copy

of the register.

NOTE!! This is a processor intensive

operation. Completion of this operation can

be monitored via 1E.C831.F

4 Reserved Internal reserved - do not modify

3:2 Command Status [1:0] [3:2]

0x3 = Command failed

0x2 = Command in progress

0x1 = Command succeeded

0x0 = Idle

RO Status of command. When a command has

completed, the read returns either 0x3 or

0x1, depending on the outcome of the

command. Subsequent reads return Idle

(0x0), until a new command is initiated. This

field is RO by the MDIO and is R/W by the

uP and will automatically clear to 0x0 when

the value is either 0x3 or 0x1 when read by

the MDIO.

1:0 Extended Commands

[1:0]

0x3 = Read all NVR contents

0x2 = Vendor Specific

0x1 = Vendor Specific

0x0 = Vendor Specific

R/W 0x0 If the extended command bits are set to 0x3

when a read command is issued, all of the

NVR volatile registers will have their values

re-initialized to the default values stored in

the NVR. This is similar to a reset.

Table 6.47 XENPAK Control: Address 1.8000

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6.6.44 XENPAK Header - XENPAK MSA Version Supported: Address 1.8007

6.6.45 XENPAK Header - NVR Size 1: Address 1.8008

6.6.46 XENPAK Header - NVR Size 2: Address 1.8009

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Version [7:0] [7:0] = Version * 10 RO Version * 10: i.e Maximum version = 25.5.

Table 6.48 XENPAK Header - XENPAK MSA Version Supported: Address 1.8007

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 NVR Size MSW [F:8] [7:0] = Bits [F:8] of NVR size in

bytes

ROS 0x01 256 Bytes synthetic NVR

Table 6.49 XENPAK Header - NVR Size 1: Address 1.8008

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 NVR Size LSW [7:0] [7:0] = Bits [7:0] of NVR size in

bytes

ROS 0x00 256 Bytes synthetic NVR

Table 6.50 XENPAK Header - NVR Size 2: Address 1.8009

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6.6.47 XENPAK Header - Memory Used 1: Address 1.800A

6.6.48 XENPAK Header - Memory Used 2: Address 1.800B

6.6.49 XENPAK Header - Basic Memory Start Address: Address 1.800C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Memory Used MSW [7:0] [7:0] = Bits [F:8] of memory used in

bytes

ROS 0x01

Table 6.51 XENPAK Header - Memory Used 1: Address 1.800A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Memory Used LSW [7:0] [7:0] = Bits [7:0] of memory used in

bytes

ROS 0x00

Table 6.52 XENPAK Header - Memory Used 2: Address 1.800B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Memory Offset

[7:0]

[7:0] = Basic memory start address ROS 0x0C The address where the basic memory

starts in the NVR.

Table 6.53 XENPAK Header - Basic Memory Start Address: Address 1.800C

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6.6.50 XENPAK Header - Customer Memory Offset: Address 1.800D

6.6.51 XENPAK Header - Vendor Memory Start Address: Address 1.800E

6.6.52 XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Memory Offset

[7:0]

[7:0] = Customer memory start

address

ROS 0x7E The address where the customer memory

starts.

Table 6.54 XENPAK Header - Customer Memory Offset: Address 1.800D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Memory Offset

[7:0]

[7:0] = Vendor memory start

address

ROS 0xAE The address where the vendor memory

starts.

Table 6.55 XENPAK Header - Vendor Memory Start Address: Address 1.800E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Extended Vendor Offset

LSW [7:0]

[7:0] = Bits [7:0] of extended vendor

memory start address

ROS 0x07 The LSW of the address where the

extended vendor memory starts.

Table 6.56 XENPAK Header - Extended Vendor Memory Offset 1: Address 1.800F

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6.6.53 XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010

6.6.54 XENPAK Basic - Reserved 0x11: Address 1.8011

6.6.55 XENPAK Basic - Transceiver Type: Address 1.8012

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Extended Vendor Offset

MSW [7:0]

[7:0] = Bits [F:8] of extended vendor

memory start address

ROS 0x01 The MSW of the address where the

extended vendor memory starts.

Table 6.57 XENPAK Header - Extended Vendor Memory Offset 2: Address 1.8010

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x11

[7:0]

ROS 0x00

Table 6.58 XENPAK Basic - Reserved 0x11: Address 1.8011

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Transceiver Type [7:0] [7:0]

0x8 → 0x2 = Reserved

0x1 = XENPAK

0x0 = Unspecified

ROS 0x01 All non-power of 2 values are invalid.

Table 6.59 XENPAK Basic - Transceiver Type: Address 1.8012

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6.6.56 XENPAK Basic - Connector Type: Address 1.8013

6.6.57 XENPAK Basic - Encoding: Address 1.8014

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Connector Type [7:0] [7:0]

0x80 = Reserved

0x40 = RJ-45

0x20 = Pigtail

0x10 = FC / PC

0x08 = MU

0x04 = MT-RJ

0x02 = LC

0x01 = SC

0x00 = Unspecified

ROS 0x40 The connector type used. Note the power of

2 encoding. All non-power of 2 values are

invalid.

Table 6.60 XENPAK Basic - Connector Type: Address 1.8013

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Encoding [7:0] [7:0]

0x8 = Reserved

0x4 = 128 DSQ

0x2 = FEC

0x1 = NRZ

0x0 = Unspecified

ROS 0x04 All non-power of 2 values are invalid.

Table 6.61 XENPAK Basic - Encoding: Address 1.8014

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6.6.58 XENPAK Basic - Bit Rate 0: Address 1.8015

6.6.59 XENPAK Basic - Bit Rate 1: Address 1.8016

6.6.60 XENPAK Basic - Protocol: Address 1.8017

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Bit Rate MSW [F:8] [7:0] = [7:0] of bit rate in Mb/s ROS 0x27 0x2710 = 10,000 Mb/s

Table 6.62 XENPAK Basic - Bit Rate 0: Address 1.8015

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Bit Rate LSW [7:0] [7:0] = [F:8] of bit rate in Mb/s ROS 0x10 0x2710 = 10,000 Mb/s

Table 6.63 XENPAK Basic - Bit Rate 1: Address 1.8016

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Protocol [7:0] [7:0]

0x80 → 0x20 = Reserved

0x10 = SONET / SDH

0x08 = LSS

0x04 = WIS

0x02 = 10GFC

0x01 = 10 GbE

0x0 = Unspecified

ROS 0x01 All non-power of 2 values are invalid.

Table 6.64 XENPAK Basic - Protocol: Address 1.8017

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6.6.61 XENPAK Basic - Standards Compliance Codes: Address 1.8018

6.6.62 XENPAK Basic - Reserved 0x19 1: Address 1.8019

6.6.63 XENPAK Basic - Reserved 0x19 2: Address 1.801A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Standard Code [7:0] [7:0]

0x80 = 10GBASE-T

0x40 = 10GBASE-EW

0x20 = 10GBASE-LW

0x10 = 10GBASE-SW

0x08 = 10GBASE-LX4

0x04 = 10GBASE-ER

0x02 = 10GBASE-LR

0x01 = 10GBASE-SR

0x0 = Unspecified

ROS 0x80 All non-power of 2 values are invalid.

Table 6.65 XENPAK Basic - Standards Compliance Codes: Address 1.8018

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x19

[7:0]

ROS 0x00

Table 6.66 XENPAK Basic - Reserved 0x19 1: Address 1.8019

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1A

[7:0]

ROS 0x00

Table 6.67 XENPAK Basic - Reserved 0x19 2: Address 1.801A

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6.6.64 XENPAK Basic - Reserved 0x19 3: Address 1.801B

6.6.65 XENPAK Basic - Reserved 0x19 4: Address 1.801C

6.6.66 XENPAK Basic - Reserved 0x19 5: Address 1.801D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1B

[7:0]

ROS 0x00

Table 6.68 XENPAK Basic - Reserved 0x19 3: Address 1.801B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1C

[7:0]

ROS 0x00

Table 6.69 XENPAK Basic - Reserved 0x19 4: Address 1.801C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1D

[7:0]

ROS 0x00

Table 6.70 XENPAK Basic - Reserved 0x19 5: Address 1.801D

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6.6.67 XENPAK Basic - Reserved 0x19 6: Address 1.801E

6.6.68 XENPAK Basic - Reserved 0x19 7: Address 1.801F

6.6.69 XENPAK Basic - Reserved 0x19 8: Address 1.8020

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1E

[7:0]

ROS 0x00

Table 6.71 XENPAK Basic - Reserved 0x19 6: Address 1.801E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x1F

[7:0]

ROS 0x00

Table 6.72 XENPAK Basic - Reserved 0x19 7: Address 1.801F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x20

[7:0]

ROS 0x00

Table 6.73 XENPAK Basic - Reserved 0x19 8: Address 1.8020

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6.6.70 XENPAK Basic - Reserved 0x19 9: Address 1.8021

6.6.71 XENPAK Basic - Reserved 0x19 10: Address 1.8022

6.6.72 XENPAK Basic - Reserved 0x19 11: Address 1.8023

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x21

[7:0]

ROS 0x00

Table 6.74 XENPAK Basic - Reserved 0x19 9: Address 1.8021

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x22

[7:0]

ROS 0x00

Table 6.75 XENPAK Basic - Reserved 0x19 10: Address 1.8022

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x23

[7:0]

ROS 0x00

Table 6.76 XENPAK Basic - Reserved 0x19 11: Address 1.8023

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6.6.73 XENPAK Basic - Reserved 0x19 12: Address 1.8024

6.6.74 XENPAK Basic - Reserved 0x19 13: Address 1.8025

6.6.75 XENPAK Basic - Reserved 0x19 14: Address 1.8026

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x24

[7:0]

ROS 0x00

Table 6.77 XENPAK Basic - Reserved 0x19 12: Address 1.8024

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x25

[7:0]

ROS 0x00

Table 6.78 XENPAK Basic - Reserved 0x19 13: Address 1.8025

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x26

[7:0]

ROS 0x00

Table 6.79 XENPAK Basic - Reserved 0x19 14: Address 1.8026

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6.6.76 XENPAK Basic - Reserved 0x19 15: Address 1.8027

6.6.77 XENPAK Basic - Reserved 0x19 16: Address 1.8028

6.6.78 XENPAK Basic - Reserved 0x19 17: Address 1.8029

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x27

[7:0]

ROS 0x00

Table 6.80 XENPAK Basic - Reserved 0x19 15: Address 1.8027

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x28

[7:0]

ROS 0x00

Table 6.81 XENPAK Basic - Reserved 0x19 16: Address 1.8028

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x29

[7:0]

ROS 0x00

Table 6.82 XENPAK Basic - Reserved 0x19 17: Address 1.8029

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6.6.79 XENPAK Basic - Reserved 0x19 18: Address 1.802A

6.6.80 XENPAK Basic - Reserved 0x19 19: Address 1.802B

6.6.81 XENPAK Basic - Reserved 0x19 20: Address 1.802C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2A

[7:0]

ROS 0x00

Table 6.83 XENPAK Basic - Reserved 0x19 18: Address 1.802A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2B

[7:0]

ROS 0x00

Table 6.84 XENPAK Basic - Reserved 0x19 19: Address 1.802B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2C

[7:0]

ROS 0x00

Table 6.85 XENPAK Basic - Reserved 0x19 20: Address 1.802C

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6.6.82 XENPAK Basic - Reserved 0x19 21: Address 1.802D

6.6.83 XENPAK Basic - Reserved 0x19 22: Address 1.802E

6.6.84 XENPAK Basic - Reserved 0x19 23: Address 1.802F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2D

[7:0]

ROS 0x00

Table 6.86 XENPAK Basic - Reserved 0x19 21: Address 1.802D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2E

[7:0]

ROS 0x00

Table 6.87 XENPAK Basic - Reserved 0x19 22: Address 1.802E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x2F

[7:0]

ROS 0x00

Table 6.88 XENPAK Basic - Reserved 0x19 23: Address 1.802F

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6.6.85 XENPAK Basic - Reserved 0x19 24: Address 1.8030

6.6.86 XENPAK Basic - Reserved 0x19 25: Address 1.8031

6.6.87 XENPAK Basic - Package Identifier 1: Address 1.8032

6.6.88 XENPAK Basic - Package Identifier 2: Address 1.8033

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x30

[7:0]

ROS 0x00

Table 6.89 XENPAK Basic - Reserved 0x19 24: Address 1.8030

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x31

[7:0]

ROS 0x00

Table 6.90 XENPAK Basic - Reserved 0x19 25: Address 1.8031

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Package ID 1 [1F:18] [7:0] = [1F:18] of Package ID RO Clone of Registers 1.E:F

Table 6.91 XENPAK Basic - Package Identifier 1: Address 1.8032

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Package ID 2 [17:10] [7:0] = [17:10] of Package ID RO Clone of Registers 1.E:F

Table 6.92 XENPAK Basic - Package Identifier 2: Address 1.8033

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6.6.89 XENPAK Basic - Package Identifier 3: Address 1.8034

6.6.90 XENPAK Basic - Package Identifier 4: Address 1.8035

6.6.91 XENPAK Basic - Vendor Identifier 1: Address 1.8036

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Package ID 3 [F:8] [7:0] = [F:8] of Package ID RO Clone of Registers 1.E:F

Table 6.93 XENPAK Basic - Package Identifier 3: Address 1.8034

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Package ID 4 [7:0] [7:0] = [7:0] of Package ID RO Clone of Registers 1.E:F

Table 6.94 XENPAK Basic - Package Identifier 4: Address 1.8035

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor ID 1 [1F:18] [7:0] = [1F:18] of Vendor ID RO

Table 6.95 XENPAK Basic - Vendor Identifier 1: Address 1.8036

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6.6.92 XENPAK Basic - Vendor Identifier 2: Address 1.8037

6.6.93 XENPAK Basic - Vendor Identifier 3: Address 1.8038

6.6.94 XENPAK Basic - Vendor Identifier 4: Address 1.8039

6.6.95 XENPAK Basic - Vendor Name 1: Address 1.803A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor ID 2 [17:10] [7:0] = [17:10] of Package ID RO

Table 6.96 XENPAK Basic - Vendor Identifier 2: Address 1.8037

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor ID 3 [F:8] [7:0] = [F:8] of Package ID RO

Table 6.97 XENPAK Basic - Vendor Identifier 3: Address 1.8038

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor ID 4 [7:0] [7:0] = [7:0] of Package ID RO

Table 6.98 XENPAK Basic - Vendor Identifier 4: Address 1.8039

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 1 [7:0] [7:0] = 1st Character RO

Table 6.99 XENPAK Basic - Vendor Name 1: Address 1.803A

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6.6.96 XENPAK Basic - Vendor Name 2: Address 1.803B

6.6.97 XENPAK Basic - Vendor Name 3: Address 1.803C

6.6.98 XENPAK Basic - Vendor Name 4: Address 1.803D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 2 [7:0] [7:0] = 2nd Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.100 XENPAK Basic - Vendor Name 2: Address 1.803B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 3 [7:0] [7:0] = 3rd Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.101 XENPAK Basic - Vendor Name 3: Address 1.803C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 4 [7:0] [7:0] = 4th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.102 XENPAK Basic - Vendor Name 4: Address 1.803D

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6.6.99 XENPAK Basic - Vendor Name 5: Address 1.803E

6.6.100 XENPAK Basic - Vendor Name 6: Address 1.803F

6.6.101 XENPAK Basic - Vendor Name 7: Address 1.8040

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 5 [7:0] [7:0] = 5th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.103 XENPAK Basic - Vendor Name 5: Address 1.803E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 6 [7:0] [7:0] = 6th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.104 XENPAK Basic - Vendor Name 6: Address 1.803F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 7 [7:0] [7:0] = 7th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.105 XENPAK Basic - Vendor Name 7: Address 1.8040

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6.6.102 XENPAK Basic - Vendor Name 8: Address 1.8041

6.6.103 XENPAK Basic - Vendor Name 9: Address 1.8042

6.6.104 XENPAK Basic - Vendor Name 10: Address 1.8043

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 8 [7:0] [7:0] = 8th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.106 XENPAK Basic - Vendor Name 8: Address 1.8041

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 9 [7:0] [7:0] = 9th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.107 XENPAK Basic - Vendor Name 9: Address 1.8042

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 10 [7:0] [7:0] = 10th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.108 XENPAK Basic - Vendor Name 10: Address 1.8043

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6.6.105 XENPAK Basic - Vendor Name 11: Address 1.8044

6.6.106 XENPAK Basic - Vendor Name 12: Address 1.8045

6.6.107 XENPAK Basic - Vendor Name 13: Address 1.8046

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 11 [7:0] [7:0] = 11th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.109 XENPAK Basic - Vendor Name 11: Address 1.8044

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 12 [7:0] [7:0] = 12th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.110 XENPAK Basic - Vendor Name 12: Address 1.8045

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 13 [7:0] [7:0] = 13th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.111 XENPAK Basic - Vendor Name 13: Address 1.8046

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6.6.108 XENPAK Basic - Vendor Name 14: Address 1.8047

6.6.109 XENPAK Basic - Vendor Name 15: Address 1.8048

6.6.110 XENPAK Basic - Vendor Name 16: Address 1.8049

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 14 [7:0] [7:0] = 14th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.112 XENPAK Basic - Vendor Name 14: Address 1.8047

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 15 [7:0] [7:0] = 15th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.113 XENPAK Basic - Vendor Name 15: Address 1.8048

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Name 16 [7:0] [7:0] = 16th Character RO Vendor name in ASCII, left aligned, and

zero padded on the right.

Table 6.114 XENPAK Basic - Vendor Name 16: Address 1.8049

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6.6.111 XENPAK Basic - Vendor Part Number 1: Address 1.804A

6.6.112 XENPAK Basic - Vendor Part Number 2: Address 1.804B

6.6.113 XENPAK Basic - Vendor Part Number 3: Address 1.804C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 1 [7:0] [7:0] = 1st Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.115 XENPAK Basic - Vendor Part Number 1: Address 1.804A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 2 [7:0] [7:0] = 2nd Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.116 XENPAK Basic - Vendor Part Number 2: Address 1.804B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 3 [7:0] [7:0] = 3rd Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.117 XENPAK Basic - Vendor Part Number 3: Address 1.804C

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6.6.114 XENPAK Basic - Vendor Part Number 4: Address 1.804D

6.6.115 XENPAK Basic - Vendor Part Number 5: Address 1.804E

6.6.116 XENPAK Basic - Vendor Part Number 6: Address 1.804F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 4 [7:0] [7:0] = 4th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.118 XENPAK Basic - Vendor Part Number 4: Address 1.804D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 5 [7:0] [7:0] = 5th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.119 XENPAK Basic - Vendor Part Number 5: Address 1.804E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 6 [7:0] [7:0] = 6th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.120 XENPAK Basic - Vendor Part Number 6: Address 1.804F

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6.6.117 XENPAK Basic - Vendor Part Number 7: Address 1.8050

6.6.118 XENPAK Basic - Vendor Part Number 8: Address 1.8051

6.6.119 XENPAK Basic - Vendor Part Number 9: Address 1.8052

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 7 [7:0] [7:0] = 7th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.121 XENPAK Basic - Vendor Part Number 7: Address 1.8050

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 8 [7:0] [7:0] = 8th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.122 XENPAK Basic - Vendor Part Number 8: Address 1.8051

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 9 [7:0] [7:0] = 9th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.123 XENPAK Basic - Vendor Part Number 9: Address 1.8052

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6.6.120 XENPAK Basic - Vendor Part Number 10: Address 1.8053

6.6.121 XENPAK Basic - Vendor Part Number 11: Address 1.8054

6.6.122 XENPAK Basic - Vendor Part Number 12: Address 1.8055

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 10 [7:0] [7:0] = 10th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.124 XENPAK Basic - Vendor Part Number 10: Address 1.8053

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 11 [7:0] [7:0] = 11th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.125 XENPAK Basic - Vendor Part Number 11: Address 1.8054

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 12 [7:0] [7:0] = 12th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.126 XENPAK Basic - Vendor Part Number 12: Address 1.8055

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6.6.123 XENPAK Basic - Vendor Part Number 13: Address 1.8056

6.6.124 XENPAK Basic - Vendor Part Number 14: Address 1.8057

6.6.125 XENPAK Basic - Vendor Part Number 15: Address 1.8058

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 13 [7:0] [7:0] = 13th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.127 XENPAK Basic - Vendor Part Number 13: Address 1.8056

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 14 [7:0] [7:0] = 14th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.128 XENPAK Basic - Vendor Part Number 14: Address 1.8057

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 15 [7:0] [7:0] = 15th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.129 XENPAK Basic - Vendor Part Number 15: Address 1.8058

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6.6.126 XENPAK Basic - Vendor Part Number 16: Address 1.8059

6.6.127 XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A

6.6.128 XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor PN 16 [7:0] [7:0] = 16th Character RO Vendor part number in ASCII, left aligned,

and zero padded on the right.

Table 6.130 XENPAK Basic - Vendor Part Number 16: Address 1.8059

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Part RN 1 [7:0] [7:0] = 1st Character RO Vendor part revision number in ASCII, left

aligned, and zero padded on the right.

Table 6.131 XENPAK Basic - Vendor Part Revision Number 1: Address 1.805A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Part RN 2 [7:0] [7:0] = 2nd Character RO Vendor part revision number in ASCII, left

aligned, and zero padded on the right.

Table 6.132 XENPAK Basic - Vendor Part Revision Number 2: Address 1.805B

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6.6.129 XENPAK Basic - Vendor Serial Number 1: Address 1.805C

6.6.130 XENPAK Basic - Vendor Serial Number 2: Address 1.805D

6.6.131 XENPAK Basic - Vendor Serial Number 3: Address 1.805E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 1 [7:0] [7:0] = 1st Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.133 XENPAK Basic - Vendor Serial Number 1: Address 1.805C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 2 [7:0] [7:0] = 2nd Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.134 XENPAK Basic - Vendor Serial Number 2: Address 1.805D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 3 [7:0] [7:0] = 3rd Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.135 XENPAK Basic - Vendor Serial Number 3: Address 1.805E

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6.6.132 XENPAK Basic - Vendor Serial Number 4: Address 1.805F

6.6.133 XENPAK Basic - Vendor Serial Number 5: Address 1.8060

6.6.134 XENPAK Basic - Vendor Serial Number 6: Address 1.8061

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 4 [7:0] [7:0] = 4th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.136 XENPAK Basic - Vendor Serial Number 4: Address 1.805F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 5 [7:0] [7:0] = 5th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.137 XENPAK Basic - Vendor Serial Number 5: Address 1.8060

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 6 [7:0] [7:0] = 6th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.138 XENPAK Basic - Vendor Serial Number 6: Address 1.8061

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6.6.135 XENPAK Basic - Vendor Serial Number 7: Address 1.8062

6.6.136 XENPAK Basic - Vendor Serial Number 8: Address 1.8063

6.6.137 XENPAK Basic - Vendor Serial Number 9: Address 1.8064

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 7 [7:0] [7:0] = 7th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.139 XENPAK Basic - Vendor Serial Number 7: Address 1.8062

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 8 [7:0] [7:0] = 8th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.140 XENPAK Basic - Vendor Serial Number 8: Address 1.8063

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 9 [7:0] [7:0] = 9th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.141 XENPAK Basic - Vendor Serial Number 9: Address 1.8064

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6.6.138 XENPAK Basic - Vendor Serial Number 10: Address 1.8065

6.6.139 XENPAK Basic - Vendor Serial Number 11: Address 1.8066

6.6.140 XENPAK Basic - Vendor Serial Number 12: Address 1.8067

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 10 [7:0] [7:0] = 10th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.142 XENPAK Basic - Vendor Serial Number 10: Address 1.8065

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 11 [7:0] [7:0] = 11th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.143 XENPAK Basic - Vendor Serial Number 11: Address 1.8066

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 12 [7:0] [7:0] = 12th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.144 XENPAK Basic - Vendor Serial Number 12: Address 1.8067

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6.6.141 XENPAK Basic - Vendor Serial Number 13: Address 1.8068

6.6.142 XENPAK Basic - Vendor Serial Number 14: Address 1.8069

6.6.143 XENPAK Basic - Vendor Serial Number 15: Address 1.806A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 13 [7:0] [7:0] = 13th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.145 XENPAK Basic - Vendor Serial Number 13: Address 1.8068

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 14 [7:0] [7:0] = 14th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.146 XENPAK Basic - Vendor Serial Number 14: Address 1.8069

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 15 [7:0] [7:0] = 15th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.147 XENPAK Basic - Vendor Serial Number 15: Address 1.806A

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6.6.144 XENPAK Basic - Vendor Serial Number 16: Address 1.806B

6.6.145 XENPAK Basic - Vendor Date Code 1: Address 1.806C

6.6.146 XENPAK Basic - Vendor Date Code 2: Address 1.806D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor SN 16 [7:0] [7:0] = 16th Character RO Vendor serial number in ASCII, left aligned,

and zero padded on the right.

Table 6.148 XENPAK Basic - Vendor Serial Number 16: Address 1.806B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Year 1 [7:0] [7:0] = 1st character of year RO ASCII 1000’s character

Table 6.149 XENPAK Basic - Vendor Date Code 1: Address 1.806C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Year 2 [7:0] [7:0] = 2nd character of year RO ASCII 100’s character

Table 6.150 XENPAK Basic - Vendor Date Code 2: Address 1.806D

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6.6.147 XENPAK Basic - Vendor Date Code 3: Address 1.806E

6.6.148 XENPAK Basic - Vendor Date Code 4: Address 1.806F

6.6.149 XENPAK Basic - Vendor Date Code 5: Address 1.8070

6.6.150 XENPAK Basic - Vendor Date Code 6: Address 1.8071

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Year 3 [7:0] [7:0] = 3rd character of year RO ASCII 10’s character

Table 6.151 XENPAK Basic - Vendor Date Code 3: Address 1.806E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Year 4 [7:0] [7:0] = 4th character of year RO ASCII 1’s character

Table 6.152 XENPAK Basic - Vendor Date Code 4: Address 1.806F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Month 1 [7:0] [7:0] = 1st character of month RO ASCII 10’s character

Table 6.153 XENPAK Basic - Vendor Date Code 5: Address 1.8070

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Month 2 [7:0] [7:0] = 2nd character of month RO ASCII 1’s character

Table 6.154 XENPAK Basic - Vendor Date Code 6: Address 1.8071

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6.6.151 XENPAK Basic - Vendor Date Code 7: Address 1.8072

6.6.152 XENPAK Basic - Vendor Date Code 8: Address 1.8073

6.6.153 XENPAK Basic - Vendor Date Code 9: Address 1.8074

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Day 1 [7:0] [7:0] = 1st character of day RO ASCII 10’s character

Table 6.155 XENPAK Basic - Vendor Date Code 7: Address 1.8072

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Day 2 [7:0] [7:0] = 2nd character of day RO ASCII 1’s character

Table 6.156 XENPAK Basic - Vendor Date Code 8: Address 1.8073

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Lot 1 [7:0] [7:0] = 1st character of lot RO ASCII 10’s character

Table 6.157 XENPAK Basic - Vendor Date Code 9: Address 1.8074

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6.6.154 XENPAK Basic - Vendor Date Code 10: Address 1.8075

6.6.155 XENPAK Basic - 5V Loading: Address 1.8076

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Lot 2 [7:0] [7:0] = 2nd character of lot RO ASCII 1’s character

Table 6.158 XENPAK Basic - Vendor Date Code 10: Address 1.8075

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 5V Loading [7:0] [7:0]

0x80 = 90% - 99%

0x40 = 80% - 89%

0x20 = 70% - 79%

0x10 = 60% - 69%

0x08 = 50% - 59%

0x04 = 40% - 49%

0x02 = 30% - 39%

0x01 = 20% - 29%

0x0 = 5V not used

RO All non-power of 2 values are invalid.

Table 6.159 XENPAK Basic - 5V Loading: Address 1.8076

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6.6.156 XENPAK Basic - 3.3V Loading: Address 1.8077

6.6.157 XENPAK Basic - APS Loading: Address 1.8078

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 3.3V Loading [7:0] [7:0]

0x80 = 90% - 99%

0x40 = 80% - 89%

0x20 = 70% - 79%

0x10 = 60% - 69%

0x08 = 50% - 59%

0x04 = 40% - 49%

0x02 = 30% - 39%

0x01 = 20% - 29%

0x0 = 3.3V not used

RO All non-power of 2 values are invalid.

Table 6.160 XENPAK Basic - 3.3V Loading: Address 1.8077

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 APS Loading [7:0] [7:0]

0x80 = 90% - 99%

0x40 = 80% - 89%

0x20 = 70% - 89%

0x10 = 60% - 89%

0x08 = 50% - 89%

0x04 = 40% - 89%

0x02 = 30% - 89%

0x01 = 20% - 89%

0x0 = APS not used

RO All non-power of 2 values are invalid.

Table 6.161 XENPAK Basic - APS Loading: Address 1.8078

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6.6.158 XENPAK Basic - APS Voltage: Address 1.8079

6.6.159 XENPAK Basic - DOM Capability: Address 1.807A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 APS Voltage [7:0] [7:0]

0x80 = Reserved

0x40 = C

0x20 = 1.8V

0x10 = 1.5V

0x08 = 1.3V

0x04 = 1.2V

0x02 = 1V

0x01 = 0.9V

0x0 = Unspecified

RO All non-power of 2 values are invalid.

Table 6.162 XENPAK Basic - APS Voltage: Address 1.8079

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 DOM Control Capability 1 = Implemented

0 = Not implemented

ROS 1 When set this bit indicates whether the

XENPAK supports DOM control and status

registers.

6 DOM Capability 1 = Implemented

0 = Not implemented

ROS 1 When set this bit indicates whether the

XENPAK supports DOM.

5:0 Reserved Internal reserved - do not modify

Table 6.163 XENPAK Basic - DOM Capability: Address 1.807A

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6.6.160 XENPAK Basic - Low-Power Startup Capability: Address 1.807B

6.6.161 XENPAK Basic - Reserved 0x7C: Address 1.807C

6.6.162 XENPAK Basic - Checksum: Address 1.807D

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Low Power Start-up

Capability

1 = Low-power start-up capable

0 = Not capable

ROS 1 When set this bit indicates whether the

XENPAK can come up in a low-power

mode.

Table 6.164 XENPAK Basic - Low-Power Startup Capability: Address 1.807B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Basic Reserved 0x7C

[7:0]

ROS 0x00

Table 6.165 XENPAK Basic - Reserved 0x7C: Address 1.807C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Checksum [7:0] [7:0] = Checksum RO The checksum over the LSBs of all the

registers from 1.8007 to 1.807C.

Table 6.166 XENPAK Basic - Checksum: Address 1.807D

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6.6.163 XENPAK Customer - Reserved 0x7E 1: Address 1.807E

6.6.164 XENPAK Customer - Reserved 0x7E 2: Address 1.807F

6.6.165 XENPAK Customer - Reserved 0x7E 3: Address 1.8080

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x7E [7:0]

Table 6.167 XENPAK Customer - Reserved 0x7E 1: Address 1.807E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x7F [7:0]

Table 6.168 XENPAK Customer - Reserved 0x7E 2: Address 1.807F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x80 [7:0]

Table 6.169 XENPAK Customer - Reserved 0x7E 3: Address 1.8080

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6.6.166 XENPAK Customer - Reserved 0x7E 4: Address 1.8081

6.6.167 XENPAK Customer - Reserved 0x7E 5: Address 1.8082

6.6.168 XENPAK Customer - Reserved 0x7E 6: Address 1.8083

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x81 [7:0]

Table 6.170 XENPAK Customer - Reserved 0x7E 4: Address 1.8081

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x82 [7:0]

Table 6.171 XENPAK Customer - Reserved 0x7E 5: Address 1.8082

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x83 [7:0]

Table 6.172 XENPAK Customer - Reserved 0x7E 6: Address 1.8083

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6.6.169 XENPAK Customer - Reserved 0x7E 7: Address 1.8084

6.6.170 XENPAK Customer - Reserved 0x7E 8: Address 1.8085

6.6.171 XENPAK Customer - Reserved 0x7E 9: Address 1.8086

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x84 [7:0]

Table 6.173 XENPAK Customer - Reserved 0x7E 7: Address 1.8084

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x85 [7:0]

Table 6.174 XENPAK Customer - Reserved 0x7E 8: Address 1.8085

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x86 [7:0]

Table 6.175 XENPAK Customer - Reserved 0x7E 9: Address 1.8086

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6.6.172 XENPAK Customer - Reserved 0x7E 10: Address 1.8087

6.6.173 XENPAK Customer - Reserved 0x7E 11: Address 1.8088

6.6.174 XENPAK Customer - Reserved 0x7E 12: Address 1.8089

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x87 [7:0]

Table 6.176 XENPAK Customer - Reserved 0x7E 10: Address 1.8087

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x88 [7:0]

Table 6.177 XENPAK Customer - Reserved 0x7E 11: Address 1.8088

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x89 [7:0]

Table 6.178 XENPAK Customer - Reserved 0x7E 12: Address 1.8089

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6.6.175 XENPAK Customer - Reserved 0x7E 13: Address 1.808A

6.6.176 XENPAK Customer - Reserved 0x7E 14: Address 1.808B

6.6.177 XENPAK Customer - Reserved 0x7E 15: Address 1.808C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8A [7:0]

Table 6.179 XENPAK Customer - Reserved 0x7E 13: Address 1.808A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8B [7:0]

Table 6.180 XENPAK Customer - Reserved 0x7E 14: Address 1.808B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8C [7:0]

Table 6.181 XENPAK Customer - Reserved 0x7E 15: Address 1.808C

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.178 XENPAK Customer - Reserved 0x7E 16: Address 1.808D

6.6.179 XENPAK Customer - Reserved 0x7E 17: Address 1.808E

6.6.180 XENPAK Customer - Reserved 0x7E 18: Address 1.808F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8D [7:0]

Table 6.182 XENPAK Customer - Reserved 0x7E 16: Address 1.808D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8E [7:0]

Table 6.183 XENPAK Customer - Reserved 0x7E 17: Address 1.808E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x8F [7:0]

Table 6.184 XENPAK Customer - Reserved 0x7E 18: Address 1.808F

165

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.181 XENPAK Customer - Reserved 0x7E 19: Address 1.8090

6.6.182 XENPAK Customer - Reserved 0x7E 20: Address 1.8091

6.6.183 XENPAK Customer - Reserved 0x7E 21: Address 1.8092

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x90 [7:0]

Table 6.185 XENPAK Customer - Reserved 0x7E 19: Address 1.8090

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x91 [7:0]

Table 6.186 XENPAK Customer - Reserved 0x7E 20: Address 1.8091

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x92 [7:0]

Table 6.187 XENPAK Customer - Reserved 0x7E 21: Address 1.8092

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.184 XENPAK Customer - Reserved 0x7E 22: Address 1.8093

6.6.185 XENPAK Customer - Reserved 0x7E 23: Address 1.8094

6.6.186 XENPAK Customer - Reserved 0x7E 24: Address 1.8095

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x93 [7:0]

Table 6.188 XENPAK Customer - Reserved 0x7E 22: Address 1.8093

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x94 [7:0]

Table 6.189 XENPAK Customer - Reserved 0x7E 23: Address 1.8094

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x95 [7:0]

Table 6.190 XENPAK Customer - Reserved 0x7E 24: Address 1.8095

167

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.187 XENPAK Customer - Reserved 0x7E 25: Address 1.8096

6.6.188 XENPAK Customer - Reserved 0x7E 26: Address 1.8097

6.6.189 XENPAK Customer - Reserved 0x7E 27: Address 1.8098

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x96 [7:0]

Table 6.191 XENPAK Customer - Reserved 0x7E 25: Address 1.8096

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x97 [7:0]

Table 6.192 XENPAK Customer - Reserved 0x7E 26: Address 1.8097

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x98 [7:0]

Table 6.193 XENPAK Customer - Reserved 0x7E 27: Address 1.8098

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.190 XENPAK Customer - Reserved 0x7E 28: Address 1.8099

6.6.191 XENPAK Customer - Reserved 0x7E 29: Address 1.809A

6.6.192 XENPAK Customer - Reserved 0x7E 30: Address 1.809B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x99 [7:0]

Table 6.194 XENPAK Customer - Reserved 0x7E 28: Address 1.8099

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9A [7:0]

Table 6.195 XENPAK Customer - Reserved 0x7E 29: Address 1.809A

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9B [7:0]

Table 6.196 XENPAK Customer - Reserved 0x7E 30: Address 1.809B

169

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.193 XENPAK Customer - Reserved 0x7E 31: Address 1.809C

6.6.194 XENPAK Customer - Reserved 0x7E 32: Address 1.809D

6.6.195 XENPAK Customer - Reserved 0x7E 33: Address 1.809E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9C [7:0]

Table 6.197 XENPAK Customer - Reserved 0x7E 31: Address 1.809C

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9D [7:0]

Table 6.198 XENPAK Customer - Reserved 0x7E 32: Address 1.809D

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9E [7:0]

Table 6.199 XENPAK Customer - Reserved 0x7E 33: Address 1.809E

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.196 XENPAK Customer - Reserved 0x7E 34: Address 1.809F

6.6.197 XENPAK Customer - Reserved 0x7E 35: Address 1.80A0

6.6.198 XENPAK Customer - Reserved 0x7E 36: Address 1.80A1

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0x9F [7:0]

Table 6.200 XENPAK Customer - Reserved 0x7E 34: Address 1.809F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA0 [7:0]

Table 6.201 XENPAK Customer - Reserved 0x7E 35: Address 1.80A0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA1 [7:0]

Table 6.202 XENPAK Customer - Reserved 0x7E 36: Address 1.80A1

171

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.199 XENPAK Customer - Reserved 0x7E 37: Address 1.80A2

6.6.200 XENPAK Customer - Reserved 0x7E 38: Address 1.80A3

6.6.201 XENPAK Customer - Reserved 0x7E 39: Address 1.80A4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA2 [7:0]

Table 6.203 XENPAK Customer - Reserved 0x7E 37: Address 1.80A2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA3 [7:0]

Table 6.204 XENPAK Customer - Reserved 0x7E 38: Address 1.80A3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA4 [7:0]

Table 6.205 XENPAK Customer - Reserved 0x7E 39: Address 1.80A4

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.202 XENPAK Customer - Reserved 0x7E 40: Address 1.80A5

6.6.203 XENPAK Customer - Reserved 0x7E 41: Address 1.80A6

6.6.204 XENPAK Customer - Reserved 0x7E 42: Address 1.80A7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA5 [7:0]

Table 6.206 XENPAK Customer - Reserved 0x7E 40: Address 1.80A5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA6 [7:0]

Table 6.207 XENPAK Customer - Reserved 0x7E 41: Address 1.80A6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA7 [7:0]

Table 6.208 XENPAK Customer - Reserved 0x7E 42: Address 1.80A7

173

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.205 XENPAK Customer - Reserved 0x7E 43: Address 1.80A8

6.6.206 XENPAK Customer - Reserved 0x7E 44: Address 1.80A9

6.6.207 XENPAK Customer - Reserved 0x7E 45: Address 1.80AA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA8 [7:0]

Table 6.209 XENPAK Customer - Reserved 0x7E 43: Address 1.80A8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xA9 [7:0]

Table 6.210 XENPAK Customer - Reserved 0x7E 44: Address 1.80A9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xAA [7:0]

Table 6.211 XENPAK Customer - Reserved 0x7E 45: Address 1.80AA

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.208 XENPAK Customer - Reserved 0x7E 46: Address 1.80AB

6.6.209 XENPAK Customer - Reserved 0x7E 47: Address 1.80AC

6.6.210 XENPAK Customer - Reserved 0x7E 48: Address 1.80AD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xAB [7:0]

Table 6.212 XENPAK Customer - Reserved 0x7E 46: Address 1.80AB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xAC [7:0]

Table 6.213 XENPAK Customer - Reserved 0x7E 47: Address 1.80AC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Customer Reserved

0xAD [7:0]

Table 6.214 XENPAK Customer - Reserved 0x7E 48: Address 1.80AD

175

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.211 XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE

6.6.212 XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF

6.6.213 XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xAE

[7:0]

Table 6.215 XENPAK Vendor - Reserved 0xAE 1: Address 1.80AE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xAF

[7:0]

Table 6.216 XENPAK Vendor - Reserved 0xAE 2: Address 1.80AF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBO

[7:0]

Table 6.217 XENPAK Vendor - Reserved 0xAE 3: Address 1.80B0

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.214 XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1

6.6.215 XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2

6.6.216 XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB1

[7:0]

Table 6.218 XENPAK Vendor - Reserved 0xAE 4: Address 1.80B1

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB2

[7:0]

Table 6.219 XENPAK Vendor - Reserved 0xAE 5: Address 1.80B2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB3

[7:0]

Table 6.220 XENPAK Vendor - Reserved 0xAE 6: Address 1.80B3

177

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.217 XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4

6.6.218 XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5

6.6.219 XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB4

[7:0]

Table 6.221 XENPAK Vendor - Reserved 0xAE 7: Address 1.80B4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB5

[7:0]

Table 6.222 XENPAK Vendor - Reserved 0xAE 8: Address 1.80B5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB6

[7:0]

Table 6.223 XENPAK Vendor - Reserved 0xAE 9: Address 1.80B6

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.220 XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7

6.6.221 XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8

6.6.222 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB7

[7:0]

Table 6.224 XENPAK Vendor - Reserved 0xAE 10: Address 1.80B7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB8

[7:0]

Table 6.225 XENPAK Vendor - Reserved 0xAE 11: Address 1.80B8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xB9

[7:0]

Table 6.226 XENPAK Vendor - Reserved 0xAE 12: Address 1.80B9

179

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.223 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA

6.6.224 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB

6.6.225 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBA

[7:0]

Table 6.227 XENPAK Vendor - Reserved 0xAE 13: Address 1.80BA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBB

[7:0]

Table 6.228 XENPAK Vendor - Reserved 0xAE 14: Address 1.80BB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBC

[7:0]

Table 6.229 XENPAK Vendor - Reserved 0xAE 15: Address 1.80BC

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.226 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD

6.6.227 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE

6.6.228 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBD

[7:0]

Table 6.230 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBE

[7:0]

Table 6.231 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xBF

[7:0]

Table 6.232 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF

181

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.229 XENPAK Vendor - Reserved 0xAE 19: Address 1.80C0

6.6.230 XENPAK Vendor - Reserved 0xAE 20: Address 1.80C1

6.6.231 XENPAK Vendor - Reserved 0xAE 21: Address 1.80C2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC0

[7:0]

Table 6.233 XENPAK Vendor - Reserved 0xAE 16: Address 1.80BD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC1

[7:0]

Table 6.234 XENPAK Vendor - Reserved 0xAE 17: Address 1.80BE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC2

[7:0]

Table 6.235 XENPAK Vendor - Reserved 0xAE 18: Address 1.80BF

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.232 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3

6.6.233 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4

6.6.234 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC3

[7:0]

Table 6.236 XENPAK Vendor - Reserved 0xAE 22: Address 1.80C3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC4

[7:0]

Table 6.237 XENPAK Vendor - Reserved 0xAE 23: Address 1.80C4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC5

[7:0]

Table 6.238 XENPAK Vendor - Reserved 0xAE 24: Address 1.80C5

183

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.235 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6

6.6.236 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7

6.6.237 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC6

[7:0]

Table 6.239 XENPAK Vendor - Reserved 0xAE 25: Address 1.80C6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC7

[7:0]

Table 6.240 XENPAK Vendor - Reserved 0xAE 26: Address 1.80C7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC8

[7:0]

Table 6.241 XENPAK Vendor - Reserved 0xAE 27: Address 1.80C8

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.238 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9

6.6.239 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA

6.6.240 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xC9

[7:0]

Table 6.242 XENPAK Vendor - Reserved 0xAE 28: Address 1.80C9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCA

[7:0]

Table 6.243 XENPAK Vendor - Reserved 0xAE 29: Address 1.80CA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCB

[7:0]

Table 6.244 XENPAK Vendor - Reserved 0xAE 30: Address 1.80CB

185

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.241 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC

6.6.242 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD

6.6.243 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCC

[7:0]

Table 6.245 XENPAK Vendor - Reserved 0xAE 31: Address 1.80CC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCD

[7:0]

Table 6.246 XENPAK Vendor - Reserved 0xAE 32: Address 1.80CD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCE

[7:0]

Table 6.247 XENPAK Vendor - Reserved 0xAE 33: Address 1.80CE

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.244 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF

6.6.245 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0

6.6.246 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xCF

[7:0]

Table 6.248 XENPAK Vendor - Reserved 0xAE 34: Address 1.80CF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD0

[7:0]

Table 6.249 XENPAK Vendor - Reserved 0xAE 35: Address 1.80D0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD1

[7:0]

Table 6.250 XENPAK Vendor - Reserved 0xAE 36: Address 1.80D1

187

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.247 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2

6.6.248 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3

6.6.249 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD2

[7:0]

Table 6.251 XENPAK Vendor - Reserved 0xAE 37: Address 1.80D2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD3

[7:0]

Table 6.252 XENPAK Vendor - Reserved 0xAE 38: Address 1.80D3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD4

[7:0]

Table 6.253 XENPAK Vendor - Reserved 0xAE 39: Address 1.80D4

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.250 XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5

6.6.251 XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6

6.6.252 XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD5

[7:0]

Table 6.254 XENPAK Vendor - Reserved 0xAE 40: Address 1.80D5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD6

[7:0]

Table 6.255 XENPAK Vendor - Reserved 0xAE 41: Address 1.80D6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD7

[7:0]

Table 6.256 XENPAK Vendor - Reserved 0xAE 42: Address 1.80D7

189

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

Revision 0.11 - January 5, 2015 - January 5, 2015

6.6.253 XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8

6.6.254 XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9

6.6.255 XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD8

[7:0]

Table 6.257 XENPAK Vendor - Reserved 0xAE 43: Address 1.80D8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xD9

[7:0]

Table 6.258 XENPAK Vendor - Reserved 0xAE 44: Address 1.80D9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDA

[7:0]

Table 6.259 XENPAK Vendor - Reserved 0xAE 45: Address 1.80DA

Aquantia Corp. - Strictly Confidential

Revision 0.11 - January 5, 2015 - Janu-

6.6.256 XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB

6.6.257 XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC

6.6.258 XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDB

[7:0]

Table 6.260 XENPAK Vendor - Reserved 0xAE 46: Address 1.80DB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDC

[7:0]

Table 6.261 XENPAK Vendor - Reserved 0xAE 47: Address 1.80DC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDD

[7:0]

Table 6.262 XENPAK Vendor - Reserved 0xAE 48: Address 1.80DD

191

Aquantia Corp. - Strictly Confidential

Use pursuant to Company instructions

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6.6.259 XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE

6.6.260 XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF

6.6.261 XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDE

[7:0]

Table 6.263 XENPAK Vendor - Reserved 0xAE 49: Address 1.80DE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xDF

[7:0]

Table 6.264 XENPAK Vendor - Reserved 0xAE 50: Address 1.80DF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE0

[7:0]

Table 6.265 XENPAK Vendor - Reserved 0xAE 51: Address 1.80E0

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6.6.262 XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1

6.6.263 XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2

6.6.264 XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE1

[7:0]

Table 6.266 XENPAK Vendor - Reserved 0xAE 52: Address 1.80E1

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE2

[7:0]

Table 6.267 XENPAK Vendor - Reserved 0xAE 53: Address 1.80E2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE3

[7:0]

Table 6.268 XENPAK Vendor - Reserved 0xAE 54: Address 1.80E3

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6.6.265 XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4

6.6.266 XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5

6.6.267 XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE4

[7:0]

Table 6.269 XENPAK Vendor - Reserved 0xAE 55: Address 1.80E4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE5

[7:0]

Table 6.270 XENPAK Vendor - Reserved 0xAE 56: Address 1.80E5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE6

[7:0]

Table 6.271 XENPAK Vendor - Reserved 0xAE 57: Address 1.80E6

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6.6.268 XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7

6.6.269 XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8

6.6.270 XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE7

[7:0]

Table 6.272 XENPAK Vendor - Reserved 0xAE 58: Address 1.80E7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE8

[7:0]

Table 6.273 XENPAK Vendor - Reserved 0xAE 59: Address 1.80E8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xE9

[7:0]

Table 6.274 XENPAK Vendor - Reserved 0xAE 60: Address 1.80E9

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6.6.271 XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA

6.6.272 XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB

6.6.273 XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xEA

[7:0]

Table 6.275 XENPAK Vendor - Reserved 0xAE 61: Address 1.80EA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xEB

[7:0]

Table 6.276 XENPAK Vendor - Reserved 0xAE 62: Address 1.80EB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xEC

[7:0]

Table 6.277 XENPAK Vendor - Reserved 0xAE 63: Address 1.80EC

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6.6.274 XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED

6.6.275 XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE

6.6.276 XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xED

[7:0]

Table 6.278 XENPAK Vendor - Reserved 0xAE 64: Address 1.80ED

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xEE

[7:0]

Table 6.279 XENPAK Vendor - Reserved 0xAE 65: Address 1.80EE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xEF

[7:0]

Table 6.280 XENPAK Vendor - Reserved 0xAE 66: Address 1.80EF

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6.6.277 XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0

6.6.278 XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1

6.6.279 XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF0

[7:0]

Table 6.281 XENPAK Vendor - Reserved 0xAE 67: Address 1.80F0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF1

[7:0]

Table 6.282 XENPAK Vendor - Reserved 0xAE 68: Address 1.80F1

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF2

[7:0]

Table 6.283 XENPAK Vendor - Reserved 0xAE 69: Address 1.80F2

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6.6.280 XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3

6.6.281 XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4

6.6.282 XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF3

[7:0]

Table 6.284 XENPAK Vendor - Reserved 0xAE 70: Address 1.80F3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF4

[7:0]

Table 6.285 XENPAK Vendor - Reserved 0xAE 71: Address 1.80F4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF5

[7:0]

Table 6.286 XENPAK Vendor - Reserved 0xAE 72: Address 1.80F5

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6.6.283 XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6

6.6.284 XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7

6.6.285 XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF6

[7:0]

Table 6.287 XENPAK Vendor - Reserved 0xAE 73: Address 1.80F6

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF7

[7:0]

Table 6.288 XENPAK Vendor - Reserved 0xAE 74: Address 1.80F7

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF8

[7:0]

Table 6.289 XENPAK Vendor - Reserved 0xAE 75: Address 1.80F8

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6.6.286 XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9

6.6.287 XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA

6.6.288 XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xF9

[7:0]

Table 6.290 XENPAK Vendor - Reserved 0xAE 76: Address 1.80F9

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFA

[7:0]

Table 6.291 XENPAK Vendor - Reserved 0xAE 77: Address 1.80FA

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFB

[7:0]

Table 6.292 XENPAK Vendor - Reserved 0xAE 78: Address 1.80FB

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6.6.289 XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC

6.6.290 XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD

6.6.291 XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFC

[7:0]

Table 6.293 XENPAK Vendor - Reserved 0xAE 79: Address 1.80FC

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFD

[7:0]

Table 6.294 XENPAK Vendor - Reserved 0xAE 80: Address 1.80FD

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFE

[7:0]

Table 6.295 XENPAK Vendor - Reserved 0xAE 81: Address 1.80FE

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6.6.292 XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF

6.6.293 XENPAK Vendor - Reserved 0xAE 83: Address 1.8100

6.6.294 XENPAK Vendor - Reserved 0xAE 84: Address 1.8101

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0xFF

[7:0]

Table 6.296 XENPAK Vendor - Reserved 0xAE 82: Address 1.80FF

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x100

[7:0]

Table 6.297 XENPAK Vendor - Reserved 0xAE 83: Address 1.8100

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x101

[7:0]

Table 6.298 XENPAK Vendor - Reserved 0xAE 84: Address 1.8101

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6.6.295 XENPAK Vendor - Reserved 0xAE 85: Address 1.8102

6.6.296 XENPAK Vendor - Reserved 0xAE 86: Address 1.8103

6.6.297 XENPAK Vendor - Reserved 0xAE 87: Address 1.8104

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x102

[7:0]

Table 6.299 XENPAK Vendor - Reserved 0xAE 85: Address 1.8102

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x103

[7:0]

Table 6.300 XENPAK Vendor - Reserved 0xAE 86: Address 1.8103

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x104

[7:0]

Table 6.301 XENPAK Vendor - Reserved 0xAE 87: Address 1.8104

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6.6.298 XENPAK Vendor - Reserved 0xAE 88: Address 1.8105

6.6.299 XENPAK Vendor - Reserved 0xAE 89: Address 1.8106

6.6.300 XENPAK Rx_Alarm - Control: Address 1.9000

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x105

[7:0]

Table 6.302 XENPAK Vendor - Reserved 0xAE 88: Address 1.8105

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Vendor Reserved 0x106

[7:0]

Table 6.303 XENPAK Vendor - Reserved 0xAE 89: Address 1.8106

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5 Reserved 1 Reserved for future use R/W

4 PMA Receive Fault

Enable

Setting this bit high enables

generation of interrupts on PMA

Receive Fault

R/W

1 This bit is mirrored to 1E.C473.2

Note F/W performs mirror. Completion of

this operation can be monitored via

1E.C831.F

Table 6.304 XENPAK Rx_Alarm - Control: Address 1.9000

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6.6.301 XENPAK Tx_Alarm - Control: Address 1.9001

3 PCS Receive Fault

Enable

Setting this bit high enables

generation of interrupts on PCS

Receive Fault

R/W

1 This bit is mirrored to 1E.C473.1

Note F/W performs mirror. Completion of

this operation can be monitored via

1E.C831.F

2:1 Reserved Internal reserved - do not modify

0 PHY XS Receive Fault

Enable

Setting this bit high enables

generation of interrupts on PHY XS

Receive Fault

R/W

1 This bit is mirrored to 1E.C473.0

Note F/W performs mirror. Completion of

this operation can be monitored via

1E.C831.F

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 Temperature Fault

Enable

Setting this bit high enables

generation of interrupts on

Temperature Fault

R/W

0 Setting this bit enables the generation of

interrupt for the temperature high and low

alarms (1.A070.7:6). The generation of

interrupt for the temperature high and low

warnings is not supported.

7 Reserved Internal reserved - do not modify

6 Reserved 1 Reserved for future use R/W

5 Reserved Internal reserved - do not modify

4 PMA Transmit Fault

Enable

Setting this bit high enables

generation of interrupts on PMA

Transmit Fault

R/W

3 PCS Transmit Fault

Enable

Setting this bit high enables

generation of interrupts on PCS

Transmit Fault

R/W

Table 6.305 XENPAK Tx_Alarm - Control: Address 1.9001

Bit Name Description Type Default Note

Table 6.304 XENPAK Rx_Alarm - Control: Address 1.9000

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6.6.302 XENPAK LASI - Control: Address 1.9002

2:1 Reserved Internal reserved - do not modify

0 PHY XS Transmit Fault

Enable

Setting this bit high enables

generation of interrupts on PHY XS

Transmit Fault

R/W

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 Rx Alarm Enable Setting this bit high enables

generation of interrupts on Rx Fault

R/W

0 This bit is copied to 1E.C473.6

Note F/W performs the copy. Completion of

this operation can be monitored via

1E.C831.F

1 Tx Alarm Enable Setting this bit high enables

generation of interrupts on Tx Fault

R/W

0 This bit is copied to 1E.C473.5

Note F/W performs the copy. Completion of

this operation can be monitored via

1E.C831.F

0 Link Status Alarm Enable Setting this bit high enables

generation of interrupts on Link

Status Change

R/W

0 This enables the generation of interrupts on

link status change. Specifically if the AND

of 1.A.0, 3.20.0, and 4.18.C changes, an

alarm is generated.

This bit is copied to 1E.C473.4

Note F/W performs copy. Completion of

this operation can be monitored via

1E.C831.F

Table 6.306 XENPAK LASI - Control: Address 1.9002

Bit Name Description Type Default Note

Table 6.305 XENPAK Tx_Alarm - Control: Address 1.9001

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6.6.303 XENPAK Rx_Alarm - Status: Address 1.9003

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5 Reserved 1 Reserved for future use LH

4 PMA Receive Fault 1 = PMA Receive Fault LH This bit is automatically set by H/W if bit

1.8.A is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

3 PCS Receive Fault 1 = PCS Receive Fault LH This bit is automatically set by H/W if bit

3.8.A is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

2:1 Reserved Internal reserved - do not modify

0 PHY XS Receive Fault 1 = PHY XS Receive Fault LH This bit is automatically set by H/W if bit

4.8.A is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

Table 6.307 XENPAK Rx_Alarm - Status: Address 1.9003

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6.6.304 XENPAK Tx_Alarm - Status: Address 1.9004

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 Temperature Fault 1 = Temperature Fault LH This bit is set if either a high or low

temperature alarm (1.A070.7:6) is set and

the corresponding temperature interrupt

enable (1.900.7:6) is set.

This bit reverts to RO behavior if bit

1E.C441.1 is set.

7 Reserved Internal reserved - do not modify

6 Reserved 1 Reserved for future use LH

5 Reserved Internal reserved - do not modify

4 PMA Transmit Fault 1 = PMA Transmit Fault LH This bit is automatically set by H/W if bit

1.8.B is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

3 PCS Transmit Fault 1 = PCS Transmit Fault LH This bit is automatically set by H/W if bit

3.8.B is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

Table 6.308 XENPAK Tx_Alarm - Status: Address 1.9004

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6.6.305 XENPAK LASI - Status: Address 1.9005

2:1 Reserved Internal reserved - do not modify

0 PHY XS Transmit Fault 1 = PHY XS Transmit Fault LH This bit is automatically set by H/W if bit

4.8.B is set.

This bit is automatically mirrored by H/W to

1.8.B, i.e. if 1.8.B is cleared, this bit will be

automatically cleared and vice versa.

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 Rx Alarm 1 = Rx Fault RO This bit is automatically set by H/W if any of

the Rx fault bits (1.9003.0, 1.9003.3, or

1.9003.4) are set and mask is enabled.

1 Tx Alarm 1 = Tx Fault RO This bit is automatically set by H/W if any of

the Tx fault bits (1.9004.0, 1.9004.3, or

1.9004.4) are set and mask is enabled.

0 Link Status Alarm 1 = Link Status Change LRF This bit is automatically set by H/W if the

AND of 1.A.0, 3.20.0, and 4.18.C has

changed state (i.e. this bit is set if a rising or

falling edge is detected on the AND).

Table 6.309 XENPAK LASI - Status: Address 1.9005

Bit Name Description Type Default Note

Table 6.308 XENPAK Tx_Alarm - Status: Address 1.9004

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6.6.306 XENPAK DOM - Tx Control: Address 1.9006

6.6.307 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 High Temperature Alarm

Enable

Setting this bit high enables

generation of alarms on the

temperature exceeding the high

temperature threshold.

R/W

0 This enables the generation of interrupt for

the high temperature alarm. The generation

for high temperature warning is not

supported.

6 Low Temperature Alarm

Enable

Setting this bit high enables

generation of alarms on the

temperature exceeding the low

temperature threshold.

R/W

0 This enables the generation of interrupt for

the low temperature alarm. The generation

for low temperature warning is not

supported.

5:0 Reserved Internal reserved - do not modify

Table 6.310 XENPAK DOM - Tx Control: Address 1.9006

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 High Temp Threshold

[7:0]

[7:0] of high temperature R/W

0x00 In XENPAK mode, F/W will use 1.A000 and

1.A001 registers instead of 1E.C421.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD8. Default

is 70°C.

Table 6.311 XENPAK DOM - High Temperature Alarm Threshold LSW: Address 1.A000

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6.6.308 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001

6.6.309 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 High Temp Threshold

[F:8]

[F:8] of high temperature R/W

0x46 In XENPAK mode, F/W will use 1.A000 and

1.A001 registers instead of 1E.C421.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD8. Default

is 70°C.

Table 6.312 XENPAK DOM - High Temperature Alarm Threshold MSW: Address 1.A001

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Low Temp Threshold

[7:0]

[7:0] of low temperature R/W

0x00 In XENPAK mode, F/W will use 1.A002 and

1.A003 registers instead of 1E.C422.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 0°C.

Table 6.313 XENPAK DOM - Low Temperature Alarm Threshold LSW: Address 1.A002

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6.6.310 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003

6.6.311 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Low Temp Threshold

[F:8]

[F:8] of low temperature R/W

0x00 In XENPAK mode, F/W will use 1.A002 and

1.A003 registers instead of 1E.C422.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 0°C.

Table 6.314 XENPAK DOM - Low Temperature Alarm Threshold MSW: Address 1.A003

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 High Temp Warning

Threshold [7:0]

[7:0] of high temperature R/W

0x00 In XENPAK mode, F/W will use 1.A004 and

1.A005 registers instead of 1E.C423.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 60°C.

Table 6.315 XENPAK DOM - High Temperature Warning Threshold LSW: Address 1.A004

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6.6.312 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005

6.6.313 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 High Temp Warning

Threshold [F:8]

[F:8] of high temperature R/W

0x3C In XENPAK mode, F/W will use 1.A004 and

1.A005 registers instead of 1E.C423.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 60°C.

Table 6.316 XENPAK DOM - High Temperature Warning Threshold MSW: Address 1.A005

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Low Temp Warning

Threshold [7:0]

[7:0] of low temperature R/W

0x00 In XENPAK mode, F/W will use 1.A006 and

1.A007 registers instead of 1E.C424.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 10°C.

Table 6.317 XENPAK DOM - Low Temperature Warning Threshold LSW: Address 1.A006

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6.6.314 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007

6.6.315 XENPAK DOM - Temperature LSW: Address 1.A060

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Low Temp Warning

Threshold [F:8]

[F:8] of low temperature R/W

0x0A In XENPAK mode, F/W will use 1.A006 and

1.A007 registers instead of 1E.C424.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 10°C.

Table 6.318 XENPAK DOM - Low Temperature Warning Threshold MSW: Address 1.A007

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Temperature [7:0] [7:0] of temperature RO 1.A060 and 1.A061 combine to form the

16-bit temperature. This register is

connected to and driven by the register

1E.C820.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Table 6.319 XENPAK DOM - Temperature LSW: Address 1.A060

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6.6.316 XENPAK DOM - Temperature MSW: Address 1.A061

6.6.317 XENPAK DOM - Status: Address 1.A06E

6.6.318 XENPAK DOM - Capability: Address 1.A06F

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 Temperature [F:8] [F:8] of temperature RO 1.A060 and 1.A061 combine to form the

16-bit temperature. This register is

connected to and driven by the output of

1E.C820.

2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Table 6.320 XENPAK DOM - Temperature MSW: Address 1.A061

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Temperature Ready 1 = temperature measurement is

valid

RO This register is connected to and driven by

the register 1E.C821.

Table 6.321 XENPAK DOM - Status: Address 1.A06E

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Temperature Capability 1 = device supports temperature

measurement capability

ROS 1

6:0 Reserved Internal reserved - do not modify

Table 6.322 XENPAK DOM - Capability: Address 1.A06F

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6.6.319 XENPAK DOM - Alarms 1: Address 1.A070

6.6.320 XENPAK DOM - Alarms 2: Address 1.A071

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 High Temperature Alarm 1 = High temperature alarm LH This register is set when the temperature in

than the high temperature alarm threshold

(1.A000 and 1.A001).

Note this bit is set by F/W.

6 Low Temperature Alarm 1 = Low temperature alarm LH This register is set when the temperature in

the high temperature alarm threshold

(1.A002 and 1.A003).

Note this bit is set by F/W.

5:0 Reserved Internal reserved - do not modify

Table 6.323 XENPAK DOM - Alarms 1: Address 1.A070

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.324 XENPAK DOM - Alarms 2: Address 1.A071

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6.6.321 XENPAK DOM - Alarms 3: Address 1.A072

6.6.322 XENPAK DOM - Alarms 4: Address 1.A073

6.6.323 XENPAK DOM - Alarms 5: Address 1.A074

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.325 XENPAK DOM - Alarms 3: Address 1.A072

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.326 XENPAK DOM - Alarms 4: Address 1.A073

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 High Temperature

Warning

1 = High temperature warning LH This register is set when the temperature in

than the high temperature alarm threshold

(1.A003 and 1.A005).

Note this bit is set by F/W.

6 Low Temperature

Warning

1 = Low temperature warning LH This register is set when the temperature in

the high temperature alarm threshold

(1.A006 and 1.A007).

Note this bit is set by F/W.

5:0 Reserved Internal reserved - do not modify

Table 6.327 XENPAK DOM - Alarms 5: Address 1.A074

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6.6.324 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100

6.6.325 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:2 Reserved 1 [1:0] Reserved for future use RO

These registers are not implemented as

mirroring is done on a steady basis,

regardless.

1:0 Reserved 2 [1:0] Reserved for future use RO

Table 6.328 XENPAK DOM - Control and Status<XENPAK DOM - Control & Status>: Address 1.A100

Bit Name Description Type Default Note

F:4 Reserved Spare

Transmit

Provisioning 0

[B:0]

Reserved for future use R/W

0x000

3:0 Tx Polarity Invert

Enable [3:0]

1 = Invert corresponding Tx lane R/W 0x0 Bit 0 corresponds to Lane A, Bit 1 to Lane B,

etc.

Table 6.329 PMA Transmit Reserved Vendor Provisioning 0: Address 1.C412

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6.6.326 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413

6.6.327 PMA Transmit Vendor Alarms 1: Address 1.CC00

6.6.328 PMA Transmit Vendor Alarms 2: Address 1.CC01

Bit Name Description Type Default Note

F:C Channel

Mask[3:0]

Channel mask specifying which

channels will be affected by the TX PSD

target.

R/W

0x000

B:8 Reserved Spare

Transmit

Provisioning 1

[3:0]

Reserved for future use R/W

0x000

7:0 Incremental Tx

PSD Target [7:0]

Deviation from the current TX PSD

target based on registers A.A and A.B in

2’s complement form s7.

R/W

0x00

Table 6.330 PMA Transmit Reserved Vendor Provisioning 1: Address 1.C413

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.331 PMA Transmit Vendor Alarms 1: Address 1.CC00

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.332 PMA Transmit Vendor Alarms 2: Address 1.CC01

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6.6.329 PMA Transmit Vendor Alarms 3: Address 1.CC02

6.6.330 PMA Transmit Standard Interrupt Mask 1: Address 1.D000

Bit Name Description Type Default Note

F:2 Reserved PMA

Transmit Alarms 3

[D:0]

Reserved for internal use LH

1 Zero Defined as 0 ROS 0 Used to provide a guaranteed zero location in

the same register as Reset Complete

0 Reset Complete 1 = Hardware and Firmware reset

has completed

LH This bit is a mirror of 1E.CC00.6, but has

associated with it a known zero bit that can be

used to ascertain that HW reset has

completed, enabling Reset Complete to be

read in one shot without double polling and

dealing with tristate MDIO issues. It avoids of

problem of not knowing if / when the HW

complete phase of a reset has occurred when

double-polling

Table 6.333 PMA Transmit Vendor Alarms 3: Address 1.CC02

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 PMA Receive Link

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 1.1.2.

1:0 Reserved Internal reserved - do not modify

Table 6.334 PMA Transmit Standard Interrupt Mask 1: Address 1.D000

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6.6.331 PMA Transmit Standard Interrupt Mask 2: Address 1.D001

6.6.332 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400

6.6.333 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401

6.6.334 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Transmit Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 1.8.B

A Receive Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 1.8.A

9:0 Reserved Internal reserved - do not modify

Table 6.335 PMA Transmit Standard Interrupt Mask 2: Address 1.D001

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.336 PMA Transmit Vendor LASI Interrupt Mask 1: Address 1.D400

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.337 PMA Transmit Vendor LASI Interrupt Mask 2: Address 1.D401

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.338 PMA Transmit Vendor LASI Interrupt Mask 3: Address 1.D402

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6.6.335 PMA Transmit Vendor Debug 1: Address 1.D800

6.6.336 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400

Bit Name Description Type Default Note

F PMA Digital

System

Loopback

1 = Enable PMA digital system loopback R/W

E:0 Reserved Internal reserved - do not modify

Table 6.339 PMA Transmit Vendor Debug 1: Address 1.D800

Bit Name Description Type Default Note

F External PHY

Loopback

1 = Enable external PHY loopback

0 = Normal operation

R/W

0 External PHY loopback expects a loopback

connector such that Pair A is connected to Pair

B, and Pair C is connected to Pair D.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

E:3 Reserved

Receive

Provisioning 1

[B:0]

Reserved for future use R/W

0x000

2 Enable Aquantia

Fast Retrain

1 = Enable PMA Fast Link Retrain

0 = Disable PMA Fast Link Retrain

R/W

0 If the link partner is an Aquantia PHY and also

has Fast Retrain enabled use a special retrain

sequence to bring the link back up without

going back through the Autonegotiation

sequence.

Table 6.340 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400

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6.6.337 PMA Receive Vendor State 1: Address 1.E800

6.6.338 PMA Receive Reserved Vendor State 1: Address 1.E810

1 Force MDI

Configuration

1 = Ignore state of MDI_CFG pin

0 = Set MDI Configuration based on

state of MDI_CFG

R/W

0 MDI_CFG pin is not brought out. Set this bit to

1 and use the MDI Configuration bit to control

the MDI pairs’ arrangement.

0MDI

Configuration

1 = MDI Reversed (ABCD -> DCBA)

0 = MDI Normal (ABCD -> ABCD)

R/W

0 The setting of this bit determines whether the

MDI is reversed or not. Note that the reversal

does not change pair polarity - i.e. A+ maps to

D+, etc. The value of this bit is sampled during

autonegotiation. If this bit is changed manually

after autonegotiation completes,

autonegotiation must be restarted to achieve

the desired MDI configuration.

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 PMA Receive

Link Current

Status

1 = Rx link good RO This is the current state of 1.1.2

Table 6.341 PMA Receive Vendor State 1: Address 1.E800

Bit Name Description Type Default Note

F:0 Accumulated

Fast Retrain

Time[F:0]

Accumulated time in milliseconds spent

in fast retrain since the last

auto-negotiation sequence

RO This is a saturating register.

Table 6.342 PMA Receive Reserved Vendor State 1: Address 1.E810

Bit Name Description Type Default Note

Table 6.340 PMA Receive Reserved Vendor Provisioning 1: Address 1.E400

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6.6.339 PMA Receive Reserved Vendor State 2: Address 1.E811

6.6.340 PMA Vendor Global Interrupt Flags 1: Address 1.FC00

Bit Name Description Type Default Note

F:8 Total Number Of

Link Recovery

Events Since

Last AutoNeg

[7:0]

The count of the cumulative number of

Link Recovery Events since last

autonegotiation

RO This register is automatically reset to 0 during

Auto-negotiation. It increments once for each

series of back-to-back Fast Retrain events.

The result is reported modulo 256 (wrap

around).

7:0 Total Number Of

RFI Training

Link Recovery

Events Since

Last AutoNeg

[7:0]

The count of the cumulative number of

RFI Training Link Recovery Events

since last autonegotiation

RO This register is automatically reset to 0 during

Auto-negotiation. The result is reported

modulo 256 (wrap around).

Table 6.343 PMA Receive Reserved Vendor State 2: Address 1.E811

Bit Name Description Type Default Note

F Vendor Specific

Tx Alarms 1

Interrupt

1 = Interrupt RO An interrupt was generated from status

Address 1.CC00” on page 129.) and the

corresponding mask register (See “PMA

Transmit Vendor Interrupt Mask 1: Address

1.D400” on page 132.)

E Vendor Specific

Tx Alarms 2

Interrupt

1 = Interrupt RO An interrupt was generated from status

Address 1.CC01” on page 129.) and the

corresponding mask register (See “PMA

Transmit Vendor Interrupt Mask 2: Address

1.D401” on page 132.)

Table 6.344 PMA Vendor Global Interrupt Flags 1: Address 1.FC00

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D Vendor Specific

Tx Alarms 3

Interrupt

1 = Interrupt RO An interrupt was generated from status

Address 1.CC02” on page 130.) and the

corresponding mask register (See “PMA

Transmit Vendor Interrupt Mask 3: Address

1.D402” on page 133.)

C Reserved Internal reserved - do not modify

B Standard Alarm

1 Interrupt

1 = Interrupt RO An interrupt was generated from bit 1.1.2.

An interrupt was generated from status

Address 1.1” on page 2.) and the

corresponding mask register (See “PMA

Transmit Standard Interrupt Mask 1: Address

1.D000” on page 131.)

A Standard Alarm

2 Interrupt

1 = Interrupt RO An interrupt was generated from either bit

1.8.B or 1.8.A.

An interrupt was generated from status

Address 1.8” on page 8.) and the

corresponding mask register (See “PMA

Transmit Standard Interrupt Mask 2: Address

1.D001” on page 131.)

9:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.344 PMA Vendor Global Interrupt Flags 1: Address 1.FC00

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6.7 PCS Registers

6.7.1 PCS Standard Control 1: Address 3.0

Bit Name Description Type Default Note

F Reset 1 = PCS reset

0 = Normal operation

R/W

1 Resets the entire PHY.

The reset bit is automatically cleared upon

completion of the reset sequence by the

microcontroller. This bit is set to 1 during reset.

The reset is internally stretched by

approximately 1.7 us. Therefore the MDIO or

uP should allow for 1.7 us before writing any

PCS registers after this bit is set.

E Loopback 1 = Enable loopback mode

0 = Normal operation

R/W

0 This enables the PCS DSQ System Loopback.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

D Speed Selection

LSB

{6,D}

1 1 = Speed set by Bits [5:2]

1 0 = 1000 Mb/s

0 1 = 100 Mb/s

0 0 = 10 Mb/s

R/W

C Reserved Internal reserved - do not modify

Table 6.345 PCS Standard Control 1: Address 3.0

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B Low Power 1 = Low-power mode

0 = Normal operation

R/W

0 A one written to this register causes the PCS to

enter low-power mode. If a global chip

low-power state is desired, use Bit B in "Global

Standard Control 1: Address 1E.0" should be

set.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

A Clock Stop Enable 1 = The PHY may stop the clock during

LPI

0 = Clock not stoppable

R/W

9:7 Reserved Internal reserved - do not modify

6 Speed Selection

MSB

{6,D}

1 1 = Speed set by Bits [5:2]

1 0 = 1000 Mb/s

0 1 = 100 Mb/s

0 0 = 10 Mb/s

R/W

5:2 10G Speed

Selection [3:0]

1 x x x = Reserved

x 1 x x = Reserved

x x 1 x = Reserved

x x x 1 = 10PASS-TS / 2BASE-TL

0 0 0 0 = 10 Gb/s

R/W

0x0

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.345 PCS Standard Control 1: Address 3.0

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6.7.2 PCS Standard Status 1: Address 3.1

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Tx LPI Received 1 = Tx PCS has received LPI

0 = LPI not received

LH The source of the LPI signal is configured in

1E.C4A1.3:0.

A Rx LPI Received 1 = Rx PCS has received LPI

0 = LPI not received

LH The source of the LPI signal is configured in

1E.C4A1.3:0.

9 Tx LPI Indication 1 = Tx PCS is currently receiving LPI

0 = Tx PCS is not currently receiving LPI

RO The source of the LPI signal is configured in

1E.C4A1.3:0.

8 Rx LPI Indication 1 = Rx PCS is currently receiving LPI

0 = Rx PCS is not currently receiving LPI

RO The source of the LPI signal is configured in

1E.C4A1.3:0.

7 Fault 1 = Fault condition detected

0 = No fault detected

RO This is the top-level fault indicator flag for the

PCS block, This bit is set if either of the two bits

3.8.B or 3.8.A are set.

6 Clock Stop

Capable

1 = The MAC may stop the clock during

LPI

0 = Clock not stoppable

ROS 0

5:3 Reserved Internal reserved - do not modify

2 PCS Receive

Link Status

Status of the PCS receive link

1 = Link up

0 = Link lost since last read

LL This indicates the status of the PCS receive

link. This is a latching low version of Bit 3.20.C.

1Low Power

Ability

1 = PCS supports low-power mode

0 = no low-power mode supported

ROS 1 Indicates whether the XAUI interface supports

a low-power mode

0 Reserved Internal reserved - do not modify

Table 6.346 PCS Standard Status 1: Address 3.1

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6.7.3 PCS Standard Device Identifier 1: Address 3.2

6.7.4 PCS Standard Device Identifier 2: Address 3.3

6.7.5 PCS Standard Speed Ability: Address 3.4

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.347 PCS Standard Device Identifier 1: Address 3.2

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.348 PCS Standard Device Identifier 2: Address 3.3

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 10PASS-TS /

2BASE-TL

Capable

1 = PCS is 10PASS-TS / 2BASE-TL

capable

0 = PCS is not 10PASS-TS / 2BASE-TL

capable

ROS 0 This is always set to 0 in the AQR405.

0 10G Capable 1 = PCS is 10 Gb/s capable

0 = PCS is not 10 Gb/s capable

ROS 1 This is always set to 1 in the AQR405.

Table 6.349 PCS Standard Speed Ability: Address 3.4

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6.7.6 PCS Standard Devices in Package 1: Address 3.5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no DTE

XAUI interface in the AQR405.

4 PHY XS Present 1 = PHY XS is present in package

0 = PHY XS is not present in package

ROS 1 This is always set to 1 as there is a PHY XS

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Table 6.350 PCS Standard Devices in Package 1: Address 3.5

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6.7.7 PCS Standard Devices in Package 2: Address 3.6

6.7.8 PCS Standard Control 2: Address 3.7

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the global control registers.

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the GbE registers.

C:0 Reserved Internal reserved - do not modify

Table 6.351 PCS Standard Devices in Package 2: Address 3.6

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1:0 PCS Device

Type [1:0]

[1:0]

0x3 = 10GBASE-T

0x2 = 10GBASE-W

0x1 = 10GBASE-X

0x0 = 10GBASE-R

R/W

0x3 This defaults to 10GBASE-T

Table 6.352 PCS Standard Control 2: Address 3.7

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6.7.9 PCS Standard Status 2: Address 3.8

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 0x2, as the PCS

registers reside here in the AQR405.

D:C Reserved Internal reserved - do not modify

B Transmit Fault 1 = Fault condition on transmit path

0 = No fault condition on transmit path

LH This bit indicates whether there is a fault

somewhere along the transmit path. This

bit is duplicated at 3.CC01.0.

A Receive Fault 1 = Fault condition on receive path

0 = No fault condition on receive path

LH This bit indicates whether there is a fault

somewhere along the receive path. This bit

is duplicated at 3.EC04.2.

9:4 Reserved Internal reserved - do not modify

3 10GBASE-T

capable

1 = PCS supports 10GBASE-T PCS type

0 = PCS does not support 10GBASE-T

ROS 1 This field is always set to 1, as the PCS in

the AQR405 only supports 10GBASE-T

and 10GBASE-R.

2 10GBASE-W

capable

1 = PCS supports 10GBASE-W PCS type

0 = PCS does not support 10GBASE-W

ROS 0 This field is always set to 0, as the PCS in

the AQR405 only supports 10GBASE-T

and 10GBASE-R.

1 10GBASE-X

capable

1 = PCS supports 10GBASE-X PCS type

0 = PCS does not support 10GBASE-X

ROS 0 This field is always set to 0, as the PCS in

the AQR405 only supports 10GBASE-T

and 10GBASE-R.

0 10GBASE-R

capable

1 = PCS supports 10GBASE-R PCS type

0 = PCS does not support 10GBASE-R

ROS 1 This field is always set to 1, as the PCS in

the AQR405 only supports 10GBASE-T

and 10GBASE-R.

Table 6.353 PCS Standard Status 2: Address 3.8

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6.7.10 PCS Standard Package Identifier 1: Address 3.E

6.7.11 PCS Standard Package Identifier 2: Address 3.F

6.7.12 PCS EEE Capability Register : Address 3.14

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.354 PCS Standard Package Identifier 1: Address 3.E

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.355 PCS Standard Package Identifier 2: Address 3.F

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 10GBASE-KR EEE 1 = Advertise that the 10GBASE-KR has

EEE capability

0 = Do not advertise that the

10GBASE-KR has EEE capability

ROS 1

5 10GBASE-KX4

EEE

1 = Advertise that the 10GBASE-KX4

has EEE capability

0 = Do not advertise that the

10GBASE-KX4 has EEE capability

ROS 1

Table 6.356 PCS EEE Capability Register : Address 3.14

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6.7.13 PCS EEE Wake Error Counter: Address 3.16

4 1000BASE-KX EEE 1 = Advertise that the 1000BASE-KX

has EEE capability

0 = Do not advertise that the

1000BASE-KX has EEE capability

ROS 1

3 10GBASE-T EEE 1 = Advertise that the 10GBASE-T has

EEE capability

0 = Do not advertise that the

10GBASE-T has EEE capability

ROS 1

2 1000BASE-T EEE 1 = Advertise that the 1000BASE-T has

EEE capability

0 = Do not advertise that the

1000BASE-T has EEE capability

ROS 1

1 100BASE-TX EEE 1 = Advertise that the 100BASE-TX has

EEE capability

0 = Do not advertise that the

100BASE-TX has EEE capability

ROS 0

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:0 EEE Wake Error

Counter [F:0]

EEE wake error counter SCT 0x0000 This register is a 16-bit saturating clear on read

counter. The wake error source is configured

with 1E.C4A1.A:8. The default wake error

source is from the RPL.

Table 6.357 PCS EEE Wake Error Counter: Address 3.16

Bit Name Description Type Default Note

Table 6.356 PCS EEE Capability Register : Address 3.14

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6.7.14 PCS 10G Status 1: Address 3.20

Bit Name Description Type Default Note

F:D Reserved Internal reserved - do not modify

C 10G Receive

Link Status

1 = 10G Receive Link Up

0 = 10G Receive Link Down

RO When set, this bit indicates that the 10G

Receive Link is functioning properly. This is a

non-latching version of bit 3.1.2. See “PCS

Standard Status 1: Address 3.1” on page 229.

The Receive Link is up when the Block Lock

status is asserted and the High BER is

deasserted.)

B:4 Reserved Internal reserved - do not modify

3 10GBASE-R

PRBS9 Pattern

Testing

Ability

1 = PCS is able to support PRBS9

pattern testing on KR Interface

0 = PCS is not able to support PRBS9

pattern testing on KR Interface

ROS 1

2 10GBASE-R

PRBS31 Pattern

Testing

Ability

1 = PCS is able to support PRBS31

pattern testing on KR Interface

0 = PCS is not able to support PRBS31

pattern testing on KR Interface

ROS 1

1 10G High BER 1 = PCS is reporting a BER ≥ 10-4

0 = PCS is reporting a BER < 10-4

RO When set, this bit indicates a high BER is being

seen at the PCS. The interrupt for this bit is at

3.21.E. The status bit for medium BER is found

in “Global Alarms 2: Address 1E.CC01” on

page 615.

0 10G PCS Block

Lock

1 = 10GBASE-T PCS Framer is locked

0 = 10GBASE-T PCS Framer is not

locked

RO When set, this bit indicates that 10G PCS

Framer has acquired frame synchronization

and is locked. The interrupt for this bit is at

3.21.F.

Table 6.358 PCS EEE Wake Error Counter: Address 3.16

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6.7.15 PCS 10G Status 2: Address 3.21

6.7.16 PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22

Bit Name Description Type Default Note

F PCS Block Lock

Latched

1 = 10GBASE-T PCS Framer is Locked

0 = 10GBASE-T PCS Framer is not

locked

LL When set, this bit indicates that 10G PCS

Framer has acquired frame synchronization

and is locked. This is the interrupt for bit 3.20.0.

See “PCS EEE Wake Error Counter: Address

3.16” on page 235.

E High BER

Latched

1 = PCS is reporting a BER ≥ 10-4

0 = PCS is reporting a BER < 10-4

LH When set, this bit indicates a high BER is being

seen at the PCS. This is the interrupt for bit

3.20.1. See “PCS EEE Wake Error Counter:

Address 3.16” on page 235.

D:8 Errored Frame

Counter [5:0]

A saturating count of the number of

times a bad LDPC frame is received.

SCT 0x00 Clear on read. In 10GBASE-T mode, this is

taken from the state machine in Figure 55.14 in

the 10GBASE-T specification. In 10GBASE-R

mode, this is calculated using controls in

7:0 Errored Block

Counter [7:0]

A saturating count of the number of

times a bad 65B block is received.

SCT 0x00 Clear on read. In 10GBASE-T mode, this is

taken from the state machine in Figure 55.16 in

the 10GBASE-T specification.

Table 6.359 PCS 10G Status 2: Address 3.21

Bit Name Description Type Default Note

F:0 Test Pattern

Seed A Bits 15:0

[F:0]

Test pattern seed A bits 15:0 R/W

0x0000

Table 6.360 PCS 10GBASE-R Test Pattern Seed A 1: Address 3.22

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6.7.17 PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23

6.7.18 PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24

6.7.19 PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25

Bit Name Description Type Default Note

F:0 Test Pattern

Seed A Bits

31:16 [1F:10]

Test pattern seed A bits 31:16 R/W

0x0000

Table 6.361 PCS 10GBASE-R Test Pattern Seed A 2: Address 3.23

Bit Name Description Type Default Note

F:0 Test Pattern

Seed A Bits

47:32 [2F:20]

Test pattern seed A bits 47:32 R/W

0x0000

Table 6.362 PCS 10GBASE-R Test Pattern Seed A 3: Address 3.24

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Test Pattern

Seed A Bits

57:48 [39:30]

Test pattern seed A bits 57:48 R/W

0x000

Table 6.363 PCS 10GBASE-R Test Pattern Seed A 4: Address 3.25

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6.7.20 PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26

6.7.21 PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27

6.7.22 PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28

Bit Name Description Type Default Note

F:0 Test Pattern

Seed B Bits 15:0

[F:0]

Test pattern seed B bits 15:0 R/W

0x0000

Table 6.364 PCS 10GBASE-R Test Pattern Seed B 1: Address 3.26

Bit Name Description Type Default Note

F:0 Test Pattern

Seed B Bits

31:16 [1F:10]

Test pattern seed B bits 31:16 R/W

0x0000

Table 6.365 PCS 10GBASE-R Test Pattern Seed B 2: Address 3.27

Bit Name Description Type Default Note

F:0 Test Pattern

Seed B Bits

47:32 [2F:20]

Test pattern seed B bits 47:32 R/W

0x0000

Table 6.366 PCS 10GBASE-R Test Pattern Seed B 3: Address 3.28

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6.7.23 PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29

6.7.24 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Test Pattern

Seed B Bits

57:48 [39:30]

Test pattern seed B bits 57:48 R/W

0x000

Table 6.367 PCS 10GBASE-R Test Pattern Seed B 4: Address 3.29

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 PRBS9 Transmit

Test-Pattern

Enable

1 = Enable PRBS9 test-pattern mode on

the transmit path

0 = Disable PRBS9 test-pattern mode

on the transmit path

R/W

5 PRBS31

Receive

Test-Pattern

Enable

1 = Enable PRBS31 test-pattern mode

on the receive path

0 = Enable PRBS31 test-pattern mode

on the receive path

R/W

4 PRBS31

Transmit

Test-Pattern

Enable

1 = Enable PRBS31 test-pattern mode

on the transmit path

0 = Enable PRBS31 test-pattern mode

on the transmit path

R/W

3 Transmit

Test-Pattern

Enable

1 = Enable transmit test pattern

0 = Disable transmit test pattern

R/W

Table 6.368 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A

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6.7.25 PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B

6.7.26 TimeSync PCS Capability: Address 3.1800

2 Receive

Test-Pattern

Enable

1 = Enable receive test-pattern testing

0 = Disable receive test-pattern testing

R/W

1 Test-Pattern

Select

1 = Square wave test pattern

0 = Pseudo random test pattern

R/W

0 Data Pattern

Select

1 = Zeros data pattern

0 = LF data pattern

R/W

Bit Name Description Type Default Note

F:0 Test-Pattern

Error Counter

[F:0]

Error Counter R/W

0x0000

Table 6.369 PCS 10GBASE-R PCS Test-Pattern Error Counter: Address 3.2B

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

Table 6.370 TimeSync PCS Capability: Address 3.1800

Bit Name Description Type Default Note

Table 6.368 PCS 10GBASE-R PCS Test-Pattern Control: Address 3.2A

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6.7.27 TimeSync PCS Transmit Path Data Delay 1: Address 3.1801

6.7.28 TimeSync PCS Transmit Path Data Delay 2: Address 3.1802

1 TimeSync

Transmit Path

Data Delay

1 = PCS provides information on

transmit path data delay in registers

3.1801 through 3.1804

0 = PCS does not provide information on

transmit path data delay

0 TimeSync

Receive Path

Data Delay

1 = PCS provides information on receive

path data delay in registers 3.1805

through 3.1808

0 = PCS does not provide information on

receive path data delay

Bit Name Description Type Default Note

F:0 Maximum PCS

Transmit Path

Data Delay LSW

[F:0]

LSW of maximum PCS transmit delay in

nanoseconds

Table 6.371 TimeSync PCS Transmit Path Data Delay 1: Address 3.1801

Bit Name Description Type Default Note

F:0 Maximum PCS

Transmit Path

Data Delay

MSW [F:0]

MSW of maximum PCS transmit delay in

nanoseconds

Table 6.372 TimeSync PCS Transmit Path Data Delay 2: Address 3.1802

Bit Name Description Type Default Note

Table 6.370 TimeSync PCS Capability: Address 3.1800

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6.7.29 TimeSync PCS Transmit Path Data Delay 3: Address 3.1803

6.7.30 TimeSync PCS Transmit Path Data Delay 4: Address 3.1804

6.7.31 TimeSync PCS Receive Path Data Delay 1: Address 3.1805

Bit Name Description Type Default Note

F:0 Minimum PCS

Transmit Path

Data Delay LSW

[F:0]

LSW of minimum PCS transmit delay in

nanoseconds

Table 6.373 TimeSync PCS Transmit Path Data Delay 3: Address 3.1803

Bit Name Description Type Default Note

F:0 Minimum PCS

Transmit Path

Data Delay

MSW [F:0]

MSW of minimum PCS transmit delay in

nanoseconds

Table 6.374 TimeSync PCS Transmit Path Data Delay 4: Address 3.1804

Bit Name Description Type Default Note

F:0 Maximum PCS

Receive Path

Data Delay LSW

[F:0]

LSW of maximum PCS receive delay in

nanoseconds

Table 6.375 TimeSync PCS Receive Path Data Delay 1: Address 3.1805

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6.7.32 TimeSync PCS Receive Path Data Delay 2: Address 3.1806

6.7.33 TimeSync PCS Receive Path Data Delay 3: Address 3.1807

6.7.34 TimeSync PCS Receive Path Data Delay 4: Address 3.1808

Bit Name Description Type Default Note

F:0 Maximum PCS

Receive Path

Data Delay

MSW [F:0]

MSW of maximum PCS receive delay in

nanoseconds

Table 6.376 TimeSync PCS Receive Path Data Delay 2: Address 3.1806

Bit Name Description Type Default Note

F:0 Minimum PCS

Receive Path

Data Delay LSW

[F:0]

LSW of minimum PCS receive delay in

nanoseconds

Table 6.377 TimeSync PCS Receive Path Data Delay 3: Address 3.1807

Bit Name Description Type Default Note

F:0 Minimum PCS

Receive Path

Data Delay

MSW [F:0]

MSW of minimum PCS receive delay in

nanoseconds

Table 6.378 TimeSync PCS Receive Path Data Delay 4: Address 3.1808

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6.7.35 PCS Transmit Vendor Provisioning 1: Address 3.C400

6.7.36 PCS Transmit Vendor Provisioning 2: Address 3.C401

6.7.37 PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0PCS Tx

Auxilliary Bit

Value

The value that will be set in the auxilliary

bit of the PCS transmission frame

R/W

0 This bit is currently undefined in the 802.3an

standard.

Table 6.379 PCS Transmit Vendor Provisioning 1: Address 3.C400

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.380 PCS Transmit Vendor Provisioning 2: Address 3.C401

Bit Name Description Type Default Note

F:1 Reserved

Transmit

Provisioning 1

[F:1]

Reserved for future use R/W

0x0000

0 PCS IEEE

Loopback

Passthrough

Disable

1 = Disable data passthrough on IEEE

loopback

R/W

0 When set, this bit disables the output of the

PHY when IEEE loopback is set.

Table 6.381 PCS Transmit Reserved Vendor Provisioning 1: Address 3.C410

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6.7.38 PCS Transmit XFI Vendor Provisioning 1: Address 3.C455

6.7.39 PCS Transmit XFI Vendor Provisioning 2: Address 3.C456

6.7.40 PCS Transmit XFI Vendor Provisioning 3: Address 3.C457

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed A Word 0

[F:0]

XFI test pattern seed A bits 15:0 R/W 0x0000 10GBASE-R Test Pattern Seed A

Used for both XFI0 and XFI1.

Table 6.382 PCS Transmit XFI Vendor Provisioning 1: Address 3.C455

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed A Word 1

[F:0]

XFI test pattern seed A bits 31:16 R/W 0x0000 10GBASE-R Test Pattern Seed A

Used for both XFI0 and XFI1.

Table 6.383 PCS Transmit XFI Vendor Provisioning 2: Address 3.C456

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed A Word 2

[F:0]

XFI test pattern seed A bits 47:32 R/W 0x0000 10GBASE-R Test Pattern Seed A

Used for both XFI0 and XFI1.

Table 6.384 PCS Transmit XFI Vendor Provisioning 3: Address 3.C457

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6.7.41 PCS Transmit XFI Vendor Provisioning 4: Address 3.C458

6.7.42 PCS Transmit XFI Vendor Provisioning 5: Address 3.C459

6.7.43 PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI Test Pattern

Seed A Word 3

[9:0]

XFI test pattern seed A bits 57:48 R/W 0x000 10GBASE-R Test Pattern Seed A

Used for both XFI0 and XFI1.

Table 6.385 PCS Transmit XFI Vendor Provisioning 4: Address 3.C458

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed B Word 0

[F:0]

XFI test pattern seed B bits 15:0 R/W 0x0000 10GBASE-R Test Pattern Seed B

Used for both XFI0 and XFI1.

Table 6.386 PCS Transmit XFI Vendor Provisioning 5: Address 3.C459

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed B Word 1

[F:0]

XFI test pattern seed B bits 31:16 R/W 0x0000 10GBASE-R Test Pattern Seed B

Used for both XFI0 and XFI1.

Table 6.387 PCS Transmit XFI Vendor Provisioning 6: Address 3.C45A

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6.7.44 PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B

6.7.45 PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C

6.7.46 PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460

Bit Name Description Type Default Note

F:0 XFI Test Pattern

Seed B Word 2

[F:0]

XFI test pattern seed B bits 47:32 R/W 0x0000 10GBASE-R Test Pattern Seed B

Used for both XFI0 and XFI1.

Table 6.388 PCS Transmit XFI Vendor Provisioning 7: Address 3.C45B

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI Test Pattern

Seed B Word 3

[9:0]

XFI test pattern seed B bits 57:48 R/W 0x000 10GBASE-R Test Pattern Seed B

Used for both XFI0 and XFI1.

Table 6.389 PCS Transmit XFI Vendor Provisioning 8: Address 3.C45C

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 XFI0 PCS

Scrambler

Disable

1 = Disable PCS scrambler R/W

0 PCS Scrambler Disable (default: 0)

0 Reserved Internal reserved - do not modify

Table 6.390 PCS Transmit XFI0 Vendor Provisioning 1: Address 3.C460

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6.7.47 PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 XFI0 Test

Sqaure Wave

Test Duration

0 = 6 ones followed by 6 zeroes

1 = 11 ones followed by 11 zeroes

R/W 0 10GBASE-R Square Wave Test Duration.

Repeating pattern of n ones, followed by n

zeros, where n = 6 or 11 (0:n= 6, 1:n=11,

default:0)

8 XFI0 Test Data

Select

1 = Data pattern select R/W 0 10GBASE-R Data Pattern Select (0:LF,

1:Zero, default:0)

7 XFI0 Test Mode

Select

1 = Test pattern select R/W 0 10GBASE-R Test Pattern Select (0:Pseudo

random, 1:Square wave, default:0)

6 XFI0 Test

PRBS-9 Enable

1 = Test pattern PRBS-9 enabled R/W 0 10GBASE-R PRBS 9 Test Pattern Enable

(0:disable, 1:enable, default:0)

5 XFI0 Test

PRBS-31

Enable

1 = Test pattern PRBS-31 enabled R/W 0 10GBASE-R PRBS 31 Test Pattern Enable

(0:disable, 1:enable, default:0)

4 XFI0 Test

Pattern Enable

1 = Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern

Enable (0:disable, 1:enable, default:0)

3 XFI0 Local Fault

Inject

1 = Inject local fault R/W 0 Inject Local_Fault (default:0)

2 XFI0 Inject

Single Error

1 = Inject single Error R/W 0 Inject single error on the 10GBASE-R Test

Pattern including pseudo-random, PRB31 or

PRBS9 (default:0)

1 XFI0 PCS High

BER Inject

1 = Inject PCS High BER R/W 0 Inject error to cause HI_BER at far-end

(default:0)

0 XFI0 PCS Loss

Of Lock Inject

1 = Inject loss of lock R/W 0 Inject error to cause loss of block_lock at

far-end (default:0)

Table 6.391 PCS Transmit XFI0 Vendor Provisioning 2: Address 3.C461

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6.7.48 PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470

6.7.49 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 XFI1 PCS

Scrambler

Disable

1 = Disable PCS scrambler R/W

0 PCS Scrambler Disable (default: 0)

0 Reserved Internal reserved - do not modify

Table 6.392 PCS Transmit XFI1 Vendor Provisioning 1: Address 3.C470

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 XFI1 Test

Sqaure Wave

Test Duration

0 = 6 ones followed by 6 zeroes

1 = 11 ones followed by 11 zeroes

R/W 0 10GBASE-R Square Wave Test Duration.

Repeating pattern of n ones, followed by n

zeros, where n = 6 or 11 (0:n= 6, 1:n=11,

default:0)

8 XFI1 Test Data

Select

1 = Data pattern select R/W 0 10GBASE-R Data Pattern Select (0:LF,

1:Zero, default:0)

7 XFI1 Test Mode

Select

1 = Test pattern select R/W 0 10GBASE-R Test Pattern Select (0:Pseudo

random, 1:Square wave, default:0)

Table 6.393 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471

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6 XFI1 Test

PRBS-9 Enable

1 = Test pattern PRBS-9 enabled R/W 0 10GBASE-R PRBS 9 Test Pattern Enable

(0:disable, 1:enable, default:0)

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

5 XFI1 Test

PRBS-31

Enable

1 = Test pattern PRBS-31 enabled R/W 0 10GBASE-R PRBS 31 Test Pattern Enable

(0:disable, 1:enable, default:0)

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

4 XFI1 Test

Pattern Enable

1 = Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern

Enable (0:disable, 1:enable, default:0)

3 XFI1 Local Fault

Inject

1 = Inject local fault R/W 0 Inject Local_Fault (default:0)

2 XFI1 Inject

Single Error

1 = Inject single Error R/W 0 Inject single error on the 10GBASE-R Test

Pattern including pseudo-random, PRB31 or

PRBS9 (default:0)

1 XFI1 PCS High

BER Inject

1 = Inject PCS High BER R/W 0 Inject error to cause HI_BER at far-end

(default:0)

0 XFI1 PCS Loss

Of Lock Inject

1 = Inject loss of lock R/W 0 Inject error to cause loss of block_lock at

far-end (default:0)

Bit Name Description Type Default Note

Table 6.393 PCS Transmit XFI1 Vendor Provisioning 2: Address 3.C471

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6.7.50 PCS USX0 Memory Control Register: Address 3.C4C0

6.7.51 PCS USX0 Control Register 1: Address 3.C4C1

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 USX0 Memory

power down

USX0 Memory power down R/W 0

5:0 USX0 Memory

RM [5:0]

USX0 Memory RM bits R/W 0x00

Table 6.394 PCS USX0 Memory Control Register: Address 3.C4C0

Bit Name Description Type Default Note

F USX0 Clock

Enable

USX0 Clock Enable R/W 1 Enable clock of USX0 block

E USX0 Bypass USX0 Bypass R/W 0 Bypass USX0 block. This can be set to one to

bypass USX for regular XFI 10G operation to

reduce latency and power.

D USX0 Link FIFO

Mode

USX0 Link FIFO Mode R/W 0 This shall be set to one to enable

frame-adaptation in USX0 for AQRate

5G/2.5G mode.

CUSX0

Replication

Mode

USX0 Replication Mode R/W 1 Set to 1 to select word-based replication. Set to

0 to select byte-based replication. Always set

this to 1 (default).

B:8 Reserved Internal reserved - do not modify

7 USX0 PCS

Reset

USX0 PCS Reset R/W 0 PCS Reset

Table 6.395 PCS USX0 Control Register 1: Address 3.C4C1

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6.7.52 PCS USX0 Local fault Control Register: Address 3.C4C2

6 USX0 PCS low

power

USX0 PCS low power R/W 0 PCS Low Power

5USX0 Parity

check sense

USX0 Parity check sense (default:0) R/W 0 Always leave to 0. Set to1 to force parity error

for diagnostics.

4:3 USX0 Speed

mode[1:0]

USX0 Speed mode (00:based on

AQRate mode, 10:1G, 11:100M)

R/W 0x0 Configure link speed. Set to 0 to select 10G or

AQRate mode. Otherwise, set to 2 or 3 to

select 1G or 100M mode.

2:1 USX0 AQRate

mode[1:0]

USX0 AQRate mode (00:10G, 10:5G,

11:2.5G)

R/W 0x0 This register is ignored if the USX0 Speed

mode is set to non-zero (1G or 100M mode).

0 USX0 XGS RKL

mode

USX0 XGS RKL mode R/W 0 This shall be set to1 to enable XGS to support

USX0.

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 USX0 Inject Tx

Local_Fault

USX0 Inject Tx USXGMII Local_Fault

(default:0)

R/W 0 Toggle this bit to inject single Local_Fault

towards the external MAC.

7:0 USX0

Local_Fault

code[7:0]

USX0 USXGMII Local_Fault code

(default:0x11)

R/W 0x11 Configure the LSB 8-bit of the Local_Fault

codeword.

Table 6.396 PCS USX0 Local fault Control Register: Address 3.C4C2

Bit Name Description Type Default Note

Table 6.395 PCS USX0 Control Register 1: Address 3.C4C1

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6.7.53 PCS USX0 MAC Local fault Control Register: Address 3.C4C3

6.7.54 PCS USX0 Auto-Neg Control Register: Address 3.C4C4

Bit Name Description Type Default Note

F:8 USX0 user

define code[7:0]

USX0 User-defined code to replace

USXGMII

Local_Fault received (default:0x01).

R/W 0x01 Configure the LSB 8-bit to replace the Rx

USXGMII Local_Fault codeword if enabled.

7 USX0 Inject

Local Fault

signal

USX0 Inject Local Fault signal towards

the MAC in 1G/100M mode (default:0)

R/W 0 Set to1 to inject Local_Fault towards the

external MAC in 1G/100M mode continuously

with the progammable gap.

6:0 USX0 Number of

Idle coulmn[6:0]

USX0 Number of Idle coulmn between

Local Fault signals (0 to 127, default:31)

R/W 0x1F Configures the number of Idle column between

Local_Fault signals during injection in

1G/100M mode.

Table 6.397 PCS USX0 MAC Local fault Control Register: Address 3.C4C3

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9USX0 Restart

Auto-Negotiatio

USX0 Restart Auto-Negotiation R/W 0 Toggle this bit to restart USXGMII

Auto-Negotiation.

8 USX0 Auto-neg

Enable

USX0 Auto negotiation Enable R/W 0 Set to 1 to enable USXGMII Auto-Negotiation.

7:0 USX0 Auto neg

Message

code[7:0]

USX0 USXGMII Auto-Negotiation

Message Opcode.

R/W 0x03 Configure the message opcode for USXGMII

Auto-Negotiation.

Table 6.398 PCS USX0 Auto-Neg Control Register: Address 3.C4C4

255

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6.7.55 PCS USX0 PTP Control Register: Address 3.C4C5

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 USX0 Tx Rsvd

Control[3:0]

USX0 Transmit Reserved Control R/W 0x0 Bit 0: Set to 1 to insert USXGMII Local Fault

when the Link FIFO is empty

Bit 1: reserved

Bit 2: Set to 1 to swap bit-order of CRC

Bit 3: Set to 1 to swap byte-order of CRC

7 Reserved Internal reserved - do not modify

6 USX0 Header

CRC Gen

USX0 Header CRC Generation Enable R/W 0 Set to 1 to generate CRC for the Packet

Information Message and replace the SFD

byte of transmit frame.

5 USX0 Enable

PTP timestamp

USX0 Enable the injection of PTP

timestamp into Extension Field of the

Packet Information Message

R/W 0 Enable the injection of PTP timestamp into

Extension Field of the Packet Information

Message

4 USX0 Enable

Packet

Information

Message

USX0 Enable the injection of the Packet

Information Message

R/W 0 Enable the injection of the Packet Information

Message

3:0 USX0 GMII to

XGMII

Conversion

Control[3:0]

USX0 GMII/MII to XGMII Conversion

Control

R/W 0x0 Bit 0: Disable continuous Idle insertion to

MAC when FIFO depth is below the IFG

thresh

Bit 1: Enable error char insertion to MAC

upon corrupted or missing SFD

Bit 2: Enable Idle deletion to MAC when

FIFO depth is beyond the high thresh

Bit 3: Reserved

Table 6.399 PCS USX0 PTP Control Register: Address 3.C4C5

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6.7.56 PCS USX0 PKT Info Message Register-0: Address 3.C4C6

6.7.57 PCS USX0 PKT Info Message Register-1: Address 3.C4C7

6.7.58 PCS USX0 PKT Info Message Register-2: Address 3.C4C8

Bit Name Description Type Default Note

F:0 USX0 Packet

info message

15:0 [F:0]

USX0 Packet Information Message to

be injected bits [15:0]

R/W 0x0000 Configure the message word before enabling

the injection.

Table 6.400 PCS USX0 PKT Info Message Register-0: Address 3.C4C6

Bit Name Description Type Default Note

F:0 USX0 Packet

info message

31:16 [1F:10]

USX0 Packet Information Message to

be injected bits [31:16]

R/W 0x0000

Table 6.401 PCS USX0 PKT Info Message Register-1: Address 3.C4C7

Bit Name Description Type Default Note

F:0 USX0 Packet

info message

47:32 [2F:20]

USX0 Packet Information Message to

be injected bits [47:32]

R/W 0x0000

Table 6.402 PCS USX0 PKT Info Message Register-2: Address 3.C4C8

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6.7.59 PCS USX0 link Fill Data Register-0: Address 3.C4C9

6.7.60 PCS USX0 link Fill Data Register-1: Address 3.C4CA

6.7.61 PCS USX0 Link FIFO Control Register: Address 3.C4CB

Bit Name Description Type Default Note

F:0 USX0 XGMII

Link Fill

Word[F:0]

USX0 XGMII data for link fill word[15:0] R/W 0xBAD

This has to be different from

normal control words in standard XGMII

traffic.

Table 6.403 PCS USX0 link Fill Data Register-0: Address 3.C4C9

Bit Name Description Type Default Note

F:0 USX0 XGMII

Link Fill

Word[1F:10]

USX0 XGMII data for link fill word[31:16] R/W 0xBAD

Table 6.404 PCS USX0 link Fill Data Register-1: Address 3.C4CA

Bit Name Description Type Default Note

F:A USX0 High

Threshold[5:0]

USX0 Configure the high threshold for

the link FIFO

R/W 0x14 When the link FIFO is beyond this threshold, it

requests the upstream to pause traffic by

inserting link fill words. When link FIFO mode

is set to one, idle words can also be deleted.

9:5 USX0 Low

Threshold[4:0]

USX0 Configure the low threshold for

the link FIFO

R/W 0x0A When the link FIFO is below this threshold, idle

words can be inserted if link FIFO mode is set

to one.

Table 6.405 PCS USX0 Link FIFO Control Register: Address 3.C4CB

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6.7.62 PCS USX0 TX FIFO Control Register: Address 3.C4CC

4 USX0 Link Fifo

Reset

USX0 Set to 1 to force link FIFO to reset

This FIFO is only used for AQRate

5G/2.5G mode.

R/W 0

3:0 USX0 Link Fill

Control[3:0]

USX0 XGMII control for link fill word. R/W 0xF

Bit Name Description Type Default Note

F:D Reserved Internal reserved - do not modify

C USX0 TX FIFO

Reset

USX0 MAC Tx FIFO reset R/W 0

B:8 USX0 TX FIFO

threshold[3:0]

USX0 MAC Tx FIFO threshold

This is used to establish minimum FIFO

depth before starting to read.

R/W 0x1

7:4 USX0 Tx FIFO

IFG

threshold[3:0]

USX0 MAC Tx FIFO IFG threshold

This is used to insert Idle when FIFO

depth is below this threshold.

R/W 0x8

3:0 USX0 Tx FIFO hi

threshold[3:0]

USX0 MAC Tx FIFO High threshold

This is used to delete Idle when FIFO

depth is beyond this threshold.

R/W 0xA

Table 6.406 PCS USX0 TX FIFO Control Register: Address 3.C4CC

Bit Name Description Type Default Note

Table 6.405 PCS USX0 Link FIFO Control Register: Address 3.C4CB

259

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6.7.63 PCS USX0 Local Advertisement Register: Address 3.C4CD

Bit Name Description Type Default Note

F USX0 Local

Status

USX0 Local advertisement status.

0 = Link down

1 = Link up

R/W 0

E:D Reserved USX0

Local

Advertisement 0

[1:0]

Reserved for future use. R/W 0x0

C USX0 Local

Duplex

USX0 Local advertisement duplex.

0 = Half duplex

1 = Full duplex

R/W 0

B:9 USX0 Local

Speed [2:0]

USX0 Local advertisement speed.

0 = 10M

1 = 100M

2 = 1G

3 = 10G

4 = 2.5G

5 = 5G

R/W 0x0

8 USX0 Local

EEE Capability

USX0 Local advertisement EEE

capability.

0 = Not supported

1 = Supported

R/W 0

7 USX0 Local

EEE Clock Stop

Capability

USX0 Local advertisement EEE Clock

Stop capability.

0 = Not supported

1 = Supported

R/W 0

Table 6.407 PCS USX0 Local Advertisement Register: Address 3.C4CD

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6.7.64 PCS USX1 Memory Control Register: Address 3.C4E0

6.7.65 PCS USX1 Control Register 1: Address 3.C4E1

6:1 Reserved USX0

Local

Advertisement 1

[5:0]

Reserved for future use. R/W 0x00

0 USX0 Local

Mode

USX0 Local advertisement mode.

0 = SGMII

1 = USXGMII

R/W 1

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 USX1 Memory

power down

USX1 Memory power down R/W 0

5:0 USX1 Memory

RM [5:0]

USX1 Memory RM bits R/W 0x00

Table 6.408 PCS USX1 Memory Control Register: Address 3.C4E0

Bit Name Description Type Default Note

F USX1 Clock

Enable

USX1 Clock Enable R/W 1 Enable clock of USX1 block

E USX1 Bypass USX1 Bypass R/W 0 Bypass USX1 block. This can be set to one to

bypass USX for regular XFI 10G operation to

reduce latency and power.

Table 6.409 PCS USX1 Control Register 1: Address 3.C4E1

Bit Name Description Type Default Note

Table 6.407 PCS USX0 Local Advertisement Register: Address 3.C4CD

261

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D USX1 Link FIFO

Mode

USX1 Link FIFO Mode R/W 0 This can be set to one to enable

frame-adaptation in USX1 for AQRate

5G/2.5G mode.

CUSX1

Replication

Mode

USX1 Replication Mode R/W 1 Set to 1 to select word-based replication. Set to

0 to select byte-based replication. Always set

this to 1 (default).

B:8 Reserved Internal reserved - do not modify

7 USX1 PCS

Reset

USX1 PCS Reset R/W 0

6 USX1 PCS low

power

USX1 PCS low power R/W 0

5USX1 Parity

check sense

USX1 Parity check sense R/W 0

4:3 USX1 Speed

mode[1:0]

USX1 Speed mode (00:10G, 10:1G,

11:100M)

R/W 0x0

2:1 USX1 AQRate

mode[1:0]

USX1 AQRate mode (00:10G, 10:5G,

11:2.5G)

R/W 0x0

0 USX1 XGS RKL

mode

USX1 XGS RKL mode R/W 0

Bit Name Description Type Default Note

Table 6.409 PCS USX1 Control Register 1: Address 3.C4E1

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6.7.66 PCS USX1 Local fault Control Register: Address 3.C4E2

6.7.67 PCS USX1 MAC Local fault Control Register: Address 3.C4E3

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 USX1 Inject Tx

Local_Fault

USX1 Inject Tx USXGMII Local_Fault R/W 0

7:0 USX1

Local_Fault

code[7:0]

USX1 USXGMII Local_Fault code R/W 0x11

Table 6.410 PCS USX1 Local fault Control Register: Address 3.C4E2

Bit Name Description Type Default Note

F:8 USX1 user

define code[7:0]

USX1 User-defined code to replace

USXGMII

Local_Fault received.

R/W 0x01

7 USX1 Inject

Local Fault

signal

USX1 Inject Local Fault signal towards

the MAC in 1G/100M mode

R/W 0

6:0 USX1 Number of

Idle coulmn[6:0]

USX1 Number of Idle coulmn between

Local Fault signals

R/W 0x1F

Table 6.411 PCS USX1 MAC Local fault Control Register: Address 3.C4E3

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6.7.68 PCS USX1 Auto-Neg Control Register: Address 3.C4E4

6.7.69 PCS USX1 PTP Control Register: Address 3.C4E5

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9USX1 Restart

Auto-Negotiatio

USX1 Restart Auto-Negotiation R/W 0

8 USX1 Auto-neg

Enable

USX1 Auto negotiation Enable R/W 0

7:0 USX1 Auto neg

Message

code[7:0]

USX1 USXGMII Auto-Negotiation

Message Opcode.

R/W 0x03

Table 6.412 PCS USX1 Auto-Neg Control Register: Address 3.C4E4

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 USX1 Tx Rsvd

Control[3:0]

USX1 Transmit Reserved Control R/W 0x0

7 Reserved Internal reserved - do not modify

6 USX1 Header

CRC Gen

USX1 Header CRC Generation Enable R/W 0

5 USX1 Enable

PTP timestamp

USX1 Enable the injection of PTP

timestamp into Extension Field of the

Packet Information Message

R/W 0

Table 6.413 PCS USX1 PTP Control Register: Address 3.C4E5

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6.7.70 PCS USX1 PKT Info Message Register-0: Address 3.C4E6

4 USX1 Enable

Packet

Information

Message

USX1 Enable the injection of the Packet

Information Message

R/W 0

3:0 USX1 GMII to

XGMII

Conversion

Control[3:0]

USX1 GMII/MII to XGMII Conversion

Control

Bit 0: Disable continuous Idle insertion to

MAC when FIFO depth is below the IFG

thresh

Bit 1: Enable error char insertion to MAC

upon corrupted or missing SFD

Bit 2: Enable Idle deletion to MAC when

FIFO depth is beyond the high thresh

Bit 3: Reserved

R/W 0x0

Bit Name Description Type Default Note

F:0 USX1 Packet

info message

15:0 [F:0]

USX1 Packet Information Message to

be injected bits [15:0]

R/W 0x0000

Table 6.414 PCS USX1 PKT Info Message Register-0: Address 3.C4E6

Bit Name Description Type Default Note

Table 6.413 PCS USX1 PTP Control Register: Address 3.C4E5

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6.7.71 PCS USX1 PKT Info Message Register-1: Address 3.C4E7

6.7.72 PCS USX1 PKT Info Message Register-2: Address 3.C4E8

6.7.73 PCS USX1 link Fill Data Register-0: Address 3.C4E9

Bit Name Description Type Default Note

F:0 USX1 Packet

info message

31:16 [1F:10]

USX1 Packet Information Message to

be injected bits [31:16]

R/W 0x0000

Table 6.415 PCS USX1 PKT Info Message Register-1: Address 3.C4E7

Bit Name Description Type Default Note

F:0 USX1 Packet

info message

47:32 [2F:20]

USX1 Packet Information Message to

be injected bits [47:32]

R/W 0x0000

Table 6.416 PCS USX1 PKT Info Message Register-2: Address 3.C4E8

Bit Name Description Type Default Note

F:0 USX1 XGMII

Link Fill

Word[F:0]

USX1 XGMII data for link fill word[15:0] R/W 0xBAD

Table 6.417 PCS USX1 link Fill Data Register-0: Address 3.C4E9

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6.7.74 PCS USX1 link Fill Data Register-1: Address 3.C4EA

6.7.75 PCS USX1 Link FIFO Control Register: Address 3.C4EB

Bit Name Description Type Default Note

F:0 USX1 XGMII

Link Fill

Word[1F:10]

USX1 XGMII data for link fill word[31:16] R/W 0xBAD

Table 6.418 PCS USX1 link Fill Data Register-1: Address 3.C4EA

Bit Name Description Type Default Note

F:A USX1 High

Threshold[5:0]

Configure the high threshold for the link

FIFO

R/W 0x14 When the link FIFO is beyond this threshold, it

requests the upstream to pause traffic by

inserting link fill words. When link FIFO mode

is set to one, idle words can also be deleted.

9:5 USX1 Low

Threshold[4:0]

Configure the low threshold for the link

FIFO

R/W 0x0A When the link FIFO is below this threshold, idle

words can be inserted if link FIFO mode is set

to one.

4 USX1 Link Fifo

Reset

Set to 1 to force link FIFO to reset This

FIFO is only used for AQRate

5G/2.5G mode.

R/W 0

3:0 USX1 Link Fill

Control[3:0]

USX1 XGMII control for link fill word. R/W 0xF

Table 6.419 PCS USX1 Link FIFO Control Register: Address 3.C4EB

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6.7.76 PCS USX1 TX FIFO Control Register: Address 3.C4EC

6.7.77 PCS USX1 Local Advertisement Register: Address 3.C4ED

Bit Name Description Type Default Note

F:D Reserved Internal reserved - do not modify

C USX1 TX FIFO

Reset

USX1 MAC Tx FIFO reset R/W 0

B:8 USX1 TX FIFO

threshold[3:0]

USX1 MAC Tx FIFO threshold

This is used to establish minimum FIFO

depth before starting to read.

R/W 0x1

7:4 USX1 Tx FIFO

IFG

threshold[3:0]

USX1 MAC Tx FIFO IFG threshold

This is used to insert Idle when FIFO

depth is below this threshold.

R/W 0x8

3:0 USX1 Tx FIFO hi

threshold[3:0]

USX1 MAC Tx FIFO High threshold

This is used to delete Idle when FIFO

depth is beyond this threshold.

R/W 0xA

Table 6.420 PCS USX1 TX FIFO Control Register: Address 3.C4EC

Bit Name Description Type Default Note

F USX1 Local

Status

USX1 Local advertisement status.

0 = Link down

1 = Link up

R/W 0

E:D Reserved USX1

Local

Advertisement 0

[1:0]

Reserved for future use. R/W 0x0

Table 6.421 PCS USX1 Local Advertisement Register: Address 3.C4ED

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C USX1 Local

Duplex

USX1 Local advertisement duplex.

0 = Half duplex

1 = Full duplex

R/W 0

B:9 USX1 Local

Speed [2:0]

USX1 Local advertisement speed.

0 = 10M

1 = 100M

2 = 1G

3 = 10G

4 = 2.5G

5 = 5G

R/W 0x0

8 USX1 Local

EEE Capability

USX1 Local advertisement EEE

capability.

0 = Not supported

1 = Supported

R/W 0

7 USX1 Local

EEE Clock Stop

Capability

USX1 Local advertisement EEE Clock

Stop capability.

0 = Not supported

1 = Supported

R/W 0

6:1 Reserved USX1

Local

Advertisement 1

[5:0]

Reserved for future use. R/W 0x00

0 USX1 Local

Mode

USX1 Local advertisement mode.

0 = SGMII

1 = USXGMII

R/W 1

Bit Name Description Type Default Note

Table 6.421 PCS USX1 Local Advertisement Register: Address 3.C4ED

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6.7.78 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0

Bit Name Description Type Default Note

F:E Serdes Mux

Swap TX Lane 3

[1:0]

The lane swap setting for Lane 3, in the

Tx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 3, 1=lane 0, 2=lane 1, 3=lane 2

D:C Serdes Mux

Swap TX Lane 2

[1:0]

The lane swap setting for Lane 2, in the

Tx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 2, 1=lane 3, 2=lane 0, 3=lane 1

B:A Serdes Mux

Swap TX Lane 1

[1:0]

The lane swap setting for Lane 1, in the

Tx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 1, 1=lane 2, 2=lane 3, 3=lane 0

9:8 Serdes Mux

Swap TX Lane 0

[1:0]

The lane swap setting for Lane 0, in the

Tx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 0, 1=lane 1, 2=lane 2, 3=lane 3

7:6 Serdes Mux

Swap RX Lane 3

[1:0]

The lane swap setting for Lane 3, in the

Rx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 3, 1=lane 0, 2=lane 1, 3=lane 2

5:4 Serdes Mux

Swap RX Lane 2

[1:0]

The lane swap setting for Lane 2, in the

Rx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 2, 1=lane 3, 2=lane 0, 3=lane 1

Table 6.422 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0

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6.7.79 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820

6.7.80 PCS Transmit Vendor FCS No Error Frame Counter 2: Address 3.C821

3:2 Serdes Mux

Swap RX Lane 1

[1:0]

The lane swap setting for Lane 1, in the

Rx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 1, 1=lane 2, 2=lane 3, 3=lane 0

1:0 Serdes Mux

Swap RX Lane 0

[1:0]

The lane swap setting for Lane 0, in the

Rx direction. It is implemented at the

internal interface between the SerDes

and digital logic.

R/W 0x0 0=lane 0, 1=lane 1, 2=lane 2, 3=lane 3

Bit Name Description Type Default Note

F:0 10GBASE-T

Good Frame

Counter LSW

[F:0]

10GBASE-T Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.423 PCS Transmit Vendor FCS No Error Frame Counter 1: Address 3.C820

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 10GBASE-T

Good Frame

Counter MSW

[19:10]

10GBASE-T Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.424 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823

Bit Name Description Type Default Note

Table 6.422 PCS SERDES MUX Swap TXRX Register: Address 3.C4F0

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6.7.81 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822

6.7.82 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823

6.7.83 PCS Transmit XFI0 Vendor State 1: Address 3.C860

Bit Name Description Type Default Note

F:0 10GBASE-T

Error Frame

Counter LSW

[F:0]

10GBASE-T Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.425 PCS Transmit Vendor FCS Error Frame Counter 1: Address 3.C822

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 10GBASE-T

Error Frame

Counter MSW

[19:10]

10GBASE-T Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.426 PCS Transmit Vendor FCS Error Frame Counter 2: Address 3.C823

Bit Name Description Type Default Note

F:0 XFI0 Good

Frame Counter

LSW [F:0]

XFI0 Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.427 PCS Transmit XFI0 Vendor State 1: Address 3.C860

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6.7.84 PCS Transmit XFI0 Vendor State 2: Address 3.C861

6.7.85 PCS Transmit XFI0 Vendor State 3: Address 3.C862

6.7.86 PCS Transmit XFI0 Vendor State 4: Address 3.C863

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI0 Good

Frame Counter

MSW [9:0]

XFI0 Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.428 PCS Transmit XFI0 Vendor State 2: Address 3.C861

Bit Name Description Type Default Note

F:0 XFI0 Bad Frame

Counter LSW

[F:0]

XFI0 Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.429 PCS Transmit XFI0 Vendor State 3: Address 3.C862

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI0 Bad Frame

Counter MSW

[9:0]

XFI0 Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.430 PCS Transmit XFI0 Vendor State 4: Address 3.C863

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6.7.87 PCS Transmit XFI1 Vendor State 1: Address 3.C870

6.7.88 PCS Transmit XFI1 Vendor State 2: Address 3.C871

6.7.89 PCS Transmit XFI1 Vendor State 3: Address 3.C872

Bit Name Description Type Default Note

F:0 XFI1 Good

Frame Counter

LSW [F:0]

XFI1 Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.431 PCS Transmit XFI1 Vendor State 1: Address 3.C870

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI1 Good

Frame Counter

MSW [9:0]

XFI1 Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.432 PCS Transmit XFI1 Vendor State 2: Address 3.C871

Bit Name Description Type Default Note

F:0 XFI1 Bad Frame

Counter LSW

[F:0]

XFI1 Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.433 PCS Transmit XFI1 Vendor State 3: Address 3.C872

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6.7.90 PCS Transmit XFI1 Vendor State 4: Address 3.C873

6.7.91 PCS Transmit XGS Vendor State 1: Address 3.C880

6.7.92 PCS Transmit XGS Vendor State 2: Address 3.C881

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI1 Bad Frame

Counter MSW

[9:0]

XFI1 Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.434 PCS Transmit XFI1 Vendor State 4: Address 3.C873

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XGS Collision

Events Counter

0 [7:0]

XGS collision events: Byte location from

1 to 64 bytes counter

SCT 0x00 1G/100M PHY collision events: Byte location

from 1 to 64 counter

Table 6.435 PCS Transmit XGS Vendor State 1: Address 3.C880

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XGS Collision

Events Counter

1 [7:0]

XGS collision events: Byte location from

65 to 96 bytes counter

SCT 0x00 1G/100M PHY collision events: Byte location

from 65 to 96 counter

Table 6.436 PCS Transmit XGS Vendor State 1: Address 3.C880

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6.7.93 PCS Transmit XGS Vendor State 3: Address 3.C882

6.7.94 PCS Transmit XGS Vendor State 4: Address 3.C883

6.7.95 PCS Transmit XGS Vendor State 5: Address 3.C884

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XGS Collision

Events Counter

2 [7:0]

XGS collision events: Byte location from

97 to 128 counter

SCT 0x00 1G/100M PHY collision events: Byte location

from 97 to 128 bytes counter

Table 6.437 PCS Transmit XGS Vendor State 3: Address 3.C882

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XGS Collision

Events Counter

3 [7:0]

XGS collision events: Byte location from

129 to 192 counter

SCT 0x00 1G/100M PHY collision events: Byte location

from 129 to 192 bytes counter

Table 6.438 PCS Transmit XGS Vendor State 4: Address 3.C883

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XGS Collision

Events Counter

4 [7:0]

XGS collision events: Byte location from

193 to 320 counter

SCT 0x00 1G/100M PHY collision events: Byte location

from 193 to 320 bytes counter

Table 6.439 PCS Transmit XGS Vendor State 5: Address 3.C884

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6.7.96 PCS USX0 Transmit Status : Address 3.C8C0

6.7.97 PCS USX1 Transmit Status : Address 3.C8D0

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 USX0 Tx Rsvd

Status[3:0]

USX0 Tx Reserved Status LH

7:6 Reserved Internal reserved - do not modify

5 USX0 Tx Idle

Insertion

USX0 Tx Idle Insertion LH Tx Link Idle insertion

4 USX0 Tx Idle

Deletion

USX0 Tx Idle Deletion LH Rx Link Idle deletion

3:0 USX0 Tx GMII to

XGMII

convertion

status[3:0]

USX0 GMII/MII to XGMII Conversion

Status

LH Bit 0: Detect FIFO empty during sending

packet

Bit 1: Inject Local_Fault to MAC

Bits 2-3: Reserved

Table 6.440 PCS USX0 Transmit Status : Address 3.C8C0

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 USX1 Tx Rsvd

Status[3:0]

USX1 Tx Reserved Status LH

7:6 Reserved Internal reserved - do not modify

5 USX1 Tx Idle

Insertion

USX1 Tx Idle Insertion LH

Table 6.441 PCS USX1 Transmit Status : Address 3.C8D0

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6.7.98 PCS Transmit Vendor System Interface State 1: Address 3.C8F0

6.7.99 PCS PTP Vendor State 1: Address 3.C900

4 USX1 Tx Idle

Deletion

USX1 Tx Idle Deletion LH

3:0 USX1 TX GMII

to XGMII

convertion

status[3:0]

USX1 GMII/MII to XGMII Conversion

Status

LH Bit 0: Detect FIFO empty during sending

packet

Bit 1: Inject Local_Fault to MAC

Bits 2-3: Reserved

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 System Interface

Transmit Fault

1 = Fault condition on transmit path

0 = No fault condition on transmit path

RO See "PCS Standard Status 1: Address 3.1"

Table 6.442 PCS USX1 Transmit Status : Address 3.C8D0

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Seconds

Count Bits 15:0

[F:0]

PTP digital clock seconds count bits

15:0

RO Digital clock seconds counter current value

Table 6.443 PCS PTP Vendor State 1: Address 3.C900

Bit Name Description Type Default Note

Table 6.441 PCS USX1 Transmit Status : Address 3.C8D0

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6.7.100 PCS PTP Vendor State 2: Address 3.C901

6.7.101 PCS PTP Vendor State 3: Address 3.C902

6.7.102 PCS PTP Vendor State 4: Address 3.C903

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Seconds

Count Bits 31:16

[1F:10]

PTP digital clock seconds count bits

31:16

RO Digital clock seconds counter current value

Table 6.444 PCS PTP Vendor State 2: Address 3.C901

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Seconds

Count Bits 47:32

[2F:20]

PTP digital clock seconds count bits

47:32 RO Digital clock seconds counter current value

Table 6.445 PCS PTP Vendor State 3: Address 3.C902

Bit Name Description Type Default Note

F:0 PTP Digital

Clock

Nanoseconds

Count LSW [F:0]

PTP digital clock nanoseconds count

bits 15:0

RO Digital clock nano-seconds counter current

value

Table 6.446 PCS PTP Vendor State 4: Address 3.C903

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6.7.103 PCS PTP Vendor State 5: Address 3.C904

6.7.104 PCS PTP Vendor State 6: Address 3.C905

6.7.105 PCS PTP Vendor State 7: Address 3.C906

Bit Name Description Type Default Note

F:0 PTP Digital

Clock

Nanoseconds

Count MSW

[1F:10]

PTP digital clock nanoseconds count

bits 31:16

RO Digital clock nano-seconds counter current

value

Table 6.447 PCS PTP Vendor State 5: Address 3.C904

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Fractional

Nanoseconds

Count LSW [F:0]

PTP digital clock fractional

nanoseconds count bits 15:0

RO Digital clock fractional nano-seconds counter

current value

Table 6.448 PCS PTP Vendor State 6: Address 3.C905

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Fractional

Nanoseconds

Count MSW

[1F:10]

PTP digital clock fractional

nanoseconds count bits 31:16

RO Digital clock fractional nano-seconds counter

current value

Table 6.449 PCS PTP Vendor State 7: Address 3.C906

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6.7.106 PCS PTP Vendor State 8: Address 3.C907

6.7.107 PCS PTP Vendor State 9: Address 3.C908

6.7.108 PCS PTP Vendor State 10: Address 3.C909

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Fractional

Seconds Count

LSW [F:0]

PTP digital clock fractional seconds

count bits 15:0

RO Digital clock fractional seconds counter current

value

Table 6.450 PCS PTP Vendor State 8: Address 3.C907

Bit Name Description Type Default Note

F:0 PTP Digital

Clock Fractional

Seconds Count

MSW [1F:10]

PTP digital clock fractional seconds

count bits 31:16

RO Digital clock fractional seconds counter current

value

Table 6.451 PCS PTP Vendor State 9: Address 3.C908

Bit Name Description Type Default Note

F:0 PTP External

Clock Count

LSW [F:0]

PTP external clock count bits 15:0 RO External clock counter value

Table 6.452 PCS PTP Vendor State 10: Address 3.C909

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6.7.109 PCS PTP Vendor State 11: Address 3.C90A

6.7.110 PCS PTP Vendor State 12: Address 3.C90B

6.7.111 PCS PTP Vendor State 13: Address 3.C90C

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D:0 PTP External

Clock Count

MSW [1D:10]

PTP external clock count bits 29:16 RO External clock counter value

Table 6.453 PCS PTP Vendor State 11: Address 3.C90A

Bit Name Description Type Default Note

F:0 PTP External

Clock Seconds

Count Bits 15:0

[F:0]

PTP external clock seconds count bits

15:0

RO External clock seconds counter value

Table 6.454 PCS PTP Vendor State 12: Address 3.C90B

Bit Name Description Type Default Note

F:0 PTP External

Clock Seconds

Count Bits 31:16

[1F:10]

PTP external clock seconds count bits

31:16

RO External clock seconds counter value

Table 6.455 PCS PTP Vendor State 13: Address 3.C90C

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6.7.112 PCS PTP Vendor State 14: Address 3.C90D

6.7.113 PCS PTP Vendor State 15: Address 3.C90E

6.7.114 PCS PTP Vendor State 16: Address 3.C90F

Bit Name Description Type Default Note

F:0 PTP External

Clock Seconds

Count Bits 47:32

[2F:20]

PTP external clock seconds count bits

47:32

RO External clock seconds counter value

Table 6.456 PCS PTP Vendor State 14: Address 3.C90D

Bit Name Description Type Default Note

F:0 PTP External

Clock

Nanoseconds

Count LSW [F:0]

PTP external clock nanoseconds count

bits 15:0

RO External clock nanoseconds counter value

Table 6.457 PCS PTP Vendor State 15: Address 3.C90E

Bit Name Description Type Default Note

F:0 PTP External

Clock

Nanoseconds

Count MSW

[1F:10]

PTP external clock nanoseconds count

bits 31:16

RO External clock nanoseconds counter value

Table 6.458 PCS PTP Vendor State 16: Address 3.C90F

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6.7.115 PCS PTP Vendor State 17: Address 3.C910

6.7.116 PCS PTP Vendor State 18: Address 3.C911

6.7.117 PCS PTP Vendor State 19: Address 3.C912

Bit Name Description Type Default Note

F:0 PTP External

Clock Fractional

Nanoseconds

Count LSW [F:0]

PTP external clock fractional

nanoseconds count bits 15:0

RO External clock fractional nanoseconds counter

value

Table 6.459 PCS PTP Vendor State 17: Address 3.C910

Bit Name Description Type Default Note

F:0 PTP External

Clock Fractional

Nanoseconds

Count MSW

[1F:10]

PTP external clock fractional

nanoseconds count bits 31:16

RO External clock fractional nanoseconds counter

value

Table 6.460 PCS PTP Vendor State 18: Address 3.C911

Bit Name Description Type Default Note

F:0 PTP External

Clock Fractional

Seconds Count

LSW [F:0]

PTP external clock fractional seconds

count bits 15:0

RO External clock fractional seconds counter

value

Table 6.461 PCS PTP Vendor State 19: Address 3.C912

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6.7.118 PCS PTP Vendor State 20: Address 3.C913

6.7.119 PCS PTP Vendor State 21: Address 3.C914

6.7.120 PCS PTP Vendor State 22: Address 3.C915

Bit Name Description Type Default Note

F:0 PTP External

Clock Fractional

Seconds Count

MSW [1F:10]

PTP external clock fractional seconds

count bits 31:16

RO External clock fractional seconds counter

value

Table 6.462 PCS PTP Vendor State 20: Address 3.C913

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Seconds Count

LSW [F:0]

PTP external GPIO clock seconds count

bits 15:0

RO External GPIO seconds counter value

Table 6.463 PCS PTP Vendor State 21: Address 3.C914

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Seconds Count

MSW [1F:10]

PTP external GPIO clock seconds count

bits 31:16

RO External GPIO seconds counter value

Table 6.464 PCS PTP Vendor State 22: Address 3.C915

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6.7.121 PCS PTP Vendor State 23: Address 3.C916

6.7.122 PCS PTP Vendor State 24: Address 3.C917

6.7.123 PCS PTP Vendor State 25: Address 3.C918

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Nanoseconds

Count LSW [F:0]

PTP external GPIO clock nanosecods

count bits 15:0

RO External GPIO nanosecods counter value

Table 6.465 PCS PTP Vendor State 23: Address 3.C916

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Nanoseconds

Count MSW

[1F:10]

PTP external GPIO clock nanosecods

count bits 31:16

RO External GPIO nanosecods counter value

Table 6.466 PCS PTP Vendor State 24: Address 3.C917

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Fractional

Nanoseconds

Count LSW [F:0]

PTP external GPIO clock fractional

nanosecods count bits 15:0

RO External GPIO fractional nanosecods counter

value

Table 6.467 PCS PTP Vendor State 25: Address 3.C918

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6.7.124 PCS PTP Vendor State 26: Address 3.C919

6.7.125 PCS PTP Vendor State 27: Address 3.C91A

6.7.126 PCS PTP Vendor State 28: Address 3.C91B

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Fractional

Nanoseconds

Count MSW

[1F:10]

PTP external GPIO clock fractional

nanosecods count bits 31:16

RO External GPIO fractional nanosecods counter

value

Table 6.468 PCS PTP Vendor State 26: Address 3.C919

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Fractional

Seconds Count

LSW [F:0]

PTP external GPIO clock fractional

seconds count bits 15:0

RO External GPIO fractional seconds counter

value

Table 6.469 PCS PTP Vendor State 27: Address 3.C91A

Bit Name Description Type Default Note

F:0 PTP External

GPIO Clock

Fractional

Seconds Count

MSW [1F:10]

PTP external GPIO clock fractional

seconds count bits 31:16

RO External GPIO fractional seconds counter

value

Table 6.470 PCS PTP Vendor State 28: Address 3.C91B

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6.7.127 PCS PTP Vendor State 29: Address 3.C91C

6.7.128 PCS PTP Vendor State 30: Address 3.C91D

6.7.129 PCS PTP Vendor State 31: Address 3.C91E

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 PTP External

GPIO Clock

Update Done

PTP external GPIO clock update done BLH External GPIO fractional seconds counter

value

Table 6.471 PCS PTP Vendor State 29: Address 3.C91C

Bit Name Description Type Default Note

F:0 PTP USX0 Rx

Timestamp Bits

15:0 [F:0]

PTP USX0 Rx Timestamp bits 15:0 RO USX0 Rx timestamp current value

Table 6.472 PCS PTP Vendor State 30: Address 3.C91D

Bit Name Description Type Default Note

F:0 PTP USX0 Rx

Timestamp Bits

31:16 [1F:10]

PTP USX0 Rx Timestamp bits 31:16 RO USX0 Rx timestamp current value

Table 6.473 PCS PTP Vendor State 31: Address 3.C91E

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6.7.130 PCS PTP Vendor State 32: Address 3.C91F

6.7.131 PCS PTP Vendor State 33: Address 3.C920

6.7.132 PCS PTP Vendor State 34: Address 3.C921

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 PTP USX0 Rx

Timestamp Bits

34:32 [22:20]

PTP USX0 Rx Timestamp bits 34:32 RO USX0 Rx timestamp current value

Table 6.474 PCS PTP Vendor State 32: Address 3.C91F

Bit Name Description Type Default Note

F:0 PTP USX1 Rx

Timestamp Bits

15:0 [F:0]

PTP USX1 Rx Timestamp bits 15:0 RO USX1 Rx timestamp current value

Table 6.475 PCS PTP Vendor State 33: Address 3.C920

Bit Name Description Type Default Note

F:0 PTP USX1 Rx

Timestamp Bits

31:16 [1F:10]

PTP USX1 Rx Timestamp bits 31:16 RO USX1 Rx timestamp current value

Table 6.476 PCS PTP Vendor State 34: Address 3.C921

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6.7.133 PCS PTP Vendor State 35: Address 3.C922

6.7.134 PCS PTP Egress Vendor State 1: Address 3.C930

6.7.135 PCS PTP Egress Vendor State 2: Address 3.C931

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 PTP USX1 Rx

Timestamp Bits

34:32 [22:20]

PTP USX1 Rx Timestamp bits 34:32 RO USX1 Rx timestamp current value

Table 6.477 PCS PTP Vendor State 35: Address 3.C922

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 PTP Egress

Packet Count

[2:0]

PTP Egress packet count RO PTP packet count (0 to 4)

Table 6.478 PCS PTP Vendor State 30: Address 3.C91D

Bit Name Description Type Default Note

F:0 PTP Egress

Packet Data

LSW [F:0]

PTP Egress packet count RO PTP packet data

Table 6.479 PCS PTP Egress Vendor State 2: Address 3.C931

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6.7.136 PCS PTP Egress Vendor State 3: Address 3.C932

6.7.137 PCS PTP Egress Vendor State 4: Address 3.C933

Bit Name Description Type Default Note

F:0 PTP Egress

Packet Data

MSW [1F:10]

PTP Egress packet count RO PTP packet data

Table 6.480 PCS PTP Egress Vendor State 3: Address 3.C932

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 PTP Egress

Packet

Truncated

PTP Egress packet EOP RO Asserted when PTP packet has been

truncated because it is longer than 128 byte.

1 PTP Egress

Packet EOP

PTP Egress packet EOP RO Asserted when the PTP packet data returns

the last word of packet

0 PTP Egress

Packet SOP

PTP Egress packet SOP RO Asserted when the PTP packet data returns

the first word of packet

Table 6.481 PCS PTP Egress Vendor State 4: Address 3.C933

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6.7.138 PCS PTP Egress Vendor State 5: Address 3.C934

6.7.139 PCS PTP Egress Vendor State 6: Address 3.C935

6.7.140 PCS PTP Egress Vendor State 7: Address 3.C936

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 PTP Egress

Packet Time

Stamp Count

[2:0]

PTP Egress packet count RO PTP packet timestamp count (0 to 4)

Table 6.482 PCS PTP Egress Vendor State 5: Address 3.C934

Bit Name Description Type Default Note

F:0 PTP Egress

Packet Time

Stamp [F:0]

PTP Egress packet count RO PTP packet timestamp

Report arrival timestamp in 8 consecutive

reads for every packet (MSB first):

48-bit sec, 32-bit nano-sec, 16-bit fractional

nano-sec, 32-bit fractional sec

Table 6.483 PCS PTP Egress Vendor State 6: Address 3.C935

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

Table 6.484 PCS PTP Egress Vendor State 7: Address 3.C936

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6.7.141 PCS Transmit Vendor Alarms 1: Address 3.CC00

7PTP Egress Gap

FIFO Error

PTP Egress Gap FIFO error RO Read Egress Gap FIFO error for debug

6:0 PTP Egress Rx

Packet

Information [6:0]

PTP Egress packet count RO Received PTP packet information

Report diagnostic information about the type of

PTP packet being received.

Bits[1:0]: 0=L2, 1=IPv4, 2=IPv6, 3=reserved

Bits[3:2]: 0=1588v1, 1=1588v2, 2=NTP/SNTP,

3=reserved

For IEEE 1588:

Bits[6:4]: 0=Sync, 1=Delay_Req, 2=General,

3=PDelay_Req, 4=Pdelay_Resp,

5=User-defined, 6 to 7=reserved

For NTP/SNTP:

Bits [6:4]: 0=Non-control, 1=Control & Private,

2 to 7=reserved

Bit Name Description Type Default Note

F:1 Reserved PCS

Transmit Vendor

Alarms 1 [F:1]

Reserved for future use LH

0 XAUI Transmit Invalid

64B Block Detected

1 = Bad 64B block detected LH

Table 6.485 PCS Transmit Vendor Alarms 1: Address 3.CC00

Bit Name Description Type Default Note

Table 6.484 PCS PTP Egress Vendor State 7: Address 3.C936

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6.7.142 PCS Transmit Vendor Alarms 2: Address 3.CC01

6.7.143 PCS Transmit Vendor Alarms 3: Address 3.CC02

6.7.144 PCS Transmit Vendor Alarms 4: Address 3.CC03

Bit Name Description Type Default Note

F:0 Reserved PCS Transmit

Vendor Alarms 2 [F:0]

Reserved for future use LH

Table 6.486 PCS Transmit Vendor Alarms 2: Address 3.CC01

Table 6.487 PCS Transmit Vendor Alarms 3: Address 3.CC02

Bit Name Description Type Default Note

F:0 Reserved PCS

Transmit Vendor

Alarms 3 [F:0]

Reserved for future use LH

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D XFI1 Transmit Invalid

XGMII Character

Received

1 = Invalid XGMII Character

Received

C XFI1 Transmit

Reserved XGMII

Character Received

1 = Reserved XGMII Character

Received

B XFI1 Transmit 64B

Encode Error

1 = 64B Encode Error LH

Table 6.488 PCS Transmit Vendor Alarms 4: Address 3.CC03

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6.7.145 PCS Standard Interrupt Mask 1: Address 3.D000

A:9 Reserved Internal reserved - do not modify

8 XFI1 Transmit LOF

Detected

1 = Loss of Frame detected LH

7:6 Reserved Internal reserved - do not modify

5 XFI0 Transmit Invalid

XGMII Character

Received

1 = Invalid XGMII Character

Received

4 XFI0 Transmit

Reserved XGMII

Character Received

1 = Reserved XGMII Character

Received

3 XFI0 Transmit 64B

Encode Error

1 = 64B Encode Error LH

2:1 Reserved Internal reserved - do not modify

0 XFI0 Transmit LOF

Detected

1 = Loss of frame detected LH

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Tx LPI Received

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 3.1.B.

A Rx LPI Received

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 3.1.A.

Table 6.489 PCS Standard Interrupt Mask 1: Address 3.D000

Bit Name Description Type Default Note

Table 6.488 PCS Transmit Vendor Alarms 4: Address 3.CC03

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6.7.146 PCS Standard Interrupt Mask 2: Address 3.D001

9:3 Reserved Internal reserved - do not modify

2 PCS Receive Link

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 3.1.2. Note this bit also shows up

as Bit 3.20.C, but only as a status bit.

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Transmit Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 3.8.B

A Receive Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 3.8.A

9:0 Reserved Internal reserved - do not modify

Table 6.490 PCS Standard Interrupt Mask 2: Address 3.D001

Bit Name Description Type Default Note

Table 6.489 PCS Standard Interrupt Mask 1: Address 3.D000

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6.7.147 PCS Standard Interrupt Mask 3: Address 3.D002

6.7.148 PCS Transmit Vendor Interrupt Mask 1: Address 3.D400

Bit Name Description Type Default Note

F 10GBASE-T

PCS Block Lock

Latched Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 When set, this bit indicates that 10GBASE-T

PCS Framer has acquired frame

synchronization and is locked. This is the

interrupt for bit 3.21.F

E 10GBASE-T

High BER

Latched Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 When set, this bit indicates a high BER is being

seen at the PCS. This is the interrupt for bit

3.21.E

D:0 Reserved Internal reserved - do not modify

Table 6.491 PCS Standard Interrupt Mask 3: Address 3.D002

Bit Name Description Type Default Note

F:1 Reserved PCS

Transmit Vendor

Alarms 1 Mask

[F:1]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0000

0 XAUI Transmit

Invalid 64B

Block Detected

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.492 PCS Transmit Vendor Interrupt Mask 1: Address 3.D400

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6.7.149 PCS Transmit Vendor Interrupt Mask 2: Address 3.D401

6.7.150 PCS Transmit Vendor Interrupt Mask 3: Address 3.D402

6.7.151 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403

Bit Name Description Type Default Note

F:0 Reserved PCS Transmit

Vendor Alarms 2 Mask

[F:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0000

Table 6.493 PCS Transmit Vendor Interrupt Mask 2: Address 3.D401

Bit Name Description Type Default Note

F:0 Reserved PCS

Transmit Vendor

Alarms 3 Mask

[F:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x000

Table 6.494 PCS Transmit Vendor Interrupt Mask 3: Address 3.D402

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D XFI1 Transmit

Invalid XGMII

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C XFI1 Transmit

Reserved XGMII

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.495 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403

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6.7.152 PCS Transmit Vendor Debug 1: Address 3.D800

B XFI1 Transmit

Encode 64B

Error Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A:6 Reserved Internal reserved - do not modify

5 XFI0 Transmit

Invalid XGMII

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

4 XFI0 Transmit

Reserved XGMII

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 XFI0 Transmit

Encode 64B

Error Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

FPCS Tx

Scrambler

Disable

1 = Tx Scrambler Disabled

0 = Normal Operation

R/W

0 Setting this bit disables the Tx scrambler

during regular data transmission (i.e.

scrambler functionality during training and

startup is unmodified).

E PCS Tx Inject

CRC Error

1 = Inject CRC Error R/W 0 Setting this bit injects a CRC error in a single

frame.

Table 6.496 PCS Transmit Vendor Debug 1: Address 3.D800

Bit Name Description Type Default Note

Table 6.495 PCS Transmit Vendor Interrupt Mask 4: Address 3.D403

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6.7.153 PCS Receive Vendor Provisioning 1: Address 3.E400

6.7.154 PCS Receive XFI0 Provisioning 1: Address 3.E460

D PCS Tx Inject

Frame Error

1 = Inject frame error R/W 0 Setting this bit injects an error at the location

contained in Bits C:0 in the next PCS

transmission frame.

C:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 PCS Rx Error

LDPC Frame

Enable

1 = Enable erroring the LDPC frame

payload

0 = Disable erroring the LDPC frame

payload

R/W

1 Error the entire LDPC frame payload upon

uncorrectable LDPC parity or CRC error.

Table 6.497 PCS Receive Vendor Provisioning 1: Address 3.E400

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1XFI0 Rx

Descrambler

Disable

1 = XFI0 Disable PCS scrambler R/W 0 PCS Descrambler Disable

0 Reserved Internal reserved - do not modify

Table 6.498 PCS Receive XFI0 Provisioning 1: Address 3.E460

Bit Name Description Type Default Note

Table 6.496 PCS Transmit Vendor Debug 1: Address 3.D800

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6.7.155 PCS Receive XFI0 Provisioning 2: Address 3.E461

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 XFI0 Test Data

Source

XFI0 Data pattern select

1 = All-zero input for pseudo-random

test

1 = Local-fault (LF) input for

pseudo-random test

R/W 0 This bit determines the source of the data for

the pseudo-random test (selected by Bit 7).

7:5 XFI0 Test Mode

Select [2:0]

Test Pattern Select:

xx1 = PRBS-31

x10 = PRBS-9

100 = Square-wave

000 = Pseudo-random

R/W 0x0 Note that the source for the pseudo-random

test is determined by Bit 8.

4 XFI0 Test

Pattern Enable

1 = XFI0 Enable test pattern R/W 0 10GBASE-R Pseudo-Random Test Pattern

Enable - see the external view for an

explanation

3 XFI0 Local Fault

Inject

1 = XFI0 Inject local fault R/W 0 Inject Local_Fault

2:0 Reserved Internal reserved - do not modify

Table 6.499 PCS Receive XFI0 Provisioning 2: Address 3.E461

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6.7.156 PCS Receive XFI1 Provisioning 1: Address 3.E470

6.7.157 PCS Receive XFI1 Provisioning 2: Address 3.E471

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1XFI1 Rx

Descrambler

Disable

1 = XFI1 Disable PCS scrambler R/W 0 PCS Descrambler Disable

0 Reserved Internal reserved - do not modify

Table 6.500 PCS Receive XFI1 Provisioning 1: Address 3.E470

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 XFI1 Test Data

Source

XFI1 Data pattern select

1 = All-zero input for pseudo-random

test

1 = Local-fault (LF) input for

pseudo-random test

R/W 0 This bit determines the source of the data for

the pseudo-random test (selected by Bit 7).

7:5 XFI0 Test Mode

Select [2:0]

Test Pattern Select:

xx1 = PRBS-31

x10 = PRBS-9

100 = Square-wave

000 = Pseudo-random

R/W 0x0 Note that the source for the pseudo-random

test is determined by Bit 8.

4 XFI1 Test

Pattern Enable

1 = XFI1 Test pattern enabled R/W 0 10GBASE-R Pseudo-Random Test Pattern

Enable - see the external view for an

explanation

Table 6.501 PCS Receive XFI1 Provisioning 2: Address 3.E471

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6.7.158 PCS USX0 RX Control Register: Address 3.E4D0

3 XFI1 Local Fault

Inject

1 = XFI1 Inject local fault R/W 0 Inject Local_Fault

2:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:C USX0 Rx Rsvd

Control[3:0]

USX0 Receive Reserved Control R/W 0x0

B:A Reserved Internal reserved - do not modify

9 USX0 Header

CRC Chk

USX0 Header CRC Check Enable R/W 0

8 USX0 RX PKT

Info Extension

Field

Set to 1 to include the Extension Field

for the detection of the change

notification, otherwise the Extension

Field is ignored.

R/W 0

7:6 USX0 RX Local

Fault Mode[1:0]

Rx USXGMII Local_Fault mode:

0=Pass-through

1=Replaced with Idle

2=Replaced with user-defined code

3=Reserved

R/W 0x0

Table 6.502 PCS USX0 RX Control Register: Address 3.E4D0

Bit Name Description Type Default Note

Table 6.501 PCS Receive XFI1 Provisioning 2: Address 3.E471

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6.7.159 PCS USX0 RX FIFO Control Register: Address 3.E4D1

5:4 USX0 RX IFG

mode[1:0]

Rx Inter-Frame Gap Mode [1:0]

Minimum IFG assured on traffic sent to

GMII/MII (0:12-byte, 1 to 2: reserved,

3:none, default:0)

R/W 0x0

3:0 USX0 RX XGMII

to GMII

conversion

control[3:0]

XGMII to GMII/MII Conversion Control

Bits 0-3: Reserved

R/W 0x0

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 USX0 RX FIFO

Reset

MAC Rx FIFO reset R/W 0

7:4 USX0 RX FIFO

Threshold[3:0]

MAC Rx FIFO threshold

This is used to establish minimum FIFO

depth before starting to read.

R/W 0x1

3:0 USX0 RX FIFO

IFG

Threshold[3:0]

MAC Rx FIFO IFG threshold (default:8)

This is used to delete Idle when FIFO

depth is beyond this threshold.

R/W 0x8

Table 6.503 PCS USX0 RX FIFO Control Register: Address 3.E4D1

Bit Name Description Type Default Note

Table 6.502 PCS USX0 RX Control Register: Address 3.E4D0

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6.7.160 PCS USX0 SM Control Register: Address 3.E4D2

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

BUSX0 SM

Freeze

SAN State Machine Freeze R/W 0

A USX0 SM Force SAN State Machine Force R/W 0

9USX0 SM

Redirect

SAN State Machine Redirect R/W 0

8:6 USX0 SM

Current State

Match[2:0]

SAN State Machine Current State Match R/W 0x0

5:3 USX0 SM Next

state Match[2:0]

SAN State Machine Next State Match R/W 0x0

2:0 USX0 SM

Redirect

state[2:0]

SAN State Machine redirect State. R/W 0x0

Table 6.504 PCS USX0 SM Control Register: Address 3.E4D2

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6.7.161 PCS USX0 Link Timer Control Register: Address 3.E4D3

6.7.162 PCS USX0 RX Fault Control Register: Address 3.E4D4

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B USX0 Link Timer

Reset

Link_timer Reset (0=Normal, 1=Reset to

R/W 0

A USX0 Link Timer

Freeze

Link_timer Freeze (0=Normal,

1=Frozen)

R/W 0

9:0 USX0 Link Timer

Threshold[9:0]

Link timer threshold (in terms of 12.8us,

default=125 for 1.6ms)

R/W 0x07D

Table 6.505 PCS USX0 Link Timer Control Register: Address 3.E4D3

Bit Name Description Type Default Note

F:8 USX0 RX Fault

Mask[7:0]

Set to 1 to compare the corresponding

bit(s) against the Fault data pattern,

otherwise the corresponding bit(s) are

ignored.

R/W 0xFF

7:0 USX0 RX Fault

Data[7:0]

Data pattern with the corresponding

mask to compare against the receive

data for the detection of Fault signal.

R/W 0x11

Table 6.506 PCS USX0 RX Fault Control Register: Address 3.E4D4

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6.7.163 PCS USX1 RX Control Register: Address 3.E4E0

Bit Name Description Type Default Note

F:C USX1 Rx Rsvd

Control[3:0]

USX0 Receive Reserved Control R/W 0x0

B:A Reserved Internal reserved - do not modify

9 USX1 Header

CRC Chk

USX1 Header CRC Check Enable R/W 0

8 USX1 RX PKT

Info Extension

Field

Set to 1 to include the Extension Field

for the detection of the change

notification, otherwise the Extension

Field is ignored.

R/W 0

7:6 USX1 RX Local

Fault Mode[1:0]

Rx USXGMII Local_Fault mode:

0=Pass-through

1=Replaced with Idle

2=Replaced with user-defined code

3=Reserved

R/W 0x0

5:4 USX1 RX IFG

mode[1:0]

Rx Inter-Frame Gap Mode [1:0]

Minimum IFG assured on traffic sent to

GMII/MII (0:12-byte, 1 to 2: reserved,

3:none, default:0)

R/W 0x0

3:0 USX1 RX XGMII

to GMII

conversion

control[3:0]

XGMII to GMII/MII Conversion Control

Bits 0-3: Reserved

R/W 0x0

Table 6.507 PCS USX1 RX Control Register: Address 3.E4E0

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6.7.164 PCS USX1 RX FIFO Control Register: Address 3.E4E1

6.7.165 PCS USX1 SM Control Register: Address 3.E4E2

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 USX1 RX FIFO

Reset

MAC Rx FIFO reset R/W 0

7:4 USX1 RX FIFO

Threshold[3:0]

MAC Rx FIFO threshold

This is used to establish minimum FIFO

depth before starting to read.

R/W 0x1

3:0 USX1 RX FIFO

IFG

Threshold[3:0]

MAC Rx FIFO IFG threshold (default:8)

This is used to delete Idle when FIFO

depth is beyond this threshold.

R/W 0x8

Table 6.508 PCS USX1 RX FIFO Control Register: Address 3.E4E1

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

BUSX0 SM

Freeze

SAN State Machine Freeze R/W 0

A USX1 SM Force SAN State Machine Force R/W 0

9USX1 SM

Redirect

SAN State Machine Redirect R/W 0

Table 6.509 PCS USX1 SM Control Register: Address 3.E4E2

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6.7.166 PCS USX1 Link Timer Control Register: Address 3.E4E3

8:6 USX1 SM

Current State

Match[2:0]

SAN State Machine Current State Match R/W 0x0

5:3 USX1 SM Next

state Match[2:0]

SAN State Machine Next State Match R/W 0x0

2:0 USX1 SM

Redirect

state[2:0]

SAN State Machine redirect State. R/W 0x0

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B USX1 Link Timer

Reset

Link_timer Reset (0=Normal, 1=Reset to

R/W 0

A USX1 Link Timer

Freeze

Link_timer Freeze (0=Normal,

1=Frozen)

R/W 0

9:0 USX1 Link Timer

Threshold[9:0]

Link timer threshold (in terms of 12.8us,

default=125 for 1.6ms)

R/W 0x07D

Table 6.510 PCS USX1 Link Timer Control Register: Address 3.E4E3

Bit Name Description Type Default Note

Table 6.509 PCS USX1 SM Control Register: Address 3.E4E2

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6.7.167 PCS USX1 RX Fault Control Register: Address 3.E4E4

6.7.168 PCS PTP Ingress Vendor Provisioning 1: Address 3.E600

Bit Name Description Type Default Note

F:8 USX1 RX Fault

Mask[7:0]

Set to 1 to compare the corresponding

bit(s) against the Fault data pattern,

otherwise the corresponding bit(s) are

ignored.

R/W 0xFF

7:0 USX1 RX Fault

Data[7:0]

Data pattern with the corresponding

mask to compare against the receive

data for the detection of Fault signal.

R/W 0x11

Table 6.511 PCS USX1 RX Fault Control Register: Address 3.E4E4

Bit Name Description Type Default Note

F PTP Ingress

VLAN Tagging

Enable

1 = PTP Ingress VLAN tagging enabled R/W 0 Enable VLAN tagging for IEEE1588 or

NTP/SNTP packet (default:0x1)

E PTP Ingress

IPv6/UDP

Encapsulated

Enabled

1 = PTP Ingress IPv6/UDP

encapsulated enable

R/W 0 Enable IPv6/UDP encapsulated IEEE1588 or

NTP/SNTP packet (default: 0)

D PTP Ingress

IPv4/UDP

Encapsulated

Enabled

1 = PTP Ingress IPv4/UDP

encapsulated enable

R/W 0 Enable IPv4/UDP encapsulated IEEE1588 or

NTP/SNTP packet (default: 0)

Table 6.512 PCS USX1 RX Control Register: Address 3.E4E0

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C PTP Ingress

Ethernet

Encapsulated

Enable

1 = PTP Ingress ethernet encapsulated

enable

R/W 0 Enable Ethernet encapsulated IEEE1588

packet (default: 0)

B:A Reserved Internal reserved - do not modify

9:8 PTP Ingress

NTP

Configuration

[1:0]

PTP Ingress NTP/SNTP configuration R/W 0x0 NTP/SNTP configuration (bit 0: 0=client,

1=server, bit 1: 0=Ingress, 1=ingress)

7:6 Reserved Internal reserved - do not modify

5 PTP Ingress

Back Pressure

Enable

1 = PTP Ingress back pressure enable R/W 0 PTP FIFO ready enable (default: 0)

Set to 1 to enable the back pressure during the

appending of timestamp to the end of packet

Set to 0 to disable the back pressue.

4 PTP Ingress

NTP Enable

1 = PTP Ingress NTP/SNTP enable R/W 0 Enable NTP/SNTP

3:2 Reserved Internal reserved - do not modify

1 PTP Ingress

1588 Version 2

Enable

1 = PTP Ingress 1588 version 2 enable R/W 0 Enable IEEE 1588 Version 2

0 PTP Ingress

1588 Version 1

Enable

1 = PTP Ingress 1588 version 1 enable R/W 0 Enable IEEE 1588 Version 1

Bit Name Description Type Default Note

Table 6.512 PCS USX1 RX Control Register: Address 3.E4E0

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6.7.169 PCS PTP Ingress Vendor Provisioning 2: Address 3.E601

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:C PTP Ingress

IPv6 Destination

Address

Matching Enable

[2:0]

PTP Ingress IPv6 destination address

matching enable

R/W 0x3 Enable IPv6 destination address matching for

IEEE1588 (default:0x3)

bit 0: FF0X:0:0:0:0:0:0:181 (X: 0x0 to 0xF)

bit 1: FF02:0:0:0:0:0:0:6B

bit 2: user-defined

B:8 PTP Ingress

IPv4 Destination

Address

Matching Enable

[3:0]

PTP Ingress IPv4 destination address

matching enable

R/W 0x7 Enable IPv4 destination address matching for

IEEE1588 (default:0x7)

bit 0: 224.0.1.129

bit 1: 224.0.1.130-132

bit 2: 224.0.0.107

bit 3: user-defiined

7 Reserved Internal reserved - do not modify

6:4 PTP Ingress

MAC Destination

Address

Matching Enable

[2:0]

PTP Ingress MAC destination address

matching enable

R/W 0x3 Enable MAC destination address matching for

IEEE1588 (default:0x3)

bit 0: 01-1B-19-00-00-00

bit 1: 01-80-C2-00-00-0E

bit 2: user-defined

3:2 Reserved Internal reserved - do not modify

1:0 PTP Ingress

Ethertype

Matching Enable

[1:0]

PTP Ingress ethertype matching enable R/W 0x1 Enable Ethertype matching for Ethernet

encapsulated IEEE1588 packet (default:0x1)

bit 0: 0x88F7

bit 1: user-defined

This shall be configured before enable

Ethernet encapsulation. At least one bit needs

to be set.

Table 6.513 PCS PTP Ingress Vendor Provisioning 2: Address 3.E601

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6.7.170 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:C PTP Ingress

NTP/SNTP

Version [2:0]

PTP Ingress NTP/SNTP version R/W 0x3 Version of NTP/SNTP (default: 3)

It specifies the minimum value of version

number of NTP/SNTP to be supported. It shall

not be less than 3, but a value of 0 will disable

version checking.

B:8 PTP Ingress

1588 Version

[3:0]

PTP Ingress IEEE 1588 version R/W 0x2 Latest version of IEEE1588 (default: 2)

It allows support of future versions of the IEEE

1588. It shall not be less than 2, but a value of

0 will disable version checking and assume to

be compatible with version 2.

7:6 Reserved Internal reserved - do not modify

5 PTP Ingress

1588 2 Step

Enable

PTP Ingress 1588 2 step enable R/W 0 Set to 1 to consider the two-step flag for

IEEE1588v2 (or PTP_ASSIST for

IEEE1588v1). It will prevent timestamp

overwritten for 2-step Sync message. Set to 0

will allow timestamp update regardless of the

flag (default: 0)

4 PTP Ingress

1588 Version 2

Domain

Matching Enable

1 = PTP Ingress 1588 version 2 domain

matching enable

R/W 0 Enable domain matching for IEEE1588v2

(default: 0)

Table 6.514 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602

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6.7.171 PCS PTP Ingress Vendor Provisioning 4: Address 3.E603

6.7.172 PCS PTP Ingress Vendor Provisioning 5: Address 3.E604

3 Reserved Internal reserved - do not modify

2:0 PTP Ingress

UDP Destination

Port Matching

Enable [2:0]

PTP Ingress UDP destination port

matching enable

R/W 0x3 Enable UDP destination port matching for

IEEE 1588 or NTP/SNTP (default:0x3)

bit 0: 319 for IEEE1588, or 123 for NTP/SNTP

bit 1: 320 for IEEE1588, not used for

NTP/SNTP

bit 2: user-defined

Bit Name Description Type Default Note

F:0 PTP Ingress

Ethertype [F:0]

PTP Ingress UDP destination port

matching enable

R/W 0x0000 User-defined EtherType for Ethernet

encapsulated IEEE1588 packets (default: 0)

Table 6.515 PCS PTP Ingress Vendor Provisioning 4: Address 3.E603

Bit Name Description Type Default Note

F:0 PTP Ingress

MAC Destination

Address Bits

15:0 [F:0]

PTP Ingress MAC destination address

bits 15:0

R/W 0x0000 User-defined MAC destination address

(default: 0)

Table 6.516 PCS PTP Ingress Vendor Provisioning 5: Address 3.E604

Bit Name Description Type Default Note

Table 6.514 PCS PTP Ingress Vendor Provisioning 3: Address 3.E602

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6.7.173 PCS PTP Ingress Vendor Provisioning 6: Address 3.E605

6.7.174 PCS PTP Ingress Vendor Provisioning 7: Address 3.E606

6.7.175 PCS PTP Ingress Vendor Provisioning 8: Address 3.E607

Bit Name Description Type Default Note

F:0 PTP Ingress

MAC Destination

Address Bits

31:16 [1F:10]

PTP Ingress MAC destination address

bits 31:16

R/W 0x0000 User-defined MAC destination address

(default: 0)

Table 6.517 PCS PTP Ingress Vendor Provisioning 6: Address 3.E605

Bit Name Description Type Default Note

F:0 PTP Ingress

MAC Destination

Address Bits

47:32 [2F:20]

PTP Ingress MAC destination address

bits 47:32

R/W 0x0000 User-defined MAC destination address

(default: 0)

Table 6.518 PCS PTP Ingress Vendor Provisioning 7: Address 3.E606

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv4 Destination

Address LSW

[F:0]

PTP Ingress IPv4 destination address

bits 15:0

R/W 0x0000 User-defined IPv4 destination address

(default: 0)

Table 6.519 PCS PTP Ingress Vendor Provisioning 8: Address 3.E607

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6.7.176 PCS PTP Ingress Vendor Provisioning 9: Address 3.E608

6.7.177 PCS PTP Ingress Vendor Provisioning 10: Address 3.E609

6.7.178 PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv4 Destination

Address MSW

[1F:10]

PTP Ingress IPv4 destination address

bits 31:16

R/W 0x0000 User-defined IPv4 destination address

(default: 0)

Table 6.520 PCS PTP Ingress Vendor Provisioning 9: Address 3.E608

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

15:0 [F:0]

PTP Ingress IPv6 destination address

bits 15:0

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.521 PCS PTP Ingress Vendor Provisioning 10: Address 3.E609

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

31:16 [1F:10]

PTP Ingress IPv6 destination address

bits 31:16

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.522 PCS PTP Ingress Vendor Provisioning 11: Address 3.E60A

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6.7.179 PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B

6.7.180 PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C

6.7.181 PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

47:32 [2F:20]

PTP Ingress IPv6 destination address

bits 47:32

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.523 PCS PTP Ingress Vendor Provisioning 12: Address 3.E60B

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

63:48 [3F:30]

PTP Ingress IPv6 destination address

bits 63:48

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.524 PCS PTP Ingress Vendor Provisioning 13: Address 3.E60C

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

79:64 [4F:40]

PTP Ingress IPv6 destination address

bits 79:64

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.525 PCS PTP Ingress Vendor Provisioning 14: Address 3.E60D

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6.7.182 PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E

6.7.183 PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F

6.7.184 PCS PTP Ingress Vendor Provisioning 17: Address 3.E610

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

95:80 [5F:50]

PTP Ingress IPv6 destination address

bits 95:80

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.526 PCS PTP Ingress Vendor Provisioning 15: Address 3.E60E

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

111:96 [6F:60]

PTP Ingress IPv6 destination address

bits 111:96

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.527 PCS PTP Ingress Vendor Provisioning 16: Address 3.E60F

Bit Name Description Type Default Note

F:0 PTP Ingress

IPv6 Destination

Address Bits

127:112 [7F:70]

PTP Ingress IPv6 destination address

bits 127:112

R/W 0x0000 User-defined IPv6 destination address

(default: 0)

Table 6.528 PCS PTP Ingress Vendor Provisioning 17: Address 3.E610

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6.7.185 PCS PTP Ingress Vendor Provisioning 18: Address 3.E611

6.7.186 PCS PTP Ingress Vendor Provisioning 19: Address 3.E612

6.7.187 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613

Bit Name Description Type Default Note

F:0 PTP Ingress

UDP Destination

Port [F:0]

PTP Ingress UDP destination port R/W 0x0000 User-defined UDP destination port (default: 0)

Table 6.529 PCS PTP Ingress Vendor Provisioning 18: Address 3.E611

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 PTP Ingress

1588 Version 2

Domain [7:0]

PTP Ingress 1588 Version 2 Domain R/W 0x00 User-defined domain for IEEE1588v2

(default:0)

Table 6.530 PCS PTP Ingress Vendor Provisioning 19: Address 3.E612

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3 PTP Ingress

Correction

Offset Sign

1 = PTP Ingress correction offset sign R/W 0 Correction field offset sign (0: add, 1:subtract,

default: 0)

This indicates whether to add or subtract the

correction field offset.

Table 6.531 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613

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6.7.188 PCS PTP Ingress Vendor Provisioning 21: Address 3.E614

6.7.189 PCS PTP Ingress Vendor Provisioning 22: Address 3.E615

2 PTP Ingress

Time Stamp

Offset Sign

1 = PTP Ingress time stamp offset sign R/W 0 Timestamp nano-/fractional-seconds offset

sign (0: add, 1:subtract, default: 0)

This indicates whether to add or subtract the

timestamp compensation offset.

1 PTP Ingress Set

Time Stamp

Offset

1 = PTP Ingress set time stamp offset R/W 0 Toggle to set the new offsets of the timestamp

and correction field (default: 0)

0 PTP Ingress

Byte Swap

1 = PTP Ingress byte swap R/W 0 Swap byte order of the 32-bit packet data

(default:0)

Bit Name Description Type Default Note

F:0 PTP Ingress

Time Stamp

Nanosecond

Offset [F:0]

PTP Ingress time stamp nanosecond

offset

R/W 0x0000 Timestamp nanoseconds offset (default: 0)

This compensates the difference between MDI

and timestamping point.

Table 6.532 PCS PTP Ingress Vendor Provisioning 21: Address 3.E614

Bit Name Description Type Default Note

F:0 PTP Ingress

Time Stamp

Fractional

Second Offset

LSW [F:0]

PTP Ingress time stamp fractional

second offset

R/W 0x0000 Timestamp fractional-seconds offset (default:

This is the LSB 19-bit of the 32-bit fractional-

seconds counter. Software shall this value is

equivalent to the corresponding nanoseconds

offset.

Table 6.533 PCS PTP Ingress Vendor Provisioning 22: Address 3.E615

Bit Name Description Type Default Note

Table 6.531 PCS PTP Ingress Vendor Provisioning 20: Address 3.E613

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6.7.190 PCS PTP Ingress Vendor Provisioning 23: Address 3.E616

6.7.191 PCS PTP Ingress Vendor Provisioning 24: Address 3.E617

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 PTP Ingress

Time Stamp

Fractional

Second Offset

MSW [12:10]

PTP Ingress time stamp fractional

second offset

R/W 0x0 Timestamp fractional-seconds offset (default:

This is the LSB 19-bit of the 32-bit fractional-

seconds counter. Software shall this value is

equivalent to the corresponding nanoseconds

offset.

Table 6.534 PCS PTP Ingress Vendor Provisioning 23: Address 3.E616

Bit Name Description Type Default Note

F:0 PTP Ingress

Correction

Offset LSW [F:0]

PTP Ingress correction offset R/W 0x0000 Correction field offset (16-bit nano-second &

16-bit fractional nano-second, default: 0)

This compensates the asymmetrical Tx/Rx

delay, and/or any adjustment for transparent

application.

Table 6.535 PCS PTP Ingress Vendor Provisioning 24: Address 3.E617

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6.7.192 PCS PTP Ingress Vendor Provisioning 25: Address 3.E618

6.7.193 PCS PTP Ingress Vendor Provisioning 26: Address 3.E619

Bit Name Description Type Default Note

F:0 PTP Ingress

Correction

Offset MSW

[1F:10]

PTP Ingress correction offset R/W 0x0000 Correction field offset (16-bit nano-second &

16-bit fractional nano-second, default: 0)

This compensates the asymmetrical Tx/Rx

delay, and/or any adjustment for transparent

application.

Table 6.536 PCS PTP Ingress Vendor Provisioning 25: Address 3.E618

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:0 PTP Ingress

Packet Action

[B:0]

PTP Ingress packet action R/W 0x000 IEEE 1588v2 packet action(0=None,

1=Capture, 2=reserved, 3=Capture & forward,

default: 0)

Bits [1:0]: Sync message

Bits [3:2]: Delay_Req message

Bits [5:4]: Pdelay_Req message

Bits [7:6]: Pdelay_Resp message

Bits [9:8]: User-defined message

Bits [11:10]: General messages

Table 6.537 PCS PTP Ingress Vendor Provisioning 26: Address 3.E619

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6.7.194 PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A

6.7.195 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D:C PTP Ingress

NTP/SNTP Time

Stamp Action

[1:0]

PTP Ingress correct action R/W 0x0 NTP/SNTP timestamp action (0=None,

1=Overwrite, 2=Append, 3=reserved)

B:8 PTP Ingress

NTP/SNTP

Packet Action

[3:0]

PTP Ingress correct action R/W 0x0 NTP/SNTP packet action (0=None,

1=Capture, 2=reserved, 3=Capture & forward,

3=reserved)

Bits [1:0]: Non-control messages

Bits [3:2]: Control & Private-use messages

7:0 Reserved Internal reserved - do not modify

Table 6.538 PCS PTP Ingress Vendor Provisioning 27: Address 3.E61A

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5 PTP Ingress

Correction

Fractional

Nanosecond

Timestampe

Enable

1 = PTP Ingress CRC append enable R/W 0 Correction fractional-nanoseconds timestamp

enable (default: 0)

Set to 1 to allow the fractional-nanoseconds

count of the timestamp to be carried by the

LSB 16-bit of the original Correction field (See

pif_ptp_ing_correct_act_i=3). Set to 0 to

ignore the fractional-nanoseconds count

during update of the Correction field.

Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B

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4 PTP Ingress

Correction Clear

Timestamp

Enable

1 = PTP Ingress CRC append enable R/W 1 Correction clear timestamp enable (default: 1)

Set to 1 to allow the timestamp field to be

cleared to 0 by the corresponding Correction

field action (See pif_ptp_ing_correct_act_i).

Set to 0 to keep the timestamp field determined

by the corresponding timestamp action (See

pif_ptp_ing_ts_act_i)

3 PTP Ingress

CRC Append

Enable

1 = PTP Ingress CRC append enable R/W 0 Ethernet FCS appending enable (default: 0)

Set to 1 to append FCS into Ethernet frame.

Set to 0 to have no FCS at the end of frame.

2 PTP Ingress

UDP Append

Format

1 = PTP Ingress UDP append format R/W 0 UDP packet appending format (default: 0)

This applies only for IEEE 1588v1 or

NTP/SNTP packets. Set to 1 to replace the last

16-bit of appended timestamp (fractional

nanoseconds) with a 16-bit word to

compensate for the change of UDP checksum

due to the appended timestamp. This allows

timestamp removal of any packet length

without the need of disabling the UDP

checksum (setting to all-zeroes). See

ptp_pif_egr_pkt_remove_err_o for more

information. Set to 0 to append 96-bit

timestamp without UDP checksum

compensation.

There is no need for IEEE 1588v2 because the

packet length shall be supported without error,

and the 16-bit fractional nanoseconds are

used to update the Correction field.

Bit Name Description Type Default Note

Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B

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6.7.196 PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C

1 PTP Ingress

UDP Append

Enable

1 = PTP Ingress UDP append enable R/W 1 UDP packet appending enable (default: 1)Set

to1 to append timestamp/correction field (if

enabled by the corresponding action) into UDP

payload. Set to 0 to append those into L2

Ethernet payload

0 PTP Ingress

UDP Checksum

Enable

1 = PTP Ingress UDP checksum enable R/W 1 UDP checksum calculation enable (default: 1)

Set to 1 to recalculate the UDP checksum

Set to 0 to set the UDP checksum to all-zeroes

Bit Name Description Type Default Note

F PTP Ingress

Packet Pipeline

Reset

1 = PTP Ingress packet pipeline reset R/W 0 PTP packet pipeline reset (default:0)

Set to 1 to reset PTP packet pipeline

E PTP Ingress

Packet Ready

FIFO Reset

1 = PTP Ingress packet ready FIFO

reset

R/W 0 PTP packet ready FIFO reset (default:0)

Set to 1 to reset PTP packet ready FIFO

D:0 Reserved Internal reserved - do not modify

Table 6.540 PCS PTP Ingress Vendor Provisioning 29: Address 3.E61C

Bit Name Description Type Default Note

Table 6.539 PCS PTP Ingress Vendor Provisioning 28: Address 3.E61B

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6.7.197 PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D

6.7.198 PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:0 PTP Ingress

Packet Pipeline

Threshold [3:0]

1 = PTP Ingress UDP append enable R/W 0x5 PTP packet pipeline threshold (default: 0x5)

This is used in 1G or 100M mode to regulate

packet flow. This has no effect in 10G mode.

Table 6.541 PCS PTP Ingress Vendor Provisioning 30: Address 3.E61D

Bit Name Description Type Default Note

F PTP Ingress

Packet Buffer

Reset

1 = PTP Ingress packet buffer reset R/W 0 PTP packet buffer reset (default: 0)

Set to 1 to reset PTP packet extraction buffer

and timestamp

E:1 Reserved Internal reserved - do not modify

0 PTP Ingress

Packet Buffer

Read Enable

1 = PTP Ingress packet buffer read

enable

R/W 0 PTP packet buffer read (default: 0)

Toggle 0->1->0 to read the next packet data

out of extraction FIFO

Table 6.542 PCS PTP Ingress Vendor Provisioning 31: Address 3.E61E

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6.7.199 PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F

6.7.200 PCS PTP Ingress Vendor Provisioning 33: Address 3.E620

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 PTP Ingress

Packet Pause

PTP Ingress packet pause R/W 0 PTP packet & timestamp extraction pause

(default: 0)

Set to 1 to pause the extraction of packet and

timestamp into the corresponding buffers. Set

to 0 to resume the extraction.

0 PTP Ingress

Packet Size

Limit

PTP Ingress packet size limit R/W 0 PTP packet size limit (default: 0)

Set to 1 to limit PTP packet to 128-byte to

ensure packet buffer is enough to fit up to 4

packets

Table 6.543 PCS PTP Ingress Vendor Provisioning 32: Address 3.E61F

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 PTP Ingress

Packet Time

Stamp Read

Enable

1 = PTP Ingress packet time stamp

reset enable

R/W 0 PTP packet timestamp read (default: 0)

Toggle 0->1->0 to read the next word of

corresponding timestamp of the extracted

packet

Table 6.544 PCS PTP Ingress Vendor Provisioning 33: Address 3.E620

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6.7.201 PCS PTP Ingress Vendor Provisioning 34: Address 3.E621

6.7.202 PCS PTP Ingress Vendor Provisioning 35: Address 3.E622

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 PTP Ingress

1588 Version 1

Time Stamp

Action [3:0]

PTP ingress 1588 version 1 time stamp

action

R/W 0x0 IEEE 1588v1 timestamp action (0=None,

1=Overwrite, 2=Append, 3=Remove, default:

0).

Bits [1:0]: Sync messages

Bits [3:2]: All other event messages

7:6 Reserved Internal reserved - do not modify

5:0 PTP Ingress

1588 Version 1

Packet Action

[5:0]

PTP ingress 1588 version 1 packet

action

R/W 0x00 IEEE 1588v1 packet action (0=None,

1=Capture, 2=reserved, 3=Capture & forward,

default: 0).

Bits [1:0]: Sync message

Bits [3:2]: All other event messages

Bits [5:4]: General messages

Table 6.545 PCS PTP Ingress Vendor Provisioning 34: Address 3.E621

Bit Name Description Type Default Note

F:0 PTP Ingress

Stacked VLAN

ID [F:0]

User-defined Tag Protocol Identifier

(TPID) for stacked VLAN

R/W 0x88A8 User-defined Tag Protocol Identifier (TPID) for

stacked VLAN (default: 0x88A8 for 802.1ad).

For Q-in-Q, it can be 0x9100 or other

user-defined values. In addition, 0x8100 will

always be recognized as valid TPID.

Table 6.546 PCS PTP Ingress Vendor Provisioning 35: Address 3.E622

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6.7.203 PCS PTP Ingress Vendor Provisioning 36: Address 3.E623

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:0 PTP Ingress

Correction

Action [E:0]

PTP Ingress correct action R/W 0x0000 IEEE 1588v2 correction field action (default:0)

0: No change

1: Correction + TS - TS(Append) + Offset

2: Correction + Offset

3: TS - Timestamp + Offset

(Timestamp field will be set to 0 if enabled.

See pif_ptp_egr_correct_clr_ts_en_i)

4: Correction + TS + Offset

5: Correction - TS + Offset

6 to 7: Reserved

Bits [2:0]: Sync messages

Bits [5:3]: Delay_Req message

Bits [8:6]: Pdelay_Req message

Bits [11:9]: Pdelay_Resp message

Bits [14:12]: User-defined message

Table 6.547 PCS PTP Ingress Vendor Provisioning 36: Address 3.E623

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6.7.204 PCS PTP Ingress Vendor Provisioning 37: Address 3.E624

6.7.205 PCS PTP Ingress Vendor Provisioning 38: Address 3.E625

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 PTP Ingress

Time Stamp

Action [9:0]

PTP Ingress packet action R/W 0x000 IEEE 1588v2 timestamp action (0=None,

1=Overwrite, 2=Append, 3=Remove, default:

0).

Bits [1:0]: Sync messages

Bits [3:2]: Delay_Req message

Bits [5:4]: Pdelay_Req message

Bits [7:6]: Pdelay_Resp message

Bits [9:8]: User-defined message

Table 6.548 PCS PTP Ingress Vendor Provisioning 37: Address 3.E624

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:0 PTP Ingress

1588 Version 2

Message Type

[3:0]

PTP Ingress 1588 version 2 message

type

R/W 0xF IEEE 1588v2 User-defined Message Type

Bit pattern to compare against the

messageType field after applying the bit mask

(default:0xF)

Table 6.549 PCS PTP Ingress Vendor Provisioning 38: Address 3.E625

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6.7.206 PCS PTP Ingress Vendor Provisioning 39: Address 3.E626

6.7.207 PCS PTP Ingress Vendor Provisioning 40: Address 3.E627

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:0 PTP Ingress

1588 Version 2

Message Mask

[3:0]

PTP Ingress 1588 version 2 message

mask

R/W 0xF IEEE 1588v2 User-defined Message Mask

Bit mask to compare against the

messageType field (for each bit, 1=compare,

0=ignore, default: 0xF)

Table 6.550 PCS PTP Ingress Vendor Provisioning 39: Address 3.E626

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:0 PTP Ingress

Packet IFG

Threshold [3:0]

PTP Ingress packet IFG threshold R/W 0x0 PTP packet IFG threshold (default: 0x0)

This is used in 1G or 100M mode to insert extra

idle during IFG. This has no effect in 10G

mode.

Table 6.551 PCS PTP Ingress Vendor Provisioning 40: Address 3.E627

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6.7.208 PCS PTP Ingress Vendor Provisioning 41: Address 3.E628

Bit Name Description Type Default Note

F:8 PTP Ingress RX

MAC FIFO base

[7:0]

PTP Ingress RX MAC FIFO Base Value R/W 0x0a When = 0, the ingress Gap FIFO is bypassed.

7:6 PTP Ingress RX

MAC FIFO

Correction [1:0]

PTP Ingress RX MAC FIFO Correction

Amount

R/W 0x3 Compensates for the additional latency

incurred if the MAC RX FIFO fill beyond the

“base” (bits F:8) value. A value of 1

corresponds to 1ns, 2 -> 2n, 3 -> 3n, and 4 ->

4ns.

5 PTP Ingress RX

MAC FIFO

Correction

Enable

PTP Ingress RX MAC FIFO Correction

Enable

R/W 0 Enables the MAC RX FIFO latency

compensation

4 PTP Ingress

Gap FIFO

Bypass

PTP Ingress Gap FIFO bypass R/W 1 When = 0, the ingress Gap FIFO is bypassed.

3:0 PTP Ingress

Packet Ready

Threshold [3:0]

PTP Ingress packet ready threshold R/W 0x2 PTP packet Ready threshold (default: 0x2)

This is used in 1G or 100M mode to deassert

ready when the pipeline FIFO is almost full.

This has no effect in 10G mode.

Table 6.552 PCS PTP Ingress Vendor Provisioning 41: Address 3.E628

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6.7.209 PCS Receive Vendor State 1: Address 3.E800

6.7.210 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 PCS Rx Current

Value of

Auxilliary Bit

The current value of the PCS Rx

auxilliary bit

RO This value has a maskable interrupt

associated with it in 3.EC00.0.

Table 6.553 PCS Receive Vendor State 1: Address 3.E800

Bit Name Description Type Default Note

F:0 CRC-8 Error

Counter LSW

[F:0]

Lower 16 bits of CRC-8 error counter SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of CRC-8 errors (but without LDPC

frame parity error) has been detected on the

received LDPC frame.

Table 6.554 PCS Receive Vendor CRC-8 Error Counter 1: Address 3.E810

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6.7.211 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811

6.7.212 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:0 CRC-8 Error

Counter MSW

[15:10]

Upper 6 bits of CRC-8 error counter SCT

0x00 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of CRC-8

errors (but without LDPC frame parity error)

has been detected on the received LDPC

frame.

Table 6.555 PCS Receive Vendor CRC-8 Error Counter 2: Address 3.E811

Bit Name Description Type Default Note

F:0 10GBASE-T

Good Frame

Counter LSW

[F:0]

10GBASE-T Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.556 PCS Receive Vendor FCS No Error Frame Counter 1: Address 3.E812

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6.7.213 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813

6.7.214 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814

6.7.215 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 10GBASE-T

Good Frame

Counter MSW

[19:10]

10GBASE-T Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.557 PCS Receive Vendor FCS No Error Frame Counter 2: Address 3.E813

Bit Name Description Type Default Note

F:0 10GBASE-T

Error Frame

Counter LSW

[F:0]

10GBASE-T Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.558 PCS Receive Vendor FCS Error Frame Counter 1: Address 3.E814

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 10GBASE-T

Error Frame

Counter MSW

[19:10]

10GBASE-T Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.559 PCS Receive Vendor FCS Error Frame Counter 2: Address 3.E815

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6.7.216 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820

6.7.217 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821

Bit Name Description Type Default Note

F:0 Uncorrected

Frame Counter

LSW [F:0]

Lower 16 bits of LDPC uncorrected

frames which the decoder abandoned.

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of uncorrected frames.

Table 6.560 PCS Receive Vendor Uncorrected Frame Counter 1: Address 3.E820

Bit Name Description Type Default Note

F:0 Uncorrected

Frame Counter

MSW [1F:10]

Upper 16 bits of LDPC uncorrected

frames which the decoder abandoned

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of uncorrected

frames.

Table 6.561 PCS Receive Vendor Uncorrected Frame Counter 2: Address 3.E821

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6.7.218 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840

6.7.219 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841

Bit Name Description Type Default Note

F:0 Corrected

Frames 1

Iteration Counter

LSW [F:0]

Lower 16 bits of LDPC corrected frames

which converged in 1 iteration

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of corrected frames which converged

in 1 iteration.

Table 6.562 PCS Receive Vendor Corrected Frame 1 Iteration Counter 1: Address 3.E840

Bit Name Description Type Default Note

F:0 Corrected

Frames 1

Iteration Counter

MSW [1F:10]

Upper 16 bits of LDPC corrected frames

which converged in 1 iteration

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of corrected

frames which converged in 1 iteration.

Table 6.563 PCS Receive Vendor Corrected Frame 1 Iteration Counter 2: Address 3.E841

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6.7.220 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842

6.7.221 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843

Bit Name Description Type Default Note

F:0 Corrected

Frames 2

Iteration Counter

LSW [F:0]

Lower 16 bits of LDPC corrected frames

which converged in 2 iteration

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of corrected frames which converged

in 2 iteration.

Table 6.564 PCS Receive Vendor Corrected Frame 2 Iteration Counter 1: Address 3.E842

Bit Name Description Type Default Note

F:0 Corrected

Frames 2

Iteration Counter

MSW [1F:10]

Upper 16 bits of LDPC corrected frames

which converged in 2 iteration

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of corrected

frames which converged in 2 iteration.

Table 6.565 PCS Receive Vendor Corrected Frame 2 Iteration Counter 2: Address 3.E843

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6.7.222 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844

6.7.223 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845

Bit Name Description Type Default Note

F:0 Corrected

Frames 3

Iteration Counter

LSW [F:0]

Lower 16 bits of LDPC corrected frames

which converged in 3 iteration

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of corrected frames which converged

in 3 iteration.

Table 6.566 PCS Receive Vendor Corrected Frame 3 Iteration Counter 1: Address 3.E844

Bit Name Description Type Default Note

F:0 Corrected

Frames 3

Iteration Counter

MSW [1F:10]

Upper 16 bits of LDPC corrected frames

which converged in 3 iteration

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of corrected

frames which converged in 3 iteration.

Table 6.567 PCS Receive Vendor Corrected Frame 3 Iteration Counter 2: Address 3.E845

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6.7.224 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846

6.7.225 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847

Bit Name Description Type Default Note

F:0 Corrected

Frames 4

Iteration Counter

LSW [F:0]

Lower 16 bits of LDPC corrected frames

which converged in 4 iteration

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of corrected frames which converged

in 4 iteration.

Table 6.568 PCS Receive Vendor Corrected Frame 4 Iteration Counter 1: Address 3.E846

Bit Name Description Type Default Note

F:0 Corrected

Frames 4

Iteration Counter

MSW [1F:10]

Upper 16 bits of LDPC corrected frames

which converged in 4 iteration

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of corrected

frames which converged in 4 iteration.

Table 6.569 PCS Receive Vendor Corrected Frame 4 Iteration Counter 2: Address 3.E847

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6.7.226 PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848

6.7.227 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849

Bit Name Description Type Default Note

F:0 Corrected

Frames 5

Iteration Counter

LSW [F:0]

Lower 16 bits of LDPC corrected frames

which converged in 5 iteration

SCT

0x0000 When the LSW is read, the MSW will be copied

to a shadow register and then both the LSW

and MSW are cleared. The LSW of the counter

must be read first. The MSW of the counter

must be read immediately after the LSW is

read. A saturating counter that counts the

number of corrected frames which converged

in 5 iteration.

Table 6.570 PCS Receive Vendor Corrected Frame 5 Iteration Counter 1: Address 3.E848

Bit Name Description Type Default Note

F:0 Corrected

Frames 5

Iteration Counter

MSW [1F:10]

Upper 16 bits of LDPC corrected frames

which converged in 5 iteration

SCT

0x0000 The MSW of the counter must be read

immediately after the LSW of the counter is

read. The MSW is actually a shadow copy of

the MSW of the counter and is loaded after the

LSW of the counter is read. A saturating

counter that counts the number of corrected

frames which converged in 5 iteration.

Table 6.571 PCS Receive Vendor Corrected Frame 5 Iteration Counter 2: Address 3.E849

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6.7.228 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850

6.7.229 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851

6.7.230 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852

Bit Name Description Type Default Note

F:0 Corrected

Frames 6

Iteration Counter

[F:0]

LDPC corrected frames which

converged in 6 iteration

SCT 0x0000 Clear on read. A saturating counter that counts

the number of corrected frames which

converged in 6 iteration.

Table 6.572 PCS Receive Vendor Corrected Frame 6 Iteration Counter: Address 3.E850

Bit Name Description Type Default Note

F:0 Corrected

Frames 7

Iteration Counter

[F:0]

LDPC corrected frames which

converged in 7 iteration

SCT 0x0000 Clear on read. A saturating counter that counts

the number of corrected frames which

converged in 7 iteration.

Table 6.573 PCS Receive Vendor Corrected Frame 7 Iteration Counter: Address 3.E851

Bit Name Description Type Default Note

F:0 Corrected

Frames 8

Iteration Counter

[F:0]

LDPC corrected frames which

converged in 8 iteration

SCT 0x0000 Clear on read. A saturating counter that counts

the number of corrected frames which

converged in 8 iteration.

Table 6.574 PCS Receive Vendor Corrected Frame 8 Iteration Counter: Address 3.E852

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6.7.231 PCS Receive XFI0 Vendor State 1: Address 3.E860

6.7.232 PCS Receive XFI0 Vendor State 2: Address 3.E861

6.7.233 PCS Receive XFI0 Vendor State 3: Address 3.E862

Bit Name Description Type Default Note

F:0 XFI0 Good

Frame Counter

LSW [F:0]

XFI0 Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.575 PCS Receive XFI0 Vendor State 1: Address 3.E860

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI0 Good

Frame Counter

MSW [9:0]

XFI0 Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.576 PCS Receive XFI0 Vendor State 2: Address 3.E861

Bit Name Description Type Default Note

F:0 XFI0 Bad Frame

Counter LSW

[F:0]

XFI0 Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.577 PCS Receive XFI0 Vendor State 3: Address 3.E862

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6.7.234 PCS Receive XFI0 Vendor State 4: Address 3.E863

6.7.235 PCS Receive XFI0 Vendor State 5: Address 3.E864

6.7.236 PCS Receive XFI0 Vendor State 6: Address 3.E865

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI0 Bad Frame

Counter MSW

[9:0]

XFI0 Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.578 PCS Receive XFI0 Vendor State 4: Address 3.E863

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:0 XFI0 BER

Counter [5:0]

XFI0 BER counter SCT 0x00 10GBASE-R BER Counter[5:0] saturating

clear on read

Table 6.579 PCS Receive XFI0 Vendor State 5: Address 3.E864

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XFI0 Errored

Block Counter

[7:0]

XFI0 errored block counter SCT 0x00 10GBASE-R Errored Block Counter[7:0]

saturating clear on read

Table 6.580 PCS Receive XFI0 Vendor State 6: Address 3.E865

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6.7.237 PCS Receive XFI0 Vendor State 7: Address 3.E866

6.7.238 PCS Receive XFI1 Vendor State 1: Address 3.E870

6.7.239 PCS Receive XFI1 Vendor State 2: Address 3.E871

Bit Name Description Type Default Note

F:0 XFI0 Test

Pattern Error

Counter [F:0]

XFI0 test pattern error counter SCT 0x0000 10GBASE-R Test Pattern Error Counter[15:0]

saturating clear on read

Table 6.581 PCS Receive XFI0 Vendor State 7: Address 3.E866

Bit Name Description Type Default Note

F:0 XFI1 Good

Frame Counter

LSW [F:0]

XFI1 Good Frame Counter LSW SCT

0x0000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.582 PCS Receive XFI1 Vendor State 1: Address 3.E870

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI1 Good

Frame Counter

MSW [9:0]

XFI1 Good Frame Counter MSW SCT

0x000 This counts Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.583 PCS Receive XFI1 Vendor State 2: Address 3.E871

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6.7.240 PCS Receive XFI1 Vendor State 3: Address 3.E872

6.7.241 PCS Receive XFI1 Vendor State 4: Address 3.E873

6.7.242 PCS Receive XFI1 Vendor State 5: Address 3.E874

Bit Name Description Type Default Note

F:0 XFI1 Bad Frame

Counter LSW

[F:0]

XFI1 Bad Frame Counter LSW SCT

0x0000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.584 PCS Receive XFI1 Vendor State 3: Address 3.E872

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 XFI1 Bad Frame

Counter MSW

[9:0]

XFI1 Bad Frame Counter MSW SCT

0x000 This counts Ethernet bad frames (i.e. Ethernet

CRC-32 / FCS errors).

Table 6.585 PCS Receive XFI1 Vendor State 4: Address 3.E873

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:0 XFI1 BER

Counter [5:0]

XFI1 BER counter SCT 0x00 10GBASE-R BER Counter[5:0] saturating

clear on read

Table 6.586 PCS Receive XFI1 Vendor State 5: Address 3.E874

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6.7.243 PCS Receive XFI1 Vendor State 6: Address 3.E875

6.7.244 PCS Receive XFI1 Vendor State 7: Address 3.E876

6.7.245 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 XFI1 Errored

Block Counter

[7:0]

XFI1 errored block counter SCT 0x00 10GBASE-R Errored Block Counter[7:0]

saturating clear on read

Table 6.587 PCS Receive XFI1 Vendor State 6: Address 3.E875

Bit Name Description Type Default Note

F:0 XFI1 Test

Pattern Error

Counter [F:0]

XFI1 test pattern error counter SCT 0x0000 10GBASE-R Test Pattern Error Counter[15:0]

saturating clear on read

Table 6.588 PCS Receive XFI1 Vendor State 7: Address 3.E876

Bit Name Description Type Default Note

F:0 USX0 Header

CRC Error

Counter [F:0]

Rx Header CRC error counter SCT 0x0000 This register is a 16-bit saturating clear on read

counter for USXGMII Header CRC error

Table 6.589 PCS USX0 Receive CRC Error Counter Register: Address 3.E8D0

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6.7.246 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1

6.7.247 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2

6.7.248 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3

Bit Name Description Type Default Note

F:0 USX0 Packet

Information

Message to be

injected 15:0

[F:0]

Packet Information Message to be

injected15:0

RO Rx Packet Information message bit’s 15:0

Table 6.590 PCS USX0 Receive Packet Info Message-0: Address 3.E8D1

Bit Name Description Type Default Note

F:0 USX0 Packet

Information

Message to be

injected 31:16

[1F:10]

Packet Information Message to be

injected 31:16

RO Rx Packet Information message bit’s 31:16

Table 6.591 PCS USX0 Receive Packet Info Message-1: Address 3.E8D2

Bit Name Description Type Default Note

F:0 USX0 Packet

Information

Message to be

injected 47:32

[2F:20]

Packet Information Message to be

injected 47:32

RO Rx Packet Information message bit’s 47:32

Table 6.592 PCS USX0 Receive Packet Info Message-2: Address 3.E8D3

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6.7.249 PCS USX0 Unidata and SM status Register: Address 3.E8D4

6.7.250 PCS USX0 Receive Status Register: Address 3.E8D5

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:4 USX0

Rx_Unidata

Indication[1:0]

Rx_Unidata Indication

(0=None, 1=Invalid,

2=Idle, 3=Config)

3 Reserved Internal reserved - do not modify

2:0 USX0 SAN

State Machine

current state[2:0]

SAN State Machine current state RO

Table 6.593 PCS USX0 Unidata and SM status Register: Address 3.E8D4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:4 USX0 Rx Rsvd

Status[3:0]

USX0 Rx Reserved Status BLH

3:0 USX0 XGMII to

GMII conversion

Status[3:0]

XGMII to GMII/MII Conversion Status

Bit 0: Detect Rx min IFG error

Bit 1: Detect Rx Signal Ordered_set

Bits 2-3: Reserved

BLH

Table 6.594 PCS USX0 Receive Status Register: Address 3.E8D5

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6.7.251 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6

Bit Name Description Type Default Note

F USX0 Link

Partner

Status

USX0 Link Partner advertisement

status.

0 = Link down

1 = Link up

E:D Reserved USX0

Link Partner

Advertisement 0

[1:0]

Reserved for future use. RO

C USX0 Link

Partner

Duplex

USX0 Link Partner advertisement

duplex.

0 = Half duplex

1 = Full duplex

B:9 USX0 Link

Partner

Speed [2:0]

USX0 Link Partner advertisement

speed.

0 = 10M

1 = 100M

2 = 1G

3 = 10G

4 = 2.5G

5 = 5G

8 USX0 Link

Partner

EEE Capability

USX0 Link Partner advertisement EEE

capability.

0 = Not supported

1 = Supported

Table 6.595 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6

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6.7.252 PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0

7 USX0 Link

Partner

EEE Clock Stop

Capability

USX0 Link Partner advertisement EEE

Clock Stop capability.

0 = Not supported

1 = Supported

6:1 Reserved USX0

Link Partner

Advertisement 1

[5:0]

Reserved for future use. RO

0 USX0 Link

Partner

Mode

USX0 Link Partner advertisement mode.

0 = SGMII

1 = USXGMII

Bit Name Description Type Default Note

F:0 USX1 Header

CRC Error

Counter [F:0]

Rx Header CRC error counter SCT 0x0000 This register is a 16-bit saturating clear on read

counter for USXGMII Header CRC error

Table 6.596 PCS USX1 Receive CRC Error Counter Register: Address 3.E8E0

Bit Name Description Type Default Note

Table 6.595 PCS USX0 Link Partner Adv Register<PCS USX0 Link Parter Adv Register>: Address 3.E8D6

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6.7.253 PCS USX1 Receive Packet Info Message-0: Address 3.E8E1

6.7.254 PCS USX1 Receive Packet Info Message-1: Address 3.E8E2

6.7.255 PCS USX1 Receive Packet Info Message-2: Address 3.E8E3

Bit Name Description Type Default Note

F:0 USX1 Packet

Information

Message to be

injected 15:0

[F:0]

Packet Information Message to be

injected15:0

RO Rx Packet Information message bit’s 15:0

Table 6.597 PCS USX1 Receive Packet Info Message-0: Address 3.E8E1

Bit Name Description Type Default Note

F:0 USX1 Packet

Information

Message to be

injected 31:16

[1F:10]

Packet Information Message to be

injected 31:16

RO Rx Packet Information message bit’s 31:16

Table 6.598 PCS USX1 Receive Packet Info Message-1: Address 3.E8E2

Bit Name Description Type Default Note

F:0 USX1 Packet

Information

Message to be

injected 47:32

[2F:20]

Packet Information Message to be

injected 47:32

RO Rx Packet Information message bit’s 47:32

Table 6.599 PCS USX1 Receive Packet Info Message-2: Address 3.E8E3

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6.7.256 PCS USX1 Unidata and SM status Register: Address 3.E8E4

6.7.257 PCS USX1 Receive Status Register: Address 3.E8E5

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:4 USX1

Rx_Unidata

Indication[1:0]

Rx_Unidata Indication

(0=None, 1=Invalid,

2=Idle, 3=Config)

3 Reserved Internal reserved - do not modify

2:0 USX1 SAN

State Machine

current state[2:0]

SAN State Machine current state RO

Table 6.600 PCS USX1 Unidata and SM status Register: Address 3.E8E4

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:4 USX1 Rx Rsvd

Status[3:0]

USX1 Rx Reserved Status BLH

3:0 USX1 XGMII to

GMII conversion

Status[3:0]

XGMII to GMII/MII Conversion Status

Bit 0: Detect Rx min IFG error

Bit 1: Detect Rx Signal Ordered_set

Bits 2-3: Reserved

BLH

Table 6.601 PCS USX1 Receive Status Register: Address 3.E8E5

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6.7.258 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6

Bit Name Description Type Default Note

F USX1 Link

Partner

Status

USX1 Link Partner advertisement

status.

0 = Link down

1 = Link up

E:D Reserved USX1

Link Partner

Advertisement 0

[1:0]

Reserved for future use. RO

C USX1 Link

Partner

Duplex

USX1 Link Partner advertisement

duplex.

0 = Half duplex

1 = Full duplex

B:9 USX1 Link

Partner

Speed [2:0]

USX1 Link Partner advertisement

speed.

0 = 10M

1 = 100M

2 = 1G

3 = 10G

4 = 2.5G

5 = 5G

8 USX1 Link

Partner

EEE Capability

USX1 Link Partner advertisement EEE

capability.

0 = Not supported

1 = Supported

Table 6.602 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6

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6.7.259 PCS Receive Vendor Alarms 1: Address 3.EC00

7 USX1 Link

Partner

EEE Clock Stop

Capability

USX1 Link Partner advertisement EEE

Clock Stop capability.

0 = Not supported

1 = Supported

6:1 Reserved USX1

Link Partner

Advertisement 1

[5:0]

Reserved for future use. RO

0 USX1 Link

Partner

Mode

USX1 Link Partner advertisement mode.

0 = SGMII

1 = USXGMII

Bit Name Description Type Default Note

F CRC Error 1 = Rx CRC Frame error LH This bit is set when a CRC-8 error is detected

on the receive PCS frame.

E LDPC Decode

Failure

1 = LDPC decode failure LH This bit is set when the LDPC decoder fails to

decode an LDPC block.

D:C Reserved Internal reserved - do not modify

B Local Fault

Detect

1 = RPL local fault detect LH Local_Fault Interrupt

A LOF Detect 1 = RPL LOF detect LH LOF Detection Interrupt

Table 6.603 PCS Receive Vendor Alarms 1: Address 3.EC00

Bit Name Description Type Default Note

Table 6.602 PCS USX1 Link Partner Adv Register<PCS USX1 Link Parter Adv Register>: Address 3.E8E6

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9 40G BIP Lock 1 = RPL 40G BIP lock LH Indicates the 40G BIP checker has achieved

lock to the alignment marker

8 Invalid 65B

Block

1 = Invalid Rx 65B block received in PCS

transmission frame

LH This bit is set when an invalid 65B block (but

without LDPC frame parity error) has been

detected on the received LDPC frame.

7 EEE Rx LPI

Active Off

1 = EEE Rx LPI Active Off LL

6 EEE Rx LPI

Active On

1 = EEE Rx LPI Active On LH

5LDPC

Consecutive

Errored Frame

Exceeded

1 = Rx PCS LDPC consecutive errored

frame threshold exceeded

LH Indicates the consecutive LDPC errored frame

has exceeded the threshold.

4 EEE Rx LPI Alert 1 = Rx PCS received alert indication LH Indicate Rx PCS received alert indication

3 EEE Rx LPI

Received

Latched Low

1 = Rx LPI has been detected LL Indicate LPI ordered-set is detected

2 EEE Rx LPI

Received

Latched High

1 = Rx LPI has been detected LH Indicate LPI ordered-set is detected

1 Reserved Internal reserved - do not modify

0 Change in

Auxilliary Bit

1 = Indicates a change in the value of the

auxilliary bit

LRF This bit is set when a change is detected in the

auxilliary bit.

Bit Name Description Type Default Note

Table 6.603 PCS Receive Vendor Alarms 1: Address 3.EC00

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6.7.260 PCS Receive Vendor Alarms 2: Address 3.EC01

6.7.261 PCS Receive Vendor Alarms 3: Address 3.EC02

6.7.262 PCS Receive Vendor Alarms 4: Address 3.EC03

6.7.263 PCS Receive Vendor Alarms 5: Address 3.EC04

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.604 PCS Receive Vendor Alarms 2: Address 3.EC01

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.605 PCS Receive Vendor Alarms 3: Address 3.EC02

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.606 PCS Receive Vendor Alarms 4: Address 3.EC03

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.607 PCS Receive Vendor Alarms 5: Address 3.EC04

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6.7.264 PCS Receive Vendor Alarms 6: Address 3.EC05

6.7.265 PCS Receive Vendor Alarms 7: Address 3.EC06

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B XFI1 Invalid 66B

Character

Received

1 = XFI1 Receive invalid 66B character

received

LH Invalid 66B code error

A:4 Reserved Internal reserved - do not modify

3 XFI0 Invalid 66B

Character

Received

1 = XFI0 Receive invalid 66B character

received

LH Invalid 66B code error

2:0 Reserved Internal reserved - do not modify

Table 6.608 PCS Receive Vendor Alarms 6: Address 3.EC05

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 XFI1 Receive

Link Status

Latch High

Status of the XFI1 receive link LH This indicates the status of the XFI1 receive

link.

6 Reserved Internal reserved - do not modify

5 XFI1 High BER

Status

1 = XFI1 High BER condition LH

4 XFI1 Block Lock

Status

1 = XFI1 Block Lock condition LL

Table 6.609 PCS Receive Vendor Alarms 7: Address 3.EC06

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6.7.266 PCS Receive Vendor Alarms 10: Address 3.EC09

3 XFI0 Receive

Link Status

Latch High

Status of the XFI0 receive link LH This indicates the status of the XFI0 receive

link.

2 Reserved Internal reserved - do not modify

1 XFI0 High BER

Status

1 = XFI0 High BER condition LH

0 XFI0 Block Lock

Status

1 = XFI0 Block Lock condition LL

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B PTP Ingress Packet

Ready FIFO Error

1 = PTP Ingress packet ready FIFO

error

LH Asserted when PTP packet ready FIFO has

detected FIFO error

A PTP Ingress Packet

Ready FIFO Parity

Error

1 = PTP Ingress packet ready FIFO

parity error

LH Asserted when PTP packet ready FIFO has

detected parity error

9 PTP Ingress Packet

Remove Error

1 = PTP Ingress packet remove

error

LH Asserted when the packet length is too long for

the UDP checksum to be updated during

removal of the timestamp appended at the end

of packet. When this happens, the UDP

checksum will be set to all-zeroes.

8 PTP Ingress Packet

Received

1 = PTP Ingress packet received LH Asserted when a valid PTP packet has been

received. This can be used as the valid signal

for the received PTP packet information.

Table 6.610 PCS Receive Vendor Alarms 10: Address 3.EC09

Bit Name Description Type Default Note

Table 6.609 PCS Receive Vendor Alarms 7: Address 3.EC06

359

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7 PTP Ingress Packet

Pipeline FIFO Error

1 = PTP Ingress packet pipeline

FIFO error detected

LH Asserted when PTP packet buffer has

detected parity error

6 PTP Ingress Packet

Pipeline Parity Error

1 = PTP Ingress packet pipeline

parity error detected

LH Asserted when PTP timestamp buffer has

detected parity error

5 PTP Ingress Time

Stamp Buffer Parity

Error

1 = PTP Ingress time stamp buffer

parity error detected

LH Asserted when PTP packet pipeline has

detected parity error

4 PTP Ingress Packet

Buffer Parity Error

1 = PTP Ingress packet buffer

parity error detected

LH Asserted when PTP packet pipeline has

detected FIFO error

3 PTP Ingress Packet

Correction Field Error

1 = PTP Ingress packet correction

field error

LH Asserted when the packet length is too long for

the Correction field to be updated due to the

ingress timestamp appended at the end of

packet. This shall not happen for IEEE1588v2

compliant packets. But when this happens, the

Correction field will not be changed.

2 PTP Ingress Packet

Buffer Overflow Error

1 = PTP Ingress packet buffer

overflow error detected

LH Asserted when PTP packet has not been

captured because the buffer was full

1 PTP Ingress Time

Stamp Ready

1 = PTP Ingress packet time stamp

ready

RO Asserted when PTP packet timestamp has

captured. It will be cleared when the timestamp

buffer is empty

0 PTP Ingress Packet

Ready

1 = PTP Ingress packet ready RO Asserted when PTP packet has captured. It

will be cleared when the buffer is empty

Bit Name Description Type Default Note

Table 6.610 PCS Receive Vendor Alarms 10: Address 3.EC09

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6.7.267 PCS Receive Vendor Alarms 14: Address 3.EC0D

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E USX0 Rx

Header CRC

Error

Detect Rx Header CRC Error LH

D USX0 Rx

USXGMII

Local_Fault

Detect Rx USXGMII Local_Fault LH

C USX0 Link FIFO

Overflow Error

Link FIFO Overflow Error LH

B USX0 Link FIFO

Underflow Error

Link FIFO Underflow Error LH

A USX0 Link FIFO

Parity Error

Link FIFO Parity Error LH

9 USX0 RX

Packet Info

Message

Indicate the received Packet Information

Message has changed.

8 USX0 MAC Rx

FIFO Parity

Error

MAC Rx FIFO Parity Error LH

7 USX0 MAC Rx

FIFO Overflow

Err

MAC Rx FIFO Overflow Error LH

Table 6.611 PCS Receive Vendor Alarms 14: Address 3.EC0D

361

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6.7.268 PCS Receive Vendor Alarms 15: Address 3.EC0E

6 USX0 MAC Rx

FIFO Underflow

Err

MAC Rx FIFO Underflow Error LH

5 USX0 MAC Rx

FIFO Idle

deletion

MAC Rx FIFO Idle deletion LH

4 USX0 MAC Tx

FIFO Parity Err

MAC Tx FIFO Parity Error LH

3 USX0 MAC Tx

FIFO Overflow

MAC Tx FIFO Overflow Error LH

2 USX0 MAC Tx

FIFO Underflow

MAC Tx FIFO Underflow Error LH

1 USX0 MAC Tx

SFD Error

MAC Tx SFD Error LH

0 USX0 MAC Tx

FIFO Idle

insertion

MAC Tx FIFO Idle insertion LH

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E USX1 Rx

Header CRC

Error

Detect Rx Header CRC Error LH

Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E

Bit Name Description Type Default Note

Table 6.611 PCS Receive Vendor Alarms 14: Address 3.EC0D

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D USX1 Rx

USXGMII

Local_Fault

Detect Rx USXGMII Local_Fault LH

C USX1 Link FIFO

Overflow Error

Link FIFO Overflow Error LH

B USX1 Link FIFO

Underflow Error

Link FIFO Underflow Error LH

A USX1 Link FIFO

Parity Error

Link FIFO Parity Error LH

9 USX1 RX

Packet Info

Message

Indicate the received Packet Information

Message has changed.

8 USX1 MAC Rx

FIFO Parity

Error

MAC Rx FIFO Parity Error LH

7 USX1 MAC Rx

FIFO Overflow

Err

MAC Rx FIFO Overflow Error LH

6 USX1 MAC Rx

FIFO Underflow

Err

MAC Rx FIFO Underflow Error LH

5 USX1 MAC Rx

FIFO Idle

deletion

MAC Rx FIFO Idle deletion LH

4 USX1 MAC Tx

FIFO Parity Err

MAC Tx FIFO Parity Error LH

Bit Name Description Type Default Note

Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E

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6.7.269 PCS Receive Vendor Alarms 16: Address 3.EC0F

3 USX1 MAC Tx

FIFO Overflow

MAC Tx FIFO Overflow Error LH

2 USX1 MAC Tx

FIFO Underflow

MAC Tx FIFO Underflow Error LH

1 USX1 MAC Tx

SFD Error

MAC Tx SFD Error LH

0 USX1 MAC Tx

FIFO Idle

insertion

MAC Tx FIFO Idle insertion LH

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A USX0 Auto Neg

Complete Latch

Low

Auto-Negotiation complete LL

9 USX0 Auto Neg

Complete Latch

High

Auto-Negotiation complete LH

8 USX0 AN State

Machine

Interrupt

Auto-Negotiation State Machine

Interrupt

7 USX0 RX

Unidata Config

Change

Rx_Unidata or Rx_Config_Reg (Link

partner advertisement register) change

Table 6.613 PCS Receive Vendor Alarms 16: Address 3.EC0F

Bit Name Description Type Default Note

Table 6.612 PCS Receive Vendor Alarms 15: Address 3.EC0E

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6 USX0

Invocation of the

priority

resolution

function

Invocation of the priority resolution

function

5 USX0 Link

Timer Done

Link Timer Done LH

4 USX0

Ability match

indication

Ability match indication LH

3 USX0

Acknowledgeme

nt match

indication

Acknowledgement match indication LH

2 USX0

Consistency

match indication

Consistency match indication LH

1 USX0 Idle

Match Indication

Idle Match Indication LH

0 USX0 Link

Partner Adv

Change

Link partner advertisement register

change

Bit Name Description Type Default Note

Table 6.613 PCS Receive Vendor Alarms 16: Address 3.EC0F

365

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6.7.270 PCS Receive Vendor Alarms 17: Address 3.EC10

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A USX1 Auto Neg

Complete Latch

Low

Auto-Negotiation complete LL

9 USX1 Auto Neg

Complete Latch

High

Auto-Negotiation complete LH

8 USX1 AN State

Machine

Interrupt

Auto-Negotiation State Machine

Interrupt

7 USX1 RX

Unidata Config

Change

Rx_Unidata or Rx_Config_Reg (Link

partner advertisement register) change

6 USX1

Invocation of the

priority

resolution

function

Invocation of the priority resolution

function

5 USX1 Link

Timer Done

Link Timer Done LH

4 USX1

Ability match

indication

Ability match indication LH

3 USX1

Acknowledgeme

nt match

indication

Acknowledgement match indication LH

Table 6.614 PCS Receive Vendor Alarms 17: Address 3.EC10

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6.7.271 PCS Receive Vendor Internal Alarms : Address 3.ED0D

2 USX1

Consistency

match indication

Consistency match indication LH

1 USX1 Idle

Match Indication

Idle Match Indication LH

0 USX1 Link

Partner Adv

Change

Link partner advertisement register

change

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E USX0 Rx

Header CRC

Error

Detect Rx Header CRC Error LH

D USX0 Rx

USXGMII

Local_Fault

Detect Rx USXGMII Local_Fault LH

C USX0 Link FIFO

Overflow Error

Link FIFO Overflow Error LH

B USX0 Link FIFO

Underflow Error

Link FIFO Underflow Error LH

A USX0 Link FIFO

Parity Error

Link FIFO Parity Error LH

Table 6.615 PCS Receive Vendor Internal Alarms : Address 3.ED0D

Bit Name Description Type Default Note

Table 6.614 PCS Receive Vendor Alarms 17: Address 3.EC10

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9 USX0 RX

Packet Info

Message

Indicate the received Packet Information

Message has changed.

8 USX0 MAC Rx

FIFO Parity

Error

MAC Rx FIFO Parity Error LH

7 USX0 MAC Rx

FIFO Overflow

Err

MAC Rx FIFO Overflow Error LH

6 USX0 MAC Rx

FIFO Underflow

Err

MAC Rx FIFO Underflow Error LH

5 USX0 MAC Rx

FIFO Idle

deletion

MAC Rx FIFO Idle deletion LH

4 USX0 MAC Tx

FIFO Parity Err

MAC Tx FIFO Parity Error LH

3 USX0 MAC Tx

FIFO Overflow

MAC Tx FIFO Overflow Error LH

2 USX0 MAC Tx

FIFO Underflow

MAC Tx FIFO Underflow Error LH

1 USX0 MAC Tx

SFD Error

MAC Tx SFD Error LH

0 USX0 MAC Tx

FIFO Idle

insertion

MAC Tx FIFO Idle insertion LH

Bit Name Description Type Default Note

Table 6.615 PCS Receive Vendor Internal Alarms : Address 3.ED0D

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6.7.272 PCS Receive Vendor Internal Alarms : Address 3.ED0E

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E USX1 Rx

Header CRC

Error

Detect Rx Header CRC Error LH

D USX1 Rx

USXGMII

Local_Fault

Detect Rx USXGMII Local_Fault LH

C USX1 Link FIFO

Overflow Error

Link FIFO Overflow Error LH

B USX1 Link FIFO

Underflow Error

Link FIFO Underflow Error LH

A USX1 Link FIFO

Parity Error

Link FIFO Parity Error LH

9 USX1 RX

Packet Info

Message

Indicate the received Packet Information

Message has changed.

8 USX1 MAC Rx

FIFO Parity

Error

MAC Rx FIFO Parity Error LH

7 USX1 MAC Rx

FIFO Overflow

Err

MAC Rx FIFO Overflow Error LH

Table 6.616 PCS Receive Vendor Internal Alarms : Address 3.ED0E

369

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6.7.273 PCS Receive Vendor Internal Alarms : Address 3.ED0F

6 USX1 MAC Rx

FIFO Underflow

Err

MAC Rx FIFO Underflow Error LH

5 USX1 MAC Rx

FIFO Idle

deletion

MAC Rx FIFO Idle deletion LH

4 USX1 MAC Tx

FIFO Parity Err

MAC Tx FIFO Parity Error LH

3 USX1 MAC Tx

FIFO Overflow

MAC Tx FIFO Overflow Error LH

2 USX1 MAC Tx

FIFO Underflow

MAC Tx FIFO Underflow Error LH

1 USX1 MAC Tx

SFD Error

MAC Tx SFD Error LH

0 USX1 MAC Tx

FIFO Idle

insertion

MAC Tx FIFO Idle insertion LH

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A USX0 Auto Neg

Complete Latch

Low

Auto-Negotiation complete LL

Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F

Bit Name Description Type Default Note

Table 6.616 PCS Receive Vendor Internal Alarms : Address 3.ED0E

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9 USX0 Auto Neg

Complete Latch

High

Auto-Negotiation complete LH

8 USX0 AN State

Machine

Interrupt

Auto-Negotiation State Machine

Interrupt

7 USX0 RX

Unidata Config

Change

Rx_Unidata or Rx_Config_Reg (Link

partner advertisement register) change

6 USX0

Invocation of the

priority

resolution

function

Invocation of the priority resolution

function

5 USX0 Link

Timer Done

Link Timer Done LH

4 USX0

Ability match

indication

Ability match indication LH

3 USX0

Acknowledgeme

nt match

indication

Acknowledgement match indication LH

2 USX0

Consistency

match indication

Consistency match indication LH

Bit Name Description Type Default Note

Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F

371

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6.7.274 PCS Receive Vendor Internal Alarms : Address 3.ED10

1 USX0 Idle

Match Indication

Idle Match Indication LH

0 USX0 Link

Partner Adv

Change

Link partner advertisement register

change

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A USX1 Auto Neg

Complete Latch

Low

Auto-Negotiation complete LL

9 USX1 Auto Neg

Complete Latch

High

Auto-Negotiation complete LH

8 USX1 AN State

Machine

Interrupt

Auto-Negotiation State Machine

Interrupt

7 USX1 RX

Unidata Config

Change

Rx_Unidata or Rx_Config_Reg (Link

partner advertisement register) change

6 USX1 Invocation

of the priority

resolution

function

Invocation of the priority resolution

function

Table 6.618 PCS Receive Vendor Internal Alarms : Address 3.ED10

Bit Name Description Type Default Note

Table 6.617 PCS Receive Vendor Internal Alarms : Address 3.ED0F

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6.7.275 PCS Receive Vendor Interrupt Mask 1: Address 3.F400

5 USX1 Link Timer

Done

Link Timer Done LH

4 USX1

Ability match

indication

Ability match indication LH

3 USX1

Acknowledgeme

nt match

indication

Acknowledgement match indication LH

2 USX1

Consistency

match indication

Consistency match indication LH

1 USX1 Idle Match

Indication

Idle Match Indication LH

0 USX1 Link

Partner Adv

Change

Link partner advertisement register

change

Bit Name Description Type Default Note

F CRC Error Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 This bit is set when a CRC-8 error is detected

on the receive PCS frame.

E LDPC Decode

Failure Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 This bit is set when the LDPC decoder fails to

decode an LDPC block.

D:C Reserved Internal reserved - do not modify

Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400

Bit Name Description Type Default Note

Table 6.618 PCS Receive Vendor Internal Alarms : Address 3.ED10

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B Local Fault

Detect Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A LOF Detect

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

9 40G BIP Lock

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

8 Invalid 65B

Block Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 This bit is set when an invalid 65B block (but

without LDPC frame parity error) has been

detected on the received LDPC frame.

7 EEE Rx LPI

Active Off Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

6 EEE Rx LPI

Active On Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5LDPC

Consecutive

Errored Frame

Exceeded Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

4 EEE Rx LPI Alert

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 EEE Rx LPI

Received

Latched Low

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400

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6.7.276 PCS Receive Vendor Interrupt Mask 2: Address 3.F401

6.7.277 PCS Receive Vendor Interrupt Mask 3: Address 3.F402

6.7.278 PCS Receive Vendor Interrupt Mask 4: Address 3.F403

2 EEE Rx LPI

Received

Latched High

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 Reserved Internal reserved - do not modify

0 Change in

Auxilliary Bit

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 This bit is set when a change is detected in the

auxilliary bit.

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.620 PCS Receive Vendor Interrupt Mask 2: Address 3.F401

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.621 PCS Receive Vendor Interrupt Mask 3: Address 3.F402

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.622 PCS Receive Vendor Interrupt Mask 4: Address 3.F403

Bit Name Description Type Default Note

Table 6.619 PCS Receive Vendor Interrupt Mask 1: Address 3.F400

375

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6.7.279 PCS Receive Vendor Interrupt Mask 5: Address 3.F404

6.7.280 PCS Receive Vendor Interrupt Mask 6: Address 3.F405

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.623 PCS Receive Vendor Interrupt Mask 5: Address 3.F404

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B XFI1 Invalid 66B

Character

Received Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A:4 Reserved Internal reserved - do not modify

3 XFI0 Invalid 66B

Character

Received Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2:0 Reserved Internal reserved - do not modify

Table 6.624 PCS Receive Vendor Interrupt Mask 6: Address 3.F405

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6.7.281 PCS Receive Vendor Interrupt Mask 7: Address 3.F406

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 XFI1 Receive

Link Status

Latch High

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

6 Reserved Internal reserved - do not modify

5 XFI1 High BER

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

4 XFI1 Block Lock

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 XFI0 Receive

Link Status

Latch High

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2 Reserved Internal reserved - do not modify

1 XFI0 High BER

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 XFI0 Block Lock

Status Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.625 PCS Receive Vendor Interrupt Mask 7: Address 3.F406

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6.7.282 PCS Receive Vendor Debug 1: Address 3.F800

Bit Name Description Type Default Note

F PCS Rx

Descrambler

Disable

1 = Rx Descrambler Disabled

0 = Normal Operation

R/W

0 Setting this bit disables the Rx descrambler

during regular data transmission (i.e.

descrambler functionality during training and

startup is unmodified).

E:3 Reserved Internal reserved - do not modify

2 PCS Network

Loopback Merge

When set to 1, XAUI data from the local

MAC and PCS Network Loopback data

will be merged.

R/W

1 If the MAC sends data, it will take priority over

the PCS Network Loopback data. The

loopback data will be dropped.

1 PCS Network

Loopback Pass

Through

When set to 1, this bit enables loopback

traffic from the PCS Network Loopback

to pass-through towards the System

XAUI side. When set to 0, the data sent

towards the system XUAI will be an

IDLE ordered set data stream when in

PCS Network Loopback

R/W

1 This enables traffic to pass through as well as

loopback when the PCS Network Loopback is

enabled.

0 PCS Network

Loopback

When set to 1, data after the Rx PCS

layer will be looped back to the Tx PCS

layer and transmitted back towards the

network UTP line.

R/W

Table 6.626 PCS Receive Vendor Debug 1: Address 3.F800

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6.7.283 PCS Vendor Global Interrupt Flags 1: Address 3.FC00

Bit Name Description Type Default Note

F Standard Alarm

1 Interrupt

1 = Interrupt in standard alarms 1 RO An interrupt was generated from status

Address 3.1” on page 229.) and the

corresponding mask register (See “PCS

Standard Interrupt Mask 1: Address 3.D000”

on page 294.).

E Standard Alarm

2 Interrupt

1 = Interrupt in standard alarms 2 RO An interrupt was generated from status

Address 3.8” on page 233.) and the

corresponding mask register (See “PCS

Standard Interrupt Mask 2: Address 3.D001”

on page 295.).

D Standard Alarm

3 Interrupt

1 = Interrupt in standard alarms 3 RO An interrupt was generated from status

3.21” on page 237.) and the corresponding

mask register (See “PCS Standard Interrupt

Mask 3: Address 3.D002” on page 296.).

C Reserved Internal reserved - do not modify

B Vendor Specific

Tx Alarms 1

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from status

Address 3.CC00” on page 292.) and the

corresponding mask register (See “PCS

Transmit Vendor Interrupt Mask 1: Address

3.D400” on page 296.).

A Vendor Specific

Tx Alarms 2

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from status

Address 3.CC01” on page 293.) and the

corresponding mask register (See “PCS

Transmit Vendor Interrupt Mask 2: Address

3.D401” on page 297.).

Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00

379

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9 Vendor Specific

Tx Alarms 3

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from status

Address 3.CC02” on page 293.) and the

corresponding mask register (See “PCS

Transmit Vendor Interrupt Mask 3: Address

3.D402” on page 297.).

8:7 Reserved Internal reserved - do not modify

6 Vendor Specific

Rx Alarms 1

Interrupt

1 = Interrupt in vendor specific Rx

alarms 1

RO An interrupt was generated from status

Address 3.EC00” on page 354.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 1: Address

3.F400” on page 372.).

5 Vendor Specific

Rx Alarms 2

Interrupt

1 = Interrupt in vendor specific Rx

alarms 2

RO An interrupt was generated from status

Address 3.EC01” on page 356.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 2: Address

3.F401” on page 374.).

4 Vendor Specific

Rx Alarms 3

Interrupt

1 = Interrupt in vendor specific Rx

alarms 3

RO An interrupt was generated from status

Address 3.EC02” on page 356.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 3: Address

3.F402” on page 374.).

3 Vendor Specific

Rx Alarms 4

Interrupt

1 = Interrupt in vendor specific Rx

alarms 4

RO An interrupt was generated from status

Address 3.EC03” on page 356.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 4: Address

3.F403” on page 374.).

Bit Name Description Type Default Note

Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00

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6.7.284 PCS Vendor Global Interrupt Flags 3: Address 3.FC02

2 Vendor Specific

Rx Alarms 5

Interrupt

1 = Interrupt in vendor specific Rx

alarms 5

RO An interrupt was generated from status

Address 3.EC04” on page 356.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 5: Address

3.F404” on page 375.).

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Vendor Specific

Rx Alarms 6

Interrupt

1 = Interrupt in vendor specific Rx

alarms 6

RO An interrupt was generated from status

Address 3.EC05” on page 357.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 6: Address

3.F405” on page 375.).

6 Vendor Specific

Rx Alarms 7

Interrupt

1 = Interrupt in vendor specific Rx

alarms 7

RO An interrupt was generated from status

Address 3.EC06” on page 357.) and the

corresponding mask register (See “PCS

Receive Vendor Interrupt Mask 7: Address

3.F406” on page 376.).

5:0 Reserved Internal reserved - do not modify

Table 6.628 PCS Vendor Global Interrupt Flags 3: Address 3.FC02

Bit Name Description Type Default Note

Table 6.627 PCS Vendor Global Interrupt Flags 1: Address 3.FC00

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6.8 PHY XS Registers

6.8.1 PHY XS Standard Control 1: Address 4.0

Bit Name Description Type Default Note

F Reset 1 = PHY XS reset

0 = Normal operation

R/W

1 Resets the entire PHY.

The reset bit is automatically cleared upon

completion of the reset sequence by the

microcontroller. This bit is set to 1 during reset.

The reset is internally stretched by

approximately 1.7 us. Therefore the MDIO or

uP should allow for 1.7 us before writing any

PHY XS registers after this bit is set.

E Loopback 1 = System Interface Network

Loopback

0 = Normal operation

R/W 0 This enables network loopback on the

designated system interface.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

D Speed Selection 0 1 = 10Gb/s and above

0 = Unspecified

ROS 1 This should always be set to 1

C Reserved Internal reserved - do not modify

B Low Power 1 = Low-power mode

0 = Normal operation

R/W 0 A one written to this register causes the PHY

XS to enter low-power mode. If a global chip

low-power state is desired, use Bit B in "Global

Standard Control 1: Address 1E.0" should be

set.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Table 6.629 PHY XS Standard Control 1: Address 4.0

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6.8.2 PHY XS Standard Status 1: Address 4.1

A Clock Stop Enable 1 = The PHY XS may stop the clock

during LPI

0 = Clock not stoppable

R/W 0

9 XAUI Stop Enable 1 = The PHY XS may stop XAUI

signals during LPI

0 = XAUI not stoppable

R/W 0

8:7 Reserved Internal reserved - do not modify

6 Speed Selection 1 1 = 10Gb/s and above

0 = Unspecified

ROS 1 This should always be set to 1

5:2 Speed Selection 2

[3:0]

1 x x x = Reserved

x 1 x x = Reserved

x x 1 x = Reserved

x x x 1 = Reserved

0 0 0 0 = 10 Gb/s

ROS 0x0 This should always be set to 0

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Tx LPI Received 1 = Tx PHY XS has received LPI

0 = LPI not received

LH The source of the LPI signal is configured in

1E.C4A2.3:0.

A Rx LPI Received 1 = Rx PHY XS has received LPI

0 = LPI not received

LH The source of the LPI signal is configured in

1E.C4A2.3:0.

Table 6.630 PHY XS Standard Status 1: Address 4.1

Bit Name Description Type Default Note

Table 6.629 PHY XS Standard Control 1: Address 4.0

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9 Tx LPI Indication 1 = Tx PHY XS is currently receiving LPI

0 = Tx PHY XS is not currently receiving

LPI

RO The source of the LPI signal is configured in

1E.C4A2.3:0.

8 Rx LPI Indication 1 = Rx PHY XS is currently receiving LPI

0 = Rx PHY XS is not currently receiving

LPI

RO The source of the LPI signal is configured in

1E.C4A2.3:0.

7 Fault 1 = Fault condition detected

0 = No fault detected

RO This is the top-level fault indicator flag for the

PHY XS (aka XAUI) block, This bit is set if

either of the two bits 4.8.B or 4.8.A are set.

6 Clock Stop

Capable

1 = The attached PHY may stop the

clock during LPI

0 = Clock not stoppable

ROS 0

5:3 Reserved Internal reserved - do not modify

2 PHY XS

Transmit Link

Alignment

Status

Status of receive XAUI interface

alignment:

1 = XAUI receiver is aligned correctly

0 = XAUI receiver is not aligned

LL This indicates the status of the lane alignment

function on the receive XAUI interface. This is

a latching low version of Bit 4.18.C.

1Low Power

Ability

1 = PHY XS supports low-power mode

0 = no low-power mode supported

ROS 1 Indicates whether the XAUI interface supports

a low-power mode

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.630 PHY XS Standard Status 1: Address 4.1

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6.8.3 PHY XS Standard Device Identifier 1: Address 4.2

6.8.4 PHY XS Standard Device Identifier 2: Address 4.3

6.8.5 PHY XS Standard Speed Ability: Address 4.4

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.631 PHY XS Standard Device Identifier 1: Address 4.2

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.632 PHY XS Standard Device Identifier 2: Address 4.3

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 10G Capable 1 = PHY XS is 10 Gb/s capable

0 = PHY XS is not 10 Gb/s capable

ROS 1 This is always set to 1 in the AQR405.

Table 6.633 PHY XS Standard Speed Ability: Address 4.4

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6.8.6 PHY XS Standard Devices in Package 1: Address 4.5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no DTE

XAUI interface in the AQR405.

4 PHY XS Present 1 = PHY XS is present in package

0 = PHY XS is not present in package

ROS 1 This is always set to 1 as there is a PHY XS

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Table 6.634 PHY XS Standard Devices in Package 1: Address 4.5

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6.8.7 PHY XS Standard Devices in Package 2: Address 4.6

6.8.8 PHY XS Standard Status 2: Address 4.8

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the Global registers.

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the GbE registers.

C:0 Reserved Internal reserved - do not modify

Table 6.635 PHY XS Standard Devices in Package 2: Address 4.6

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 2, as the PHY XS is

present in the AQR405.

D:C Reserved Internal reserved - do not modify

Table 6.636 PHY XS Standard Status 2: Address 4.8

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6.8.9 PHY XS Standard Package Identifier 1: Address 4.E

6.8.10 PHY XS Standard Package Identifier 2: Address 4.F

B Transmit Fault 1 = Fault condition on transmit path

0 = No fault condition on transmit path

LH This bit indicates whether there is a fault

somewhere along the transmit path. A fault will

be indicated if there is an alignment fault, a

synchronization fault on any lane, or a FIFO

underflow/overflow error.

A Receive Fault 1 = Fault condition on receive path

0 = No fault condition on receive path

LH This bit indicates whether there is a fault

somewhere along the receive path. A fault will

be indicated if there is a FIFO

underflow/overflow error.

9:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.637 PHY XS Standard Package Identifier 1: Address 4.E

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.638 PHY XS Standard Package Identifier 2: Address 4.F

Bit Name Description Type Default Note

Table 6.636 PHY XS Standard Status 2: Address 4.8

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6.8.11 PHY XS EEE Capability Register: Address 4.14

6.8.12 PHY XS EEE Wake Error Counter: Address 4.16

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4 PHY XS EEE 1 = EEE is supported for PHY XS

0 = EEE is not supported for PHY XS

ROS 1

3:1 Reserved Internal reserved - do not modify

0 XAUI Stop Capable 1 = The DTE XS may stop XAUI signals

during LPI

0 = XAUI signals not stoppable

ROS 0

Table 6.639 PHY XS EEE Capability Register: Address 4.14

Bit Name Description Type Default Note

F:0 EEE Wake Error

Counter [F:0]

EEE wake error counter SCT 0x0000 This register is a 16-bit saturating clear on read

counter. The wake error source is configured

with 1E.C4A2.A:8. The default wake error

source is from the TXI.

Table 6.640 PHY XS EEE Wake Error Counter: Address 4.16

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6.8.13 PHY XS Standard XGXS Lane Status: Address 4.18

6.8.14 PHY XS Standard XGXS Test Control: Address 4.19

Bit Name Description Type Default Note

F:D Reserved Internal reserved - do not modify

C PHY XGXS

Lane Alignment

Status

1 = XAUI Rx lanes aligned

0 = XAUI Rx lanes not aligned

RO When set, this bit indicates that the four XAUI

Rx lanes are properly aligned. This is a

non-latching version of bit 4.1.2.

B PHY XGXS

Pattern Testing

Ability

1 = XAUI has the ability to generate

XAUI Tx test patterns

0 = XAUI does not have the ability to

generate XAUI Tx test patterns

ROS 1 This is always set to 1 as the AQR405 is

capable of generating test patterns at the XAUI

interface.

A PHY XGXS

Loopback Ability

1 = XAUI has the ability to perform a

loopback function

0 = XAUI does not have the ability to

perform a loopback function

ROS 1 This is always set to 1 as the AQR405 is

capable of performing loopback at the XAUI

interface.

9:4 Reserved Internal reserved - do not modify

3:0 Lane Sync [3:0] 1 = Lane is synchronized

0 = Lane is not synchronized

Bit 0 corresponds to Lane 0 and so on

RO When set, these bits indicates that the

corresponding lane of the XAUI interface is

synchronized.

Table 6.641 PHY XS Standard XGXS Lane Status: Address 4.18

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

Table 6.642 PHY XS Standard XGXS Test Control: Address 4.19

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6.8.15 TimeSync PHY XS Capability: Address 4.1800

2 Receive Test-

Pattern Enable

1 = XAUI Tx test pattern enabled

0 = XAUI Tx test pattern not enabled

R/W

0 When set, this bit places the transmitters of the

XAUI interface into test pattern mode.

1:0 Test-Pattern

Select [1:0]

0x3 = Reserved

0x2 = Mixed-frequency test pattern

0x1 = Low-frequency test pattern

0x0 = High-frequency test pattern

R/W

0x2 These test patterns are described in Annex

48A of 802.3ae. These bits also interact with

the Extended Test Pattern Control bits [C:B] in

“PHY XS Transmit (XAUI Rx) Vendor Debug 1:

Address 4.D800” on page 413. The full range

of options is described there, but for these

functions to correspond to the test-patterns

described here, bits [C:B] must be set to zero.

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 TimeSync

Transmit Path

Data Delay

1 = PHY XS provides information on

transmit path data delay in registers

4.1801 through 4.1804

0 = PHY XS does not provide

information on transmit path data

delay

0 TimeSync

Receive Path

Data Delay

1 = PHY XS provides information on

receive path data delay in registers

4.1805 through 4.1808

0 = PHY XS does not provide

information on receive path data

delay

Table 6.643 TimeSync PHY XS Capability: Address 4.1800

Bit Name Description Type Default Note

Table 6.642 PHY XS Standard XGXS Test Control: Address 4.19

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6.8.16 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801

6.8.17 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802

6.8.18 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803

Bit Name Description Type Default Note

F:0 Maximum PHY

XS Transmit

Path Data Delay

LSW [F:0]

LSW of maximum PHY XS transmit

delay in nanoseconds

Table 6.644 TimeSync PHY XS Transmit Path Data Delay 1: Address 4.1801

Bit Name Description Type Default Note

F:0 Maximum PHY

XS Transmit

Path Data Delay

MSW [F:0]

MSW of maximum PHY XS transmit

delay in nanoseconds

Table 6.645 TimeSync PHY XS Transmit Path Data Delay 2: Address 4.1802

Bit Name Description Type Default Note

F:0 Minimum PHY

XS Transmit

Path Data Delay

LSW [F:0]

LSW of minimum PHY XS transmit delay

in nanoseconds

Table 6.646 TimeSync PHY XS Transmit Path Data Delay 3: Address 4.1803

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6.8.19 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804

6.8.20 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805

6.8.21 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806

Bit Name Description Type Default Note

F:0 Minimum PHY

XS Transmit

Path Data Delay

MSW [F:0]

MSW of minimum PHY XS transmit

delay in nanoseconds

Table 6.647 TimeSync PHY XS Transmit Path Data Delay 4: Address 4.1804

Bit Name Description Type Default Note

F:0 Maximum PHY

XS Receive Path

Data Delay LSW

[F:0]

LSW of maximum PHY XS receive delay

in nanoseconds

Table 6.648 TimeSync PHY XS Receive Path Data Delay 1: Address 4.1805

Bit Name Description Type Default Note

F:0 Maximum PHY

XS Receive Path

Data Delay

MSW [F:0]

MSW of maximum PHY XS receive

delay in nanoseconds

Table 6.649 TimeSync PHY XS Receive Path Data Delay 2: Address 4.1806

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6.8.22 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807

6.8.23 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808

6.8.24 PHY XS SERDES Configuration 1: Address 4.C180

Bit Name Description Type Default Note

F:0 Minimum PHY

XS Receive Path

Data Delay LSW

[F:0]

LSW of minimum PHY XS receive delay

in nanoseconds

Table 6.650 TimeSync PHY XS Receive Path Data Delay 3: Address 4.1807

Bit Name Description Type Default Note

F:0 Minimum PHY

XS Receive Path

Data Delay

MSW [F:0]

MSW of minimum PHY XS receive delay

in nanoseconds

Table 6.651 TimeSync PHY XS Receive Path Data Delay 4: Address 4.1808

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4 SERDES

Configuration

Reserved 1-1

Reserved R/W 0

Table 6.652 PHY XS SERDES Configuration 1: Address 4.C180

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6.8.25 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0

6.8.26 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0

3 Reserved Internal reserved - do not modify

2:0 SERDES

Configuration

Reserved 1-2

[2:0]

Reserved R/W 0x0

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SERDES Lane 0

Configuration

Reserved 1

Reserved R/W 1

Table 6.653 PHY XS SERDES Lane 0 Configuration 1: Address 4.C1C0

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SERDES Lane 1

Configuration

Reserved 1

Reserved R/W 1

Table 6.654 PHY XS SERDES Lane 1 Configuration 1: Address 4.C1D0

Bit Name Description Type Default Note

Table 6.652 PHY XS SERDES Configuration 1: Address 4.C180

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6.8.27 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0

6.8.28 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0

6.8.29 PHY XS SERDES LUT 256: Address 4.C200

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SERDES Lane 2

Configuration

Reserved 1

Reserved R/W 1

Table 6.655 PHY XS SERDES Lane 2 Configuration 1: Address 4.C1E0

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SERDES Lane 3

Configuration

Reserved 1

Reserved R/W 1

Table 6.656 PHY XS SERDES Lane 3 Configuration 1: Address 4.C1F0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SERDES LUT 256

Reserved [7:0]

Reserved R/W 0x00 Spans 0xC200 to 0xC2FF.

Table 6.657 PHY XS SERDES LUT 256: Address 4.C200

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6.8.30 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440

Bit Name Description Type Default Note

F:D Reserved

Transmit

Provisioning

C440 [2:0]

Reserved for future use R/W

0x0

C 50 MHz Primary

Output Enable

This bit enables the output of the 50

MHz reference clock on the primary

output:

1 = Enable the 50 MHz primary output

0 = Disable the 50 MHz primary output

R/W

0These fields can only be changed through the

primary PHY only (i.e. PHY 0)!!

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

B50 MHz

Secondary

Output Enable

This bit enables the output of the 50

MHz reference clock on the secondary

output:

1 = Enable the 50 MHz secondary output

0 = Disable the 50 MHz secondary

output

R/W

Table 6.658 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440

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A:1 Reserved

Transmit

Provisioning 1

[9:0]

Reserved for future use R/W

0x000

0 SERDES Reset 1 = Reset SERDES

0 = Reset completed

R/W

0 This self-clearing register reinitializes the

SERDES. If the network interface is linked, the

SERDES will be reinitialized at the current line

rate. If not, the rate used will be based on the

SERDES startup mode.

NOTE! This bit will not self-clear in the

absence of a valid Rx signal that can be used

to perform Rx autocal

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Bit Name Description Type Default Note

Table 6.658 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 1: Address 4.C440

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6.8.31 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441

Bit Name Description Type Default Note

F:E System I/F 10G

Operating Mode

[1:0]

This field sets the 10G configuration of

the system I/F:

0x0 = XAUI

0x1 = RXAUI

0x2 = KR (SERDES2 = XFI1)

0x3 = Reserved

R/W

0x0 This field can only be changed via

provisioning.

NOTE! The start-up mode for these rates is

selected in 7.C410.F:D. Also - KR

autonegotiation is not supported as it is not

defined to operate with Clause 28

Autonegotation. If UXSGMII operation is

desired, select KR, and it will be used for all

rates.

D System I/F

2500BASE-X

Enable

0 = Normal mode

1 = Enable 2500BASE-X mode for 2.5G

R/W

0 If enabled, 2500BASE-X mode will be used for

2.5G. In normal mode, 2.5G operation

depends on the 10G Operating Mode setting

(4.C441.[F:E])

Operation mode of other speeds depend on

the 10G Operating Mode setting and SERDES

Start-Up Mode (7.C410.[F:D]).

C:B System I/F

1G/100M

Operating Mode

[1:0]

This field sets the 1G/100M

configuration of the system I/F:

0x0 = Normal mode

0x1 = XFI

0x2 - 0x3 = reserved

R/W

0x0 This field can only be changed via

provisioning.

In normal mode, 1G/100M operating mode

depends on the SERDES Start-Up Mode

(7.C410.[F:D])

A:9 Reserved

Transmit

Provisioning 2a

[1:0]

Reserved for future use R/W

0x0

Table 6.659 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441

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8:6 PHY Operating

Mode [2:0]

This field sets the connectivity of the

PHY:

0x0 = Selected 10G mode on System I/F

UTP (RJ-45) is Network I/F

0x1 = Look-aside Mode: KR1 is System

I/F (SERDES 2 = XFI1 / SGMII1)

KR0 is Network I/F (SERDES 0 =

SFI0 / SGMII0)

0x2 = 1+ 1 (SERDES 2 = KR1 / SGMII1

of the selected PHY (see Bit 5) is

the System I/F)

0x3 = Reserved

0x4 -> 0x7 = Reserved

R/W

0x0 This register selects the basic PHY

configuration. This field can only be changed

via provisioning.

5RXAUI

Operating Mode

1 = Dune

0 = Marvell

R/W

0 This bit governs whether the RXAUI functions

in Marvell mode (default) or Dune mode.

4 Enable KR

Training

1 = KR Training Enabled

0 = KR Training Disabled

R/W

0 This bit governs whether KR training is

performed if KR is selected as the 10G

operating interface. NOTE! KR without training

enabled is essentially XFI+.

3 USX Autoneg

Control For MAC

1 = Enable

0 = Disable

R/W

0 USX enable/disable control for MAC. This

gives USX autonegotiation control to MAC to

enable/disable at any time after PHY reset.

2 Reserved

Transmit

Provisioning 2b

Reserved for future use R/W

1:0 Lookaside Port

Operating Mode

[1:0]

0x0 = 10GBASE-R (XFI0)

0x1 = 1000BASE-X (SGMII0)

0x3 = KR / USXGMII

R/W

0x0 This field is used to control the start-up

behavior of the PHY’s lookaside port I/F, when

the PHY Operation Mode (Bits 7:6) is set to

0x1.

Bit Name Description Type Default Note

Table 6.659 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2: Address 4.C441

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6.8.32 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442

Bit Name Description Type Default Note

F:E XAUI Rx Lane 3

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

These are used to change the mapping of the

SERDES to the XAUI lanes, allowing for

flexible PCB layout. This field can only be

changed via provisioning.

D:C XAUI Rx Lane 2

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

B:A XAUI Rx Lane 1

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

9:8 XAUI Rx Lane 0

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

7:4 XAUI Rx Lane

Invert [3:0]

A 1 inverts the selected XAUI lane(s),

with Bit 0 = Lane 0, etc.

R/W

0x0

3:2 System SGMII

Rx SERDES

[1:0]

This sets the lane to be used for System

SGMII Rx Interface (GbE Tx path):

0x0 = SERDES 0

0x1 = SERDES 1

0x2 = SERDES 2

0x3 = SERDES 3

R/W

0x0 This selection is independent of what rate /

format the system 10G interface is running at,

except if look-aside mode (Bits 4.C441.7:6). In

this case, Lane 2 must be used as the SGMII

interface. This field can only be changed via

provisioning.

1 System SGMII

Rx Invert

1 = Invert the System SGMII Rx

Interface

R/W

0 This inverts the SGMII Rx interface. This field

can only be changed via provisioning.

0 Reserved Internal reserved - do not modify

Table 6.660 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 3: Address 4.C442

401

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6.8.33 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443

Bit Name Description Type Default Note

F:C Reserved

Transmit

Provisioning 4a

[3:0]

Reserved for future use R/W

0x0

BSystem KR Rx

Invert

1 = Invert System KR Rx (SERDES2 =

KR1)

R/W

0 This field can only be changed via

provisioning.

A Lookaside Port

Rx Invert

1 = Invert KR0 / SGMII0 Rx R/W

0 SERDES0 = KR0 / SGMII0 is the network

interface. This field can only be changed via

provisioning.

9:0 Reserved

Transmit

Provisioning 4

[9:0]

Reserved for future use R/W

0x000

Table 6.661 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 4: Address 4.C443

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6.8.34 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444

Bit Name Description Type Default Note

F:B Loopback

Control [4:0]

0x00 = No loopback

0x01 = System Interface - System Loopback

0x02 = Reserved

0x03 = System Interface - Network Loopback

0x04 - 0x08 = Reserved

0x09 = Network Interface - System Loopback

0x0A = Reserved

0x0B = Network Interface - Network

Loopback

0x0C - 0x1F = Reserved

R/W

0x00 These bits, in conjunction with the chip

configuration and the rate (Bits 1:0), select the

loopback to configure for the chip. Setting one

of these loopbacks provisions the chip for the

specified loopback. Upon clearing the

loopback, the chip returns to it’s configuration

prior to entering loopback (irregardless of

whether other loopbacks were selected after

the initial loopback).

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

A:6 Reserved

Transmit

Provisioning 5

[4:0]

Reserved for future use R/W

0x00

5 MDI Packet

Generation

1 = CRPAT packet generation out MDI

interface

0 = No CRPAT packet generation out

MDI interface

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

on the MDI interface at the selected rate.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Table 6.662 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444

403

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4 Look-Aside Port

Packet

Generation

1 = CRPAT packet generation out 10G

look-aside interface (KR0)

0 = No CRPAT packet generation out

10G look-aside interface (KR0)

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

on KR0.

NOTE!! This only functions if KR1 (SERDES2)

is selected as the system interface in

(4.C441.F:E).

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

3 System I/F

Packet

Generation

1 = CRPAT packet generation out 10G

system interface

0 = No CRPAT packet generation out

10G system interface

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

CRPAT packets on the selected 10G system

interface (4.C441.F:E)

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

2:0 Rate [2:0] 0x7 - 0x6 = reserved

0x5 = 5G

0x4 = 2.5G

0x3 = 10G

0x2 = 1G

0x1 = 100M

0x0 = reserved

R/W

0x0 These bits select the rate for the loopback and

packet generation. SERDES configuration, as

well autonegotiation is controlled accordingly

when a loopback is selected. For instance, if

100M system loopback on the network

interface is selected, SGMII on the system

interface is enabled to connect at 100M, and if

passthrough is enabled 100BASE-TX will be

the only advertised rate and will force a

re-autonegotiation if not already connected at

100M.

Bit Name Description Type Default Note

Table 6.662 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 5: Address 4.C444

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6.8.35 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445

6.8.36 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802

6.8.37 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803

Bit Name Description Type Default Note

F:0 Reserved

Transmit

Provisioning 6

[F:0]

Reserved for future use R/W

0x0000

Table 6.663 PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 6: Address 4.C445

Bit Name Description Type Default Note

F:0 Tx Frame

Counter LSW

[F:0]

Tx Good Frame Counter SCT

0x0000 This counts 10G Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.664 PHY XS Transmit (XAUI Rx) PCS Status 1: Address 4.C802

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Tx Frame

Counter MSW

[9:0]

Tx Good Frame Counter SCT

0x000 This counts 10G Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.665 PHY XS Transmit (XAUI Rx) PCS Status 2: Address 4.C803

405

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6.8.38 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804

6.8.39 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805

6.8.40 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820

Bit Name Description Type Default Note

F:0 Tx Frame Error

Counter LSW

[F:0]

Tx Bad Frame Counter SCT

0x0000 This counts 10G Ethernet frames with a bad

FCS (aka CRC-32).

Table 6.666 PHY XS Transmit (XAUI Rx) PCS Status 3: Address 4.C804

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Tx Frame Error

Counter MSW

[9:0]

Tx Bad Frame Counter SCT

0x000 This counts 10G Ethernet frames with a bad

FCS (aka CRC-32).

Table 6.667 PHY XS Transmit (XAUI Rx) PCS Status 4: Address 4.C805

Bit Name Description Type Default Note

F:0 Numbers of

Serdes Cals

[F:0]

Number of SERDES calibrations since

the last PHY reset (or power-up).

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

Table 6.668 PHY XS Transmit (XAUI Rx) Reserved Vendor State 1: Address 4.C820

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6.8.41 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821

6.8.42 PHY XS Transmit (XAUI Rx) Reserved Vendor State 3: Address 4.C822

Bit Name Description Type Default Note

F:8 Number of SIF

Block Lock

Transtitions 1 - 0

[7:0]

Number of SIF block lock transitions

since PHY reset from 1 to 0 i.e. loss of

block lock.

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

7:0 Number of SIF

Block Lock

Transtitions 0 - 1

[7:0]

Number of SIF block lock transitions

since PHY reset from 0 to 1, i.e.

regained block lock.

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

Table 6.669 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821

Bit Name Description Type Default Note

F:0 Number of SIF

XGS

Switch-overs

[F:0]

Number of SIF side XGS Switch-overs

since Phy Reset.

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

Table 6.670 PHY XS Transmit (XAUI Rx) Reserved Vendor State 2: Address 4.C821

407

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6.8.43 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00

6.8.44 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01

Bit Name Description Type Default Note

F CRPAT Test Pattern

Checker Sync Error

1 = Test pattern checker is out of

sync

0 = Test pattern checker is in sync

E:B PRBS Test Pattern

Checker Sync Error

[3:0]

1 = Test pattern checker is out of

sync

0 = Test pattern checker is in sync

Bit 0 corresponds to lane 0 and so

A:1 Reserved Internal reserved - do not modify

0 MACSEC Egress

Interrupt

1 = MACSEC Egress Interrupt LH

Table 6.671 PHY XS Transmit (XAUI Rx) Vendor Alarms 1: Address 4.CC00

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D XAUI Rx Sequence

Ordered Set

Deletion

1 = Sequence ordered set was deleted

on the XAUI Rx interface

C Reserved Internal reserved - do not modify

Table 6.672 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01

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B:A XAUI Rx Lane

Alignment Lock

Status [1:0]

1 = Lanes locked LL

9 XAUI Rx Reserved

XGMII Character

Received

1 = Reserved XGMII character was

received on the XAUI Rx interface

8 XAUI Rx Invalid

XGMII Character

Received

1 = Invalid XGMII character was

received on the XAUI Rx interface

7:4 XAUI Rx Code

Violation Error [3:0]

1 = A code violation error was detected

on the corresponding lane of the

XAUI Rx interface.

Bit 0 corresponds to lane 0 and so on

3:0 XAUI Rx Running

Disparity Error [3:0]

1 = A running disparity error was

detected on the corresponding lane

of the XAUI Rx interface.

Bit 0 corresponds to lane 0 and so on

Bit Name Description Type Default Note

Table 6.672 PHY XS Transmit (XAUI Rx) Vendor Alarms 2: Address 4.CC01

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6.8.45 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02

6.8.46

6.8.47 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000

Bit Name Description Type Default Note

F:C Loss of Signal [3:0] 1 = Loss of Signal on associated

logical lane:

Bit 0: KR0, XAUI Lane 0, SGMII

Bit 1: XAUI Lane 1

Bit 2: KR1, XAUI Lane 2

Bit 3: XAUI Lane 3

LH These bits provide the Loss of Signal

indication for the logical SERDES lane that

loses signal.

B:0 Reserved PHY XS

Transmit Alarms [B:0]

Reserved LH

Table 6.673 PHY XS Transmit (XAUI Rx) Vendor Alarms 3: Address 4.CC02

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Tx LPI Received

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 4.1.B.

A Rx LPI Received

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 4.1.A.

9:3 Reserved Internal reserved - do not modify Mask for Bit 4.1.B.

Table 6.674 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000

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6.8.48 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001

6.8.49 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400

2 PHY XS Transmit

Link Alignment Status

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for Bit 4.1.2. Note this bit also shows up

as Bit 4.24.C, but only as a status bit.

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B Transmit Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 4.8.B

A Receive Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Bit 4.8.A

9:0 Reserved Internal reserved - do not modify

Table 6.675 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 2: Address 4.D001

Bit Name Description Type Default Note

F CRPAT Test Pattern

Checker Sync Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E:B PRBS Test Pattern

Checker Sync Error

Mask [3:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

Table 6.676 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400

Bit Name Description Type Default Note

Table 6.674 PHY XS Transmit (XAUI Rx) Standard Interrupt Mask 1: Address 4.D000

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6.8.50 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401

A:1 Reserved Internal reserved - do not modify

0 MACSEC Egress

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D XAUI Rx

Sequence

Ordered Set

Deletion Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C Reserved Internal reserved - do not modify

B:A XAUI Rx Lane

Alignment Lock

Status Mask

[1:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

9 XAUI Rx

Reserved XGMII

Character

Received Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

8 XAUI Rx Invalid

XGMII Character

Received Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.677 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401

Bit Name Description Type Default Note

Table 6.676 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 1: Address 4.D400

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6.8.51 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402

6.8.52

6.8.53

6.8.54

7:4 XAUI Rx Code

Violation Error

Mask [3:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

3:0 XAUI Rx

Running

Disparity Error

Mask [3:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

Bit Name Description Type Default Note

F:C Loss of Signal

Mask [3:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W 0x0

B:0 Reserved PHY

XS Transmit

Alarms Mask

[B:0]

Reserved R/W 0x000

Table 6.678 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 3: Address 4.D402

Bit Name Description Type Default Note

Table 6.677 PHY XS Transmit (XAUI Rx) Vendor Interrupt Mask 2: Address 4.D401

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6.8.55 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800

Bit Name Description Type Default Note

F Test Pattern

Force Error

1 = Force test pattern error R/W 0 This injects 10 PRBS Errors or 32 CRPAT

errors

E Test Pattern

Mode 7 Force

Error

1 = Force test pattern #7 error R/W 0 This injects 32 errors

D XAUI Rx Local

Fault Injection

1 = Inject local fault towards UTP Line R/W 0

C:B Test-Pattern

Extended Select

[1:0]

{Test-Pattern Extended Select [C:B],

Test-Pattern Select[1:0]}

0x0 = Annex 48A.1 High Frequency

0x1 = Annex 48A.2 Low Frequency

0x2 = Annex 48A.3 Mixed Frequency

0x4 = Annex 48A.4 CRPAT

0x5 = Annex 48A.5 CJPAT

0x6 = At speed CRPAT out the line

0x7 = PRBS-31 (x^31+x^28+1)

0x8 = PRBS-23 (x^23+x^18+1)

0x9 = PRBS-7 (x^7+x^6+1)

0xA = PRBS-15 (x^15+x^14+1)

0x3, 0xC -> 0xF = Reserved

R/W

0x0 These bits combine with the standard

defined bits [1:0] in “PHY XS Standard

XGXS Test Control: Address 4.19” on page

10 to define a broader suite of tests.

A Test Pattern

Check Enable

1 = Test pattern checker enabled

0 = Test pattern checker not enabled

R/W

0 Test pattern checker enable. (Used for

PRBS, Annex 48.4, and datapath error

checking.) This should only be enabled

after the test mode is selected.

9:8 Reserved Internal reserved - do not modify

7 Test Pattern

Check Point

Test pattern check point for CRPAT and

data path tests.

R/W

0 This is latched on the rising edge of "Test

Pattern Check Enable"

Table 6.679 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800

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6.8.56 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801

6 Test Pattern

Mode 7 Check

Enable

Enable checking for Test Mode 7 R/W

5 Test Pattern

Invert

Inverts the PRBS generation and checking R/W

1 Inversion can also be done using the

individual Tx and Rx lane inversion bits.

4:0 Test Pattern

Synchronization

Threshold [4:0]

PRBS synchronization threshold

configuration. If the number of PRBS bit

errors is greater than or equal to the

threshold within a 4 clock cycle window, the

PRBS checker will declare a

synchronization error and attempt to

resynchronize to the incoming PRBS

pattern. Setting this to 0, disables the

resynchronization

R/W

0x0A

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:C Test Pattern

Insert Extra Idles

[2:0]

Number of extra 4 Idle Octets to insert R/W 0x0 Number of extra 4 idle octets to insert in

CRPAT and CJPAT generation.

B:8 Test Pattern

Check Select

[3:0]

1 = Enable PRBS checking on the

corresponding XAUI Rx Lane

R/W 0x0

Table 6.680 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801

Bit Name Description Type Default Note

Table 6.679 PHY XS Transmit (XAUI Rx) Vendor Debug 1: Address 4.D800

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6.8.57 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810

6.8.58 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811

7:4 Reserved Internal reserved - do not modify

3:0 Test Pattern

Channel Select

[3:0]

1 = Test Pattern enabled R/W 0x0 Used to select which XAUI channel(s) the

PRBS is inserted on.

Bit Name Description Type Default Note

F:0 Channel 0 Test

Pattern Error

Counter [F:0]

A saturating 16 bit counter for errors

detected from the test mode. Error

counters for CRPAT, CJPAT, XAUI

PRBS7,23,31 (for channel(s) selected).

Note that CRPAT and CJPAT only use

channel 0

SCT 0x0000 Clear on read. This is a saturating 16-bit

counter which accumulates the number of test

errors during pattern test. Note that the API

must be used to read the x^15 error counts.

Table 6.681 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 1: Address 4.D810

Bit Name Description Type Default Note

F:0 Channel 1 Test

Pattern Error

Counter [F:0]

A saturating 16 bit counter for errors

detected from the test mode. Error

counters for CRPAT, CJPAT, XAUI

PRBS7,23,31 (for channel(s) selected).

Note that CRPAT and CJPAT only use

channel 0

SCT 0x0000 Clear on read. This is a saturating 16-bit

counter which accumulates the number of test

errors during pattern test. Note that the API

must be used to read the x^15 error counts.

Table 6.682 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 2: Address 4.D811

Bit Name Description Type Default Note

Table 6.680 PHY XS Transmit (XAUI Rx) Vendor Debug 2: Address 4.D801

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6.8.59 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812

6.8.60 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813

Bit Name Description Type Default Note

F:0 Channel 2 Test

Pattern Error

Counter [F:0]

A saturating 16 bit counter for errors

detected from the test mode. Error

counters for CRPAT, CJPAT, XAUI

PRBS7,23,31 (for channel(s) selected).

Note that CRPAT and CJPAT only use

channel 0

SCT 0x0000 Clear on read. This is a saturating 16-bit

counter which accumulates the number of test

errors during pattern test. Note that the API

must be used to read the x^15 error counts.

Table 6.683 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 3: Address 4.D812

Bit Name Description Type Default Note

F:0 Channel 3 Test

Pattern Error

Counter [F:0]

A saturating 16 bit counter for errors

detected from the test mode. Error

counters for CRPAT, CJPAT, XAUI

PRBS7,23,31 (for channel(s) selected).

Note that CRPAT and CJPAT only use

channel 0

SCT 0x0000 Clear on read. This is a saturating 16-bit

counter which accumulates the number of test

errors during pattern test. Note that the API

must be used to read the x^15 error counts.

Table 6.684 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 4: Address 4.D813

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6.8.61 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814

6.8.62 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410

Bit Name Description Type Default Note

F:0 Test Pattern

Mode 7 Error

Counter [F:0]

A saturating 16 bit counter for errors

detected from the test mode #7

SCT 0x0000 This is a saturating 16-bit counter which

accumulates the number of test errors during

pattern test as specified in test mode #7

Clause 55 test.

Table 6.685 PHY XS Transmit (XAUI Rx) Test Pattern Error Counter 5: Address 4.D814

Bit Name Description Type Default Note

F:E XAUI Tx Lane 3

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

These are used to change the mapping of the

SERDES to the XAUI lanes, allowing for

flexible PCB layout. This field can only be

changed via provisioning.

D:C XAUI Tx Lane 2

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

B:A XAUI Tx Lane 1

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

9:8 XAUI Tx Lane 0

SERDES [1:0]

Designates the SERDES for XAUI Lane

R/W

0x0

7:4 XAUI Tx Lane

Invert [3:0]

A 1 inverts the selected XAUI lane(s),

with Bit 0 = Lane 0, etc.

R/W

0x0 This field can only be changed via

provisioning.

Table 6.686 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410

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6.8.63 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411

3:2 System SGMII

Tx SERDES

[1:0]

This sets the lane to be used for System

SGMII Tx (GbE Rx path):

0x0 = SERDES 0

0x1 = SERDES 1

0x2 = SERDES 2

0x3 = SERDES 3

R/W

0x0 This selection is independent of what rate /

format the system 10G interface is running at,

except if look-aside mode (Bits 4.C441.7:6). In

this case, Lane 2 must be used as the SGMII

interface. This field can only be changed via

provisioning.

1 System SGMII

Tx Invert

1 = Invert System SGMII Tx Interface R/W

0 This inverts the System SGMII Tx interface.

This field can only be changed via

provisioning.

0 Reserved

Receive

Provisioning 1

Reserved for future use R/W

Bit Name Description Type Default Note

F:C Reserved

Receive

Provisioning 2a

[3:0]

Reserved for future use R/W

0x0

BSystem KR Tx

Invert

1 = Invert System KR Tx (SERDES2 =

KR1)

R/W

0 This field can only be changed via

provisioning.

A Lookaside Port

Tx Invert

1 = Invert SERDES0 = KR0 / SGMII0 Tx R/W

0 This field can only be changed via

provisioning.

Table 6.687 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411

Bit Name Description Type Default Note

Table 6.686 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 1: Address 4.E410

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6.8.64 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412

9 Apply SERDES

Tx Settings

1 = Apply SERDES transmit settings R/W

0 When set to 1, the SERDES transmit settings

in 4.E412 through 4.E419 will be propogated to

the SERDES core registers. This bit will be

cleared after the transfer is completed.

8:0 Reserved

Receive

Provisioning 2

[8:0]

Reserved for future use R/W

0x000

Bit Name Description Type Default Note

F:C Reserved Rx

Provisioning 3

[3:0]

R/W

0x0

B:8 SERDES Lane 0

Post Tap 1 [3:0]

R/W

0x0

7:5 SERDES Lane 0

Pre Tap [2:0]

R/W

0x0

4:0 SERDES Lane 0

Main Tap [4:0]

R/W

0x00

Table 6.688 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 3: Address 4.E412

Bit Name Description Type Default Note

Table 6.687 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 2: Address 4.E411

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6.8.65 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413

6.8.66 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414

Bit Name Description Type Default Note

F:3 Reserved Rx

Provisioning 4

[C:0]

R/W

0x0000

2:0 SERDES Lane 0

Amplitude [2:0]

Reserved for internal use R/W

0x0

Table 6.689 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 4: Address 4.E413

Bit Name Description Type Default Note

F:C Reserved Rx

Provisioning 5

[3:0]

R/W

0x0

B:8 SERDES Lane 1

Post Tap 1 [3:0]

R/W

0x0

7:5 SERDES Lane 1

Pre Tap [2:0]

R/W

0x0

4:0 SERDES Lane 1

Main Tap [4:0]

R/W

0x00

Table 6.690 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 5: Address 4.E414

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6.8.67 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415

6.8.68 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 7: Address 4.E416

Bit Name Description Type Default Note

F:3 Reserved Rx

Provisioning 6

[C:0]

R/W

0x0000

2:0 SERDES Lane 1

Amplitude [2:0]

Reserved for internal use R/W

0x0

Table 6.691 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415

Bit Name Description Type Default Note

F:C Reserved Rx

Provisioning 7

[3:0]

R/W

0x0

B:8 SERDES Lane 2

Post Tap 1 [3:0]

R/W

0x0

7:5 SERDES Lane 2

Pre Tap [2:0]

R/W

0x0

4:0 SERDES Lane 2

Main Tap [4:0]

R/W

0x00

Table 6.692 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 6: Address 4.E415

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6.8.69 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417

6.8.70 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418

Bit Name Description Type Default Note

F:3 Reserved Rx

Provisioning 8

[C:0]

R/W

0x0000

2:0 SERDES Lane 2

Amplitude [2:0]

Reserved for internal use R/W

0x0

Table 6.693 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 8: Address 4.E417

Bit Name Description Type Default Note

F:C Reserved Rx

Provisioning 9

[3:0]

R/W

0x0

B:8 SERDES Lane 3

Post Tap 1 [3:0]

R/W

0x0

7:5 SERDES Lane 3

Pre Tap [2:0]

R/W

0x0

4:0 SERDES Lane 3

Main Tap [4:0]

R/W

0x00

Table 6.694 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 9: Address 4.E418

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6.8.71 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419

6.8.72 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802

6.8.73 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803

Bit Name Description Type Default Note

F:3 Reserved Rx

Provisioning 10

[C:0]

R/W

0x0000

2:0 SERDES Lane 3

Amplitude [2:0]

Reserved for internal use R/W

0x0

Table 6.695 PHY XS Receive (XAUI Tx) Reserved Vendor Provisioning 10: Address 4.E419

Bit Name Description Type Default Note

F:0 Rx Frame

Counter LSW

[F:0]

Rx Good Frame Counter SCT

0x0000 This counts 10G Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.696 PHY XS Receive (XAUI Tx) PCS Status 1: Address 4.E802

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Rx Frame

Counter MSW

[9:0]

Rx Good Frame Counter SCT

0x000 This counts 10G Ethernet good frames (i.e. no

Ethernet CRC-32 / FCS errors).

Table 6.697 PHY XS Receive (XAUI Tx) PCS Status 2: Address 4.E803

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6.8.74 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804

6.8.75 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805

6.8.76 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810

Bit Name Description Type Default Note

F:0 Rx Frame Error

Counter LSW

[F:0]

Rx Bad Frame Counter SCT

0x0000 This counts 10G Ethernet frames with a bad

FCS (aka CRC-32).

Table 6.698 PHY XS Receive (XAUI Tx) PCS Status 3: Address 4.E804

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 Rx Frame Error

Counter MSW

[9:0]

Rx Bad Frame Counter SCT

0x000 This counts 10G Ethernet frames with a bad

FCS (aka CRC-32).

Table 6.699 PHY XS Receive (XAUI Tx) PCS Status 4: Address 4.E805

Bit Name Description Type Default Note

F:0 Number of USX

Aneg Restarts

[F:0]

Number of USX autonegotiations since

PHY reset.

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset

Table 6.700 PHY XS Receive (XAUI Tx) Reserved Vendor State 1: Address 4.E810

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6.8.77 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>:

Address 4.E812

Bit Name Description Type Default Note

F:E System Interface

Autoneg Status

[1:0]

0 = N/A

1 = Not Complete

2 = Complete

3 = Reserved

RO Indicates the completion progress of the

system interface’s autonegotation.

D Rx Link Up 0 = Link Not Up

1 = Link Up

RO Indicates that the system interface has linked

and is ready to receive.

C Tx Ready 0 = Not Ready

1 = Ready

RO Indicates that the system interface is ready to

transmit.

B:8 System Interface

Rate [3:0]

0 = 10M

1 = 100M

2 = 1G

3 = 10G

4 = 2.5G

5 = 5G

6 = Power Down

7 - 0xF = Reserved

RO Indicates the currently active data rate for the

system interface.

Table 6.701 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812

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6.8.78 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00

7:3 System Interface

In Use [4:0]

0 = Backplane KR

1 = Backplane KX

2 = XFI

3 = USXGMII

4 = XAUI

5 = XAUI Pause Based

6 = SGMII

7 = RXAUI

8 = MAC

9 = OFF

0xA - 0x1F = Reserved

RO Indicates the currently active mode for the

system interface.

2:0 Reserved

Receive State 3

[2:0]

Reserved for future use RO

Bit Name Description Type Default Note

F Reserved XGMII

Character

Received from

PCS

1 = Reserved XGMII character was

received from the PCS

E Invalid XGMII

Character

Received from

PCS

1 = Invalid XGMII character was

received from the PCS

Table 6.702 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00

Bit Name Description Type Default Note

Table 6.701 PHY XS System Interface Connection Status<PHY XS Receive (XAUI Tx) Reserved Vendor State 3>: Address 4.E812

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6.8.79 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01

D Link status

Message

Received from

PCS

1 = Link status message was received

from the PCS

C:1 Reserved Internal reserved - do not modify

0 MACSEC

Ingress Interrupt

1 = MACSEC Ingress Interrupt LH

Bit Name Description Type Default Note

F System Interface Rx

Link Up

1 = System Interface Rx has come

LH This bit indicates that the SERDES receive link

has come up. This is an alarm bit

corresponding to a 1 value of the status bit:

4.E812.D

E System Interface Rx

Link Down

1 = System Interface Rx has gone

down

LH This bit indicates that the SERDES receive link

has gone down. This is an alarm bit

corresponding to a 0 value of the status bit:

4.E812.D

D System Interface Tx

Ready

1 = System Interface Tx has

become ready to transmit

LH This bit indicates that the SERDES transmit

link has become ready to transmit. This is an

alarm bit corresponding to a 1 value of the

status bit: 4.E812.C

Table 6.703 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01

Bit Name Description Type Default Note

Table 6.702 PHY XS Receive (XAUI Tx) Vendor Alarms 1: Address 4.EC00

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6.8.80 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400

C System Interface Tx

Not Ready

1 = System Interface Tx has

become not-ready to transmit

LH This bit indicates that the SERDES transmit

link has become not-ready to transmit. This is

an alarm bit corresponding to a 0 value of the

status bit: 4.E812.C

B:0 Reserved PHY XS

Receive Alarms 2

[B:0]

Reserved LH

Bit Name Description Type Default Note

F Reserved XGMII

Character

Received from

PCS Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E Invalid XGMII

Character

Received from

PCS Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

D Link status

Message

Received from

PCS Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C:1 Reserved Internal reserved - do not modify

0 MACSEC

Ingress Interrupt

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.704 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 1: Address 4.F400

Bit Name Description Type Default Note

Table 6.703 PHY XS Receive (XAUI Tx) Vendor Alarms 2: Address 4.EC01

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6.8.81 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401

Bit Name Description Type Default Note

F System Interface Rx

Link Up Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for alarm: 4.EC01.F

E System Interface Rx

Link Down Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for alarm: 4.EC01.E

D System Interface Tx

Ready Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for alarm: 4.EC01.D

C System Interface Tx

Not Ready Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mask for alarm: 4.EC01.C

B:0 Reserved PHY XS

Receive Alarms 2

Mask [B:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0000 1 = Enable interrupt generation

0 = Disable interrupt generation

Table 6.705 PHY XS Receive (XAUI Tx) Vendor Interrupt Mask 2: Address 4.F401

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6.8.82 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800

6.8.83 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801

Bit Name Description Type Default Note

F:D XAUI Tx Error

Injection Lane

Select [2:0]

[F:D]

0x0 = Lane 0

0x1 = Lane 1

0x2 = Lane 2

0x3 = Lane 3

0x4 = All four lanes

R/W 0x0 This controls which of the 4 Tx XAUI lanes

debug error injection occurs on.

C XAUI Tx Inject

Synchronization

Error

1 = Inject a synchronization error R/W 0 This injects a synchronization error on the

lanes selected in F:D

B XAUI Tx Inject

Alignment Error

1 = Inject an alignment error R/W 0 This injects an alignment error on the lanes

selected in F:D

A XAUI Tx Inject

Code Violation

1 = Inject code violation error R/W 0 This injects the 10B codeword on the lanes

selected in F:D

9:0 XAUI Tx 10B

Violation

Codeword [9:0]

[9:0] = 10B violation codeword to be

injected by writing a 1 to Bit A

R/W 0x000

Table 6.706 PHY XS Receive (XAUI Tx) Vendor Debug 1: Address 4.F800

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.707 PHY XS Receive (XAUI Tx) Vendor Debug 2: Address 4.F801

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6.8.84 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802

6.8.85 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00

Bit Name Description Type Default Note

F PHY XS System

Loopback Pass

Through

When set to 1, this bit enables loopback

traffic from the PHY XS System

Loopback to pass-through towards the

network UTP line.

When set to 0, the data sent towards the

network UTP line will be all IDLEs

when in PHY XS System Loopback

R/W 0 This enables traffic to pass through as well as

loopback when the PHY XS System Loopback

is enabled.

E PHY XS System

Loopback

Enable

1 = Enable PHY XS System Loopback

mode

0 = Normal operation

R/W 0 This bit enables the PHY XS System Loopback

from the Tx XAUI Interface after lane

alignment to the Rx XAUI interface.

D XAUI Tx Local

Fault Injection

1 = Inject local fault towards XAUI

system side

0 = Normal operation

R/W 0

C Reserved 4 Reserved for future use R/W 0

B:0 Reserved Internal reserved - do not modify

Table 6.708 PHY XS Receive (XAUI Tx) Vendor Debug 3: Address 4.F802

Bit Name Description Type Default Note

F Standard Alarms

1 Interrupt

1 = Interrupt in standard alarms 1 RO An interrupt was generated from the status

E Standard Alarms

2 Interrupt

1 = Interrupt in standard alarms 2 RO An interrupt was generated from the status

Table 6.709 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00

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D:B Reserved Internal reserved - do not modify

A Vendor Specific

Tx Alarms 1

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from the status

9 Vendor Specific

Tx Alarms 2

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from the status

8 Vendor Specific

Tx Alarms 3

Interrupt

1 = Interrupt in vendor specific Tx alarms

RO An interrupt was generated from the status

7:3 Reserved Internal reserved - do not modify

2 Vendor Specific

Rx Alarms 1

Interrupt

1 = Interrupt in vendor specific Rx

alarms 1

RO An interrupt was generated from the status

1 Vendor Specific

Rx Alarms 2

Interrupt

1 = Interrupt in vendor specific Rx

alarms 1

RO An interrupt was generated from the status

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.709 PHY XS Vendor Global Interrupt Flags 1: Address 4.FC00

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6.9 Autonegotiation Registers

6.9.1 Autonegotiation Standard Control 1: Address 7.0

Bit Name Description Type Default Note

F Reset 1 = Autonegotiation reset

0 = Normal operation

R/W

1 Resets the entire PHY.

The reset bit is automatically cleared upon

completion of the reset sequence by the

microcontroller. This bit is set to 1 during

reset. The reset is internally stretched by

approximately 1.7 us. Therefore the MDIO

or uP should allow for 1.7 us before writing

any Autonegotiation registers after this bit

is set.

E Reserved Internal reserved - do not modify

D Extended Next

Page Control

1 = Extended next pages are enabled

0 = Extended next pages are disabled

R/W

1 This bit is OR’ed with bit 7.10.C.

C Autonegotiation

Enable

1 = Enable autonegotiation

0 = Disable autonegotiation

R/W

1 When enabled, autonegotiation determines

the link speed. If this bit is disabled,

autonegotiation is disabled.

B:A Reserved Internal reserved - do not modify

9Restart

Autonegotiation

1 = Restart autonegotiation process

0 = Normal operation

R/W

0 NOTE!! This is a processor intensive

operation. Completion of this operation can

be monitored via 1E.C831.F

8:0 Reserved Internal reserved - do not modify

Table 6.710 Autonegotiation Standard Control 1: Address 7.0

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6.9.2 Autonegotiation Standard Status 1: Address 7.1

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 Parallel

Detection Fault

1 = A fault has been detected via the parallel

detection function

0 = A fault has not been detected via the

parallel detection function

8 Reserved Internal reserved - do not modify

7 Extended Next

Page Status

1 = Extended next page will be used

0 = Extended next page will not be used

RO Indicates that both the local device and

the link partner have indicated support

for extended next page.

6 Page Received 1 = A page has been received

0 = A page has not been received

LH Indicates that a page has been

received. If a regular page, it is placed in

7.13 ->7.15. If an extended next page it

is placed in registers 7.19 -> 7.1B

5 Autonegotiation

Complete

1 = Autonegotiation complete

0 = Autonegotiation in process

RO This indicates the status of the

Autonegotiation receive link.

4 Remote Fault 1 = Remote fault condition detected

0 = No remote fault condition detected

LH This indicates that the remote PHY has

a fault.

3 Autonegotiation

Ability

1 = PHY is able to perform autonegotiation

0 = PHY is not able to perform autonegotiation

ROS 1 Always set as 1 as the local device has

autonegotiation ability.

2 Link Status 1 = Link is up

0 = Link lost since last read

LL This bit it is a duplicate of the PMA link

status bit in 1.1.2. Note that this is

latching low, so it can only be used to

detect link drops, and not the current

status of the link without performing

back-to-back reads.

Table 6.711 Autonegotiation Standard Status 1: Address 7.1

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6.9.3 Autonegotiation Standard Device Identifier 1: Address 7.2

6.9.4 Autonegotiation Standard Device Identifier 2: Address 7.3

1 Reserved Internal reserved - do not modify

0 Link Partner

Autonegotiation

Ability

1 = Link Partner able to perform

autonegotiation

0 = Link Partner not able to perform

autonegotiation

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.712 Autonegotiation Standard Device Identifier 1: Address 7.2

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.713 Autonegotiation Standard Device Identifier 2: Address 7.3

Bit Name Description Type Default Note

Table 6.711 Autonegotiation Standard Status 1: Address 7.1

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6.9.5 Autonegotiation Standard Devices in Package 1: Address 7.5

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no DTE

XAUI interface in the AQR405.

4 PHY XS Present 1 = PHY XS is present in package

0 = PHY XS is not present in package

ROS 1 This is always set to 1 as there is a PHY XS

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Table 6.714 Autonegotiation Standard Devices in Package 1: Address 7.5

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6.9.6 Autonegotiation Standard Devices in Package 2: Address 7.6

6.9.7 Autonegotiation Standard Status 2: Address 7.8

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the global control registers.

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the GbE registers.

C:0 Reserved Internal reserved - do not modify

Table 6.715 Autonegotiation Standard Devices in Package 2: Address 7.6

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 0x2, as the

Autonegotiation resides here in the AQR405.

D:0 Reserved Internal reserved - do not modify

Table 6.716 Autonegotiation Standard Status 2: Address 7.8

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6.9.8 Autonegotiation Standard Package Identifier 1: Address 7.E

6.9.9 Autonegotiation Standard Package Identifier 2: Address 7.F

6.9.10 Autonegotiation Advertisement Register: Address 7.10†

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.717 Autonegotiation Standard Package Identifier 1: Address 7.E

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.718 Autonegotiation Standard Package Identifier 2: Address 7.F

Bit Name Description Type Default Note

F Next page Ability 1 = Next page ability R/W

1 If a device implements Next Page ability

and wishes to engage in Next Page

exchange, it shall set the NP bit to 1. A

device may implement Next Page ability

and choose not to engage in Next Page

exchange by setting the NP bit to a 0.

E Reserved Internal reserved - do not modify

Table 6.719 Autonegotiation Advertisement Register: Address 7.10

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†This register is used in conjunction with bit 7.C400.5 to hard provision the autonegotiation base page that will be sent.

D Advertisement

Remote Fault

1 = Remote fault R/W 0 The remote fault bit provides a standard

transport mechanism for the transmission

of simple fault information. When the RF bit

in the received base link code word is set to

1, the RF bit will be set to 1.

Note: The PHY does not support a remote

fault sensing function.

C Extended Next

Page Ability

1 = Extended next page capable

0 = Not capable of extended next pages

R/W

1 The Extended Next Page (XNP) bit

indicates that the local device supports

transmission of extended next pages when

set to 1 and indicates that the local device

does not support extended next pages

when set to 0.

Bit Name Description Type Default Note

Table 6.719 Autonegotiation Advertisement Register: Address 7.10

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AQR405 Revision 0.11 - January 5, 2015

6.9.11 Autonegotiation Link Partner Base Page Ability Register: Address 7.13

B:5 Technology

Ability Field [6:0]

Bit 0: 10BASE-T

Bit 1: 10BASE-T full duplex

Bit 2: 100BASE-TX

Bit 3: 100BASE-TX full duplex

Bit 4: 100BASE-T4

Bit 5: PAUSE operation for full duplex links

Bit 6: Asymmetric PAUSE operation for full

duplex links

R/W

0x00 The Technology Ability Field contains

information indicating supported

technologies defined in Annex 28B.2 and

Annex 28D. Multiple technologies may be

advertised in the link code word. A device

shall support the data service ability for a

technology it advertises.

Since the PHY does not support 10BASE-T

or 100BASE-T4, these bits (0, 1, 4) should

always be set to zero.

4:0 Selector Field

[4:0]

This defines the device compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

R/W

0x01 This field should always be set to 0x01 as

the PHY is only capable of handling 802.3

Ethernet.

Bit Name Description Type Default Note

F Link Partner

Ability

1 = Next page ability

0 = Next page ability not supported or

not engaged

RO If Next Page ability is not supported, the NP bit

shall always be set to 0. If a device implements

Next Page ability and wishes to engage in Next

Page exchange, it shall set the NP bit to logic

E Link Partner

Base Page

Acknowledge

1 = Acknowledge RO The Acknowledge (ACK) is used by the

Auto-Negotiation function to indicate that a

device has successfully received its Link

Partner’s Link Code Word.

Table 6.720 Autonegotiation Link Partner Base Page Ability Register: Address 7.13

Bit Name Description Type Default Note

Table 6.719 Autonegotiation Advertisement Register: Address 7.10

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D Link Partner

Remote Fault

1 = Remote fault RO The remote fault bit provides a standard

transport mechanism for the transmission of

simple fault information. When the RF bit in the

received base link code word is set to 1, the RF

bit will be set to 1.

C Link Partner

Extended Next

Page Ability

1 = Extended next page capable

0 = Not capable of extended next pages

RO The extended next page indicates that the link

partner has indicated support for the extended

next page when set to 1. When set to 0, the link

partner does not support extended next page.

B:5 Link Partner

Technology

Ability Field [6:0]

Bit 0: 10BASE-T

Bit 1: 10BASE-T full duplex

Bit 2: 100BASE-TX

Bit 3: 100BASE-TX full duplex

Bit 4: 100BASE-T4

Bit 5: PAUSE operation for full duplex

links

Bit 6: Asymmetric PAUSE operation for

full duplex links

RO Technology ability field contains information

indicating supported technologies defined in

Annex 28B.2 and Annex 28D. Multiple

technologies may be advertised in the link

code word. A device shall support the data

service ability for a technology it advertises.

The arbitration function determines the

common mode of operation shared by a link

partner and resolves the multiple common

modes.

4:0 Link Partner

Selector Field

[4:0]

This defines the device compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

RO Selector field encodes 32 possible messages

defined in Annex 28A. Combinations not

specified are reserved for future use and shall

not be transmitted.

Bit Name Description Type Default Note

Table 6.720 Autonegotiation Link Partner Base Page Ability Register: Address 7.13

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6.9.12 Autonegotiation Extended Next Page Transmit Register: Address 7.16†

Bit Name Description Type Default Note

F Next Page 1 = Additional next page will follow

0 = Last page

R/W 0 Next page is used by the next page function

to indicate whether or not this is the last next

page to be transmitted.

E Reserved Internal reserved - do not modify

D Message Page 1 = Message page

0 = Unformatted page

R/W 0 Message page is used by the next page

function to differentiate a message page from

an unformatted page.

C Acknowledge 2 1 = Will comply with corresponding

message

0 = Cannot comply with corresponding

message

R/W 0 Acknowledge 2 is used by the next page

function to indicate that a device has the

ability to comply with the message.

B Toggle Value of toggle bit RO Set to opposite of corresponding bit in

previous page.

A:0 Message Code

Field [A:0]

[A:0] = Message Code Field:

0x0 = Reserved

0x1 = Null message

0x2 -> 0x3 Reserved Expansion message

0x4 = Remote fault details message

0x5 = OUI message

0x6 = PHY ID message

0x7 = 100BASE-T2 message

0x8 = 1000BASE-T message

0x9 = 10GBASE-T message

R/W

0x001 Interpreted as message code (see 802.3

Appendix 28C) if Message Page bit is set to

one (7.16:1). Otherwise interpreted as an

unformatted code field.

Table 6.721 Autonegotiation Extended Next Page Transmit Register: Address 7.16

†This register is used in conjunction with bit 7.C400.5 and registers 7.17 and 7.18 to hard provision the autonegotiation extended next page that

will be sent. Using this it is possible to hard-code the 1G and 10G capabilities, as well as short-reach capability.

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6.9.13 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17

6.9.14 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18

6.9.15 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19†

Bit Name Description Type Default Note

F:0 Unformatted Code

Field 1 [1F:10]

[F:0] = Unformatted Code Field 1 R/W

0x0000

Table 6.722 Autonegotiation Extended Next Page Unformatted Code Register 1: Address 7.17

Bit Name Description Type Default Note

F:0 Unformatted Code

Field 2 [2F:20]

[F:0] = Unformatted Code Field 2 R/W

0x0000

Table 6.723 Autonegotiation Extended Next Page Unformatted Code Register 2: Address 7.18

Bit Name Description Type Default Note

F Link Partner

1 = Next page ability RO

E Link Partner

Extended Next

Page

Acknowledge

1 = Link Partner acknowledges receipt

of corresponding page

RO Acknowledge is used by the autonegotiation

function to indicate that a device has

successfully received its link partners link code

word.

D Link Partner

Message Page

1 = Message page

0 = Unformatted page

Table 6.724 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19

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6.9.16 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A

†This register, along with 7.1A and 7.1B, are used to store the received next pages. If an extended next page is used, it is stored in 7.19 -> 7.1B.

C Link Partner

Acknowledge 2

1 = Link partner acknowledges that they

can comply with the current next

page

0 = Link partner cannot comply with the

current next page

B Link Partner

Toggle

Value of link partner’s toggle bit RO Set to opposite of corresponding bit in previous

page.

A:0 Link Partner

Message Code

Field [A:0]

[A:0] = Message Code Field:

0x0 = Reserved

0x1 = Null message

0x2 -> 0x3 Reserved Expansion

message

0x4 = Remote fault details message

0x5 = OUI message

0x6 = PHY ID message

0x7 = 100BASE-T2 message

0x8 = 1000BASE-T message

0x9 = 10GBASE-T message

RO Interpreted as message code (see 802.3

Appendix 28C) if Message Page bit is set to

one (7.16:1). Otherwise interpreted as an

unformatted code field.

Bit Name Description Type Default Note

F:0 Link Partner

Unformatted Code

Field 1 [F:0]

[F:0] = Unformatted Code Field 1 [15:0] RO

Table 6.725 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 1: Address 7.1A

Bit Name Description Type Default Note

Table 6.724 Autonegotiation Link Partner Extended Next Page Ability Register: Address 7.19

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6.9.17 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B

6.9.18 Autonegotiation 10GBASE-T Control Register: Address 7.20

Bit Name Description Type Default Note

F:0 Link Partner

Unformatted Code

Field 2 [F:0]

[F:0] = Unformatted Code Field 2 [15:0] RO

Table 6.726 Autonegotiation Link Partner Extended Next Page Unformatted Code Register 2: Address 7.1B

Bit Name Description Type Default Note

F MASTER-SLAVE

Manual

Configuration

Enable

1 = Enable MASTER-SLAVE Manual

configuration

0 = Disable MASTER-SLAVE Manual

configuration

R/W

E MASTER-SLAVE

Configuration

1 = MASTER

0 = SLAVE

R/W

D Port Type 1 = Multiport device

0 = Single port device

R/W

C 10GBASE-T Ability 1 = Advertise PHY as 10GBASE-T

capable

0 = Do not advertise PHY as

10GBASE-T capable

R/W

B:3 Reserved Internal reserved - do not modify

2 LD PMA Training

Reset Request

1 = Local device requests that Link

Partner reset PMA training PRBS

every frame

0 = Local device requests that Link

Partner run PMA training PRBS

continuously

R/W

Table 6.727 Autonegotiation 10GBASE-T Control Register: Address 7.20

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6.9.19 Autonegotiation 10GBASE-T Status Register: Address 7.21

1 LD Fast Retrain

Ability

1 = Advertise PHY as 10GBASE-T fast

retrain capable

0 = Do not advertise PHY as

10GBASE-T fast retrain capable

R/W

0 LD Loop Timing

Ability

1 = Advertise PHY as capable of loop

timing

0 = Do not advertise PHY as capable of

loop timing

R/W

Bit Name Description Type Default Note

F MASTER-SLAVE

Configuration Fault

1 = MASTER-SLAVE configuration fault LH

E MASTER-SLAVE

Configuration

Resolution

1 = Local PHY resolved to MASTER

0 = Local PHY resolved to SLAVE

D Local Receiver

Status

1 = Local receiver OK

0 = Local receiver not OK

RO Set by microcontroller

C Remote Receiver

Status

1 = Remote receiver OK

0 = Remote receiver not OK

RO Set by microcontroller

B Link Partner

10GBASE-T Ability

1 = Link partner is 10GBASE-T capable

0 = Link partner is not 10GBASE-T

capable

RO This bit is only valid when the Page

received bit 7.1.6 is set to 1.

A Link Partner Loop

Timing Ability

1 = Link partner is capable of loop timing

0 = Link partner is not capable of loop

timing

Table 6.728 Autonegotiation 10GBASE-T Status Register: Address 7.21

Bit Name Description Type Default Note

Table 6.727 Autonegotiation 10GBASE-T Control Register: Address 7.20

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6.9.20 Autonegotiation EEE Advertisement Register: Address 7.3C

9 Link Partner

Training Reset

Request

1 = Link partner has requested that PMA

PRBS training be reset every frame

0 = Link partner has requested that PMA

PRBS training run continuously.

8:2 Reserved Internal reserved - do not modify

1 Link Partner Fast

Retrain Ability

1 = Link partner is capable of

10GBASE-T fast retrain

0 = Link partner is not capable of

10GBASE-T fast retrain.

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 10GBASE-KR EEE 1 = Advertise that the 10GBASE-KR has

EEE capability

0 = Do not advertise that the

10GBASE-KR has EEE capability

R/W 0

5 10GBASE-KX4

EEE

1 = Advertise that the 10GBASE-KX4

has EEE capability

0 = Do not advertise that the

10GBASE-KX4 has EEE capability

R/W 0

4 1000BASE-KX EEE 1 = Advertise that the 1000BASE-KX

has EEE capability

0 = Do not advertise that the

1000BASE-KX has EEE capability

R/W 0

Table 6.729 Autonegotiation EEE Advertisement Register: Address 7.3C

Bit Name Description Type Default Note

Table 6.728 Autonegotiation 10GBASE-T Status Register: Address 7.21

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6.9.21 Autonegotiation EEE Link Partner Ability Register: Address 7.3D

3 10GBASE-T EEE 1 = Advertise that the 10GBASE-T has

EEE capability

0 = Do not advertise that the

10GBASE-T has EEE capability

R/W 1

2 1000BASE-T EEE 1 = Advertise that the 1000BASE-T has

EEE capability

0 = Do not advertise that the

1000BASE-T has EEE capability

R/W 1

1 100BASE-TX EEE 1 = Advertise that the 100BASE-TX has

EEE capability

0 = Do not advertise that the

100BASE-TX has EEE capability

R/W 0

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 Link Partner

10GBASE-KR EEE

1 = Link partner is advertising that its

10GBASE-KR has EEE capability

0 = Link partner is advertising that its

10GBASE-KR does not have EEE

capability

5 Link Partner

10GBASE-KX4

EEE

1 = Link partner is advertising that its

10GBASE-KX4 has EEE capability

0 = Link partner is advertising that its

10GBASE-KX4 does not have EEE

capability

Table 6.730 Autonegotiation EEE Link Partner Ability Register: Address 7.3D

Bit Name Description Type Default Note

Table 6.729 Autonegotiation EEE Advertisement Register: Address 7.3C

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4 Link Partner

1000BASE-KX EEE

1 = Link partner is advertising that its

1000BASE-KX has EEE capability

0 = Link partner is advertising that its

1000BASE-KX does not have EEE

capability

3 Link Partner

10GBASE-T EEE

1 = Link partner is advertising that its

10GBASE-T has EEE capability

0 = Link partner is advertising that its

10GBASE-T does not have EEE

capability

2 Link Partner

1000BASE-T EEE

1 = Link partner is advertising that its

1000BASE-T has EEE capability

0 = Link partner is advertising that its

1000BASE-T does not have EEE

capability

1 Link Partner

100BASE-TX EEE

1 = Link partner is advertising that its

100BASE-TX has EEE capability

0 = Link partner is advertising that its

100BASE-TX does not have EEE

capability

0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.730 Autonegotiation EEE Link Partner Ability Register: Address 7.3D

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6.9.22 KR0 Autonegotiation Control: Address 7.C200

6.9.23 KR0 Autonegotiation Status: Address 7.C201

Bit Name Description Type Default Note

F Reset 1 = Autonegotiation reset

0 = Normal operation

R/W

E:D Reserved 0 [1:0] Reserved for future use R/W

0x0

C Autonegotiation Enable 1 = Enable autonegotiation

0 = Disable autonegotiation

R/W

B:A Reserved 1 [1:0] Reserved for future use R/W

0x0

9 Autonegotiation Restart 1 = Restart autonegotiation

0 = Normal operation

R/W

8:0 Reserved 2 [8:0] Reserved for future use R/W

0x000

Table 6.731 KR0 Autonegotiation Control: Address 7.C200

Bit Name Description Type Default Note

F:A Reserved 0 [5:0] Reserved for future use R/W

0x00

9 Parallel Detection Fault 1 = Fault detected

0 = No fault detected

Table 6.732 KR0 Autonegotiation Status: Address 7.C201

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8:7 Reserved 1 [1:0] Reserved for future use R/W

0x0

6 Page Received 1 = A new DME page has been

received

0 = Normal operation

5 Autonegotiation

Complete

1 = Autonegotiation complete

0 = Normal operation

4 Reserved 2 Reserved for future use R/W

3 Autonegotiation Ability 1 = PHY is able to perform

autonegotiation

0 = PHY is not able to perform

autonegotiation

ROS 1 Always set as 1 as the local device has

autonegotiation ability.

2:1 Reserved 3 [1:0] Reserved for future use R/W

0x0

0 Link Partner

Autonegotiation Ability

1 = Link partner is able to perform

autonegotiation

0 = Link partner is not able to

perform autonegotiation

ROS 0

Bit Name Description Type Default Note

Table 6.732 KR0 Autonegotiation Status: Address 7.C201

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6.9.24 KR0 Autonegotiation Advertisement Word 1: Address 7.C210

Bit Name Description Type Default Note

F Next Page 1 = Next page ability

0 = Next page ability not supported

or not engaged

R/W

E Acknowledge 1 = Acknowledge

0 = No fault detected

R/W

0 The Acknowledge (Ack) is used by the

Autonegotiation function to indicate that a

device has successfully received its Link

Partner's Link Code Word.

D Remote Fault 1 = Remote fault R/W 0 The remote fault bit provides a standard

transport mechanism for the transmission

of simple fault information. When the RF bit

in the received base link code word is set to

1, the RF bit will be set to 1.

C Reserved 0 Reserved for future use R/W

B:A Pause Capability [1:0] Bit B: PAUSE operation for full

duplex links

Bit A: Asymmetric PAUSE

operation for full duplex links

R/W

0x0

Table 6.733 KR0 Autonegotiation Advertisement Word 1: Address 7.C210

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6.9.25 KR0 Autonegotiation Advertisement Word 2: Address 7.C211

9:5 Echoed Nonce [4:0] Echoed nonce R/W

0x00

4:0 Selector Field [4:0] This defines the device

compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

R/W

0x01 This field should always be set to 0x01 as

the PHY is only capable of handling 802.3

Ethernet.

Bit Name Description Type Default Note

F:8 Technology Ability Bits

A3 to A10 [7:0]

Reserved for future technology R/W

0x00

7 Technology Ability Bit A2 1 = 10GBASE-KR is supported

0 = 10GBASE-KR is not supported

R/W

6 Technology Ability Bit A1 1 = 10GBASE-KX4 is supported

0 = 10GBASE-KX4 is not

supported

R/W

5 Technology Ability Bit A0 1 = 10GBASE-KX is supported

0 = 10GBASE-KX is not supported

R/W

4:0 Transmitted Nonce [4:0] Transmitted nonce R/W

0x00

Table 6.734 KR0 Autonegotiation Advertisement Word 2: Address 7.C211

Bit Name Description Type Default Note

Table 6.733 KR0 Autonegotiation Advertisement Word 1: Address 7.C210

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6.9.26 KR0 Autonegotiation Advertisement Word 3: Address 7.C212

6.9.27 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213

Bit Name Description Type Default Note

F FEC Requested 1 = Enable 10GBASE-KR FEC

ability.

0 = Disable 10GBASE-KR FEC

ability.

R/W

E FEC Ability 1 = 10GBASE-KR PHY has FEC

capability.

0 = 10GBASE-KR PHY does not

have FEC capability.

R/W

D:0 Technology Ability Bits

A11 to A24 [D:0]

Reserved for future technology R/W

0x0000

Table 6.735 KR0 Autonegotiation Advertisement Word 3: Address 7.C212

Bit Name Description Type Default Note

F Link Partner Next Page 1 = Next page ability

0 = Next page ability not supported

or not engaged

E Link Partner

Acknowledge

1 = Acknowledge

0 = No fault detected

RO The Acknowledge (Ack) is used by the

Autonegotiation function to indicate that a

device has successfully received its Link

Partner's Link Code Word.

Table 6.736 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213

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D Link Partner Remote

Fault

1 = Remote fault RO The remote fault bit provides a standard

transport mechanism for the transmission

of simple fault information. When the RF bit

in the received base link code word is set to

1, the RF bit will be set to 1.

C Reserved 0 Reserved for future use RO

B:A Link Partner Pause

Capability [1:0]

Bit B: PAUSE operation for full

duplex links

Bit A: Asymmetric PAUSE

operation for full duplex links

9:5 Link Partner Echoed

Nonce [4:0]

Echoed nonce RO

4:0 Link Partner Selector

Field [4:0]

This defines the device

compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

RO This field should always be set to 0x01 as

the PHY is only capable of handling 802.3

Ethernet.

Bit Name Description Type Default Note

Table 6.736 KR0 Link Partner Autonegotiation Advertisement Word 1: Address 7.C213

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6.9.28 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214

Bit Name Description Type Default Note

F:8 Link Partner Technology

Ability bits A3 to A10

[7:0]

Reserved for future technology RO

7 Link Partner Technology

Ability bit A2

1 = 10GBASE-KR is supported

0 = 10GBASE-KR is not supported

6 Link Partner Technology

Ability bit A1

1 = 10GBASE-KX4 is supported

0 = 10GBASE-KX4 is not

supported

5 Link Partner Technology

Ability Bit A0

1 = 10GBASE-KX is supported

0 = 10GBASE-KX is not supported

4:0 Link Partner Transmitted

Nonce [4:0]

Transmitted nonce RO

Table 6.737 KR0 Link Partner Autonegotiation Advertisement Word 2: Address 7.C214

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6.9.29 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215

6.9.30 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216

Bit Name Description Type Default Note

F Link Partner FEC

Requested

1 = Enable 10GBASE-KR FEC

ability.

0 = Disable 10GBASE-KR FEC

ability.

E Link Partner FEC Ability 1 = 10GBASE-KR PHY has FEC

capability.

0 = 10GBASE-KR PHY does not

have FEC capability.

D:0 Link Partner Technology

Ability Bits A11 to A24

[D:0]

Reserved for future technology RO

Table 6.738 KR0 Link Partner Autonegotiation Advertisement Word 3: Address 7.C215

Bit Name Description Type Default Note

F:0 Extended Next Page 0

[F:0]

Extended next page bits [F:0] R/W

0x0000

Table 6.739 KR0 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C216

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6.9.31 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217

6.9.32 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218

6.9.33 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219

6.9.34 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A

Bit Name Description Type Default Note

F:0 Extended Next Page 1

[1F:10]

Extended next page bits [1F:10] R/W

0x0000

Table 6.740 KR0 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C217

Bit Name Description Type Default Note

F:0 Extended Next Page 2

[2F:20]

Extended next page bits [2F:20] R/W

0x0000

Table 6.741 KR0 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C218

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 0 [F:0]

Extended next page bits [F:0] RO

Table 6.742 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C219

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 1 [1F:10]

Extended next page bits [1F:10] RO

Table 6.743 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C21A

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6.9.35 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B

6.9.36 KR1 Autonegotiation Control: Address 7.C300

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 2 [2F:20]

Extended next page bits [2F:20] RO

Table 6.744 KR0 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C21B

Bit Name Description Type Default Note

F Reset 1 = Autonegotiation reset

0 = Normal operation

R/W

E:D Reserved 0 [1:0] Reserved for future use R/W

0x0

C Autonegotiation Enable 1 = Enable autonegotiation

0 = Disable autonegotiation

R/W

B:A Reserved 1 [1:0] Reserved for future use R/W

0x0

9 Autonegotiation Restart 1 = Restart autonegotiation

0 = Normal operation

R/W

8:0 Reserved 2 [8:0] Reserved for future use R/W

0x000

Table 6.745 KR1 Autonegotiation Control: Address 7.C300

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6.9.37 KR1 Autonegotiation Status: Address 7.C301

Bit Name Description Type Default Note

F:A Reserved 0 [5:0] Reserved for future use R/W

0x00

9 Parallel Detection Fault 1 = Fault detected

0 = No fault detected

8:7 Reserved 1 [1:0] Reserved for future use R/W

0x0

6 Page Received 1 = A new DME page has been

received

0 = Normal operation

5 Autonegotiation

Complete

1 = Autonegotiation complete

0 = Normal operation

4 Reserved 2 Reserved for future use R/W

3 Autonegotiation Ability 1 = PHY is able to perform

autonegotiation

0 = PHY is not able to perform

autonegotiation

ROS 1 Always set as 1 as the local device has

autonegotiation ability.

2:1 Reserved 3 [1:0] Reserved for future use R/W

0x0

0 Link Partner

Autonegotiation Ability

1 = Link partner is able to perform

autonegotiation

0 = Link partner is not able to

perform autonegotiation

ROS 0

Table 6.746 KR1 Autonegotiation Status: Address 7.C301

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6.9.38 KR1 Autonegotiation Advertisement Word 1: Address 7.C310

Bit Name Description Type Default Note

F Next Page 1 = Next page ability

0 = Next page ability not supported

or not engaged

R/W

E Acknowledge 1 = Acknowledge

0 = No fault detected

R/W

0 The Acknowledge (Ack) is used by the

Autonegotiation function to indicate that a

device has successfully received its Link

Partner's Link Code Word.

D Remote Fault 1 = Remote fault R/W 0 The remote fault bit provides a standard

transport mechanism for the transmission

of simple fault information. When the RF bit

in the received base link code word is set to

1, the RF bit will be set to 1.

C Reserved 0 Reserved for future use R/W

B:A Pause Capability [1:0] Bit B: PAUSE operation for full

duplex links

Bit A: Asymmetric PAUSE

operation for full duplex links

R/W

0x0

Table 6.747 KR1 Autonegotiation Advertisement Word 1: Address 7.C310

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6.9.39 KR1 Autonegotiation Advertisement Word 2: Address 7.C311

9:5 Echoed Nonce [4:0] Echoed nonce R/W

0x00

4:0 Selector Field [4:0] This defines the device

compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

R/W

0x01 This field should always be set to 0x01 as

the PHY is only capable of handling 802.3

Ethernet.

Bit Name Description Type Default Note

F:8 Technology Ability Bits

A3 to A10 [7:0]

Reserved for future technology R/W

0x00

7 Technology Ability Bit A2 1 = 10GBASE-KR is supported

0 = 10GBASE-KR is not supported

R/W

6 Technology Ability Bit A1 1 = 10GBASE-KX4 is supported

0 = 10GBASE-KX4 is not

supported

R/W

5 Technology Ability Bit A0 1 = 10GBASE-KX is supported

0 = 10GBASE-KX is not supported

R/W

4:0 Transmitted Nonce [4:0] Transmitted nonce R/W

0x00

Table 6.748 KR1 Autonegotiation Advertisement Word 2: Address 7.C311

Bit Name Description Type Default Note

Table 6.747 KR1 Autonegotiation Advertisement Word 1: Address 7.C310

463

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6.9.40 KR1 Autonegotiation Advertisement Word 3: Address 7.C312

6.9.41 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313

Bit Name Description Type Default Note

F FEC Requested 1 = Enable 10GBASE-KR FEC

ability.

0 = Disable 10GBASE-KR FEC

ability.

R/W

E FEC Ability 1 = 10GBASE-KR PHY has FEC

capability.

0 = 10GBASE-KR PHY does not

have FEC capability.

R/W

D:0 Technology Ability Bits

A11 to A24 [D:0]

Reserved for future technology R/W

0x0000

Table 6.749 KR1 Autonegotiation Advertisement Word 3: Address 7.C312

Bit Name Description Type Default Note

F Link Partner Next Page 1 = Next page ability

0 = Next page ability not supported

or not engaged

E Link Partner

Acknowledge

1 = Acknowledge

0 = No fault detected

RO The Acknowledge (Ack) is used by the

Autonegotiation function to indicate that a

device has successfully received its Link

Partner's Link Code Word.

Table 6.750 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313

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D Link Partner Remote

Fault

1 = Remote fault RO The remote fault bit provides a standard

transport mechanism for the transmission

of simple fault information. When the RF bit

in the received base link code word is set to

1, the RF bit will be set to 1.

C Reserved 0 Reserved for future use RO

B:A Link Partner Pause

Capability [1:0]

Bit B: PAUSE operation for full

duplex links

Bit A: Asymmetric PAUSE

operation for full duplex links

9:5 Link Partner Echoed

Nonce [4:0]

Echoed nonce RO

4:0 Link Partner Selector

Field [4:0]

This defines the device

compatibility:

0x00 = Reserved

0x01 = IEEE 802.3

0x02 = IEEE 802.9 ISLAN-16T

0x03 = IEEE 802.5

0x04 = IEEE 1394

0x05 -> 0x1F = Reserved

RO This field should always be set to 0x01 as

the PHY is only capable of handling 802.3

Ethernet.

Bit Name Description Type Default Note

Table 6.750 KR1 Link Partner Autonegotiation Advertisement Word 1: Address 7.C313

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6.9.42 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314

Bit Name Description Type Default Note

F:8 Link Partner Technology

Ability Bits A3 to A10

[7:0]

Reserved for future technology RO

7 Link Partner Technology

Ability Bit A2

1 = 10GBASE-KR is supported

0 = 10GBASE-KR is not supported

6 Link Partner Technology

Ability Bit A1

1 = 10GBASE-KX4 is supported

0 = 10GBASE-KX4 is not

supported

5 Link Partner Technology

Ability Bit A0

1 = 10GBASE-KX is supported

0 = 10GBASE-KX is not supported

4:0 Link Partner Transmitted

Nonce [4:0]

Transmitted nonce RO

Table 6.751 KR1 Link Partner Autonegotiation Advertisement Word 2: Address 7.C314

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6.9.43 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315

6.9.44 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316

Bit Name Description Type Default Note

F Link Partner FEC

Requested

1 = Enable 10GBASE-KR FEC

ability.

0 = Disable 10GBASE-KR FEC

ability.

E Link Partner FEC Ability 1 = 10GBASE-KR PHY has FEC

capability.

0 = 10GBASE-KR PHY does not

have FEC capability.

D:0 Link Partner Technology

Ability Bits A11 to A24

[D:0]

Reserved for future technology RO

Table 6.752 KR1 Link Partner Autonegotiation Advertisement Word 3: Address 7.C315

Bit Name Description Type Default Note

F:0 Extended Next Page 0

[F:0]

Extended next page bits [F:0] R/W

0x0000

Table 6.753 KR1 Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C316

467

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6.9.45 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317

6.9.46 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318

6.9.47 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319

6.9.48 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A

Bit Name Description Type Default Note

F:0 Extended Next Page 1

[1F:10]

Extended next page bits [1F:10] R/W

0x0000

Table 6.754 KR1 Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C317

Bit Name Description Type Default Note

F:0 Extended Next Page 2

[2F:20]

Extended next page bits [2F:20] R/W

0x0000

Table 6.755 KR1 Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C318

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 0 [F:0]

Extended next page bits [F:0] RO

Table 6.756 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 1: Address 7.C319

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 1 [1F:10]

Extended next page bits [1F:10] RO

Table 6.757 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 2: Address 7.C31A

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6.9.49 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B

6.9.50 Autonegotiation Vendor Provisioning 1: Address 7.C400

Bit Name Description Type Default Note

F:0 Link Partner Extended

Next Page 2 [2F:20]

Extended next page bits [2F:20] RO

Table 6.758 KR1 Link Partner Autonegotiation Extended Next Page Advertisement Word 3: Address 7.C31B

Bit Name Description Type Default Note

F 1000BASE-T Full Duplex

Ability

1 = Advertise PHY as 1000BASE-T

Full Duplex capable

0 = Do not advertise PHY as

1000BASE-T Full Duplex

capable

R/W

E 1000BASE-T Half

Duplex Ability

1 = Advertise PHY as 1000BASE-T

Half Duplex capable

0 = Do not advertise PHY as

1000BASE-T Half Duplex

capable

R/W

D Short-Reach 1 = Advertise PHY as operating in

short-reach mode

0 = Do not advertise PHY as

operating in short-reach mode

R/W

C AQRate Downshift

Capability

1 = Advertise PHY as supporting

AQRate fast-retrain downshift

mechanism

0 = Do not advertise PHY as

supporting AQRate fast-retrain

downshift mechanism

R/W

Table 6.759 Autonegotiation Vendor Provisioning 1: Address 7.C400

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B 5G 1 = Advertise PHY as supporting

0 = Do not advertise PHY as

supporting 5G

R/W

A 2.5G 1 = Advertise PHY as supporting

2.5G

0 = Do not advertise PHY as

supporting 2.55G

R/W

9:7 Reserved1 [2:0] Reserved for future use R/W

0x0

6 Exchange PHY ID

Information

1 = Exchange PHY ID Information R/W

5 User Provided

Autonegotiation Data

1 = User provides the next page or

extended next page data directly

(7.16 -> 7.18), and the

configuration info in 7.20 and

7.C400 is ignored.

0 = Construct the correct

autonegotiation words based on

the register settings of 7.10, 7.20,

and 7.C400

R/W

0 If this bit is set, the PHY will attempt to use

the user provided autonegotiation words. If

there is a mismatch (such as a legacy

1GBASE-T device attempting connect), the

PHY will then attempt to construct a new

set of autonegotiation words from the data

provided in these words.

Otherwise, the PHY will construct the

correct autonegotiation words based on the

provisioned values.

4 Automatic Downshift

Enable

1 = Enable automatic downshift

0 = Manual downshift

R/W

3:0 Retry Attempts Before

Downshift [3:0]

Number of retry attempts before

downshift

R/W

0x4 If Automatic Downshifting is enabled, this is

the number of retry attempts the PHY will

make to connect at the maximum mutually

acceptable rate, before removing this rate

from the list and trying the next lower rate.

Bit Name Description Type Default Note

Table 6.759 Autonegotiation Vendor Provisioning 1: Address 7.C400

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6.9.51 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410

Bit Name Description Type Default Note

F:D SERDES

Start-Up Mode

[2:0]

The state up mode of the MAC interface:

0x0 = Selected 10G interface on with

automatic rate select

0x1 = Reserved

0x2 = SGMII on with automatic rate

select and SGMII autonegotiation

(XSGMII mode)

0x3 = USXGMII Mode

0x4 = 1000BASE-X on with automatic

rate select and no SGMII

autonegotiation

0x5 = Reserved

0x6 = All interfaces off with automatic

rate select

0x7 = Reserved

R/W

0x0 This sets the start-up mode for the MAC

interface. In all scenarios, the AQR405 sets

the interface rate based on the autonegotiated

line rate. The interface selection controls are in

4.C441.

NOTE! USXGMII requires KR to be selected in

4.C441, and when selected it will be used for

all rates.

C:B Reserved

Provisioning 0

[1:0]

Reserved for future use R/W

0x0

A:8 Semi-Cross Link

Attempt Period

[2:0]

Number of failed link attempts before

trying semi cross

R/W

0x0 Set to zero (0) to disable semi-cross. Set to

0x7 to always use semi-cross.

7 WoL Mode 0 = 100BASE-TX

1 = 1000BASE-T

R/W

0This bit indicates whether the AQR405 is going to go into

100BASE-TX or 1000BASE-T Wake-On-LAN operation.

6 WoL Enable 1 = Enable Wake-On-LAN operation

0 = Normal Operation

R/W

0Setting this bit enables Wake-On-LAN operation. In this state,

power is minimized by turning all interfaces except the MDI receive

path and the MDIO interface off.

Table 6.760 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410

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5:2 Extra Page

Count [3:0]

Number of extra pages to send at end of

auto-negotiation sequence when link

partner is legacy gigabit PHY.

R/W

0x0 Intervals between pages for GbE PHYs may

be much longer. When this is the case, the link

partner may still be in auto-negotiation when

the AQR405 has started training. This may

confuse the link partner MDI/MDI-X state

machine. Sending extra pages seems to solve

this problem.

1:0 MDI / MDI-X

Control [1:0]

0x0 = Automatic MDI / MDI-X operation

0x1 = Manual MDI

0x2 = Manual MDI-X

0x3 = Reserved

R/W

0x0 These bits are used to force a manual MDI or

MDI-X configuration

Bit Name Description Type Default Note

Table 6.760 Autonegotiation Reserved Vendor Provisioning 1: Address 7.C410

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6.9.52 Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411

Bit Name Description Type Default Note

F:C Autonegotiation

Timeout [3:0]

The length of time in (seconds*2) before

autonegotiation restarts. Valueof zero

indicates there is no timeout.

R/W

0x0 These bits control the use of autonegotiation

timeout watchdog during the Arbit state

machine

B Autonegotiation

Timeout Mode

0 = Enable timeout for all

autonegotiation behavior

1 = Enable timeout only if the following

are enabled: LPLU, downshifting

R/W

0 The timeout behavior can be described as

follows:

Bits F:C = non-zero, Bit B = 0: Timeout exists

for all autonegotiation behavior, including

LPLU and if downshift is enabled.

Bits F:C = 0, Bit B = 0: No timeout enabled

Bits F:C = non-zero, Bit B = 1: If we are in LPLU

or downshift is enabled, timeout exists. If we

are not in LPLU or downshift is not enabled,

there is no timeout.

Bits F:C = 0, Bit B = 1: If we are in LPLU or

downshift is enabled, there is no timeout. If we

are not in LPLU or downshift is not enabled,

there is no timeout. IE, there is no timeout.

A:0 Reserved Internal reserved - do not modify

Table 6.761 Autonegotiation Reserved Vendor Provisioning 2: Address 7.C411

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6.9.53 Autonegotiation Vendor Status 1: Address 7.C800

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3:1 Connect Rate

[2:0]

The rate the PHY connected or

attempting to connect at:

0x5 = 5G

0x4 = 2.5G

0x3 = 10GBASE-T

0x2 = 1000BASE-T

0x1 = 100BASE-TX

0x0 = 10BASE-T

RO This field is used in conjunction with

Connection State in "Autonegotiation

Reserved Vendor Status 1: Address 7.C810"

to indicated the rate the PHY is connected or

attempting to connect at.

0 Connect Type The duplex method the PHY connected

or attempting to connect at:

1 = Full Duplex

0 = Half-Duplex

RO This field is used in conjunction with

Connection State in "Autonegotiation

Reserved Vendor Status 1: Address 7.C810"

to indicated the duplex method the PHY is

connected or attempting to connect at.

Table 6.762 Autonegotiation Vendor Status 1: Address 7.C800

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AQR405 Revision 0.11 - January 5, 2015

6.9.54 Autonegotiation Reserved Vendor Status 1: Address 7.C810

Bit Name Description Type Default Note

F Energy On Line 1 = Energy detected on line

0 = No energy detected on line

RO This bit is used to indicate that the PHY has

detected energy on the line. Specifically, when

MDI/MDI-X resolution has completed, this bit is

true. This bit will be set false before entering

autonegotiation.

E Device Present 1 = Far-end Ethernet device present

0 = No far-end Ethernet device detected

RO If true, a far-end Ethernet device exists, as

valid link pulses have been detected in the

most recent autonegotiation session, or a valid

Ethernet connection has been established. If

false, no connection is established, and the

most recent attempt at autonegotiation failed

to detect any valid link pulses. Specifically,

when MDI/MDI-X resolution has completed,

this bit is true. This bit will be set false before

entering autonegotiation.

D:9 Connection

State [4:0]

The current state of the connection:

0x00 = Inactive (i.e. high-impedance)

0x01 = Cable diagnostics

0x02 = Autonegotiation

0x03 = Training (10G, 5G, 2.5G and 1G

only)

0x04 = Connected

0x05 = Fail (Autonegotiation Break Link)

0x06 = Test Mode

0x07 = Loopback Mode

0x08 = Low Power Mode

0x09 = Connected Wake-On-LAN Mode

0x0A = System Calibrating

0x0B = Cable Disconnected

0x0C -> 0x1E = Reserved

0x1F = Invalid

RO This field is used in conjunction with Connect

Rate and Connect Type in "Autonegotiation

Vendor Status 1: Address 7.C800" to indicated

the current state the PHY is in.

Table 6.763 Autonegotiation Reserved Vendor Status 1: Address 7.C810

475

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6.9.55 Autonegotiation Reserved Vendor Status 2: Address 7.C811

8 MDI/MDI-X 0 = MDI

1 = MDI-X

RO When autonegotiation is completed, this

made as an MDI or MDI-X connection.

7 Duplicate Link

Partner

Autonegotiation

Ability

Link Partner is capable of

Autonegotiation.

RO This is a duplicate of the bit at 07.0001.0.

6:2 Reserved Status

1 [6:2]

Reserved for future use RO

1 Receive PAUSE

Resolution

1 = Receive PAUSE Enabled

0 = Receive PAUSE Disabled

PAUSE resolution from 28B-3

0 Transmit

PAUSE

Resolution

1 = Transmit PAUSE Enabled

0 = Transmit PAUSE Disabled

Bit Name Description Type Default Note

F:0 Autonegotiation

Attempts [F:0]

The number of autonegotiation attempts

since the last successful connection (or

power-up)

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset, or the

completion of a successful connection.

Table 6.764 Autonegotiation Reserved Vendor Status 2: Address 7.C811

Bit Name Description Type Default Note

Table 6.763 Autonegotiation Reserved Vendor Status 1: Address 7.C810

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6.9.56 Autonegotiation Reserved Vendor Status 3: Address 7.C812

6.9.57 Autonegotiation Reserved Vendor Status 4: Address 7.C813

6.9.58 Autonegotiation Reserved Vendor Status 5: Address 7.C814

Bit Name Description Type Default Note

F Link Pulse

Detected Status

1 = Link Pulse Detected

0 = Link Pulse not Detected

E:0 Reserved State

3 [E:0]

Reserved for future use RO

Table 6.765 Autonegotiation Reserved Vendor Status 3: Address 7.C812

Bit Name Description Type Default Note

F:0 Autonegotiation

Restarts

Handled [F:0]

The number of line-side autonegotiation

restart commands received.

RO This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

Table 6.766 Autonegotiation Reserved Vendor Status 4: Address 7.C813

Bit Name Description Type Default Note

F:0 Autonegotiation

Attempts Since

Reset [F:0]

The number of autonegotiation attempts

since the last PHY reset (or power-up).

RO Increments when the line-side goes back to

‘break-link’ state and then re-negotiates.

This is a rolling counter (i.e. upon saturation it

reverts to zero). It is cleared upon reset.

Table 6.767 Autonegotiation Reserved Vendor Status 5: Address 7.C814

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6.9.59 Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00

6.9.60 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3 Autonegotiation

Completed For

Non-supported Rate

1 = Autonegotiation has completed

for a rate that is not supported

by the AQR405

LH This means that the AQR405 has

completed autonegotiation, and was

unable to agree on a rate that both could

operate at. Indication should be ignored in

case of Master/Slave resolution fault

2 Autonegotiation

Completed for Supported

Rate

1 = Autonegotiation has completed

successfully for a rate that is

supported by the AQR405

1 Automatic Downshift 1 = Automatic downshift has

occurred

0 Connection State

Change

1 = The connection state has

changed

LH This interrupt indicates a change in

Connection State [D:B] in "Autonegotiation

Reserved Vendor Status 1: Address

7.C810" on page 474. Note that this

indicates any state change, versus

7.CC01.0 which indicates a connect or

disconnect event.

Table 6.768 Autonegotiation Transmit Vendor Alarms 1: Address 7.CC00

Bit Name Description Type Default Note

F Link Pulse Detect 1 = Link Pulse Detected LH

Table 6.769 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01

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6.9.61 Autonegotiation Standard Interrupt Mask 1: Address 7.D000

E:1 Reserved Vendor

Alarms 2 [D:0]

Reserved for future use LH

0 Link Connect /

Disconnect

1 = MDI Link has either connected

or disconnected

LH This indicates whether the link has achieved a

connect state, or was in a connect state and

disconnected.

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 Parallel Detection

Fault Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

8:7 Reserved Internal reserved - do not modify

6 Extended Next Page

Received Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5 Reserved Internal reserved - do not modify

4 Remote Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 Reserved Internal reserved - do not modify

2 Link Status Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1:0 Reserved Internal reserved - do not modify

Table 6.770 Autonegotiation Standard Interrupt Mask 1: Address 7.D000

Bit Name Description Type Default Note

Table 6.769 Autonegotiation Transmit Vendor Alarms 2: Address 7.CC01

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6.9.62 Autonegotiation Standard Interrupt Mask 2: Address 7.D001

6.9.63 Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400

Bit Name Description Type Default Note

F MASTER-SLAVE

Configuration Fault

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E:0 Reserved Internal reserved - do not modify

Table 6.771 Autonegotiation Standard Interrupt Mask 2: Address 7.D001

Bit Name Description Type Default Note

F:4 Reserved Internal reserved - do not modify

3 Autonegotiation

Completed For

Non-supported Rate

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2 Autonegotiation

Completed for Supported

Rate Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 Automatic Downshift

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Connection State

Change Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.772 Autonegotiation Transmit Vendor Interrupt Mask 1: Address 7.D400

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6.9.64 Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401

6.9.65 Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402

Bit Name Description Type Default Note

F Link Pulse Detect

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E:1 Reserved Vendor

Alarms 2 Mask [D:0]

Reserved for future use R/W

0x0000

0 Link Connect /

Disconnect Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.773 Autonegotiation Transmit Vendor Interrupt Mask 2: Address 7.D401

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.774 Autonegotiation Transmit Vendor Interrupt Mask 3: Address 7.D402

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6.9.66 Autonegotiation Receive Link Partner Status 1: Address 7.E820

Bit Name Description Type Default Note

F Link Partner

1000BASE-T

Full Duplex

Ability

1 = Link Partner is 1000BASE-T Full

Duplex capable

0 = Link Partner is not 1000BASE-T Full

Duplex capable

E Link Partner

1000BASE-T

Half Duplex

Ability

1 = Link Partner is 1000BASE-T

Half-Duplex capable

0 = Link Partner is not 1000BASE-T

Half-Duplex capable

D Link Partner

Short-Reach

1 = Link Partner is operating in

short-reach mode

0 = Link Partner is not operating in

short-reach mode

C Link Partner

AQRate

Downshift

Capability

1 = Link Partner PHY supports AQRate

fast-retrain downshift mechanism

0 = Link Partner PHY does not support

AQRate fast-retrain downshift

mechanism

R/W

B Link Partner 5G 1 = Link Partner PHY is 5G capable

0 = Link Partner PHY is not 5G capable

R/W

A Link Partner

2.5G

1 = Link Partner PHY is 5G capable

0 = Link Partner PHY is not 5G capable

R/W

9:3 Reserved2 [6:0] Reserved for future use RO

2 Aquantia Link

Partner

1 = Link Partner is an Aquantia PHY

0 = Link Partner is not an Aquantia PHY

1:0 Reserved Internal reserved - do not modify

Table 6.775 Autonegotiation Receive Link Partner Status 1: Address 7.E820

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6.9.67 Autonegotiation Receive Link Partner Status 2: Address 7.E821

6.9.68 Autonegotiation Receive Link Partner Status 3: Address 7.E822

6.9.69 Autonegotiation Receive Link Partner Status 4: Address 7.E823

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.776 Autonegotiation Receive Link Partner Status 2: Address 7.E821

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.777 Autonegotiation Receive Link Partner Status 3: Address 7.E822

Bit Name Description Type Default Note

F:8 Link Partner

Firmware Major

Revision

Number [7:0]

[F:8] = Link partner firmware major

revision number

RO Only the lower six bits of major and minor

firmware revision are exchanged in

autonegotiation when the PHYID message is

sent. Consequently the upper 2 bits of the

major and minor revision should always be

zero.

7:0 Link Partner

Firmware Minor

Revision

Number [7:0]

[7:0] = Link partner firmware minor

revision number

Table 6.778 Autonegotiation Receive Link Partner Status 4: Address 7.E823

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6.9.70 Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830

6.9.71 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831

Bit Name Description Type Default Note

F:C Link

Attempts[3:0]

Number of attempts needed to establish

current link

Once a link has been established, save the

total number of auto-negotiation and training

sequence passes.

B:9 Link Partner

PHY Tag [2:0]

When the link partner is Aquantia and

PHY ID pages have been exchanged

this field contains the vendor specific link

partner PHY tag value

This field is only valid if the link partner is

Aquantia and PHY ID link pages have been

exchanged during Autonegotiation.

8:0 Reserved

Receive Status 1

[8:0]

Reserved for future use RO

Table 6.779 Autonegotiation Receive Reserved Vendor Status 1: Address 7.E830

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D Autonegotiation

Protocol Error

State

1 = Link partner has violated the

Autonegotation protocol

RO This is the state bit associated with

"Autonegotiation Protocol Error" (See

“Autonegotiation Receive Vendor Alarms 2:

Address 7.EC01” on page 485.)

Table 6.780 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831

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6.9.72 Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832

6.9.73 Autonegotiation Receive Vendor Alarms 1: Address 7.EC00

C FLP Idle Error

State

1 = No FLP Burst has been seen for 50

milliseconds forcing the receive state

machine back to the Idle state

RO This is the state bit associated with "FLP Idle

Error" (See “Autonegotiation Receive Vendor

Alarms 2: Address 7.EC01” on page 485.)

B:0 Reserved

Receive State 2

[B:0]

Reserved for future use RO This is the state bit associated with "Reserved

Receive Vendor Alarms 2 [B:0]" (See

“Autonegotiation Receive Vendor Alarms 2:

Address 7.EC01” on page 485.)

Bit Name Description Type Default Note

F:1 Reserved

Receive State 3

[E:0]

Reserved for future use RO

0 Link Partner

AFR Enabled

1 = The link partner has Aquantia Fast

Reframe capability enabled

Table 6.781 Autonegotiation Receive Reserved Vendor Status 3: Address 7.E832

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.782 Autonegotiation Receive Vendor Alarms 1: Address 7.EC00

Bit Name Description Type Default Note

Table 6.780 Autonegotiation Receive Reserved Vendor Status 2: Address 7.E831

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6.9.74 Autonegotiation Receive Vendor Alarms 2: Address 7.EC01

6.9.75 Autonegotiation Receive Vendor Alarms 3: Address 7.EC02

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D Autonegotiation

Protocol Error

1 = Link partner has violated the

Autonegotation protocol

LH If the Arbiter state machine detects a protocol

violation, the Autonegotiation process resets

itself and goes back to the “break link” state.

C FLP Idle Error 1 = No FLP Burst has been seen for

50 milliseconds forcing the

receive state machine back to

the Idle state

LH Once FLP bursts are detected on any receive

channel, they must keep coming. If no burst

has been detected for a period of 50

milliseconds, the Autonegotiation process

resets itself and goes back to the “break link”

state.

B:0 Reserved Receive

Vendor Alarms 2 [B:0]

Reserved for future use LH

Table 6.783 Autonegotiation Receive Vendor Alarms 2: Address 7.EC01

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 10BASE-T Device

Detect

0 = 10BASE-T device detected LL This bit indicates that the detected far-end

device is 10BASE-T when it is 0. This bit is 1

when link pulses are no longer received

1:0 Reserved Internal reserved - do not modify

Table 6.784 Autonegotiation Receive Vendor Alarms 3: Address 7.EC02

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6.9.76 Autonegotiation Receive Vendor Alarms 4: Address 7.EC03

6.9.77 Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400

6.9.78 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401

Bit Name Description Type Default Note

F:1 Reserved Receive

Vendor Alarms 4 [E:0]

Reserved LH

0 100BASE-TX Parallel

Detect

1 = 100BASE-TX parallel event

detection occurred

Table 6.785 Autonegotiation Receive Vendor Alarms 4: Address 7.EC03

Bit Name Description Type Default Note

F:0 Reserved Receive

Vendor Alarms 1 Mask

[F:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0000

Table 6.786 Autonegotiation Receive Vendor Interrupt Mask 1: Address 7.F400

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D Autonegotiation

Protocol Error Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.787 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401

487

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6.9.79 Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402

6.9.80 Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403

C FLP Idle Error Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

B:0 Reserved Receive

Vendor Alarms 2

Mask [B:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x000

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2 10BASE-T Device

Detect Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1:0 Reserved Internal reserved - do not modify

Table 6.788 Autonegotiation Receive Vendor Interrupt Mask 3: Address 7.F402

Bit Name Description Type Default Note

F:1 Reserved Receive

Vendor Alarms 4

Mask [E:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0000

0 100BASE-TX Parallel

Detect Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.789 Autonegotiation Receive Vendor Interrupt Mask 4: Address 7.F403

Bit Name Description Type Default Note

Table 6.787 Autonegotiation Receive Vendor Interrupt Mask 2: Address 7.F401

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6.9.81 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00

Bit Name Description Type Default Note

F Standard Alarms 1

Interrupt

1 = Interrupt RO An interrupt was generated from status

Status 1: Address 7.1” on page 434.) and

the corresponding mask register (See

“Autonegotiation Standard Interrupt Mask

1: Address 7.D000” on page 478.).

E Standard Alarms 2

Interrupt

1 = Interrupt RO An interrupt was generated from status

Status Register: Address 7.21” on

page 446.) and the corresponding mask

Interrupt Mask 2: Address 7.D001” on

page 479.).

D:B Reserved Internal reserved - do not modify

A Vendor Specific

Alarms 1 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 1: Address 7.CC00” on

page 477.) and the corresponding mask

Vendor Interrupt Mask 1: Address 7.D400”

on page 479.).

9 Vendor Specific

Alarms 2 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 2: Address 7.CC01” on

page 477.) and the corresponding mask

Vendor Interrupt Mask 2: Address 7.D401”

on page 480.).

8:4 Reserved Internal reserved - do not modify

Table 6.790 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00

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3 Vendor Specific Rx

Alarms 1 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 1: Address 7.EC00” on

page 484.) and the corresponding mask

Vendor Interrupt Mask 1: Address 7.F400”

on page 486.).

2 Vendor Specific Rx

Alarms 2 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 2: Address 7.EC01” on

page 485.) and the corresponding mask

Vendor Interrupt Mask 2: Address 7.F401”

on page 486.).

1 Vendor Specific Rx

Alarms 3 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 3: Address 7.EC02” on

page 485.) and the corresponding mask

Vendor Interrupt Mask 3: Address 7.F402”

on page 487.).

0 Vendor Specific Rx

Alarms 4 Interrupt

1 = Interrupt RO An interrupt was generated from status

Vendor Alarms 4: Address 7.EC03” on

page 486.) and the corresponding mask

Vendor Interrupt Mask 4: Address 7.F403”

on page 487.).

Bit Name Description Type Default Note

Table 6.790 Autonegotiation Vendor Global Interrupt Flags 1: Address 7.FC00

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6.10 100BASE-TX and 1000BASE-T Registers

6.10.1 GbE Standard Device Identifier 1: Address 1D.2

6.10.2 GbE Standard Device Identifier 2: Address 1D.3

6.10.3 GbE Standard Devices in Package 1: Address 1D.5

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.791 GbE Standard Device Identifier 1: Address 1D.2

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.792 GbE Standard Device Identifier 2: Address 1D.3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

Table 6.793 GbE Standard Devices in Package 1: Address 1D.5

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6.10.4 GbE Standard Vendor Devices in Package 2: Address 1D.6

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no MAC

XAUI interface in the AQR405.

4 Control Present 1 = Control is present in package

0 = Control is not present in package

ROS 1 This is always set to 1 as there is a PHY XAUI

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the global control registers.

Table 6.794 GbE Standard Vendor Devices in Package 2: Address 1D.6

Bit Name Description Type Default Note

Table 6.793 GbE Standard Devices in Package 1: Address 1D.5

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6.10.5 GbE Standard Status 2: Address 1D.8

6.10.6 GbE Standard Package Identifier 1: Address 1D.E

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the global control registers.

C:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 2, as the Control is

present in the AQR405.

D:0 Reserved Internal reserved - do not modify

Table 6.795 GbE Standard Status 2: Address 1D.8

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.796 GbE Standard Package Identifier 1: Address 1D.E

Bit Name Description Type Default Note

Table 6.794 GbE Standard Vendor Devices in Package 2: Address 1D.6

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6.10.7 GbE Standard Package Identifier 2: Address 1D.F

6.10.8 GbE PHY SGMII Test Control : Address 1D.C282

6.10.9 GbE PHY WoL Control 1: Address 1D.C300

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.797 GbE Standard Package Identifier 2: Address 1D.F

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SGMII Test

Pattern Injection

Enable

1 = Inject test pattern

0 = Normal mode

R/W 0

Table 6.798 GbE PHY SGMII Test Control : Address 1D.C282

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.799 GbE PHY WoL Control 1: Address 1D.C300

495

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6.10.10 GbE PHY WoL Control 2: Address 1D.C301

6.10.11 GbE PHY WoL Control 3: Address 1D.C302

6.10.12 GbE PHY WoL Control 4: Address 1D.C303

6.10.13 GbE PHY WoL Control 5: Address 1D.C304

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.800 GbE PHY WoL Control 2: Address 1D.C301

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.801 GbE PHY WoL Control 3: Address 1D.C302

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.802 GbE PHY WoL Control 4: Address 1D.C303

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.803 GbE PHY WoL Control 5: Address 1D.C304

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6.10.14 GbE PHY WoL Control 6: Address 1D.C305

6.10.15 GbE PHY WoL Control 7: Address 1D.C306

6.10.16 GbE PHY WoL Control 8: Address 1D.C307

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Wake Up Frame

Detection

Enable

Wake Up Frame Detection Enable R/W 0

Table 6.804 GbE PHY WoL Control 6: Address 1D.C305

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 0

[F:0]

Wake Up Frame Pattern Mask 0 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.805 GbE PHY WoL Control 7: Address 1D.C306

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 1

[F:0]

Wake Up Frame Pattern Mask 0 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.806 GbE PHY WoL Control 7: Address 1D.C306

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6.10.17 GbE PHY WoL Control 9: Address 1D.C308

6.10.18 GbE PHY WoL Control 10: Address 1D.C309

6.10.19 GbE PHY WoL Control 11: Address 1D.C30A

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 2

[F:0]

Wake Up Frame Pattern Mask 0 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.807 GbE PHY WoL Control 9: Address 1D.C308

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 3

[F:0]

Wake Up Frame Pattern Mask 0 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.808 GbE PHY WoL Control 10: Address 1D.C309

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 4

[F:0]

Wake Up Frame Pattern Mask 0 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.809 GbE PHY WoL Control 11: Address 1D.C30A

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6.10.20 GbE PHY WoL Control 12: Address 1D.C30B

6.10.21 GbE PHY WoL Control 13: Address 1D.C30C

6.10.22 GbE PHY WoL Control 14: Address 1D.C30D

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 5

[F:0]

Wake Up Frame Pattern Mask 0 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.810 GbE PHY WoL Control 12: Address 1D.C30B

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 6

[F:0]

Wake Up Frame Pattern Mask 0 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.811 GbE PHY WoL Control 13: Address 1D.C30C

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 0 Word 7

[F:0]

Wake Up Frame Pattern Mask 0 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 0 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.812 GbE PHY WoL Control 14: Address 1D.C30D

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6.10.23 GbE PHY WoL Control 15: Address 1D.C30E

6.10.24 GbE PHY WoL Control 16: Address 1D.C30F

6.10.25 GbE PHY WoL Control 17: Address 1D.C310

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 0 Word 0

[F:0]

Wake Up Frame CRC 0 bits 15:0 R/W 0x0000

Table 6.813 GbE PHY WoL Control 15: Address 1D.C30E

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 0 Word 1

[F:0]

Wake Up Frame CRC 0 bits 31:16 R/W 0x0000

Table 6.814 GbE PHY WoL Control 16: Address 1D.C30F

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 0

[F:0]

Wake Up Frame Pattern Mask 1 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.815 GbE PHY WoL Control 17: Address 1D.C310

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6.10.26 GbE PHY WoL Control 18: Address 1D.C311

6.10.27 GbE PHY WoL Control 19: Address 1D.C312

6.10.28 GbE PHY WoL Control 20: Address 1D.C313

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 1

[F:0]

Wake Up Frame Pattern Mask 1 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.816 GbE PHY WoL Control 18: Address 1D.C311

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 2

[F:0]

Wake Up Frame Pattern Mask 1 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.817 GbE PHY WoL Control 19: Address 1D.C312

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 3

[F:0]

Wake Up Frame Pattern Mask 1 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.818 GbE PHY WoL Control 20: Address 1D.C313

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6.10.29 GbE PHY WoL Control 21: Address 1D.C314

6.10.30 GbE PHY WoL Control 22: Address 1D.C315

6.10.31 GbE PHY WoL Control 23: Address 1D.C316

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 4

[F:0]

Wake Up Frame Pattern Mask 1 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.819 GbE PHY WoL Control 21: Address 1D.C314

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 5

[F:0]

Wake Up Frame Pattern Mask 1 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.820 GbE PHY WoL Control 22: Address 1D.C315

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 6

[F:0]

Wake Up Frame Pattern Mask 1 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.821 GbE PHY WoL Control 23: Address 1D.C316

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6.10.32 GbE PHY WoL Control 24: Address 1D.C317

6.10.33 GbE PHY WoL Control 25: Address 1D.C318

6.10.34 GbE PHY WoL Control 26: Address 1D.C319

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 1 Word 7

[F:0]

Wake Up Frame Pattern Mask 1 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 1 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.822 GbE PHY WoL Control 24: Address 1D.C317

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 1 Word 0

[F:0]

Wake Up Frame CRC 1 bits 15:0 R/W 0x0000

Table 6.823 GbE PHY WoL Control 25: Address 1D.C318

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 1 Word 1

[F:0]

Wake Up Frame CRC 1 bits 31:16 R/W 0x0000

Table 6.824 GbE PHY WoL Control 26: Address 1D.C319

503

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6.10.35 GbE PHY WoL Control 27: Address 1D.C31A

6.10.36 GbE PHY WoL Control 28: Address 1D.C31B

6.10.37 GbE PHY WoL Control 29: Address 1D.C31C

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 0

[F:0]

Wake Up Frame Pattern Mask 2 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.825 GbE PHY WoL Control 27: Address 1D.C31A

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 1

[F:0]

Wake Up Frame Pattern Mask 2 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.826 GbE PHY WoL Control 28: Address 1D.C31B

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 2

[F:0]

Wake Up Frame Pattern Mask 2 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.827 GbE PHY WoL Control 29: Address 1D.C31C

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AQR405 Revision 0.11 - January 5, 2015

6.10.38 GbE PHY WoL Control 30: Address 1D.C31D

6.10.39 GbE PHY WoL Control 31: Address 1D.C31E

6.10.40 GbE PHY WoL Control 32: Address 1D.C31F

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 3

[F:0]

Wake Up Frame Pattern Mask 2 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.828 GbE PHY WoL Control 30: Address 1D.C31D

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 4

[F:0]

Wake Up Frame Pattern Mask 2 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.829 GbE PHY WoL Control 31: Address 1D.C31E

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 5

[F:0]

Wake Up Frame Pattern Mask 2 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.830 GbE PHY WoL Control 32: Address 1D.C31F

505

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6.10.41 GbE PHY WoL Control 33: Address 1D.C320

6.10.42 GbE PHY WoL Control 34: Address 1D.C321

6.10.43 GbE PHY WoL Control 35: Address 1D.C322

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 6

[F:0]

Wake Up Frame Pattern Mask 2 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.831 GbE PHY WoL Control 33: Address 1D.C320

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 2 Word 7

[F:0]

Wake Up Frame Pattern Mask 2 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 2 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.832 GbE PHY WoL Control 34: Address 1D.C321

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 2 Word 0

[F:0]

Wake Up Frame CRC 2 bits 15:0 R/W 0x0000

Table 6.833 GbE PHY WoL Control 35: Address 1D.C322

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AQR405 Revision 0.11 - January 5, 2015

6.10.44 GbE PHY WoL Control 36: Address 1D.C323

6.10.45 GbE PHY WoL Control 37: Address 1D.C324

6.10.46 GbE PHY WoL Control 38: Address 1D.C325

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 2 Word 1

[F:0]

Wake Up Frame CRC 2 bits 31:16 R/W 0x0000

Table 6.834 GbE PHY WoL Control 36: Address 1D.C323

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 0

[F:0]

Wake Up Frame Pattern Mask 3 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.835 GbE PHY WoL Control 37: Address 1D.C324

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 1

[F:0]

Wake Up Frame Pattern Mask 3 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.836 GbE PHY WoL Control 38: Address 1D.C325

507

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6.10.47 GbE PHY WoL Control 39: Address 1D.C326

6.10.48 GbE PHY WoL Control 40: Address 1D.C327

6.10.49 GbE PHY WoL Control 41: Address 1D.C328

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 2

[F:0]

Wake Up Frame Pattern Mask 3 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.837 GbE PHY WoL Control 39: Address 1D.C326

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 3

[F:0]

Wake Up Frame Pattern Mask 3 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.838 GbE PHY WoL Control 40: Address 1D.C327

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 4

[F:0]

Wake Up Frame Pattern Mask 3 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.839 GbE PHY WoL Control 41: Address 1D.C328

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6.10.50 GbE PHY WoL Control 42: Address 1D.C329

6.10.51 GbE PHY WoL Control 43: Address 1D.C32A

6.10.52 GbE PHY WoL Control 44: Address 1D.C32B

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 5

[F:0]

Wake Up Frame Pattern Mask 3 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.840 GbE PHY WoL Control 42: Address 1D.C329

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 6

[F:0]

Wake Up Frame Pattern Mask 3 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.841 GbE PHY WoL Control 43: Address 1D.C32A

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 3 Word 7

[F:0]

Wake Up Frame Pattern Mask 3 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 3 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.842 GbE PHY WoL Control 44: Address 1D.C32B

509

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6.10.53 GbE PHY WoL Control 45: Address 1D.C32C

6.10.54 GbE PHY WoL Control 46: Address 1D.C32D

6.10.55 GbE PHY WoL Control 47: Address 1D.C32E

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 3 Word 0

[F:0]

Wake Up Frame CRC 3 bits 15:0 R/W 0x0000

Table 6.843 GbE PHY WoL Control 45: Address 1D.C32C

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 3 Word 1

[F:0]

Wake Up Frame CRC 3 bits 31:16 R/W 0x0000

Table 6.844 GbE PHY WoL Control 46: Address 1D.C32D

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 0

[F:0]

Wake Up Frame Pattern Mask 4 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.845 GbE PHY WoL Control 47: Address 1D.C32E

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6.10.56 GbE PHY WoL Control 48: Address 1D.C32F

6.10.57 GbE PHY WoL Control 49: Address 1D.C330

6.10.58 GbE PHY WoL Control 50: Address 1D.C331

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 1

[F:0]

Wake Up Frame Pattern Mask 4 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.846 GbE PHY WoL Control 48: Address 1D.C32F

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 2

[F:0]

Wake Up Frame Pattern Mask 4 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.847 GbE PHY WoL Control 49: Address 1D.C330

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 3

[F:0]

Wake Up Frame Pattern Mask 4 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.848 GbE PHY WoL Control 50: Address 1D.C331

511

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6.10.59 GbE PHY WoL Control 51: Address 1D.C332

6.10.60 GbE PHY WoL Control 52: Address 1D.C333

6.10.61 GbE PHY WoL Control 53: Address 1D.C334

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 4

[F:0]

Wake Up Frame Pattern Mask 4 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Note : This configuration is used for the RSI

and RSI2. It is not used for RSI1.

Table 6.849 GbE PHY WoL Control 51: Address 1D.C332

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 5

[F:0]

Wake Up Frame Pattern Mask 4 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.850 GbE PHY WoL Control 52: Address 1D.C333

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 6

[F:0]

Wake Up Frame Pattern Mask 4 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.851 GbE PHY WoL Control 53: Address 1D.C334

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AQR405 Revision 0.11 - January 5, 2015

6.10.62 GbE PHY WoL Control 54: Address 1D.C335

6.10.63 GbE PHY WoL Control 55: Address 1D.C336

6.10.64 GbE PHY WoL Control 56: Address 1D.C337

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 4 Word 7

[F:0]

Wake Up Frame Pattern Mask 4 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 4 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.852 GbE PHY WoL Control 54: Address 1D.C335

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 4 Word 0

[F:0]

Wake Up Frame CRC 4 bits 15:0 R/W 0x0000

Table 6.853 GbE PHY WoL Control 55: Address 1D.C336

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 4 Word 1

[F:0]

Wake Up Frame CRC 4 bits 31:16 R/W 0x0000

Table 6.854 GbE PHY WoL Control 56: Address 1D.C337

513

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AQR405 Revision 0.11 - January 5, 2015

6.10.65 GbE PHY WoL Control 57: Address 1D.C338

6.10.66 GbE PHY WoL Control 58: Address 1D.C339

6.10.67 GbE PHY WoL Control 59: Address 1D.C33A

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Magic Packet

Frame Detection

Enable

1 = Magic Packet Frame Detection

Enable

R/W 0

Table 6.855 GbE PHY WoL Control 57: Address 1D.C338

Bit Name Description Type Default Note

F:0 Magic Packet

Frame Pattern

Word 0 [F:0]

Magic Packet Frame Pattern bits 15:0 R/W 0x0000 Magic packet frame pattern (MAC address)

Table 6.856 GbE PHY WoL Control 58: Address 1D.C339

Bit Name Description Type Default Note

F:0 Magic Packet

Frame Pattern

Word 1 [F:0]

Magic Packet Frame Pattern bits 31:16 R/W 0x0000 Magic packet frame pattern (MAC address)

Table 6.857 GbE PHY WoL Control 59: Address 1D.C33A

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AQR405 Revision 0.11 - January 5, 2015

6.10.68 GbE PHY WoL Control 60: Address 1D.C33B

6.10.69 GbE PHY Extended WoL Control 1: Address 1D.C420

6.10.70 GbE PHY Extended WoL Control 2: Address 1D.C421

Bit Name Description Type Default Note

F:0 Magic Packet

Frame Pattern

Word 2 [F:0]

Magic Packet Frame Pattern bits 47:32 R/W 0x0000 Magic packet frame pattern (MAC address)

Table 6.858 GbE PHY WoL Control 60: Address 1D.C33B

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 0

[F:0]

Wake Up Frame Pattern Mask 5 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.859 GbE PHY Extended WoL Control 1: Address 1D.C420

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 1

[F:0]

Wake Up Frame Pattern Mask 55 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.860 GbE PHY Extended WoL Control 2: Address 1D.C421

515

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6.10.71 GbE PHY Extended WoL Control 3: Address 1D.C422

6.10.72 GbE PHY Extended WoL Control 4: Address 1D.C423

6.10.73 GbE PHY Extended WoL Control 5: Address 1D.C424

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 2

[F:0]

Wake Up Frame Pattern Mask 5 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.861 GbE PHY Extended WoL Control 3: Address 1D.C422

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 3

[F:0]

Wake Up Frame Pattern Mask 5 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.862 GbE PHY Extended WoL Control 4: Address 1D.C423

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 4

[F:0]

Wake Up Frame Pattern Mask 5 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.863 GbE PHY Extended WoL Control 5: Address 1D.C424

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AQR405 Revision 0.11 - January 5, 2015

6.10.74 GbE PHY Extended WoL Control 6: Address 1D.C425

6.10.75 GbE PHY Extended WoL Control 7: Address 1D.C426

6.10.76 GbE PHY Extended WoL Control 8: Address 1D.C427

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 5

[F:0]

Wake Up Frame Pattern Mask 5 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.864 GbE PHY Extended WoL Control 6: Address 1D.C425

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 6

[F:0]

Wake Up Frame Pattern Mask 5 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.865 GbE PHY Extended WoL Control 7: Address 1D.C426

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 5 Word 7

[F:0]

Wake Up Frame Pattern Mask 5 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 5 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.866 GbE PHY Extended WoL Control 8: Address 1D.C427

517

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AQR405 Revision 0.11 - January 5, 2015

6.10.77 GbE PHY Extended WoL Control 9: Address 1D.C428

6.10.78 GbE PHY Extended WoL Control 10: Address 1D.C429

6.10.79 GbE PHY Extended WoL Control 11: Address 1D.C42A

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 5 Word 0

[F:0]

Wake Up Frame CRC 5 bits 15:0 R/W 0x0000

Table 6.867 GbE PHY Extended WoL Control 9: Address 1D.C428

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 5 Word 1

[F:0]

Wake Up Frame CRC 5 bits 31:16 R/W 0x0000

Table 6.868 GbE PHY Extended WoL Control 10: Address 1D.C429

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 0

[F:0]

Wake Up Frame Pattern Mask 6 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.869 GbE PHY Extended WoL Control 11: Address 1D.C42A

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AQR405 Revision 0.11 - January 5, 2015

6.10.80 GbE PHY Extended WoL Control 12: Address 1D.C42B

6.10.81 GbE PHY Extended WoL Control 13: Address 1D.C42C

6.10.82 GbE PHY Extended WoL Control 14: Address 1D.C42D

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 1

[F:0]

Wake Up Frame Pattern Mask 65 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.870 GbE PHY Extended WoL Control 12: Address 1D.C42B

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 2

[F:0]

Wake Up Frame Pattern Mask 6 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.871 GbE PHY Extended WoL Control 13: Address 1D.C42C

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 3

[F:0]

Wake Up Frame Pattern Mask 6 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.872 GbE PHY Extended WoL Control 14: Address 1D.C42D

519

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AQR405 Revision 0.11 - January 5, 2015

6.10.83 GbE PHY Extended WoL Control 15: Address 1D.C42E

6.10.84 GbE PHY Extended WoL Control 16: Address 1D.C42F

6.10.85 GbE PHY Extended WoL Control 17: Address 1D.C430

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 4

[F:0]

Wake Up Frame Pattern Mask 6 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.873 GbE PHY Extended WoL Control 15: Address 1D.C42E

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 5

[F:0]

Wake Up Frame Pattern Mask 6 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.874 GbE PHY Extended WoL Control 16: Address 1D.C42F

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 6

[F:0]

Wake Up Frame Pattern Mask 6 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.875 GbE PHY Extended WoL Control 17: Address 1D.C430

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AQR405 Revision 0.11 - January 5, 2015

6.10.86 GbE PHY Extended WoL Control 18: Address 1D.C431

6.10.87 GbE PHY Extended WoL Control 19: Address 1D.C432

6.10.88 GbE PHY Extended WoL Control 20: Address 1D.C433

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 6 Word 7

[F:0]

Wake Up Frame Pattern Mask 6 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 6 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.876 GbE PHY Extended WoL Control 18: Address 1D.C431

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 6 Word 0

[F:0]

Wake Up Frame CRC 6 bits 15:0 R/W 0x0000

Table 6.877 GbE PHY Extended WoL Control 19: Address 1D.C432

Bit Name Description Type Default Note

F:0 Rx Wake Up

Frame CRC 6

Word 1 [F:0]

Wake Up Frame CRC 6 bits 31:16 R/W 0x0000

Table 6.878 GbE PHY Extended WoL Control 20: Address 1D.C433

521

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AQR405 Revision 0.11 - January 5, 2015

6.10.89 GbE PHY Extended WoL Control 21: Address 1D.C434

6.10.90 GbE PHY Extended WoL Control 22: Address 1D.C435

6.10.91 GbE PHY Extended WoL Control 23: Address 1D.C436

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 0

[F:0]

Wake Up Frame Pattern Mask 7 bits

15:0

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.879 GbE PHY Extended WoL Control 21: Address 1D.C434

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 1

[F:0]

Wake Up Frame Pattern Mask 75 bits

31:16

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.880 GbE PHY Extended WoL Control 22: Address 1D.C435

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 2

[F:0]

Wake Up Frame Pattern Mask 7 bits

47:32

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.881 GbE PHY Extended WoL Control 23: Address 1D.C436

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6.10.92 GbE PHY Extended WoL Control 24: Address 1D.C437

6.10.93 GbE PHY Extended WoL Control 25: Address 1D.C438

6.10.94 GbE PHY Extended WoL Control 26: Address 1D.C439

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 3

[F:0]

Wake Up Frame Pattern Mask 7 bits

63:48

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.882 GbE PHY Extended WoL Control 24: Address 1D.C437

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 4

[F:0]

Wake Up Frame Pattern Mask 7 bits

79:64

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.883 GbE PHY Extended WoL Control 25: Address 1D.C438

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 5

[F:0]

Wake Up Frame Pattern Mask 7 bits

95:80

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.884 GbE PHY Extended WoL Control 26: Address 1D.C439

523

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AQR405 Revision 0.11 - January 5, 2015

6.10.95 GbE PHY Extended WoL Control 27: Address 1D.C43A

6.10.96 GbE PHY Extended WoL Control 28: Address 1D.C43B

6.10.97 GbE PHY Extended WoL Control 29: Address 1D.C43C

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 6

[F:0]

Wake Up Frame Pattern Mask 7 bits

111:96

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.885 GbE PHY Extended WoL Control 27: Address 1D.C43A

Bit Name Description Type Default Note

F:0 Wake Up Frame

Mask 7 Word 7

[F:0]

Wake Up Frame Pattern Mask 7 bits

127:112

R/W 0x0000 Wake-up Frame Pattern Mask 7 (0=disable,

1=enable, bit 0 for the first byte,

default:all-zeroes)

Table 6.886 GbE PHY Extended WoL Control 28: Address 1D.C43B

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 7 Word 0

[F:0]

Wake Up Frame CRC 7 bits 15:0 R/W 0x0000

Table 6.887 GbE PHY Extended WoL Control 29: Address 1D.C43C

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6.10.98 GbE PHY Extended WoL Control 30: Address 1D.C43D

6.10.99 GbE Reserved Provisioning 1: Address 1D.C500

Bit Name Description Type Default Note

F:0 Wake Up Frame

CRC 7 Word 1

[F:0]

Wake Up Frame CRC 7 bits 31:16 R/W 0x0000

Table 6.888 GbE PHY Extended WoL Control 30: Address 1D.C43D

Bit Name Description Type Default Note

F 100M System

Loopback

1 = Enable System Loopback R/W

0 Setting this bit enables the 100M system

loopback.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

E GbE System

Loopback

1 = Enable System Loopback R/W

0 Setting this bit enables the 1G system

loopback.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

D:0 Reserved

Provisioning 1

[D:0]

Reserved for future use R/W

0x0000

Table 6.889 GbE Reserved Provisioning 1: Address 1D.C500

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6.10.100 GbE Reserved Provisioning 2: Address 1D.C501

Bit Name Description Type Default Note

F:D Test Mode [2:0] 000 = Normal mode

001 = Test Mode 1 - Transmit waveform

test

010 = Test Mode 2 - Master transmit

jitter test

011 = Test Mode 3 - Slave transmit jitter

test

100 = Test Mode 4 - Transmitter

distortion test

101 -> 1111 = Reserved

R/W 0x0 NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

C:2 Reserved

Provisioning 2

[A:0]

Reserved for future use R/W

0x000

1:0 100BASE-TX

Test Mode [1:0]

00 = Normal mode

01 = 100BASE-TX IEEE Test Mode

10 = 100BASE-TX ANSI Jitter Test

11 = 100BASE-TX ANSI Droop Test

R/W 0x0 100BASE-TX IEEE Test Mode = MLT-3 Idle

Sequence

ANSI Jitter Test = FDDI - Clause 9.1.3 Fig. 12

ANSI Droop Test = FDDI - Clause 9.1.8 Fig. 14

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

Table 6.890 GbE Reserved Provisioning 2: Address 1D.C501

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6.10.101 GbE PHY SGMII1 Rx Status 1: Address 1D.D280

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 SGMII

Synchronization

Status

1 = SGMII is Synchronized RO

7 SGMII Loopback

Idle Insertion

Detected

1 = SGMII Idle Insertion Detected LH

6 SGMII Loopback

Idle Deletion

Detected

1 = SGMII Idle Deletion Detected LH

5 SGMII Idle

Insertion

Detected

1 = SGMII Idle Insertion Detected LH

4 SGMII Idle

Deletion

Detected

1 = SGMII Idle Deletion Detected LH

3:2 Reserved Internal reserved - do not modify

1 SGMII TX_ER

Suppression

1 = TX_ER suppressed LH Indicate TX_ER has been suppressed when

TX_EN was not asserted

0 SGMII Rx Link

Activity

1 = SGMII Rx Link Activity LH SGMII Start Character K27_7 detected

Table 6.891 GbE PHY SGMII1 Rx Status 1: Address 1D.D280

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6.10.102 GbE PHY SGMII1 Rx Status 2: Address 1D.D281

6.10.103 GbE PHY SGMII1 Rx Status 3: Address 1D.D282

6.10.104 GbE PHY SGMII1 Rx Status 4: Address 1D.D283

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.892 GbE PHY SGMII1 Rx Status 2: Address 1D.D281

Bit Name Description Type Default Note

F:0 SGMII1 Rx

Frame Counter

LSW [F:0]

SGMII1 Rx Good Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.893 GbE PHY SGMII1 Rx Status 3: Address 1D.D282

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII1 Rx

Frame Counter

MSW [9:0]

SGMII1 Rx Good Frame Counter SCT

0x000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.894 GbE PHY SGMII1 Rx Status 4: Address 1D.D283

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6.10.105 GbE PHY SGMII1 Rx Status 5: Address 1D.D284

6.10.106 GbE PHY SGMII1 Rx Status 6: Address 1D.D285

6.10.107 GbE PHY SGMII1 Rx Status 7: Address 1D.D286

Bit Name Description Type Default Note

F:0 SGMII1 Rx

Frame Error

Counter LSW

[F:0]

SGMII1 Rx Bad Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.895 GbE PHY SGMII1 Rx Status 5: Address 1D.D284

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII1 Rx

Frame Error

Counter MSW

[9:0]

SGMII1 Rx Bad Frame Counter SCT

0x000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.896 GbE PHY SGMII1 Rx Status 6: Address 1D.D285

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SGMII1 Rx

Comma Detect

1 = SGMII1 Rx Comma Detected LH Indicates when SGMII Rx has detected a

comma character

Table 6.897 GbE PHY SGMII1 Rx Status 7: Address 1D.D286

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6.10.108 GbE PHY SGMII1 Rx Status 8: Address 1D.D287

6.10.109 GbE PHY SGMII1 Rx Status 9: Address 1D.D288

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII1 Rx

False Carrier

Counter [7:0]

SGMII1 Rx False Carrier Counter SCT 0x00 TSI detects false carrier on the SGMII

interface.

Table 6.898 GbE PHY SGMII1 Rx Status 8: Address 1D.D287

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 SGMII1 Rx EEE

Rx LPI State

Machine [3:0]

SGMII1 Rx EEE Rx LPI state machine RO Rx LPI state machine

7:5 Reserved Internal reserved - do not modify

4 SGMII1 Rx EEE

Rx LPI Ordered

Set Dectected

1 = SGMII1 Rx LPI ordered set detected LH Indicate LPI ordered_set is detected

3 SGMII1 Rx EEE

Rx LPI Wake

Timer Fault Error

1 = SGMII1 Rx Rx LPI detected wake

timer fault

LH Indicate Rx LPI detected wake timer fault

2 SGMII1 Rx EEE

Rx LPI Wake

Done State

1 = SGMII1 Rx Rx LPI is in wake done

state

RO Indicate Rx LPI is in wake done state

Table 6.899 GbE PHY SGMII1 Rx Status 9: Address 1D.D288

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6.10.110 GbE PHY SGMII0 Rx Status 1: Address 1D.D290

1 SGMII1 Rx EEE

Rx LPI Quiet

State

1 = SGMII1 Rx Rx LPI is in quiet state RO Indicate Rx LPI is in quiet state

0 SGMII1 Rx EEE

Rx LPI Active

State

1 = SGMII1 Rx Rx LPI is in active state RO Indicate Rx LPI is in active state

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 SGMII0 Rx

Synchronization

Status

1 = SGMII0 Rx is Synchronized RO

7 SGMII0 Rx

Loopback Idle

Insertion

Detected

1 = SGMII0 Rx Idle Insertion Detected LH

6 SGMII0 Rx

Loopback Idle

Deletion

Detected

1 = SGMII0 Rx Idle Deletion Detected LH

5 SGMII0 Rx Idle

Insertion

Detected

1 = SGMII0 Rx Idle Insertion Detected LH

4 SGMII0 Rx Idle

Deletion

Detected

1 = SGMII0 Rx Idle Deletion Detected LH

Table 6.900 GbE PHY SGMII0 Rx Status 1: Address 1D.D290

Bit Name Description Type Default Note

Table 6.899 GbE PHY SGMII1 Rx Status 9: Address 1D.D288

531

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6.10.111 GbE PHY SGMII0 Rx Status 2: Address 1D.D291

6.10.112 GbE PHY SGMII0 Rx Status 3: Address 1D.D292

3:2 Reserved Internal reserved - do not modify

1 SGMII0 Rx

TX_ER

Suppression

1 = SGMII0 Rx TX_ER suppressed LH Indicate TX_ER has been suppressed when

TX_EN was not asserted

0 SGMII0 Rx Rx

Link Activity

1 = SGMII0 Rx Rx Link Activity LH SGMII Start Character K27_7 detected

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.901 GbE PHY SGMII0 Rx Status 2: Address 1D.D291

Bit Name Description Type Default Note

F:0 SGMII0 Rx

Frame Counter

LSW [F:0]

SGMII0 Rx Good Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.902 GbE PHY SGMII0 Rx Status 3: Address 1D.D292

Bit Name Description Type Default Note

Table 6.900 GbE PHY SGMII0 Rx Status 1: Address 1D.D290

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6.10.113 GbE PHY SGMII0 Rx Status 4: Address 1D.D293

6.10.114 GbE PHY SGMII0 Rx Status 5: Address 1D.D294

6.10.115 GbE PHY SGMII0 Rx Status 6: Address 1D.D295

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII0 Rx

Frame Counter

MSW [9:0]

SGMII0 Rx Good Frame Counter SCT

0x000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.903 GbE PHY SGMII0 Rx Status 4: Address 1D.D293

Bit Name Description Type Default Note

F:0 SGMII0 Rx

Frame Error

Counter LSW

[F:0]

SGMII0 Rx Bad Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.904 GbE PHY SGMII0 Rx Status 5: Address 1D.D294

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII0 Rx

Frame Error

Counter MSW

[9:0]

SGMII0 Rx Bad Frame Counter SCT

0x000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.905 GbE PHY SGMII0 Rx Status 6: Address 1D.D295

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6.10.116 GbE PHY SGMII0 Rx Status 7: Address 1D.D296

6.10.117 GbE PHY SGMII0 Rx Status 8: Address 1D.D297

6.10.118 GbE PHY SGMII0 Rx Status 9: Address 1D.D298

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 SGMII0 Rx

Comma Detect

1 = SGMII0 Rx Comma Detected LH Indicates when Rx has detected a comma

character

Table 6.906 GbE PHY SGMII0 Rx Status 7: Address 1D.D296

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII0 Rx

False Carrier

Counter [7:0]

SGMII0 Rx False Carrier Counter SCT 0x00 False carrier events on XFI0 SGMII interface.

Table 6.907 GbE PHY SGMII0 Rx Status 8: Address 1D.D297

Bit Name Description Type Default Note

F:C Reserved Internal reserved - do not modify

B:8 SGMII0 Rx EEE

Rx LPI State

Machine [3:0]

SGMII0 Rx EEE Rx LPI state machine RO Rx LPI state machine

7:5 Reserved Internal reserved - do not modify

Table 6.908 GbE PHY SGMII0 Rx Status 9: Address 1D.D298

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6.10.119 GbE PHY SGMII1 WoL Status: Address 1D.D302

4 SGMII0 Rx EEE

Rx LPI Ordered

Set Dectected

1 = SGMII0 Rx LPI ordered set detected LH Indicate LPI ordered_set is detected

3 SGMII0 Rx EEE

Rx LPI Wake

Timer Fault Error

1 = SGMII0 Rx Rx LPI detected wake

timer fault

LH Indicate Rx LPI detected wake timer fault

2 SGMII0 Rx EEE

Rx LPI Wake

Done State

1 = SGMII0 Rx Rx LPI is in wake done

state

RO Indicate Rx LPI is in wake done state

1 SGMII0 Rx EEE

Rx LPI Quiet

State

1 = SGMII0 Rx Rx LPI is in quiet state RO Indicate Rx LPI is in quiet state

0 SGMII0 Rx EEE

Rx LPI Active

State

1 = SGMII0 Rx Rx LPI is in active state RO Indicate Rx LPI is in active state

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 Wake Up Frame

Type [2:0]

Wake Up Frame Type RO Wake-up Frame type detected (0 to

4:Wake-up Frame 0 to 4)

Table 6.909 GbE PHY SGMII1 WoL Status: Address 1D.D302

Bit Name Description Type Default Note

Table 6.908 GbE PHY SGMII0 Rx Status 9: Address 1D.D298

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6.10.120 GbE PHY SGMII1 Tx Status 1: Address 1D.D303

6.10.121 GbE PHY SGMII1 Tx Status 2: Address 1D.D304

6.10.122 GbE PHY SGMII1 Tx Status 3: Address 1D.D305

Bit Name Description Type Default Note

F:0 SGMII1 Tx

Frame Counter

LSW [F:0]

SGMII1 Tx Good Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.910 GbE PHY SGMII1 Rx Status 3: Address 1D.D282

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII1 Tx

Frame Counter

MSW [9:0]

SGMII1 Tx Good Frame Counter SCT

0x000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.911 GbE PHY SGMII1 Rx Status 4: Address 1D.D283

Bit Name Description Type Default Note

F:0 SGMII1 Tx

Frame Error

Counter LSW

[F:0]

SGMII1 Tx Bad Frame Error Counter SCT

0x0000 Frames with CRC error counter.

Table 6.912 GbE PHY SGMII1 Rx Status 5: Address 1D.D284

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6.10.123 GbE PHY SGMII1 Tx Status 4: Address 1D.D306

6.10.124 GbE PHY SGMII1 Tx Status 5: Address 1D.D307

6.10.125 GbE PHY SGMII1 Tx Status 6: Address 1D.D308

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII1 Tx

Frame Error

Counter MSW

[9:0]

SGMII1 Tx Bad Frame Error Counter SCT

0x000 Frames with CRC error counter.

Table 6.913 GbE PHY SGMII1 Rx Status 6: Address 1D.D285

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII1 Tx False

Carrier Counter

[7:0]

SGMII1 Tx False Carrier Counter SCT 0x00 SGMII1 Tx detected false carrier event the on

the SERDES interface.

Table 6.914 GbE PHY SGMII1 Tx Status 5: Address 1D.D307

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII1 Tx

Collision

Counter [7:0]

SGMII1 Tx Collision Counter SCT 0x00 SGMII1 Tx detected a collision on the

SERDES interface.

Table 6.915 GbE PHY SGMII1 Tx Status 6: Address 1D.D308

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6.10.126 GbE PHY SGMII1 Tx Status 7: Address 1D.D309

6.10.127 GbE PHY SGMII1 Tx Status 8: Address 1D.D30A

6.10.128 GbE PHY SGMII1 Tx Status 9: Address 1D.D30B

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII1 Tx Line

Collision

Counter [7:0]

SGMII1 Tx Line Collision Counter SCT 0x00 SGMII1 Tx detects collision on the GMII/MII

interface.

Table 6.916 GbE PHY SGMII1 Tx Status 7: Address 1D.D309

Bit Name Description Type Default Note

F:0 SGMII1 Tx

Frame

Alignment

Counter [F:0]

SGMII1 Tx Frame Alignment Counter SCT 0x0000 SGMII1 Tx Frame Count with alignment error.

This is detected by CRC error with an extra

nibble on MII interface (100M mode) on the

GMII/MII interface.

Table 6.917 GbE PHY SGMII1 Tx Status 8: Address 1D.D30A

Bit Name Description Type Default Note

F:0 SGMII1 Tx Runt

Frame Counter

LSW [F:0]

SGMII1 Tx Runt Frame Counter SCT

0x0000 SGMII1 Tx Runt Frame (less than 64 byte

long) Count on the GMII/MII interface.

Table 6.918 GbE PHY SGMII1 Tx Status 9: Address 1D.D30B

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6.10.129 GbE PHY SGMII1 Tx Status 10: Address 1D.D30C

6.10.130 SGMII0 WoL Status : Address 1D.D312

6.10.131 GbE PHY SGMII0 Tx Status 1: Address 1D.D313

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:0 SGMII1 Tx Runt

Frame Counter

MSW [5:0]

SGMII1 Tx Runt Frame Counter SCT

0x00 Rx Runt Frame (less than 64 byte long) Count

on the GMII/MII interface.

Table 6.919 GbE PHY SGMII1 Tx Status 10: Address 1D.D30C

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 SGMII0 Wake

Up Frame Type

[2:0]

SGMII0 Wake Up Frame Type RO Wake-up Frame type detected (0 to 7:

Wake-up Frame 0 to 7)

Table 6.920 SGMII0 WoL Status : Address 1D.D312

Bit Name Description Type Default Note

F:0 SGMII0 Tx

Frame Counter

LSW [F:0]

SGMII0 Tx Good Frame Counter SCT

0x0000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.921 GbE PHY SGMII0 Tx Status 1: Address 1D.D313

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6.10.132 GbE PHY SGMII0 Tx Status 2: Address 1D.D314

6.10.133 GbE PHY SGMII0 Tx Status 3: Address 1D.D315

6.10.134 GbE PHY SGMII0 Tx Status 4: Address 1D.D316

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII0 Tx

Frame Counter

MSW [9:0]

SGMII0 Tx Good Frame Counter SCT

0x000 This counts 100M / GbE Ethernet good frames

(i.e. no Ethernet CRC-32 / FCS errors).

Table 6.922 GbE PHY SGMII0 Tx Status 2: Address 1D.D314

Bit Name Description Type Default Note

F:0 SGMII0 Tx

Frame Error

Counter LSW

[F:0]

SGMII0 Tx Bad Frame Error Counter SCT

0x0000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.923 GbE PHY SGMII0 Tx Status 3: Address 1D.D315

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9:0 SGMII0 Tx

Frame Error

Counter MSW

[9:0]

SGMII0 Tx Bad Frame Error Counter SCT

0x000 This counts 100M / GbE Ethernet frames with

a bad FCS (aka CRC-32).

Table 6.924 GbE PHY SGMII0 Tx Status 4: Address 1D.D316

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6.10.135 GbE PHY SGMII0 Tx Status 5: Address 1D.D317

6.10.136 GbE PHY SGMII0 Tx Status 6: Address 1D.D318

6.10.137 GbE PHY SGMII0 Tx Status 7: Address 1D.D319

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII0 Tx False

Carrier Counter

[7:0]

SGMII0 Tx False Carrier Counter SCT 0x00 SGMII0 Tx detected false carrier on the

GMII/MII interface.

Table 6.925 GbE PHY SGMII0 Tx Status 5: Address 1D.D317

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII0 Tx

Collision

Counter [7:0]

SGMII0 Tx Collision Counter SCT 0x00 SGMII0 Tx detected a collision on the SGMII

interface.

Table 6.926 GbE PHY SGMII0 Tx Status 6: Address 1D.D318

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 SGMII0 Tx Line

Collision

Counter [7:0]

SGMII0 Tx Line Collision Counter SCT 0x00 SGMII0 Tx detected a collision on the GMII/MII

interface.

Table 6.927 GbE PHY SGMII0 Tx Status 7: Address 1D.D319

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6.10.138 GbE PHY SGMII0 Tx Status 8: Address 1D.D31A

6.10.139 GbE PHY SGMII0 Tx Status 9: Address 1D.D31B

6.10.140 GbE PHY SGMII0 Tx Status 10: Address 1D.D31C

Bit Name Description Type Default Note

F:0 SGMII0 Tx

Frame

Alignment

Counter [F:0]

SGMII0 Tx Frame Alignment Counter SCT 0x0000 SGMII0 Tx Frame Count with alignment error.

This is detected by CRC error with an extra

nibble on the MII interface (100M mode) on the

GMII/MII interface.

Table 6.928 GbE PHY SGMII0 Tx Status 8: Address 1D.D31A

Bit Name Description Type Default Note

F:0 SGMII0 Tx Runt

Frame Counter

LSW [F:0]

SGMII0 Tx Runt Frame Counter SCT

0x0000 SGMII0 Tx Runt Frame (less than 64 byte

long) Count on the GMII/MII interface.

Table 6.929 GbE PHY SGMII0 Tx Status 9: Address 1D.D31B

Bit Name Description Type Default Note

F:6 Reserved Internal reserved - do not modify

5:0 SGMII0 Tx Runt

Frame Counter

MSW [5:0]

SGMII0 Tx Runt Frame Counter SCT

0x00 SGMII0 Tx Runt Frame (less than 64 byte

long) Count on the GMII/MII interface.

Table 6.930 GbE PHY SGMII0 Tx Status 10: Address 1D.D31C

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6.10.141 GbE PHY SGMII WoL Status: Address 1D.D322

6.10.142 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10

Bit Name Description Type Default Note

F:3 Reserved Internal reserved - do not modify

2:0 SGMII Wake Up

Frame Type

[2:0]

SGMII Wake Up Frame Type RO Wake-up Frame type detected (0 to 7:

Wake-up Frame 0 to 7)

Table 6.931 GbE PHY SGMII WoL Status: Address 1D.D322

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 SGMII0 Rx Loss

of Signal

1 = SGMII0 Loss of Signal LH

6 SGMII0 Rx

Invalid

Character Error

1 = SGMII0 Rx Invalid Character Error LH

5 SGMII0 Rx

Running

Disparity Error

1 = SGMII0 Rx Running Disparity Error LH

4 SGMII0 Rx Code

Violation Error

1 = SGMII0 Rx Code Violation Error LH

3 SGMII1 Rx Loss

of Signal

1 = SGMII1 Loss of Signal LH

2 SGMII1 Rx

Invalid

Character Error

1 = SGMII1 Rx Invalid Character Error LH

Table 6.932 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10

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6.10.143 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20

1 SGMII1 Rx

Running

Disparity Error

1 = SGMII1 Rx Running Disparity Error LH

0 SGMII1 Rx Code

Violation Error

1 = SGMII1 Rx Code Violation Error LH

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 SGMII Magic

Packet Frame

Detected

1 = SGMII Magic Packet Frame

Detected LH

8 SGMII Wake Up

Frame Detected

1 = SGMII Wake Up Frame Detected LH

7 Reserved Internal reserved - do not modify

6 SGMII0 Tx

Invalid GMII

Character

Detected

1 = SGMII0 Tx Invalid GMII Character

Detected

5 SGMII0 Magic

Packet Frame

Detected

1 = SGMII0 Magic Packet Frame

Detected

4 SGMII0 Wake

Up Frame

Detected

1 = SGMII0 Wake Up Frame Detected LH

3 Reserved Internal reserved - do not modify

Table 6.933 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20

Bit Name Description Type Default Note

Table 6.932 GbE PHY SGMII Rx Alarms 1: Address 1D.EC10

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6.10.144 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410

2 SGMII1 Tx

Invalid GMII

Character

Detected

1 = SGMII1 Tx Invalid GMII Character

Detected

1 SGMII1 Magic

Packet Frame

Detected

1 = SGMII1 Magic Packet Frame

Detected

0 SGMII1 Wake

Up Frame

Detected

1 = SGMII1 Wake Up Frame Detected LH

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 SGMII0 Rx Loss

of Signal Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

6 SGMII0 Rx

Invalid

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5 SGMII0 Rx

Running

Disparity Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.934 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410

Bit Name Description Type Default Note

Table 6.933 GbE PHY SGMII Tx Alarms 1: Address 1D.EC20

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6.10.145 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420

4 SGMII0 Rx Code

Violation Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 SGMII1 Rx Loss

of Signal Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2 SGMII1 Rx

Invalid

Character Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 SGMII1 Rx

Running

Disparity Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 SGMII1 Rx Code

Violation Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F:A Reserved Internal reserved - do not modify

9 SGMII Magic

Packet Frame

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

8 SGMII Wake Up

Frame Detected

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.935 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420

Bit Name Description Type Default Note

Table 6.934 GbE PHY SGMII Rx Interrupt Mask 1: Address 1D.F410

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7 Reserved Internal reserved - do not modify

6 SGMII0 Tx

Invalid GMII

Character

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5 SGMII0 Magic

Packet Frame

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

4 SGMII0 Wake

Up Frame

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 Reserved Internal reserved - do not modify

2 SGMII1 Tx

Invalid GMII

Character

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 SGMII1 Magic

Packet Frame

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 SGMII1 Wake

Up Frame

Detected Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

Table 6.935 GbE PHY SGMII Tx Interrupt Mask 1: Address 1D.F420

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6.10.146 GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4 Vendor Specific

SGMII Tx

Alarms 1

Interrupt

1 = Interrupt in vendor specific SGMII Tx

Alarms 1

RO An interrupt was generated from the status

3 Vendor Specific

SGMII Tx

Alarms 2

Interrupt

1 = Interrupt in vendor specific SGMII Tx

Alarms 2

RO An interrupt was generated from the status

2 Vendor Specific

SGMII Rx

Alarms 1

Interrupt

1 = Interrupt in vendor specific SGMII Tx

Alarms 1

RO An interrupt was generated from the status

1 Vendor Specific

SGMII Rx

Alarms 2

Interrupt

1 = Interrupt in vendor specific SGMII Tx

Alarms 2

RO An interrupt was generated from the status

0 Reserved Internal reserved - do not modify

Table 6.936 GbE PHY Vendor Global Interrupt Flags 1: Address 1D.FC00

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6.11 Global Registers

6.11.1 Global Standard Control 1: Address 1E.0

6.11.2 Global Standard Device Identifier 1: Address 1E.2

Bit Name Description Type Default Note

F Soft Reset 1 = Global soft reset

0 = Normal operation

R/W

1 Resets the entire PHY.

Setting this bit initiates a global soft reset on all of

the digital logic not including the microprocessor

(i.e. microprocessor is not reset). Upon completion

of the reset sequence, this bit is set back to 0by the

microprocessor. Note this bit is OR’ed with the

individual MMD resets. This bit should be set to 0

before setting the individual MMD resets.

E:C Reserved Internal reserved - do not modify

B Low Power 1 = Low-power mode

0 = Normal operation

R/W

0 A one written to this register causes the chip to

enter low-power mode. This bit puts the entire chip

in low-power mode, with only the MDIO and

microprocessor functioning, and turns off the

analog front-end: i.e. places it in high-impedance

mode. Setting this bit also sets all of the Low Power

bits in the other MMDs.

A:0 Reserved Internal reserved - do not modify

Table 6.937 Global Standard Control 1: Address 1E.0

Bit Name Description Type Default Note

F:0 Device ID MSW

[1F:10]

Bits 31 - 16 of Device ID RO

Table 6.938 Global Standard Device Identifier 1: Address 1E.2

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6.11.3 Global Standard Device Identifier 2: Address 1E.3

6.11.4 Global Standard Devices in Package 1: Address 1E.5

Bit Name Description Type Default Note

F:0 Device ID LSW

[F:0]

Bits 15 - 0 of Device ID RO

Table 6.939 Global Standard Device Identifier 2: Address 1E.3

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7 Autonegotiation

Present

1 = Autonegotiation is present in

package

0 = Autonegotiation is not present in

package

ROS 1 This is always set to 1, as there is

Autonegotiation in the AQR405.

6 TC Present 1 = TC is present in package

0 = TC is not present in package

ROS 0 This is always set to 0, as there is no TC

functionality in the AQR405.

5 DTE XS Present 1 = DTE XS is present in package

0 = DTE XS is not present in package

ROS 0 This is always set to 0, as there is no DTE

XAUI interface in the AQR405.

4 PHY XS Present 1 = PHY XS is present in package

0 = PHY XS is not present in package

ROS 1 This is always set to 1 as there is a PHY XS

interface in the AQR405.

3 PCS Present 1 = PCS is present in package

0 = PCS is not present in package

ROS 1 This is always set to 1 as there is PCS

functionality in the AQR405.

2 WIS Present 1 = WIS is present in package

0 = WIS is not present in package

ROS 0 This is always set to 0, as there is no WIS

functionality in the AQR405.

Table 6.940 Global Standard Devices in Package 1: Address 1E.5

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6.11.5 Global Standard Vendor Devices in Package 2: Address 1E.6

1 PMA Present 1 = PMA is present in package

0 = PMA is not present

ROS 1 This is always set to 1 as there is PMA

functionality in the AQR405.

0 Clause 22

Registers

Present

1 = Clause 22 registers are present in

package

0 = Clause 22 registers are not present

in package

ROS 0 This is always set to 0 in the AQR405, as there

are no Clause 22 registers in the device.

Bit Name Description Type Default Note

F Vendor Specific

Device #2

Present

1 = Device #2 is present in package

0 = Device #2 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the DSP PMA registers.

E Vendor Specific

Device #1

Present

1 = Device #1 is present in package

0 = Device #1 is not present in package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the global control registers.

D Clause 22

Extension

Present

1 = Clause 22 Extension is present in

package

0 = Clause 22 Extension is not present in

package

ROS 1 This is always set to 1 as the AQR405 utilizes

this device for the GbE registers.

C:0 Reserved Internal reserved - do not modify

Table 6.941 Global Standard Vendor Devices in Package 2: Address 1E.6

Bit Name Description Type Default Note

Table 6.940 Global Standard Devices in Package 1: Address 1E.5

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6.11.6 Global Standard Status 2: Address 1E.8

6.11.7 Global Standard Package Identifier 1: Address 1E.E

6.11.8 Global Standard Package Identifier 2: Address 1E.F

Bit Name Description Type Default Note

F:E Device Present

[1:0]

[F:E]

0x3 = No device at this address

0x2 = Device present at this address

0x1 = No device at this address

0x0 = No device at this address

ROS 0x2 This field is always set to 0x2, as the Global

MMD resides here in the AQR405.

D:0 Reserved Internal reserved - do not modify

Table 6.942 Global Standard Status 2: Address 1E.8

Bit Name Description Type Default Note

F:0 Package ID

MSW [1F:10]

Bits 31- 16 of Package ID RO

Table 6.943 Global Standard Package Identifier 1: Address 1E.E

Bit Name Description Type Default Note

F:0 Package ID

LSW [F:0]

Bits 15 - 0 of Package ID RO

Table 6.944 Global Standard Package Identifier 2: Address 1E.F

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6.11.9 Global Firmware ID: Address 1E.20

6.11.10 Global NVR Interface 1: Address 1E.100

Bit Name Description Type Default Note

F:8 Firmware Major

Revision

Number [7:0]

[F:8] = Major revision number RO

The lower six bits of major and minor firmware

revision are exchanged in autonegotiation

when the PHYID message is sent.

7:0 Firmware Minor

Revision

Number [7:0]

[7:0] = Minor revision number RO

Table 6.945 Global Firmware ID: Address 1E.20

Bit Name Description Type Default Note

F NVR Execute

Operation

1 = Start NVR Operation R/W

0 When set to 1, the NVR operation will begin.

Ensure that the uP is stalled using the "uP Run

Stall" bit to ensure no NVR contention.

E NVR Write Mode 1 = Write to NVR

0 = Read from NVR

R/W 0

D Freeze NVR

CRC

1 = Freeze NVR Mailbox CRC

calculation register

R/W 0 To prevent an erroneous answer, this bit

should not be set at the same time the "NVR

Execute Operation" bit is set.

C Reset NVR CRC 1 = Reset NVR Mailbox CRC calculation

R/W

0 To prevent an erroneous answer, this bit

should not be set at the same time the "NVR

Execute Operation" bit is set.

B Reserved Internal reserved - do not modify

Table 6.946 Global NVR Interface 1: Address 1E.100

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6.11.11 Global NVR Interface 2: Address 1E.101

A NVR Burst 0 = Single read or write operation of up

to 4 bytes

1 = Burst operation

R/W 0 When this bit is set, the operation is a burst

operation where more than 32-bits is read from

the NVR or written to the NVR. This bit should

be set to one until the last burst in the read or

write operation, when it should be set to zero.

It operates by gating the SPI clock, and not

restarting it until new data is ready to be

written, or the previous contents have been

read. Each burst of data requires the NVR

Execute Operation bit to be set to initiate the

next phase.

9 Reserved Internal reserved - do not modify

8 NVR Busy 1 = NVR is busy

0 = NVR is ready

RO When set to 1, the NVR is busy. A new NVR

operation should not occur until this bit is 0. If

the NVR clock is greater than 64/63 of the

MDIO clock, this bit never needs to be polled

when operating over the MDIO.

7:0 NVR Opcode

[7:0]

NVR instruction opcode R/W 0x03

Bit Name Description Type Default Note

F:0 NVR Mailbox CRC [F:0] The running CRC-16 of everything

passing through the NVR interface

RO The CRC-16 over all data written or read

through the NVR interface. The CRC-16 is

calculated by dividing the data by:

x^16 + x^12 + x^5 + 1

Table 6.947 Global NVR Interface 2: Address 1E.101

Bit Name Description Type Default Note

Table 6.946 Global NVR Interface 1: Address 1E.100

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6.11.12 Global NVR Interface 3: Address 1E.102

6.11.13 Global NVR Interface 4: Address 1E.103

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:0 NVR Address

MSW [17:10]

NVR address MSW bits [17:10] R/W 0x00 The address of where to read and write

from in the NVR. This is self-incrementing

and will automatically increment after

each read or write operation. The

increment amount is based on the data

length (i.e. increments by 4 if the data

length is 4 bytes)

Table 6.948 Global NVR Interface 3: Address 1E.102

Bit Name Description Type Default Note

F:0 NVR Address

LSW [F:0]

NVR address LSW bits [F:0] R/W 0x0000 The address of where to read and write

from in the NVR. This is self-incrementing

and will automatically increment after

each read or write operation.

Table 6.949 Global NVR Interface 4: Address 1E.103

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6.11.14 Global NVR Interface 5: Address 1E.104

Bit Name Description Type Default Note

F:0 NVR Data MSW

[1F:10]

NVR data MSW bits [1F:10] R/W 0x0000 Data is stored and read-out from these

registers in little-endian format for operations

such as FLASH device ID, and for

programming the processor.

For instance the 64K Atmel device code reads

out as two bytes 0x651F into the LSW register,

whereas the datasheet indicates that 1F is the

first byte read, followed by 65 as the second

byte.

To burst read and write these 4 bytes in the

correct order (where DD is written to address

x), they should be stored as:

AA BB in the MSW

CC DD in the LSW.

Table 6.950 Global NVR Interface 5: Address 1E.104

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6.11.15 Global NVR Interface 6: Address 1E.105

6.11.16 Global Mailbox Interface 1: Address 1E.200

Bit Name Description Type Default Note

F:0 NVR Data LSW

[F:0]

NVR data LSW bits [F:0] R/W 0x0000 Data is stored and read-out from these

registers in little-endian format for

operations such as FLASH device ID, and

for programming the processor.

For instance the 64K Atmel device code

reads out as two bytes 0x651F into the

LSW register, whereas the datasheet

indicates that 1F is the first byte read,

followed by 65 as the second byte.

To burst read and write these 4 bytes in

the correct order (where DD is written to

address x), they should be stored as:

AA BB in the MSW

CC DD in the LSW.

Table 6.951 Global NVR Interface 6: Address 1E.105

Bit Name Description Type Default Note

F uP Mailbox

Execute

Operation

1 = Start of mailbox Operation R/W

0 Indicates mailbox is loaded and ready

E uP Mailbox Write

Mode

1 = Write

0 = Read

R/W 0 Mailbox direction

D Reserved Internal reserved - do not modify

Table 6.952 Global Mailbox Interface 1: Address 1E.200

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6.11.17 Global Mailbox Interface 2: Address 1E.201

C Reset uP

Mailbox CRC

1 = Reset uP mailbox CRC calculation

R/W

B:9 Reserved Internal reserved - do not modify

8 uP Mailbox Busy 1 = uP mailbox busy

0 = uP mailbox ready

RO In general the uP will respond within a few

processor cycles to any PIF slave request,

much faster than the MDIO. If the busy is

asserted over multiple MDIO polling cycles,

then a H/W error may have occurred and a

Global S/W reset or uP reset is required.

7:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:0 uP Mailbox CRC [F:0] The running CRC-16 of everything

passing through the mailbox

interface

Table 6.953 Global Mailbox Interface 2: Address 1E.201

Bit Name Description Type Default Note

Table 6.952 Global Mailbox Interface 1: Address 1E.200

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6.11.18 Global Mailbox Interface 3: Address 1E.202

6.11.19 Global Mailbox Interface 4: Address 1E.203

6.11.20 Global Mailbox Interface 5: Address 1E.204

Bit Name Description Type Default Note

F:0 uP Mailbox

Address MSW

[1F:10]

uP Mailbox MSW address R/W 0x0000 The address of where to read and write from in

the Microcontroller Mailbox. This is

self-incrementing and automatically

increments after each read and write

operation.AQR405

Table 6.954 Global Mailbox Interface 3: Address 1E.202

Bit Name Description Type Default Note

F:2 uP Mailbox

Address LSW

[F:2]

uP LSW Mailbox address [F:2] R/W 0x0000 The address of where to read and write from in

the Microcontroller Mailbox. This is

self-incrementing and automatically

increments after each read and write

operation.AQR405

1:0 uP Mailbox

Address LSW

Don’t Care [1:0]

Least significant uP LSW Mailbox

address bits [1:0]

RO These bits are always set to 0 since each

memory access is on a 4-byte boundary.

Table 6.955 Global Mailbox Interface 4: Address 1E.203

Bit Name Description Type Default Note

F:0 uP Mailbox Data

MSW [1F:10]

uP Mailbox data MSW R/W 0x0000

Table 6.956 Global Mailbox Interface 5: Address 1E.204

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6.11.21 Global Mailbox Interface 6: Address 1E.205

6.11.22 Global Mailbox Interface 7: Address 1E.206

6.11.23 Global Microprocessor Scratch Pad 1: Address 1E.300

Bit Name Description Type Default Note

F:0 uP Mailbox Data

LSW [F:0]

uP Mailbox data LSW R/W 0x0000

Table 6.957 Global Mailbox Interface 6: Address 1E.205

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 uP Mailbox CRC

Read Enable

1 = Update uP mailbox CRC on read R/W 0

0 Reserved Internal reserved - do not modify

Table 6.958 Global Mailbox Interface 7: Address 1E.206

Bit Name Description Type Default Note

F:0 Scratch Pad 1[F:0] General Purpose Scratch Pad R/W 0x0000

Table 6.959 Global Microprocessor Scratch Pad 1: Address 1E.300

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6.11.24 Global Microprocessor Scratch Pad 2: Address 1E.301

6.11.25 Global Control 1: Address 1E.C000

6.11.26 Global Control 2: Address 1E.C001

Bit Name Description Type Default Note

F:0 Scratch Pad 2 [F:0] General Purpose Scratch Pad R/W 0x0000

Table 6.960 Global Microprocessor Scratch Pad 2: Address 1E.301

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.961 Global Control 1: Address 1E.C000

Bit Name Description Type Default Note

F uP Reset 1 = Reset R/W 0 Resets the uP and the PIF master and slave

bus. Will be active for a minimum of 100

microseconds.

E:7 Reserved Internal reserved - do not modify

6 uP Run Stall

Override

0 = uP Run Stall from “MDIO Boot Load”

pin.

1 = uP Run Stall from "uP Run Stall" bit

R/W 0 This bit selects the uP Run Stall from either the

“MDIO Boot Load” pin or the "uP Run Stall" bit.

Pin no longer brought out as deprecated.

Table 6.962 Global Control 2: Address 1E.C001

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6.11.27 Global Reset Control: Address 1E.C006

6.11.28 Global Diagnostic Provisioning: Address 1E.C400

5:1 Reserved Internal reserved - do not modify

0 uP Run Stall 1 = uP Run Stall

0 = uP normal mode

R/W 0 Deactivates the uP.

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E Global MMD

Reset Disable

1 = Disable the S/W reset to the Global

MMD registers

0 = Enable the S/W reset to the Global

MMD registers

R/W

0 Setting this bit prevents a Global S/W reset or

Global S/W reset from resetting the Global

MMD registers

D:0 Reserved Internal reserved - do not modify

Table 6.963 Global Reset Control: Address 1E.C006

Bit Name Description Type Default Note

F Enable

Diagnostics

1 = Chip performs diagnostics on

power-up

R/W

E:0 Reserved Internal reserved - do not modify

Table 6.964 Global Diagnostic Provisioning: Address 1E.C400

Bit Name Description Type Default Note

Table 6.962 Global Control 2: Address 1E.C001

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6.11.29 Global Thermal Provisioning 1: Address 1E.C420

6.11.30 Global Thermal Provisioning 2: Address 1E.C421

Bit Name Description Type Default Note

F:0 Reserved 0 [F:0] Internal reserved - do not modify R/W

0x0000

Table 6.965 Global Thermal Provisioning 1: Address 1E.C420

Bit Name Description Type Default Note

F:0 High Temp Failure

Threshold [F:0]

[F:0] of high temperature failure

threshold

R/W

0x4600 2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 70°C.

In XENPAK mode, F/W will use the

XENPAK register 1.A000 - 1.A001: instead

of this register.

NOTE! All Thresholds are orthogonal and

can be set to any value regardless the

value of the other thresholds. i.e.

High-Temperature-Warning (1E.C423)

could be higher than

High-Temperature-Failure (1E.C421).

Table 6.966 Global Thermal Provisioning 2: Address 1E.C421

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6.11.31 Global Thermal Provisioning 3: Address 1E.C422

Bit Name Description Type Default Note

F:0 Low Temp Failure

Threshold [F:0]

[F:0] of low temperature failure

threshold

R/W

0x0000 2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 0°C.

In XENPAK mode, F/W will use the

XENPAK register 1.A002 - 1.A003: instead

of this register.

NOTE! All Thresholds are orthogonal and

can be set to any value regardless the

value of the other thresholds. i.e.

High-Temperature-Warning (1E.C423)

could be higher than

High-Temperature-Failure (1E.C421).

Table 6.967 Global Thermal Provisioning 3: Address 1E.C422

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6.11.32 Global Thermal Provisioning 4: Address 1E.C423

Bit Name Description Type Default Note

F:0 High Temp Warning

Threshold [F:0]

[F:0] of high temperature warning

threshold

R/W

0x3C00 2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD008.

Default is 60°C.

In XENPAK mode, F/W will use the

XENPAK register 1.A004 - 1.A005: instead

of this register.

NOTE! All Thresholds are orthogonal and

can be set to any value regardless the

value of the other thresholds. i.e.

High-Temperature-Warning (1E.C423)

could be higher than

High-Temperature-Failure (1E.C421).

Table 6.968 Global Thermal Provisioning 4: Address 1E.C423

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6.11.33 Global Thermal Provisioning 5: Address 1E.C424

6.11.34 Global LED Provisioning 1: Address 1E.C430

Bit Name Description Type Default Note

F:0 Low Temp Warning

Threshold [F:0]

[F:0] of low temperature warning

threshold

R/W

0x0A00 2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 10°C.

In XENPAK mode, F/W will use the

XENPAK register 1.A006 - 1.A007: instead

of this register.

NOTE! All Thresholds are orthogonal and

can be set to any value regardless the

value of the other thresholds. i.e.

High-Temperature-Warning (1E.C423)

could be higher than

High-Temperature-Failure (1E.C421).

Table 6.969 Global Thermal Provisioning 5: Address 1E.C424

Bit Name Description Type Default Note

F LED #0 5 Gb/s

Link Established

1 = LED is on when link connects at 5 Gb/s R/W

E LED #0 2.5 Gb/s

Link Established

1 = LED is on when link connects at 2.5 Gb/s R/W

D:9 Reserved

Provisioning

C430 [4:0]

Reserved for future use R/W

0x00

Table 6.970 Global LED Provisioning 1: Address 1E.C430

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8 LED #0 Manual

Set

1 = LED On R/W

7 LED #0 10 Gb/s

Link Established

1 = LED is on when link connects at 10 Gb/s R/W

6 LED #0 1 Gb/s

Link Established

1 = LED is on when link connects at 1 Gb/s R/W

5 LED #0 100

Mb/s Link

Established

1 = LED is on when link connects at 100 Mb/s. R/W

4LED #0

Connecting

1 = LED is on when attempting to connect. R/W

3 LED #0 Receive

Activity

1 = LED toggles on receive activity R/W

2 LED #0 Transmit

Activity

1 = LED toggles on transmit activity R/W

1:0 LED #0 Activity

Stretch [1:0]

[1:0]

0x3 = stretch activity by 100 ms

0x2 = stretch activity by 60 ms

0x1 = stretch activity by 28 ms

0x0 = no stretching

R/W

0x3

Bit Name Description Type Default Note

Table 6.970 Global LED Provisioning 1: Address 1E.C430

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6.11.35 Global LED Provisioning 2: Address 1E.C431

Bit Name Description Type Default Note

F LED #1 5 Gb/s

Link Established

1 = LED is on when link connects at 5 Gb/s R/W

E LED #1 2.5 Gb/s

Link Established

1 = LED is on when link connects at 2.5 Gb/s R/W

D:9 Reserved

Provisioning

C431 [4:0]

Reserved for future use R/W

0x00

Table 6.971 Global LED Provisioning 2: Address 1E.C431

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8 LED #1 Manual

Set

1 = LED On R/W

7 LED #1 10 Gb/s

Link Established

1 = LED is on when link connects at 10 Gb/s R/W

6 LED #1 1 Gb/s

Link Established

1 = LED is on when link connects at 1 Gb/s R/W

5 LED #1 100

Mb/s Link

Established

1 = LED is on when link connects at 100 Mb/s. R/W

4LED #1

Connecting

1 = LED is on when attempting to connect. R/W

3 LED #1 Receive

Activity

1 = LED toggles on receive activity R/W

2 LED #1 Transmit

Activity

1 = LED toggles on transmit activity R/W

1:0 LED #1 Activity

Stretch [1:0]

[1:0]

0x3 = stretch activity by 100 ms

0x2 = stretch activity by 60 ms

0x1 = stretch activity by 28 ms

0x0 = no stretching

R/W

0x3

Bit Name Description Type Default Note

Table 6.971 Global LED Provisioning 2: Address 1E.C431

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AQR405 Revision 0.11 - January 5, 2015

6.11.36 Global LED Provisioning 3: Address 1E.C432

Bit Name Description Type Default Note

F LED #2 5 Gb/s

Link Established

1 = LED is on when link connects at 5 Gb/s R/W

E LED #2 2.5 Gb/s

Link Established

1 = LED is on when link connects at 2.5 Gb/s R/W

D:9 Reserved

Provisioning

C432 [4:0]

Reserved for future use R/W

0x00

Table 6.972 Global LED Provisioning 3: Address 1E.C432

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6.11.37 Global LED Provisioning 4: Address 1E.C433

8 LED #2 Manual

Set

1 = LED On R/W

7 LED #2 10 Gb/s

Link Established

1 = LED is on when link connects at 10 Gb/s R/W

6 LED #2 1 Gb/s

Link Established

1 = LED is on when link connects at 1 Gb/s R/W

5 LED #2 100

Mb/s Link

Established

1 = LED is on when link connects at 100 Mb/s. R/W

4LED #2

Connecting

1 = LED is on when attempting to connect. R/W

3 LED #2 Receive

Activity

1 = LED toggles on receive activity R/W

2 LED #2 Transmit

Activity

1 = LED toggles on transmit activity R/W

1:0 LED #2 Activity

Stretch [1:0]

[1:0]

0x3 = stretch activity by 100 ms

0x2 = stretch activity by 60 ms

0x1 = stretch activity by 28 ms

0x0 = no stretching

R/W

0x3

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.973 Global LED Provisioning 4: Address 1E.C433

Bit Name Description Type Default Note

Table 6.972 Global LED Provisioning 3: Address 1E.C432

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6.11.38 Global LED Provisioning 5: Address 1E.C434

6.11.39 Global LED Provisioning 6: Address 1E.C435

6.11.40 Global LED Provisioning 7: Address 1E.C436

6.11.41 Global LED Provisioning 8: Address 1E.C437

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.974 Global LED Provisioning 5: Address 1E.C434

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.975 Global LED Provisioning 6: Address 1E.C435

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.976 Global LED Provisioning 7: Address 1E.C436

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 LED Operation

Mode

1 = LED link activity in Mode #2

0 = LED link activity in Aquantia classic mode

R/W

0 When set to 1, the LED blinking rate is

based on Mode #2 algorithm. When set

to 0, the LED blinking rate is based on

the classic Aquantia algorithm.

Table 6.977 Global LED Provisioning 8: Address 1E.C437

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6.11.42 Global LED Provisioning 15: Address 1E.C43E

6.11.43 Global General Provisioning 1: Address 1E.C440

6.11.44 Global General Provisioning 2: Address 1E.C441

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.978 Global LED Provisioning 15: Address 1E.C43E

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.979 Global General Provisioning 1: Address 1E.C440

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E MDIO Broadcast

Mode Enable

1 = Enable broadcast on address set in

1E.C446

0 = Disable broadcast on n address set

in 1E.C446

R/W

0 When enabled, writes and load MMD address

opcodes are supported. Read opcodes are

ignored.

D MDIO Read

MSW First

Enable

1 = MSW of counter must be read first

0 = LSW of counter must be read first

R/W

0 This bit configures whether the MSW or LSW

must be read first for counters greater than 16

bits.

C:5 Reserved Internal reserved - do not modify

Table 6.980 Global General Provisioning 2: Address 1E.C441

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AQR405 Revision 0.11 - January 5, 2015

6.11.45 Global General Provisioning 3: Address 1E.C442

4 MDIO Drive

Configuration

0 = MDIO driver is in normal mode

1 = MDIO driver is in open drain mode

R/W

0 When the MDIO driver is in open drain mode

during a read cycle, “0” data will be actively

driven out of the MDIO, “1” data will set the

MDIO driver in high impedance state and an

external pullup will set the MDIO line to “1”.

The Turn-Around “0” will also be actively driven

out of the MDIO, therefore in open drain mode,

the Turn-Around is still “Z0”.

3 MDIO Preamble

Detection

Disable

1 = Suppress preamble detection on

MDIO

0 = Enable preamble detection on MDIO

R/W

2 Reserved Internal reserved - do not modify

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Daisy Chain

Reset

1 = Reset the daisy chain R/W 0 Toggling this bit from 0 to 1 will reload the

IRAM and DRAM and reset the uP. The uP will

be in uP run stall during the reload process.

After the reload process, uP run stall will be

de-asserted and the uP reset will be asserted.

Note that before setting this bit, the "Soft

Reset" bit needs to be de-asserted.

Table 6.981 Global General Provisioning 3: Address 1E.C442

Bit Name Description Type Default Note

Table 6.980 Global General Provisioning 2: Address 1E.C441

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6.11.46 Global General Provisioning 4: Address 1E.C443

6.11.47 Global General Provisioning 5: Address 1E.C444

6.11.48 Global General Provisioning 6: Address 1E.C445

6.11.49 Global General Provisioning 7: Address 1E.C446

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.982 Global General Provisioning 4: Address 1E.C443

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.983 Global General Provisioning 5: Address 1E.C444

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.984 Global General Provisioning 6: Address 1E.C445

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.985 Global General Provisioning 7: Address 1E.C446

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6.11.50 Global General Provisioning 8: Address 1E.C447

6.11.51 Global General Provisioning 9: Address 1E.C448

6.11.52 Global General Provisioning 10: Address 1E.C449

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4:0 MDIO Broadcast

Address

Configuration

[4:0]

Broadcast address R/W

0x1F Allows setting the broadcast address. By

default this is set to 0x1F

Table 6.986 Global General Provisioning 8: Address 1E.C447

Bit Name Description Type Default Note

F:0 Reserved Internal reserved - do not modify

Table 6.987 Global General Provisioning 9: Address 1E.C448

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6:0 MDIO Preamble

Length [6:0]

MDIO Preamble Length R/W 0x02

Table 6.988 Global General Provisioning 10: Address 1E.C449

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6.11.53 Global NVR Provisioning 1: Address 1E.C450

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A:8 NVR Data

Length [2:0]

NVR data length ranges from 0 bytes to

4 bytes

R/W

0x4 This sets the length of the data burst used in

read and write operations.

7 Reserved Internal reserved - do not modify

6:4 NVR Dummy

Length [2:0]

NVR dummy length ranges from 0 bytes

to 4 bytes

R/W

0x0 This sets the length of the dummy field used in

some manufacturer’s read status and write

status operations.

3:2 Reserved Internal reserved - do not modify

1:0 NVR Address

Length [1:0]

NVR address length ranges from 0 bytes

up to 3 bytes

R/W

0x2 This sets the length of the address field used in

read and write operations. Use of this field is

enabled via Bit 8 of “Global NVR Provisioning

2: Address 1E.C451” on page 578.

Table 6.989 Global NVR Provisioning 1: Address 1E.C450

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AQR405 Revision 0.11 - January 5, 2015

6.11.54 Global NVR Provisioning 2: Address 1E.C451

6.11.55 Global NVR Provisioning 3: Address 1E.C452

Bit Name Description Type Default Note

F:9 Reserved Internal reserved - do not modify

8 NVR Address

Length Override

0 = NVR address length is based on the

“NVR_SIZE” pin.

1 = NVR address length is based on the

"NVR Address Length [1:0]" register

R/W

0 When this bit = 0 and NVR_SIZE pin = 0, the

NVR address length is 2 bytes. When this bit =

0 and the NVR_SIZE pin = 1, the NVR address

length is 3 bytes. When this bit = 1 the NVR

address length is from the "NVR Address

Length [1:0]"

7:0 NVR Clock

Divide [7:0]

NVR clock divide. Clock frequency is

divided by the NVR clock divide + 1

R/W

0xA0

Table 6.990 Global NVR Provisioning 2: Address 1E.C451

Bit Name Description Type Default Note

F:2 Reserved Internal reserved - do not modify

1 NVR Daisy

Chain Clock

Divide Override

1 = Override NVR clock divide when in

daisy chain master mode

R/W 0 When in daisy chain master mode, the clock

divide configuration is received from the

FLASH. This bit will override the clock divide

configuration from the FLASH with the "NVR

Clock Divide [7:0]" .

0 NVR Daisy

Chain Disable

1 = Disable the Daisy Chain R/W 0 When in daisy chain master mode, the daisy

chain and MDIO can both access the SPI.

Setting this bit to 1 will disable the daisy chain

from accessing the SPI and force it into a reset

state.

Table 6.991 Global NVR Provisioning 3: Address 1E.C452

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6.11.56 Global NVR Provisioning 4: Address 1E.C453

Bit Name Description Type Default Note

F:5 Reserved Internal reserved - do not modify

4 NVR Reset 1 = Reset SPI R/W 0

3:0 Reserved Internal reserved - do not modify

Table 6.992 Global NVR Provisioning 4: Address 1E.C453

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6.11.57 Global Reserved Provisioning 1: Address 1E.C470

Bit Name Description Type Default Note

F Diagnostics

Select

1 = Provide Extended MDI Diagnostics

Information.

0 = Provide normal cable diagnostics

R/W

0These bits select what sort of cable diagnostics to

perform. For regular cable diagnostics, Bit F is set to

zero, and the diagnostics are triggered by setting Bit

4. For extended diagnostics, Bit F is set to 1, and the

desired extended diagnostics are selected by Bits

E:D. The routine is then triggered by setting Bit 4.

Each of the extended diagnostic routines present

data for all for MDI pairs (A, B, C, D) consecutively,

and after the data for each channel is gathered Bits

F:D are reset. To get the data for the next pair, Bits

F:D must be set back to the desired value (which

must be the same as the initial channel). This

continues until the data for all channels has been

gathered. The address in memory where the data is

stored is given in 1E.C802 and 1E.C804.

For the case of PSD, the structure is as follows:

Int32 info

Int16 data[Len]

Info = Len << 16 | TxEnable << 8 | Pair (0 = A, etc.)

For TDR:

Int32 info

Int16 tdr_A[Len]

Int16 tdr_B[Len]

Int16 tdr_C[Len]

Int16 tdr_D[Len]

Info = Len << 16 | Channel

TDR data is from the current pair to all other pairs.

At the end of retrieving extended MDI diag data, the

part will be reset. Conversely the only way to exit

this routine once it starts is to issue a PMA reset.

E:D Extended MDI

Diagnostics

Select [1:0]

0x0 = TDR Data

0x1 = RFI Channel PSD

0x2 = Noise PSD while the local Tx is Off

0x3 = Noise PSD while the local Tx is On

R/W

0x0

Table 6.993 Global Reserved Provisioning 1: Address 1E.C470

581

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6.11.58 Global Reserved Provisioning 2: Address 1E.C471

C:8 Reserved Internal reserved - do not modify

7 Trigger

Diagnostic

Interrupt

1 = Trigger Diagnostic Interrupt R/W

6:5 Reserved Internal reserved - do not modify

4 Initiate Cable

Diagnostics

1 = Perform cable diagnostics R/W

0 Perform cable diagnostics regardless of link

state. If link is up, setting this bit will cause the

link to drop while diagnostics are performed.

This bit is self-clearing upon completion of the

cable diagnostics.

NOTE!! This is a processor intensive

operation. Completion of this operation can

also be monitored via 1E.C831.F

3:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

F:7 Reserved Internal reserved - do not modify

6 Enable

Daisy-Chain

Hop-Count

Override

1 = Hop-count is set by Bits 5:0

0 = Hop-count is determined by the

daisy-chain

R/W

0 Daisy-Chain Hop-Count Override should be

used during MDIO boot-load operation, as the

daisy-chain hop-count does not function when

the daisy-chain is disabled (1E.C452.0).

Setting this bit tells the processor where in the

daisy-chain it is, so that the provisioning

operation will function correctly.

5:0 Daisy-Chain

Hop-Count

Override Value

[5:0]

The value to use for the PHY’s

daisy-chain hop-count. Valid values are

from 0 -> 47

R/W

0x00

Table 6.994 Global Reserved Provisioning 2: Address 1E.C471

Bit Name Description Type Default Note

Table 6.993 Global Reserved Provisioning 1: Address 1E.C470

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AQR405 Revision 0.11 - January 5, 2015

6.11.59 Global Reserved Provisioning 3: Address 1E.C472

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E Enable VDD

Power Supply

Tuning

1 = Enable external VDD power supply

tuning

0 = Disable external VDD power supply

tuning is disabled

R/W

0 This bit controls whether the PHY attempts to

tune the external VDD power supply via the

SMBus. This bit is only operational if the

external supply is present. (See 1E.C472.6)

D:7 Reserved Internal reserved - do not modify

6 Tunable

External VDD

Power Supply

Present

1 = Tunable external VDD power supply

present

0 = No tunable external VDD power

supply present

R/W

0 This bit must be set if tuning of external power

supply is desired.

5:2 External VDD

Change Request

[3:0]

The amount of VDD change requested

by firmware, in mV (2’s complement

value).

R/W

0x0

1 Enable XENPAK

1 = XENPAK register space enabled

0 = XENPAK register space disabled

R/W

0 Enable 5th

Channel RFI

Cancellation

1 = 5th channel and RFI cancellers

operation enabled

0 = 5th channel AFE is powered down,

5th channel digital is clock gated,

RFI cancellers are disabled

R/W

0 Note: The value of this bit at the time of

Autonegotiation sets the local PHY behavior

until the next time Autonegotiation occurs.

Table 6.995 Global Reserved Provisioning 3: Address 1E.C472

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6.11.60 Global Reserved Provisioning 4: Address 1E.C473

Bit Name Description Type Default Note

F:B Reserved Internal reserved - do not modify

A:8 Rate Transition

Request [2:0]

0 = No Transition

1 = Reserved

2 = Reserved

3 = Retrain at 10G

4 = Retrain at 5G

5 = Retrain at 2.5G

6 = Retrain at 1G

7 = Reserved

R/W

0x0

7:0 Training SNR

[7:0]

SNR during 10G training on the worst

channel. SNR is in steps of 0.1dB

R/W

0x00 The SNR margin that is enjoyed by the worst

channel, over and above the minimum SNR

required to operate at a BER of 10-12. It is

reported with 0.1 dB of resolution to an

accuracy of 0.5 dB within the range of -12.7 dB

to 12.7 dB. The number is in offset binary, with

0.0 dB represented by 0x8000.

Table 6.996 Global Reserved Provisioning 4: Address 1E.C473

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AQR405 Revision 0.11 - January 5, 2015

6.11.61 Global Reserved Provisioning 5: Address 1E.C474

6.11.62 Global Reserved Provisioning 6: Address 1E.C475

Bit Name Description Type Default Note

F:1 Reserved

Provisioning 5

[F:1]

Reserved for future use R/W

0x0000

0 NVR Daisy

Chain Kickstart

1 = Kickstart the Daisy Chain R/W 0 When in daisy chain master mode, the PHY0

can kickstart the daisy chain. The kickstart will

not reload the IRAM/DRAM or reset the uP for

PHY0. It will just read the FLASH and transfer

the FLASH data to the daisy chain.

Table 6.997 Global Reserved Provisioning 5: Address 1E.C474

Bit Name Description Type Default Note

F:E Reserved Internal reserved - do not modify

D Smart

Power-Down

Status

1 = Smart Power-Down Active

0 = Smart Power-Down Inactive

R/W

C Reserved

Provisioning 6

Internal reserved - do not modify R/W

B CFR LP Disable

Timer

1 = Link partner requires cfr_disable

timer

0 = Link partner does not require

cfr_disable timer

R/W

Table 6.998 Global Reserved Provisioning 6: Address 1E.C475

585

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ACFR LP

Extended

Maxwait

1 = Link partner requires extended

maxwait

0 = Link partner does not require

extended maxwait

R/W

9 CFR LP THP 1 = Link partner requires local PHY to

enable THP

0 = Link partner does not require local

PHY to enable THP

R/W

8 CFR LP Support 1 = Link partner supports Cisco Fast

Retrain

0 = Link partner does support Cisco Fast

Retrain

R/W

7CFR Disable

Timer

1 = Local PHY requires cfr_disable timer

0 = Local PHY does not require

cfr_disable timer

R/W

6 CFR Extended

Maxwait

1 = Local PHY requires extended

maxwait

0 = Local PHY does not require

extended maxwait

R/W

5 CFR THP 1 = Local PHY requires local PHY to

enable THP

0 = Local PHY does not require local

PHY to enable THP

R/W

Bit Name Description Type Default Note

Table 6.998 Global Reserved Provisioning 6: Address 1E.C475

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AQR405 Revision 0.11 - January 5, 2015

4 CFR Support 1 = Local PHY supports Cisco Fast

Retrain

0 = Local PHY does support Cisco Fast

Retrain

R/W

3 Deadlock

Avoidance

Enable

1 = SPD with deadlock avoidance: PHY

transmits autonegotiation pulses

(FLPs) at a slower rate (~ 1 FLP/

100ms) than specified by

autonegotiation standard (~1 FLP /

8.25ms). Receiver is active and able

to detect the pulses.

0 = SPD without deadlock avoidance:

PHY transmitter is shut down, no

autonegotiation pulses are sent on

the line but the receiver is active and

able to detect the pulses

R/W

2 Smart

Power-Down

Enable

1 = Enable smart power down mode

0 = Smart power-down mode disabled

R/W

0 Smart power down (SPD) is the lowest power

mode at which PHY is able to autonegotiate.

SPD can be enabled with bit 1E.C475.2

1:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.998 Global Reserved Provisioning 6: Address 1E.C475

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6.11.63 Global Reserved Provisioning 9: Address 1E.C478

6.11.64 Global Reserved Provisioning 10: Address 1E.C479

Bit Name Description Type Default Note

F DTE Enable 1 = Enable DTE

0 = Disable DTE

R/W

E:B DTE Drop

Reporting Timer

[3:0]

Number of seconds between loss of link

partner filter and assertion of

no-power-needed state, in 5 second

increments (e.g. 0x4 = 20 seconds).

R/W

0x0 These bits are used to set how long the PHY

waits after it no longer detects the link partner

filter before declaring that power is not needed.

A:0 Reserved

Provisioning 9

[A:0]

Reserved for future use R/W

0x000

Table 6.999 Global Reserved Provisioning 9: Address 1E.C478

Bit Name Description Type Default Note

F Power Up Stall 1 = Stall FW at Power Up

0 = Unstall the FW

R/W

0 This bit needs to be provisioned in Power Up

Init for firmware to stall.

E:0 Reserved

Provisioning 10

[E:0]

Reserved for future use R/W

0x0000

Table 6.1000 Global Reserved Provisioning 10: Address 1E.C479

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AQR405 Revision 0.11 - January 5, 2015

6.11.65 Global Reserved Provisioning 11: Address 1E.C47A

Bit Name Description Type Default Note

F:B Loopback

Control [4:0]

0x00 = No loopback

0x01 = System Interface - System Loopback

0x02 = System Interface - System Loopback

with Passthrough

0x03 = System Interface - Network Loopback

0x04 = System Interface - Network Loopback

with Passthrough

0x05 = System Interface - Network Loopback

with Passthrough and Merge

0x06 = System Interface - Peer-to-peer

loopback

0x07 - 0x08 = Reserved

0x09 = Network Interface - System Loopback

0x0A = Network Interface - System

Loopback with Passthrough

0x0B = Network Interface - Network

Loopback

0x0C = Network Interface - Network

Loopback with Passthrough

0x0D = Network Interface - Peer-to-peer

loopback

0x0E - 0x0F = Reserved

0x10 = Cross-connect System Loopback

0x11 = Cross-connect Network Loopback

0x12 - 0x13 = Reserved

0x14 = Network Interface - System Loopback

via Loopback Plug

0x15 - 0x1F = Reserved

R/W

0x00 These bits, in conjunction with the chip

configuration and the rate (Bits 1:0), select the

loopback to configure for the chip. Setting one

of these loopbacks provisions the chip for the

specified loopback. Upon clearing the

loopback, the chip returns to it’s configuration

prior to entering loopback (irregardless of

whether other loopbacks were selected after

the initial loopback).

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F.

The controls in this register are identical to,

and mirrored with, the controls in 4.C444.

A:6 Reserved

Provisioning 11

[4:0]

Reserved for future use R/W

0x00

Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A

589

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5MDI Packet

Generation

1 = CRPAT packet generation out MDI

interface

0 = No CRPAT packet generation out

MDI interface

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

on the MDI interface at the selected rate.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

The controls in this register are identical to,

and mirrored with, the controls in 4.C444.

4 Look-Aside Port

Packet

Generation

1 = CRPAT packet generation out 10G

look-aside interface (KR0)

0 = No CRPAT packet generation out

10G look-aside interface (KR0)

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

on KR0.

NOTE!! This only functions if KR1 (SERDES2)

is selected as the system interface in

(4.C441.F:E).

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

The controls in this register are identical to,

and mirrored with, the controls in 4.C444.

Bit Name Description Type Default Note

Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A

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3 System I/F

Packet

Generation

1 = CRPAT packet generation out 10G

system interface

0 = No CRPAT packet generation out

10G system interface

R/W

0 Selecting this mode of operation causes the

CRPAT packet generator in the PHY to output

CRPAT packets on the selected 10G system

interface (4.C441.F:E)

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

The controls in this register are identical to,

and mirrored with, the controls in 4.C444.

2:0 Rate [2:0] 0x7 - 0x6 = reserved

0x5 = 5G

0x4 = 2.5G

0x3 = 10G

0x2 = 1G

0x1 = 100M

0x0 = reserved

R/W

0x0 These bits select the rate for the loopback and

packet generation. SERDES configuration, as

well autonegotiation is controlled accordingly

when a loopback is selected. For instance, if

100M system loopback on the network

interface is selected, SGMII on the system

interface is enabled to connect at 100M, and if

passthrough is enabled 100BASE-TX will be

the only advertised rate and will force a

re-autonegotiation if not already connected at

100M.

NOTE!! This is a processor intensive

operation. Completion of this operation can be

monitored via 1E.C831.F

The controls in this register are identical to,

and mirrored with, the controls in 4.C444.

Bit Name Description Type Default Note

Table 6.1001 Global Reserved Provisioning 11: Address 1E.C47A

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6.11.66 Global Reserved Provisioning 12: Address 1E.C47B

6.11.67 PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C

6.11.68 PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D

Bit Name Description Type Default Note

F:2 Reserved

Provisioning 12

[D:0]

Reserved for future use R/W

0x0000

1 Enable MACSec 1 = MACSec functionality is enabled

0 = MACSec functionality is disabled

R/W

0 If this bit is 1, the PTP/SEC block will be

included in the data path, regardless of

operating mode.

0 Enable PTP 1 = PTP functionality is enabled

0 = PTP functionality is disabled

R/W

0 If this bit is 1, the PTP/SEC block will be

included in the data path, regardless of

operating mode.

Table 6.1002 Global Reserved Provisioning 12: Address 1E.C47B

Bit Name Description Type Default Note

F:0 PIF Mailbox

Address [F:0]

The least 16 bits of the PIF address to

read or write.

R/W

0x0000

Table 6.1003 PIF Mailbox Control 1<Global Reserved Provisioning 13>: Address 1E.C47C

Bit Name Description Type Default Note

F:0 PIF Mailbox

Data [F:0]

The data to be written, or that had been

read.

R/W

0x0000

Table 6.1004 PIF Mailbox Control 2<Global Reserved Provisioning 14>: Address 1E.C47D

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6.11.69 PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E

6.11.70 PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F

Bit Name Description Type Default Note

F:C Reserved PIF

Mailbox Control

3 [3:0]

Reserved for future use R/W

0x0

B:8 PIF Mailbox

Command Type

[3:0]

0 = No Action

1 = Read

2 = Write

R/W

0x0 System SW writes non-zero value to start a

PIF command.

7:0 PIF Mailbox

MMD [7:0]

MMD (upper 8 bits) of the PID address to

read or write.

R/W

0x00

Table 6.1005 PIF Mailbox Control 3<Global Reserved Provisioning 15>: Address 1E.C47E

Bit Name Description Type Default Note

F:4 Reserved PIF

Mailbox Control

4 [B:0]

Reserved for future use R/W

0x000

3:0 PIF Mailbox

Command

Status [3:0]

0 = Idle

1 = Command completed

2 = Command did not complete

R/W

0x0 System SW should write 0 before writing

Command Type to clear completion status

Table 6.1006 PIF Mailbox Control 4<Global Reserved Provisioning 16>: Address 1E.C47F

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6.11.71 Global SMBus 0 Provisioning 6: Address 1E.C485

6.11.72 Global SMBus 1 Provisioning 6: Address 1E.C495

6.11.73 Global EEE Provisioning 1: Address 1E.C4A0

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:1 SMB 0 Slave

Address [7:1]

SMB slave address configuration R/W 0x00

0 Reserved Internal reserved - do not modify

Table 6.1007 Global SMBus 0 Provisioning 6: Address 1E.C485

Bit Name Description Type Default Note

F:8 Reserved Internal reserved - do not modify

7:1 SMB 1 Slave

Address [7:1]

SMB slave address configuration R/W 0x00

0 Reserved Internal reserved - do not modify

Table 6.1008 Global SMBus 1 Provisioning 6: Address 1E.C495

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 EEE Mode 1 = EEE mode of operation R/W

0 EEE mode of operation (0=disable, 1=enable,

default:0)

Table 6.1009 Global EEE Provisioning 1: Address 1E.C4A0

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6.11.74 Global Cable Diagnostic Status 1: Address 1E.C800

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E:C Pair A Status

[2:0]

[F:D]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

011= Connected to Pair D

010= Connected to Pair C

001= Connected to Pair B

000= OK

RO This register summarizes the worst impairment

on Pair A.

B Reserved Internal reserved - do not modify

A:8 Pair B Status

[2:0]

[C:A]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

011= Connected to Pair A

010= Connected to Pair D

001= Connected to Pair C

000= OK

RO This register summarizes the worst impairment

on Pair B.

7 Reserved Internal reserved - do not modify

6:4 Pair C Status

[2:0]

[9:7]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

011= Connected to Pair B

010= Connected to Pair A

001= Connected to Pair D

000= OK

RO This register summarizes the worst impairment

on Pair C.

Table 6.1010 Global Cable Diagnostic Status 1: Address 1E.C800

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6.11.75 Global Cable Diagnostic Status 2: Address 1E.C801

3 Reserved Internal reserved - do not modify

2:0 Pair D Status

[2:0]

[6:4]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

011= Connected to Pair C

010= Connected to Pair B

001= Connected to Pair A

000= OK

RO This register summarizes the worst impairment

on Pair D.

Bit Name Description Type Default Note

F:8 Pair A Reflection #1

[7:0]

The distance in meters, accurate to ±1m, of

the first of the four worst reflections seen by

the PHY on Pair A

RO The distance to this reflection is given in

"Global Cable Diagnostic Impedance 1:

Address 1E.C880" . A value of zero

indicates that this reflection does not

exist or was not computed.

7:0 Pair A Reflection #2

[7:0]

The distance in meters, accurate to ±1m, of

the second of the four worst reflections

seen by the PHY on Pair A

Table 6.1011 Global Cable Diagnostic Status 2: Address 1E.C801

Bit Name Description Type Default Note

Table 6.1010 Global Cable Diagnostic Status 1: Address 1E.C800

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6.11.76 Global Cable Diagnostic Status 3: Address 1E.C802

6.11.77 Global Cable Diagnostic Status 4: Address 1E.C803

6.11.78 Global Cable Diagnostic Status 5: Address 1E.C804

Bit Name Description Type Default Note

F:0 Impulse Response

MSW [F:0]

The MSW of the memory location that

contains the start of the impulse response

data for the Extended Diagnostic type in

1E.C470.E:D

RO See 1E.C470 for more information

Table 6.1012 Global Cable Diagnostic Status 3: Address 1E.C802

Bit Name Description Type Default Note

F:8 Pair B Reflection #1

[7:0]

The distance in meters, accurate to ±1m, of

the first of the four worst reflections seen by

the PHY on Pair B

RO The distance to this reflection is given in

"Global Cable Diagnostic Impedance 2:

Address 1E.C881" . A value of zero

indicates that this reflection does not

exist or was not computed.

7:0 Pair B Reflection #2

[7:0]

The distance in meters, accurate to ±1m, of

the second of the four worst reflections

seen by the PHY on Pair B

Table 6.1013 Global Cable Diagnostic Status 4: Address 1E.C803

Bit Name Description Type Default Note

F:0 Impulse Response

LSW [F:0]

The LSW of the memory location that

contains the start of the impulse response

data for the Extended Diagnostic type

specified in 1E.C470.E:D

RO See 1E.C470 for more information

Table 6.1014 Global Cable Diagnostic Status 5: Address 1E.C804

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6.11.79 Global Cable Diagnostic Status 6: Address 1E.C805

6.11.80 Global Cable Diagnostic Status 7: Address 1E.C806

6.11.81 Global Cable Diagnostic Status 8: Address 1E.C807

Bit Name Description Type Default Note

F:8 Pair C Reflection #1

[7:0]

The distance in meters, accurate to ±1m, of

the first of the four worst reflections seen by

the PHY on Pair C

RO The distance to this reflection is given in

"Global Cable Diagnostic Impedance 3:

Address 1E.C882" . A value of zero

indicates that this reflection does not

exist or was not computed.

7:0 Pair C Reflection #2

[7:0]

The distance in meters, accurate to ±1m, of

the second of the four worst reflections

seen by the PHY on Pair C

Table 6.1015 Global Cable Diagnostic Status 6: Address 1E.C805

Bit Name Description Type Default Note

F:0 Reserved 1 [F:0] Reserved for future use RO

Table 6.1016 Global Cable Diagnostic Status 7: Address 1E.C806

Bit Name Description Type Default Note

F:8 Pair D Reflection #1

[7:0]

The distance in meters, accurate to ±1m, of

the first of the four worst reflections seen by

the PHY on Pair D

RO The distance to this reflection is given in

"Global Cable Diagnostic Impedance 4:

Address 1E.C883" . A value of zero

indicates that this reflection does not

exist or was not computed.

7:0 Pair D Reflection #2

[7:0]

The distance in meters, accurate to ±1m, of

the second of the four worst reflections

seen by the PHY on Pair D

Table 6.1017 Global Cable Diagnostic Status 8: Address 1E.C807

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6.11.82 Global Thermal Status 1: Address 1E.C820

6.11.83 Global Thermal Status 2: Address 1E.C821

6.11.84 Global General Status 1: Address 1E.C830

Bit Name Description Type Default Note

F:0 Temperature [F:0] [F:0] of temperature RO 2’s complement value with the LSB

representing 1/256 of a degree Celsius.

This corresponds to -40°C = 0xD800.

Default is 70°C. This is a mirror of the

XENPAK register 1.A060 - 1.A061. The

mirror is performed in H/W.

Table 6.1018 Global Thermal Status 1: Address 1E.C820

Bit Name Description Type Default Note

F:1 Reserved Internal reserved - do not modify

0 Temperature Ready 1 = Temperature measurement is

valid

RO This is a mirror of the XENPAK register

1.A06E.

Table 6.1019 Global Thermal Status 2: Address 1E.C821

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify 0

E High Temperature

Failure State

1 = High temperature failure

threshold has been exceeded

RO In XENPAK mode, F/W will copy this register to

the 1.A070.7 register.

Table 6.1020 Global General Status 1: Address 1E.C830

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D Low Temperature

Failure State

1 = Low temperature failure

threshold has been exceeded

RO In XENPAK mode, F/W will copy this register to

the 1.A070.6 register.

C High Temperature

Warning State

1 = High temperature warning

threshold has been exceeded

RO In XENPAK mode, F/W will copy this register to

the 1.A074.7 register.

B Low Temperature

Warning State

1 = Low temperature warning

threshold has been exceeded

RO In XENPAK mode, F/W will copy this register to

the 1.A074.6 register.

A:0 Reserved Internal reserved - do not modify

Bit Name Description Type Default Note

Table 6.1020 Global General Status 1: Address 1E.C830

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6.11.85 Global General Status 2: Address 1E.C831

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Bit Name Description Type Default Note

F Processor

Intensive MDIO

Operation In-

Progress

1 = PHY microprocessor is busy with a

processor-intensive MDIO operation

0 = Processor-intensive MDIO operation

completed

RO This bit should may be used with certain

processor-intensive MDIO commands (such as

Loopbacks, Test Modes, Low power modes,

Tx-Disable, Restart autonegotiation, Cable

Diagnostics, etc.) that take longer than an MDIO

cycle to complete. Upon receiving an MDIO

command that involves the PHY’s microprocessor,

this bit is set, and when the command is completed,

this bit is cleared.

NOTE!!! This bit should be checked only after 1 ms

of issuing a processor-intensive MDIO operation.

The list of operations that set this bit are as follows:

1.0.0, PMA Loopback

1.0.B, Low power mode

1.9.4:0, Tx Disable

1.84, 10G Test modes

1.8000.5, XENPAK Control

1.9000, XENPAK Rx Fault Enable

1.9002, XENPAK Alarm Enable

1.E400.F, External loopback

3.0.B, Low power mode

3.0.E, System PCS loopback

3.C471.5, PRBS Test

3.C471.6, PRBS Test

3.E471.5, PRBS Test

3.E471.6, PRBS Test

4.0.B, Low power mode

4.0.E, PHY-XS network loopback

4.C440, Output clock control, Load SERDES parameters

4.F802.E, System loopback

4.C444.F:B, Loopback Control

4.C444.4:2, Packet generation

4.C445.C, SERDES calibration

7.0.9, Restart autonegotiation

1D.C280, 1G/100M Network loopback

1D.C500, 1G System loopback

1D.C501, 1G / 100M Test modes

1E.C470.4, Cable diagnostics

1E.C47A.F:B, Loopback Control

1E.C47A.4:2, Packet generation

E:0 Reserved Internal reserved - do not modify

Table 6.1021 Global General Status 2: Address 1E.C831

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6.11.86 Global Pin Status: Address 1E.C840

6.11.87 Global Daisy Chain Status 2: Address 1E.C842

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E Reserved Internal reserved - do not modify

D DC_MASTER_

Value of DC_MASTER_N pin:

0x1 = PHY Slave Daisy Chain Boot

0x0 = PHY Master Daisy Chain Boot

from FLASH

C:A Reserved Internal reserved - do not modify

9 Package

Connectivity

Value of the package connection pin RO

8 Reserved Internal reserved - do not modify

7 Tx Enable Current Value of Tx Enable pin RO 0 = Disable Transmitter

6 Reserved Internal reserved - do not modify

5:0 LED Pullup

State [5:0]

1 = LED output pin is pulled high

0 = LED output pin is pulled low

Table 6.1022 Global Pin Status: Address 1E.C840

Bit Name Description Type Default Note

F:0 Rx Daisy Chain

Calculated CRC

[F:0]

Rx Daisy Chain Calculated CRC RO This is the calculated daisy chain CRC.

Table 6.1023 Global Daisy Chain Status 2: Address 1E.C842

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6.11.88 Global Fault Message: Address 1E.C850

Bit Name Description Type Default Note

F:0 Message

[F:0]

Error code

describing fault

RO Code 0x8001: Firmware not compatible with chip architecture. This fault occurs when

firmware compiled for a different microprocessor core is loaded.

Code 0x8002: VCO calibration failed. This occurs when the main PLLs on chip fail to

lock: this is not possible to trigger.

Code 0x8003: XAUI calibration failed. This occurs when the XAUI PLLs fail to lock: this

is not possible to trigger.

Code 0x8005: Unexpected device ID. This occurs if the device ID programmed into the

internal E-Fuse registers in not valid: this is not possible to trigger.

Code 0x8006: Computed checksum does not match expected checksum. This occurs

when the FLASH checksum check performed at boot time fails. This only occurs when

the system boots from FLASH.

Code 0x8007: Detected a bit error in static memory. To trigger, corrupt one of the static

regions.

Code 0xC001: Illegal Instruction exception. This occurs when the processor attempts

to execute an illegal instruction. To trigger this, write an illegal instruction to program

memory. It's possible that the bit error check will trigger before the illegal instruction is

executed.

Code 0xC002 Instruction Fetch Error. Internal physical address or a data error during

instruction fetch: this is not possible to trigger.

Code 0xC003 Load Store Error. Internal physical address or data error during load

store operation: this is not possible to trigger..

Code 0xC004 Privileged Instruction. Attempt to execute a privileged operation without

sufficient privilege: this is not possible to trigger.

Code 0xC005 Unaligned Load or Store. Attempt to load or store data at an address

which cannot be handled due to alignment: this is not possible to trigger.

Code 0xC006 Instruction fetch from prohibited space: this is not possible to trigger.

Code 0xC007 Data load from prohibited space: this is not possible to trigger.

Code 0xC008 Data store into prohibited space: this is not possible to trigger.

Table 6.1024 Global Fault Message: Address 1E.C850

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6.11.89 Global Cable Diagnostic Impedance 1: Address 1E.C880

Bit Name Description Type Default Note

F Reserved 1 Reserved RO

E:C Pair A Reflection

#1 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the first worst reflection on

Pair A. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 1: Address 1E.C800"

B Reserved 2 Reserved RO

A:8 Pair A Reflection

#2 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the second worst reflection

on Pair A. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 1: Address 1E.C800"

7 Reserved 3 Reserved RO

6:4 Pair A Reflection

#3 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the third worst reflection on

Pair A. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 1: Address 1E.C800"

Table 6.1025 Global Cable Diagnostic Impedance 1: Address 1E.C880

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6.11.90 Global Cable Diagnostic Impedance 2: Address 1E.C881

3 Reserved 4 Reserved RO

2:0 Pair A Reflection

#4 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the fourth worst reflection

on Pair A. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 1: Address 1E.C800"

Bit Name Description Type Default Note

F Reserved 5 Reserved RO

E:C Pair B Reflection

#1 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the first worst reflection on

Pair B. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 2: Address 1E.C801"

B Reserved 6 Reserved RO

A:8 Pair B Reflection

#2 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the second worst reflection

on Pair B. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 2: Address 1E.C801"

7 Reserved 7 Reserved RO

Table 6.1026 Global Cable Diagnostic Impedance 2: Address 1E.C881

Bit Name Description Type Default Note

Table 6.1025 Global Cable Diagnostic Impedance 1: Address 1E.C880

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6.11.91 Global Cable Diagnostic Impedance 3: Address 1E.C882

6:4 Pair B Reflection

#3 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the third worst reflection on

Pair B. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 2: Address 1E.C801"

3 Reserved 8 Reserved RO

2:0 Pair B Reflection

#4 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the fourth worst reflection

on Pair B. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 2: Address 1E.C801"

Bit Name Description Type Default Note

F Reserved 9 Reserved RO

E:C Pair C Reflection

#1 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the first worst reflection on

Pair C. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 3: Address 1E.C802"

B Reserved 10 Reserved RO

Table 6.1027 Global Cable Diagnostic Impedance 3: Address 1E.C882

Bit Name Description Type Default Note

Table 6.1026 Global Cable Diagnostic Impedance 2: Address 1E.C881

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A:8 Pair C Reflection

#2 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the second worst reflection

on Pair C. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 3: Address 1E.C802"

7 Reserved 11 Reserved RO

6:4 Pair C Reflection

#3 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the third worst reflection on

Pair C. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 3: Address 1E.C802"

3 Reserved 12 Reserved RO

2:0 Pair C Reflection

#4 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the fourth worst reflection

on Pair C. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 3: Address 1E.C802"

Bit Name Description Type Default Note

Table 6.1027 Global Cable Diagnostic Impedance 3: Address 1E.C882

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6.11.92 Global Cable Diagnostic Impedance 4: Address 1E.C883

Bit Name Description Type Default Note

F Reserved 13 Reserved RO

E:C Pair D Reflection

#1 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the first worst reflection on

Pair D. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 4: Address 1E.C803"

B Reserved 14 Reserved RO

A:8 Pair D Reflection

#2 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the second worst reflection

on Pair D. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 4: Address 1E.C803"

7 Reserved 15 Reserved RO

6:4 Pair D Reflection

#3 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the third worst reflection on

Pair D. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 4: Address 1E.C803"

Table 6.1028 Global Cable Diagnostic Impedance 4: Address 1E.C883

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6.11.93 Global Status: Address 1E.C884

3 Reserved 16 Reserved RO

2:0 Pair D Reflection

#4 [2:0]

111 = Open Circuit (> 300Ω)

110 = High Mismatch (> 115Ω)

101 = Low Mismatch (< 85Ω)

100 = Short Circuit (< 30Ω)

0xx= No information available

RO The impedance of the fourth worst reflection

on Pair D. The corresponding length of this

reflection from the PHY is given in "Global

Cable Diagnostic Status 4: Address 1E.C803"

Bit Name Description Type Default Note

F:8 Reserved Status

0 [7:0]

Reserved RO

7:0 Cable Length

[7:0]

The estimated length of the cable in

meters

RO The length of the cable shown here is

estimated from the cable diagnostic engine

and should be accurate to +/-1m.

Table 6.1029 Global Status: Address 1E.C884

Bit Name Description Type Default Note

Table 6.1028 Global Cable Diagnostic Impedance 4: Address 1E.C883

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6.11.94 Global Reserved Status 1: Address 1E.C885

6.11.95 Global Reserved Status 2: Address 1E.C886

Bit Name Description Type Default Note

F:A Nearly Seconds

MSW[5:0]

Bits 16 to 21 of the 22 bit “Nearly

Seconds” uptime counter.

RO The “Nearly Seconds” counter is incremented

every 1024 milliseconds.

9:8 XENPAK NVR

Status [1:0]

Status of XENPAK NVR:

0: NVR not enabled

1: Last NVR operation succeeded

2: Last NVR operation failed

3: Reserved

ROS

0x0 XENPAK register space is mirrored in NVR

(SPI ROM). This register indicates the status of

the last NVR operation.

7:4 Firmware Build

ID [3:0]

Firmware Build ID ROS

0x00 Customers may receive multiple ROM images

that differ only in their provisioning. This field is

used to differentiate those images. This field is

used in conjunction with the firmware major

and minor revision numbers to uniquely

identify ROM images.

3:0 Provisioning ID

[3:0]

Provisioning ID ROS

0x00 Customers may receive multiple ROM images

that differ only in their provisioning. This field is

used to differentiate those images. This field is

used in conjunction with the firmware major

and minor revision numbers to uniquely

identify ROM images.

Table 6.1030 Global Reserved Status 1: Address 1E.C885

Bit Name Description Type Default Note

F:0 Nearly Seconds

LSW [F:0]

Bits 0 to 15 of the 22 bit “Nearly

Seconds” uptime counter

RO The “Nearly Seconds” counter is incremented

every 1024 milliseconds.

Table 6.1031 Global Reserved Status 2: Address 1E.C886

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6.11.96 Global Reserved Status 3: Address 1E.C887

Bit Name Description Type Default Note

F DTE Status 1 = Need power

0 = Don’t need power

ROS 0

E Power Up Stall

Status

1 = FW is stalled at power up

0 = Firmware is unstalled

ROS 0

D:0 Reserved Status

3 [D:0]

Reserved for future use RO

Table 6.1032 Global Reserved Status 3: Address 1E.C887

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6.11.97 Global Reserved Status 4: Address 1E.C888

Bit Name Description Type Default Note

F:B Loopback Status

[4:0]

0x00 = No loopback

0x01 = System Interface - System Loopback

0x02 = System Interface - System Loopback

with Passthrough

0x03 = System Interface - Network Loopback

0x04 = System Interface - Network Loopback

with Passthrough

0x05 = System Interface - Network Loopback

with Passthrough and Merge

0x06 = System Interface - Peer-to-peer

loopback

0x07 - 0x08 = Reserved

0x09 = Network Interface - System Loopback

0x0A = Network Interface - System

Loopback with Passthrough

0x0B = Network Interface - Network

Loopback

0x0C = Network Interface - Network

Loopback with Passthrough

0x0D = Network Interface - Peer-to-peer

loopback

0x0E - 0x0F = Reserved

0x10 = Cross-connect System Loopback

0x11 = Cross-connect Network Loopback

0x12 - 0x13 = Reserved

0x14 = Network Interface - System Loopback

via Loopback Plug

0x15 - 0x1F = Reserved

RO 0x00 These bits, in conjunction with the chip

configuration and the rate (Bits 1:0), report the

selected loopback.

A:6 Reserved Status

4 [4:0]

Reserved for future use RO 0x00

Table 6.1033 Global Reserved Status 4: Address 1E.C888

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6.11.98 Global Alarms 1: Address 1E.CC00

5MDI Packet

Generation

Status

1 = CRPAT packet generation out MDI

interface

0 = No CRPAT packet generation out

MDI interface

RO 0 Reports whether the CRPAT packet generator

in the PHY outputs on the MDI interface at the

selected rate.

4 Look-Aside Port

Packet

Generation

Status

1 = CRPAT packet generation out 10G

look-aside interface (KR0)

0 = No CRPAT packet generation out

10G look-aside interface (KR0)

RO 0 Reports whether the CRPAT packet generator

in the PHY outputs on the KR0 interface at the

selected rate.

3 System I/F

Packet

Generation

Status

1 = CRPAT packet generation out 10G

system interface

0 = No CRPAT packet generation out

10G system interface

RO 0 Reports whether the CRPAT packet generator

in the PHY outputs on the selected system

interface at the selected rate.

2:0 Rate [2:0] 0x7 - 0x6 = reserved

0x5 = 5G

0x4 = 2.5G

0x3 = 10G

0x2 = 1G

0x1 = 100M

0x0 = invalid

RO 0x0 These bits report the selected rate for the

loopback and packet generation.

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify 0

Table 6.1034 Global Alarms 1: Address 1E.CC00

Bit Name Description Type Default Note

Table 6.1033 Global Reserved Status 4: Address 1E.C888

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E High Temperature

Failure

1 = High temperature failure

threshold has been exceeded

These bits mirror the matching bit in 1.A070

and 1.A074. These bits are driven by Bits E:B

in “Global General Status 1: Address 1E.C830”

on page 598.

D Low Temperature

Failure

1 = Low temperature failure

threshold has been exceeded

C High Temperature

Warning

1 = High temperature warning

threshold has been exceeded

B Low Temperature

Warning

1 = Low temperature warning

threshold has been exceeded

A:7 Reserved Internal reserved - do not modify

6 Reset completed 1 = Chip wide reset completed LH This bit is set by the microprocessor when it

has completed it’s initialization sequence. This

bit is mirrored in 1.CC02.0

5 Reserved Internal reserved - do not modify

4 Device Fault 1 = Fault LH When set, a fault has been detected by the uP

and the associated 16 bit error code is visible

in Global Fault Message: Address 1E.C850

3 Reserved Alarm A Reserved for future use LH

2 Reserved Alarm B Reserved for future use LH

1 Reserved Alarm C Reserved for future use LH

0 Reserved Alarm D Reserved for future use LH

Bit Name Description Type Default Note

Table 6.1034 Global Alarms 1: Address 1E.CC00

615

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6.11.99 Global Alarms 2: Address 1E.CC01

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E Smart Power-Down

Entered

1 = Smart Power-Down State

Entered

LH When this bit is set, it indicates that the Smart

Power-Down state was entered

D XENPAK Alarm 1 = XENPAK Alarm RO

C IP Phone Detect 1 = IP Phone Detect LH Assertion of this bit means that the presence of

an IP Phone has been detected.

B DTE Status Change 1 = DTE status change LH Change in 1E.C887[F].

A:8 Reserved Alarms

[2:0]

Reserved LH

7 MDIO Command

Handling Overflow

1 = PHY was issued more MDIO

requests than it could service in

it’s request buffer

LH Assertion of this bit means that more MDIO

commands were issued than FW could handle.

6:1 Reserved Internal reserved - do not modify

0 Diagnostic Alarm 1 = Alarm triggered by a write to

1E.C470.7

LH A diagnostic alarm use to test system alarm

circuitry.

Table 6.1035 Global Alarms 2: Address 1E.CC01

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6.11.100 Global Alarms 3: Address 1E.CC02

Bit Name Description Type Default Note

F NVR Operation

Complete

1 = NVR operation is complete LH NVR interface is ready interrupt for registers

Global NVR Interface 1: Address 1E.100 -

Global NVR Interface 5: Address 1E.104.

E Mailbox Operation:

Complete

1 = Mailbox operation is complete LH Mailbox interface is ready interrupt for

registers Global Mailbox Interface 1: Address

1E.200 - Global Mailbox Interface 5: Address

1E.204

D:B Reserved Internal reserved - do not modify

A uP DRAM Parity Error 1 = Parity error detected in the uP

DRAM

9:8 uP IRAM Parity Error

[1:0]

1 = Parity error detected in the uP

IRAM

LH Bit 0 indicates a parity error was detected in

the uP IRAM but was corrected.

Bit 1 indicates a multiple parity errors were

detected in the uP IRAM and could not be

corrected.

The uP IRAM is protected with ECC.

7:6 Reserved Internal reserved - do not modify

5 Tx Enable State

Change

1 = TX_EN pin has changed state LRF

4:3 Reserved Internal reserved - do not modify

2 MDIO MMD Error 1 = Invalid MMD address detected LH

1 MDIO Timeout Error 1 = MDIO timeout detected LH

0 Watchdog Timer

Alarm

1 = Watchdog timer alarm LH

Table 6.1036 Global Alarms 3: Address 1E.CC02

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6.11.101 Global Interrupt Mask 1: Address 1E.D400

Bit Name Description Typ

Default Note

F Reserved Internal reserved - do not modify

E High Temperature

Failure Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

D Low Temperature

Failure Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C High Temperature

Warning Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

B Low Temperature

Warning Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A:7 Reserved Internal reserved - do not modify

6 Reset completed

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5 Reserved Internal reserved - do not modify

4 Device Fault Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

3 Reserved Alarm A

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

2 Reserved Alarm B

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.1037 Global Interrupt Mask 1: Address 1E.D400

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6.11.102 Global Interrupt Mask 2: Address 1E.D401

1 Reserved Alarm C

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Reserved Alarm D

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F Reserved Internal reserved - do not modify

E Smart Power-Down

Entered Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

D XENPAK Alarm Mask 1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C IP Phone Detect

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

B DTE Status Change

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A:8 Reserved Alarms

Mask [2:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

7 MDIO Command

Handling Overflow

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.1038 Global Interrupt Mask 2: Address 1E.D401

Bit Name Description Typ

Default Note

Table 6.1037 Global Interrupt Mask 1: Address 1E.D400

619

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6.11.103 Global Interrupt Mask 3: Address 1E.D402

6:1 Reserved Internal reserved - do not modify

0 Diagnostic Alarm

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F NVR Operation

Complete Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 NVR interface is ready interrupt for registers

Global NVR Interface 1: Address 1E.100 -

Global NVR Interface 5: Address 1E.104

E Mailbox Operation

Complete Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Mailbox interface is ready interrupt for

registers Global Mailbox Interface 1: Address

1E.200 - Global Mailbox Interface 5: Address

1E.204

D:B Reserved Internal reserved - do not modify

A uP DRAM Parity Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

9:8 uP IRAM Parity Error

Mask [1:0]

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0x0

7:6 Reserved Internal reserved - do not modify

5 Tx Enable State

Change Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

4:3 Reserved Internal reserved - do not modify

Table 6.1039 Global Interrupt Mask 3: Address 1E.D402

Bit Name Description Type Default Note

Table 6.1038 Global Interrupt Mask 2: Address 1E.D401

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6.11.104 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00

2 MDIO MMD Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 MDIO Timeout Error

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Watchdog Timer

Alarm Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F PMA Standard Alarm

1 Interrupt

1 = Interrupt in PMA standard

alarms 1

RO An interrupt was generated from bit 1.1.2.

An interrupt was generated from status

Address 1.1” on page 94.) and the

corresponding mask register. (See “PMA

Transmit Standard Interrupt Mask 1: Address

1.D000” on page 220.)

E PMA Standard Alarm

2 Interrupt

1 = Interrupt in PMA standard

alarms 2

RO An interrupt was generated from either bit

1.8.B or 1.8.A.

An interrupt was generated from status

Address 1.8” on page 99.) and the

corresponding mask register. (See “PMA

Transmit Standard Interrupt Mask 2: Address

1.D001” on page 221.)

Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00

Bit Name Description Type Default Note

Table 6.1039 Global Interrupt Mask 3: Address 1E.D402

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D PCS Standard Alarm

1 Interrupt

1 = Interrupt in PCS standard

alarms 1

RO An interrupt was generated from status

Address 3.1” on page 229.) and the

corresponding mask register. (See “PCS

Standard Interrupt Mask 1: Address 3.D000”

on page 294.)

C PCS Standard Alarm

2 Interrupt

1 = Interrupt in PCS standard

alarms 2

RO An interrupt was generated from status

Address 3.8” on page 233.) and the

corresponding mask register. (See “PCS

Standard Interrupt Mask 2: Address 3.D001”

on page 295.)

B PCS Standard Alarm

3 Interrupt

1 = Interrupt in PCS standard

alarms 3

RO An interrupt was generated from status

3.21” on page 237.) and the corresponding

mask register. (See “PCS Standard Interrupt

Mask 3: Address 3.D002” on page 296.)

A PHY XS Standard

Alarms 1 Interrupt

1 = Interrupt in PHY XS standard

alarms 1

RO An interrupt was generated from the status

Address 4.1” on page 382.) and the

corresponding mask register. (See “PHY XS

Transmit (XAUI Rx) Standard Interrupt Mask 1:

Address 4.D000” on page 409.)

9 PHY XS Standard

Alarms 2 Interrupt

1 = Interrupt in PHY XS standard

alarms 2

RO An interrupt was generated from the status

Address 4.8” on page 386.) and the

corresponding mask register. (See “PHY XS

Transmit (XAUI Rx) Standard Interrupt Mask 2:

Address 4.D001” on page 410.)

Bit Name Description Type Default Note

Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00

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8 Autonegotiation

Standard Alarms 1

Interrupt

1 = Interrupt in Autonegotiation

standard alarms 1

RO An interrupt was generated from status

Status 1: Address 7.1” on page 434.) and the

corresponding mask register. (See

“Autonegotiation Standard Interrupt Mask 1:

Address 7.D000” on page 478.)

7 Autonegotiation

Standard Alarms 2

Interrupt

1 = Interrupt in Autonegotiation

standard alarms 2

RO An interrupt was generated from status

Status Register: Address 7.21” on page 446.)

and the corresponding mask register. (See

“Autonegotiation Standard Interrupt Mask 2:

Address 7.D001” on page 479.)

6 GbE Standard Alarms

Interrupt

1 = Interrupt in GbE standard

alarms

RO An interrupt was generated from the TGE core.

5:1 Reserved Internal reserved - do not modify

0 All Vendor Alarms

Interrupt

1 = Interrupt in all vendor alarms RO An interrupt was generated from status

Interrupt Flags: Address 1E.FC01” on

page 623.) and the corresponding mask

Vendor Mask: Address 1E.FF01” on

page 625.)

Bit Name Description Type Default Note

Table 6.1040 Global Chip-Wide Standard Interrupt Flags: Address 1E.FC00

623

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6.11.105 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01

Bit Name Description Type Default Note

F PMA Vendor Alarm

Interrupt

1 = Interrupt in PMA vendor specific

alarm

RO A PMA alarm was generated. (See “PMA

Vendor Global Interrupt Flags 1: Address

1.FC00” on page 224.)

E PCS Vendor Alarm

Interrupt

1 = Interrupt in PCS vendor specific

alarm

RO A PCS alarm was generated. (See “PCS

Vendor Global Interrupt Flags 1: Address

3.FC00” on page 378.)

D PHY XS Vendor

Alarm Interrupt

1 = Interrupt in PHY XS vendor

specific alarm

RO A PHY XS alarm was generated. (See “PHY

XS Vendor Global Interrupt Flags 1: Address

4.FC00” on page 431.)

C Autonegotiation

Vendor Alarm

Interrupt

1 = Interrupt in Autonegotiation

vendor specific alarm

RO An Autonegotiation alarm was generated. (See

“Autonegotiation Vendor Global Interrupt Flags

1: Address 7.FC00” on page 488.)

B GbE Vendor Alarm

Interrupt

1 = Interrupt in GbE vendor specific

alarm

RO A GbE alarm was generated. (See “GbE PHY

Vendor Global Interrupt Flags 1: Address

1D.FC00” on page 547.)

A:3 Reserved Internal reserved - do not modify

2 Global Alarms 1

Interrupt

1 = Interrupt in Global alarms 1 RO An interrupt was generated from status

1E.CC00” on page 613.) and the

corresponding mask register. (See “Global

Interrupt Mask 1: Address 1E.D400” on

page 617.)

Table 6.1041 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01

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6.11.106 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00

1 Global Alarms 2

Interrupt

1 = Interrupt in Global alarms 2 RO An interrupt was generated from status

1E.CC01” on page 615.) and the

corresponding mask register. (See “Global

Interrupt Mask 2: Address 1E.D401” on

page 618.)

0 Global Alarms 3

Interrupt

1 = Interrupt in Global alarms 3 RO An interrupt was generated from status

1E.CC02” on page 616.) and the

corresponding mask register. (See “Global

Interrupt Mask 3: Address 1E.D402” on

page 619.)

Bit Name Description Type Default Note

F PMA Standard Alarm

1 Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E PMA Standard Alarm

2 Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

D PCS Standard Alarm

1 Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

C PCS Standard Alarm

2 Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

B PCS Standard Alarm

3 Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.1042 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00

Bit Name Description Type Default Note

Table 6.1041 Global Chip-Wide Vendor Interrupt Flags: Address 1E.FC01

625

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6.11.107 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01

A PHY XS Standard

Alarms 1 Interrupt

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

9 PHY XS Standard

Alarms 2 Interrupt

Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

8 Autonegotiation

Standard Alarms 1

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

7 Autonegotiation

Standard Alarms 2

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

6 Gbe Standard Alarms

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

5:1 Reserved Internal reserved - do not modify

0 All Vendor Alarms

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

F PMA Vendor Alarm

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

E PCS Vendor Alarm

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

D PHY XS Vendor

Alarm Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Table 6.1043 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01

Bit Name Description Type Default Note

Table 6.1042 Global Interrupt Chip-Wide Standard Mask: Address 1E.FF00

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C Autonegotiation

Vendor Alarm

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

B GbE Vendor Alarm

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

A:3 Reserved Internal reserved - do not modify

2 Global Alarms 1

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

1 Global Alarms 2

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

0 Global Alarms 3

Interrupt Mask

1 = Enable interrupt generation

0 = Disable interrupt generation

R/W

Bit Name Description Type Default Note

Table 6.1043 Global Interrupt Chip-Wide Vendor Mask: Address 1E.FF01

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References:

[1] “XENPAK 10 Gigabit Ethernet MSA”, XENPAK MSA Rev. 3.0, Issue 3.0,

September 18, 2002.

[2] “X2 MSA Specification”, X2 MSA Issue 2.0b, April 7, 2005.

[3] “Part 3: Carrier sense multiple access with collision detection (CSMA/CD)

access method and physical layer specifications”, 802.3 - 2008, IEEE Computer

Society, The Institute of Electrical and Electronics Engineers, Inc., 3 Park

Avenue, New York, NY 10016-5997, USA, December 26, 2008.

[4] “Fibre Channel 10 Gigabit (10GFC) Rev. 4.0”, INCITS 364-2002 T11/Project

1413-D/Rev 4.0, INCITS working draft proposed American National Standard for

Information Technology, April 1, 2004.

[5] “The Test Access Port and Boundary-Scan Architecture”, IEEE STD-1149.1

-2001, IEEE Standards Office, The Institute of Electrical and Electronics

Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, October 25,

2001.

[6] “The Test Access Port and Boundary-Scan Architecture”, IEEE STD-1149.6

-2003, IEEE Standards Office, The Institute of Electrical and Electronics

Engineers, Inc., 3 Park Avenue, New York, NY 10016-5997, USA, April 17,

2003.

[7] “Media Access Control (MAC) Security”, IEEE STD-802.AE-2006, IEEE

Standards Office, The Institute of Electrical and Electronics Engineers, Inc., 3

Park Avenue, New York, NY 10016-5997, USA, April 17, 2003.

[8] “Doxygen”, http://www.stack.nl/~dimitri/doxygen, Dimitri van Heesch, November

2006.

[9] “Microsoft Network Device Class Specification”,

http://www.microsoft.com/whdc/resources/respec/specs/pmref/PMnetwork.ms

px, Version 2.0 October 12, 2000.

[10] “Serial-GMII Specification Version 1.8“, Document ENG-46158, Cisco Systems,

April 27, 2005.

[11] “Information Technology - Generic cabling for customer premises”, ISO/IEC

11801, Second edition 2002-09.

[12] “API”, Aquantia Corporation.

[13] “Hardware Design Guide”, Aquantia Corporation.

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AQR405 Revision 0.11 - January 5, 2015

Data Sheet

January 2015

10GBASE-T Ethernet PHY Transceiver

AQR405

PROPRIETARY AND CONFIDENTIAL: All of the information included herein, as well as any oral or written discussions regarding such information and any materials generated as a result of

such discussions, is confidential information that is proprietary to Aquantia Corporation and should be used by its recipient solely as authorized by Aquantia Corporation under written non-dis-

closure agreement.

Aquantia Corp. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Aquantia is a

registered trademark of Aquantia Corp. Aquantia and the Aquantia logo are trademarks of Aquantia Corp. Consult the current Release Notes for the AQR405 to obtain a list of all currently known

issues and errata associated with the AQR405.

For additional information, contact your Aquantia Account Manager or the following:

INTERNET: Home: http://www.aquantia.com

E-MAIL: sales@aquantia.com

ADDRESS: Aquantia Corp., 700 Tasman Drive, Milpitas, CA 95035

408-228-8300, FAX 408-228-1190

Strictly Confidential