Triple, 200 mA, Low Noise,
High PSRR Voltage Regulator
Data Sheet
ADP320
Rev. C Document Feedback
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FEATURES
Bias voltage range (VBIAS): 2.5 V to 5.5 V
LDO input voltage range (VIN1/VIN2, VIN3): 1.8 V to 5.5 V
Three 200 mA low dropout voltage regulators
16-lead, 3 mm × 3 mm LFCSP
Initial accuracy: ±1%
Stable with 1 µF ceramic output capacitors
No noise bypass capacitor required
3 independent logic controlled enables
Over current and thermal protection
Key specifications
High PSRR
76 dB PSRR up to 1 kHz
70 dB PSRR 10 kHz
60 dB PSRR at 100 kHz
40 dB PSRR at 1 MHz
Low output noise
24 µV rms typical output noise at VOUT = 1.2 V
43 µV rms typical output noise at VOUT = 2.8 V
Excellent transient response
Low dropout voltage: 110 mV @ 200 mA load
85 µA typical ground current at no load, all LDOs enabled
100 µs fast turn-on circuit
Guaranteed 200 mA output current per regulator
−40°C to +125°C junction temperature
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Portable medical devices
Post dc-to-dc regulation
TYPICAL APPLICATION CIRCUITS
ADP320
VBIAS
VOUT1
GND
VBIAS
1µF
OFF
ON
EN1
OFF
ON
EN2
OFF
ON
EN3
+
1µF
+
LDO 1
EN LD1
VBIAS
VBIAS
VOUT2
1µF
+
LDO 2
EN LD2
VOUT3
1µF
+
LDO 3
EN LD3
2.5V TO
5.5V
VIN1/VIN2
VIN3
1µF
+
1.8V TO
5.5V
1.8V TO
5.5V
1µF
+
09874-001
Figure 1. Typical Application Circuit
GENERAL DESCRIPTION
The ADP320 200 mA triple output LDO combines high PSRR, low
noise, low quiescent current, and low dropout voltage in a voltage
regulator ideally suited for wireless applications with demanding
performance and board space requirements.
The low quiescent current, low dropout voltage, and wide input
voltage range of the ADP320 triple LDO extend the battery life of
portable devices. The ADP320 triple LDO maintains power supply
rejection greater than 60 dB for frequencies as high as 100 kHz
while operating with a low headroom voltage. The ADP320 triple
LDO offers much lower noise performance than competing LDOs
without the need for a noise bypass capacitor.
The ADP320 triple LDO is available in a miniature 16-lead 3 mm ×
3 mm LFCSP package and is stable with tiny 1 µF ±30% ceramic output
capacitors, resulting in the smallest possible board area for a wide
variety of portable power needs.
The ADP320 triple LDO is available in output voltage combin-
ations ranging from 0.8 V to 3.3 V and offers over current and
thermal protection to prevent damage in adverse conditions.
ADP320 Data Sheet
Rev. C | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Typical Application Circuits ............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Input and Output Capacitor, Recommended Specifications .. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 15
Applications Information .............................................................. 16
ADIsimPower Design Tool ....................................................... 16
Capacitor Selection .................................................................... 16
Undervoltage Lockout ............................................................... 17
Enable Feature ............................................................................ 17
Current-Limit and Thermal Overload Protection ................. 18
Thermal Considerations ............................................................ 18
Printed Circuit Board Layout Considerations........................ 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
2/2017—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
11/2014—Rev. A to Rev. B
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Figure 28, Figure 29, Figure 30, and Figure 31;
Added Figure 32; Renumbered Sequentially .............................. 11
Added Figure 33 and Figure 34; Changes to Figure 36,
Figure 37, and Figure 38 ................................................................ 12
Added Figure 39 ............................................................................. 13
Added ADIsimPower Design Tool Section ................................. 16
4/2011—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 20
6/2010—Revision 0: Initial Version
Data Sheet ADP320
Rev. C | Page 3 of 21
SPECIFICATIONS
VIN1/VIN2 = VIN3 = (VOUT + 0.5 V) or 1.8 V (whichever is greater), VBIAS = 2.5 V, EN1, EN2, EN3 = VBIAS, IOUT1 = IOUT2 = IOUT3 = 10 mA,
CIN = COUT1 = COUT2 = COUT3 = 1 µF, and TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
INPUT BIAS VOLTAGE RANGE VBIAS TJ = −40°C to +125°C 2.5 5.5 V
INPUT LDO VOLTAGE RANGE VIN1/VIN2/ VIN3 TJ = −40°C to +125°C 1.8 5.5 V
GROUND CURRENT WITH ALL
REGULATORS ON
IGND IOUT = 0 µA 85 µA
IOUT = 0 µA, TJ = −40°C to +125°C 160 µA
IOUT = 10 mA 120 µA
IOUT = 10 mA, TJ = −40°C to +125°C 220 µA
IOUT = 200 mA 250 µA
IOUT = 200 mA, TJ = −40°C to +125°C 380 µA
INPUT BIAS CURRENT IBIAS 66 µA
TJ = −40°C to +125°C 140 µA
SHUTDOWN CURRENT IGND-SD EN1 = EN2 = EN3 = GND 0.1 µA
EN1 = EN2 = EN3 = GND, TJ = −40°C to +125°C 2.5 µA
OUTPUT VOLTAGE ACCURACY
V
OUT
+1
%
100 µA < IOUT < 200 mA, VIN = (VOUT + 0.5 V) to 5.5 V,
TJ = −40°C to +125°C
−2 +2 %
LINE REGULATION ∆VOUT/∆VIN VIN = (VOUT + 0.5 V) to 5.5 V 0.01 %/ V
VIN = (VOUT + 0.5 V) to 5.5 V, TJ = −40°C to +125°C −0.03 +0.03 %/ V
LOAD REGULATION1
∆V
OUT
/∆I
OUT
I
OUT
= 1 mA to 200 mA
0.001
%/mA
IOUT = 1 mA to 200 mA, TJ = −40°C to +125°C 0.005 %/mA
DROPOUT VOLTAGE2 VDROPOUT VOUT = 3.3 V mV
IOUT = 10 mA 6 mV
I
OUT
= 10 mA, T
J
= −40°C to +125°C
9
mV
IOUT = 200 mA 110 mV
IOUT = 200 mA, TJ = −40°C to +125°C 170 mV
START-UP TIME3 TSTART-UP VOUT = 3.3 V, all VOUT initially off, enable one 240 µs
VOUT = 0.8 V 100 µs
VOUT = 3.3 V, one VOUT initially on, enable second 160 µs
VOUT = 0.8 V 20 µs
CURRENT LIMIT THRESHOLD4 ILIMIT 250 360 600 mA
THERMAL SHUTDOWN
Thermal Shutdown Threshold
TS
SD
T
J
rising
155
°C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
EN INPUT
EN Input Logic High VIH 2.5 V ≤ VBIAS ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.5 V ≤ VBIAS ≤ 5.5 V 0.4 V
EN Input Leakage Current VI-LEAKAGE EN1 = EN2 = EN3 = VIN or GND 0.1 µA
EN1 = EN2 = EN3 = VIN or GND, TJ = −40°C to +125°C 1 µA
UNDERVOLTAGE LOCKOUT UVLO
Input Bias Voltage (VBIAS) Rising UVLORISE 2.45 V
Input Bias Voltage (VBIAS) Falling UVLOFALL 2.0 V
Hysteresis UVLOHYS 180 mV
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 50 µV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.8 V 43 µV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 2.5 V 40 µV rms
10 Hz to 100 kHz, VIN = 3.6 V, VOUT = 1.2 V 24 µV rms
ADP320 Data Sheet
Rev. C | Page 4 of 21
Parameter Symbol Conditions Min Typ Max Unit
POWER SUPPLY REJECTION RATIO PSRR VIN = 1.8 V, VOUT = 0.8 V, IOUT = 100 mA
100 Hz 70 dB
1 kHz 70 dB
10 kHz 70 dB
100 kHz 60 dB
1 MHz 40 dB
VIN = 3.3 V, VOUT = 2.8 V, IOUT = 100 mA
100 Hz
68
dB
1 kHz 62 dB
10 kHz 68 dB
100 kHz 60 dB
1 MHz 40 dB
1 Based on an end-point calculation using 1 mA and 200 mA loads.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages above 1.8 V.
3 Start-up time is defined as the time between the rising edge of ENx to VOUTx being at 90% of its nominal value.
4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
MINIMUM INPUT AND OUTPUT CAPACITANCE1 CMIN TA = −40°C to +125°C 0.70 µF
CAPACITOR ESR RESR TA = −40°C to +125°C 0.001 1 Ω
1 The minimum input and output capacitance must be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
Y5V and Z5U capacitors are not recommended for use with LDOs.
Data Sheet ADP320
Rev. C | Page 5 of 21
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VIN1/VIN2, VIN3, VBIAS to GND –0.3 V to +6.5 V
VOUT1, VOUT2 to GND
–0.3 V to VIN1/VIN2
VOUT3 to GND –0.3 V to VIN3
EN1, EN2, EN3 to GND –0.3 V to +6.5 V
Storage Temperature Range –65°C to +150°C
Operating Junction Temperature Range –40°C to +125°C
Soldering Conditions JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination.
The ADP320 triple LDO can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temper-
ature does not guarantee that the junction temperature (TJ) is
within the specified temperature limits. In applications with
high power dissipation and poor thermal resistance the
maximum ambient temperature may have to be derated. In
applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits.
The junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction-to-ambient thermal resistance of the
package (θJA). Maximum junction temperature (TJ) is calculated
from the ambient temperature (TA) and power dissi-pation (PD)
using the following formula:
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending on
PCB material, layout, and environmental conditions. The
specified values of θJA are based on a four-layer, 4-inch × 3-inch
circuit board. Refer to JEDEC JESD 51-9 for detailed informa-
tion on the board construction. For additional information, see
the AN-617 Application Note, MicroCSP™ Wafer Level Chip
Scale Package.
ΨJB is the junction to board thermal characterization parameter
with units of °C / W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package; factors that make ΨJB more useful in real-world
applications. Maximum junction temperature (TJ) is calculated
from the board temperature (TB) and power dissipation (PD)
using the following formula
TJ = TB + (PD × ΨJB)
Refer to JEDEC JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θJA ΨJB Unit
16-Lead 3 mm × 3 mm LFCSP 49.5 25.2 °C/W
ESD CAUTION
ADP320 Data Sheet
Rev. C | Page 6 of 21
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
12
11
10
1
3
4
GND
GND
VIN3
9VIN3
EN1
VIN1/VIN2
2
VBIAS
VIN1/VIN2
6
VOUT2
5
VOUT1
7
VOUT3
8
NC
16 EN2
15 EN3
14 NC
13 NC
TOP VIEW
(No t to S cale)
ADP320
NOTES
1. NC = NO CONNE CT.
2
. CO NNE CT EX POSE D PAD TO GRO UND PLANE.
09874-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 EN1 Enable Input for Regulator 1. Drive EN1 high to turn on Regulator 1; drive it low to turn off Regulator 1. For
automatic startup, connect EN1 to VBIAS.
2 VBIAS Input Voltage Bias Supply. Bypass VBIAS to GND with a 1 μF or greater capacitor.
3 VIN1/VIN2
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
4 VIN1/VIN2
Regulator Input Supply for Output Voltage 1 and Output Voltage 2. Bypass VIN1/VIN2 to GND with a 1 μF or
greater capacitor.
5 VOUT1 Regulated Output Voltage 1. Connect a 1 μF or greater output capacitor between VOUT1 and GND.
6 VOUT2 Regulated Output Voltage 2. Connect a 1 μF or greater output capacitor between VOUT2 and GND.
7 VOUT3 Regulated Output Voltage 3. Connect a 1 μF or greater output capacitor between VOUT3 and GND.
8 NC Not connected internally.
9 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
10 VIN3 Regulator Input Supply for Output Voltage 3. Bypass VIN3 to GND with a 1 μF or greater capacitor.
11 GND Ground Pin.
12 GND Ground Pin.
13 NC Not connected internally.
14 NC Not connected internally.
15 EN3 Enable Input for Regulator 3. Drive EN3 high to turn on Regulator 3; drive it low to turn off Regulator 3. For
automatic startup, connect EN3 to VBIAS.
16 EN2 Enable Input for Regulator 2. Drive EN1 high to turn on Regulator 2; drive it low to turn off Regulator 2. For
automatic startup, connect EN2 to VBIAS.
EP EP Exposed pad for enhanced thermal performance. Connect to copper ground plane.
Data Sheet ADP320
Rev. C | Page 7 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
VIN1/VIN2 = VIN3 =VBIAS = 4 V, VOUT1 = 3.3 V, VOUT2 = 1.8 V, VOUT3 = 1.5 V, IOUT = 10 mA, CIN = COUT1 = COUT2 = COUT3 = 1 μF, TA = 25°C,
unless otherwise noted.
3.27
3.28
3.29
3.30
3.31
3.32
3.33
–40 –5 25 85 125
T
J
(°C)
V
OUT
(V)
LO AD = 1mA
LO AD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-003
Figure 3. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 μF
3.300
3.305
3.310
3.315
3.320
1 10 100 1000
I
LOAD
(mA)
V
OUT
(V)
09874-004
Figure 4. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 μF
3.300
3.305
3.310
3.315
3.320
3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4
VIN (V)
VOUT (V)
LOAD = 1mA
LOAD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-005
Figure 5. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 μF
1.780
1.785
1.790
1.795
1.800
1.805
1.810
1.815
1.820
–40 –5 25 85 125
T
J
(°C)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09874-006
Figure 6. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 μF
1.800
1.805
1.810
1.815
1.820
1 10 100 1000
I
LOAD
(mA)
V
OUT
(V)
09874-007
Figure 7. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 μF
1.800
1.805
1.810
1.815
1.820
2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-008
Figure 8. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 μF
ADP320 Data Sheet
Rev. C | Page 8 of 21
1.480
1.485
1.490
1.495
1.500
1.505
1.510
1.515
1.520
–40 –5 25 85 125
T
J
(°C)
V
OUT
(V)
LO AD = 1mA
LO AD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-009
Figure 9. Output Voltage vs. Junction Temperature, VRIPPLE = 50 mV, COUT = 1 μF
1.500
1.502
1.504
1.506
1.508
1.510
1 10 100 1000
I
LOAD
(mA)
V
OUT
(V)
09874-010
Figure 10. Output Voltage vs. Load Current, VRIPPLE = 50 mV, COUT = 1 μF
1.500
1.502
1.504
1.506
1.508
1.510
1.80 2.20 2.60 3.00 3.40 3.80 4.20 4.60 5.00 5.40
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10m A
LOAD = 50m A
LOAD = 100m A
LOAD = 200m A
09874-011
Figure 11. Output Voltage vs. Input Voltage, VRIPPLE = 50 mV, COUT = 1 μF
0
20
40
60
80
100
120
140
–40 –5 25 85 125
T
J
(°C)
GRO UND CURRENT (µ A)
LO AD = 1mA
LO AD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-012
Figure 12. Ground Current vs. Junction Temperature, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 μF
0
20
40
60
80
100
120
1 10 100 1000
I
LOAD
(mA)
GRO UND CURRENT ( µA)
09874-013
Figure 13. Ground Current vs. Load Current, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 μF
0
20
40
60
80
100
120
1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4
V
IN
(V)
GRO UND CURRENT (µ A)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09874-014
Figure 14. Ground Current vs. Input Voltage, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 μF
Data Sheet ADP320
Rev. C | Page 9 of 21
0
50
100
150
200
250
300
350
–40 –5 25 85 125
T
J
(°C)
GRO UND CURRE NT (µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10m A
LOAD = 50m A
LOAD = 100m A
LOAD = 200m A
09874-015
Figure 15. Ground Current vs. Junction Temperature,
All Outputs Loaded Equally, VRIPPLE = 50 mV, COUT = 1 μF
0
50
100
150
200
250
300
1 10 100 1000
TOTA L LOAD CURRENT (mA)
GRO UND CURRENT (µ A)
09874-016
Figure 16. Ground Current vs. Load Current, All Outputs Loaded Equally,
VRIPPLE = 50 mV, COUT = 1 μF
0
50
100
150
200
250
300
1.7 2.1 2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
V
IN
(V)
GRO UND CURRENT (µ A)
LOAD = 1mA
LOAD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-017
Figure 17. Ground Current vs. Input Voltage, All Outputs Loaded Equally,
VRIPPLE = 50 mV, COUT = 1 μF
–40 –5 25 85 125
T
J
(°C)
BIAS CURRENT (µ A)
0
20
40
60
80
100
120
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09874-018
Figure 18. Bias Current vs. Junction Temperature, Single Output Loaded,
VRIPPLE = 50 mV, COUT = 1 μF
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
I
LOAD
(mA)
BIAS CURRE NT ( µ A)
09874-019
Figure 19. Bias Current vs. Load Current, Single Output Load,
VRIPPLE = 50 mV, COUT = 1 μF
64
66
68
70
72
74
76
2.5 2.9 3.3 3.7 4.1 4.5 4.9 5.3
VIN (V)
BIAS CURRE NT (µ A)
LO AD = 1mA
LO AD = 5mA
LO AD = 10mA
LO AD = 50mA
LO AD = 100mA
LO AD = 200mA
09874-020
Figure 20. Bias Current vs. Input Voltage, Single Output Load,
VRIPPLE = 50 mV, COUT = 1 μF
ADP320 Data Sheet
Rev. C | Page 10 of 21
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
–50 –25 0 25 50 75 100 125
TEMPERATURE (°C)
SHUTDOW N CURRENT (µ A)
3.6
3.8
4.2
4.4
4.8
5.5
09874-021
Figure 21. Shutdown Current vs. Temperature at Various Input Voltages,
VRIPPLE = 50 mV, COUT = 1 μF
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
LO AD (mA)
DROPOUT (mV)
09874-022
Figure 22. Dropout Voltage vs. Load Current and Output Voltage,
VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 μF
2.95
3.00
3.05
3.10
3.15
3.20
3.25
3.30
3.35
3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09874-023
Figure 23. Output Voltage vs. Input Voltage (In Dropout),
VOUT1 = 3.3 V, VRIPPLE = 50 mV, COUT = 1 μF
0
50
100
150
200
250
300
350
3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50
V
IN
(V)
GRO UND CURRE NT ( µA)
LOAD = 1mA
LOAD = 5mA
LOAD = 10m A
LOAD = 50m A
LOAD = 100m A
LOAD = 200m A
09874-024
Figure 24. Ground Current vs. Input Voltage (in Dropout), VOUT1 = 3.3 V,
VRIPPLE = 50 mV, COUT = 1 μF
0
50
100
150
200
250
300
1 10 100 1000
LOAD (mA)
DROPOUT (mV)
09874-025
Figure 25. Dropout Voltage vs. Load Current and Output Voltage,
VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 μF
1.45
1.50
1.55
1.60
1.65
1.70
1.75
1.80
1.85
1.70 1.80 1.90 2.00 2.10
V
IN
(V)
V
OUT
(V)
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
09874-026
Figure 26. Output Voltage vs. Input Voltage (in Dropout),
VOUT2 = 1.8 V, VRIPPLE = 50 mV, COUT = 1 μF
Data Sheet ADP320
Rev. C | Page 11 of 21
LOAD = 1mA
LOAD = 5mA
LOAD = 10mA
LOAD = 50mA
LOAD = 100mA
LOAD = 200mA
0
20
40
60
80
100
120
140
160
1.70 1.80 1.90 2.00 2.10
VIN (V)
GROUND CURRENT (µA)
09874-027
Figure 27. Ground Current vs. Input Voltage in Dropout), VOUT2 = 1.8 V,
VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-028
Figure 28. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V,
VIN = 2.8 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-129
Figure 29. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.8 V,
VIN = 2.3 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-029
Figure 30. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V,
VIN = 4.3 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-131
Figure 31. Power Supply Rejection Ratio vs. Frequency, VOUT = 3.3 V,
VIN = 3.8 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-030
Figure 32. Power Supply Rejection Ratio vs. Frequency, VOUT = 1.5 V,
VIN = 2.5 V, VRIPPLE = 50 mV, COUT = 1 µF
ADP320 Data Sheet
Rev. C | Page 12 of 21
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-133
Figure 33. Power Supply Rejection Ratio vs. Frequency, VOUT= 1.5 V,
VIN = 2.0 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
PSRR (dB)
10mA
100mA
200mA
FREQUENCY (Hz)
110 100 1k 10k 100k 1M 10M
09874-134
Figure 34. Power Supply Rejection Ratio vs. Frequency, VOUT= 1.2 V,
VIN = 2.2 V, VRIPPLE = 50 mV, COUT = 1 µF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FREQUENCY (Hz)
PSRR (dB)
1.8V/200mA
1.8V/100mA
1.8V/10mA
1.2V/200mA
1.2V/100mA
1.2V/10mA
1V HEADROOM
1.8V PSRR
1.2 XTALK
10 100 1k 10k 100k 1M 10M
09874-031
Figure 35. Power Supply Rejection Ratio vs. Frequency,
Channel to Channel Crosstalk, VRIPPLE = 50 mV, COUT = 1 µF
1
10
100
10k
1k
NOISE SPECTRAL DENSITY (nV/√Hz)
FREQUENCY (Hz)
09874-032
110 100 1k 10k 100k 1M 10M
1.5V
1.8V
2.5V
3.3V
Figure 36. Output Noise Spectral Density, VIN = 5 V, ILOAD = 10 mA,
VRIPPLE = 50 mV, COUT = 1 µF
0
10
20
30
40
50
0.001 0.01 0.1 110 100 1000
LOAD CURRENT (mA)
NOISE (µV rms)
09874-033
1.5V
1.8V
2.5V
3.3V
Figure 37. 10 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage,
VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF
0
10
20
30
40
50
0.001 0.01 0.1 110 100 1000
LOAD CURRENT (mA)
NOISE (µV rms)
09874-138
1.5V
1.8V
2.5V
3.3V
Figure 38. 100 Hz to 100 kHz Output Noise vs. Load Current and Output Voltage,
VIN = 5 V, VRIPPLE = 50 mV, COUT = 1 µF
Data Sheet ADP320
Rev. C | Page 13 of 21
0
10
20
30
40
50
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
NOISE (µV rms)
OUTPUT VOLTAGE (V)
1µA
10µA
100µA
1mA
10mA
100mA
200mA
09874-139
Figure 39. Output Noise vs. Output Voltage, Different Load Currents, VIN = 5 V,
VRIPPLE = 50 mV, COUT = 1 µF
CH1 100mACH2 50mV
CH3 10mV CH4 10mV
M40µs A CH1 44mA
1
2
3
4
T 9.8%
BWBW
BW
BW
Ω
09874-034
I
LOAD1
V
OUT1
V
OUT2
V
OUT3
Figure 40. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = ILOAD3 = 1 mA,CH1 = ILOAD1,
CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF
1
2
T 10.2%
CH1 200mAM40µs A CH1 124mA
BW
BW
ΩCH2 50mV
09874-035
I
LOAD1
V
OUT1
Figure 41. Load Transient Response,
ILOAD1 = 1 mA to 200 mA, COUT1 = 1 μF,
CH1 = ILOAD1, CH2 = VOUT1, VRIPPLE = 50 mV, COUT = 1 µF
CH2
1
2
T 10.4%
CH1 200mA50mV M40µs A CH1 84mA
BW
BW
Ω
09874-036
I
LOAD2
V
OUT2
Figure 42. Load Transient Response,
ILOAD2 = 1 mA to 200 mA, COUT2 = 1 μF,
CH1 = ILOAD2, CH2 = VOUT2, VRIPPLE = 50 mV, COUT = 1 µF
CH1 200mACH2 50mV M40µs A CH1 124mA
1
2
T 10.2%
BW
BW
Ω
09874-037
ILOAD3
VOUT3
Figure 43. Load Transient Response,
ILOAD3 = 1 mA to 200 mA, COUT3 = 1 μF,
CH1 = ILOAD3, CH2 = VOUT3, VRIPPLE = 50 mV, COUT = 1 µF
CH3 10mV
BW
1
4
3
2
T 15%
CH1 1V CH2 10mV M1µs A CH1 4.62V
BW
CH4 10mV
BW
BW
09874-038
VIN
VOUT1
VOUT2
VOUT3
Figure 44. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
ADP320 Data Sheet
Rev. C | Page 14 of 21
CH2
1
4
3
2
T 12%
CH1 1V 10mV M2µs A CH1 4.58V
BW
CH4 10mV
BW
CH3 10mV
BW
BW
09874-039
VIN
VOUT1
VOUT2
VOUT3
Figure 45. Line Transient Response,
VIN = 4 V to 5 V, ILOAD1 = ILOAD2 = ILOAD3 =1 mA,
CH1 = VIN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
CH3
CH2
500mV BW
1
2
T 10.2%
CH1 1V 500mV M100µs A CH1 540mV
BW
CH4 500mV BW
BW
09874-040
V
EN
V
OUT1
V
OUT2
V
OUT3
Figure 46. Turn On Response,
ILOAD1 = ILOAD2 = ILOAD3 =100 mA,
CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3,
VRIPPLE = 50 mV, COUT = 1 µF
Data Sheet ADP320
Rev. C | Page 15 of 21
THEORY OF OPERATION
The ADP320 triple LDO is a low quiescent current, low dropout
linear regulator that operates from 1.8 V to 5.5 V on VIN1/VIN2
and VIN3 and provides up to 200 mA of current from each
output. Drawing a low 250 μA quiescent current (typical) at full
load makes the ADP320 triple LDO ideal for battery-operated
portable equipment. Shutdown current consumption is typically
100 nA.
Optimized for use with small 1 µF ceramic capacitors, the
ADP320 triple LDO provides excellent transient performance.
0.5V
REF
OVERCURRENT
VOUT1
VOUT2
VOUT3
VIN1/VIN2
GND
EN1
VBIAS
VIN3
EN3
EN2
0.5V
REF
OVERCURRENT
0.5V
REF
OVERCURRENT
INTERNAL BIAS
VOLTAGES/CURRENTS,
UVLO AND THERMAL
PROTECT
SHUTDOWN
VOUT1
SHUTDOWN
VOUT2
SHUTDOWN
VOUT3
09874-041
Figure 47. Internal Block Diagram
Internally, the ADP320 triple LDO consist of a reference, three
error amplifiers, three feedback voltage dividers, and three
PMOS pass transistors. Output current is delivered via the
PMOS pass device, which is controlled by the error amplifier.
The error amplifier compares the reference voltage with the
feedback voltage from the output and amplifies the difference. If
the feedback voltage is lower than the reference voltage, the gate
of the PMOS device is pulled lower, allowing more current to
flow and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to flow and decreasing the
output voltage.
The ADP320 triple LDO is available in multiple output voltage
options ranging from 0.8 V to 3.3 V. The ADP320 triple LDO
uses the EN1, EN2, and EN3 enable pins to enable and disable
the VOUT1/VOUT2/VOUT3 pins under normal operating
conditions. When the enable pins are high, VOUT1/VOUT2/
VOUT3 turn on; when enable pins are low, VOUT1/VOUT2/
VOUT3 turn off. For automatic startup, the enable pins can be
tied to VBIAS.
ADP320 Data Sheet
Rev. C | Page 16 of 21
APPLICATIONS INFORMATION
ADIsimPOWER DESIGN TOOL
The ADP323 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count,
taking into consideration the operating conditions and limitations
of the IC and all real external components. For more information
about, and to obtain ADIsimPower design tools, visit
www.analog.com/ADIsimPower.
CAPACITOR SELECTION
Output Capacitor
The ADP320 triple LDO is designed for operation with small,
space-saving ceramic capacitors, but the parts function with
most commonly used capacitors as long as care is taken in
regards to the effective series resistance (ESR) value. The ESR of
the output capacitor affects stability of the LDO control loop. A
minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is
recommended to ensure stability of the ADP320 triple LDO.
Transient response to changes in load current is also affected by
output capacitance. Using a larger value of output capacitance
improves the transient response of the ADP320 triple LDO to large
changes in the load current. Figure 48 show the transient
response for an output capacitance value of 1 µF.
CH1 100mAΩCH2 50mV
CH4 10mVCH3 10mV
M40µs A CH1 44mA
1
2
3
4
T 9.8%
BWBW
BW
BW
09874-042
I
LOAD1
V
OUT1
V
OUT2
V
OUT3
Figure 48. Output Transient Response,
ILOAD1 = 1 mA to 200 mA, ILOAD2 = 1 mA, ILOAD3 = 1 mA,
CH1 = ILOAD1, CH2 = VOUT1, CH3 = VOUT2 , CH4 = VOUT3
Input Bypass Capacitor
Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and
VBIAS to GND reduces the circuit sensitivity to the PCB layout,
especially when long input traces or high source impedance are
encountered. If an output capacitance greater than 1 µF is
required, the input capacitor can be increased to match it.
Input and Output Capacitor Properties
Any good quality ceramic capacitor may be used with the ADP320
triple LDO, as long as the capacitor meets the minimum capacit-
ance and maximum ESR requirements. Ceramic capacitors are
manufactured with a variety of dielectrics, each with a different
behavior over temperature and applied voltage. Capacitors must
have an adequate dielectric to ensure the minimum capacitance
over the necessary temperature range and dc bias conditions.
X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are
recommended. Y5V and Z5U dielectrics are not recommended,
due to their poor temperature and dc bias characteristics.
Figure 49 depicts the capacitance vs. voltage bias characteristic
of an 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is about ±15% over the −40°C to +85°C tempera-
ture range and is not a function of the package or voltage rating.
1.2
1.0
0.8
0.6
0.4
0.2
0
0 2 4 6 8 10
VOLTAGE (V)
CAPACITANCE (µF)
09874-043
Figure 49. Capacitance vs. Voltage Bias Characteristic
Data Sheet ADP320
Rev. C | Page 17 of 21
Use Equation 1 to determine the worst-case capacitance
accounting for capacitor variation over temperature, compo-
nent tolerance, and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
In this example, TEMPCO over −40°C to +85°C is assumed to
be 15% for an X5R dielectric. TOL is assumed to be 10%, and
CBIAS is 0.94 μF at 1.8 V from the graph in Figure 49.
Substituting these values into Equation 1 yields
CEFF = 0.94 μF × (1 − 0.15) × (1 − 0.1) = 0.719 μF
Therefore, the capacitor chosen in this example meets the mini-
mum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage.
To guarantee the performance of the ADP320 triple LDO, it is
imperative that the effects of dc bias, temperature, and toler-
ances on the behavior of the capacitors are evaluated for each
application.
UNDERVOLTAGE LOCKOUT
The ADP320 triple LDO has an internal undervoltage lockout
circuit that disables all inputs and the output when the input
voltage bias, VBIAS, is less than approximately 2.2 V. This
ensures that the inputs of the ADP320 triple LDO and the
output behave in a predictable manner during power-up.
ENABLE FEATURE
The ADP320 triple LDO uses the ENx pins to enable and disable
the VOUTx pins under normal operating conditions. Figure 50
shows a rising voltage on EN crossing the active threshold, then
VOUTx turns on. When a falling voltage on ENx crosses the
inactive threshold, VOUTx turns off.
ENABLE VOLTAGE (V)
V
OUT
(V)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.4 0.60.5 0.7 0.90.8 1.0 1.1 1.2
09874-054
VOUT
@ 4.5V
IN
Figure 50. Typical ENx Pin Operation
As shown in Figure 50, the ENx pin has built-in hysteresis. This
prevents on/off oscillations that can occur due to noise on the
ENx pin as it passes through the threshold points.
The active/inactive thresholds of the ENx pin are derived from the
VBIAS voltage. Therefore, these thresholds vary with changing input
voltage. Figure 51 shows typical ENx active/inactive thresholds
when the input voltage varies from 2.5 V to 5.5 V.
INPUT VOLTAGE (V)
ENABLE THRESHOLDS
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V
EN
RISE V
EN
FALL
09874-053
Figure 51. Typical ENx Pins Thresholds vs. Input Voltage
The ADP320 triple LDO utilizes an internal soft start to limit the
inrush current when the output is enabled. The start-up time
for the 2.8 V option is approximately 220 µs from the time the
ENx active threshold is crossed to when the output reaches 90%
of its final value. The start-up time is somewhat dependent on
the output voltage setting and increases slightly as the output
voltage increases.
09874-046
CH3
CH2
500mV
BW
1
2
T 10.2%
CH1 1V 500mV M100µs A CH1 540mV
BW
CH4 500mV
BW
BW
V
EN
V
OUT1
V
OUT2
V
OUT3
Figure 52. Typical Start-Up Time,
ILOAD1 = ILOAD2 = ILOAD3 = 100 mA,
CH1 = VEN, CH2 = VOUT1, CH3 = VOUT2, CH4 = VOUT3
ADP320 Data Sheet
Rev. C | Page 18 of 21
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADP320 triple LDO is protected against damage due to
excessive power dissipation by current and thermal overload
protection circuits. The ADP320 triple LDO is designed to
current limit when the output load reaches 300 mA (typical).
When the output load exceeds 300 mA, the output voltage is
reduced to maintain a constant current limit.
Thermal overload protection is built-in, which limits the
junction temperature to a maximum of 155°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation) when the junction temperature starts to rise
above 155°C, the output is turned off, reducing the output
current to zero. When the junction temperature drops below
140°C, the output is turned on again and the output current is
restored to its nominal value.
Consider the case where a hard short from VOUTx to GND
occurs. At first, the ADP320 triple LDO current limits, so that
only 300 mA is conducted into the short. If self-heating of the
junction is great enough to cause its temperature to rise above
155°C, thermal shutdown activates turning off the output and
reducing the output current to zero. As the junction tempera-
ture cools and drops below 140°C, the output turns on and
conducts 300 mA into the short, again causing the junction
temperature to rise above 155°C. This thermal oscillation
between 140°C and 154°C causes a current oscillation between
0 mA and 300 mA that continues as long as the short remains at
the output.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For reliable
operation, device power dissipation must be externally limited
so junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP320 triple LDO does not dissipate
a lot of heat due to high efficiency. However, in applications
with a high ambient temperature and high supply voltage to out-
put voltage differential, the heat dissipated in the package is
large enough that it can cause the junction temperature of the
die to exceed the maximum junction temperature of 125°C.
When the junction temperature exceeds 155°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 140°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is very important to guarantee reliable performance over all
conditions. The junction temperature of the die is the sum of
the ambient temperature of the environment and the tempera-
ture rise of the package due to the power dissipation, as shown
in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP320 triple LDO must not exceed 125°C. To ensure that the
junction temperature stays below this maximum value, the user
needs to be aware of the parameters that contribute to junction
temperature changes. These parameters include ambient tem-
perature, power dissipation in the power device, and thermal
resistances between the junction and ambient air (θJA). The θJA
number is dependent on the package assembly compounds used
and the amount of copper to which the GND pins of the package
are soldered on the PCB. Table 6 shows typical θJA values for the
ADP320 triple LDO for various PCB copper sizes.
Table 6. Typical θJA Values
Copper Size (mm
2
)
ADP320 Triple LDO (°C/W)
JEDEC1 49.5
100
83.7
500 68.5
1000 64.7
1 Device soldered to JEDEC standard board.
The junction temperature of the ADP320 triple LDO can be
calculated from the following equation:
TJ = TA + (PD × θJA) (2)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
PD = Σ[(VIN − VOUT) × ILOAD] + Σ(VIN × IGND) (3)
where:
ILOAD is the load current.
IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
Power dissipation due to ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to
TJ = TA + {Σ[(VIN − VOUT) × ILOAD] × θJA} (4)
As shown in Equation 4, for a given ambient temperature,
input-to-output voltage differential, and continuous load
current, there exists a minimum copper size requirement for the
PCB to ensure the junction temperature does not rise above
125°C. Figure 53 to Figure 56 show junction temperature
calculations for different ambient temperatures, total power
dissipation, and areas of PCB copper.
In cases where the board temperature is known, the thermal
characterization parameter, ΨJB, may be used to estimate the
junction temperature rise. TJ is calculated from TB and PD using
the formula
TJ = TB + (PD × ΨJB) (5)
The typical ΨJB value for the 16-lead 3 mm × 3 mm LFCSP is
25.2° C / W.
Data Sheet ADP320
Rev. C | Page 19 of 21
09874-047
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2
TOTAL POWER DI SSIPATION (W)
JUNCTI ON T EMPER
A
TURE, T
J
(°C)
1000mm
2
500mm
2
100mm
2
50mm
2
JEDEC
T
J
MAX
Figure 53. Junction Temperature vs. Total Power Dissipation, TA = 25°C
09874-048
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2
TOTAL POWER DISSIPATION (W)
JUNCTI ON TEMPE
R
A
TURE, T
J
(°C)
1000mm
2
500mm
2
100mm
2
50mm
2
JEDEC
T
J
MAX
Figure 54. Junction Temperature vs. Total Power Dissipation, TA = 50°C
09874-049
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2
TOTAL PO W E R DI SSIPATIO N (W )
JUNCTI ON TEMPE R
A
TURE, T
J
(°C)
1000mm
2
500mm
2
100mm
2
50mm
2
JEDEC
T
J
MAX
Figure 55. Junction Temperature vs. Total Power Dissipation, TA = 85°C
09874-050
0
20
40
60
80
100
120
140
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
TOTAL POWER DIS SIPATIO N ( W)
JUNCTION TEMPER
A
TURE, T
J
(°C)
T
B
= 25°C
T
B
= 50°C
T
B
= 85°C
T
J
MAX
Figure 56. Junction Temperature vs. Total Power Dissipation and
Board Temperature
ADP320 Data Sheet
Rev. C | Page 20 of 21
PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS
Heat dissipation from the package can be improved by
increasing the amount of copper attached to the pins of the
ADP320 triple LDO. However, as can be seen from Table 6, a
point of diminishing returns eventually is reached, beyond
which an increase in the copper size does not yield significant
heat dissipation benefits.
Place the input capacitor as close as possible to the VINx and
GND pins. Place the output capacitors as close as possible to the
VOUTx and GND pins. Use 0402 or 0603 size capacitors and
resistors to achieve the smallest possible footprint solution on
boards where area is limited.
09874-051
Figure 57. Example of PCB Layout, Top Side
09874-052
Figure 58. Example of PCB Layout, Bottom Side
Data Sheet ADP320
Rev. C | Page 21 of 21
OUTLINE DIMENSIONS
0.30
0.23
0.18
1.75
1.60 SQ
1.45
3.10
3.00 SQ
2.90
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
16
5
8
9
12
13
4
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
0.80
0.75
0.70
COMPLIANT
TO
JEDEC STANDARDS MO-220-WEED-6.
PKG-005138
SEATING
PLANE
TOP VIEW
EXPOSED
PAD
02-23-2017-E
PIN 1
INDIC
A
TOR AREA OPTIONS
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 59. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Output Voltage (V)2 Package Description Package Option Branding
ADP320ACPZ331815R7 −40°C to +125°C 3.3, 1.8, 1.5 16-Lead LFCSP CP-16-22 LGP
ADP320ACPZ-110-R7
−40°C to +125°C
3.3, 3.3, 1.5
16-Lead LFCSP
CP-16-22
L15
1 Z = RoHS Compliant Part.
2 For additional voltage options, contact a local Analog Devices sales or distribution representative.
©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09874-0-2/17(C)