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Stratix V Device Overview

2014.04.08

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Many of the Stratix®V devices and features are enabled in the Quartus®II software version 13.0. The

remaining devices and features will be enabled in future versions of the Quartus II software.

Altera’s 28-nm Stratix V FPGAs include innovations such as an enhanced core architecture, integrated

transceivers up to 28.05 gigabits per second (Gbps), and a unique array of integrated hard intellectual property

(IP) blocks. With these innovations, Stratix V FPGAs deliver a new class of application-targeted devices

optimized for:

•Bandwidth-centric applications and protocols, including PCI Express®(PCIe®) Gen3

•Data-intensive applications for 40G/100G and beyond

•High-performance, high-precision digital signal processing (DSP) applications

Stratix V devices are available in four variants (GT, GX, GS, and E), each targeted for a different set of

applications. For higher volume production, you can prototype with Stratix V FPGAs and use the low-risk,

low-cost path to HardCopy®V ASICs.

Related Information

•Stratix V Device Handbook: Known Issues

Lists the planned updates to the Stratix V Device Handbook chapters.

•Upcoming Stratix V Device Features

Stratix V Family Variants

The Stratix V device family contains the GT, GX, GS, and E variants.

Stratix V GT devices, with both 28.05-Gbps and 12.5-Gbps transceivers, are optimized for applications that

require ultra-high bandwidth and performance in areas such as 40G/100G/400G optical communications

systems and optical test systems. 28.05-Gbps and 12.5-Gbps transceivers are also known as GT and GX

channels, respectively.

Stratix V GX devices offer up to 66 integrated transceivers with 14.1-Gbps data rate capability. These

transceivers also support backplane and optical interface applications. These devices are optimized for high-

performance, high-bandwidth applications such as 40G/100G optical transport, packet processing, and

traffic management found in wireline, military communications, and network test equipment markets.

Stratix V GS devices have an abundance of variable precision DSP blocks, supporting up to 3,926 18x18 or

1,963 27x27 multipliers. In addition, Stratix V GS devices offer integrated transceivers with 14.1-Gbps data

rate capability. These transceivers also support backplane and optical interface applications. These devices

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are optimized for transceiver-based DSP-centric applications found in wireline, military, broadcast, and

high-performance computing markets.

Stratix V E devices offer the highest logic density within the Stratix V family with nearly one million logic

elements (LEs) in the largest device. These devices are optimized for applications such as ASIC and system

emulation, diagnostic imaging, and instrumentation.

Common to all Stratix V family variants are a rich set of high-performance building blocks, including a

redesigned adaptive logic module (ALM), 20 Kbit (M20K) embedded memory blocks, variable precision

DSP blocks, and fractional phase-locked loops (PLLs). All of these building blocks are interconnected by

Altera’s superior multi-track routing architecture and comprehensive fabric clocking network.

Also common to Stratix V devices is the new Embedded HardCopy Block, which is a customizable hard IP

block that leverages Altera’s unique HardCopy ASIC capabilities. The Embedded HardCopy Block in Stratix V

FPGAs is used to harden IP instantiation of PCIe Gen3, Gen2, and Gen1.

Stratix V Features Summary

Table 1: Summary of Features for Stratix V Devices

DescriptionFeature

•28-nm TSMC process technology

•0.85-V or 0.9-V core voltage

Technology

•28.05-Gbps transceivers on Stratix V GT devices

•Electronic dispersion compensation (EDC) for XFP, SFP+, QSFP, CFP optical

module support

•Adaptive linear and decision feedback equalization

•Transmitter pre-emphasis and de-emphasis

•Dynamic reconfiguration of individual channels

•On-chip instrumentation (EyeQ non-intrusive data eye monitoring)

Low-power serial

transceivers

•600-Megabits per second (Mbps) to 12.5-Gbps data rate capabilityBackplane capability

•1.6-Gbps LVDS

•1,066-MHz external memory interface

•On-chip termination (OCT)

•1.2-V to 3.3-V interfacing for all Stratix V devices

General-purpose I/Os

(GPIOs)

•PCIe Gen3, Gen2, and Gen1 complete protocol stack, x1/x2/x4/x8 end point

and root port

Embedded HardCopy

Block

•Interlaken physical coding sublayer (PCS)

•Gigabit Ethernet (GbE) and XAUI PCS

•10G Ethernet PCS

•Serial RapidIO®(SRIO) PCS

•Common Public Radio Interface (CPRI) PCS

•Gigabit Passive Optical Networking (GPON) PCS

Embedded transceiver hard

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DescriptionFeature

•Programmable Power Technology

•Quartus II integrated PowerPlay Power Analysis

Power management

•Enhanced ALM with four registers

•Improved routing architecture reduces congestion and improves compile

times

High-performance core

fabric

•M20K: 20-Kbit with hard error correction code (ECC)

•MLAB: 640-bit

Embedded memory blocks

•Up to 600 MHz performance

•Natively support signal processing with precision ranging from 9x9 up to

54x54

•New native 27x27 multiply mode

•64-bit accumulator and cascade for systolic finite impulse responses (FIRs)

•Embedded internal coefficient memory

•Pre-adder/subtractor improves efficiency

•Increased number of outputs allows more independent multipliers

Variable precision DSP

blocks

•Fractional mode with third-order delta-sigma modulation

•Integer mode

•Precision clock synthesis, clock delay compensation, and zero delay buffer

(ZDB)

Fractional PLLs

•800-MHz fabric clocking

•Global, quadrant, and peripheral clock networks

•Unused clock networks can be powered down to reduce dynamic power

Clock networks

•Serial and parallel flash interface

•Enhanced advanced encryption standard (AES) design security features

•Tamper protection

•Partial and dynamic reconfiguration

•Configuration via Protocol (CvP)

Device configuration

•Multiple device densities with identical package footprints enables seamless

migration between different FPGA densities

•FBGA packaging with on-package decoupling capacitors

•Lead and RoHS-compliant lead-free options

High-performance

packaging

—HardCopy V migration

Stratix V Family Plan

The following tables list the features of the different Stratix V devices.

The information in this section is correct at the time of publication. For the latest information and to get

more details, refer to the Altera Product Selector.

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Table 2: Stratix V GT Device Features

5SGTC75SGTC5Feature

622425Logic Elements (K)

939642Registers (K)

4/324/3228.05/12.5-Gbps Transceivers

11PCIe hard IP Blocks

2828Fractional PLLs

2,5602,304M20K Memory Blocks

5045M20K Memory (MBits)

512512Variable Precision Multipliers (18x18)

256256Variable Precision Multipliers (27x27)

44DDR3 SDRAM x72 DIMM Interfaces

User I/Os(1), Full-Duplex LVDS, 28.05/12.5-Gbps Transceivers

5SGTC75SGTC5Package (2) (3)

600, 150, 36600, 150, 36KF40-F1517 (4)

Table 3: Stratix V GX Device Features

5SGXBB5SGXB95SGXB65SGXB55SGXAB5SGXA95SGXA75SGXA55SGXA45SGXA3Features

952840597490952840622490420340Logic

Elements

(K)

1,4371,2689027401,4371,268939740634513Registers

(K)

6666666636 or 4836 or 4824, 36,

or 48

24, 36,

or 48

24 or 3612, 24,

or 36

14.1-Gbps

Transceivers

1 or 41 or 41 or 41 or 41, 2, or

1, 2, or

1 or 21 or 2PCIe hard

IP Blocks

(1) The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os

includes transceiver I/Os.

(2) Packages are flipchip ball grid array (1.0-mm pitch).

(3) Each package row offers pin migration (common board footprint) for all devices in the row.

(4) Migration between select Stratix V GT devices and Stratix V GX devices is available. For more information,

refer to Table 6 and to AN 644: Migration Between Stratix V GX and Stratix V GT Devices.

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5SGXBB5SGXB95SGXB65SGXB55SGXAB5SGXA95SGXA75SGXA55SGXA45SGXA3Features

32322424282828282420 (5)

Fractional

PLLs

2,6402,6402,6602,1002,6402,6402,5602,3041,900957M20K

Memory

Blocks

52525241525250453719M20K

Memory

(MBits)

704704798798704704512512512512Variable

Precision

Multipliers

(18x18)

352352399399352352256256256256Variable

Precision

Multipliers

(27x27)

4444666644DDR3

SDRAM

x72 DIMM

Interfaces

User I/Os(1), Full-Duplex LVDS, 14.1-Gbps Transceivers

5SGXBB5SGXB95SGXB65SGXB55SGXAB5SGXA95SGXA75SGXA55SGXA45SGXA3Package (2) (3)

(6) (7)

—————————360, 90,

12H

EH29-

H780

——————552,

138, 24

552,

138, 24

552,

138, 24

432,

108, 24

HF35-

F1152 (8)

——————432,

108, 36

432,

108, 36

432,

108, 36

432,

108, 36

KF35-

F1152

(5) The F1517 package contains 24 PLLs. The other packages with this device contain 20 PLLs.

(6) LVDS counts are full duplex channels. Each full duplex channel is one transmitter (TX) pair plus one receiver

(RX) pair.

(7) A superscript Hafter the number of transceivers indicates that this device is only available in a hybrid package.

Hybrid packages are slightly larger than conventional FBGAs. Refer to Altera’s packaging documentation for

more information.

(8) Migration between select Stratix V GX devices and Stratix V GS devices is available. For more information,

refer to Table 6.

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User I/Os(1), Full-Duplex LVDS, 14.1-Gbps Transceivers

5SGXBB5SGXB95SGXB65SGXB55SGXAB5SGXA95SGXA75SGXA55SGXA45SGXA3Package (2) (3)

(6) (7)

————696,

174,

36H

696,

174,

36H

696,

174, 36

696,

174, 36

696,

174, 36

696,

174, 36

KF40-

F1517 /

KH40-

H1517 (8)

——————600,

150, 48

600,

150, 48

——NF40-

F1517 (4)

——432,

108, 66

432,

108, 66

——————RF40-

F1517

——600,

150, 66

600,

150, 66

——————RF43-

F1760

600, 150, 66H

600,

150,

66H

————————RH43-

H1760

————840,

210, 48

840,

210, 48

840,

210, 48

840,

210, 48

——NF45-

F1932 (8)

Table 4: Stratix V GS Device Features

5SGSD85SGSD65SGSD55SGSD45SGSD3Features

695583457360236Logic Elements (K)

1,050880690543356Registers (K)

36 or 4836 or 4824 or 3612, 24, or 3612 or 2414.1-Gbps

transceivers

1, 2, or 41, 2, or 4111PCIe hard IP blocks

28282420 (5)

20Fractional PLLs

2,5672,3202,014957688M20K Memory

Blocks

5045391913M20K Memory

(MBits)

3,9263,5503,1802,0881,200Variable Precision

Multipliers (18x18)

1,9631,7751,5901,044600Variable Precision

Multipliers (27x27)

66442DDR3 SDRAM x72

DIMM Interfaces

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User I/Os(1), Full-Duplex LVDS, 14.1-Gbps Transceivers

5SGSD85SGSD65SGSD55SGSD45SGSD3Package (2) (3) (6) (7)

———360, 90, 12H

360, 90, 12H

EH29-H780

——552, 138, 24432, 108, 24432, 108, 24HF35-F1152 (8)

696, 174, 36696, 174, 36696, 174, 36696, 174, 36—KF40-F1517 (8)

840, 210, 48840, 210, 48———NF45-F1932 (8)

Table 5: Stratix V E Device Features

5SEEB5SEE9Features

952840Logic Elements (K)

1,4371,268Registers (K)

2828Fractional PLLs

2,6402,640M20K Memory Blocks

5252M20K Memory (MBits)

704704Variable Precision Multipliers (18x18)

352352Variable Precision Multipliers (27x27)

66DDR3 SDRAM x72 DIMM Interfaces

User I/Os(1), Full-Duplex LVDS

5SEEB5SEE9Package (2) (3) (6) (7)

696, 174H

H40-H1517

840, 210840, 210F45-F1932

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Table 6: Device Migration List Across All Stratix V Device Variants

All devices in a specific column allow migration.

Package

RH43-

H1760

F45-

F1932

NF45-

F1932

(10)

RF43-

F1760

H40-

H1517

RF40-

F1517

NF40/

KF40-

F1517

(11) (12)

KF40-

F1517/

KH40-

H1517

(10)

KF35-

F1152

HF35-

F1152

(9)

EH29-

H780

Stratix V GX devices

YesYesYesYesA3

YesYesYesA4

YesYesYesYesYesA5

YesYesYesYesYesA7

YesYesA9

YesYesAB

YesYesB5

YesYesB6

YesB9

YesBB

Stratix V GT devices

YesC5

YesC7

Stratix V GS devices

YesYesD3

YesYesYesD4

YesYesD5

YesYesD6

YesYesD8

Stratix V E devices

YesYesE9

(9) All devices in this column are in the HF35 package and have twenty-four 14.1-Gbps transceivers.

(10) Different devices within this column have small differences in the overall package height. When multiple Stratix

V devices with different package heights are placed on a single board, a single-piece heatsink may not cover

the devices evenly. Refer to AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages.

(11) The 5SGTC5/7 devices in the KF40 package have four 28.05-Gbps transceivers and thirty-two 12.5-Gbps

transceivers. Other devices in this column are in the NF40 package and have forty-eight 14.1-Gbps transceivers.

(12) For more information, refer to AN 644: Migration Between Stratix V GX and Stratix V GT Devices.

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Package

YesYesEB

To verify the pin migration compatibility, use the Pin Migration View window in the Quartus II

software Pin Planner.

Note:

Related Information

•Altera Product Selector

Provides the latest information about Altera products.

•For more information about verifying the pin migration compatibility, refer to the I/O Management

chapter in volume 2 of the Quartus II Handbook.

•For full package details, refer to the Package information datasheet for Altera devices.

•AN 644: Migration Between Stratix V GX and Stratix V GT Devices

•AN 670: Thermal Solutions to Address Height Variation in Stratix V Packages

Low-Power Serial Transceivers

Stratix V FPGAs deliver the industry’s most flexible transceivers with the highest bandwidth from 600 Mbps

to 28.05 Gbps, low bit error ratio (BER), and low power. Stratix V transceivers have many enhancements to

improve flexibility and robustness. These enhancements include robust analog receiver clock and data

recovery (CDR), advanced pre-emphasis, and equalization. In addition, each channel provides full featured

embedded PCS hard IP to simplify the design, lower the power, and save valuable core resources.

Stratix V transceivers are compliant with a wide range of standard protocols and data rates and are equipped

with a variety of signal conditioning features to support backplane, optical module, and chip-to-chip

applications.

Stratix V transceivers are located on the left and right sides of the device, as shown in the figure below. The

transceivers are isolated from the rest of the chip to prevent core and I/O noise from coupling into the

transceivers, thereby ensuring optimal signal integrity. The transceiver channels consist of the physical

medium attachment (PMA), PCS, and high-speed clock networks. You can also configure unused transceiver

PMA channels as additional transmitter PLLs.

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Figure 1: Stratix V GT, GX, and GS Device Chip View

This figure represents one variant of a Stratix V device with transceivers. Other variants may have a different

floorplan than the one shown here.

PCS

PMA

(1)

Clock Networks

M20K Blocks

DSP Blocks

M20K Blocks

DSP Blocks

M20K Blocks

DSP Blocks

Core Logic

Fabric

Core Logic

Fabric

PMA

Per Channel: Standard PCS, 10G PCS, PCIe Gen3 PCS

PMA

Per Channel: Standard PCS, 10G PCS, PCIe Gen3 PCS

Embedded HardCopy BlockEmbedded HardCopy Block

Embedded HardCopy Block Embedded HardCopy Block

I/O, LVDS, and Memory Interface

Fractional PLLs

Note:

(1) You can use the unused transceiver channels as additional transceiver transmitter PLLs.

The following table lists the PMA features for the Stratix V transceivers.

Table 7: Transceiver PMA Features

CapabilityFeature

28.05 Gbps and 12.5 Gbps (Stratix V GT devices) and 14.1 Gbps

(Stratix V GX and GS devices)

Chip-to-chip support

12.5 Gbps (Stratix V GX, GS, and GT devices)Backplane support

PCIe cable and eSATA applicationsCable driving support

10G Form-factor Pluggable (XFP), Small Form-factor Pluggable

(SFP+), Quad Small Form-factor Pluggable (QSFP), CXP, 100G

Pluggable (CFP), 100G Form-factor Pluggable

Optical module support with EDC

Receiver 4-stage linear equalization to support high-attenuation

channels

Continuous Time Linear Equalization

(CTLE)

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CapabilityFeature

Receiver 5-tap digital equalizer to minimize losses and crosstalkDecision Feedback Equalization (DFE)

Adaptive engine to automatically adjust equalization to

compensate for changes over time

Adaptive equalization (AEQ)

Superior jitter tolerance versus phase interpolation techniquesPLL-based clock recovery

Flexible deserialization width and configurable word alignment

patterns

Programmable deserialization and word

alignment

Transmitter driver 4-tap pre-emphasis and de-emphasis for

protocol compliance under lossy conditions

Transmitter equalization (pre-emphasis)

Choice of transmitter PLLs per channel, optimized for specific

protocols and applications

Ring and LC oscillator transmitter PLLs

Allows non-intrusive on-chip monitoring of both width and

height of the data eye

On-chip instrumentation (EyeQ data-eye

monitor)

Allows reconfiguration of single channels without affecting

operation of other channels

Dynamic reconfiguration

Compliance with over 50 industry standard protocols in the range

of 600 Mbps to 28.05 Gbps

Protocol support

The Stratix V core logic connects to the PCS through an 8-, 10-, 16-, 20-, 32-, 40-, 64-, or 66-bit interface,

depending on the transceiver data rate and protocol. Stratix V devices contain PCS hard IP to support PCIe

Gen3, Gen2, Gen1, Interlaken, 10GE, XAUI, GbE, SRIO, CPRI, and GPON protocols. All other standard

and proprietary protocols are supported through the transceiver PCS hard IP. The following table lists the

transceiver PCS features.

Table 8: Transceiver PCS Features

Receiver Data PathTransmitter Data PathData Rates (Gbps)Protocol

Word aligner, de-skew FIFO,

rate match FIFO, 8B/10B

decoder, byte deserializer, and

byte ordering

Phase compensation FIFO, byte

serializer, 8B/10B encoder, bit-slip,

and channel bonding

0.6 to 8.5Custom PHY

RX FIFO and gear boxTX FIFO, gear box, and bit-slip9.98 to 14.1Custom 10G

PHY

Same as custom PHY plus PIPE

2.0 interface to core logic

Same as custom PHY plus PIPE 2.0

interface to core logic

2.5 and 5.0x1, x4, x8 PCIe

Gen1 and Gen2

Block synchronization, rate

match FIFO, decoder,

de-scrambler, and phase

compensation FIFO

Phase compensation FIFO,

encoder, scrambler, gear box, and

bit-slip

8x1, x4, x8 PCIe

Gen3

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Receiver Data PathTransmitter Data PathData Rates (Gbps)Protocol

RX FIFO, 64/66 decoder,

de-scrambler, block synchro-

nization, and gear box

TX FIFO, 64/66 encoder,

scrambler, and gear box

10.312510G Ethernet

RX FIFO, frame generator,

CRC-32 checker, frame

decoder, descrambler, disparity

checker, block synchronization,

and gearbox

TX FIFO, frame generator, CRC-32

generator, scrambler, disparity

generator, and gear box

4.9 to 14.1Interlaken

RX FIFO, 64/66 decoder,

de-scrambler, lane reorder,

deskew, alignment marker lock,

block synchronization, gear

box, and destripper

TX FIFO, 64/66 encoder,

scrambler, alignment marker

insertion, gearbox, and block

striper

4 x 10.312540GBASE-R

Ethernet

10 x 10.3125100GBASE-R

Ethernet

RX FIFO, lane deskew, and byte

de-serializer

TX FIFO, channel bonding, and

byte serializer

(4 +1) x 11.3

OTN 40 and 100

(10 +1) x 11.3

Same as custom PHY plus GbE

state machine

Same as custom PHY plus GbE

state machine

1.25GbE

Same as custom PHY plus

XAUI state machine for re-

aligning four channels

Same as custom PHY plus XAUI

state machine for bonding four

channels

3.125 to 4.25XAUI

Same as custom PHY plus SRIO

V2.1compliant x2 and x4

deskew state machine

Same as custom PHY plus SRIO

V2.1 compliant x2 and x4 channel

bonding

1.25 to 6.25SRIO

Same as custom PHY plus RX

deterministic latency

Same as custom PHY plus TX

deterministic latency

0.6144 to 9.83CPRI

Same as custom PHYSame as custom PHY1.25, 2.5, and 10GPON

PCIe Gen3, Gen2, and Gen1 Hard IP (Embedded HardCopy Block)

Stratix V devices have PCIe hard IP designed for performance, ease-of-use, and increased functionality. The

PCIe hard IP consists of the PCS, data link, and transaction layers. The PCIe hard IP supports Gen3, Gen2,

and Gen1 end point and root port up to x8 lane configurations.

The Stratix V PCIe hard IP operates independently from the core logic, which allows the PCIe link to wake

up and complete link training in less than 100 ms while the Stratix V device completes loading the

programming file for the rest of the FPGA. The PCIe hard IP also provides added functionality, which helps

support emerging features such as Single Root I/O Virtualization (SR-IOV) or optional protocol extensions.

In addition, the Stratix V device PCIe hard IP has improved end-to-end data path protection using ECC

and enables device CvP.

In all Stratix V devices, the primary PCIe hard IP that supports CvP is always in the bottom left corner of

the device (IOBANK_B0L) when viewing the die from the top.

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External Memory and GPIO

Each Stratix V I/O block has a hard FIFO that improves the resynchronization margin as data is transferred

from the external memory to the FPGA.

The hard FIFO also lowers PHY latency, resulting in higher random access performance. GPIOs include

on-chip dynamic termination to reduce the number of external components and minimize reflections. On-

package decoupling capacitors suppress noise on the power lines, which reduce noise coupling into the I/Os.

Memory banks are isolated to prevent core noise from coupling to the output, thus reducing jitter and

providing optimal signal integrity.

The external memory interface block uses advanced calibration algorithms to compensate for process, voltage

and temperature (PVT) variations in the FPGA and external memory components. The advanced algorithms

ensure maximum bandwidth and a robust timing margin across all conditions. Stratix V devices deliver a

complete memory solution with the High Performance Memory Controller II (HPMC II) and UniPHY

MegaCore®IP that simplifies a design for today’s advanced memory modules. The following table lists

external memory interface block performance.

Table 9: External Memory Interface Performance

The specifications listed in this table are performance targets. For a current achievable performance, use the External

Memory Interface Spec Estimator.

Performance (MHz)Interface

933DDR3

400DDR2

350QDR II

550QDR II+

533RLDRAM II

800RLDRAM III

Related Information

External Memory Interface Spec Estimator

Adaptive Logic Module

Stratix V devices use an improved ALM to implement logic functions more efficiently. The Stratix V ALM

has eight inputs with a fracturable look-up table (LUT), two dedicated embedded adders, and four dedicated

registers.

The Stratix V ALM has the following enhancements:

•Packs 6% more logic when compared with the ALM found in Stratix IV devices.

•Implements select 7-input LUT-based functions, all 6-input logic functions, and two independent functions

consisting of smaller LUT sizes (such as two independent 4-input LUTs) to optimize core usage.

•Adds more registers (four registers per 8-input fracturable LUT). More registers allow Stratix V devices

to maximize core performance at a higher core logic usage and provides easier timing closure for register-

rich and heavily pipelined designs.

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The Quartus II software leverages the Stratix V ALM logic structure to deliver the highest performance,

optimal logic usage, and lowest compile times. The Quartus II software simplifies design re-use because it

automatically maps legacy Stratix designs into the new Stratix V ALM architecture.

Clocking

The Stratix V device core clock network is designed to support 800-MHz fabric operations and 1,066-MHz

and 1,600-Mbps external memory interfaces.

The clock network architecture is based on Altera’s proven global, quadrant, and peripheral clock structure,

which is supported by dedicated clock input pins and fractional clock synthesis PLLs. The Quartus II software

identifies all unused sections of the clock network and powers them down, which reduces power consumption.

Fractional PLL

Stratix V devices contain up to 32 fractional PLLs.

You can use the fractional PLLs to reduce both the number of oscillators required on the board and the clock

pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In

addition, you can use the fractional PLLs for clock network delay compensation, zero delay buffering, and

transmitter clocking for transceivers. Fractional PLLs can be individually configured for integer mode or

fractional mode with third-order delta-sigma modulation.

Embedded Memory

Stratix V devices contain two types of embedded memory blocks: MLAB (640-bit) and M20K (20-Kbit).

MLAB blocks are ideal for wide and shallow memories. M20K blocks are useful for supporting larger memory

configurations and include ECC.

Both types of memory blocks operate up to 600 MHz and can be configured to be a single- or dual-port

RAM, FIFO, ROM, or shift register. These memory blocks are flexible and support a number of memory

configurations, as shown in the following table.

Table 10: Embedded Memory Block Configuration

M20K (20,480 Bits)MLAB (640 Bits)

512x40

1Kx20

2Kx10

4Kx5

8Kx2

16Kx1

32x20

64x10

The Quartus II software simplifies design re-use by automatically mapping memory blocks from legacy

Stratix devices into the Stratix V memory architecture.

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Variable Precision DSP Block

Stratix V FPGAs feature the industry’s first variable precision DSP block that you can configure to natively

support signal processing with precision ranging from 9x9 to 36x36.

You can independently configure each DSP block at compile time as either a dual 18x18 multiply accumulate

or a single 27x27 multiply accumulate. With a dedicated 64-bit cascade bus, you can cascade multiple variable

precision DSP blocks to implement even higher precision DSP functions efficiently. The following

table describes how variable precision is accommodated within a DSP block or by using multiple blocks.

Table 11: Variable Precision DSP Block Configurations

Expected UsageDSP Block ResourcesMultiplier Size (bits)

Low precision fixed point1/3 of variable precision DSP block9x9

Medium precision fixed point1/2 of variable precision DSP block18x18

High precision fixed or single precision floating

point

1 variable precision DSP block27x27

Very high precision fixed point2 variable precision DSP blocks36x36

Complex multiplication is common in DSP algorithms. One of the most popular applications of complex

multipliers is the fast Fourier transform (FFT) algorithm, which increases precision requirements on only

one side of the multiplier. The variable precision DSP block is designed to support the FFT algorithm with

a proportional increase in DSP resources with precision growth. The following table lists complex multipli-

cation with variable precision DSP blocks.

Table 12: Complex Multiplication with Variable Precision DSP Blocks

Expected UsageDSP Block ResourcesMultiplier Size (bits)

Resource optimized FFTs2 variable precision DSP blocks18x18

Accommodate bit growth through FFT stages3 variable precision DSP blocks18x25

Highest precision FFT stages4 variable precision DSP blocks18x36

Single precision floating point4 variable precision DSP blocks27x27

For FFT applications with high dynamic range requirements, only the Altera®FFT MegaCore offers an

option of single precision floating point implementation, with the resource usage and performance similar

to high-precision fixed point implementations.

Other new features include:

•64-bit accumulator, the largest in the industry

•Hard pre-adder, available in both 18- and 27-bit modes

•Cascaded output adders for efficient systolic FIR filters

•Internal coefficient register banks

•Enhanced independent multiplier operation

•Efficient support for single- and double-precision floating point arithmetic

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•Ability to infer all the DSP block modes through HDL code using the Altera Complete Design Suite

The variable precision DSP block is ideal for higher bit precision in high-performance DSP applications. At

the same time, the variable precision DSP block can efficiently support the many existing 18-bit DSP

applications, such as high definition video processing and remote radio heads. Stratix V FPGAs, with the

variable precision DSP block architecture, are the only FPGA family that can efficiently support many

different precision levels, up to and including floating point implementations. This flexibility results in

increased system performance, reduced power consumption, and reduced architecture constraints for system

algorithm designers.

Power Management

Stratix V devices leverage FPGA architectural features and process technology advancements to reduce total

power consumption by up to 30% when compared with Stratix IV devices at the same performance level.

Stratix V devices continue to provide programmable power technology, introduced in earlier generations

of Stratix FPGA families. The Quartus II software PowerPlay feature identifies critical timing paths in a

design and biases core logic in that path for high performance. PowerPlay also identifies non-critical timing

paths and biases core logic in that path for low power instead of high performance. PowerPlay automatically

biases core logic to meet performance and optimize power consumption.

Additionally, Stratix V devices have a number of hard IP blocks that reduce logic resources and deliver

substantial power savings when compared with soft implementations. The list includes PCIe Gen1/Gen2/Gen3,

Interlaken PCS, hard I/O FIFOs, and transceivers. Hard IP blocks consume up to 50% less power than

equivalent soft implementations.

Stratix V transceivers are designed for power efficiency. The transceiver channels consume 50% less power

than Stratix IV FPGAs. The transceiver PMA consumes approximately 90 mW at 6.5 Gbps and 170 mW at

12.5 Gbps.

Incremental Compilation

The Quartus II software incremental compilation feature reduces compilation time by up to 70% and preserves

performance to ease timing closure.

Incremental compilation supports top-down, bottom-up, and team-based design flows. Incremental

compilation facilitates modular hierarchical and team-based design flows where a team of designers work

in parallel on a design. Different designers or IP providers can develop and optimize different blocks of the

design independently, which you can then import into the top-level project.

Enhanced Configuration and CvP

Stratix V device configuration is enhanced for ease-of-use, speed, and cost.

Stratix V devices support a new 4-bit bus active serial mode (ASx4). ASx4 supports up to a 400Mbps data

rate using small low-cost quad interface Flash devices. ASx4 mode is easy to use and offers an ideal balance

between cost and speed. Finally, the fast passive parallel (FPP) interface is enhanced to support 8-, 16-, and

32-bit data widths to meet a wide range of performance and cost goals.

You can configure Stratix V FPGAs using CvP with PCIe. CvP with PCIe divides the configuration process

into two parts: the PCIe hard IP and periphery and the core logic fabric. CvP uses a much smaller amount

of external memory (flash or ROM) because CvP has to store only the configuration file for the PCIe hard

IP and periphery. The 100-ms power-up to active time (for PCIe) is much easier to achieve when only the

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PCIe hard IP and periphery are loaded. After the PCIe hard IP and periphery are loaded and the root port

is booted up, application software running on the root port can send the configuration file for the FPGA

fabric across the PCIe link where the file is loaded into the FPGA. The FPGA is then fully configured and

functional.

The following table lists the configuration modes available for Stratix V devices.

Table 13: Configuration Modes for Stratix V Devices

Max Data Rate

(Mbps)

Max Clock

Rate (MHz)

Data WidthRemote

Update

EncryptionCompres-

sion

Fast or

Slow POR

Mode

4001001, 4YesYesYesYesActive Serial

(AS)

1251251—YesYesYesPassive Serial

(PS)

3,000125 (14)

8, 16, 32Yes (13)

YesYesYesFast Passive

Parallel (FPP)

3,000—1, 2, 4, 8YesYes——CvP

2,00012516YesYes——Partial

Reconfigura-

tion

33331————JTAG

Partial Reconfiguration

Partial reconfiguration allows you to reconfigure part of the FPGA while other sections continue to operate.

This capability is required in systems where uptime is critical because partial reconfiguration allows you to

make updates or adjust functionality without disrupting services. While lowering power and cost, partial

reconfiguration also increases the effective logic density by removing the necessity to place FPGA functions

that do not operate simultaneously. Instead, you can store these functions in external memory and load

them as required. This capability reduces the size of the FPGA by allowing multiple applications on a single

FPGA, saving board space and reducing power.

You no longer need to know all the details of the FPGA architecture to perform partial reconfiguration.

Altera simplifies the process by extending the power of incremental compilation used in earlier versions of

the Quartus II software.

Partial reconfiguration is supported in the following configurations:

•Partial reconfiguration through the FPP x16 I/O interface

•CvP

•Soft internal core, such as the Nios®II processor.

(13) Remote update support with the Parallel Flash Loader.

(14) The maximum clock rate is 125 MHz for x8 and x16 FPP, but only 100 MHz for x32 FPP.

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Automatic Single Event Upset Error Detection and Correction

Stratix V devices offer single event upset (SEU) error detection and correction circuitry that is robust and

easy to use.

The correction circuitry includes protection for configuration RAM (CRAM) programming bits and user

memories. The CRAM is protected by a continuously running cyclical redundancy check (CRC) error

detection circuit with integrated ECC that automatically corrects one or double-adjacent bit errors and

detects higher order multi-bit errors. When more than two errors occur, correction is available through a

core programming file reload that refreshes a design while the FPGA is operating.

The physical layout of the FPGA is optimized to make the majority of multi-bit upsets appear as independent

single- or double-adjacent bit errors, which are automatically corrected by the integrated CRAM ECC

circuitry. In addition to the CRAM protection in Stratix V devices, user memories include integrated ECC

circuitry and are layout-optimized to enable error detection of 3-bit errors and correction for 2-bit errors.

HardCopy V Devices

HardCopy V ASICs offer the lowest risk and lowest total cost in ASIC designs with embedded high-speed

transceivers. You can prototype and debug with Stratix V FPGAs, then use HardCopy V ASICs for volume

production. The proven turnkey process creates a functionally equivalent HardCopy V ASIC with or without

embedded transceivers to meet all timing constraints in as little as 12 weeks.

The powerful combination of Stratix V FPGAs and HardCopy V ASICs can help you meet your design

requirements. Whether you plan for ASIC production and require the lowest-risk, lowest-cost path from

specification to production or require a cost reduction path for your FPGA-based systems, Altera provides

the optimal solution for power, performance, and device bandwidth.

Ordering Information

This section describes ordering information for Stratix V GT, GX, GS, and E devices.

The following figure shows the ordering codes for Stratix V devices.

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Figure 2: Ordering Information for Stratix V Devices

Family Signature

Embedded HardCopy

Block Variant

Transceiver Count

Transceiver PMA

Speed Grade

Package Type

Ball Array Dimension

Corresponds to pin count

Operating Temperature

Transceiver PCS and

FPGA Fabric Speed Grade

Optional Suffix (2)

(1)

GX : 14.1-Gbps transceivers

GT : 28.05-Gbps transceivers

GS: DSP-Oriented

E: Highest logic density,

no transceivers

M : Mainstream

E : Extended

5S : Stratix V

GX GT GS E

A3 C5 D3 E9

A4 C7 D4 EB

A5 D5

A7 D6

A9 D8

E : 12

H : 24

K : 36

N : 48

R : 66

1 (fastest)

F : FineLine BGA

H : Hybrid FineLine BGA

29 : 780 pins

35 : 1,152 pins

40 : 1,517 pins

43 : 1,760 pins

45 : 1,932 pins

C : Commercial (0 to 85°C)

I : Industrial (–40 to 100°C)

1 (fastest)

L : Low-power device

N : Lead-free packaging

ES : Engineering sample silicon

5S GX M A5 K 3F 35 C 2 L N ES

Member Code

Family Variant

Notes:

(1) Stratix V mainstream “M” devices have exactly one instantiation of PCI Express hard IP. Extended “E” devices have either two or four instantiations of PCI Express hard IP,

depending on the device and package combination. For non-transceiver Stratix V devices, this character does not appear in the part number.

(2) You can select one of these options, or you can ignore these options.

Document Revision History

Table 14: Document Revision History

Changes MadeVersionDate

Updated "Variable precision DSP blocks" section of the

"Features Summary" table to 600 MHz performance.

2014.04.08April 2014

•Updated GPIOs section of the "Features Summary" table

to 1.6 Gbps LVDS.

•Changed clocking speed to 800 MHz in the "Features

Summary" and the "Clocking" sections.

2014.04.03April 2014

•Added link to Altera Product Selector in the "Stratix V

Family Plan" section.

•Corrected DDR2 performance from 533 MHz to 400 MHz.

•Updated "Device Migration List Across All Stratix V Device

Variants" table.

2014.01.10January 2014

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Changes MadeVersionDate

•Added link to the known document issues in the

Knowledge Base.

•Updated backplane support information.

•Added a note about the number of I/Os to each table in

the "Stratix V Family Plan" section.

•Updated the "Ordering Information for Stratix V Devices"

figure.

2013.05.06May 2013

•Updated Table 6 and Table 13.

•Updated Figure 2.

3.1December 2012

•Converted chapter to stand-alone format and removed

from the Stratix V handbook.

•Changed title of document to Stratix V Device Overview

•Updated Figure 1.

•Minor text edits.

3.0June 2012

•Updated Table 1–2, Table 1–3, Table 1–4, and Table 1–5.

•Updated Figure 1–2.

•Updated “Automatic Single Event Upset Error Detection

and Correction”on page 18.

•Minor text edits.

2.3February 2012

Updated Table 1–2 and Table 1–3.2.2December 2011

•Changed Stratix V GT transceiver speed from 28 Gbps to

28.05 Gbps.

•Updated Figure 1–2.

2.1November 2011

•Revised Figure 1–2.

•Updated Table 1–5.

•Minor text edits.

2.0November 2011

Updated Table 1–2, Table 1–3, and Table 1–4.1.10September 2011

•Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4, and

Table 1–5.

•Updated Figure 1–2.

•Minor text edits.

1.9September 2011

Changed 800 MHz to 1,066 MHz for DDR3 in Table 1–8 and

in text.

1.8June 2011

•For Stratix V GT devices, changed 14.1 Gbps to 12.5 Gbps.

•Changed Configuration via PCIe to Configuration via

Protocol

•Updated Table 1–1, Table 1–2, Table 1–3, Table 1–4,

Table 1–5, and Table 1–6.

•Chapter moved to Volume 1.

1.7May 2011

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Changes MadeVersionDate

•Added Stratix V GS information.

•Updated tables listing device features.

•Added device migration information.

•Updated 12.5-Gbps transceivers to 14.1-Gbps transceivers

1.6January 2011

Updated Table 1-1.1.5December 2010

•Updated Table 1-1.

•Updated Figure 1-2.

•Converted to the new template.

•Minor text edits.

1.4December 2010

Updated Table 1–51.3July 2010

•Updated “Features Summary”on page 1–2

•Updated resource counts in Table 1–1 and Table 1–2

•Removed “Interlaken PCS Hard IP”and “10G Ethernet

Hard IP”

•Added “40G and 100G Ethernet Hard IP (Embedded

HardCopy Block)”on page 1–7

•Added information about Configuration via PCIe

•Added “Partial Reconfiguration”on page 1–12

•Added “Ordering Information”on page 1–14

1.2July 2010

Updated part numbers in Table 1–1 and Table 1–21.1May 2010

Initial release1.0April 2010

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