DATA SH EET
Product specification
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
HEF4050B
buffers
HEX non-inverting buffers
For a complete data sheet, please also download:
•The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
•The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
January 1995 2
Philips Semiconductors Product specification
HEX non-inverting buffers HEF4050B
buffers
DESCRIPTION
The HEF4050B provides six non-inverting buffers with
high current output capability suitable for driving TTL or
high capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also
be used to convert logic levels of up to 15 V to standard
TTL levels. Their guaranteed fan-out into common bipolar
logic elements is shown in the table below.
Fig.1 Functional diagram.
HEF4050BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4050BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4050BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
Fig.2 Pinning diagram.
Guaranteed fan-out in common logic families
DRIVEN ELEMENT GUARANTEED
FAN-OUT
standard TTL 2
74 LS 9
74 L 16
Fig.3 Logic diagram (one gate).
APPLICATION INFORMATION
Some examples of applications for the HEF4050B are:
•LOCMOS to DTL/TTL converter
•HIGH sink current for driving 2 TTL loads
•HIGH-to-LOW level logic conversion
Input protection
FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
Fig.4 Input protection circuit that allows input
voltages in excess of VDD.
January 1995 3
Philips Semiconductors Product specification
HEX non-inverting buffers HEF4050B
buffers
DC CHARACTERISTICS
VSS = 0 V; VI=V
SS or VDD
HEF VDD
VVO
VSYMBOL Tamb (°C)
−40 +25 +85
MIN. MAX. MIN. MAX. MIN. MAX.
Output (sink) 4,75 0,4 3,5 −2,9 −2,3 −mA
current LOW 10 0,5 IOL 12,0 −10,0 −8,0 −mA
15 1,5 24,0 −20,0 −16,0 −mA
Output (source) 5 4,6 0,52 −0,44 −0,36 −mA
current HIGH 10 9,5 IOH 1,3 −1,1 −0,9 −mA
15 13,5 3,6 −3,0 −2,4 −mA
Output (source)
current HIGH 5 2,5 IOH 1,7 −1,4 −1,1 −mA
HEC VDD
VVO
VSYMBOL Tamb (°C)
−55 +25 +125
MIN. MAX. MIN. MAX. MIN. MAX.
Output (sink) 4,75 0,4 3,6 −2,9 −1,9 −mA
current LOW 10 0,5 IOL 12,5 −10,0 −6,7 −mA
15 1,5 25,0 −20,0 −13,0 −mA
Output (source) 5 4,6 0,52 −0,44 −0,36 −mA
current HIGH 10 9,5 IOH 1,3 −1,1 −0,9 −mA
15 13,5 3,6 −3,0 −2,4 −mA
January 1995 4
Philips Semiconductors Product specification
HEX non-inverting buffers HEF4050B
buffers
AC CHARACTERISTICS
VSS = 0 V; Tamb =25°C; CL= 50 pF; input transition times ≤ 20 ns
VDD
VSYMBOL TYP. MAX. TYPICAL EXTRAPOLATION
FORMULA
Propagation delays 5 35 70 ns 26 ns +(0,18 ns/pF) CL
InOn10 tPHL 20 35 ns 16 ns +(0,08 ns/pF) CL
HIGH to LOW 15 15 30 ns 12 ns +(0,05 ns/pF) CL
5 55 110 ns 28 ns +(0,55 ns/pF) CL
LOW to HIGH 10 tPLH 25 55 ns 14 ns +(0,23 ns/pF) CL
15 20 40 ns 12 ns +(0,16 ns/pF) CL
Output transition 5 25 50 ns 7 ns +(0,35 ns/pF) CL
times 10 tTHL 10 20 ns 3 ns +(0,14 ns/pF) CL
HIGH to LOW 15 7 14 ns 2 ns +(0,09 ns/pF) CL
5 60 120 ns 10 ns +(1,0 ns/pF) CL
LOW to HIGH 10 tTLH 30 60 ns 9 ns +(0,42 ns/pF) CL
15 20 40 ns 6 ns +(0,28 ns/pF) CL
VDD
VTYPICAL FORMULA FOR P (µW)
Dynamic power 5 3 800 fi+∑(foCL)×VDD2where
dissipation per 10 11 600 fi+∑(foCL)×VDD2fi= input freq. (MHz)
package (P) 15 65 900 fi+∑(foCL)×VDD2fo= output freq. (MHz)
CL= load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
