W3J128M72G-XLBX W3J128M72G-XPBX 1GB - 128M x 72 DDR3 SDRAM FEATURES BENEFITS DDR3 Data Rate = 800, 1,066, 1333 Mb/s 30%** Space savings vs. FBGA Package: Reduced part count * 375 Plastic Ball Grid Array (PBGA), 20.5mm x 21.5mm 21% I/O reduction vs. FBGA * Future option: Low profile: 305 Plastic Ball Grid Array (PBGA), 21mm x 22mm. Estimated height = 2.5mm (0.100"). Address/control terminations included Differential clock terminations included Built-in decoupling * 1.0mm pitch Output drive calibration resistors (RZQ) included Supply Voltage = 1.5V Reduced trace lengths for lower parasitic capacitance 1.5V center terminated push/pull I/O Suitable for hi-reliability applications Differential bidirectional data strobe Enhanced thermal management Differential clock inputs (CK, CK#) Designed as "SODIMM in a BGA" - routed/designed as a DIMM (flyby, length matching) and all terminations included. The first true x72 DIMM in a single BGA package 8n-bit prefetch architecture Eight internal banks Fixed Burst length (BL) of 8 and Burst Chop (BC) of 4 Low profile future option is footprint compatible with current 375 PBGA package Selectable BC4 or BL8 on-the-fly (OTF) * This product is subject to change without notice. Auto Refresh and Self Refresh Modes ** Not including terminations or space between FBGAs. Nominal and dynamic On Die Termination (ODT) Programmable CAS latency: 5, 6, 7, 8, 9, 10 or 11 TYPICAL APPLICATION Posted CAS additive latency: 0, 1, 2 Write leveling Write latency = 5, 6, 7, 8, based on tCK RAM Commercial and industrial temperature ranges Host Organized as 1 rank of 128M x 72 (128M x 64 also available) FPGA/ Processor Lower voltage (1.35V) option available in same package DDR2/DDR3 W3X128M72-XBI SSD (SLC) MSM32/MSM64 (SATA BGA)) W7N16GVHxxBI (PATA BGA)) M400/M100/M50 (SATA, 2.5in) n)) FIGURE 1 - DENSITY COMPARISONS CSP Approach (mm) 9 96 14 FBGA W3J128M72G-XPBX 9 9 9 9 96 FBGA 96 FBGA 96 FBGA 96 FBGA 20.5 S A V I N G S 21.5 W3J128M72G-XPBX Area 5 x 126mm2 = 630mm2 440.75mm2 30%** I/O Count 5 x 96 balls = 480 balls 375 Balls 21% Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 1 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 2 - FUNCTIONAL BLOCK DIAGRAM FOR W3J128M72G-XPBX A0-13, BA0-2, RAS#, CAS# WE#, RST#, CKE, ODT, CS# CK# CK CCOMP 24 CK# CK 128M x 16 DM DQ DQS 11 DQS0, DQS0# DM0, DQ0-7 DM DQ DQS 11 DQS1, DQS1# DM1, DQ8-15 ZQ 240 24 CK# CK 128M x 16 DM DQ DQS 11 DQS2, DQS2# DM2, DQ16-23 DM DQ DQS 11 DQS3, DQS3# DM3, DQ24-31 ZQ 240 24 CK# CK 128M x 16 DM DQ DQS 11 DM DQ DQS 11 ZQ DQS4, DQS4# DM4, DQ32-39 X 240 24 CK# CK 128M x 16 DM DQ DQS 11 DQS5, DQS5# DM5, DQ40-47 DM DQ DQS 11 DQS6, DQS6# DM6, DQ48-55 ZQ 240 24 CK# CK 128M x 16 DM DQ DQS 11 DQS7, DQS7# DM7, DQ56-63 DM DQ DQS 11 DQS8, DQS8# DM8, DQ64-71 ZQ 240 VTT RTT NOTE: Block diagram shows actual fly-by order. RTT 23 VCC CTT Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 2 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 3 - PIN CONFIGURATION TOP VIEW 1 A 2 3 4 GND VCC DM7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DQS7# DQS7 DQ65 DQ69 DQ33 DQ39 DM4 DQ34 DQ36 DQ45 DQS6 DQS6# DQS5# DQS5 VCC GND GND A GND DQ50 DQ54 GND DM5 DQ41 GND DQ51 VCC GND B DQS4 DQS4# DQ48 DQ52 DQ43 DQ47 DQ55 DQ40 DQ46 VCC C B GND VCC DQ68 GND DQ60 DQ71 GND DQ56 DQ35 GND VCC C VCC DQ59 DQ70 DQ64 DQ62 DQ58 DQ67 DM8 DQ37 DQ32 DQ38 D DQ63 GND DQS8# GND DQ57 VCC VCC VCC GND VCC GND VCC GND VCC VCC VCC DQ42 GND DM6 GND DQ53 D E DQ61 DQ66 DQS8 DQ13 DQ15 GND VCC NC NC NC NC NC NC NC VCC GND DQ31 DQ28 DQ30 DQ49 DQ44 E F DQ11 DQ9 DQ12 DQS1# DQS1 GND VCC NC NC NC NC NC NC NC VCC GND DQ29 DQ24 DQS3 DQS3# DQ26 F G DM1 GND DQ14 GND DQ10 VCC VCC NC NC NC NC NC NC NC VCC VCC DQ27 GND DQ25 GND DM2 G H DQ0 DQ2 DQS0 DQ8 DM0 VCC VCC NC NC NC NC NC NC NC VCC VCC DQS2 DQ16 DM3 DQ17 DQ19 H J DQ6 DQ4 DQS0# DQ1 DQ3 GND GND NC NC NC NC NC NC NC GND GND DQS2# DQ22 DQ18 DQ23 DQ21 J GND DQ7 GND DQ5 GND GND NC NC NC NC NC NC NC GND GND NC GND DQ20 VCC K K L VCC VCC VREFDQ ODT VCC VCC VCC NC NC NC NC NC NC NC VCC VCC GND NC NC VCC VCC L M CK GND CAS# WE# VCC VCC VCC NC NC NC NC NC NC NC VCC VCC GND VCC GND GND GND M N CK# GND A10 BA2 GND GND GND NC NC NC NC NC NC NC GND GND VCC VCC VCC GND GND N P VCC VCC BA1 A0 GND GND GND NC NC NC NC NC NC NC GND GND VCC VCC VCC GND GND P R A4 A2 A6 VTT VCC VCC VCC VCC GND GND VCC GND GND VCC VCC VCC GND GND GND VCC VCC R T VCC VTT VTT A9 VCC VCC VCC NC A5 A12 CS# RAS# GND VCC VCC VCC GND GND GND GND VCC T U GND VCC VTT A8 GND GND GND DNU* A11 A3 DNU* CKE VCC GND GND GND VCC VCC VCC VCC GND U V GND GND VCC A13 GND GND GND RST# A7 A1 BA0 VREFCA VCC GND GND GND VCC VCC VCC GND GND V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 * Ball U8 is reserved for address A14 and ball U11 for A15 on future upgrades. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 3 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 3A - PIN CONFIGURATION FOR W3J128M72G-XLBX TOP VIEW 1 A 2 3 4 GND VCC DM7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DQS7# DQS7 DQ65 DQ69 DQ33 DQ39 DM4 DQ34 DQ36 DQ45 DQS6 DQS6# DQS5# DQS5 VCC GND GND A GND DQ50 DQ54 GND DM5 DQ41 GND DQ51 VCC GND B DQS4 DQS4# DQ48 DQ52 DQ43 DQ47 DQ55 DQ40 DQ46 VCC C VCC VCC VCC DQ42 GND DM6 GND DQ53 D B GND VCC DQ68 GND DQ60 DQ71 GND DQ56 DQ35 GND VCC C VCC DQ59 DQ70 DQ64 DQ62 DQ58 DQ67 DM8 DQ37 DQ32 DQ38 D DQ63 GND DQS8# GND DQ57 VCC VCC VCC GND VCC GND E DQ61 DQ66 DQS8 DQ13 DQ15 GND VCC VCC GND DQ31 DQ28 DQ30 DQ49 DQ44 E F DQ11 DQ9 DQ12 DQS1# DQS1 GND VCC VCC GND DQ29 DQ24 DQS3 DQS3# DQ26 F G DM1 GND DQ14 GND DQ10 VCC VCC VCC VCC DQ27 GND DQ25 GND DM2 G H DQ0 DQ2 DQS0 DQ8 DM0 VCC VCC VCC VCC DQS2 DQ16 DM3 DQ17 DQ19 H J DQ6 DQ4 DQS0# DQ1 DQ3 GND GND GND GND DQS2# DQ22 DQ18 DQ23 DQ21 J GND DQ7 GND DQ5 GND GND GND GND NC GND DQ20 VCC K VCC GND K L VCC VCC VREFDQ ODT VCC VCC VCC VCC VCC GND NC NC VCC VCC L M CK GND CAS# WE# VCC VCC VCC VCC VCC GND VCC GND GND GND M N CK# GND A10 BA2 GND GND GND GND GND VCC VCC VCC GND GND N P VCC VCC BA1 A0 GND GND GND GND GND VCC VCC VCC GND GND P R A4 A2 A6 VTT VCC VCC VCC VCC GND GND VCC GND GND VCC VCC VCC GND GND GND VCC VCC R T VCC VTT VTT A9 VCC VCC VCC NC A5 A12 CS# RAS# GND VCC VCC VCC GND GND GND GND VCC T U GND VCC VTT A8 GND GND GND DNU* A11 A3 DNU* CKE VCC GND GND GND VCC VCC VCC VCC GND U V GND GND VCC A13 GND GND GND RST# A7 A1 BA0 VREFCA VCC GND GND GND VCC VCC VCC GND GND V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 * Ball U8 is reserved for address A14 and ball U11 for A15 on future upgrades. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 4 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 1 - BALL DESCRIPTIONS Symbol Type Description ODT Input On-Die termination: ODT (registered HIGH) enables and (registered LOW) disables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each of the following balls: DQ[15:0], DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQS and DQS#) is referenced to the crossings of CK and CK#. CKE Input Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle),or active power-down (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# is considered part of the command code. CS# is referenced to VREFCA RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered and are referenced to VREFCA DM0-8 Input Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. BA0-BA2 Input Bank address inputs: BA0-BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA0-BA2 define which mode register including (MR, MR0, MR1, MR2, MR3) is loaded during the LOAD MODE command. BA0-2 are referenced to VREFCA RST# Input Reset = RST# or RESET# is an active low CMOS input referenced to VSS. The RST# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH 0.8 x VCCQ and DC LOW 0.2 x VCCQ. RST# assertion and desertion are asynchronous A0-A13 Input Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). DQ0-71 I/O Data input/output: Bidirectional data bus. DQs are referenced to VREFDQ. DQS0-8, DQS0-8# I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. VCC Supply Single Power Supply - VCC and VCCQ are internally tied together VTT Supply Termination supply VREFCA Supply Reference voltage for control, command, and address. VREFCA must be maintained at all times (including self refresh) for proper device operation. VREFDQ Supply Reference voltage for data. VREFDQ must be maintained at all times (including self refresh) for proper device operation. GND Supply Ground. NC - No connect: These balls should be left unconnected. DNU - Future use; Row address bits A14 and A15 are reserved for future densities. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 5 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX DESCRIPTION GENERAL NOTES The 8Gb DDR3 SDRAM is a high-speed CMOS, dynamic randomaccess memory containing five 2Gb, (2,147,483,648) bit chips. Each of the five chips in the MCP are internally configured as 8-bank DRAM. The block diagram of the device is shown in Figure 2. Ball assignments and are shown in Figure 3. * The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. (normal operation) * Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. The terms "DQS" and "CK" found throughout the data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. * Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. * Any specific requirement takes precedence over a general statement. * Any functionality not specifically stated here within is considered illegal, and not supported and can result in unknown operations. The 8Gb DDR3 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is a 8n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the 8Gb DDR3 SDRAM consists of a single 8n-bitwide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls. A differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is center-aligned with data for writes. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The 8Gb DDR3 SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered in the first rising edge of "DQS" after the "WRITE" preamble, and output data is referenced on the first rising edge of "DQS" after the "READ" preamble. Read and write accesses to the DDR3 SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. DDR3 SDRAM use "READ" and "WRITE" BL8 and "BC4" An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR3 SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving powerdown mode. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 6 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX INITIALIZATION 5. After this CKE LOW time, CKE may be brought HIGH (synchronously) and only NOP or DES commands may be issued. The clock must be present and valid for at least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least tIS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be continuously registered HIGH until the full initialization process is complete. 6. After CKE is registered HIGH and after tXPR has been satisfied, MRS commands may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable settings (provide LOW to BA2 and BA0 and HIGH to BA1). Condition A: 7. Issue an MRS command to MR3 with the applicable settings. * VCC and VCCQ are driven from a single-power converter output and are ramped with a maximum delta voltage between them of V 300mV. Slope reversal of any power supply signal is allowed. The voltage levels on all balls other than VCC, VCCQ, VSS, VSSQ must be less than or equal to VCCQ and VCC on one side, and must be greater than or equal to VSSQ and VSS on the other side. 8. Issue an MRS command to MR1 with the applicable settings, including enabling the DLL and configuring ODT. 9. Issue an MRS command to MR0 with the applicable settings, including a DLL RESET command. tDLLK (512) cycles of clock input are required to lock the DLL. DDR3 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. The following sequence is required for power up and initialization and is shown in Figure 4. 1. Applying power; RST# is recommended to be below 0.2 x VCCQ during power ramp to ensure the outputs remain disabled. (HIGH-Z) and ODT off (RTT is also HIGH-Z). All other inputs, including ODT, may be undefined. During power up, either of the following conditions may exist and must be met: 10. Issue a ZQCL command to calibrate RTT and RON values for the process voltage temperature (PVT). Prior to normal operation, tZQINIT must be satisfied. * Both VCC and VCCQ power supplies ramp to VCC (MIN) and VCCQC (MIN) within tVDDPR = 200ms. 11. When tDLLK and tZQINIT have been satisfied, the DDR3 SDRAM will be ready for normal operation. * VREFDQ tracks VCC x 0.5, VREFCA tracks VCC x 0.5. * VTT is limited to 0.95V when the power ramp is complete and is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latchup. Condition B: * Vcc may be applied before or at the same time as VCCQ. * VCCQ may be applied before or at the same time as VTT, VREFDQ, and VREFCA. * No slope reversals are allowed in the power supply ramp for this condition. 2. Until stable power, maintain RST# LOW to ensure the outputs remain disabled (High-Z). After the power is stable, RST# must be LOW for at least 200s to begin the initialization process. ODT will remain in the High-Z state while RST# is LOW and until CKE is registered HIGH. 3. CKE must be LOW 10ns prior to RST# transitioning HIGH. 4. After RST# transitions HIGH, wait 500s (minus one clock) with CKE LOW. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 7 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 4 - POWER-UP AND INITIALIZATION Notes appear on page 7 T (MAX) = 200ms VCC See power-up con ditions in the initialization sequence text, set up 1 VTT VREF Power-up ramp t VTD Sta ble an d vali d clo ck T0 T1 t CK Tc0 Tb0 Ta0 Td0 CK# CK t CKSRX t CL t CL t IOz = 20ns RESET# t IS T (MIN) = 10ns CKE Vali d ODT Vali d t IS Command NOP MRS MRS MRS MRS ZQCL Address Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Vali d DM BA[2:0] Vali d Vali d A10 = H Vali d DQS DQ RTT T = 200s (MIN) T = 500s (MIN) MR2 All voltage supplies valid and stable t MRD t MRD t XPR MR3 t MRD MR1 with DLL enable t MOD MR0 with DLL reset t ZQINIT ZQ cali bration t DLLK DRAM ready for external commands Normal operation Indicates A Break in Time Scale Don't Care Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 8 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 5 - WRITE COMMAND CK# CK CKE HIGH CS# RAS# CAS# WE# CA ADDRESS EN AP A10 DIS AP BANK ADDRESS BA DON' T CARE Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge. TABLE 3 - WRITE USING CONCURRENT AUTO PRECHARGE From Command (Bank n) WRITE with Auto Precharge To Command (Bank m) Minimum Delay (With Concurrent Auto Precharge) Units READ OR READ w/AP (CL-1) + (BL/2) + tWTR tCK WRITE or WRITE w/AP (BL/2) tCK PRECHARGE or ACTIVE 1 tCK Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 9 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 4. DDR3 only supports 4-bit burst chop and 8-bit burst access modes. Full interleave address ordering is supported for READs, while WRITEs are restricted to nibble (BC4) or word (BL8) boundaries. MODE REGISTERS Mode registers (MR0-MR3) are used to define various modes of programmable operations of the DDR3 SDRAM. A mode register is programmed via the MODE REGISTER SET (MRS) command during initialization, and it retains the stored information (except for MR0[8] which is self-clearing) until it is either reprogrammed, RESET# goes LOW, or until the device loses power. Contents of a mode register can be altered by re-executing the MRS command. If the user chooses to modify only a subset of the mode register's variables, all variables must be programmed when the MRS command is issued. Reprogramming the mode register will not alter the contents of the memory array, provided it is performed correctly. The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). After an MRS command has been issued, two parameters must be satisfied: tMRD and tMOD. The controller must wait tMRD before initiating any subsequent MRS commands The controller must also wait tMOD before initiating any non MRS commands (excluding NOP and DES). The DRAM requires tMOD in order to update the requested features, with the exception of DLL RESET, which requires additional time. Until tMOD has been satisfied, the updated features are to be assumed unavailable. DLL RESET DLL RESET is defined by MR0[8] (see Figure 6). Programming MR0[8] to "1" activates the DLL RESET function. MR0[8] is selfclearing, meaning it returns to a value of "0" after the DLL RESET function has been initiated. Anytime the DLL RESET function is initiated, CKE must be HIGH and the clock held stable for 512 (tDLLK) clock cycles before a READ command can be issued. This is to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in invalid output timing specifications, such as tDQSCK timings. WRITE RECOVERY WRITE recovery time is defined by MR0[11:9] (see Figure 6). Write recovery values of 5, 6, 7, 8, 10, or 12 may be used by programming MR0[11:9]. The user is required to program the correct value of write recovery and is calculated by dividing tWR (ns) by tCK (ns) and rounding up a non integer value to the next integer: WR (cycles) = roundup (tWR [ns]/tCK [ns]). MODE REGISTER 0 (MR0) The base register, MR0, is used to define various DDR3 SDRAM modes of operations. These definitions include the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and precharge power-down mode. PRECHARGE POWER-DOWN (PRECHARGE PD) The precharge PD bit applies only when precharge power-down mode is being used. When MR0[12] is set to "0," the DLL is off during precharge power-down providing a lower standby current mode; however, tXPDLL must be satisfied when exiting. When MR0[12] is set to "1," the DLL continues to run during precharge power-down mode to enable a faster exit of precharge power-down mode; however, tXP must be satisfied when exiting. BURST LENGTH Burst length is defined by MR0[1: 0]. (see figure 9) Read and write accesses to the DDR3 SDRAM are burst-oriented, with the burst length being programmable to "4" (chop mode), "8" (fixed), or selectable using A12 during a READ/WRITE command (on-the-fly). The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. When MR0[1:0] is set to "01" during a READ/ WRITE command, if A12 = 0, then BC4 (chop) mode is selected. If A12 = 1, then BL8 mode is selected. Specific timing diagrams, and turnaround between READ/WRITE, are shown in the READ/ WRITE sections of this document. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A[i:2] when the burst length is set to "4" and by A[i:3] when the burst length is set to "8" (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. CAS LATENCY (CL) The CAS latency (CL) is defined by MR0[6:4], as shown in Figure 6. CL is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM does not support any half-clock latencies. MODE REGISTER 1 (MR1) The mode register 1 (MR1) controls additional functions and features not available in the other mode registers: Q OFF (OUTPUT DISABLE), TDQS (for the x8 configuration only, DLL ENABLE/DLL DISABLE, RTT_NOM value (ODT), WRITE LEVELING, POSTED CAS ADDITIVE latency, and OUTPUT DRIVE STRENGTH. These functions are controlled via the bits shown in Figure 8. The MR1 register is programmed via the MRS command and retains the stored informations until it is reprogrammed, until RESET# goes LOW, or until the device loses power. Reprogramming the MR1 register will not alter the contents of the memory array, provided it is performed correctly. BURST TYPE Accesses within a given burst may be programmed to either a sequential or an interleaved order. The burst type is selected via MR0[3], as shown in Figure 6. The ordering of accesses within The MR1 register must be loaded when all banks are idle and no Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 10 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 6 - MODE REGISTER 0 (MR0) DEFINITIONS M16 M15 BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 17 16 15 14 13 12 11 10 01 0 0 01 01 PD WR Mode register 0 (MR0) 9 8 7 6 5 4 3 2 DLL 01 CAS# latency BT 01 1 0 BL M1 M0 Mode Register 0 0 Mode register 0 (MR0) 0 1 Mode register 1 (MR1) M12 Precharge PD 1 0 Mode register 2 (MR2) 0 DLL off (slow exit) 0 1 1 Mode register 3 (MR3) 1 DLL on (fast exit) 1 M11 M10 M9 Fixed BL8 0 0 1 No 1 0 Fixed BC4 (chop) Yes 1 1 Reserved M8 DLL Reset M6 M5 M4 Write Recovery Burst Length 0 4 or 8 (on-the-fly via A12) CAS Latency M3 READ Burst Type 0 0 0 Reserved 0 0 0 Reserved 0 Sequential (nibble) 0 0 1 5 0 0 1 5 1 Interleaved 0 1 0 6 0 1 0 6 0 1 1 7 0 1 1 7 1 0 0 8 1 0 0 8 1 0 1 10 1 0 1 9 1 1 0 12 1 1 0 10 1 1 1 Reserved 1 1 1 11 Note: 1.MR0[17, 14, 13, 7, 2] are reserved for future use and must be programmed to 0.. TABLE 4 - BURST ORDER Burst Length READ/ WRITE READ 4 CHOP WRITE 8 READ WRITE Burst Starting Column Address Type = Sequential Type = Interleaved Notes 0 0 0 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, Z, Z, Z, Z 1, 2 0 0 1 1, 2, 3, 0, Z, Z, Z, Z 1, 0, 3, 2, Z, Z, Z, Z 1, 2 0 1 0 2, 3, 0, 1, Z, Z, Z, Z 2, 3, 0, 1, Z, Z, Z, Z 1, 2 0 1 1 3, 0, 1, 2, Z, Z, Z, Z 3, 2, 1, 0, Z, Z, Z, Z 1, 2 1 0 0 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, Z, Z, Z, Z 1, 2 1 0 1 5, 6, 7, 4, Z, Z, Z, Z 5, 4, 7, 6, Z, Z, Z, Z 1, 2 1 1 0 6, 7, 4, 5, Z, Z, Z, Z 6, 7, 4, 5, Z, Z, Z, Z 1, 2 1 1 1 7, 4, 5, 6, Z, Z, Z, Z 7, 6, 5, 4, Z, Z, Z, Z 1, 2 0 V V 0, 1, 2, 3, Z, Z, Z, Z 0, 1, 2, 3, X, X, X, X 1, 3, 4 1 V V 4, 5, 6, 7, Z, Z, Z, Z 4, 5, 6, 7, X, X, X, X 1, 3, 4 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1 0 0 1 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 1 0 1 0 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 1 0 1 1 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 1 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 1 0 1 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 1 1 1 0 5, 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 1 1 1 1 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 1 V V V 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 1, 3 NOTES: 1. Internal read and write operations start at the same point in time for BC4 as they do for BL8 2. Z = Data strobe output drives are in tri-state 3. V = A valid logic level (0 or 1), but the respective input buffer ignores level-on input pins 4. X = "Don't care". Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 11 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX bursts are in progress. The controller must satisfy the specified timing parameters. tMRD and tMOD before initiating a subsequent operation DQS#) are tri-stated. The output disable feature is intended to be used during ICC characterization of the READ current and during tDQSS margining (write leveling) only. DLL ENABLE/DLL DISABLE ON-DIE TERMINATION (ODT) The DLL may be enabled or disabled by programming MR1[0] during the LOAD MODE command, as shown in Figure 11. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL should always be followed by resetting the DLL using the appropriate LOAD MODE command. ODT resistance RTT_NOM is defined by MR1[9, 6, 2] (see Figure 8). The RTT termination value applies to the DQ, DM, DQS, DQS#, and TDQS, TDQS# balls. DDR3 supports multiple RTT termination values based on RZQ/n where n can be 2, 4, 6, 8, or 12 and RZQ is 240. Unlike DDR2, DDR3 ODT must be turned off prior to reading data out and must remain off during a READ burst. RTT_NOM termination is allowed any time after the DRAM is initialized, calibrated, and not performing read access, or when it is not in self refresh mode. Additionally, write accesses with dynamic ODT enabled (RTT_WR) temporarily replaces RTT_NOM with RTT_WR. If the DLL is enabled prior to entering self refresh mode, the DLL is automatically disabled when entering SELF REFRESH operation an is automatically reenabled and reset upon exit of SELF REFRESH operation. IF the DLL is disabled prior to entering self refresh mode, the DLL remains disabled even upon exit of SELF REFRESH operation until it is reenabled and reset. The actual effective termination, RTT_EFF, may be different from the RTT targeted due to nonlinearity of the termination. The ODT feature is designed to improve signal integrity of the memory channel by enabling the DDR3 SDRAM controller to independently turn on/off ODT for any or all devices. The ODT input control pin is used to determine when RTT is turned on (ODTL on) and off (ODTL off), assuming ODT has been enabled via MR1[9, 6, 2]. The DRAM is not tested to check-nor does WEDC warrant compliance with normal mode timings or functionality when the DLL is disabled. An attempt has been made to have the DRAM operate in the normal mode where reasonably possible when the DLL has been disabled; however, by industry standard, a few known exceptions are defined: 1. ODT is not allowed to be used. WRITE LEVELING 2. The output data is no longer edge-aligned to the clock. The WRITE LEVELING function is enabled by MR1[7], as shown in Figure 8. Write leveling is used (during initialization) to deskew the DQS strobe to clock offset as a result of fly-by topology designs. For better signal integrity, DDR3 SDRAM memory adopted fly-by topology for the commands, addresses, control signals, and clocks. 3. CL and CWL can only be six clocks. When the DLL is disabled, timing and functionality can vary from the normal operation specifications when the DLL is enabled (see "DLL Disable Mode"). Disabling the DLL also implies the need to change the clock frequency. The fly-by topology benefits from a reduced number of stubs and their lengths. However, fly-by topology induces flight time skews between the clock and DQS strobe (and DQ) at each DRAM. Controllers will have a difficult time maintaining tDQSS, tDSS, and tDSH specifications without supporting write leveling in systems which use fly-by topology-based designs. OUTPUT DRIVE STRENGTH The DDR3 SDRAM uses a programmable impedance output buffer. The drive strength mode register setting is defined by MR1[5, 1]. RZQ/7 (34 [NOM]) is the primary output driver impedance setting for DDR3 SDRAM devices. To calibrate the output driver impedance, an external precision resistor (RZQ) is connected between the ZQ ball and VSSQ. The value of the resistor must be 240 1 percent. The output impedance is set during initialization. Additional impedance calibration updates do not affect device operation, and all data sheet timings and current specifications are met during an update. POSTED CAS ADDITIVE LATENCY (AL) Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR3 SDRAM. MR1 [4, 3] define the value of AL, as shown in Figure 8. MR1 [4, 3] enable the user to program the DDR3 SDRAM with an Al = 0, CL-1 or CL -2. With this feature, the DDR3 SDRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank prior to tRCD (MIN). The only restriction is ACTIVATE to READ or WRITE + AL tRCD (MIN) must be satisfied. Assuming tRCD (MIN) = CL, a typical application using this feature sets AL = CL - 1tCK = tRCD (MIN) - 1 tCK. The READ or WRITE command is held for the time of the AL before it is released internally to the DDR3 SDRAM device. READ latency (RL) is controlled by the sum of the AL and CAS latency (CL), RL = AL + CL. WRITE latency (WL) is the sum of CAS WRITE latency and AL, WL = AL + CWL. To meet the 34 specification, the output drive strength must be set to 34 during initialization. To obtain a calibrated output driver impedance after power-up, the DDR3 SDRAM needs a calibration command that is part of the initialization and reset procedure OUTPUT ENABLE/DISABLE The OUTPUT ENABLE function is defined by MR1[12], as shown in Figure 8. When enabled (MR1[12] = 0), all outputs (DQ, DQS, DQS#) function when in the normal mode of operation. When disabled (MR1[12] = 1), all DDR3 SDRAM outputs (DQ and DQS, Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 12 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 7 - READ LATENCY T0 T1 T2 T3 T4 T5 READ NOP NOP NOP NOP NOP T6 T7 T8 NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ T0 T1 T2 T3 T4 T5 READ NOP NOP NOP NOP NOP DI n+1 DI n+2 DI n+3 DI n+4 T6 T7 T8 NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Don't Care NOTES: 1. For illustration purposes, only CL = 6 and CL = 8 are shown. Other CL values are possible. 2. Shown with nominal tDQSCK and nominal tDSDQ. MODE REGISTER 2 (MR2) AUTO SELF REFRESH (ASR) The mode register 2 (MR2) controls additional functions and features not available in the other mode registers. These additional functions are CAS WRITE latency (CWL), AUTO SELF REFRESH (ASR), SELF REFRESH TEMPERATURE (SRT), and DYNAMIC ODT (RTT_WR). These functions are controlled via the bits shown in Figure 10. The MR2 is programmed via the MRS command and will retain the stored information until it is programmed again or until the device loses power. Reprogramming the MR2 register will not alter the contents of the memory array, provided it is performed correctly. The MR2 register must be loaded when all banks are idle and not data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. Mode register MR2[6] is used to disable/enable the ASR function. CAS WRITE LATENCY (CWL) SELF REFRESH TEMPERATURE (SRT) CWL is defined by MR2[5:3] and is the delay, in clock cycles, from the releasing of the internal write to the latching of the first data in. CWL must be correctly set to the corresponding operating clock frequency (see Figure 10). The overall WRITE latency (WL) is equal to CWL + AL (Figure 11) Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode's refresh rate is assumed to be at the normal 85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, SRT requires the user to ensure the DRAM never exceeds a TC of 85C while in self refresh mode unless the user enables ASR. When ASR is disabled, the self refresh mode's refresh rate is assumed to be at the normal 85C limit (sometimes referred to as 1X refresh rate). In the disabled mode, ASR requires the user to ensure the DRAM never exceeds a TC of 85C while in self refresh unless the user enables the SRT feature listed below when the TC is between 85C and 95C. Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to 2X when the case temperature exceeds 85C. This enables the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of 95C while in self refresh mode. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 13 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX support data integrity when it switches from a 1X to a 2X refresh rate, it may switch at a lower temperature than 85C. Since only one mode is necessary, SRT and ASR cannot be enabled at the same time. When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regardless of the case temperature. This enables the user to operate the DRAM beyond the standard 85C limit up to the optional extended temperature range of 95C while in self refresh mode. The standard self refresh current test specifies test conditions to normal case temperature (85C) only, meaning if SRT is enabled, the standard self refresh current specifications do not apply. DYNAMIC ODT The dynamic ODT (RTT_WR) feature is defined by MR2[10, 9]. Dynamic ODT is enabled when a value is selected. This new DDR3 SDRAM feature enables the ODT termination value to change without issuing an MRS command, essentially changing the ODT termination "on-the-fly." SRT VS. ASR If the normal case temperature limit of 85C is not exceeded, then neither SRT nor ASR is required, and both can be disabled throughout operation. However, if the extended temperature option of 95C is needed, the user is required to provide a 2X refresh rate during (manual) refresh and to enable either the SRT or the ASR to ensure self refresh is performed at the 2X rate. With dynamic ODT (RTT_WR) enabled, the DRAM switches from normal ODT (RTT_NOM) to dynamic ODT (RTT_WR) when beginning a WRITE burst and subsequently switches back to ODT (RTT_NOM) at the completion of the WRITE burst. If RTT_NOM is disabled, the RTT_NOM value will be High-Z. Special timing parameters must be adhered to when dynamic ODT (RTT_WR) is enabled: ODTLCNW, ODTLCNW4, ODTLCNW8, ODTH4, ODTH8, and tADC. SRT forces the DRAM to switch the internal self refresh rate from 1X to 2X. Self refresh is performed at the 2X refresh rate regardless of the case temperature. ASR automatically switches the DRAM's internal self refresh rate from 1X to 2X. However, while in self refresh mode, ASR enables the refresh rate to automatically adjust between 1X to 2X over the supported temperature range. One other disadvantage with ASR is the DRAM cannot always switch from a 1X to a 2X refresh rate at an exact case temperature of 85C. Although the DRAM will Dynamic ODT is only applicable during WRITE cycles. If ODT (RTT_NOM) is disabled, dynamic ODT (RTT_WR) is still permitted. RTT_NOM and RTT_WR can be used independent of one other. Dynamic ODT is not available during write leveling mode, regardless of the state of ODT (RTT_NOM). FIGURE 8 - MODE REGISTER 1 (MR1) DEFINITION BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 1 M16 M15 11 10 9 8 7 6 5 1 1 1 0 Q Off TDQS 0 RTT 0 WL RTT ODS 4 15 14 13 12 17 16 0 1 0 1 0 3 AL 2 1 0 RTT ODS DLL Mode register 1 (MR1) Mode Register 0 0 Mode register set 0 (MR0) M12 Q Off M11 TDQS 0 1 Mode register set 1 (MR1) 0 Enabled 0 Disabled 1 0 Mode register set 2 (MR2) 1 Disabled 1 Enabled 1 1 Mode register set 3 (MR3) RTT,nom (ODT)3 M9 M6 M2 M0 DLL Enable 0 Enable (normal) 1 Disable M5 M1 Output Drive Strength RTT,nom (ODT)3 Non-Writes Writes 0 1 0 0 0 RTT,nom disabled RTT,nom disabled 0 0 1 RZQ/4 (60 [NOM]) RZQ/4 (60 [NOM]) 0 1 0 RZQ/2 (120 [NOM]) RZQ/2 (120 [NOM]) 0 1 1 RZQ/6 (40 [NOM]) RZQ/6 (40 [NOM]) 1 0 0 RZQ/12 (20 [NOM]) 1 0 1 RZQ/8 (30 [NOM]) M7 Write Levelization Disable (normal) Enable 0 0 RZQ/6 (40 [NOM]) 0 1 RZQ/7 (34 [NOM]) 1 0 Reserved 1 1 Reserved M4 M3 Additive Latency (AL) n/a 0 0 Disabled (AL = 0) n/a 0 1 AL = CL - 1 1 1 0 Reserved Reserved 1 0 AL = CL - 2 1 1 1 Reserved Reserved 1 1 Reserved NOTES: 1.MR1[17, 14, 13, 10, 8] are reserved for future use and must be programmed to 0. 2.During write leveling, if MR1[7] and MR1[12] are 1, then all RTT,nom values are available for use. 3.During write leveling, if MR1[7] is a 1, but MR1[12] is a 0, then only RTT,nom write values are available for use. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 14 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX MODE REGISTER 3 (MR3) * A2 = 0; burst order = 0, 1, 2, 3 The mode register 3 (MR3) controls additional functions and features not available in the other mode registers. Currently defined is the MULTIPURPOSE REGISTER (MPR). This function is controlled via the bits shown in Figure 12. The MR3 is programmed via the LOAD MODE command and retains the stored information until it is programmed again or until the device loses power. Reprogramming the MR3 register will not alter the contents of the memory array, provided it is performed correctly. The MR3 register must be loaded when all banks are idle and no data bursts are in progress, and the controller must wait the specified time tMRD and tMOD before initiating a subsequent operation. * A2 = 1; burst order = 4, 5, 6, 7 Burst order bit 0 (the first bit) is assigned to LSB, and burst order bit 7 (the last bit) is assigned to MSB A[9:3] are a "Don't Care" A10 is a "Don't Care" A11 is a "Don't Care" A12: Selects burst chop mode on-the-fly, if enabled within MR0 A13 is a "Don't Care" BA[2:0] are a "Don't Care" MULTIPURPOSE REGISTER (MPR) MPR REGISTER ADDRESS DEFINITIONS AND BURSTING ORDER The MULTIPURPOSE REGISTER function is used to output a predefined system timing calibration bit sequence. Bit 2 is the master bit that enables or disables access to the MPR register, and bits 1 and 0 determine which mode the MPR is placed in. The basic concept of the multipurpose register is shown in Figure 13. The MPR currently supports a single data format. This data format is a predefined read pattern for system calibration. The predefined pattern is always a repeating 0-1 bit pattern. If MR3[2] is a "0," then the MPR access is disabled, and the DRAM operates in normal mode. However, if MR3[2] is a "1," then the DRAM no longer outputs normal read data but outputs MPR data as defined by MR3[0, 1]. If MR3[0, 1] is equal to "00," then a predefined read pattern for system calibration is selected. DESELECT (DES) The DES command (CS# HIGH) prevents new commands from being executed by the DRAM. Operations already in progress are not affected. To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1 (see Table 5). Prior to issuing the MRS command, all banks must be in the idle state (all banks are precharged, and tRP is met). When the MPR is enabled, any subsequent READ or RDAP commands are redirected to the multipurpose register. The resulting operation when either a READ or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see Table 6). When the MPR is enabled, only READ or RDAP commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0). Power-down mode, self refresh, and any other nonREAD/RDAP command is not allowed during MPR enable mode. The RESET function is supported during MPR enable mode. NO OPERATION (NOP) The NOP command (CS# LOW) prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. ZQ CALIBRATION ZQ CALIBRATION LONG (ZQCL) The ZQCL command is used to perform the initial calibration during a power-up initialization and reset sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM. After calibration is achieved, the calibrated values are transferred from the calibration engine to the DRAM I/O, which are reflected as updated RON and ODT values. MPR FUNCTIONAL DESCRIPTION The MPR is a 1-bit-wide logical interface via all DQ balls during a READ command. DQ0 on a x4 and a x8 is the prime DQ and outputs the MPR data while the remaining DQ are driven LOW. Similarly, for the x16, DQ0 (lower byte) and DQ8 (upper byte) are the prime DQ and output the MPR data while the remaining DQ drive LOW. The MPR readout supports fixed READ burst and READ burst chop (MRS and OTF via A12/BC#) with regular READ latencies and AC timings applicable, provided the DLL is locked as required. The DRAM is allowed a timing window defined by either tZQINIT or tZQOPER to perform the full calibration and transfer of values. When ZQCL is issued during the initialization sequence, the timing parameter tZQINIT must be satisfied. When initialization is complete, subsequent ZQCL commands require the timing parameter tZQOPER to be satisfied. ZQ CALIBRATION SHORT (ZQCS) MPR addressing for a valid MPR read is as follows: The ZQCS command is used to perform periodic calibrations to account for small voltage and temperature variations. The shorter timing window is provided to perform the reduced calibration and transfer of values as defined by timing parameter tZQCS. A ZQCS command can effectively correct a minimum of 0.5 percent RON and RTT impedance error within 64 clock cycles, assuming the maximum sensitivities. A[1:0] must be set to "00" as the burst order is fixed per nibble A2 selects the burst order: * BL8, A2 is set to "0," and the burst order is fixed to 0, 1, 2, 3, 4, 5, 6, 7 For burst chop 4 cases, the burst order is switched on the nibble base and: Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 15 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 9 - READ LATENCY (AL = 5, CL = 6) BC4 T0 T1 ACTIVEn READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates A Break in Time Scale Transitioning Data Don't Care the corresponding data inputs will be ignored and a WRITE will not be executed to that byte/column location. ACTIVATE The ACTIVATE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA[2:0] inputs selects the bank, and the address provided on inputs A[n:0] selects the row. This row remains open (or active) for accesses until a PRECHARGE command is issued to that bank. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or in all banks. The bank(s) are available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued, except in the case of concurrent auto precharge. A READ or WRITE command to a different bank is allowed during concurrent auto precharge as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are precharged. In the case where only one bank is precharged, inputs BA[2:0] select the bank; otherwise, BA[2:0] are treated as "Don't Care." After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is treated as a NOP if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period is determined by the last PRECHARGE command issued to the bank. A PRECHARGE command must be issued before opening a different row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The address provided on inputs A[2:0] selects the starting column address depending on the burst length and burst type selected. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. If auto precharge is not selected, the row will remain open for subsequent accesses. The value on input A12 (if enabled in the mode register) when the READ command is issued determines whether BC4 (chop) or BL8 is used. After a READ command is issued, the READ burst may not be interrupted. A summary of READ commands is shown in Table 9. REFRESH REFRESH is used during normal operation of the DRAM and is analogous to CAS#- before-RAS# (CBR) refresh or auto refresh. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during a REFRESH command. The DRAM requires REFRESH cycles at an average interval of 7.8s (maximum when TC 85C or 3.9s MAX when TC 95C). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight REFRESH commands can be posted to any given DRAM, meaning that the maximum absolute interval between any REFRESH command and the next REFRESH command is nine times the WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA[2:0] inputs selects the bank. The value on input A10 determines whether or not auto precharge is used. The value on input A12 (if enabled in the MR) when the WRITE command is issued determines whether BC4 (chop) or BL8 is used. The WRITE command summary is shown in Table 10. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 16 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 10 - MODE REGISTER 2 (MR2) DEFINITION BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 17 16 15 14 13 12 11 10 9 8 7 6 1 0 01 01 01 01 RTT(WR) 01 SRT ASR 5 4 CWL 01 M16 M15 Mode Register M7 Self Refresh Temperature 3 2 1 0 Address bus Mode register 2 (MR2) 01 0 1 01 M5 M4 M3 CAS Write Latency (CWL) 0 0 Mode register set 0 (MR0) 0 Normal (0C to 85C) 0 0 0 5 CK (tCK 2.5ns) 0 1 Mode register set 1 (MR1) 1 Extended (0C to 95C) 0 0 1 6 CK (2.5ns > tCK 1.875ns) 1 0 Mode register set 2 (MR2) 0 1 0 7 CK (1.875ns > tCK 1.5ns) 1 1 Mode register set 3 (MR3) 0 1 1 8 CK (1.5ns > tCK 1.25ns) 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M10 M9 0 0 Dynamic ODT (RTT(WR)) RTT(WR) disabled M6 0 Auto Self Refresh (Optional) Disabled: Manual 1 Enabled: Automatic 0 1 1 0 RZQ/2 1 1 Reserved RZQ/4 Note: 1. MR2[17, 14:11, 8, and 2:0] are reserved for future use and must all be programmed to 0. FIGURE 11 - CAS WRITE LATENCY BC4 T0 T1 ACTIVEn WRITEn T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don't Care Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 17 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX maximum average interval refresh rate. The REFRESH period begins when the REFRESH command is registered and ends tRFC (MIN) later. 5. The DRAM will be ready for its next command in the DLL disable mode after the greater of tMRD or tMOD has been satisfied. A ZQCL command should be issued with appropriate timings met as well. SELF REFRESH A similar procedure is required for switching from the DLL disable mode back to the DLL enable mode. This also requires changing the frequency during self refresh mode. The SELF REFRESH command is used to retain data in the DRAM, even if the rest of the system is powered down. When in the self refresh mode, the DRAM retains data without external clocking. The self refresh mode is also a convenient method used to enable/ disable the DLL (see "DLL Disable Mode") as well as to change the clock frequency within the allowed synchronous operating range (see "Input Clock Frequency Change"). All power supply inputs (including VREFCA and VREFDQ) must be maintained at valid levels upon entry/exit and during SELF REFRESH operation. 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), enter self refresh mode. 2. After tCKSRE is satisfied, change the frequency to the new clock rate. 3. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with the appropriate values. At a minimum, set MR1[0] to "0" to enable the DLL. Wait tMRD, then set MR0[8] to "1" to enable DLL RESET. DLL DISABLE MODE If the DLL is disabled by the mode register (MR1[0] can be switched during initialization or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal mode with a few notable exceptions: 4. After another tMRD delay is satisfied, then update the remaining mode registers with the appropriate values. 5. The DRAM will be ready for its next command in the DLL enable mode after the greater of tMRD or tMOD has been satisfied. However, before applying any command or function requiring a locked DLL, a delay of tDLLK after DLL RESET must be satisfied. A ZQCL command should be issued with the appropriate timings met as well. The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS WRITE latency (CWL = 6). DLL disable mode affects the read data clock-to-data strobe relationship (tDQSCK), but not the read data-to-data strobe relationship (tDQSQ, tQH). Special attention is needed to line the read data up with the controller time domain when the DLL is disabled. The clock frequency range for the DLL disable mode is specified by the parameter tCKDLL_DIS. Due to latency counter and timing restrictions, only CL = 6 and CWL = 6 are supported. In normal operation (DLL on), tDQSCK starts from the rising clock edge AL + CL cycles after the READ command. In DLL disable mode, tDQSCK starts AL + CL - 1 cycles after the READ command. Additionally, with the DLL disabled, the value of tDQSCK could be larger than tCK. DLL disable mode will affect the read data clock to data strobe relationship (tDQSCK) but not the data strobe to data relationship (tDQSQ, tQH). Special attention is needed to line up read data to the controller time domain. Compared to the DLL on mode where tDQSCK starts from the rising clock edge AL + CL cycles after the READ command, the DLL disable mode tDQSCK starts AL + CL - 1 cycles after the READ command. The ODT feature is not supported during DLL disable mode (including dynamic ODT). The ODT resistors must be disabled by continuously registering the ODT ball LOW by programming RTT_NOM MR1[9, 6, 2] and RTT_WR MR2[10, 9] to "0" while in the DLL disable mode. WRITE operations function similarly between the DLL enable and DLL disable modes; however, ODT functionality is not allowed with DLL disable mode. Specific steps must be followed to switch between the DLL enable and DLL disable modes due to a gap in the allowed clock rates between the two modes (tCK [AVG]MAX and tCK [DLL disable] MIN, respectively). The only time the clock is allowed to cross this clock rate gap is during self refresh mode. Thus, the required procedure for switching from the DLL enable mode to the DLL disable mode is to change frequency during self refresh: INPUT CLOCK FREQUENCY CHANGE When the DDR3 SDRAM is initialized, it requires the clock to be stable during most normal states of operation. This means that after the clock frequency has been set to the stable state, the clock period is not allowed to deviate except what is allowed for by the clock jitter and spread spectrum clocking (SSC) specifications. 1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT is turned off, and RTT_NOM and RTT_WR are High-Z), set MR1[0] to "1" to disable the DLL. The input clock frequency can be changed from one stable clock rate to another under two conditions: self refresh mode and precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the self refresh mode condition, when the DDR3 SDRAM has been successfully placed into self refresh mode and tCKSRE has been satisfied, the state of the clock becomes a "Don't Care." When the clock becomes a "Don't Care," changing the clock frequency is permissible, provided 2. Enter self refresh mode after tMOD has been satisfied. 3. After tCKSRE is satisfied, change the frequency to the desired clock rate. 4. Self refresh may be exited when the clock is stable with the new frequency for tCKSRX. After tXS is satisfied, update the mode registers with appropriate values. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 18 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 12 - MODE REGISTER 3 (MR3) DEFINITION BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 17 01 16 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 01 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF Mode register 3 (MR3) Mode Register M2 MPR Enable 0 0 Mode register set (MR0) 0 Normal DRAM operations 2 0 0 Predefined pattern 3 0 1 Mode register set 1 (MR1) 1 Dataflow from MPR 0 1 Reserved 1 0 Mode register set 2 (MR2) 1 0 Reserved 1 1 Mode register set 3 (MR3) 1 1 Reserved M16 M15 MPR READ Function M1 M0 NOTES: 1.MR3[17 and 14:3] are reserved for future use and must all be programmed to 0. 2.When MPR control is set for normal DRAM operation, MR3[1, 0] will be ignored. 3.Intended to be used for READ synchronization. Precharge all banks the new clock frequency is stable prior to tCKSRX. When entering and exiting self refresh mode for the sole purpose of changing the clock frequency, the self refresh entry and exit specifications must still be met. After tRP is satisfied, set MRS, MR3[2] = 1 and MR3[1:0] = 00. This redirects all subsequent reads and loads the predefined pattern into the MPR. As soon as tMRD and tMOD are satisfied, the MPR is available The precharge power-down mode condition is when the DDR3 SDRAM is in precharge power-down mode (either fast exit mode or slow exit mode). Either ODT must be at a logic LOW or RTT_NOM and RTT_WR must be disabled via MR1 and MR2. This ensures RTT_NOM and RTT_WR are in an off state prior to entering precharge power-down mode, and CKE must be at a logic LOW. A minimum of tCKSRE must occur after CKE goes LOW before the clock frequency can change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade (tCK [AVG]MIN to tCK [AVG]MAX). During the input clock frequency change, CKE must be held at a stable LOW level. When the input clock frequency is changed, a stable clock must be provided to the DRAM tCKSRX before precharge power-down may be exited. After precharge power-down is exited and tXP has been satisfied, the DLL must be reset via the MRS. Depending on the new clock frequency, additional MRS commands may need to be issued. During the DLL lock time, RTT_NOM and RTT_WR must remain in an off state. After the DLL lock time, the DRAM is ready to operate with a new clock frequency. Data WRITE operations are not allowed until the MPR returns to the normal DRAM state Issue a read with burst order information (all other address pins are "Don't Care"): * A[1:0] = 00 (data burst order is fixed starting at nibble) * A2 = 0 (for BL8, burst order is fixed as 0, 1, 2, 3, 4, 5, 6, 7) * A12 = 1 (use BL8) After RL = AL + CL, the DRAM bursts out the predefined read calibration pattern (0, 1, 0, 1, 0, 1, 0, 1) The memory controller repeats the calibration reads until read data capture at memory controller is optimized After the last MPR READ burst and after tMPRR has been satisfied, issue MRS, MR3[2] = 0, and MR3[1:0] = "Don't Care" to the normal DRAM state. All subsequent read and write accesses will be regular reads and writes from/to the DRAM array When tMRD and tMOD are satisfied from the last MRS, the regular DRAM commands (such as activate a memory bank for regular read or write access) are permitted MPR READ PREDEFINED PATTERN The predetermined read calibration pattern is a fixed pattern of 0, 1, 0, 1, 0, 1, 0, 1. The following is an example of using the read out predetermined read calibration pattern. The example is to perform multiple reads from the multipurpose register in order to do system level read timing calibration based on the predetermined and standardized pattern. MODE REGISTER SET (MRS) The mode registers are loaded via inputs BA[2:0], A[13:0]. BA[2:0] determine which mode register is programmed: BA2 = 0, BA1 = 0, BA0 = 0 for MR0 The following protocol outlines the steps used to perform the read calibration: BA2 = 0, BA1 = 0, BA0 = 1 for MR1 (continued on page 20) Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 19 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 13 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM Memory core MR3[2] = 0 (MPR off) Multipurpose register predefined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQS, DQS# NOTES: 1. A predefined data pattern can be read out of the MPR with an external READ command. 2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When the data flow is defined, the MPR contents can be read out continuously with a regular READ or RDAP command. TABLE 5 - MPR FUNCTIONAL DESCRIPTION OF MR3 BITS MR3(2) MR3(1:0) MPR MPR Read Function 0 "Don't Care" Normal operation, no MPR transaction All subsequent READs come from the DRAM memory array All subsequent WRITEs go to the DRAM memory array 1 A(1:0) Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and 2 Function TABLE 6 - MPR READOUTS AND BURST ORDER BIT MAPPING MR3(2) 1 MR3(1:0) 00 Functions Read predefined pattern for system calibration Burst Length Read A[2:0] Function BL8 000 Burst order: 0 ,1, 2, 3, 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1, 0, 1, 0, 1 BC4 000 Burst order: 0 ,1, 2, 3 Predefined pattern: 0, 1, 0, 1 BC4 100 Burst order: 4, 5, 6, 7 Predefined pattern: 0, 1, 0, 1 1 01 RFU n/a n/a n/a 1 10 RFU n/a n/a n/a 1 11 RFU n/a n/a n/a Note: 1. Burst order bit 0 is assigned to LSB, and burst order bit 7 is assigned to MSB of the selected MPR agent. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 20 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX BA2 = 0, BA1 = 1, BA0 = 0 for MR2 to convert other specification limits from time units to clock cycles. BA2 = 0, BA1 = 1, BA0 = 1 for MR3 When at least one bank is open, any READ-to-READ command delay or WRITE-to-WRITE command delay is restricted to tCCD (MIN). The MRS command can only be issued (or reissued) when all banks are idle and in the precharged state (tRP is satisfied and no data bursts are in progress). The controller must wait the specified time tMRD before initiating a subsequent operation such as an ACTIVATE command. There is also a restriction after issuing an MRS command with regard to when the updated functions become available. This parameter is specified by tMOD. Violating either of these requirements (tMOD, tMRD) will result in unspecified operation. A subsequent ACTIVATE command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). The minimum time interval between successive ACTIVATE commands to the same bank is defined by tRC. A subsequent ACTIVATE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVATE commands to different banks is defined by tRRD. No more than four bank ACTIVATE commands may be issued in a given tFAW (MIN) period, and the tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies, regardless of the number of banks already opened or closed. ZQ CALIBRATION The ZQ CALIBRATION command is used to calibrate the DRAM output drivers (RON) and ODT values (RTT) over process, voltage, and temperature, provided a dedicated 240 (1 percent) external resistor is connected from the DRAM's ZQ ball to VSSQ. DDR3 SDRAM need a longer time to calibrate RON and ODT at powerup initialization and self refresh exit and a relatively shorter time to perform periodic calibrations. DDR3 SDRAM defines two ZQ CALIBRATION commands: ZQ CALIBRATION LONG (ZQCL) and ZQ CALIBRATION SHORT (ZQCS). An example of ZQ calibration timing is shown in Figure 22. READ READ bursts are initiated with a READ command. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is automatically precharged at the completion of the burst. If auto precharge is disabled, the row will be left open after the completion of the burst. All banks must be precharged and tRP must be met before ZQCL or ZQCS commands can be issued to the DRAM. No other activities (other than another ZQCL or ZQCS command may be issued to another DRAM) can be performed on the DRAM channel by the controller for the duration of tZQINIT or tZQOPER . The quiet time on the DRAM channel helps accurately calibrate RON and ODT. After DRAM calibration is achieved, the DRAM should disable the ZQ ball's current consumption path to reduce power. During READ bursts, the valid data-out element from the starting column address is available READ latency (RL) clocks later. RL is defined as the sum of POSTED CAS ADDITIVE latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is programmable in the mode register via the MRS command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (that is, at the next crossing of CK and CK#). ZQ CALIBRATION commands can be issued in parallel to DLL RESET and locking time. Upon self refresh exit, an explicit ZQCL is required if ZQ calibration is desired. In dual-rank systems that share the ZQ resistor between devices, the controller must not allow overlap of tZQINIT, tZQOPER, or tZQCS between ranks. DQS, DQS# is driven by the DRAM along with the output data. The initial low state on DQS and HIGH state on DQS# is known as the READ preamble (tRPRE). The low state on DQS and the HIGH state on DQS#, coincident with the last data-out element, is known as the READ postamble (tRPST). Upon completion of a burst, assuming no other commands have been initiated, the DQ will go High-Z. ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DRAM, a row in that bank must be opened (activated). This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. Data from any READ burst may be concatenated with data from a subsequent READ command to provide a continuous flow of data. The first data element from the new burst follows the last element of a completed burst. The new READ command should be issued tCCD cycles after the first READ command. If BC4 is enabled, tCCD must still be met which will cause a gap in the data output. DDR3 SDRAM do not allow interrupting or truncating any READ burst. After a row is opened with an ACTIVATE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. However, if the additive latency is programmed correctly, a READ or WRITE command may be issued prior to tRCD (MIN). In this operation, the DRAM enables a READ or WRITE command to be issued after the ACTIVATE command for that bank, but prior to tRCD (MIN) with the requirement that (ACTIVATE-toREAD/WRITE) + AL tRCD (MIN) (see "POSTED CAS ADDITIVE Latency (AL)"). tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVATE command on which a READ or WRITE command can be entered. The same procedure is used Data from any READ burst must be completed before a subsequent WRITE burst is allowed. To ensure the read data is completed before the write data is on the bus, the minimum READ-to-WRITE timing is RL + tCCD - WL + 2tCK. A READ burst may be followed by a PRECHARGE command to the same bank provided auto precharge is not activated. The minimum READ-to-PRECHARGE command spacing to the same bank is Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 21 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 7 - TRUTH TABLE - DDR3 COMMANDS CKE Function Symbol Previous Cycle Next Cycle CS# RAS# CAS# WE# BA2 BA1 BA0 MODE REGISTER SET MRS H H L L L L BA REFRESH REF H H L L L H V V V V V SELF-REFRESH Entry SRE H L V V V V V 6 V V V V V 6, 7 BA V V L V V V H V L L L H H V V V L H H H L L H L An A12 A11 A10 A9-A0 Notes OP Code SELF-REFRESH Exit SRX L H Single bank precharge PRE H H All banks PRECHARGE PREA H H L L H L V Bank activate ACT H H L H L L BA BL8MRS, BC4MRS WR H H L H L L BA RFU V L CA 8 BC4OTF WRS4 H H L H L L BA RFU L L CA 8 BL8OTF WRS8 H H L H L L BA RFU H L CA 8 BL8MRS, BC4MRS WRAP H H L H L L BA RFU V H CA 8 BC4OTF WRAPS4 H H L H L L BA RFU L H CA 8 BL8OTF WRAPS8 H H L H L L BA RFU H H CA 8 BL8MRS BC4MRS RD H H L H L H BA RFU V L CA 8 BC4OTF RDS4 H H L H L H BA RFU L L CA 8 WRITE WRITE with auto precharge READ Row address (RA) BL8OTF RDS8 H H L H L H BA RFU H L CA 8 BL8MRS BC4MRS RDAP H H L H L H BA RFU V H CA 8 BC4OTF RDAPS4 H H L H L H BA RFU L H CA 8 BL8OTF RDAPS8 H H L H L H BA RFU H H CA 8 NO OPERATION NOP H H L H H H V V V V V 9 Device DESELECT DES H H H X X X X X X X X 10 POWER-DOWN entry PDE H L V V V V V 6 POWER-DOWN exit PDX L H V V V V V 6, 11 ZQ CALIBRATION LONG ZQCL H 12 ZQ QALIBRATION SHORT ZQCS H READ with auto precharge L H H H H V V V L H H H H V V V H L H H L X X X H X H L H H L X X X L X NOTES: (notes 1-5 apply to the entire table) 1. Commands are defined by states of CAS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock. The MSB of BA, RA and CA are device-density and configuration-dependent. 2. RESET# is LOW enabled and used only for asynchronous reset. Thus, RESET# must be held HIGH during any normal operation. 3. The state of ODT doesn not affect the states described in this table. 4. Operations apply to the bank defined by the bank address. For MRS, BA selects one of four mode registers. 5. "V" means "H" or "L" (a defined logic level), and "X" means "Don't Care." 6. See Table 8 for additional information on CKE transition. 7. Self refresh exit is asynchronous. 8. Burst READs or WRITEs cannot be terminated or interrupted. MRS (fixed) and OTF BL/BC are defined in MR0. 9. The purpose of the NOP command is to prevent the DRAM from registering any unwanted commands. A NOP will not terminate an operation that is executing. 10. The DES and NOP commands perform similarly. 11. The power-down mode does not perform any REFRESH operations. 12. ZQ CALIBRATION LONG is used for either ZQINIT (first ZQCL command during initialization) or ZQ oper(ZQCL command after initialization) Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 22 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 8 - TRUTH TABLE - CKE 1, 2 CKE Current State3 Cycle4 Previous (n - 1) Power-down Self Refresh Bank(s) Active Previous Cycle4 (n ) Command5 Action5 L L "Don't Care" Maintain power-down L H DES or NOP Power-down exit Maintain self refresh L L "Don't Care" L H DES or NOP Self refresh exit H L DES or NOP Active power-down entry Reading H L DES or NOP Power-down entry Writing H L DES or NOP Power-down entry Precharging H L DES or NOP Power-down entry Refreshing All banks idle H L DES or NOP Precharge power-down entry H L DES or NOP Precharge power-down entry H L REFRESH Self Refresh Notes 6 NOTES: 1. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 2. tCKE (MIN) means CKE must be registered at multiple consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the required number of registration clocks. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (MIN) + tIH. 3. Current state = The state of the DRAM immediately prior to clock edge n. 4. CKE (n) is the logic state of CKE at clock edge n; CKE (n - 1) was the state of CKE at the previous clock edge. 5. COMMAND is the command registered at the clock edge (must be a legal command as defined in Table 7). Action is a result of COMMAND. ODT does not affect the states described in this table and is not listed. 6. Idle state = All banks are closed, no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied -- All self refresh exit and power-down exit parameters are also satisfied. four clocks and must also satisfy a minimum analog time from the READ command. This time is called tRTP (READ-to-PRECHARGE). tRTP starts AL cycles later than the READ command. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The PRECHARGE command followed by another PRECHARGE command to the same bank is allowed. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. WRITE operation is in progress. CKE is allowed to go LOW while any of the other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or REFRESH) are in progress. However, the power-down ICC specifications are not applicable until such operations have been completed. Depending on the previous DRAM state and the command issued prior to CKE going LOW, certain timing constraints must be satisfied. Entering power-down disables the input and output buffers, excluding CK, CK#, ODT, CKE, and RESET#. NOP or DES commands are required until tCPDED has been satisfied, at which time all specified input/output buffers will be disabled. The DLL should be in a locked state when power-down is entered for the fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting powerdown mode for proper READ operation as well as synchronous ODT operation. If A10 is HIGH when a READ command is issued, the READ with auto precharge function is engaged. The DRAM starts an auto precharge operation on the rising edge which is AL + tRTP cycles after the READ command. DRAM support a tRAS lockout feature. If tRAS (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is not satisfied at the edge, the starting point of the auto precharge operation will be delayed until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP starts at the point at which the internal precharge happens (not at the next rising clock edge after this event). The time from READ with auto precharge to the next ACTIVATE command to the same bank is AL + (tRTP + tRP)*, where "*" means rounded up to the next integer. In any event, internal precharge does not start earlier than four clocks after the last 8n-bit prefetch. During power-down entry, if any bank remains open after all inprogress commands are complete, the DRAM will be in active power-down mode. If all banks are closed after all in-progress commands are complete, the DRAM will be in precharge powerdown mode. Precharge power-down mode must be programmed to exit with either a slow exit mode or a fast exit mode. When entering precharge power-down mode, the DLL is turned off in slow exit mode or kept on in fast exit mode. POWER-DOWN MODE The DLL remains on when entering active power-down as well. ODT has special timing constraints when slow exit mode precharge power-down is enabled and entered. Power-down is synchronously entered when CKE is registered LOW coincident with a NOP or DES command. CKE is not allowed to go LOW while either an MRS, MPR, ZQCAL, READ, or Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 23 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX While in either power-down state, CKE is held LOW, RESET# is held HIGH, and a stable clock signal must be maintained. ODT must be in a valid state but all other input signals are a "Don't Care." If RESET# goes LOW during power-down, the DRAM will switch out of power-down mode and go into the reset state. After CKE is registered LOW, CKE must remain LOW until tPD (MIN) has been satisfied. The maximum time allowed for powerdown duration is tPD (MAX) (9 x tREFI). and so forth need to be selected as well. It should also be noted that when the outputs are enabled during write leveling mode, the DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write leveling mode, only the DQS strobe terminations are activated and deactivated via the ODT ball. The DQ remain disabled and are not affected by the ODT ball. The power-down states are synchronously exited when CKE is registered HIGH (with a required NOP or DES command). CKE must be maintained HIGH until tCKE has been satisfied. A valid, executable command may be applied after power-down exit latency, tXP tXPDLL have been satisfied. A memory controller initiates the DRAM write leveling mode by setting MR1[7] to a "1," assuming the other programable features (MR0, MR1, MR2, and MR3) are first set and the DLL is fully reset and locked. The DQ balls enter the write leveling mode going from a High-Z state to an undefined driving state, so the DQ bus should not be driven. During write leveling mode, only the NOP or DES commands are allowed. The memory controller should attempt to level only one rank at a time; thus, the outputs of other ranks should be disabled by setting MR1[12] to a "1" in the other ranks. The memory controller may assert ODT after a tMOD delay as the DRAM will be ready to process the ODT transition. ODT should be turned on prior to DQS being driven LOW by at least ODTL on delay (WL - 2 tCK), provided it does not violate the aforementioned tMOD delay requirement. WRITE LEVELING PROCEDURE For certain CKE-intensive operations, for example, repeating a power-down exit to refresh to power-down entry sequence, the number of clock cycles between power-down exit and powerdown entry may not be sufficient enough to keep the DLL properly updated. In addition to meeting tPD when the REFRESH command is used in between power-down exit and power-down entry, two other conditions must be met. First, tXP must be satisfied before issuing the REFRESH command. Second, tXPDLL must be satisfied before the next power-down may be entered. The memory controller may drive DQS LOW and DQS# HIGH after tWLDQSEN has been satisfied. The controller may begin to toggle DQS after tWLMRD (one DQS toggle is DQS transitioning from a LOW state to a HIGH state with DQS# transitioning from a HIGH state to a LOW state, then both transition back to their original states). At a minimum, ODTL on and tAON must be satisfied at least one clock prior to DQS toggling. WRITE LEVELING For better signal integrity, DDR3 SDRAM memory modules adopted fly-by topology for the commands, addresses, control signals, and clocks. Write leveling is a scheme for the memory controller to adjust or deskew the DQS strobe (DQS, DQS#) to CK relationship at the DRAM with a simple feedback feature provided by the DRAM. Write leveling is generally used as part of the initialization process, if required. For normal DRAM operation, this feature must be disabled. This is the only DRAM operation where the DQS functions as an input (to capture the incoming clock) and the DQ function as outputs (to report the state of the clock). Note that nonstandard ODT schemes are required. After tWLMRD and a DQS LOW preamble (tWPRE) have been satisfied, the memory controller may provide either a single DQS toggle or multiple DQS toggles to sample CK for a given DQS-to-CK skew. Each DQS toggle must not violate tDQSL (MIN) and tDQSH (MIN) specifications. tDQSL (MAX) and tDQSH (MAX) specifications are not applicable during write leveling mode. The DQS must be able to distinguish the CK's rising edge within tWLS and tWLH. The prime DQ will output the CK's status asynchronously from the associated DQS rising edge CK capture within tWLO. The remaining DQ that always drive LOW when DQS is toggling must be LOW within tWLOE after the first tWLO is satisfied (the prime DQ going LOW). As previously noted, DQS is an input and not an output during this process. The memory controller using the write leveling procedure must have adjustable delay settings on its DQS strobe to align the rising edge of DQS to the clock at the DRAM pins. This is accomplished when the DRAM asynchronously feeds back the CK status via the DQ bus and samples with the rising edge of DQS. The controller repeatedly delays the DQS strobe until a CK transition from "0" to "1" is detected. The DQS delay established through this procedure helps ensure tDQSS, tDSS, and tDSH specifications in systems that use fly-by topology by deskewing the trace length mismatch. The memory controller will likely sample each applicable prime DQ state and determine whether to increment or decrement its DQS delay setting. After the memory controller performs enough DQS toggles to detect the CK's "0-to-1" transition, the memory controller should lock the DQS delay setting for that DRAM. After locking the DQS setting, leveling for the rank will have been achieved, and the write leveling mode for the rank should be disabled or reprogrammed (if write leveling of another rank follows). When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ outputs the sampled CK's status. The prime DQ for a x16 configuration is DQ0 for the lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a x16 enable each byte lane to be leveled independently. WRITE LEVELING MODE EXIT PROCEDURE The write leveling mode register interacts with other mode registers to correctly configure the write leveling functionality. Besides using MR1[7] to disable/enable write leveling, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst length, After the DRAM are leveled, they must exit from write leveling mode before the normal mode can be used. After the last rising DQS (capturing a "1" at T0), the memory controller should stop Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 24 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX LOW satisfies tIS, ODT must be kept LOW (at ~Tb0) until the DRAM is ready for either another rank to be leveled or until the normal mode can be used. After DQS termination is switched off, write level mode should be disabled via the MRS command (at Tc2). After tMOD is satisfied (at Te1), any valid command may be registered by the DRAM. Some MRS commands may be issued after tMRD (at Td1). driving the DQS signals after tWLO (MAX) delay plus enough delay to enable the memory controller to capture the applicable prime DQ state (at ~Tb0). The DQ balls become undefined when DQS no longer remains LOW, and they remain undefined until tMOD after the MRS command (at Te1). The ODT input should be deasserted LOW such that ODTL off (MIN) expires after the DQS is no longer driving LOW. When ODT TABLE 9 - READ COMMAND SUMMARY CKE Function Symbol BL8MRS, BC4MRS RD Next Cycle H CS# RAS# CAS# WE# BA [3:0] An A12 A10 A[11, 9:0] L H L H BA RFU V L CA BC4OTF RDS4 H L H L H BA RFU L L CA BL8OTF RDS8 H L H L H BA RFU H L CA BL8MRS, BC4MRS RDAP H L H L H BA RFU V H CA BC4OTF RDAPS4 H L H L H BA RFU L H CA BL8OTF RDAPS8 H L H L H BA RFU H H CA WE# BA [3:0] An A12 A10 A[11, 9:0] Read Read with auto precharge Previous Cycle TABLE 10 - WRITE COMMAND SUMMARY CKE Function Write Write with auto precharge Symbol Previous Cycle Next Cycle CS# RAS# CAS# BL8MRS, BC4MRS WR H L H L L BA RFU V L CA BC4OTF WRS4 H L H L L BA RFU L L CA CA BL8OTF WRS8 H L H L L BA RFU H L BL8MRS, BC4MRS WRAP H L H L L BA RFU V H CA BC4OTF WRAPS4 H L H L L BA RFU L H CA BL8OTF WRAPS8 H L H L L BA RFU H H CA TABLE 11 - READ ELECTRICAL CHARACTERISTICS, DLL DISABLE MODE Parameter Symbol Min Max Units Access window of DQS from CK, CK# tDQSCK (DLL_DIS) 1 10 ns Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 25 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 14A - DC OPERATING CONDITIONS All voltages referenced to VSS Parameter Supply voltage I/O Supply voltage Input leakage current Any input 0V VIN VCC, VREF pin 0V VIN 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VCC/2 or VREFCA = VCC/2 (All other pins not under test = 0V) Symbol VCC VCCQ Min 1.425 1.425 Typical 1.5 1.5 Max 1.575 1.575 Unit V V II -10 - 10 A IVREF -5 - 5 A Notes 1, 2 1, 2 3 NOTES: 1. VCC and VCCQ must track one another. VCCQ must be less than or equal to VCC. VSS = VSSQ. 2. VCC and VCCQ may include AC noise of 50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) specifications. VCC and VCCQ must be at same level for valid AC timing parameters. 3. VREF (see table 14B) 4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. Table 14B - DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS All voltages are referenced to VSS Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) Symbol VIL VIH VREFCA(DC) VREFDQ(DC) VREFDQ(sr) Min VSS See table 15 0.49 X VCC 0.49 x VCC Vss Nom n/a n/a 0.5 X VCC 0.5 X VCC 0.5 X VCC Max See table 15 VCC 0.51 X VCC 0.51 x VCC VCC Units V V V V V Notes VTT - 0.5 x VCCQ - V 5 1, 2 2, 3 4 NOTES: 1. VREFCA(DC) is expected to be approximately 0.5 x VCC and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed 1 % x VCC around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed 2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces aCCitional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 x VCC and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed 1 % x VCC around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed 2% of VREFDQ(DC). 4. VREFDQ(DC) may transition to VREFDQ(sr) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent. TABLE 15 - ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCQ VIN, VOUT TSTG Parameter Voltage on VCC pin relative to VSS Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage temperature MIN -0.4 -0.4 -0.4 -55 MAX 1.975 1.975 1.975 125 Unit V V V C Notes 1 NOTES: 1. VCC and VCCQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 x VCCQ. When VCC and VCCQ are less than 500mV, VREF may be 300mV. 2. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 26 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 17 - BGA THERMAL RESISTANCE Description Junction to Ambient (No Airflow) Symbol Theta JA Typical TBD Units C/W Junction to Ball Junction to Case (Top) Theta JB Theta JC TBD TBD C/W C/W Notes TABLE 18 - AC INPUT OPERATING CONDITIONS Parameter Symbol Input high AC voltage: Logic 1 Command and Address VIH(AC175)min Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 VIN(AC150)min VIH(DC100)min VIL(DC100)max VIL(AC150)max Input low AC voltage: Logic 0 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 VIL(AC175)max DQ and DM VIH(AC175)min VIH(AC150)min Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 VIH(DC100)min VIL(DC100)max VIL(AC150)max VIL(AC175)max DDR3-800 DDR3-1066 DDR3-1333 Unit +175 +150 +100 -100 +175 +150 +100 -100 mV mV mV mV -150 -175 -150 -175 mV mV +175 - mV +150 +100 -100 -150 -175 +150 +100 -100 -150 - mV mV mV mV mV NOTES 1. All voltages are referenced to VREF, VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). TABLE 19 - ON=DIE TERMINATION DC ELECTRICAL CHARACTERISICS Parameter RTT effective impedance Deviation of VM with respect to VCCQ/2 Symbol RTT_EFF VMM Min Nom See Table 20 -10 Max +5 Unit % Notes 1, 2 1, 2, 3 NOTES 1. 1. Tolerance limits are applicable after proper ZQ calibration has been performed at a stable temperature and voltage (VCCQ = VCC, VSSQ = VSS). 2. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I[VIH(AC)], then apply VIL(AC) to pin under test and measure current I[VIL(AC)]: 3. Measure voltage (VM) at the tested pin with no load: RTT = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) ( ) VM = 2 x VM - 1 x 100 VCCQ Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 27 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 20 - AC INPUT OPERATING CONDITIONS MR1 [9, 6, 2] RTT Resistor VOUT Min Nom Max Units 0, 1, 0 120 RTT120PD240 0.2 x VCCQ 0.6 1.0 1.1 RZQ/1 0.5 x VCCQ 0.9 1.0 1.1 RZQ/1 0.8 x VCCQ 0.9 1.0 1.4 RZQ/1 0.2 x VCCQ 0.9 1.0 1.4 RZQ/1 0.5 x VCCQ 0.9 1.0 1.1 RZQ/1 RTT120PU240 120 0, 0, 1 60 RTT60PD120 RTT60PU120 60 0, 1, 1 40 RTT40PD80 RTT40PU80 40 1, 0, 1 30 RTT30PD60 RTT30PU60 30 1, 0, 0 20 RTT20PD40 RTT20PU40 20 0.8 x VCCQ 0.6 1.0 1.1 RZQ/1 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 0.2 x VCCQ 0.6 1.0 1.1 RZQ/2 0.5 x VCCQ 0.9 1.0 1.1 RZQ/2 0.8 x VCCQ 0.9 1.0 1.4 RZQ/2 0.2 x VCCQ 0.9 1.0 1.4 RZQ/2 0.5 x VCCQ 0.9 1.0 1.1 RZQ/2 0.8 x VCCQ 0.6 1.0 1.1 RZQ/2 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 0.2 x VCCQ 0.6 1.0 1.1 RZQ/3 0.5 x VCCQ 0.9 1.0 1.1 RZQ/3 0.8 x VCCQ 0.9 1.0 1.4 RZQ/3 0.2 x VCCQ 0.9 1.0 1.4 RZQ/3 0.5 x VCCQ 0.9 1.0 1.1 RZQ/3 0.8 x VCCQ 0.6 1.0 1.1 RZQ/3 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 0.2 x VCCQ 0.6 1.0 1.1 RZQ/4 0.5 x VCCQ 0.9 1.0 1.1 RZQ/4 0.8 x VCCQ 0.9 1.0 1.4 RZQ/4 0.2 x VCCQ 0.9 1.0 1.4 RZQ/4 0.5 x VCCQ 0.9 1.0 1.1 RZQ/4 0.8 x VCCQ 0.6 1.0 1.1 RZQ/4 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 0.2 x VCCQ 0.6 1.0 1.1 RZQ/6 0.5 x VCCQ 0.9 1.0 1.1 RZQ/6 0.8 x VCCQ 0.9 1.0 1.4 RZQ/6 0.2 x VCCQ 0.9 1.0 1.4 RZQ/6 0.5 x VCCQ 0.9 1.0 1.1 RZQ/6 0.8 x VCCQ 0.6 1.0 1.1 RZQ/6 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 NOTES 1. Values assume an RZQ of 240 (1 percent). Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 28 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 21 - DDR3 ICC SPECIFICATIONS AND CONDITIONS Symbol Proposed Conditions 1,333 CL10 800 CL6 1,066 CL8 Units ICC0 Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 500 450 mA (1, 2) ICC1 Operating one bank active-read-precharge current; IOUT = 0mA; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bud inpuyd str plosyinh 650 625 mA (1, 2) Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast 175 150 mA (1, 2) ICC2P Slow 60 60 mA (1, 2) ICC2Q Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 175 150 mA (1, 2) ICC2N Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 185 160 mA (1, 2) ICC3P Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING 200 175 mA (1, 2) ICC3N Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 200 175 mA (1, 2) ICC4W Operating burst write current; All banks open, Continuous burst writes; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1,275 1,050 mA (1, 2) ICC4R Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 8, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDAD6W 1,225 1,000 mA (1, 2) ICC5B Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING 1,000 950 mA (1, 2) ICC6 Self refresh current; CK, CK# and CKE are low. Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING 60 60 mA (1, 2, 3) 75 75 mA (2, 4) 2,125 1,875 mA (1, 2) ICC6ET ICC7 Normal Self refresh current extended temperature: CK, CK# and CKE are low; other control and address bus inputs are floating; data bus inputs are floating Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 8, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for detailed timing conditions NOTES: 1. TC = 85C; SRT and ASR are disabled. 2. Enabling ASR could increase ICCx by up to an additional 2mA 3. Resricted to TC (max) = 85C 4. Tc = 85C; ASR and ODT are disabled; SRT in enables. 5. The ICC values must be derated (increased) on devices when operated outside of the range 0C TC +85C: 5a. When TC < 0C: ICC2P and ICC3P must be derated by 4%; ICC4R and ICC5W must be derated by 2%; and ICC6 and ICC7 must be derated by 7%. 5b. When TC > +85C: ICC0, ICC1, ICC2N, ICC2NT, ICC2Q, ICC3N, ICC3P, ICC4R, ICC4W, and ICC5W must be derated by 2%; ICC2Px must be derated by 30%; and ICC6 must be derated by 80%. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 29 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 22 - DDR3-800 SPEED BINS CL-tRCD-tRP 6-6-6 Parameter Symbol Min Max Units ACTIVATE to internal READ or WRITE delay time tRCD 15 - ns PRECHARGE command period tRP 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 52.5 - ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 x tREFI ns 1 tCK (AVG) 2.5 ns 2 CL = 6 CWL = 5 3.3 Supported CL settings 6 CK Supported CWL setting 5 CK Notes NOTES: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. TABLE 23 - DDR3-1,066 SPEED BINS CL-tRCD-tRP 8-8-8 Parameter Symbol Min Max Units ACTIVATE to internal READ or WRITE delay time tRCD 15 - ns PRECHARGE command period tRP 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 52.5 - ns ACTIVATE-to-PRECHARGE command period tRAS 37.5 9 x tREFI ns 1 tCK (AVG) 1.875 ns 2 CL = 8 CWL = 6 <2.5 Supported CL settings 8 CK Supported CWL setting 6 CK Notes NOTES: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. TABLE 24 - DDR3-1,333 SPEED BINS CL-tRCD-tRP Parameter 10-10-10 Units Notes Symbol Min Max Internal READ command to fist data tAA 15 - ACTIVATE to internal READ or WRITE delay time tRCD 15 - ns PRECHARGE command period tRP 15 - ns ACTIVATE-to-ACTIVATE or REFRESH command period tRC 51 - ns ACTIVATE-to-PRECHARGE command period tRAS 36 9 x tREFI ns 1 CL = 5 CWL = 5 tCK (AVG) 3.0 3.3 ns 2 CL = 6 CWL = 5 tCK (AVG) 2.5 3.3 ns 2 CL = 8 CWL = 6 tCK (AVG) 1.875 <2.5 ns 2 CL = 10 CWL = 7 tCK (AVG) 1.5 <1.875 ns 2 Supported CL settings 5, 6, 8, 10 CK Supported CWL setting 5, 6, 7 CK NOTES: 1. tREFI depends on TOPER. 2. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement settings need to be fulfilled. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 30 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 24 - AC TIMING PARAMETERS Parameter DDR3-800 Min Max Symbol DDR3-1066 Min Max DDR3-1333 Min Max Units Notes ns 9, 42 Clock Timing Clock period average: DLL disable mode TC = 0C to 85C TC = >85C to 95C 8 tCKDLL_DIS 8 7,800 8 7,800 8 7,800 3,900 8 3,900 8 3,900 ns 42 ns 10, 11 0.53 CK 12 0.53 CK 12 -80 80 ps 13 -70 70 ps 13 Clock period average: DLL enable mode tCK (AVG) High pulse width average tCH (AVG) 0.47 0.53 0.47 0.53 0.47 Low pulse width average tCL (AVG) 0.47 0.53 0.47 0.53 0.47 DLL locked tJITPER -100 100 -90 90 DLL locking tJITPER, LCK -90 90 -80 80 Clock period jitter See "Speed Bin Tables" on page 35 for tCK range allowed MIN = tCK (AVG) MIN + tJITPER MIN; MAX = tCK (AVG) MAX + tJITPER MAX Clock absolute period tCK(ABS) Clock absolute high pulse width tCH (ABS) 0.43 tCL (ABS) 0.43 Clock absolute low pulse width Cycle-to-cycle jitter Cumulative error across - 0.43 - 0.43 200 ps - 0.43 - 0.43 180 - tCK (AVG) - tCK (AVG) 15 ps 16 160 14 DLL locked tJITCC DLL locking tJITCC, LCK ps 16 2 cycles tERR2PER -147 147 -132 132 -118 118 ps 17 3 cycles tERR3PER -175 175 -157 157 -140 140 ps 17 4 cycles tERR4PER -194 194 -175 175 -155 155 ps 17 5 cycles tERR5PER -209 209 -188 188 -168 168 ps 17 6 cycles tERR6PER -222 222 -200 200 -177 177 ps 17 7 cycles tERR7PER -232 232 -209 209 -186 186 ps 17 8 cycles tERR8PER -241 241 -217 217 -193 193 ps 17 9 cycles tERR9PER -249 249 -224 224 -200 200 ps 17 10 cycles tERR10PER -257 257 -231 231 -205 205 ps 17 11 cycles tERR11PER -263 263 -237 237 -210 210 ps 17 12 cycles tERR12PER -269 269 -242 242 -215 215 ps 17 ps 17 n = 13, 14 . . . 49, 50 cycles 180 160 140 tERRnPER MIN = (1 + 0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1 + 0.68ln[n]) x tJITPER MAX tERRnPER DQ Input Timing Data setup time to DQS, DQS# Data setup time to DQS, DQS# Data hold time from DQS, DQS# Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns tDS AC175 tDS AC150 tDH AC100 Minimum data pulse width tDIPW DQS, DQS# to DQ skew, per access tDQSQ 75 - 25 - - - ps 18, 19 250 - 200 125 - 75 - - - ps 19, 20 - 30 - ps 18, 19 275 - 150 - 250 - 180 - ps 19, 20 100 - 65 45 ps 18,19 250 600 - 200 - 165 145 ps 19, 20 - 490 - 400 360 ps 42 200 - 150 - 125 ps DQ Output Timing DQ output hold time from DQS, DQS# - tQH 0.38 - 0.38 - 0.38 - tCK (AVG) 21 DQ Low-Z time from CK, CK# tLZ (DQ) -800 400 -600 300 -500 250 ps 22, 23 DQ High-Z time from CK, CK# tHZ (DQ) - 400 - 300 - 250 ps 22, 23 Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 31 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 24 - AC TIMING PARAMETERS (continued) Parameter Symbol DDR3-800 Min DDR3-1066 Max DDR3-1333 Min Max Min Max Units Notes 25 DQ Strobe Input Timing DQS, DQS# rising to CK, CK# rising tDQSS -0.25 0.25 -0.25 0.25 -0.25 0.25 CK DQS, DQS# differential input low pulse width tDQSL 0.45 0.55 0.45 0.55 0.45 0.55 CK DQS, DQS# differential input high pulse width tDQSH 0.45 0.55 0.45 0.55 0.45 0.55 CK DQS, DQS# falling setup to CK, CK# rising tDSS 0.2 - 0.2 - 0.2 - CK 25 DQS, DQS# falling hold from CK, CK# rising tDSH 0.2 - 0.2 - 0.2 - CK 25 DQS, DQS# differential WRITE preamble tWPRE 0.9 - 0.9 - 0.9 - CK DQS, DQS# differential WRITE postamble tWPST 0.3 - 0.3 - 0.3 - CK DQ Strobe Output Timing DQS, DQS# rising to/from rising CK, CK# tDQSCK -400 400 -300 300 -255 255 ps 23 tDQSCK DLL_DIS 1 10 1 10 1 10 ns 26 DQS, DQS# differential output high time tQSH 0.38 - 0.38 - 0.40 - CK 21 DQS, DQS# differential output low time tQSL 0.38 - 0.38 - 0.40 - CK 21 DQS, DQS# Low-Z time (RL - 1) tLZ (DQS) -800 400 -600 300 -500 250 ps 22, 23 DQS, DQS# High-Z time (RL + BL/2) tHZ (DQS) - 400 - 300 - 250 ps 22, 23 DQS, DQS# differential READ preamble tRPRE 0.9 Note 24 0.9 Note 24 0.9 Note 24 CK 23, 24 DQS, DQS# differential READ postamble tRPST 0.3 Note 27 0.3 Note 27 0.3 Note 27 CK 23, 27 DQS, DQS# rising to/from rising CK, CK# when DLL is disabled Command and Address Timing DLL locking time CTRL, CMD, ADDR setup to CK,CK# CTRL, CMD, ADDR hold from CK,CK# CTRL, CMD, ADDR setup to CK,CK# tDLLK Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns Base (specification) VREF @ 1 V/ns tIS AC175 tIH tIS AC150 512 - 512 - 512 - CK 28 200 - 125 - 65 - ps 29, 30 375 - 300 - 240 - ps 20, 30 275 - 200 - 190 - ps 29, 30 375 - 300 - 340 - ps 20, 30 350 - 275 - 140 - ps 29, 30 500 - 425 - 240 - ps 20, 30 - 780 - 620 - Minimum CTRL, CMD, ADDR pulse width tIPW ps 41 ACTIVATE to internal READ or WRITE delay tRCD See "Speed Bin Tables" on page 30 for tRCD ns 31 PRECHARGE command period tRP See "Speed Bin Tables" on page 30 for tRP ns 31 ACTIVATE-to-PRECHARGE command period tRAS See "Speed Bin Tables" on page 30 for tRAS ns 31, 32 ACTIVATE-to-ACTIVATE command period tRC See "Speed Bin Tables" on page 30 for tRC ns 31 MIN = greater of 4CK or 6ns CK 31 MIN = greater of 4CK or 7.5ns CK 31 31 ACTIVATE-to-ACTIVATE minimum command period 1KB page size tRRD 900 MIN = greater of 4CK or 10ns 2KB page size Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size MIN = greater of 4CK or 7.5ns MIN = greater of 4CK or 10ns tFAW 40 - 37.5 - 30 - ns 50 - 50 - 45 - ns 31 Write recovery time tWR MIN = 15ns; MAX = n/a ns 31, 32, 33 Delay from start of internal WRITE transaction to internal READ command tWTR MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 34 READ-to-PRECHARGE time tRTP MIN = greater of 4CK or 7.5ns; MAX = n/a CK 31, 32 CAS#-to-CAS# command delay tCCD MIN = 4CK; MAX = n/a CK CK Auto precharge write recovery + precharge time tDAL MIN = WR + tRP/tCK (AVG); MAX = n/a MODE REGISTER SET command cycle time tMRD MIN = 4CK; MAX = n/a CK MODE REGISTER SET command update delay tMOD MIN = greater of 12CK or 15ns; MAX = n/a CK MULTIPURPOSE REGISTER READ burst end to mode register set for multipurpose register exit tMPRR MIN = 1CK; MAX = n/a CK continued on next page Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 32 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 24 - AC TIMING PARAMETERS (continued) Parameter Symbol ZQCL command: Long calibration time DDR3-800 Min Max Calibration Timing DDR3-1066 Min Max DDR3-1333 Min Max Units POWER-UP and RESET operation tZQINIT 512 - 512 - 512 - CK Normal operation tZQOPER 256 - 256 - 256 - CK ZQCS command: Short calibration time tZQCS 64 - 64 - 64 - CK Exit reset from CKE HIGH to a valid command tXPR MIN = greater of 5CK or tRFC + 10ns; MAX = n/a Notes Initialization and Reset Timing Begin power supply ramp to power supplies stable CK tVDDPR MIN = n/a; MAX = 200 ms RESET# LOW to power supplies stable tRPS MIN = 0; MAX = 200 ms RESET# LOW to I/O and RTT High-Z tIOz MIN = n/a; MAX = 20 ns MIN = 160; MAX = 9 x tREFI (REFRESH-to-REFRESH command period) ns 64 (1X) ms 36 32 (2X) ms 36 7.8 (64ms/8,192) s 36 3.9 (32ms/8,192) s 36 tXS MIN = greater of 5CK or tRFC + 10ns; MAX = n/a CK Exit self refresh to commands requiring a locked DLL tXSDLL MIN = tDLLK (MIN); MAX = n/a CK Minimum CKE low pulse width for self refresh entry to self refresh exit timing tCKESR MIN = tCKE (MIN) + CK; MAX = n/a CK Valid clocks after self refresh entry or powerdown entry tCKSRE MIN = greater of 5CK or 10ns; MAX = n/a CK Valid clocks before self refresh exit, powerdown exit, or reset exit tCKSRX MIN = greater of 5CK or 10ns; MAX = n/a CK 35 Refresh Timing REFRESH-to-ACTIVATE or REFRESH command period Maximum refresh period Maximum average periodic refresh TC = 0C to 85C TC = >85C to 95C TC = 0C to 85C TC = >85C to 95C tRFC - tREFI Self Refresh Timing Exit self refresh to commands not requiring a locked DLL 28 Power-Down Timing CKE MIN pulse width tCKE (MIN) Command pass disable delay Power-down entry to power-down exit timing Greater of 3CK or 7.5ns Greater of 3CK or 5.625ns Greater of 3CK or 5.625ns CK tCPDED MIN = 1; MAX = n/a CK tPD MIN = tCKE (MIN); MAX = 60ms CK Begin power-down period prior to CKE registered HIGH tANPD WL - 1CK CK Power-down entry period: ODT either synchronous or asynchronous PDE Greater of tANPD or tRFC - REFRESH command to CKE LOW time CK Power-down exit period: ODT either synchronous or asynchronous PDX tANPD + tXPDLL CK tACTPDEN MIN = 1 CK PRECHARGE/PRECHARGE ALL command to power-down entry tPRPDEN MIN = 1 CK REFRESH command to power-down entry tREFPDEN MIN = 1 CK MRS command to power-down entry tMRSPDEN MIN = tMOD (MIN) CK READ/READ with auto precharge command to power-down entry tRDPDEN MIN = RL + 4 + 1 CK BL8 (OTF, MRS) BC4OTF tWRPDEN MIN = WL + 4 + tWR/tCK (AVG) CK BC4MRS tWRPDEN MIN = WL + 2 + tWR/tCK (AVG) CK BL8 (OTF, MRS) BC4OTF tWRAPDEN MIN = WL + 4 + WR + 1 CK BC4MRS tWRAPDEN MIN = WL + 2 + WR + 1 CK Power-Down Entry Minimum Timing ACTIVATE command to power-down entry WRITE command to power-down entry WRITE with auto precharge command to power-down entry 37 continued on next page Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 33 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX TABLE 24 - AC TIMING PARAMETERS (continued) DDR3-800 Min Max Power-Down Exit Timing Parameter Symbol DLL on, any valid command, or DLL off to commands not requiring locked DLL Precharge power-down with DLL off to commands requiring a locked DLL MIN = greater of 3CK or 7.5ns; MAX = n/a tXP tXPDLL DDR3-1066 Min Max DDR3-1333 Min Max Units MIN = greater of 3CK or 6ns; MAX = n/a MIN = greater of 3CK or 6ns; MAX = n/a CK Notes MIN = greater of 10CK or 24ns; MAX = n/a CK 28 CWL + AL - 2CK CK 38 ODT Timing RTT synchronous turn-on delay ODTL on RTT synchronous turn-off delay ODTL off CK 40 RTT turn-on from ODTL on reference tAON -400 400 -300 CWL + AL - 2CK 300 -250 250 ps 23, 38 RTT turn-off from ODTL off reference tAOF 0.3 0.7 0.3 0.7 0.3 0.7 CK 39, 40 Asynchronous RTT turn-on delay (power-down with DLL off) tAONPD MIN = 2; MAX = 8.5 ns 38 Asynchronous RTT turn-off delay (power-down with DLL off) tAOFPD MIN = 2; MAX = 8.5 ns 40 ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = n/a CK ODT HIGH time without WRITE command or with WRITE command and BC4 ODTH4 MIN = 4; MAX = n/a CK Dynamic ODT Timing RTT_NOM-to-RTT_WR change skew ODTLCNW WL - 2CK CK RTT_WR-to-RTT_NOM change skew - BC4 ODTLCNW4 4CK + ODTL off CK RTT_WR-to-RTT_NOM change skew - BL8 ODTLCNW8 RTT dynamic change skew tADC 6CK + ODTL off 0.3 0.7 CK 0.3 0.7 0.3 0.7 CK 39 Write Leveling Timing First DQS, DQS# rising edge tWLMRD 40 - 40 - 40 - CK DQS, DQS# delay tWLDQSEN 25 - 25 - 25 - CK Write leveling setup from rising CK, CK# crossing to rising DQS, DQS# crossing tWLS 325 - 245 - 195 - ps Write leveling hold from rising DQS, DQS# crossing to rising CK, CK# crossing tWLH 325 - 245 - 195 - ps Write leveling output delay tWLO 0 9 0 9 0 9 ns Write leveling output error tWLOE 0 2 0 2 0 2 ns Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 34 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX AC OVERSHOOT/UNDERSHOOT SPECIFICATION Table 25 - Control and Address Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 14) Maximum peak amplitude allowed for undershoot area (see Figure 15) DDR3-800 DDR3-1066 DDR3-1333 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above VCC (see Figure 14) 0.67 Vns 0.5 Vns 0.4 Vns Maximum undershoot area below VSS (see Figure 15) 0.67 Vns 0.5 Vns 0.4 Vns DDR3-800 DDR3-1066 DDR3-1333 Maximum peak amplitude allowed for overshoot area (see Figure 14) 0.4V 0.4V 0.4V Maximum peak amplitude allowed for undershoot area (see Figure 15) 0.4V 0.4V 0.4V Maximum overshoot area above VCC/VCCQ (see Figure 14) 0.25 Vns 0.19 Vns 0.15 Vns Maximum undershoot area below VSS/VSSQ (see Figure 15) 0.25 Vns 0.19 Vns 0.15 Vns Table 26 - Clock, Data, Strobe, and Mask Pins Parameter FIGURE 14 - OVERSHOOT Maximum amplitude Overshoot area Volts (V) VCC/VCCQ Time (ns) FIGURE 15 - UNDERSHOOT VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 35 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX NOTES: 1. Parameters are applicable with 0C TC +95C and VCC/VCCQ = +1.5V 0.075V. 2. All voltages are referenced to VSS. 3. Output timings are only valid for RON34 output buffer selection. 4. Unit "tCK (AVG)" represents the actual tCK (AVG) of the input clock under operation. Unit "CK" represents one clock cycle of the input clock, counting the actual clock edges. 5. AC timing and ICC tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single ended inputs and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC). 6. All timings that use time-based values (ns, s, ms) should use tCK (AVG) to determine the correct number of clocks (AC Operation Table). In the case of non integer results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. 7. The use of "strobe" or "DQSDIFF" refers to the DQS and DQS# differential crossing point when DQS is the rising edge. The use of "clock" or "CK" refers to the CK and CK# differential crossing point when CK is the rising edge. 8. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VCCQ/2 for singleended signals and the crossing point for differential signals. 9. NOTE: When operating in DLL disable mode, WEDC does not warrant compliance with normal mode timings or functionality. 10. The clock's tCK (AVG) is the average clock over any 200 consecutive clocks and tCK(AVG) MIN is the smallest clock rate allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 11. Spread spectrum is not included in the jitter specification values. However, the input clock can accommodate spread-spectrum at a sweep rate in the range of 20-60 kHz with an additional 1 percent of tCK (AVG) as a long-term jitter component; however, the spread-spectrum may not use a clock rate below tCK (AVG) MIN. 12. The clock's tCH (AVG) and tCL (AVG) are the average half clock period over any 200 consecutive clocks and is the smallest clock half period allowed, with the exception of a deviation due to clock jitter. Input clock jitter is allowed provided it does not exceed values specified and must be of a random Gaussian distribution in nature. 13. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock. It is allowed in either the positive or negative direction. 14. tCH(ABS) is the absolute instantaneous clock high pulse width as measured from one rising edge to the following falling edge. 15. tCL(ABS) is the absolute instantaneous clock low pulse width as measured from one falling edge to the following rising edge. 16. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one cycle to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL locking time. 17. The cumulative jitter error (tERRnPER), where n is the number of clocks between 2 and 50, is the amount of clock time allowed to accumulate consecutively away from the average clock over n number of clock cycles. 18. tDS (base) and tDH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns differential DQS, DQS# slew rate. 19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transition edge to its respective data strobe signal (DQS, DQS#) crossing. 20. The setup and hold times are listed converting the base specification values (to which derating tables apply) to VREF when the slew rate is 1 V/ns. These values, with a slew rate of 1 V/ns, are for reference only. 21. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJITPER of the input clock (output deratings are relative to the SDRAM input clock). 22. Single-ended signal parameter. 23. The DRAM output timing is aligned to the nominal or average clock. Most output parameters must be derated by the actual jitter error when input clock jitter is present, even when within specification. This results in each parameter becoming larger. The following parameters are required to be derated by subtracting tERR10PER (MAX): tDQSCK (MIN), tLZ (DQS)MIN, tLZ (DQ) MIN, and tAON (MIN). The following parameters are required to be derated by subtracting tERR10PER (MIN): tDQSCK (MAX), tHZ (MAX), tLZ (DQS)MAX, tLZ (DQ) MAX, and tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX) is derated by subtracting tJITPER (MIN). 24. The maximum preamble is bound by tLZDQS (MAX). 25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock signal (CK, CK#) crossing. The specification values are not affected by the amount of clock jitter applied, as these are relative to the clock signal crossing. These parameters should be met whether clock jitter is present. 26. The tDQSCK DLL_DIS parameter begins CL + AL - 1 cycles after the READ command. 27. The maximum postamble is bound by tHZDQS (MAX). 28. Commands requiring a locked DLL are: READ (and RDAP) and synchronous ODT commands. In addition, after any change of latency tXPDLL, timing must be met. 29. tIS (base) and tIH (base) values are for a single-ended 1 V/ns control/command/ address slew rate and 2 V/ns CK, CK# differential slew rate. 30. These parameters are measured from a command/address signal transition edge to its respective clock (CK, CK#) signal crossing. The specification values are not affected by the amount of clock jitter applied as the setup and hold times are relative to the clock signal crossing that latches the command/address. These parameters should be met whether clock jitter is present. 31. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means for DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the internal PRECHARGE command until tRAS (MIN) has been satisfied. 33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for tWR. 34. The start of the write recovery time is defined as follows: - For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL - For BC4 (OTF): Rising clock edge four clock cycles after WL - For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL 35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in excessive current, depending on bus activity. 36. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, nine REFRESH commands must be asserted at least once every 70.3s. 37. Although CKE is allowed to be registered LOW after a REFRESH command when tREFPDEN (MIN) is satisfied, there are cases where additional time such as tXPDLL (MIN) is required. 38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to turn on. ODT turn-on time maximum is when the ODT resistance is fully on. 39. Half-clock output parameters must be derated by the actual tERR10PER and tJITDTY when input clock jitter is present. This results in each parameter becoming larger. The parameters tADC (MIN) and tAOF (MIN) are each required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). The parameters tADC (MAX) and tAOF (MAX) are required to be derated by subtracting both tERR10PER (MAX) and tJITDTY (MAX). 40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT turn-off time maximum is when the DRAM buffer is in High-Z. This output load is used for ODT timings. 41. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 42. Should the clock rate be larger than tRFC (MIN), an AUTO REFRESH command should have at least one NOP command between it and another AUTO REFRESH command. Additionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should be followed by a PRECHARGE ALL command. Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 36 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 16 - PACKAGE DIMENSION: 375 PLASTIC BALL GRID ARRAY (PBGA) for W3J128M72G-XPBX ble pati m o int cBGA r p t o * Fo th 305 P wi BOTTOM VIEW 375 x O 0.60 (0.024) NOM 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F J K L 15.98 (0.630) NOM H 17.0 (0.669) NOM 20.75 (0.817) MAX G M 1.0 (0.039) NOM N P R T U V 15 NOM 1.0 (0.039) NOM 20 (0.787) NOM 21.75 (0.856) MAX 0.50 (0.020) NOM 1.35 (0.053) NOM 5.50 (0.217) MAX All linear dimensions are millimeters and parenthetically in inches Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 37 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX FIGURE 16A - PACKAGE DIMENSION: 305 PLASTIC BALL GRID ARRAY (PBGA) FOR W3J128M72G-XLBX* tal n e pm ible t o l a e p v comA * De t n i G tpr Foo 375 PB with BOTTOM VIEW 305 x O 0.60 (0.024) NOM 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F H 17.0 (0.669) NOM 21.25 (0.837) MAX G J K L M 1.0 (0.039) NOM N P R T U V 1.0 (0.039) NOM 20 (0.787) NOM 0.50 (0.020) NOM 22.25 (0.876) MAX 2.50 (0.098) MAX All linear dimensions are millimeters and parenthetically in inches Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 38 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX ORDERING INFORMATION W 3J 128M 72 G - XXXX XX X X MICROSEMI CORPORATION DDR3 SDRAM CONFIGURATION, 128M x 72 1.5V POWER SUPPLY DATA RATE (Mb/s) 800 = 800Mb/s 1066 = 1,066Mb/s 1333 = 1333Mb/s PACKAGE: PB = 375 Plastic Ball Grid Array (PBGA) LB = 305 Plastic Ball Grid Array (PBGA), low profile DEVICE GRADE: I = Industrial -40C to +85C C = Commercial 0C to +70C DIE SUPPLIER: Blank = Microsemi Discretion (Best Value Option) A = Supplier A (Contact Sales) B = Supplier B (Contact Sales) C = Supplier C (Contact Sales) D = Supplier D (Contact Sales) Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 39 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX Document Title 1GB - 128M x 72 DDR3 SDRAM 375 PBGA Multi-Chip Package Revision History Rev # History Release Date Status Rev 0 Initial Release February 2010 ADVANCED Rev 1 Changes (Pg. 1, 2, 3, 35, 36) June 2010 ADVANCED September 2010 ADVANCED September 2010 ADVANCED January 2011 ADVANCED March 2011 ADVANCED June 2011 PRELIMINARY July 2011 PRELIMINARY August 2011 PRELIMINARY August 2011 PRELIMINARY 1.1 Updated package pinout to 377 PBGA 1.2 Updated functional block diagram 1.3 Updated pin configuraion 1.4 Updated mechanical outline Rev 2 Changes (Pg. 1, 3, 35, 36) 2.1 Changed package size to 20.5mm x 21.5mm 2.2 Changed pinout to 375 PBGA 2.3 Deleted balls K1 and K21 Rev 3 Changes (Pg. 1, 4, 37) 3.1 Add low profile PBGA option Rev 4 Changes (Pg. 36) 4.1 Change height dimension to 5.5mm (0.217) max and drawing corrected Rev 5 Changes (Pg. 36) 5.1 Added dimensions for top portion of the package Rev 6 Changes (Pg. 1-39) 6.1 Change status from Advanced to Preliminary Rev 7 Changes (Pg. 35, 37, 38) 7.1 Added AC Overshoot/Undershoot Specification tables (tbls 25 and 26) and figures (figrs 14 and 15) 7.2 Added "*Footprint compatible with 305 PGBA" to Figure 16 7.3 Added "*Footprint compatible with 375 PGBA" to Figure 17 Rev 8 Change (Pg. 1) 8.1 Add "Typical Application" diagram Rev 9 Change (Pg. 1) 9.1 Change description in SSD (SLC) box in "Typical Application" diagram 9.2 Add SATA, 2.5 inch drive photo to "Typical Application" diagram Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 40 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp W3J128M72G-XLBX W3J128M72G-XPBX Document Title 1GB - 128M x 72 DDR3 SDRAM 375 PBGA Multi-Chip Package Revision History (continued) Rev # History Release Date Status Rev 10 Changes (Pg. 39) August 2011 ADVANCED October 2011 FINAL October 2011 FINAL 10.1 Add die supplier options to ordering information Rev 11 Changes (Pg. 1) 11.1 Change data sheet status to FINAL Rev 12 Changes (Pg. 1, 2, 26, 27, 29, 30, 31, 32, 33, 34, 37, 39) 12.1 Change 1333 to regular option 12.2 Add bullet to Features "Lower voltage (1.35V) option available in same package 12.3 Add bullet to Benefits "Built-in decoupling" 12.4 Update block diagram 12.5 Delete Table 16 12.6 Add DDR3-1333 column to Table 18 12.7 Add 1,333 CL10 column to Table 21 and update values 12.8 Add Table 24 "DDR3-1333 SPEED BINS 12.9 Add DDR3-1333 Min - Max column to AC Timing Parameters 12.10 Change Min value under Refresh Timing on Table 24 from 110 to 160 12.11 Update side view in Figure 16 12.12 Update Ordering Info chart Microsemi Corporation reserves the right to change products or specifications without notice. October 2011 Rev. 12 (c) 2011 Microsemi Corporation. All rights reserved. 41 Microsemi Corporation * (602) 437-1520 * www.whiteedc.com www.microsemi.com/pmgp