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©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
HUF76639S3S
N-Channel Logic Level UltraFET Power MOSFET
100 V, 50 A, 27 mΩ
Packaging
Symbol
Features
Ultra Low On-Resistance
-r
DS(ON) = 0.026Ω, VGS = 10V
-r
DS(ON) = 0.027Ω, VGS = 5V
Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Mo de ls
- www.fairchildsemi.com
Peak Current vs Pu lse Width Curve
UIS Rating Curve
Switching Time vs RGS Curves
Ordering Information
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Autom ot i v e HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 an d QS9000 quality systems c e rtification.
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
D
G
S
PART NUMBER PACKAGE BRAND
TO-263AB 76639S
HUF76639S3STUNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 100 V
Drain to Gate Voltage (R GS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 100 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±16 V
Drain Current
Continuous (TC = 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
50
51
35
34
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
1.2 W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
NOTES:
1. TJ = 25oC to 150 oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operatio n of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Data Sheet October 2013
HUF76639S3ST
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source B reakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 12) 100 - - V
ID = 250µA, V GS = 0V , TC = -40oC (Figure 12) 90 - - V
Zero Gate Vo ltage Drain C urrent IDSS VDS = 95V, VGS = 0V - - 1 µA
VDS = 90V, VGS = 0V, TC = 150oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±16V - - ±100 nA
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 11) 1 - 3 V
Drain to Source On Resist ance rDS(ON) ID = 51A, VGS = 10V (Figures 9, 10) - 0.023 0.026
ID = 35A, VGS = 5V (Figure 9) - 0.024 0.027
ID = 34A, VGS = 4.5V (Figure 9) - 0.025 0.028
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case RθJC TO-263 - - 0.83 oC/W
Thermal Resistance Junction to
Ambient RθJA --62
oC/W
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time tON VDD = 50V, ID = 34A
VGS = 4.5V, RGS = 12
(Figures 15, 21, 22)
- - 336 ns
Turn-On De lay Time td(ON) -17-ns
Rise Time tr- 207 - ns
Turn-Off De lay Time td(OFF) -83-ns
Fall Time tf- 136 - ns
Turn-Off T ime tOFF - - 328 ns
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time tON VDD = 50V, ID = 51A
VGS = 10V, RGS = 12
(Figures 16, 21, 22)
- - 96 ns
Turn-On De lay Time td(ON) -10-ns
Rise Time tr-55-ns
Turn-Off De lay Time td(OFF) - 151 - ns
Fall Time tf- 110 - ns
Turn-Off T ime tOFF - - 392 ns
GATE CHARGE SPECIFICATIONS
Total Gate Charge Qg(TOT) VGS = 0V to 10V VDD = 50V,
ID = 35A,
Ig(REF) = 1.0mA
(Figures 14, 19, 20)
-7186nC
Gate Charge at 5V Qg(5) VGS = 0V to 5V - 39 47 nC
Threshold Gate Charge Qg(TH) VGS = 0V to 1V - 2.0 2.4 nC
Gate to Source Gate C harge Qgs -6-nC
Gate to Drain “Miller” Charge Qgd -19-nC
CAPACITANCE SPECIFICATIONS
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
- 2400 - pF
Output Capacitance COSS - 520 - pF
Reverse Transfer Capacitance CRSS - 140 - pF
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to D rain Diode Voltage VSD ISD = 35A - - 1.25 V
ISD = 15A - - 1.0 V
Reverse Recovery Time trr ISD = 35A, dISD/dt = 100A/µs - - 137 ns
Reverse Recovered Charge QRR ISD = 35A, dISD/dt = 100A/µs - - 503 nC
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
Typical Performance Curves
FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. PEAK CURRENT CAPABILITY
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
00 25 50 75 100 17
5
0.2
0.4
0.6
0.8
1.0
1.2
125 150
10
20
30
40
50
60
25 50 75 100 125 150 17
5
0
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
VGS = 10V
VGS = 4.5V
0.1
1
10-5 10-4 10-3 10-2 10-1 100101
0.01
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
PDM
t1t2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.01
0.02
THERMAL IMPED ANCE
100
1000
10-4 10-3 10-2 10-1 100101
10-5
50
IDM, PEAK CURRENT (A)
t, PULSE WIDTH (s)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
I = I25 175 - TC
150
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
VGS = 5V
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 10. NORMALIZED DRAIN T O SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves (Continued)
10
100
110100
300
1
30
0
100µs
10ms
1ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
LIMITED BY rDS(ON)
AREA MAY BE
OPERATION IN THIS
TJ = MAX RATED
SINGLE PULSE
TC = 25oC
0.01 0.1 1 10 10
0
10
100
1
500
IAS, AVALANCHE CURRENT (A)
tAV, TI ME IN AVALANCHE (ms)
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R = 0
If R 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
STARTING TJ = 150oC
25
50
75
100
1.5 2.0 2.5 3.0 3.5 4.
0
0
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
TJ = 175oC
TJ = 25oC TJ = -55oC
25
50
75
100
01234
5
0
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURC E VO LTAGE (V)
VGS = 3V
VGS = 3 .5V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 5V
VGS = 1 0V
VGS = 4V
25
30
35
40
24681
0
20
ID = 15A
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 51A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (m)
ID = 35A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
1.0
1.5
2.0
2.5
3.0
-80 -40 0 40 80 120 160 20
0
0.5
NORMALIZED DRAIN TO SOURCE
TJ, JUNCTION TEMPERATURE (oC)
ON RESISTANCE
VGS = 10V, ID = 51A
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
FIGURE 11. NORMALIZED GATE THRESHOLD V OLTAGE vs
JUNCTION TEMPERATURE FIGURE 12. NORMALIZED DRAIN T O SOURCE BREAKDO WN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE W A VEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Typical Performance Curves (Continued)
0.6
0.8
1.0
1.2
-80 -40 0 40 80 120 160 200
0.4
NORMALIZED GATE
TJ, JUNCTION TEMPERATURE (oC)
VGS = VDS, ID = 250µA
THRESHOLD VOLTAGE
1.0
1.1
1.2
-80 -40 0 40 80 120 160 200
0.9
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
100
1000
0.1 1 10 10
0
5000
40
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
COSS CDS + CGD
CRSS = CGD 2
4
6
8
10
0 153045607
5
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDD = 50V
Qg, GATE CHARG E (nC)
ID = 51A
ID = 35A
WAVEFORMS IN
DESCENDING ORDER:
ID = 15A
100
200
300
400
0 1020304050
0
SWITCHING TIME (ns)
RGS, GATE TO SOURCE RESISTANCE ()
VGS = 4.5V, VDD = 50V, ID = 34A
tr
tf
td(ON)
td(OFF) 200
300
400
500
600
0 1020304050
0
100
SWITCHING TIME (ns)
RGS, GATE TO SOURC E RESISTANCE ()
VGS = 10V, VDD = 50V, ID = 51A
td(OFF)
tr
td(ON)
tf
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
Test C ircuits and W aveforms
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAVEFORM
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 1V
Qg(5)
VGS = 5V
Qg(TOT)
VGS = 10
V
VDS
VGS
I
g(REF)
0
0
Qgs Qgd
VGS
RL
RGS DUT
+
-VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
PSPICE Ele ctrical Model
.SUBCKT HUF76639 2 1 3 ; rev 26 July 1999
CA 12 8 4.2e-9
CB 15 14 4.2e -9
CIN 6 8 2.27e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 118.2
EDS 1 4 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTH R ES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRA IN 2 5 1.0 e - 9
LGATE 1 9 5.1e-9
LSOURCE 3 7 3.1e-9
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 15.8e-3
RGATE 9 20 1.94
RLDRAIN 2 5 10
RLGATE 1 9 51
RLSOURCE 3 7 31
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3. 6 e -3
RVTHRES 22 8 RVTHRESMOD 1
RVTE M P 18 19 RVTEMPMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2 AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*99),3.5))}
.MODEL DBODYMOD D (IS = 2.6e-12 RS = 2.65e-3 IKF = 6 TRS1 = 1.5e- 3 TRS2 = 3.5e-6 CJO = 2.1e-9 TT = 5.6e-8 M = 0.52)
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 1e-4 TRS2 = -1e-6)
.MODE L DPLCAPMOD D (CJO = 2.6e-9 IS = 1e- 30 M = 0.89 N = 10)
.MODEL MMEDMOD NMOS (VTO = 1.77 KP = 7 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 1.94)
.MODEL MSTRO MOD NMOS (VTO = 2.06 KP = 95 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 19.4 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 2.3e-5)
.MODE L R SLCMO D RES ( T C 1 = 3.4e-3 TC2 = 2.5e - 6 )
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 1.5e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF = -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF = -4.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF = -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MO SFET Feat u ring Gl obal
Temperature Options; IEEE Power Electr onics Specialist Conference Records, 1991, written by William J . Hepp and C. Frank Wheatley.
18
22
+-
6
8
+
-
5
51
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ESLC
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
SABER Electrical Model
REV 26 July 1999
templ ate huf76639 n2,n1 , n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 2.6e-12, cjo = 2.1e-9, tt = 5 .6e-8, m = 0.52, n=10)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, m = 0.89)
m..model mmedmod = (type=_n, vto = 1 .77, kp = 7, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.06,kp = 95, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.12,is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.0, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
c.ca n12 n8 = 4.2e-9
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 2.27e-9
d.dbody n7 n71 = model = dbodymod
d.dbreak n72 n11 = model = dbreakmod
d.dplcap n10 n5 = model = dplcapmod
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.1e-9
l.lsourc e n3 n7 = 3.1e-9
m.mmed n16 n6 n8 n8 = model = mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model = mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model = mweakmod, l = 1u, w = 1u
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 1.5e-3, tc2 = 3.5e-6
res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = -1e-6
res. rdrain n50 n16 = 15.8e-3, tc1 = 8.5e-3, tc2 = 2.3e-5
res.rgate n9 n20 = 1.94
res.r ldrain n2 n5 = 10
res. rl g ate n1 n9 = 51
res.rlsource n3 n7 = 31
res.rs lc1 n5 n51 = 1e-6, tc1 = 3.4e-3, tc2 = 2.5e-6
res.r slc2 n5 n50 = 1e3
res.rs ource n8 n7 = 3.6e-3, tc1 = 1e-3, tc2 = 1e-6
res.rv temp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1.5e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -4.5e-6
spe.ebreak n11 n7 n17 n18 = 118.2
spe.e ds n14 n8 n5 n8 = 1
spe.e gs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model = s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model = s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model = s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model = s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v (n5,n51))))*((abs(v(n5,n51)*1e6/99))** 3.5))
}
}
18
22
+-
6
8
+
-
19
8
+-
17
18
6
8
+
-
5
8+
-
RBREAK
RVTEMP
VBAT
RVTHRES
IT
17 18
19
22
12
13
15
S1A
S1B
S2A
S2B
CA CB
EGS EDS
14
8
13
814
13
MWEAK
EBREAK DBODY
RSOURCE
SOURCE
11
73
LSOURCE
RLSOURCE
CIN
RDRAIN
EVTHRES 16
21
8
MMED
MSTRO
DRAIN
2
LDRAIN
RLDRAIN
DBREAK
DPLCAP
ISCL
RSLC1
10
5
51
50
RSLC2
1
GATE RGATE EVTEMP
9
ESG
LGATE
RLGATE 20
+
-
+
-
+
-
6
RDBODY
RDBREAK
72
71
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
SPICE Thermal Model
REV 26 July 1999
HUF76639T
CTHERM1 th 6 3.2e-3
CTHERM2 6 5 8 .5e-3
CTHERM3 5 4 1 .2e-2
CTHERM4 4 3 1 .6e-2
CTHERM5 3 2 5 .5e-2
CTHERM6 2 tl 1.5
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 6 .8e-2
RTHERM3 5 4 9 .2e-2
RTHERM4 4 3 2 .0e-1
RTHERM5 3 2 2 .4e-1
RTHERM6 2 tl 5.2e-2
SABER Thermal Model
SABER thermal model HUF76639T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm 1 t h 6 = 3.2e-3
ctherm.ctherm 2 6 5 = 8.5e- 3
ctherm.ctherm 3 5 4 = 1.2e- 2
ctherm.ctherm 4 4 3 = 1.6e- 2
ctherm.ctherm 5 3 2 = 5.5e- 2
ctherm.ctherm6 2 tl = 1.5
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 6.8e-2
rtherm.rtherm3 5 4 = 9.2e-2
rtherm.rtherm4 4 3 = 2.0e-1
rtherm.rtherm5 3 2 = 2.4e-1
rtherm.rtherm6 2 t l = 5.2e- 2
}
RTHERM4
RTHERM6
RTHERM5
RTHERM3
RTHERM2
RTHERM1
CTHERM4
CTHERM6
CTHERM5
CTHERM3
CTHERM2
CTHERM1
tl
2
3
4
5
6
th JUNCTION
CASE
HUF76639S3S
©2001 Fairch ild Semicond uctor Corporation HUF76639S3S Rev. C0
HUF76639S3S
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