v3 .4 PLUS ProASIC TM Flash Family FPGAs Features and Benefits * * High Capacity I/O * * * * * 75,000 to 1 million System Gates 27k to 198kbits of Two-Port SRAM 66 to 712 User I/Os Reprogrammable Flash Technology * * * * 0.22 4LM Flash-based CMOS Process Live at Power-Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/Power-Up Cycles * * * * * * * * * * The Industry's Most Effective Security Key (FlashLock) Prevents Read Back of Programming Bitstream Low Power * * * Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells * * Flexibility with Choice of Industry-Standard Frontend Tools Efficient Design through Frontend Timing and Gate Optimization ISP Support * In-System Programming (ISP) via JTAG Port SRAMs and FIFOs * * High Performance Routing Hierarchy * * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities Internal and/or External Dynamic PLL Configuration Two LVPECL Differential Pairs for Clock or Data Inputs Standard FPGA and ASIC Design Flow Secure Programming * Schmitt-Trigger Option on Every Input 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate Bidirectional Global I/Os Compliance with PCI Specification Revision 2.2 Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant Pin Compatible Packages across ProASICPLUS Family Unique Clock Conditioning Circuitry Performance 3.3V, 32-bit PCI (up to 50 MHz) Two Integrated PLLs External System Performance up to 150 MHz High Performance, Low Skew, Splittable Global Network 100% Routability and Utilization Ultra-Fast Local and Long-Line Network High Speed Very Long-Line Network ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) Table 1 * ProASICPLUS Product Profile Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Maximum System Gates 75,000 150,000 300,000 450,000 600,000 750,000 1,000,000 Maximum Tiles (Registers) 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Embedded RAM Bits (k=1,024 bits) 27k 36k 72k 108k 126k 144k 198k Embedded RAM Blocks (256x9) 12 16 32 48 56 64 88 LVPECL 2 2 2 2 2 2 2 PLL 2 2 2 2 2 2 2 Global Networks 4 4 4 4 4 4 4 Maximum Clocks 24 32 32 48 56 64 88 Maximum User I/Os 158 242 290 344 454 562 712 JTAG ISP Yes Yes Yes Yes Yes Yes Yes PCI Yes Yes Yes Yes Yes Yes Yes TQFP 100, 144 100 - - - - - PQFP 208 208 208 208 208 208 208 PBGA - 456 456 456 456 456 456 FBGA 144 144, 256 144, 256 676, 896 896, 1152 Package (by pin count) December 2003 (c) 2003 Actel Corporation 144, 256, 484 256, 484, 676 i ProASICPLUS Flash Family FPGAs Ordering Information APA1000 _ FG F 1152 I Application (Ambient Temperature Range) Blank = Commercial (0 to +70 C) I = Industrial (-40 to +85 C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) Package Lead Count Package Type TQ = Thin Quad Flat Pack (1.4mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) BG = Plastic Ball Grid Array (1.27mm pitch) Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Plastic Device Resources User I/Os* Device TQFP 100-Pin TQFP 144-Pin PQFP 208-Pin APA075 66 107 158 APA150 66 PBGA 456-Pin FBGA 144-Pin FBGA 256-Pin FBGA 484-Pin FBGA 676-Pin FBGA 896-Pin FBGA 1152-Pin 100 158 242 100 186 APA300 158 290 100 186 APA450 158 344 100 186 344 APA600 158 356 186 370 APA750 158 356 APA1000 158 356 454 454 562 642 712 Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. General Guideline Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee performance beyond the limits specified within the datasheet. i -i i v3.4 ProASICPLUS Flash Family FPGAs Product Availability Speed Grade Application Std. -F* C I 100-Pin Thin Quad Flat Pack (TQFP) 144-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 144-Pin Fine Pitch Ball Grid Array (FBGA) 100-Pin Thin Quad Flat Pack (TQFP) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 144-Pin Fine Pitch Ball Grid Array (FBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 256-Pin Fine Pitch Ball Grid Array (FBGA) 484-Pin Fine Pitch Ball Grid Array (FBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 676-Pin Fine Pitch Ball Grid Array (FBGA) 896-Pin Plastic Ball Grid Array (FBGA) 208-Pin Plastic Quad Flat Pack (PQFP) 456-Pin Plastic Ball Grid Array (PBGA) 896-Pin Fine Pitch Ball Grid Array (FBGA) 1152-Pin Fine Pitch Ball Grid Array (FBGA) APA075 Device APA150 Device APA300 Device APA450 Device APA600 Device APA750 Device APA1000 Device Notes: *-F parts are only available as commercial temperature devices. Applications: C = Commercial I = Industrial Availability: = Available PP = Product Planned v3.4 i-iii ProASICPLUS Flash Family FPGAs Table of Contents General Guideline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii General Description ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Tristate Buffer Delays Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Recommended Design Practice for VPN/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Package Pin Assignments 100-Pin TQFP ....................................................... 1 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 iv v3.4 ProASICPLUS Flash Family FPGAs General Description The ProASICPLUS family of devices, Actel's second generation Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to 1 million system gates, supp/ +;,llorted with up to 198kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Embedded two-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depth and width. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at powerup. No external Boot PROM is required to support device programming. While on-board security mechanisms prevent all access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a costeffective solution for applications in the networking, communications, computing, and avionics markets. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0, 90, 180, 270), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22m LVCMOS process with four-layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance fully compatible with gate arrays. To support customer needs for more comprehensive, lower cost board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" on page 1-10. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The ProASICPLUS devices are available in a variety of highperformance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections. v3.4 1-1 ProASICPLUS Flash Family FPGAs ProASICPLUS Architecture The proprietary ProASICPLUS architecture granularity comparable to gate arrays. Flash Switch provides The ProASICPLUS device core consists of a Sea-of-TilesTM (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 1-2 on page 1-3 and Figure 1-3 on page 1-3). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see the "Embedded Memory Configurations" on page 1-20 for more information. Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 1-2 on page 1-3). Logic Tile The logic tile cell (Figure 1-3 on page 1-3) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. RAM Block 256x9 Two-Port SRAM or FIFO Block I/Os Logic Tile RAM Block 256x9 Two Port SRAM or FIFO Block Figure 1-1 * The ProASICPLUS Device Architecture 1- 2 v3.4 ProASICPLUS Flash Family FPGAs Floating Gate Sensing Switch In Switching Word Switch Out Figure 1-2 * Flash Switch Local Routing In 1 Efficient Long-Line Routing In 2 (CLK) In 3 (Reset) Figure 1-3 * Core Logic Tile Routing Resources drive signals onto the efficient long-line resources, which can in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible fourlevel hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high speed very long-line resources, and high performance global networks. The high-speed very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 1-6 on page 1-5). The high-performance global networks are low skew, high fanout nets that are accessible from external pins or from internal logic (Figure 1-7 on page 1-6). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 1-4 on page 1-4). The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 1-5 on page 1-4). Each tile can v3.4 1-3 ProASICPLUS Flash Family FPGAs L Inputs L L L Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) Output L L L L L Figure 1-4 * Ultra-Fast Local Resources Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Logic Tile L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Logic Cell L L L L Figure 1-5 * Efficient Long-Line Resources 1- 4 v3.4 L L ProASICPLUS Flash Family FPGAs High Speed Very Long-Line Resouces PAD RING I/O RING I/O RING PAD RING SRAM SRAM PAD RING Figure 1-6 * High Speed Very Long-Line Resources ProASICPLUS offers four global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 1-7 on page 1-6). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1-1 on page 1-6. Clock Resources The ProASICPLUS family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), clock multiplier/ dividers and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" on page 1-11. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock-resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high-fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note. Clock Trees One of the main architectural benefits of ProASICPLUS is the set of power and delay friendly global networks. v3.4 1-5 ProASICPLUS Flash Family FPGAs High Performace Global Network I/O RING PAD RING PAD RING Top Spine Global Networks Global Pads Global Pads Global Spine Bottom Spine I/O RING Global Ribs Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING Note: This figure shows routing for only one global path. Figure 1-7 * High Performance Global Network Table 1-1 * Clock Spines Global Clock Networks (Trees) APA075 APA150 APA300 APA450 APA600 APA750 APA1000 4 4 4 4 4 4 4 Clock Spines/Tree 6 8 8 12 14 16 22 Total Spines 24 32 32 48 56 64 88 Top or Bottom Spine Height (Tiles) 16 24 32 32 48 64 80 Tiles in Each Top or Bottom Spine 512 768 1,024 1,024 1,536 2,048 2,560 3,072 6,144 8,192 12,288 21,504 32,768 56,320 Total Tiles Array Coordinates During many place-and-route operations in Actel's Designer software tool, it is possible to set constraints that require array coordinates. Table 1-2 on page 1-7 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups, designated by a wildcard, and containing core cells, I/Os, and memories. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O 1- 6 v3.4 cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (1,1) or (1,5) if memories are present at the bottom. Memory coordinates use the same system and are indicated in Table 1-2 on page 1-7. The memory coordinates for an APA1000 are illustrated in Figure 1-8 on page 1-7. For more information on how to use constraints, see the Designer User's Guide or online help for ProASICPLUS software tools. ProASICPLUS Flash Family FPGAs Table 1-2 * Array Coordinates Logic Tile Min. Memory Rows Max. Bottom Top All Device x y x y y y Min. Max. APA075 1 1 96 32 - (33,33) or (33, 35) 0,0 97, 37 APA150 1 1 128 48 - (49,49) or (49, 51) 0,0 129, 53 APA300 1 5 128 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 129, 73 APA450 1 5 192 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 193, 73 APA600 1 5 224 100 (1,1) or (1,3) (101,101) or (101, 103) 0,0 225, 105 APA750 1 5 256 132 (1,1) or (1,3) (133,133) or (133, 135) 0,0 257, 137 APA1000 1 5 352 164 (1,1) or (1,3) (165,165) or (165, 167) 0,0 353, 169 (1,169) Memory Blocks (353,169) (1,167) (352,167) (1,165) (352,165) (1,164) (352,164) Core (1,5) (352,5) (1,3) (352,3) (1,1) (352,1) (0,0) Memory Blocks (353,0) Figure 1-8 * Core Cell Coordinates for the APA1000 v3.4 1-7 ProASICPLUS Flash Family FPGAs Input/Output Blocks To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. If the I/O pad power supply (VDDP) is 3.3V, each I/O can be selectively configured at the 2.5V and 3.3V threshold levels1. Table 1-3 shows the available supply voltage configurations (the PLL block uses an independent 2.5V supply on the AVDD and AGND pins). All I/Os include ESD protection circuits. Each I/O has been tested to 2000V to the human body model (per JESD22 (HBM)). Six or seven standard I/O pads are grouped with a GND pad and either a VDD (core power) or VDDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers, while the other creates a virtual VDD supply for the I/O ring. I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 1-9 and Table 1-4). 3.3V/2.5V Signal Control Table 1-3 * ProASICPLUS I/O Power Supply Voltages VDDP Input Compatibility Output Drive Y 2.5V 3.3V 2.5V 3.3V, 2.5V 2.5V 1 Pull-up Control EN 3.3V, 2.5V A Note: VDD is always 2.5V. Pad 3.3V/2.5V Signal Control Drive Strength and Slew-Rate Control 1. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for details. Figure 1-9 * I/O Block Schematic Representation Table 1-4 * I/O Features Function Description I/O pads configured as inputs * Individually selectable 2.5V or 3.3V threshold levels * Optional pull-up resistor * Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities. * 3.3V PCI Compliant * Individually selectable 2.5V or 3.3V compliant output signals I/O pads configured as outputs * 2.5V - JEDEC JESD 8-5 * 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates * Tristate I/O pads configured as bidirectional * buffers * 1- 8 Individually selectable 2.5V or 3.3V compliant output signals 2.5V - JEDEC JESD 8-5 * 3.3V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3V PCI compliant * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates * Tristate v3.4 ProASICPLUS Flash Family FPGAs Power-Up Sequencing low voltage differential amplifier) and a signal and its complement, PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. While ProASICPLUS devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up before (or coincident with) VDDP on ProASICPLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel's ProASICPLUS Family Devices Power-Up Behavior application note. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 1-10. The LVPECL pad cell compares voltages, as illustrated in Figure 1-11, on the PPECL (I/P) pad and the NPECL pad and sends the results to the global MUX (Figure 1-14 on page 1-13). This high speed, low skew output essentially controls the clock conditioning circuit. LVPECL Input Pads In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 1-5). Z 0= 50 PPECL + From LVPECL Driver R = 100 Z 0= 50 Data _ NPECL Figure 1-10 * Recommended Termination for LVPECL Inputs Voltage 2.72 2.125 1.49 0.86 Figure 1-11 * LVPECL High and Low Threshold Values Table 1-5 * LVPECL Receiver Specifications Symbol Parameter Min. Max Units VIH Input High Voltage 1.49 2.72 V VIL Input Low Voltage 0.86 2.125 V VID Differential Input Voltage 0.3 VDD V v3.4 1-9 ProASICPLUS Flash Family FPGAs Boundary Scan (JTAG) operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20k pull-up resistor is added to TDO and TCK pins. ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 1-12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 1-6). The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 1-13 on page 1-11. The '1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to partial programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 1-12 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Table 1-6 * Boundary-Scan Opcodes The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. Hex Opcode EXTEST 00 SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF 1- 1 0 ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary v3.4 ProASICPLUS Flash Family FPGAs scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out 1 Test-Logic Reset 0 0 Run-Test/ Idle 1 1 Select-DRScan 0 Scan 0 Capture-DR 1 Capture-IR 1 0 0 0 Shift-DR 0 0 1 1 Exit-IR 0 Pause-DR Exit2-DR 1 Update-DR 0 1 1 0 Pause-IR 1 1 0 0 Shift-IR 1 Exit-DR 1 Select-IR- 0 Exit2-IR 1 Update-IR 0 1 Figure 1-13 * TAP Controller State Diagram Timing Control and Characteristics ProASICPLUS Clock Management System * Clock Frequency Synthesis Each PLL has the following key features: Introduction ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions: * * Clock Phase Adjustment via Programmable Delay (250 ps steps from -8 ns to +8 ns) Clock Skew Minimization * Input Frequency Range (fIN) = 1.5 to 180 MHz * Feedback Frequency Range (fVCO) = 1.5 to 180 MHz * Output Frequency Range (fOUT) = 6 to 180 MHz * Output Phase Shift = 0 , 90 , 180 , and 270 * Output Duty Cycle = 50% * Low Output Jitter (max at 25C) - v3.4 fVCO <10 MHz. Jitter 1% or better 1-11 ProASICPLUS Flash Family FPGAs - 10 MHz < fVCO < 60 MHz. Jitter 2% or better - fVCO > 60 MHz. Jitter 1% or better Note: Jitter(ps) = Jitter(%)*(10/Frequency (MHz) For Example: Jitter in picoseconds at 1 MHz = 1(%)*(10/1 (MHz)) = 10ps * Maximum Acquisition Time = 80s * Low Power Consumption - 6.9 mW (max - analog supply) + 7.0W/MHz (max - digital supply) * The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. * The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle. * The output frequency of the PLL core is given by the following formula (fREF is the reference clock frequency): Physical Implementation fOUT = fREF * m/n Each side of the chip contains a clock conditioning circuit based upon a 180 MHz PLL block (Figure 1-14 on page 113). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The two signals available to drive the global networks are as follows (Figure 1-15 on page 1-14, Table 1-7 on page 114, and Table 1-8 on page 1-15): Global A (secondary clock) * Output from Global MUX A * Conditioned version of PLL output (fOUT) - delayed or advanced * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 * The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. The implementations: fGLB = m/(n*u) fGLA = m/(n*v) enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0, 90, 180, and 270. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work. Global B * Output from Global MUX B * Delayed or advanced version of fOUT * Divided version of either of the above * Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 Lock Signal Functional Description Each PLL block contains four programmable dividers as shown in Figure 1-14 on page 1-13. These allow frequency scaling of the input clock signal as follows: * The n divider divides the input clock by integer factors from 1 to 32. An active-high Lock signal (added via the ACTgen PLL development tool) indicates that the PLL has locked to the incoming clock signal. Users can employ the Lock signal as a soft reset of the logic driven by GLB and/or GLA. PLL Configuration Options The PLL can be configured during design (via Flashconfiguration bits set in the programming bitstream) or dynamically during device operation, thus eliminating the need for complete reprogramming. The dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit of 1. This mode is available through the delay feature of the Global MUX driver. 1- 1 2 v3.4 ProASICPLUS Flash Family FPGAs Actel's ProASICPLUS PLL Dynamic Reconfiguration Using JTAG application note for more information. each PLL and then latched into the PLL block. The JTAG ports can be used along with a built-in user JTAG interface hardware to load the configuration shift register externally. Another option is internal dynamic configuration via user-designed hardware. Refer to For information on the clock conditioning circuit, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note.. AVDD AGND VDD GND GLA Global MUX B OUT Input Pins to the PLL See Figure 15 + on page 15 - External Feedback Signal Clock Conditioning Circuitry (Top level view) GLB 27 4 Global MUX A OUT 8 Flash Configuration Bits Dynamic Configuration Bits Clock Conditioning Circuitry Detailed Block Diagram CLK Bypass Primary 1 P+ OBMUX[2:0] FIVDIV[4:0] P- /n 270 180 90 0 PLL Core /m FBDIV[5:0] Clock from Core (GLINT mode) 0 /u DLYB[1:0] Delay Line 0.0ns, 0.25ns, GLB 0.50ns and 4.00ns OBDIV[1:0] 2 1 Delay Line 0.25ns to 4.00ns, 16 steps, 0.25ns increments 0 1 EXTFB 7 6 5 4 XDLYSEL Deskew Delay 2.95 ns 2 3 FBDLY[3:0] FBSEL[1:0] 3 OADIV[1:0] 2 /v Delay Line 0.0ns, 0.25ns, GLA 0.50ns and 4.00ns DLYA[1:0] 1 OAMUX[1:0] CLKA Bypass Secondary Clock from Core (GLINT mode) 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA, DLYB, DLYAFB are programmable delay lines, each with selectable values 0, 250 ps, 500 ps, and 4 ns. 3. OBDIV will also divide the phase-shift since it takes place after the PLL Core. Figure 1-14 * PLL Block - Top-Level View and Detailed PLL Block Diagram v3.4 1-13 ProASICPLUS Flash Family FPGAs Package Pins GL Physical I/O Buffers Global MUX Configuration Tile Std. Pad Cell Global MUX B OUT NPECL PECL Pad Cell PPECL External Feedback GLMX Std. Pad Cell GL Std. Pad Cell Global MUX A OUT Configuration Tile CORE Legend Physical Pin DATA Signals to the Global MUX DATA Signals to the Core Control Signals to the Global MUX DATA Signals to the PLL Block Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 1-15 * Input Connectors to ProASICPLUS Clock Conditioning Circuitry Table 1-7 * Clock-Conditioning Circuitry MUX Settings MUX Datapath Comments FBSEL 1 Internal Feedback 2 Internal Feedback and Advance Clock Using FBDLY 3 External Feedback (EXTFB) -0.25 to -4 ns in 0.25ns increments XDLYSEL 0 Feedback Unchanged 1 Deskew feedback by advancing clock by system delay OBMUX GLB 0 Primary bypass, no divider 1 Primary bypass, use divider 2 Delay Clock Using FBDLY 4 Phase Shift Clock by 0 5 Phase Shift Clock by +90 6 Phase Shift Clock by +180 7 Phase Shift Clock by +270 OAMUX +0.25 to +4 ns in 0.25ns increments GLA 0 Secondary bypass, no divider 1 Secondary bypass, use divider 2 Delay Clock Using FBDLY 3 Phase Shift Clock by 0 1- 1 4 Fixed delay of -2.95 ns +0.25 to +4 ns in 0.25ns increments v3.4 ProASICPLUS Flash Family FPGAs Clock Skew Minimization Table 1-8 * Clock-Conditioning Circuitry Delay-Line Settings Delay Line Delay Value (ns) Figure 1-20 on page 1-18 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the "input" clock. The input clock is fed to the reference clock input of the PLL. The output clock (GLA) feeds a clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note for more information. DLYB 0 0 1 +0.25 2 +0.50 3 +4.0 DLYA 0 0 1 +0.25 2 +0.50 3 +4.0 Logic Tile Timing Characteristics Timing characteristics for ProASICPLUS devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or performing simulation with post-layout delays. Sample Implementations Frequency Synthesis Figure 1-16 on page 1-16 illustrates an example where the PLL is used to multiply a 33 MHz external clock up to 133 MHz. Figure 1-17 on page 1-16 uses two dividers to synthesize a 50 MHz output clock from a 40 MHz input reference clock. The input frequency of 40 MHz is multiplied by 5 and divided by 4, giving an output clock (GLB) frequency of 50 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. For example, in this case the input divider could have been 2 and the output divider also 2, giving us a division of the input frequency by 4 to go with the feedback loop division (effective multiplication) by 5. Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are determined by net property assignment prior to placement and routing. Refer to the Actel Designer User's Guide or online help for details on using constraints. Adjustable Clock Delay Timing Derating Figure 1-18 on page 1-17 illustrates the delay of the input clock by employing one of the adjustable delay lines. This is easily done in ProASICPLUS by bypassing the PLL core entirely and using the output delay line. Notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. This is shown in Figure 1-19 on page 1-17. Since ProASICPLUS devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). Critical Nets and Typical Nets v3.4 1-15 ProASICPLUS Flash Family FPGAs Global MUX B OUT 33 MHz /1 /n 270 180 90 0 PLL Core /m /4 /u /1 D GLB 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-16 * Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz /4 /n 270 180 90 0 PLL Core /m /5 /u /1 GLB D 50 MHz D D External Feedback /v Global MUX A OUT Figure 1-17 * Using the PLL 40 MHz In, 50 MHz Out 1- 1 6 v3.4 D GLA ProASICPLUS Flash Family FPGAs Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u /1 GLB D 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-18 * Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u /1 GLB D 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-19 * Using the PLL to "Advance" the Input Clock v3.4 1-17 ProASICPLUS Flash Family FPGAs Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u D GLB /1 D D External Feedback /v Global MUX A OUT Q Q SET D CLR Figure 1-20 * Using the PLL for Clock De-Skewing 1- 1 8 v3.4 133 MHz D GLA ProASICPLUS Flash Family FPGAs PLL Electrical Specifications Parameter Value Notes Reference Frequency fIN (min.) 1.5 MHz Clock conditioning circuitry (min.) lowest input frequency Reference Frequency fIN (max.) 180 MHz Clock conditioning circuitry (max.) highest input frequency OSC Frequency fVCO (min.) 24 MHz Lowest output frequency voltage controlled oscillator OSC Frequency fVCO (max.) 180 MHz Highest output frequency voltage controlled oscillator Frequency Ranges Clock Conditioning Circuitry fOUT (min.) 6 MHz Lowest output frequency clock conditioning circuitry Clock Conditioning Circuitry fOUT (max.) 180 MHz Highest output frequency clock conditioning circuitry Long Term Jitter Peak-to-Peak Max.* Temperature 25C (or higher) Frequency MHz fVCO<10 10<fVCO<60 fVCO>60 1% 2% 1% Jitter(ps) = Jitter(%)*(10/Frequency (MHz) For Example: Jitter in picoseconds at 1 MHz = 1(%)*(10/1 (MHz)) = 10ps 0C 1.5% 2.5% 1% -40C 2.5% 3.5% 1% Acquisition Time from Cold Start Acquisition Time (max.) 30 s fVCO 40 MHz Acquisition Time (max.) 80 s fVCO > 40 MHz Power Consumption Analog Supply Power (max*) 6.9 mW Digital Supply Current (max) 7 W/MHz Duty Cycle 50% 0.5% Note: *High clock frequencies (>60 MHz) TM User Security Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. PLUS ProASIC devices have FlashLock protection bits that, once programmed, block the entire programmed contents from being read externally. If locked, the user can only reprogram the device employing the userdefined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (which are actually very small capacitors), rather than in the wiring, physical deconstruction cannot be used to compromise data. This approach is further hampered by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Embedded Memory Floorplan The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1-1 on page 1-2). Depending upon the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory or combined (using dedicated memory routing resources) to form larger, more complex memories. A single memory configuration could include blocks from both the top and bottom memory locations. v3.4 1-19 ProASICPLUS Flash Family FPGAs Embedded Memory Configurations Each block contains a 256 word, 9-bit wide (1 read port, 1 write port) memory. The memory blocks may be combined in parallel to form wider memories or stacked to form deeper memories (Figure 1-23 on page 1-23). This provides optimal bit widths of 9 (1 block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel's A Guide to ACTgen Macros for more information. The embedded memory in the ProASICPLUS family provides great configuration flexibility (Table 1-9 on page 1-20). Unlike many other programmable vendors each ProASICPLUS block is designed and optimized as a two-port memory (1 read, 1 write). This provides 198kbits of total memory for two-port and single port usage in the APA1000 device. Figure 1-24 on page 1-24 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three memories of various widths and depths. Figure 1-25 on page 1-24 shows how memory can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port memories. The Actel ACTgen software facilitates building wider and deeper memories for optimal memory usage. Each memory can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 1-10). Additional characteristics include programmable flags as well as parity checking and generation. Figure 1-21 on page 121 and Figure 1-22 on page 1-22 show the block diagrams of the basic SRAM and FIFO blocks. Table 1-11 on page 1-22 and Table 1-12 on page 1-23 describe memory block SRAM and FIFO interface signals, respectively. A single memory is designed to operate at up to 150 MHz (standard speed grade typical conditions). Table 1-9 * ProASICPLUS Memory Configurations by Device Maximum Width Maximum Depth Device Bottom Top D W D W APA075 0 12 256 108 1,536 9 APA150 0 16 256 144 2,048 9 APA300 16 16 256 144 2,048 9 APA450 24 24 256 216 3,072 9 APA600 28 28 256 252 3,584 9 APA750 32 32 256 288 4,096 9 APA1000 44 44 256 396 5,632 9 Table 1-10 * Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256x9AST RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256x9AA 1- 2 0 v3.4 ProASICPLUS Flash Family FPGAs Table 1-10 * Basic Memory Configurations (Continued) Type Write Access Read Access Parity Library Cell Name FIFO Asynchronous Asynchronous Generated FIFO256x9AAP FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256x9SAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP DI <0:8> WADDR <0:7> WRB WBLKB WCLKS SRAM (256 X 9) Sync Write & Sync Read Ports DO <0:8> RADDR <0:7> DI <0:8> WADDR <0:7> RDB RBLKB RCLKS WRB WBLKB WPE RPE WPE PARODD DI <0:8> WADDR <0:7> WRB WBLKB WCLKS SRAM (256 X 9) Sync Write & Async Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE PARODD DO <0:8> RADDR <0:7> DI <0:8> WADDR <0:7> WRB WBLKB RDB RBLKB RPE WPE SRAM (256 X 9) Async Write & Async Read Ports SRAM (256 X 9) Async Write & Sync Read Ports RDB RBLKB RCLKS RPE WPE PARODD DO <0:8> RADDR <0:7> PARODD Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 1-21 * Example SRAM Block Diagrams v3.4 1-21 ProASICPLUS Flash Family FPGAs Table 1-11 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 IN Write clock used on synchronization on write side RCLKS 1 IN Read clock used on synchronization on read side RADDR<0:7> 8 IN Read address RBLKB 1 IN Read block select (active LOW) RDB 1 IN Read pulse (active LOW) WADDR<0:7> 8 IN Write address WBLKB 1 IN Write block select (active LOW) DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in WRB 1 IN Write pulse (active LOW) DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out RPE 1 OUT Read parity error (active HIGH) WPE 1 OUT Write parity error (active HIGH) PARODD 1 IN Selects odd parity generation/detect when high, even when low Note: Not all signals shown are used in all modes. DI<0:8> DI<0:8> LEVEL<0:7> LGDEP<0:2> WRB WBLKB RDB FIFO (256 X 9) Sync Write & Sync Read Ports RBLKB WPE WRB WBLKB RPE FULL EMPTY RDB GEQTH WCLKS RESET RESET RCLKS DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB RDB RBLKB PARODD DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB DO <0:8> FIFO (256 X 9) Async Write & Sync Read Ports WPE RPE FULL EMPTY EQTH PARODD GEQTH WCLKS FIFO (256 X 9) Sync Write & Async Read Ports RBLKB EQTH PARODD DO <0:8> LEVEL<0:7> LGDEP<0:2> DO <0:8> WPE RPE FULL EMPTY EQTH RDB RBLKB GEQTH RESET PARODD RCLKS DO <0:8> FIFO (256 X 9) Async Write & Async Read Ports WPE RPE FULL EMPTY EQTH GEQTH RESET Note: To save area while using embedded memories, the memory blocks contain multiplexers (called DMUX) for each output signal. These DMUX cells do not consume any core logic tiles and connect directly to high speed routing resources between the memory blocks. They are used when memories are cascaded and are automatically inserted by the software tools. Figure 1-22 * Basic FIFO Block Diagrams 1- 2 2 v3.4 ProASICPLUS Flash Family FPGAs Table 1-12 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 IN Write clock used for synchronization on write side RCLKS 1 IN Read clock used for synchronization on read side LEVEL <0:7> 8 IN Direct configuration implements static flag logic RBLKB 1 IN Read block select (active LOW) RDB 1 IN Read pulse (active LOW) RESET 1 IN Reset for FIFO pointers (active LOW) WBLKB 1 IN Write block select (active LOW) DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Write pulse (active LOW) FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 OUT EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error (active HIGH) WPE 1 OUT Write parity error (active HIGH) LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 IN Parity generation/detect - Even when low, odd when high 9 Word Width 9 9 9 9 256 9 9 9 Word Depth 256 9 256 256 256 256 256 256 256 88 blocks Figure 1-23 * APA1000 Memory Block Architecture v3.4 1-23 ProASICPLUS Flash Family FPGAs Word Width Word Depth 9 9 9 256 256 256 256 256 256 9 9 256 256 256 words x 18 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 1-24 * Example Showing Memories with Different Widths and Depths Word Width 9 Word Depth 99 9 9 9 Write Port 9 9 Write Port 9 256 256 256 256 256 256 Read Ports 256 256 256 256 256 words x 9 bits, 2 read, 1 write Read Ports 512 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 1-25 * Multiport Memory Usage Design Environment The ProASICPLUS family of FPGAs is fully supported by both Actel's LiberoTM Integrated Design Environment (IDE) and Actel's Designer FPGA Development Software. Actel's Designer software provides a comprehensive suite of backend development tools for FPGA development. The Designer software includes timing-driven place-androute, a world-class integrated static timing analyzer and constraints editor, a design netlist schematic viewer, and SmartPower, a tool that allows the user to quickly estimate the power consumption in a design. 1- 2 4 v3.4 Libero IDE provides an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools (Figure 1-26 on page 1-25). Libero IDE includes Synplicity(R) Synplify AE for Actel, Mentor GraphicsTM ViewDraw AE for Actel, Actel's own Designer software, Model TechnologyTM ModelSim AE HDL Simulator, and SynaptiCADTM WaveFormer Lite AE. ProASICPLUS Flash Family FPGAs ISP the In-System Programming ProASICPLUS Devices and Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/ Os are inputs with pull-ups. The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be programmed in system. For more information on ISP of ProASICPLUS devices, refer to Libero IDE Design Flow TM Design Creation/Verification ACTgen Macro Builder HDL Editor WaveFormer LiteTM Testbench User Testbench Stimulus Generation R Synplify Synthesis Synthesis Libraries Functional Simulation Design Synthesis and Optimization R ViewDraw Schematic Entry ModelSim Simulator R Timing Simulation Design Implementation MultiView Navigator Compile Timer I/O Assignments Optimization and DRC Static Timing Analysis and Constraints Editor ChipPlanner or ChipEditor Floorplanning Layout PinEditor I/O Attribute Editor Select I/O Standards Timing Driven Place-and-Route NetlistViewer Back-Annotate Fuse or Bitstream Design Schematic Viewer Silicon Sculptor Back-Annotation Timing for Simulation Cross-Probing System Verification Programming (Antifuse and Flash Families) SmartPower Power Analysis Actel Device Silicon Explorer II (Antifuse Families) FlashPro (Flash Families) FlashPro Lite (ProASIC PLUS Family) BP Microsystems Programmers Figure 1-26 * Design Flow v3.4 1-25 ProASICPLUS Flash Family FPGAs Related Documents Application Notes Efficient Use of ProASIC Clock Trees http://www.actel.com/documents/clocktree.pdf I/O Features in ProASICPLUS Flash FPGAs http://www.actel.com/documents/PAPLUSLVPECL.pdf ProASICPLUS Family Devices Power-Up Behavior http://www.actel.com/documents/PAPLUS_PowerUp.pdf ProASICPLUS PLL Dynamic Reconfiguration Using JTAG http://www.actel.com/documents/ PAPLUSPLLdynamicAN.pdf Using ProASICPLUS Clock Conditioning Circuits http://www.actel.com/documents/PAPLUSPLLan.pdf In-System Programming ProASICPLUS Devices http://www.actel.com/documents/External_ISP_AN.pdf Performing Internal In-System Programming Using Actel's ProASICPLUS Devices http://www.actel.com/documents/PAplusISPAN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity.pdf User's Guide Designer User's Guide http://www.actel.com/documents/designerUG.pdf Flash Macro Library Guide http://www.actel.com/documents/PA_libguide.pdf 1- 2 6 v3.4 ProASICPLUS Flash Family FPGAs Package Thermal Characteristics A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. T J - TA P = -----------------ja ja is a function of the rate (in linear feet per minute - lfpm) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. Table 1-13 * Package Thermal Characteristics Pin Count jc ja Still Air ja 300 ft./ min. Units Thin Quad Flat Pack (TQFP) 100 12 37.5 30 C/W Thin Quad Flat Pack (TQFP) 144 11 32 24 C/W Plastic Quad Flat Pack (PQFP) 208 8 30 23 C/W PQFP with Heatspreader 208 3.8 20 17 C/W Plastic Ball Grid Array (PBGA) 456 3 15.6 12 C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 C/W Fine Pitch Ball Grid Array (FBGA) Package Type 256 3.8 25 22 C/W 1 Fine Pitch Ball Grid Array (FBGA) 484 3.2 20 15 C/W Fine Pitch Ball Grid Array (FBGA)2 484 3.2 20.5 16.6 C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 11.5 C/W Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.3 C/W Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12 8.9 C/W Notes: 1. Depopulated Array 2. Full Array v3.4 1-27 ProASICPLUS Flash Family FPGAs Calculating Typical Power Dissipation where: ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Ptotal = Pdc + Pac Pdc = Pac = 1.4 W/MHz, is the average power consumption of a logic tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * mc = the number of logic tiles switching during each Fs cycle * Fs = the clock frequency 12.5 mW (Typically 2.5V x 5mA) Poutputs = (P4 + (Cload * VDDP2)) * p * Fp Pdc includes the static components of: PVDDP + PVDD + PAVDD * P3 = Poutputs, the I/O component of AC power dissipation, is given by where: * * where: Pclock + Pstorage + Plogic + Pinputs + Poutputs + Pmemory + Ppll Pclock, the clock component of power dissipation, is given by * P4 = 326 W/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current VDD + VDDP * Cola = the output load * p * Fp = Pclock = (P1 + P2 * R - P7*R2) * Fs d where: * P1 = 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock * P2 = 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the clock = The input's component of AC power dissipation is given by Pinputs = P8 * q * Fq where: * P7 = 0.00003 W/MHz is a correction factor for highly loaded clock-trees * R the number of storage tiles clocked by this clock * q the clock frequency * Fq = * = Fs = * P8 = Pstorage = P5 * ms * Fs = 1.1 W/MHz is the average power consumption of a storage-tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2 * ms = the number of storage tiles (Register) switching during each Fs cycle * Fs = the clock frequency W/MHz is the intrinsic power consumption of an the number of inputs the average input frequency Ppll = P9 * Npll where: * P9 = 7.5 mW. This value has been estimated at maximum PLL clock frequency * NPl = number of PLLs used where: P5 = 29 input pad normalized per MHz of the input frequency Pstorage, the storage-tile (Register) component of AC power dissipation, is given by * the number of outputs the average output frequency Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmemory * Fmemory * Ememory where: * P6 = * Nmemory = Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs 1- 2 8 v3.4 175 W/MHz is the average power consumption of a memory block per MHz of the clock the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) ProASICPLUS Flash Family FPGAs * Fmemory = the clock frequency of the memory * Ememory = the average number of active blocks divided by the total number of blocks (N) of the memory. * * Plogic * => Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory In addition, an applicationdependent component to Ememory can be considered. For example, for a 1kx8 memory using only 1 cycle out of 3, Ememory = 1/4*1/3 = 1/12 Cload = 40 pF * VDDP = 3.3 V * p = 24 * Fp = 5 MHz Poutputs = (P4 + Cload * VDDP2) * p * Fp = 87.3 mW Pinputs * q = 1 * Fq = 10 MHz => Pinputs = P8 * q * Fq = 0.3 mW Pmemory * sF = 10 MHz * R Nmemory = 13,440 => = 0 (no RAM/FIFO in this shift-register) Pmemory = 0 mW Pac 2 Pclock = (P1 + P2 * R - P7*R ) * Fs = 124.2 mW => Pstorage => * => Pclock * Plogic = 0 mW Poutputs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: => m c = 0 (no logic tile in this shift-register) 360 mW Ptotal ms= 13,440 (in a shift register 100% of storagetiles are toggling at each clock cycle and Fs = 10 MHz) Pdc + Pac = 372 mW (Typical) Pstorage = P5 * ms * Fs = 147.8 mW v3.4 1-29 ProASICPLUS Flash Family FPGAs Operating Conditions Standard and -F parts are the same unless otherwise noted. -F parts are only available as commercial. Table 1-14 * Absolute Maximum Ratings* Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD) -0.3 3.0 V Supply Voltage I/O Ring (VDDP) -0.3 4.0 V DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -1.0 VDDP + 1.0 V PCI DC Input Clamp Current (absolute) VIN < -1 or VIN = VDDP + 1V LVPECL Input Voltage GND 10 mA -0.3 VDDP + 0.5 V 0 0 V Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-15 * Programming, Storage and Operating Limits Storage Temperature Operating Programming Cycles Program Retention Min. Max. TJ Max Junction Temperature Commercial 500 20 years -55C 110C 110C Industrial 500 20 years -55C 110C 110C Product Grade Note: This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. Table 1-16 * Supply Voltages Mode VDD VDDP Single Voltage 2.5V 2.5V Mixed Voltage* 2.5V 3.3V Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for more information. Table 1-17 * Recommended Maximum Operating Conditions Programming and PLL Supplies Commercial/Industrial Parameter VPP Condition Maximum Units 15.8 16.5 V 0 16.5 V -13.8 -13.2 V During Programming Normal Operation VPN Minimum 1 During Programming Normal Operation 2 0 V IPP During Programming -13.8 25 mA IPN During Programming 10 mA AVDD VDD VDD V AGND GND GND V Notes: 1. Please refer to the "VPP Programming Supply Pin" on page 1-64 for more information. 2. Please refer to the "VPN Programming Supply Pin" on page 1-64 for more information. 1- 3 0 v3.4 ProASICPLUS Flash Family FPGAs Table 1-18 * Recommended Operating Conditions Limits Parameter Symbol Commercial Industrial VDD & VDDP 2.5V 0.2V 2.5V 0.2V VDDP VDD 3.3V 0.3V 2.5V 0.2V 3.3V 0.3V 2.5V 0.2V Operating Ambient Temperature Range TA 0C to 70C -40C to 85C Maximum Operating Junction Temperature TJ 110C 110C DC Supply Voltage (2.5V I/Os) DC Supply Voltage (2.5V, 3.3V I/Os*) PLUS Note: *Please refer to the mixed-mode interfacing section in the I/O Features in ProASIC information. Flash FPGAs application note for more Table 1-19 * DC Electrical Specifications (VDDP = 2.5V 0.2V)1 Commercial / Industrial1,2 Symbol Parameter Conditions Min. VOH Output High Voltage High Drive (OB25LPH) IOH = -6 mA IOH = -12 mA IOH = -24 mA 2.1 2.0 1.7 Low Drive (OB25LPL) IOH = -3 mA IOH = -6 mA IOH = -8 mA 2.1 1.9 1.7 VOL Output Low Voltage High Drive (OB25LPH) Low Drive (OB25LPL) Typ. Max. Units V IOL = 8 mA IOL = 15 mA IOL = 24 mA 0.2 0.4 0.7 IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 V VIH Input High Voltage 1.7 VDDP + 0.3 V VIL Input Low Voltage -0.3 0.7 V 6 56 k 0.45 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) VIN 1.25V HYST Input Hysteresis Schmitt See Table 1-4 on page 1-8 IIN Input Current with pull up (VIN = GND) -240 - 20 A without pull up (VIN = GND or VDD) -10 10 A IDDQ IDDQ Quiescent Supply Current (standby) Commercial VIN = GND3 or VDD Quiescent Supply Current (standby) Industrial VIN = GND3 or VDD 0.3 0.35 Std. 5.0 15 mA -F 5.0 25 mA Std. 5.0 20 mA Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. v3.4 1-31 ProASICPLUS Flash Family FPGAs Table 1-19 * DC Electrical Specifications (VDDP = 2.5V 0.2V)1 (Continued) Commercial / Industrial1,2 Symbol Parameter Conditions IOZ 3-State Output Leakage Current VOH = GND or VDD Min. IOSL Max. Units Std. -10 10 A 4 -10 100 A -F IOSH Typ. mA Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS VIN = VSS Low Drive (OB25LPL) -120 -100 mA Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP VIN = VDDP Low Drive (OB25LPL) 100 30 CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. No pull-up resistor. 4. This will not exceed 2mA total per device. 1- 3 2 v3.4 ProASICPLUS Flash Family FPGAs Table 1-20 * DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1 Commercial / Industrial1,2 Symbol Parameter Conditions Min. VOH Output High Voltage IOH = -14 mA 3.3V I/O, High Drive (OB33P) IOH = -24 mA 0.9VDDP 2.4 IOH = -6 mA IOH = -12 mA 0.9VDDP 2.4 Typ. Max. Units V 3.3V I/O, Low Drive (OB33L) Output High Voltage 2.5V I/O, High (OB25H)3 IOH = -0.1 mA Drive IOH = -0.5 mA IOH = -3.0 mA 2.1 2.0 1.7 IOH = -0.1 mA IOH = -0.5 mA IOH = -1.0 mA 2.1 2.0 1.7 V 2.5V I/O, Low Drive (OB25L)3 VOL Output Low Voltage IOL = 15 mA 3.3V I/O, High Drive (OB33P) IOL = 20 mA IOL = 28 mA 0.1VDDP 0.4 0.7 V 3.3V I/O, Low Drive (OB33L) Output Low Voltage 2.5V I/O, High (OB25H)3 IOL = 7 mA IOL = 10 mA IOL = 15 mA 0.1VDDP 0.4 0.7 IOL = 7 mA Drive IOL = 14 mA IOL = 28 mA 0.2 0.4 0.7 IOL = 5 mA IOL = 10 mA IOL = 15 mA 0.2 0.4 0.7 V 2.5V I/O, Low Drive (OB25L)3 VIH VIL Input High Voltage 3.3V LVTTL/LVCMOS 2.5V Mode 2 1.7 VDDP + 0.3 VDDP + 0.3 Input Low Voltage 3.3V LVTTL/LVCMOS 2.5V Mode -0.3 -0.3 0.8 0.7 V Resistance VIN 1.5V 7 43 k Resistance VIN 1.5V 7 43 k with pull up (VIN = GND) -300 -40 A without pull up (VIN = GND or VDD) -10 10 A RWEAKPULLUP Weak Pull-up (IOB33U) RWEAKPULLUP Weak Pull-up (IOB25U) IIN Input Current V Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines and usage. 4. No pull-up resistor. 5. This will not exceed 2mA total per device. v3.4 1-33 ProASICPLUS Flash Family FPGAs Table 1-20 * DC Electrical Specifications (VDDP = 3.3V 0.3V and VDD 2.5V 0.2V)1 (Continued) Commercial / Industrial1,2 Symbol Parameter Conditions IDDQ Quiescent Supply Current (standby) Commercial VIN = GND4 or VDD IDDQ Quiescent Supply Current (standby) Industrial IOZ 3-State Current IOSH IOSL Output Min. Typ. Max. Units Std. 5.0 15 mA -F 5.0 25 mA VIN = GND4 or VDD Std. 5.0 20 mA Leakage VOH = GND or VDD Std. -10 10 A 4 -10 100 A -F Output Short Circuit Current VIN = GND High VIN = GND 3.3V High Drive (OB33P) 3.3V Low Drive (OB33L) VIN = GND VIN = GND 2.5V High Drive (OB25H)3 2.5V Low Drive (OB25L)3 -200 -100 mA -20 -10 Output Short Circuit Current VIN = VDD VIN = VDD Low 3.3V High Drive 3.3V Low Drive VIN = VDD VIN = VDD 2.5V High Drive3 2.5V Low Drive3 200 100 mA 200 100 CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. All process conditions. Junction Temperature: -40 to +110C. 2. -F parts are only available as commercial. 3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines and usage. 4. No pull-up resistor. 5. This will not exceed 2mA total per device. 1- 3 4 v3.4 ProASICPLUS Flash Family FPGAs Table 1-21 * DC Specifications (3.3V PCI Operation)1 Commercial / Industrial2,3 Symbol Parameter VDD Condition Min. Max. Units Supply Voltage for Core 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 V VIH Input High Voltage 0.5VDDP VDDP + 0.5 V VIL Input Low Voltage -0.5 0.3VDDP V IIPU Input Pull-up Voltage4 IIL 0.7VDDP 5 Input Leakage Current 0 < VIN < VCCI Std. -10 10 A 6 -10 100 A -F VOH Output High Voltage IOUT = -500 A VOL Output Low Voltage IOUT = 1500 A CIN Input Pin Capacitance (except CLK) CCLK CLK Pin Capacitance V 0.9VDDP 5 V 0.1VDDP V 10 pF 12 pF Notes: 1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. 2. All process conditions. Junction Temperature: -40 to +110C. 3. -F parts are available as commercial only. 4. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device. v3.4 1-35 ProASICPLUS Flash Family FPGAs Table 1-22 * AC Specifications (3.3V PCI Revision 2.2 Operation) Commercial / Industrial Symbol Parameter IOH(AC) Switching Current High Condition Min. 0 < VOUT 0.3VCCI* 0.3VCCI VOUT < 0.9VCCI 0.7VCCI < VOUT < VCCI IOL(AC) (Test Point) VOUT = 0.7VCC* Switching Current Low VCCI > VOUT * mA (-17.1 + (VDDP - VOUT)) mA See equation C - page 124 of the PCI Specification document rev. 2.2 -32VCCI 0.6VCCI* 1 mA (26.7VOUT) mA See equation D - page 124 of the PCI Specification document rev. 2.2 (Test Point) VOUT = 0.18VCC ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VCCI + 4 > VIN CCI + 1 slewF Output Fall Slew Rate 38VCCI -25 + (VIN + 1)/0.015 mA mA 25 + (VIN - VDDP - 1)/0.015 mA 0.2VCCI to 0.6VCCI load * 1 4 V/ns 0.6VCCI to 0.2VCCI load * 1 4 V/ns Note: * Refer to the PCI Specification document rev. 2.2. Pad Loading Applicable to the Rising Edge PCI pin 1/2 in. max output buffer 10 pF 1k Pad Loading Applicable to the Falling Edge PCI pin output buffer 1- 3 6 mA 16VDDP 0.18VCCI > VOUT > 0* Output Rise Slew Rate Units -12VCCI * 0.6VCCI > VOUT > 0.1VCCI slewR Max. 1k 10 pF v3.4 ProASICPLUS Flash Family FPGAs Tristate Buffer Delays EN A PAD OTBx A 50% 50% VOH PAD VOL EN EN 50% 50% tDLH 35pF tDHL 50% 50% VCC 50% PAD VOL tENZL 50% 50% VOH PAD GND 10% 90% 50% tENZH Figure 1-27 * Tristate Buffer Delays Table 1-23 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70C Max tDLH1 Max tDHL2 Max tENZH3 Macro Type Description STD -F STD -F STD OTB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 2.2 2.6 OTB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 2.4 OTB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 OTB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 OTB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 OTB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 OTB25HH OTB25HN OTB25HL OTB25LH OTB25LN OTB25LL OTB25LPHH OTB25LPHN OTB25LPHL OTB25LPLH OTB25LPLN OTB25LPLL 2.5V, High Output Current, High Slew Rate 5 2.5V, High Output Current, Nominal Slew Rate 2.5V, High Output Current, Low Slew Rate 5 2.5V, Low Output Current, High Slew Rate 5 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 5 5 5 2.5V, Low Power, High Output Current, High Slew Rate 6 2.5V, Low Power, High Output Current, Nominal Slew Rate 2.5V, Low Power, High Output Current, Low Slew Rate 6 2.5V, Low Power, Low Output Current, High Slew Rate 6 2.5V, Low Power, Low Output Current, Nominal Slew Rate 2.5V, Low Power, Low Output Current, Low Slew Rate 6 6 6 Max tENZL4 -F STD -F Units 2.0 2.4 ns 2.9 2.1 2.5 ns 2.7 3.3 2.8 3.4 ns 4.8 2.8 3.4 3.0 3.6 ns 4.3 5.2 3.2 3.8 4.1 4.9 ns 3.6 5.6 6.7 3.3 3.9 5.5 6.6 ns 3.1 3.8 1.8 2.2 2.8 3.4 1.7 2.0 ns 3.1 3.7 2.7 3.3 2.9 3.5 2.7 3.2 ns 3.1 3.7 3.9 4.7 2.9 3.5 3.8 4.6 ns 4.6 5.6 2.9 3.5 4.6 5.5 2.9 3.4 ns 4.6 5.6 3.7 4.5 4.6 5.5 3.6 4.3 ns 4.6 5.6 5.1 6.1 4.5 5.4 4.8 5.8 ns 2.0 2.4 2.1 2.5 2.3 2.7 2.0 2.4 ns 2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns 2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2 ns 2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1 ns 3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns 4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns Notes: 1. tDLH=Data-to-Pad HIGH 2. tDHL=Data-to-Pad LOW 3. tENZH=Enable-to-Pad, Z to HIGH 4. tENZL = Enable-to-Pad, Z to LOW 5. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines and usage. 6. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. v3.4 1-37 ProASICPLUS Flash Family FPGAs Output Buffer Delays A 50% 50% VOH 50% PAD 50% VOL tDLH tDHL PAD A 35pF OBx Figure 1-28 * Output Buffer Delays Table 1-24 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 70C Max tDLH1 Max tDHL2 Macro Type Description STD -F STD -F Units OB33PH 3.3V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 ns OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 ns OB33PL 3.3V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 ns OB33LH 3.3V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 ns OB33LN 3.3V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 ns OB33LL 3.3V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 ns 3.1 3.8 1.8 2.2 ns 3.1 3.7 2.7 3.3 ns 3.1 3.7 3.9 4.7 ns 4.6 5.6 2.9 3.5 ns 4.6 5.6 3.7 4.5 ns 4.6 5.6 5.1 6.1 ns 2.0 2.4 2.1 2.6 ns 2.4 2.9 3.0 3.6 ns 2.9 3.5 3.2 3.8 ns 2.7 3.3 4.6 5.5 ns 3.5 4.2 4.2 5.1 ns 4.0 4.8 5.3 6.4 ns OB25HH OB25HN 2.5V, High Output Current, High Slew Rate 3 2.5V, High Output Current, Nominal Slew Rate 3 OB25HL 2.5V, High Output Current, Low Slew Rate OB25LH 2.5V, Low Output Current, High Slew Rate3 OB25LN OB25LL 2.5V, Low Output Current, Nominal Slew Rate 2.5V, Low Output Current, Low Slew Rate 3 3 3 4 OB25LPHH 2.5V, Low Power, High Output Current, High Slew Rate OB25LPHN 2.5V, Low Power, High Output Current, Nominal Slew Rate4 OB25LPHL OB25LPLH 4 2.5V, Low Power, High Output Current, Low Slew Rate 2.5V, Low Power, Low Output Current, High Slew Rate 4 OB25LPLN 2.5V, Low Power, Low Output Current, Nominal Slew Rate OB25LPLL 2.5V, Low Power, Low Output Current, Low Slew Rate4 4 Notes: 1. tDLH = Data-to-Pad HIGH 2. tDHL = Data-to-Pad LOW 3. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines and usage. 4. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. 1- 3 8 v3.4 ProASICPLUS Flash Family FPGAs Input Buffer Delays VCC PAD Y PAD Y GND IBx 0V 50% 50% VCC 50% 50% t INYH tIN YL Figure 1-29 * Input Buffer Delays Table 1-25 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 70C Macro Type Description 3 Max. tINYH1 Max. tINYL2 Std. -F Std. -F Units IB25 2.5V, CMOS Input Levels , No Pull-up Resistor 0.7 0.9 0.8 1.0 ns IB25S 2.5V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger IB25LP IB25LPS 0.7 0.9 0.8 1.0 ns 3 0.9 1.1 0.6 0.8 ns 3 0.7 0.9 0.9 1.1 ns 3 2.5V, CMOS Input Levels , Low Power 2.5V, CMOS Input Levels , Low Power, Schmitt Trigger IB33 3.3V, CMOS Input Levels , No Pull-up Resistor 0.4 0.5 0.6 0.7 ns IB33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 0.6 0.7 0.8 0.9 ns Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. v3.4 1-39 ProASICPLUS Flash Family FPGAs Global Input Buffer Delays Table 1-26 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 70 Max. tINYH1 Macro Type Description GL25 GL25S GL25LP 2.5V, CMOS Input Levels3, No Pull-up Resistor Max. tINYL2 Std. -F Std. -F Units 1.3 1.6 1.0 1.2 ns 3 1.3 1.6 1.0 1.2 ns 3 1.1 1.2 1.0 1.3 ns 3 2.5V, CMOS Input Levels , No Pull-up Resistor, Schmitt Trigger 2.5V, CMOS Input Levels , Low Power GL25LPS 2.5V, CMOS Input Levels , Low Power, Schmitt Trigger 1.3 1.6 1.0 1.1 ns GL33 3.3V, CMOS Input Levels3, No Pull-up Resistor 1.0 1.2 1.1 1.3 ns 3 GL33S 3.3V, CMOS Input Levels , No Pull-up Resistor, Schmitt Trigger 1.0 1.2 1.1 1.3 ns PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns Notes: 1. tINYH = Input Pad-to-Y HIGH 2. tINYL = Input Pad-to-Y LOW 3. LVTTL delays are the same as CMOS delays. 4. For LP Macros, VDDP=2.3V for delays. Predicted Global Routing Delay Table 1-27 * Worst-Case Commercial Conditions1 VDDP = 3.0V, VDD = 2.3V, TJ = 70C Max. Parameter Description tRCKH tRCKL tRCKH tRCKL Std. -F Units Input Low to High2 1.1 1.3 ns Input High to Low 2 1.0 1.2 ns Input Low to High 3 0.8 1.0 ns Input High to Low 3 0.8 1.0 ns Notes: 1. The timing delay difference between tile locations is less than 15ps. 2. Highly loaded row 50%. 3. Minimally loaded row. Global Routing Skew Table 1-28 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 70C Max. Parameter Description Std. -F Units tRCKSWH Maximum Skew Low to High 270 320 ps tRCKSHH Maximum Skew High to Low 270 320 ps 1- 4 0 v3.4 ProASICPLUS Flash Family FPGAs Module Delays A B C A Y 50% 50% 50% 50% B C 50% 50% 50% Y 50% 50% tDBLH tDALH tDAHL 50% tDCLH 50% 50% tDCHL tDBHL Figure 1-30 * Module Delays Sample Macrocell Library Listing Table 1-29 * Worst-Case Commercial Conditions1 VDD = 2.3V, TJ = 70 C Standard Cell Name Description Max NAND2 2-Input NAND 0.5 0.6 ns AND2 2-Input AND 0.7 0.8 ns NOR3 3-Input NOR 0.8 1.0 ns MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns XOR2 2-Input Exclusive OR 0.6 0.8 ns LDL Active Low Latch (LH/HL) LH2 0.9 1.1 HL2 0.8 0.9 CLK-Q DFFL Min -F Max Min ns tsetup 0.7 0.8 thold 0.1 0.2 Negative Edge-Triggered D-type Flip-Flop (LH/HL) CLK-Q Units ns LH2 0.9 1.1 HL2 0.8 1.0 tsetup 0.6 0.7 thold 0.0 0.0 Notes: 1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. 2. LH and HL refer to the Q transitions from Low to High and High to Low, respectively. v3.4 1-41 ProASICPLUS Flash Family FPGAs Table 1-30 * Recommended Operating Conditions Limits Parameter Symbol Commercial/Industrial Maximum Clock Frequency* fCLOCK 180 MHz Maximum RAM Frequency* fRAM 150 MHz Maximum Rise/Fall Time on Inputs* * Schmitt Mode (10% to 90%) tR/tF 100 ns * Non-schmitt Mode (10% to 90%) tR/tF 10 ns Maximum LVPECL Frequency* 180 MHz Maximum tCK Frequency (JTAG) tCK 10 MHz Note: *-F parts will be 20% slower than standard commercial devices. Table 1-31 * Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25C Type Trig. Level Rising Edge (nS) Slew Rate (V/nS) Falling Edge (nS) Slew Rate (V/nS) PCI Mode OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes OB33PN 10%-90% 1.57 1.68 3.32 0.80 No OB33PL 10%-90% 1.57 1.68 1.99 1.32 No OB33LH 10%-90% 3.80 0.70 4.84 0.55 No OB33LN 10%-90% 4.19 0.63 3.37 0.78 No OB33LL 10%-90% 5.49 0.48 2.98 0.89 No 2 20%-60% 3.31 0.30 0.75 1.33 No 2 OB25HN 20%-60% 3.20 0.32 0.77 1.30 No OB25HL2 20%-60% 3.27 0.31 0.77 1.30 No 2 20%-60% 8.41 0.12 1.38 0.72 No 2 OB25LN 20%-60% 8.54 0.12 1.15 0.87 No 2 OB25LL 20%-60% 8.50 0.12 1.19 0.84 No OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No OB25HH OB25LH Notes: 1. Standard and -F parts. 2. Please refer to the mixed-mode interfacing section in the I/O Features in ProASICPLUS Flash FPGAs application note for guidelines and usage. 1- 4 2 v3.4 ProASICPLUS Flash Family FPGAs Embedded Memory Specifications This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 1-32). Table 1-10 on page 1-20 shows basic SRAM and FIFO configurations. Simultaneous Read and Write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. * Enclosed Timing Diagrams--SRAM Mode: * "Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)" * "Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)" * "Asynchronous SRAM Write" * "Asynchronous SRAM Read, Address Controlled, RDB=0" * "Asynchronous SRAM Read, RDB Controlled" * "Synchronous SRAM Write" Embedded Memory Specifications The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Table 1-32 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 IN Write clock used on synchronization on write side RCLKS 1 IN Read clock used on synchronization on read side RADDR<0:7> 8 IN Read address RBLKB 1 IN True read block select (active LOW) RDB 1 IN True read pulse (active LOW) WADDR<0:7> 8 IN Write address WBLKB 1 IN Write block select (active LOW) DI<0:8> 9 IN Input data bits <0:8>, <8> can be used for parity in WRB 1 IN Negative true write pulse DO<0:8> 9 OUT Output data bits <0:8>, <8> can be used for parity out RPE 1 OUT Read parity error (active HIGH) WPE 1 OUT Write parity error (active HIGH) PARODD 1 IN Selects odd parity generation/detect when high, even when low Note: Not all signals shown are used in all modes. v3.4 1-43 ProASICPLUS Flash Family FPGAs Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RBD, RBLKB New Valid Address RADDR New Valid Data Out Old Data Out DO RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tCML tOCA tRPCA tCCYC Note: The plot shows the normal operation status. Figure 1-31 * Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-33 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 7.5 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS 3.0 3.0 Note: -F speed grade devices are 20% slower than the standard numbers. 1- 4 4 v3.4 ns ns Notes ProASICPLUS Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB, RBLKB RADDR New Valid Address DO New Valid Data Out Old Data Out RPE Old RPE Out New RPE Out tOCA tRACS tRACH tRPCH tRDCH tOCH tRDCS tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-32 * Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-34 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 2.0 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS 0.75 1.0 Notes ns ns Note: -F speed grade devices are 20% slower than the standard numbers. v3.4 1-45 ProASICPLUS Flash Family FPGAs Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE tAWRS tAWRH tDWRH tWPDA tWPDH tDWRS tWRML tWRMH tWRCYC Note: The plot shows the normal operation status. Figure 1-33 * Asynchronous SRAM Write Table 1-35 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units Notes AWRH WADDR hold from WB 1.0 ns AWRS WADDR setup to WB 0.5 ns DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active WPDA WPE access from DI 3.0 ns WPE is invalid while ns PARGEN is active WPDH WPE hold from DI 1.0 WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active Note: -F speed grade devices are 20% slower than the standard numbers. 1- 4 6 v3.4 ProASICPLUS Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC Note: The plot shows the normal operation status. Figure 1-34 * Asynchronous SRAM Read, Address Controlled, RDB=0 Table 1-36 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units ACYC Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable RPAA New RPE access from RADDR stable RPAH Old RPE hold from RADDR stable 3.0 10.0 Notes ns ns 3.0 ns Note: -F speed grade devices are 20% slower than the standard numbers. v3.4 1-47 ProASICPLUS Flash Family FPGAs Asynchronous SRAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDMH tRDCYC Note: The plot shows the normal operation status. Figure 1-35 * Asynchronous SRAM Read, RDB Controlled Table 1-37 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ORDH Old DO valid from RB RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB 7.5 3.0 3.0 Note: -F speed grade devices are 20% slower than the standard numbers. 1- 4 8 ns v3.4 ns ns ProASICPLUS Flash Family FPGAs Synchronous SRAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-36 * Synchronous SRAM Write Table 1-38 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns WACH WADDR hold from WCLKS 0.5 ns WDCS WADDR setup to WCLKS 1.0 ns WPCA New WPE access from WCLKS 3.0 ns WPE is invalid while WPCH Old WPE valid from WCLKS ns PARGEN is active WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS WRB & WBLKB setup to WCLKS 0.5 0.5 ns 1.0 ns Notes: 1. On simultaneous read and write accesses to the same location DI is output to DO. 2. -F speed grade devices are 20% slower than the standard numbers. v3.4 1-49 ProASICPLUS Flash Family FPGAs Synchronous Write and Read to the Same Location tCCYC tCMH tCML RCLKS DO New Data* Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS tOCH tOCA * New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. Figure 1-37 * Synchronous Write and Read to the Same Location Table 1-39 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS to RCLKS setup time - 0.1 ns WCLKRCLKH WCLKS to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS 7.5 Max. Units ns Notes OCA/OCH displayed for Access Timed Output Note: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. -F speed grade devices are 20% slower than the standard numbers. 1- 5 0 v3.4 ProASICPLUS Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location t CMH t CML RCLKS New Data* DO Last Cycle Data WB = {WRB + WBLKB} DI t WRCKS t BRCLKH t OCH t OCA t DWRRCLKS t DWRH tCCYC * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. Note: The plot shows the normal operation status. Figure 1-38 * Asynchronous Write and Synchronous Read to the Same Location Table 1-40 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB to RCLKS setup time -0.1 ns WBRCLKH WB to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS DWRRCLKS DI to RCLKS setup time DWRH DI to WB hold time Min. Max. Units 7.5 ns 0 ns 1.5 Notes OCA/OCH displayed Access Timed Output for ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.4 1-51 ProASICPLUS Flash Family FPGAs Asynchronous Write and Read to the Same Location RB, RADDR DO NEW OLD NEWER WB = {WRB+WBLKB} tORDA tRAWRH tORDH tRAWRS tOWRA tOWRH Note: The plot shows the normal operation status. Figure 1-39 * Asynchronous Write and Read to the Same Location Table 1-41 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WB OWRH Old DO valid from WB RAWRS RB or RADDR from WB 5.0 ns RAWRH RB or RADDR from WB 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. 1- 5 2 v3.4 ProASICPLUS Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO NEW OLD NEWER WCLKS t ORDA t RAWCLKH t ORDH t OWRA t OWRH t RAWCLKS Note: The plot shows the normal operation status. Figure 1-40 * Synchronous Write and Asynchronous Read to the Same Location Table 1-42 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WCLKS OWRH Old DO valid from WCLKS RAWCLKS RB or RADDR from WCLKS 5.0 ns RAWCLKH RB or RADDR from WCLKS 5.0 ns 7.5 Units Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. -F speed grade devices are 20% slower than the standard numbers. v3.4 1-53 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 1-1 on page 1-6). The timing diagram for write is shown in Figure 1-38 on page 1-51. The timing diagram for read is shown in Figure 1-39 on page 1-52. For basic SRAM configurations, see Table 1-11 on page 1-22. Enclosed Timing Diagrams - FIFO Mode: * "Asynchronous FIFO Read" * "Asynchronous FIFO Write" * "Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)" * "Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)" * "Synchronous FIFO Write" * "FIFO Reset" Table 1-43 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 IN Write clock used for synchronization on write side RCLKS 1 IN Read clock used for synchronization on read side LEVEL <0:7>* 8 IN Direct configuration implements static flag logic RBLKB 1 IN Read block select (active LOW) RDB 1 IN Read pulse (active LOW) RESET 1 IN Reset for FIFO pointers (active LOW) WBLKB 1 IN Write block select (active LOW) DI<0:8> 9 IN Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 IN Write pulse (active LOW) FULL, EMPTY 2 OUT FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH* 2 OUT EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 OUT Output data bits <0:8> RPE 1 OUT Read parity error (active HIGH) WPE 1 OUT Write parity error (active HIGH) LGDEP <0:2> 3 IN Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 IN Selects odd parity generation/detect when high, even when low Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs. 1- 5 4 v3.4 ProASICPLUS Flash Family FPGAs FULL RB Write cycle Write inhibited Write accepted 1 ns 3 ns WB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 1-41 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1 ns 3 ns RB Note: -F speed grade devices are 20% slower than the standard numbers. Figure 1-42 * Read Timing Diagram v3.4 1-55 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Read tRPRDA tRDL Cycle Start tRDH RB = (RDB+RBLKB) (Empty inhibits read) RDATA RPE WB EMPTY FULL EQTH, GETH tRDWRS tERDH, tFRDH tORDH tERDA, tFRDA tRPRDH tTHRDH tTHRDA tORDA tRPRDA tRDL tRDH tRDCYC Note: The plot shows the normal operation status. Figure 1-43 * Asynchronous FIFO Read Table 1-44 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold THRDH time from RB ERDA New EMPTY access from RB FRDA ORDA ORDH Old DO valid from RB RDCYC Read cycle time RDWRS WB , clearing EMPTY, setup to RB 3.0 RDH RB high phase RDL Max. Units 0.5 ns 3.01 Notes Empty/full/thresh are invalid from the end of hold until the new access is complete ns FULL access from RB 3.0 1 ns New DO access from RB 7.5 ns 3.0 ns 7.5 ns 2 ns Enabling the read operation ns Inhibiting the read operation 3.0 ns Inactive RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 RPRDH Old RPE valid from RB THRDA EQTH or GETH access from RB 1.0 ns 4.0 4.5 Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns - RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. 1- 5 6 v3.4 ns ns ProASICPLUS Flash Family FPGAs Asynchronous FIFO Write Cycle Start WB = (WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRH tWRCYC Note: The plot shows the normal operation status. Figure 1-44 * Asynchronous FIFO Write Table 1-45 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units Notes DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold THWRH time after WB EWRA EMPTY access from WB FWRA 0.5 3.01 ns New FULL access from WB 3.0 1 ns THWRA EQTH or GETH access from WB 4.5 ns WPDA WPE access from DI 3.0 ns WPDH WPE hold from DI WRCYC Cycle time WRRDS RB , clearing FULL, setup to WB 3.0 WRH WB high phase 3.0 ns Inactive WRL WB low phase 3.0 ns Active 1.0 WPE is invalid while PARGEN is active ns 7.5 ns 2 ns 1.0 Enabling the write operation Inhibiting the write operation Notes: 1. At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns. 2. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns. 3. -F speed grade devices are 20% slower than the standard numbers. v3.4 1-57 ProASICPLUS Flash Family FPGAs Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tECBH, tFCBH tECBA, tFCBA tRDCS tTHCBH tOCH tRPCH tHCBA tOCA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-45 * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-46 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS 1 ns FCBA FULL access from RCLKS 1 ns 3.0 3.0 ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold THCBH time from RCLKS 1.0 ns OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 7.5 3.0 3.0 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 1- 5 8 ns v3.4 ns ns ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete ProASICPLUS Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out RPE New Valid Data Out Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tOCA tRDCH tECBA, tFCBA tTHCBH tRDCS tRPCH tOCH tHCBA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-46 * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-47 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS 3.01 ns FCBA FULL access from RCLKS 1 ns ECBH, THCBH Min. 3.0 FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS Max. 1.0 Units Notes ns OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 2.0 ns 0.75 1.0 4.5 Empty/full/thresh are invalid from the end of hold until the new access is complete ns ns ns Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMS), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. v3.4 1-59 ProASICPLUS Flash Family FPGAs Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tECBH, tFCBH tWRCS, tWBCS tECBA, tFCBA tDCS tHCBH tHCBA tWPCH tDCH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-47 * Synchronous FIFO Write Table 1-48 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns FCBA New FULL access from WCLKS 1 3.0 ns ECBA EMPTY access from WCLKS 3.01 ns ECBH, FCBH, HCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from WCLKS HCBA EQTH or GETH access from WCLKS 4.5 ns WPCA New WPE access from WCLKS 3.0 ns WPCH Old WPE valid from WCLKS WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS WRB & WBLKB setup to WCLKS 1.0 0.5 ns 0.5 ns 1.0 ns Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. -F speed grade devices are 20% slower than the standard numbers. 1- 6 0 ns v3.4 Notes Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid while PARGEN is active ProASICPLUS Flash Family FPGAs FIFO Reset RESETB Cycle Start WB* WCLKS, RCLKS Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tCBRSH tWBRSH tTHRSA tRSL tWBRSS Note: *The plot shows the normal operation status. Figure 1-48 * FIFO Reset Table 1-49 * TJ = 0C to 110C; VDD = 2.3V to 2.7V Symbol txxx Description CBRSH WCLKS or RCLKS hold from RESETB CBRSS Min. WCLKS or RCLKS setup to RESETB Max. Units Notes 1.5 ns Synchronous mode only 1.5 ns Synchronous mode only ERSA New EMPTY access from RESETB 3.0 ns FRSA FULL access from RESETB 3.0 ns RSL RESETB low phase 7.5 ns THRSA EQTH or GETH access from RESETB 4.5 ns WBRSH WB hold from RESETB 1.5 ns Asynchronous mode only WBRSS WB setup to RESETB 1.5 ns Asynchronous mode only Note: -F speed grade devices are 20% slower than the standard numbers. v3.4 1-61 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written during the transition out of full to not full or read during the transition out of empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. This indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition for slow cycles. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 1-43 on page 1-54). 1- 6 2 v3.4 The timing diagram for write is shown in Figure 1-41 on page 1-55. The timing diagram for read is shown in Figure 1-42 on page 1-55. For basic SRAM configurations, see Table 1-11 on page 1-22. Enclosed Timing Diagrams - FIFO Mode: * Asynchronous FIFO Read * Asynchronous FIFO Write * Synchronous FIFO Read, Access Strobe (Synchronous Transparent) * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) * Synchronous FIFO Write * FIFO Reset Timed Output ProASICPLUS Flash Family FPGAs Pin Description TMS The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. User Pins I/O TCK User Input/Output TDI No Connect TDO Global Pin TRST Special Function Pins Global Multiplexing Pin RCK NPECL User Negative Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. 2. In applications where two different signals access the same global net (but at different times) through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. PPECL User Positive Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, a global will be configured as an input with pull-up. AVDD PLL Power Supply Analog VDD should be VDD (core voltage) 2.5V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AVDD should be tied high (2.5V normal). Dedicated Pins Ground Common ground supply voltage. AGND Logic Array Power Supply Pin PLL Power Ground Analog GND should be 0V and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND. 2.5V supply voltage. VDDP Running Clock A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pullup and can be left floating. 1. When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit. VDD Test Reset Input Asynchronous, active low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. Low skew input pin for clock or other global signals. This pin can be used in one of two special ways: (Please see Clock Conditioning Circuits Actel's ProASICPLUS application note for details). GND Test Data Out Serial output for boundary scan. Actel recommends adding a nominal 20k pull-up resistor to this pin. Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O. GLMX Test Data In Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven. To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board. GL Test Clock Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20k pull-up resistor to this pin. The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC Test Mode Select I/O Pad Power Supply Pin 2.5V or 3.3V supply voltage. v3.4 1-63 ProASICPLUS Flash Family FPGAs VPP Programming Supply Pin VPN This pin may be connected to any voltage between GND and 16.5V during normal operation, or it can be left unconnected.1 For information on using this pin during programming, see the Performing Internal In-System Devices Programming Using Actel's ProASICPLUS application note. Actel recommends floating the pin or connecting it to VDDP. Programming Supply Pin This pin may be connected to any voltage between GND and -13.8V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND. Recommended Design Practice for VPN/VPP ProASICPLUS Devices - APA450, APA600, APA750, APA1000 Bypass capacitors are required from VPP to GND and VPN to GND for all ProASICPLUS devices during programming. During the erase cycle, ProASICPLUS devices may have current surges on the VPP and VPN power supplies. The only way to maintain the integrity of the power distribution to the ProASICPLUS device during these current surges is to counteract the inductance of the finite length conductors that distribute the power to the device. This can be accomplished by providing sufficient bypass capacitance between the VPP and VPN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the VPP and VPN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. The power supply voltage limits are defined in the "Supply Voltages" on page 1-30. The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic capacitor with a 25V or greater rating. To filter low-frequency noise (decoupling), use a 4.7 F (low ESR, <1 <, tantalum, 25V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5cm is desirable). The smaller, high-frequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor. The same dual capacitor circuit should be used on both the VPP and VPN pins (Figure 1-49 on page 1-64). ProASICPLUS Devices - APA075, APA150, APA300 These devices do not require bypass capacitors on the VPP and VPN pins as long as the total combined distance of the programming cable and the trace length on the board is less than or equal to 30 inches. Note: For trace lengths greater than 30 inches, use the bypass capacitor recommendations in the previous section. 2.5cm V + _ PP 0.1F or 0.01F Actel PLUS ProASIC Device V PN 4.7F Programming Header or Supplies _ + 0.1F or 0.01F 4.7F + (See the "Recommended Design Practice for VPN/VPP" on page 1-64) Figure 1-49 * ProASICPLUS VPP and VPN Capacitor Requirements 1. There is a nominal 40k pull-up resistor on VPP. 2. There is a nominal 40k pull-down resistor on VPN. 1- 6 4 + v3.4