Si86xx 1 Mbps Data Sheet 1 Mbps, 2.5 kVRMS Digital Isolators Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering substantial data rate, propagation delay, power, size, reliability, and external BOM advantages over legacy isolation technologies. The operating parameters of these products remain stable across wide temperature ranges and throughout device service life for ease of design and highly uniform performance. All device versions have Schmitt trigger inputs for high noise immunity and only require VDD bypass capacitors. All products support Data rates up to 1 Mbps and Enable inputs which provide a single point control for enabling and disabling output drive. All products are safety certified by UL, CSA, VDE, and CQC and support withstand ratings up to 2.5 kVRMS. Automotive Grade is available for certain part numbers. These products are built using automotive-specific flows at all steps in the manufacturing process to ensure the robustness and low defectivity required for automotive applications. Industrial Applications * Industrial automation systems * Medical electronics * Isolated switch mode supplies * Isolated ADC, DAC * Motor control * Power inverters * Communication systems Safety Regulatory Approvals * UL 1577 recognized * Up to 5000 VRMS for 1 minute * CSA component notice 5A approval * IEC 60950-1, 61010-1 * VDE certification conformity * IEC 60747-5-2 (VDE0884 Part 2) * CQC certification approval * GB4943.1 silabs.com | Building a more connected world. Automotive Applications * On-board chargers * Battery management systems * Charging stations * Traction inverters * Hybrid Electric Vehicles * Battery Electric Vehicles KEY FEATURES * High-speed operation * DC to 1 Mbps * No start-up initialization required * Wide Operating Supply Voltage * 2.5 to 5.5 V * Up to 2500 VRMS isolation * 60-year life at rated working voltage * High electromagnetic immunity * Ultra low power (typical) * 5 V Operation: 1.6 mA per channel at 1 Mbps * 2.5 V Operation: 1.5 mA per channel at 1 Mbps * Tri-state outputs with ENABLE * Schmitt trigger inputs * Transient Immunity 50 kV/s * AEC-Q100 qualification * Wide temperature range * -40 to 125 C * RoHS-compliant packages * SOIC-16 wide body * SOIC-16 narrow body * SOIC-8 narrow body * Automotive-grade OPNs available * AIAG compliant PPAP documentation support * IMDS and CAMDS listing support Rev. 1.02 Si86xx Data Sheet Ordering Guide 1. Ordering Guide Table 1.1. Ordering Guide for Valid OPNs1,2 Ordering Part Number (OPN) Number of Inputs VDD1 Side Number of Inputs VDD2 Side Max Data Rate (Mbps) Default Output State Isolation Rating (kV) Temp (C) Package Si8610AB-B-IS 1 0 1 Low 2.5 -40 to 125 C SOIC-8 Si8620AB-B-IS 2 0 1 Low 2.5 -40 to 125 C SOIC-8 Si8621AB-B-IS 1 1 1 Low 2.5 -40 to 125 C SOIC-8 Si8630AB-B-IS 3 0 1 Low 2.5 -40 to 125 C WB SOIC-16 Si8630AB-B-IS1 3 0 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8631AB-B-IS 2 1 1 Low 2.5 -40 to 125 C WB SOIC-16 Si8631AB-B-IS1 2 1 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8640AB-B-IS1 4 0 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8640AB-B-IS 4 0 1 Low 2.5 -40 to 125 C WB SOIC-16 Si8641AB-B-IS1 3 1 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8641AB-B-IS 3 1 1 Low 2.5 -40 to 125 C WB SOIC-16 Si8642AB-B-IS1 2 2 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8642AB-B-IS 2 2 1 Low 2.5 -40 to 125 C WB SOIC-16 Si8650AB-B-IS1 5 0 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8651AB-B-IS1 4 1 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8652AB-B-IS1 3 2 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8660AB-B-IS1 6 0 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8661AB-B-IS1 5 1 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8662AB-B-IS1 4 2 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8663AB-B-IS1 3 3 1 Low 2.5 -40 to 125 C NB SOIC-16 Notes: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 C according to the JEDEC industry standard classifications and peak solder temperatures. 2. "Si" and "SI" are used interchangeably. silabs.com | Building a more connected world. Rev. 1.02 | 2 Si86xx Data Sheet Ordering Guide Automotive Grade OPNs Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and feature International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compliant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass production steps. Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5 Ordering Part Number (OPN) Number of Inputs VDD1 Side Number of Inputs VDD2 Side Max Data Rate (Mbps) Default Output State Isolation Rating (kV) Temp (C) Package Si8621AB-AS 1 1 1 Low 2.5 -40 to 125 C SOIC-8 SI8641AB-AS1 3 1 1 Low 2.5 -40 to 125 C NB SOIC-16 SI8642AB-AS1 2 2 1 Low 2.5 -40 to 125 C NB SOIC-16 Si8663AB-AS1 3 3 1 Low 2.5 -40 to 125 C SOIC-16 Note: 1. All packages are RoHS-compliant with peak reflow temperatures of 260 C according to the JEDEC industry standard classifications. 2. "Si" and "SI" are used interchangeably. 3. An "R" at the end of the part number denotes tape and reel packaging option. 4. Automotive-Grade devices (with an "-A" suffix) are identical in construction materials, topside marking, and electrical parameters to their Industrial-Grade (with a "-I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is included on shipping labels. 5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales representative for further information. silabs.com | Building a more connected world. Rev. 1.02 | 3 Table of Contents 1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 Layout Recommendations . 3.3.1 Supply Bypass . . . 3.3.2 Output Pin Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 . 8 . 8 4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 Pin Descriptions (Si861x/2x Narrow Body SOIC-8) . . . . . . . . . . . . . . . . . .30 5.2 Pin Descriptions (Si863x) . . . . . . . . . . . . . . . . . . . . . . . . . .31 5.3 Pin Descriptions (Si864x) . . . . . . . . . . . . . . . . . . . . . . . . . .32 5.4 Pin Descriptions (Si8650/51/52) . . . . . . . . . . . . . . . . . . . . . . . .33 5.5 Pin Descriptions (Si866x) . . . . . . . . . . . . . . . . . . . . . . .34 6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 . . . 6.1 Package Outline (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . .35 6.2 Package Outline (16-Pin Narrow Body SOIC). . . . . . . . . . . . . . . . . . . .37 6.3 Package Outline (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . .39 7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 Land Pattern (16-Pin Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . .40 7.2 Land Pattern (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .41 7.3 Land Pattern (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .42 8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.1 Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . . . . . .43 8.2 Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . .44 8.3 Top Marking (8-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . .45 9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 silabs.com | Building a more connected world. Rev. 1.02 | 4 Si86xx Data Sheet Functional Description 2. Functional Description 2.1 Theory of Operation The operation of an Si86xx channel is analogous to that of an opto coupler, except an RF carrier is modulated instead of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A simplified block diagram for a single Si86xx channel is shown in the figure below. Transmitter Receiver RF OSCILLATOR A MODULATOR SemiconductorBased Isolation Barrier DEMODULATOR B Figure 2.1. Simplified Channel Diagram A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See the figure below for more details. Input Signal Modulation Signal Output Signal Figure 2.2. Modulation Scheme silabs.com | Building a more connected world. Rev. 1.02 | 5 Si86xx Data Sheet Device Operation 3. Device Operation Device behavior during start-up, normal operation, and shutdown is shown in Figure 3.1 Device Behavior during Normal Operation on page 8, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Refer to the table below to determine outputs when power supply (VDD) is not present. Additionally, refer to Table 3.2 Enable Input Truth1 on page 7 for logic conditions when enable pins are used. Table 3.1. Si86xx Logic Operation VI Input1,2 EN Input1,2,3,4 VDDI State1,5,6 VDDO State1,5,6 VO Output1,2 H H or NC P P H L H or NC P P L X7 L P P Hi-Z8 X7 H or NC UP P L X7 L UP P Hi-Z8 X7 X7 P UP Undetermined Comments Enabled, normal operation. Disabled. Upon transition of VDDI from unpowered to powered, VO returns to the same state as VI in less than 1 s. Disabled. Upon transition of VDDO from unpowered to powered, VO returns to the same state as VI within 1 s, if EN is in either the H or NC state. Upon transition of VDDO from unpowered to powered, VO returns to Hi-Z within 1 s if EN is L. Notes: 1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals. EN is the enable control input located on the same output side. 2. X = not applicable; H = Logic High; L = Logic Low; Hi-Z = High Impedance. 3. It is recommended that the enable inputs be connected to an external logic high or low level when the Si86xx is operating in noisy environments. 4. No Connect (NC) replaces EN1 on some devices. No Connects are not internally connected and can be left floating, tied to VDD, or tied to GND. 5. "Powered" state (P) is defined as 2.5 V < VDD < 5.5 V. 6. "Unpowered" state (UP) is defined as VDD = 0 V. 7. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current. 8. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled (EN = 0). silabs.com | Building a more connected world. Rev. 1.02 | 6 Si86xx Data Sheet Device Operation Table 3.2. Enable Input Truth1 P/N EN11,2 EN21,2 Si861x/2x -- -- Outputs are enabled and follow input state. Si8630 -- H Outputs B1, B2, B3 are enabled and follow input state. -- L Outputs B1, B2, B3 are disabled and in high impedance state.3 H X Output A3 enabled and follows input state. L X Output A3 disabled and in high impedance state.3 X H Outputs B1, B2 are enabled and follow input state. X L Outputs B1, B2 are disabled and in high impedance state.3 -- H Outputs B1, B2, B3, B4 are enabled and follow the input state. -- L Outputs B1, B2, B3, B4 are disabled and in high impedance state.3 H X Output A4 enabled and follows the input state. L X Output A4 disabled and in high impedance state.3 X H Outputs B1, B2, B3 are enabled and follow the input state. X L Outputs B1, B2, B3 are disabled and in high impedance state.3 H X Outputs A3 and A4 are enabled and follow the input state. L X Outputs A3 and A4 are disabled and in high impedance state.3 X H Outputs B1 and B2 are enabled and follow the input state. X L Outputs B1 and B2 are disabled and in high impedance state.3 -- H Outputs B1, B2, B3, B4, B5 are enabled and follow input state. -- L Outputs B1, B2, B3, B4, B5 are disabled and Logic Low or in high impedance state.3 H X Output A5 enabled and follow input state. L X Output A5 disabled and in high impedance state.3 X H Outputs B1, B2, B3, B4 are enabled and follow input state. X L Outputs B1, B2, B3, B4 are disabled and in high impedance state.3 H X Outputs A4 and A5 are enabled and follow input state. L X Outputs A4 and A5 are disabled and in high impedance state.3 X H Outputs B1, B2, B3 are enabled and follow input state. X L Outputs B1, B2, B3 are disabled and in high impedance state.3 -- -- Outputs are enabled and follow input state. Si8631 Si8640 Si8641 Si8642 Si8650 Si8651 Si8652 Si866x Operation Notes: 1. Enable inputs EN1 and EN2 can be used for multiplexing, for clock sync, or other output control. These inputs are internally pulled-up to local VDD by a 2 A current source allowing them to be connected to an external logic level (high or low) or left floating. To minimize noise coupling, do not connect circuit traces to EN1 or EN2 if they are left floating. If EN1, EN2 are unused, it is recommended they be connected to an external logic level, especially if the Si86xx is operating in a noisy environment. 2. X = not applicable; H = Logic High; L = Logic Low. 3. When using the enable pin (EN) function, the output pin state is driven into a high-impedance state when the EN pin is disabled (EN = 0). silabs.com | Building a more connected world. Rev. 1.02 | 7 Si86xx Data Sheet Device Operation 3.1 Device Startup Outputs are held low during powerup until VDD is above the UVLO threshold for time period tSTART. Following this, the outputs follow the states of inputs. 3.2 Undervoltage Lockout Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its specified operating circuits range. Both Side A and Side B each have their own undervoltage lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters UVLO when VDD1 falls below VDD1(UVLO-) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates the same as Side A with respect to its VDD2 supply. UVLO+ UVLO- VDD1 UVLO+ UVLO- VDD2 INPUT tSTART tSD tSTART tSTART tPHL tPLH OUTPUT Figure 3.1. Device Behavior during Normal Operation 3.3 Layout Recommendations To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance (creepage/clearance). If a component, such as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). Table 4.5 Regulatory Information1 on page 25 and Table 4.6 Insulation and Safety-Related Specifications on page 25 detail the working voltage and creepage/clearance capabilities of the Si86xx. These tables also detail the component standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 3.3.1 Supply Bypass The Si86xx family requires a 0.1 F bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The capacitor should be placed as close as possible to the package. To enhance the robustness of a design, the user may also include resistors (50-300 ) in series with the inputs and outputs if the system is excessively noisy. 3.3.2 Output Pin Termination The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the onchip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. silabs.com | Building a more connected world. Rev. 1.02 | 8 Si86xx Data Sheet Electrical Specifications 4. Electrical Specifications Table 4.1. Recommended Operating Conditions Parameter Ambient Operating Temperature1 Supply Voltage Symbol Min Typ Max Unit TA -40 25 125 C VDD1 2.5 -- 5.5 V VDD2 2.5 -- 5.5 V Note: 1. The maximum ambient temperature is dependent on data frequency, output loading, number of operating channels, and supply voltage. Table 4.2. Electrical Characteristics (VDD1 = 5 V10%, VDD2 = 5 V10%, TA = -40 to 125 C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV- VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT- All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 -- -- V Low Level input voltage VIL -- -- 0.8 V High Level Output Voltage VOH loh = -4 mA VDD1,VDD2 - 0.4 4.8 -- V Low Level Output Voltage VOL lol = 4 mA -- 0.2 0.4 V Input Leakage Current IL -- -- 10 A Output Impedance1 ZO -- 50 -- Enable Input High Current ENH VENx = VIH -- 2.0 -- A Enable Input Low Current IENL VENx = VIL -- 2.0 -- A VDD1 VI = 0(Ax) -- 0.6 1.2 VDD2 VI = 0(Ax) -- 0.8 1.5 VDD1 VI = 1(Ax) -- 1.8 2.9 VDD2 VI = 1(Ax) -- 0.8 1.5 DC Supply Current (All inputs 0 V or at Supply) Si8610Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 9 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 0.8 1.4 VDD2 VI = 0(Ax) -- 1.4 2.2 VDD1 VI = 1(Ax) -- 3.3 5.3 VDD2 VI = 1(Ax) -- 1.4 2.2 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 1.2 1.9 VDD1 VI = 1(Ax) -- 2.4 3.8 VDD2 VI = 1(Ax) -- 2.4 3.8 VDD1 VI = 0(Ax) -- 0.9 1.6 VDD2 VI = 0(Ax) -- 1.9 3.0 VDD1 VI = 1(Ax) -- 4.6 7.4 VDD2 VI = 1(Ax) -- 1.9 3.0 VDD1 VI = 0(Ax) -- 1.3 2.1 VDD2 VI = 0(Ax) -- 1.7 2.7 VDD1 VI = 1(Ax) -- 3.9 5.9 VDD2 VI = 1(Ax) -- 3.0 4.5 VDD1 VI = 0(Ax) -- 1.0 1.6 VDD2 VI = 0(Ax) -- 2.4 3.8 VDD1 VI = 1(Ax) -- 6.1 9.2 VDD2 VI = 1(Ax) -- 2.5 4.0 VDD1 VI = 0(Ax) -- 1.4 2.2 VDD2 VI = 0(Ax) -- 2.3 3.7 VDD1 VI = 1(Ax) -- 5.2 7.8 VDD2 VI = 1(Ax) -- 3.6 5.4 VDD1 VI = 0(Ax) -- 1.8 2.9 VDD2 VI = 0(Ax) -- 1.8 2.9 VDD1 VI = 1(Ax) -- 4.4 6.6 VDD2 VI = 1(Ax) -- 4.4 6.6 Unit Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax mA Si8641Ax mA Si8642Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 10 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 1.1 1.8 VDD2 VI = 0(Ax) -- 3.1 4.7 VDD1 VI = 1(Ax) -- 7.0 9.8 VDD2 VI = 1(Ax) -- 3.3 5.0 VDD1 VI = 0(Ax) -- 1.5 2.4 VDD2 VI = 0(Ax) -- 2.7 4.1 VDD1 VI = 1(Ax) -- 6.6 9.2 VDD2 VI = 1(Ax) -- 4.0 6.0 VDD1 VI = 0(Ax) -- 2.0 3.0 VDD2 VI = 0(Ax) -- 2.4 3.6 VDD1 VI = 1(Ax) -- 5.6 7.8 VDD2 VI = 1(Ax) -- 5.0 7.5 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 3.5 5.3 VDD1 VI = 1(Ax) -- 8.8 12.3 VDD2 VI = 1(Ax) -- 3.7 5.6 VDD1 VI = 0(Ax) -- 1.7 2.7 VDD2 VI = 0(Ax) -- 3.4 5.1 VDD1 VI = 1(Ax) -- 7.9 11.1 VDD2 VI = 1(Ax) -- 4.8 7.2 VDD1 VI = 0(Ax) -- 2.2 3.3 VDD2 VI = 0(Ax) -- 3.0 4.5 VDD1 VI = 1(Ax) -- 7.5 10.5 VDD2 VI = 1(Ax) -- 5.6 8.4 VDD1 VI = 0(Ax) -- 2.6 3.9 VDD2 VI = 0(Ax) -- 2.6 3.9 VDD1 VI = 1(Ax) -- 6.5 9.1 VDD2 VI = 1(Ax) -- 6.5 9.1 Unit Si8650Ax mA Si8651Ax mA Si8652Ax mA Si8660Ax mA Si8661Ax mA Si8662Ax mA Si8663Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 11 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 -- 1.2 2.0 mA VDD2 -- 0.9 1.5 VDD1 -- 2.1 3.1 VDD2 -- 1.6 2.4 VDD1 -- 1.9 2.9 VDD2 -- 1.9 2.9 VDD1 -- 2.8 3.9 VDD2 -- 2.2 3.1 VDD1 -- 2.7 3.8 VDD2 -- 2.6 3.6 VDD1 -- 3.6 5.0 VDD2 -- 2.9 4.0 VDD1 -- 3.4 4.8 VDD2 -- 3.3 4.6 VDD1 -- 3.3 4.6 VDD2 -- 3.3 4.6 VDD1 -- 4.1 5.7 VDD2 -- 3.7 5.2 VDD1 -- 4.2 5.8 VDD2 -- 3.8 5.3 VDD1 -- 4.0 5.6 VDD2 -- 4.0 5.6 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all Outputs) Si8610Ax Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax mA Si8641Ax mA Si8642Ax mA Si8650Ax mA Si8651Ax mA Si8652Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 12 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 -- 5.0 7.0 mA VDD2 -- 4.2 5.9 VDD1 -- 4.9 6.9 VDD2 -- 4.6 6.4 VDD1 -- 5.1 7.1 VDD2 -- 4.7 6.6 VDD1 -- 4.9 6.8 VDD2 -- 4.9 6.8 Maximum Data Rate 0 -- 1 Mbps Minimum Pulse Width -- -- 250 ns Si8660Ax Si8661Ax mA Si8662Ax mA Si8663Ax mA Timing Characteristics All Models Propagation Delay Pulse Width Distortion tPHL, tPLH See Figure 4.2 Propagation Delay Timing on page 14 -- -- 35 ns PWD See Figure 4.2 Propagation Delay Timing on page 14 -- -- 25 ns tPSK(P-P) -- -- 40 ns tPSK -- -- 35 ns -- 2.5 4.0 ns -- 2.5 4.0 ns |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew Output Rise Time tr CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 14 Output Fall Time tf CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 14 Peak eye diagram jitter tJIT(PK) See Figure 2.2 Modulation Scheme on page 5 -- 350 -- ps Common Mode Transient Immunity CMTI VI = VDD or 0 V 35 50 -- kV/s VCM = 1500 V (See Figure 4.3 Common-Mode Transient Immunity Test Circuit on page 15) Enable to Data Valid ten1 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 6.0 11 ns Enable to Data Tri-State ten2 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 8.0 12 ns silabs.com | Building a more connected world. Rev. 1.02 | 13 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition tSU Start-up Time3 Min Typ Max Unit -- 15 40 s Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. ENABLE OUTPUTS ten1 ten2 Figure 4.1. ENABLE Timing Diagram 1.4 V Typical Input tPLH tPHL 90% 90% 10% 10% 1.4 V Typical Output tr tf Figure 4.2. Propagation Delay Timing silabs.com | Building a more connected world. Rev. 1.02 | 14 Si86xx Data Sheet Electrical Specifications 3 to 5 V Supply Si86xx Input Signal Switch 3 to 5 V Isolated Supply VDD1 VDD2 INPUT OUTPUT Oscilloscope GND1 GND2 Isolated Ground Input High Voltage Differential Probe Output Vcm Surge Output High Voltage Surge Generator Figure 4.3. Common-Mode Transient Immunity Test Circuit Table 4.3. Electrical Characteristics (VDD1 = 3.3 V10%, VDD2 = 3.3 V10%, TA = -40 to 125 C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV- VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT- All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 -- -- V Low Level Input Voltage VIL -- -- 0.8 V High Level Output Voltage VOH loh = -4 mA VDD1, VDD2 - 0.4 3.1 -- V Low Level Output Voltage VOL lol = 4 mA -- 0.2 0.4 V silabs.com | Building a more connected world. Rev. 1.02 | 15 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Input Leakage Current IL -- -- 10 A Output Impedance1 ZO -- 50 -- Enable Input High Current IENH VENx = VIH -- 2.0 -- A Enable Input Low Current IENL VENx = VIL -- 2.0 -- A VDD1 VI = 0(Ax) -- 0.6 1.2 VDD2 VI = 0(Ax) -- 0.8 1.5 VDD1 VI = 1(Ax) -- 1.8 2.9 VDD2 VI = 1(Ax) -- 0.8 1.5 VDD1 VI = 0(Ax) -- 0.8 1.4 VDD2 VI = 0(Ax) -- 1.4 2.2 VDD1 VI = 1(Ax) -- 3.3 5.3 VDD2 VI = 1(Ax) -- 1.4 2.2 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 1.2 1.9 VDD1 VI = 1(Ax) -- 2.4 3.8 VDD2 VI = 1(Ax) -- 2.4 3.8 VDD1 VI = 0(Ax) -- 0.9 1.6 VDD2 VI = 0(Ax) -- 1.9 3.0 VDD1 VI = 1(Ax) -- 4.6 7.4 VDD2 VI = 1(Ax) -- 1.9 3.0 VDD1 VI = 0(Ax) -- 1.3 2.1 VDD2 VI = 0(Ax) -- 1.7 2.7 VDD1 VI = 1(Ax) -- 3.9 5.9 VDD2 VI = 1(Ax) -- 3.0 4.5 VDD1 VI = 0(Ax) -- 1.0 1.6 VDD2 VI = 0(Ax) -- 2.4 3.8 VDD1 VI = 1(Ax) -- 6.1 9.2 VDD2 VI = 1(Ax) -- 2.5 4.0 DC Supply Current (All inputs 0 V or at supply) Si8610Ax mA Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 16 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 1.4 2.2 VDD2 VI = 0(Ax) -- 2.3 3.7 VDD1 VI = 1(Ax) -- 5.2 7.8 VDD2 VI = 1(Ax) -- 3.6 5.4 VDD1 VI = 0(Ax) -- 1.8 2.9 VDD2 VI = 0(Ax) -- 1.8 2.9 VDD1 VI = 1(Ax) -- 4.4 6.6 VDD2 VI = 1(Ax) -- 4.4 6.6 VDD1 VI = 0(Ax) -- 1.1 1.8 VDD2 VI = 0(Ax) -- 3.1 4.7 VDD1 VI = 1(Ax) -- 7.0 9.8 VDD2 VI = 1(Ax) -- 3.3 5.0 VDD1 VI = 0(Ax) -- 1.5 2.4 VDD2 VI = 0(Ax) -- 2.7 4.1 VDD1 VI = 1(Ax) -- 6.6 9.2 VDD2 VI = 1(Ax) -- 4.0 6.0 VDD1 VI = 0(Ax) -- 2.0 3.0 VDD2 VI = 0(Ax) -- 2.4 3.6 VDD1 VI = 1(Ax) -- 5.6 7.8 VDD2 VI = 1(Ax) -- 5.0 7.5 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 3.5 5.3 VDD1 VI = 1(Ax) -- 8.8 12.3 VDD2 VI = 1(Ax) -- 3.7 5.6 VDD1 VI = 0(Ax) -- 1.7 2.7 VDD2 VI = 0(Ax) -- 3.4 5.1 VDD1 VI = 1(Ax) -- 7.9 11.1 VDD2 VI = 1(Ax) -- 4.8 7.2 Unit Si8641Ax mA Si8642Ax mA Si8650Ax mA Si8651Ax mA Si8652Ax mA Si8660Ax mA Si8661Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 17 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 2.2 3.3 VDD2 VI = 0(Ax) -- 3.0 4.5 VDD1 VI = 1(Ax) -- 7.5 10.5 VDD2 VI = 1(Ax) -- 5.6 8.4 VDD1 VI = 0(Ax) -- 2.6 3.9 VDD2 VI = 0(Ax) -- 2.6 3.9 VDD1 VI = 1(Ax) -- 6.5 9.1 VDD2 VI = 1(Ax) -- 6.5 9.1 VDD1 -- 1.2 2.0 VDD2 -- 0.9 1.5 VDD1 -- 2.1 3.1 VDD2 -- 1.6 2.4 VDD1 -- 1.9 2.9 VDD2 -- 1.9 2.9 VDD1 -- 2.8 3.9 VDD2 -- 2.2 3.1 VDD1 -- 2.7 3.8 VDD2 -- 2.6 3.6 VDD1 -- 3.6 5.0 VDD2 -- 2.9 4.0 VDD1 -- 3.4 4.8 VDD2 -- 3.3 4.6 VDD1 -- 3.3 4.6 VDD2 -- 3.3 4.6 Unit Si8662Ax mA Si8663Ax mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8610Ax mA Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax mA Si8641Ax mA Si8642Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 18 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 -- 4.1 5.7 mA VDD2 -- 3.7 5.2 VDD1 -- 4.2 5.8 VDD2 -- 3.8 5.3 VDD1 -- 4.0 5.6 VDD2 -- 4.0 5.6 VDD1 -- 5.0 7.0 VDD2 -- 4.2 5.9 VDD1 -- 4.9 6.9 VDD2 -- 4.6 6.4 VDD1 -- 5.1 7.1 VDD2 -- 4.7 6.6 VDD1 -- 4.9 6.8 VDD2 -- 4.9 6.8 Maximum Data Rate 0 -- 1 Mbps Minimum Pulse Width -- -- 250 ns Si8650Ax Si8651Ax mA Si8652Ax mA Si8660Ax mA Si8661Ax mA Si8662Ax mA Si8663Ax mA Timing Characteristics All Models Propagation Delay tPHL, tPLH See Figure 4.2 Propagation Delay Timing on page 14 -- -- 35 ns PWD See Figure 4.2 Propagation Delay Timing on page 14 -- -- 25 ns tPSK(P-P) -- -- 40 ns tPSK -- -- 35 ns -- 2.5 4.0 ns Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 Channel-Channel Skew Output Rise Time tr CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 14 silabs.com | Building a more connected world. Rev. 1.02 | 19 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit tf CL = 15 pF -- 2.5 4.0 ns Output Fall Time See Figure 4.2 Propagation Delay Timing on page 14 Peak eye diagram jitter tJIT(PK) See Figure 2.2 Modulation Scheme on page 5 -- 350 -- ps Common Mode CMTI VI = VDD or 0 V 35 50 -- kV/s Transient Immunity VCM = 1500 V (see Figure 4.3 Common-Mode Transient Immunity Test Circuit on page 15) Enable to Data Valid ten1 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 6.0 11 ns Enable to Data Tri-State ten2 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 8.0 12 ns Start-Up Time3 tSU -- 15 40 s Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Table 4.4. Electrical Characteristics (VDD1 = 2.5 V 5%, VDD2 = 2.5 V 5%, TA = -40 to 125 C) Parameter Symbol Test Condition Min Typ Max Unit VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 1.95 2.24 2.375 V VDD Undervoltage Threshold VDDUV- VDD1, VDD2 falling 1.88 2.16 2.325 V VDD Undervoltage Hysteresis VDDHYS 50 70 95 mV Positive-Going Input Threshold VT+ All inputs rising 1.4 1.67 1.9 V Negative-Going Input Threshold VT- All inputs falling 1.0 1.23 1.4 V Input Hysteresis VHYS 0.38 0.44 0.50 V High Level Input Voltage VIH 2.0 -- -- V Low Level Input Voltage VIL -- -- 0.8 V High Level Output Voltage VOH loh = -4 mA VDD1,VDD 2 - 0.4 2.3 -- V Low Level Output Voltage VOL lol = 4 mA -- 0.2 0.4 V Input Leakage Current IL -- -- 10 A Output Impedance1 ZO -- 50 -- silabs.com | Building a more connected world. Rev. 1.02 | 20 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Enable Input High Current IENH VENx = VIH -- 2.0 -- A Enable Input Low Current IENL VENx = VIL -- 2.0 -- A VDD1 VI = 0(Ax) -- 0.6 1.2 VDD2 VI = 0(Ax) -- 0.8 1.5 VDD1 VI = 1(Ax) -- 1.8 2.9 VDD2 VI = 1(Ax) -- 0.8 1.5 VDD1 VI = 0(Ax) -- 0.8 1.4 VDD2 VI = 0(Ax) -- 1.4 2.2 VDD1 VI = 1(Ax) -- 3.3 5.3 VDD2 VI = 1(Ax) -- 1.4 2.2 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 1.2 1.9 VDD1 VI = 1(Ax) -- 2.4 3.8 VDD2 VI = 1(Ax) -- 2.4 3.8 VDD1 VI = 0(Ax) -- 0.9 1.6 VDD2 VI = 0(Ax) -- 1.9 3.0 VDD1 VI = 1(Ax) -- 4.6 7.4 VDD2 VI = 1(Ax) -- 1.9 3.0 VDD1 VI = 0(Ax) -- 1.3 2.1 VDD2 VI = 0(Ax) -- 1.7 2.7 VDD1 VI = 1(Ax) -- 3.9 5.9 VDD2 VI = 1(Ax) -- 3.0 4.5 VDD1 VI = 0(Ax) -- 1.0 1.6 VDD2 VI = 0(Ax) -- 2.4 3.8 VDD1 VI = 1(Ax) -- 6.1 9.2 VDD2 VI = 1(Ax) -- 2.5 4.0 DC Supply Current (All inputs 0 V or at supply) Si8610Ax mA Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 21 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 1.4 2.2 VDD2 VI = 0(Ax) -- 2.3 3.7 VDD1 VI = 1(Ax) -- 5.2 7.8 VDD2 VI = 1(Ax) -- 3.6 5.4 VDD1 VI = 0(Ax) -- 1.8 2.9 VDD2 VI = 0(Ax) -- 1.8 2.9 VDD1 VI = 1(Ax) -- 4.4 6.6 VDD2 VI = 1(Ax) -- 4.4 6.6 VDD1 VI = 0(Ax) -- 1.1 1.8 VDD2 VI = 0(Ax) -- 3.1 4.7 VDD1 VI = 1(Ax) -- 7.0 9.8 VDD2 VI = 1(Ax) -- 3.3 5.0 VDD1 VI = 0(Ax) -- 1.5 2.4 VDD2 VI = 0(Ax) -- 2.7 4.1 VDD1 VI = 1(Ax) -- 6.6 9.2 VDD2 VI = 1(Ax) -- 4.0 6.0 VDD1 VI = 0(Ax) -- 2.0 3.0 VDD2 VI = 0(Ax) -- 2.4 3.6 VDD1 VI = 1(Ax) -- 5.6 7.8 VDD2 VI = 1(Ax) -- 5.0 7.5 VDD1 VI = 0(Ax) -- 1.2 1.9 VDD2 VI = 0(Ax) -- 3.5 5.3 VDD1 VI = 1(Ax) -- 8.8 12.3 VDD2 VI = 1(Ax) -- 3.7 5.6 VDD1 VI = 0(Ax) -- 1.7 2.7 VDD2 VI = 0(Ax) -- 3.4 5.1 VDD1 VI = 1(Ax) -- 7.9 11.1 VDD2 VI = 1(Ax) -- 4.8 7.2 Unit Si8641Ax mA Si8642Ax mA Si8650Ax mA Si8651Ax mA Si8652Ax mA Si8660Ax mA Si8661Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 22 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max VDD1 VI = 0(Ax) -- 2.2 3.3 VDD2 VI = 0(Ax) -- 3.0 4.5 VDD1 VI = 1(Ax) -- 7.5 10.5 VDD2 VI = 1(Ax) -- 5.6 8.4 VDD1 VI = 0(Ax) -- 2.6 3.9 VDD2 VI = 0(Ax) -- 2.6 3.9 VDD1 VI = 1(Ax) -- 6.5 9.1 VDD2 VI = 1(Ax) -- 6.5 9.1 VDD1 -- 1.2 2.0 VDD2 -- 0.9 1.5 VDD1 -- 2.1 3.1 VDD2 -- 1.6 2.4 VDD1 -- 1.9 -- VDD2 -- 1.9 -- VDD1 -- 2.8 3.9 VDD2 -- 2.2 3.1 VDD1 -- 2.7 3.8 VDD2 -- 2.6 3.6 VDD1 -- 3.6 5.0 VDD2 -- 2.9 4.0 VDD1 -- 3.4 4.8 VDD2 -- 3.3 4.6 VDD1 -- 3.3 4.6 VDD2 -- 3.3 4.6 Unit Si8662Ax mA Si8663Ax mA 1 Mbps Supply Current (All inputs = 500 kHz square wave, CI = 15 pF on all outputs) Si8610Ax mA Si8620Ax mA Si8621Ax mA Si8630Ax mA Si8631Ax mA Si8640Ax mA Si8641Ax mA Si8642Ax silabs.com | Building a more connected world. mA Rev. 1.02 | 23 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit VDD1 -- 4.1 5.7 mA VDD2 -- 3.7 5.2 VDD1 -- 4.2 5.8 VDD2 -- 3.8 5.3 VDD1 -- 4.0 5.6 VDD2 -- 4.0 5.6 VDD1 -- 5.0 7.0 VDD2 -- 4.2 5.9 VDD1 -- 4.9 6.9 VDD2 -- 4.6 6.4 VDD1 -- 5.1 7.1 VDD2 -- 4.7 6.6 VDD1 -- 4.9 6.8 VDD2 -- 4.9 6.8 Maximum Data Rate 0 -- 1 Mbps Minimum Pulse Width -- -- 250 ns Si8650Ax Si8651Ax mA Si8652Ax mA Si8660Ax mA Si8661Ax mA Si8662Ax mA Si8663Ax mA Timing Characteristics All Models Propagation Delay Pulse Width Distortion |tPLH - tPHL| Propagation Delay Skew2 tPHL, tPLH See Figure 4.2 Propagation Delay Timing on page 14 -- -- 35 ns PWD See Figure 4.2 Propagation Delay Timing on page 14 -- -- 25 ns tPSK(P-P) -- -- 40 ns tPSK -- -- 35 ns -- 2.5 4.0 ns -- 2.5 4.0 ns Channel-Channel Skew Output Rise Time tr CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 14 Output Fall Time tf CL = 15 pF See Figure 4.2 Propagation Delay Timing on page 14 silabs.com | Building a more connected world. Rev. 1.02 | 24 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Min Typ Max Unit Peak Eye Diagram Jitter tJIT(PK) See Figure 2.2 Modulation Scheme on page 5 -- 350 -- ps Common Mode CMTI VI = VDD or 0 V 35 50 -- kV/s Transient Immunity VCM = 1500 V (see Figure 4.3 Common-Mode Transient Immunity Test Circuit on page 15) Enable to Data Valid ten1 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 6.0 11 ns Enable to Data Tri-State ten2 See Figure 4.1 ENABLE Timing Diagram on page 14 -- 8.0 12 ns Startup Time3 tSU -- 15 40 s Notes: 1. The nominal output impedance of an isolator driver channel is approximately 50 , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads where transmission line effects will be a factor, output pins should be appropriately terminated with controlled impedance PCB traces. 2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 3. Start-up time is the time period from the application of power to valid data at the output. Table 4.5. Regulatory Information1 CSA The Si86xx is certified under CSA Component Acceptance Notice 5A, IEC61010-1 and IEC60950-1. For more details, see File 232873. VDE The Si86xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001. UL The Si86xx is certified under UL1577 component recognition program. For more details, see File E257455. CQC The Si86xx is certified under GB4943.1-2011. For more details, see certificates CQC13001096110 and CQC13001096239. Note: 1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. For more information, see 5.5 Pin Descriptions (Si866x). Table 4.6. Insulation and Safety-Related Specifications Parameter Symbol Test Condition Value Unit WB SOIC-16 NB SOIC-16 NB SOIC-8 Nominal Air Gap (Clearance)1 L(IO1) 8.0 4.9 4.9 mm Nominal External Tracking (Creepage)1 L(IO2) 8.0 4.01 4.01 mm 0.014 0.014 0.014 mm Minimum Internal Gap (Internal Clearance) silabs.com | Building a more connected world. Rev. 1.02 | 25 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Value Unit WB SOIC-16 NB SOIC-16 NB SOIC-8 600 600 600 VRMS Tracking Resistance (Proof Tracking Index) PTI Erosion Depth ED 0.019 0.019 0.040 mm Resistance (Input-Output)2 RIO 1012 1012 1012 Capacitance (Input-Output)2 IO 2.0 2.0 2.0 pF Input Capacitance3 CI 4.0 4.0 4.0 pF IEC60112 f = 1 z Notes: 1. The values in this table correspond to the nominal creepage and clearance values. VDE certifies the clearance and creepage limits as 4.7 mm minimum for the NB SOIC-16 and SOIC-8 packages and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage minimum for component-level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC-16 and SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package. 2. To determine resistance and capacitance, the Si86xx is converted into a 2-terminal device. Pins 1-8 (Pins 1-4 for the NB SOIC-8) are shorted together to form the first terminal and pins 9-16 (Pins 5-8 for the NB SOIC-8) are shorted together to form the second terminal. The parameters are then measured between these two terminals. 3. Measured from input pin to ground. Table 4.7. IEC 60664-1 (VDE 0844 Part 2) Ratings Parameter Test Conditions Specification NB SOIC-16 WB SOIC-16 NB SOIC-8 Basic Isolation Group Installation Classification Material Group I I Rated Mains Voltages < 150 VRMS I-IV I-IV Rated Mains Voltages < 300 VRMS I-III I-IV Rated Mains Voltages < 400 VRMS I-II I-III Rated Mains Voltages < 600 VRMS I-II I-III Table 4.8. IEC 60747-5-2 Insulation Characteristics for Si86xxxx* Parameter Symbol Test Condition Characteristic WB SOIC-16 Unit NB SOIC-16 SOIC-8 Maximum Working Insulation Voltage VIORM Input to Output Test Voltage Transient Overvoltage 1200 630 VPR Method b1 (VIORM x 1.875 = VPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC) 2250 1182 VIOTM t = 60 sec 6000 6000 2 2 Pollution Degree (DIN VDE 0110, Table 1) silabs.com | Building a more connected world. Vpeak Vpeak Rev. 1.02 | 26 Si86xx Data Sheet Electrical Specifications Parameter Symbol Test Condition Characteristic WB SOIC-16 Unit NB SOIC-16 SOIC-8 Insulation Resistance at TS, VIO = 500 V RS >109 >109 Note: Maintenance of the safety data is ensured by protective circuits. The Si86xxxx provides a climate classification of 40/125/21. Table 4.9. IEC Safety Limiting Values1 Max Parameter Case Temperature Safety Input, Output, or Supply Current Symbol Test Condition WB SOIC-16 NB SOIC-16 NB SOIC-8 Unit 150 150 150 220 215 160 mA 415 415 150 mW TS S JA = 100 C/W (WB SOIC-16), 105 C/W (NB SOIC-16), 140 C/W (NB SOIC-8), VI = 5.5 V, TJ = 150 C, TA = 25 C Device Power Dissipation2 PD Notes: 1. Maximum value allowed in the event of a failure; also see the thermal derating curve in Figure 4.4 Figure 5.4 on page 28, Figure 4.5 Figure 5.5 on page 28 and Figure 4.6 Figure 5.6 on page 29. 2. The Si86xx is tested with VDD1 = VDD2 = 5.5 V, TJ = 150 C, CL = 15 pF, input a 150 Mbps 50% duty cycle square wave. Table 4.10. Thermal Characteristics Parameter IC Junction-to-Air Thermal Resistance silabs.com | Building a more connected world. Symbol WB SOIC-16 NB SOIC-16 NB SOIC-8 Unit JA 100 105 140 C/W Rev. 1.02 | 27 Si86xx Data Sheet Electrical Specifications Safety-Limiting Current (mA) 500 450 VDD1, VDD2 = 2.70 V 400 370 VDD1, VDD2 = 3.6 V 300 220 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (C) 150 200 Figure 4.4. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Safety-Limiting Current (mA) 500 430 VDD1, VDD2 = 2.70 V 400 360 VDD1, VDD2 = 3.6 V 300 215 200 VDD1, VDD2 = 5.5 V 100 0 0 50 100 Temperature (C) 150 200 Figure 4.5. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 silabs.com | Building a more connected world. Rev. 1.02 | 28 Si86xx Data Sheet Safety-Limiting Values (mA) Electrical Specifications 400 320 VDD1, VDD2 = 2.5 V 300 270 VDD1, VDD2 = 3.3 V 200 160 VDD1, VDD2 = 5.5 V 100 0 0 50 100 150 Case Temperature (C) 200 Figure 4.6. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN EN 60747-5-2 Table 4.11. Absolute Maximum Ratings1 Parameter Symbol Min Max Unit TSTG -65 150 C Ambient Temperature Under Bias TA -40 125 C Junction Temperature TJ -- 150 C VDD1, VDD2 -0.5 7.0 V Input Voltage VI -0.5 VDD + 0.5 V Output Voltage VO -0.5 VDD + 0.5 V Output Current Drive Channel (All devices unless otherwise stated) IO -- 10 mA Output Current Drive Channel (All Si86xxxA-x-xx devices) IO -- 22 mA Latchup Immunity3 -- 100 V/ns Lead Solder Temperature (10 s) -- 260 C Maximum Isolation (Input to Output) (1 sec) NB SOIC-16, SOIC-8 -- 4500 VRMS Maximum Isolation (Input to Output) (1 sec) WB SOIC-16 -- 6500 VRMS Storage Temperature2 Supply Voltage Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. VDE certifies storage temperature from -40 to 150 C. 3. Latchup immunity specification is for slew rate applied across GND1 and GND2. silabs.com | Building a more connected world. Rev. 1.02 | 29 Si86xx Data Sheet Pin Descriptions 5. Pin Descriptions 5.1 Pin Descriptions (Si861x/2x Narrow Body SOIC-8) VDD1 RF XMITR A1 VDD1/NC GND1 I s o l a t i o n VDD2 RF RCVR Si8610 NB SOIC-8 VDD1 GND2/NC A1 RF XMITR A2 RF XMITR B1 GND2 GND1 I s o l a t i o n VDD2 VDD1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF RCVR GND2 Si8620 NB SOIC-8 GND1 I s o l a t i o n VDD2 RF RCVR B1 RF XMITR B2 Si8621 NB SOIC-8 GND2 Figure 5.1. Si861x/2x Narrow Body SOIC-8 Pin Descriptions Table 5.1. Si861x/2x Narrow Body SOIC-8 Pin Descriptions Name SOIC-8 Pin# SOIC-8 Pin# Type Description Si861x Si862x VDD1/NC* 1,3 1 Supply Side 1 power supply. GND1 4 4 Ground Side 1 ground. A1 2 2 Digital I/O Side 1 digital input or output. A2 NA 3 Digital I/O Side 1 digital input or output. B1 6 7 Digital I/O Side 2 digital input or output. B2 NA 6 Digital I/O Side 2 digital input or output. VDD2 8 8 Supply Side 2 power supply. GND2/NC* 5, 7 5 Ground Side 2 ground. Note: No connect. These pins are not internally connected. They can be left floating, tied to VDD, or tied to GND. silabs.com | Building a more connected world. Rev. 1.02 | 30 Si86xx Data Sheet Pin Descriptions 5.2 Pin Descriptions (Si863x) VDD1 GND2 GND1 A1 RF XMITR A2 RF XMITR A3 RF XMITR NC I s o l a t i o n VDD2 GND2 GND1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF RCVR NC NC EN2 EN1 NC GND1 VDD1 VDD2 Si8630 GND2 I s o l a t i o n RF RCVR B1 RF RCVR B2 RF XMITR B3 NC EN2 GND1 GND2 Si8631 Figure 5.2. Si863x Pin Descriptions Table 5.2. Si863x Pin Descriptions Name SOIC-16 Pin# Type Description VDD1 1 Supply Side 1 power supply. GND1 21 Ground Side 1 ground. A1 3 Digital Input Side 1 digital input. A2 4 Digital Input Side 1 digital input. A3 5 Digital I/O NC 6 NA EN1/NC2 7 Digital Input GND1 81 Ground Side 1 ground. GND2 91 Ground Side 2 ground. EN2 10 Digital Input NC 11 NA B3 12 Digital I/O B2 13 Digital Output Side 2 digital output. B1 14 Digital Output Side 2 digital output. GND2 151 Ground Side 2 ground. VDD2 16 Supply Side 2 power supply. Side 1 digital input or output. No Connect. Side 1 active high enable. NC on Si8630 Side 2 active high enable. No Connect. Side 2 digital input or output. Notes: 1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be connected to external ground. 2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND. silabs.com | Building a more connected world. Rev. 1.02 | 31 Si86xx Data Sheet Pin Descriptions 5.3 Pin Descriptions (Si864x) VDD1 VDD2 GND2 GND1 A1 RF XMITR A2 RF XMITR A3 RF XMITR A4 RF XMITR I s o l a t i o n VDD2 GND2 GND1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF RCVR EN2 NC GND1 VDD1 GND2 Si8640 I s o l a t i o n VDD2 GND2 GND1 RF RCVR B1 A1 RF XMITR RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF RCVR RF XMITR B4 A4 RF RCVR EN2 EN1 GND1 VDD1 Si8641 GND2 I s o l a t i o n RF RCVR B1 RF RCVR B2 RF RF XMITR RCVR B3 RF XMITR B4 EN2 EN1 GND1 Si8642 GND2 Figure 5.3. Si864x Pin Descriptions Table 5.3. Si864x Pin Descriptions Name SOIC-16 Pin# Type Description VDD1 1 Supply Side 1 power supply. GND1 21 Ground Side 1 ground. A1 3 Digital Input Side 1 digital input. A2 4 Digital Input Side 1 digital input. A3 5 Digital I/O Side 1 digital input or output. A4 6 Digital I/O Side 1 digital input or output. EN1/NC2 7 Digital Input GND1 81 Ground Side 1 ground. GND2 91 Ground Side 2 ground. EN2 10 Digital Input B4 11 Digital I/O Side 2 digital input or output. B3 12 Digital I/O Side 2 digital input or output. B2 13 Digital Output Side 2 digital output. B1 14 Digital Output Side 2 digital output. GND2 151 Ground Side 2 ground. VDD2 16 Supply Side 2 power supply. Side 1 active high enable. NC on Si8640. Side 2 active high enable. Notes: 1. For narrow-body devices, Pin 2 and Pin 8 GND must be externally connected to respective ground. Pin 9 and Pin 15 must also be connected to external ground. 2. No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND. silabs.com | Building a more connected world. Rev. 1.02 | 32 Si86xx Data Sheet Pin Descriptions 5.4 Pin Descriptions (Si8650/51/52) VDD1 VDD2 RF XMITR A1 A2 RF XMITR A3 RF XMITR A4 RF XMITR A5 RF XMITR I s o l a t i o n VDD2 RF RCVR B1 RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF XMITR RF RCVR B5 A5 RF RCVR EN2 NC GND1 VDD1 GND2 Si8650 RF XMITR A1 I s o l a t i o n VDD2 RF RCVR B1 RF RCVR B2 A2 RF XMITR RF RCVR B3 A3 RF XMITR RF RCVR B4 A4 RF RCVR RF XMITR B5 A5 RF RCVR EN2 EN1 GND1 VDD1 Si8651 GND2 RF XMITR A1 I s o l a t i o n RF RCVR B1 RF RCVR B2 RF RCVR B3 RF RF XMITR RCVR B4 RF XMITR B5 EN2 EN1 GND1 Si8652 GND2 Figure 5.4. Si865x Pin Descriptions Table 5.4. Si865x Pin Descriptions Name SOIC-16 Pin# Type Description VDD1 1 Supply A1 2 Digital Input Side 1 digital input. A2 3 Digital Input Side 1 digital input. A3 4 Digital Input Side 1 digital input. A4 5 Digital I/O Side 1 digital input or output. A5 6 Digital I/O Side 1 digital input or output. EN1/NC* 7 Digital Input GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. EN2 10 Digital Input B5 11 Digital I/O Side 2 digital input or output. B4 12 Digital I/O Side 2 digital input or output. B3 13 Digital Output Side 2 digital output. B2 14 Digital Output Side 2 digital output. B1 15 Digital Output Side 2 digital output. VDD2 16 Supply Side 2 power supply. Side 1 power supply. Side 1 active high enable. NC on Si8650. Side 2 active high enable. Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND. silabs.com | Building a more connected world. Rev. 1.02 | 33 Si86xx Data Sheet Pin Descriptions 5.5 Pin Descriptions (Si866x) VDD1 VDD1 VDD2 A1 RF XMITR A2 RF XMITR A3 RF XMITR A4 RF XMITR A5 RF XMITR A6 RF XMITR GND1 I s o l a t i o n Si8660 RF RCVR RF RCVR RF RCVR RF RCVR VDD2 A1 RF XMITR B2 A2 RF XMITR B3 A3 RF XMITR A4 RF XMITR B1 B4 RF RCVR B5 A5 RF XMITR RF RCVR B6 A6 RF RCVR GND2 GND1 I s o l a t i o n RF RCVR RF RCVR RF RCVR RF RCVR RF RCVR RF XMITR VDD1 A1 RF XMITR B2 A2 RF XMITR B3 A3 RF XMITR B1 A4 RF XMITR B5 A5 RF RCVR B6 A6 RF RCVR B4 GND2 GND1 Si8661 VDD2 I s o l a t i o n RF RCVR RF RCVR RF RCVR VDD2 A1 RF XMITR B2 A2 RF XMITR B3 A3 RF XMITR A4 RF RCVR B1 RF RCVR VDD1 B4 RF XMITR B5 A5 RF RCVR RF RF XMITR RCVR B6 A6 RF RCVR GND2 GND1 Si8662 I s o l a t i o n RF RCVR B1 RF RCVR B2 RF RCVR B3 RF XMITR B4 RF XMITR B5 RF RF XMITR RCVR B6 Si8663 GND2 Figure 5.5. Si866x Pin Descriptions Table 5.5. Si866x Pin Descriptions Name SOIC-16 Pin# Type VDD1 1 Supply A1 2 Digital Input Side 1 digital input. A2 3 Digital Input Side 1 digital input. A3 4 Digital Input Side 1 digital input. A4 5 Digital I/O Side 1 digital input or output. A5 6 Digital I/O Side 1 digital input or output. A6 7 Digital I/O Side 1 digital input or output. GND1 8 Ground Side 1 ground. GND2 9 Ground Side 2 ground. B6 10 Digital I/O Side 2 digital input or output. B5 11 Digital I/O Side 2 digital input or output. B4 12 Digital I/O Side 2 digital input or output. B3 13 Digital Output Side 2 digital output. B2 14 Digital Output Side 2 digital output. B1 15 Digital Output Side 2 digital output. VDD2 16 Supply Side 2 power supply. silabs.com | Building a more connected world. Description Side 1 power supply. Rev. 1.02 | 34 Si86xx Data Sheet Package Outlines 6. Package Outlines 6.1 Package Outline (16-Pin Wide Body SOIC) The figure below illustrates the package details for the Si86xx Digital Isolator. The table below lists the values for the dimensions shown in the illustration. Figure 6.1. 16-Pin Wide Body SOIC silabs.com | Building a more connected world. Rev. 1.02 | 35 Si86xx Data Sheet Package Outlines Table 6.1. Package Diagram Dimensions Dimension Min Max A -- 2.65 A1 0.10 0.30 A2 2.05 -- b 0.31 0.51 c 0.20 0.33 D 10.30 BSC E 10.30 BSC E1 7.50 BSC e 1.27 BSC L 0.40 1.27 h 0.25 0.75 0 8 aaa -- 0.10 bbb -- 0.33 ccc -- 0.10 ddd -- 0.25 eee -- 0.10 fff -- 0.20 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC Outline MS-013, Variation AA. 4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components. silabs.com | Building a more connected world. Rev. 1.02 | 36 Si86xx Data Sheet Package Outlines 6.2 Package Outline (16-Pin Narrow Body SOIC) The figure below illustrates the package details for the Si86xx in a 16-pin narrow-body SOIC (SO-16). The table below lists the values for the dimensions shown in the illustration. Figure 6.2. 16-pin Small Outline Integrated Circuit (SOIC) Package silabs.com | Building a more connected world. Rev. 1.02 | 37 Si86xx Data Sheet Package Outlines Table 6.2. Package Diagram Dimensions Dimension Min Max A -- 1.75 A1 0.10 0.25 A2 1.25 -- b 0.31 0.51 c 0.17 0.25 D 9.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 L2 1.27 0.25 BSC h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. silabs.com | Building a more connected world. Rev. 1.02 | 38 Si86xx Data Sheet Package Outlines 6.3 Package Outline (8-Pin Narrow Body SOIC) The figure below illustrates the package details for the Si86xx. The table below lists the values for the dimensions shown in the illustration. Figure 6.3. 8-pin Small Outline Integrated Circuit (SOIC) Package Table 6.3. Package Diagram Dimensions Symbol Millimeters Min Max A 1.35 1.75 A1 0.10 0.25 A2 1.40 REF 1.55 REF B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 silabs.com | Building a more connected world. Rev. 1.02 | 39 Si86xx Data Sheet Land Patterns 7. Land Patterns 7.1 Land Pattern (16-Pin Wide-Body SOIC) The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin wide-body SOIC. The table below lists the values for the dimensions shown in the illustration. Figure 7.1. 16-Pin SOIC Land Pattern Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 9.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.90 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.02 | 40 Si86xx Data Sheet Land Patterns 7.2 Land Pattern (16-Pin Narrow Body SOIC) The figure below illustrates the recommended land pattern details for the Si86xx in a 16-pin narrow-body SOIC. The table below lists the values for the dimensions shown in the illustration. Figure 7.2. 16-Pin Narrow Body SOIC PCB Land Pattern Table 7.2. 16-Pin Narrow Body SOIC Land Pattern Dimensions Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.02 | 41 Si86xx Data Sheet Land Patterns 7.3 Land Pattern (8-Pin Narrow Body SOIC) The figure below illustrates the recommended land pattern details for the Si86xx in an 8-pin narrow-body SOIC. The table below lists the values for the dimensions shown in the illustration. Figure 7.3. PCB Land Pattern: 8-Pin Narrow Body SOIC Table 7.3. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC) Dimension Feature (mm) C1 Pad Column Spacing 5.40 E Pad Row Pitch 1.27 X1 Pad Width 0.60 Y1 Pad Length 1.55 Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed. silabs.com | Building a more connected world. Rev. 1.02 | 42 Si86xx Data Sheet Top Markings 8. Top Markings 8.1 Top Marking (16-Pin Wide Body SOIC) Si86XYSV YYWWRTTTTT e4 CC Figure 8.1. 16-Pin Wide Body SOIC Table 8.1. Top Marking Explanation (16-Pin Wide Body SOIC) Line 1 Marking: Base Part Number Ordering Options (See 1. Ordering Guide for more information). Si86 = Isolator product series XY = Channel Configuration X = # of data channels (5, 4, 3, 2, 1) Y = # of reverse channels (2, 1, 0) S = Speed Grade (max data rate) and operating mode: A = 1 Mbps (default output = low) B = 150 Mbps (default output = low) D = 1 Mbps (default output = high) E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV; D = 5.0 kV Line 2 Marking: YY = Year WW = Workweek RTTTTT = Mfg Code Assigned by assembly subcontractor. Corresponds to the year and work week of the mold date. Manufacturing code from assembly house "R" indicates revision Line 3 Marking: Circle = 1.7 mm Diameter "e4" Pb-free symbol (Center-Justified) Country of Origin ISO Code Abbreviation silabs.com | Building a more connected world. CC = Country of Origin ISO Code Abbreviation * TW = Taiwan * TH = Thailand Rev. 1.02 | 43 Si86xx Data Sheet Top Markings 8.2 Top Marking (16-Pin Narrow Body SOIC) e3 Si86XYSV YYWWRTTTTT Figure 8.2. 16-Pin Narrow Body SOIC Table 8.2. Top Marking Explanation (16-Pin Narrow Body SOIC) Line 1 Marking: Base Part Number Ordering Options (See 1. Ordering Guide for more information.) Si86 = Isolator product series XY = Channel Configuration X = # of data channels (5, 4, 3, 2, 1) Y = # of reverse channels (2, 1, 0) S = Speed Grade (max data rate) and operating mode: A = 1 Mbps (default output = low) B = 150 Mbps (default output = low) D = 1 Mbps (default output = high) E = 150 Mbps (default output = high) V = Insulation rating A = 1 kV; B = 2.5 kV; C = 3.75 kV Line 2 Marking: Circle = 1.2 mm Diameter YY = Year WW = Work Week RTTTTT = Mfg Code "e3" Pb-Free Symbol Assigned by the assembly subcontractor. Corresponds to the year and work week of the mold date. Manufacturing code from assembly house "R" indicates revision silabs.com | Building a more connected world. Rev. 1.02 | 44 Si86xx Data Sheet Top Markings 8.3 Top Marking (8-Pin Narrow Body SOIC) Si86XYSV YYWWRT e3 TTTT Figure 8.3. 8-Pin Narrow Body SOIC Table 8.3. Top Marking Explanation (8-Pin Narrow Body SOIC) Line 1 Marking: Base Part Number Si86 = Isolator Product Series Ordering Options XY = Channel Configuration (See 1. Ordering Guide for more information). S = Speed Grade (max data rate) V = Insulation rating Line 2 Marking: YY = Year WW = Workweek Assigned by assembly subcontractor. Corresponds to the year and workweek of the mold date. R = Product Revision T = First character of the manufacturing code Line 3 Marking: Circle = 1.1 mm Diameter TTTT = Last four characters of the manufacturing code silabs.com | Building a more connected world. "e3" Pb-Free Symbol. Last four characters of the manufacturing code. Rev. 1.02 | 45 Si86xx Data Sheet Revision History 9. Revision History Revision 1.02 February 2018 * Added SI8641AB-AS1 and SI8642AB-AS1 to Ordering Guide for Automotive-Grade OPN options Revision 1.01 January 2018 * Updated data sheet format. * Added new table to Ordering Guide for Automotive-Grade OPN options * Updated Table 4.5 Regulatory Information1 on page 25. * Added CQC certificate numbers. * Updated 1. Ordering Guide. * Removed references to moisture sensitivity levels. * Removed note 2. silabs.com | Building a more connected world. Rev. 1.02 | 46 Smart. Connected. Energy-Friendly. Products Quality Support and Community www.silabs.com/products www.silabs.com/quality community.silabs.com Disclaimer Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. 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