Consumer Systems Group Communications and Advanced Consumer Technologies Group ColdFire 2/2M Addendum to ColdFire 2/2M User Manual April 14, 1998 This addendum to the ColdFire 2/2M UserOs Manual provides corrections to the original text, plus additional information not included in the original. This document and other information on this product is maintained on the World Wide Web at http://sps.motorola.com/coldfire. Instruction Set Architecture The Instruction Set Summary shown on pages 1-19 through 1-23 should be replaced with the following : Notational Conventions OPCODE WILDCARDS cc Logical Condition (example: NE for not equal) An Ay,Ax Dn Dy,Dx Rn Ry,Rx Rw Rc Any Address Register n (example: A3 is address register 3) Source and destination address registers, respectively Any Data Register n (example: D5 is data register 5) Source and destination data registers, respectively Any Address or Data Register Any source and destination registers, respectively Any second destination register Any Control Register (example VBR is the vector base register) REGISTER OPERANDS REGISTER/PORT NAMES ACC DDATA CCR MACSR MASK PC PST SR MAC Accumulator Debug Data Port Condition Code Register (lower byte of status register) MAC Status Register Mask Register Program Counter Processor Status Port Status Register MISCELLANEOUS OPERANDS #<data> <ea> Immediate data following the instruction word(s) Effective Address This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. SEMICONDUCTOR PRODUCT INFORMATION O 1998 Motorola, Inc. All Rights Reserved. Revision 0.0 Notational Conventions (Continued) <ea>y,<ea>x <label> <list> <size> Source and Destination Effective Addresses, respectively Assembly Program Label List of registers (example: D3D0) Operand data size: Byte (B), Word (W), Longword (L) + x / ~ & | ~ << >> (R) (R) sign-extended If <condition> then <operations> else <operations> Arithmetic addition or postincrement indicator Arithmetic subtraction or predecrement indicator Arithmetic multiplication Arithmetic division Invert; operand is logically complemented Logical AND Logical OR Logical exclusive OR Shift left (example: D0 << 3 is shift D0 left 3 bits) Shift right (example: D0 >> 3 is shift D0 right 3 bits) Source operand is moved to destination operand Two operands are exchanged All bits of the upper portion are made equal to the high-order bit of the lower portion Test the condition. If true, the operations after OthenO are performed. If the condition is false and the optional OelseO clause is present, the operations after OelseO are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example. OPERATIONS SUBFIELDS AND QUALIFIERS {} () dn Optional Operation Identifies an indirect address Displacement Value, n-Bits Wide (example: d16 is a 16-bit displacement) Address Bit LSB LSW MSB MSW Calculated Effective Address (pointer) Bit Selection (example: Bit 3 of D0) Least Significant Bit (example: MSB of D0) Least Significant Word Most Significant Bit Most Significant Word CONDITION CODE REGISTER BIT NAMES P C N V X Z 2 Branch Prediction Bit in CCR Carry Bit in CCR Negative Bit in CCR Overflow Bit in CCR Extend Bit in CCR Zero Bit in CCR COLDFIRE 2/2M USEROS MANUAL ADDENDUM MOTOROLA Instruction Set Summary INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION ADD Dy,<ea>x <ea>y,Dx <ea>y,Ax #<data>,Dx #<data>,<ea>x Dy,Dx Dy,<ea>x <ea>y,Dx #<data>,Dx Dx,Dy #<data>,Dx Dx,Dy <data>,Dx <label> 32 32 Source + Destination (R) Destination 32 32 32 32 32 32 Source + Destination (R) Destination Immediate Data + Destination (R) Destination Immediate Data + Destination (R) Destination Source + Destination + X (R) Destination Source & Destination (R) Destination 32 32 32 32 32 8,16 Immediate Data & Destination (R) Destination X/C (Dy << Dx) 0 X/C (Dy << #<data>) 0 BCHG Dy,<ea>x #<data>,<ea>x 8,32 8,32 BCLR Dy,<ea>x #<data>,<ea>x 8,32 8,32 BRA <label> 8,16 ~(<Bit Number> of Destination) (R) Z, Bit of Destination ~(<Bit Number> of Destination) (R) Z; 0 (R) Bit of Destination PC + dn (R) PC BSET Dy,<ea>x #<data>,<ea>x 8,32 8,32 ADDA ADDI ADDQ ADDX AND ANDI ASL ASR Bcc BSR <label> 8,16 BTST CLR CMPI CMP CMPA CPUSH DIVS Dy,<ea>x #<data>,<ea>x <ea>x #<data>,Dx <ea>y,Dx <ea>y,Ax (An) <ea>y,Dx 8,32 8,32 8,16,32 32 32 32 32 16 32 DIVU <ea>y,Dx 16 EOR EORI EXT Dy,<ea>x #<data>,Dx Dx Dx Dx none <ea> <ea> <ea>y,Ax Ax,#<data> Dx,Dy #<data>,Dx Dx,Dy #<data>,Dx 32 32 8 (R) 16 16 (R) 32 8 (R) 32 none none 32 32 16 32 32 32 32 EXTB HALT JMP JSR LEA LINK LSL LSR MOTOROLA MSB (R) (Dy >> Dx) (R) X/C MSB (R) (Dy >> #<data>) (R) X/C If Condition True, Then PC + dn (R) PC ~(<Bit Number> of Destination) (R) Z; 1(R) Bit of Destination SP 4 (R) SP; next sequential PC(R) (SP); PC + dn (R) PC ~(<Bit Number> of Destination) (R) Z 0 (R) Destination Destination Immediate Data Destination Source Destination - Source Push and Invalidate Cache Line Dx / <ea>y (R) Dx {16-bit Remainder; 16-bit Quotient} Dx / <ea>y (R) Dx {32-bit Quotient} Signed operation Dx / <ea>y (R) Dx {16-bit Remainder; 16-bit Quotient} Dx / <ea>y (R) Dx {32-bit Quotient} Unsigned operation Source ~ Destination (R) Destination Immediate Data ~ Destination (R) Destination Sign-Extended Destination (R) Destination Sign-Extended Destination (R) Destination Enter Halted State Address of <ea> (R) PC SP 4 (R) SP; next sequential PC (R) (SP); <ea> (R) PC <ea> (R) Ax SP 4 (R) SP; Ax (R) (SP); SP (R) Ax; SP + d16 (R) SP X/C (Dy << Dx) 0 X/C (Dx << #<data>) 0 0 (R) (Dy >> Dx) (R) X/C 0 (R) (Dx >> #<data>) (R) X/C COLDFIRE 2/2M USEROS MANUAL ADDENDUM 3 Instruction Set Summary (Continued) INSTRUCTION OPERAND SYNTAX MAC Ry,Rx <shift> Ry,Rx<shift>,<ea>y,Rw MACL Ry,Rx<shift> Ry,Rx,<shift>,<ea>y,Rw MOVE <ea>y,<ea>x MOVE from ACC ACC,Rx MOVE from CCR Dx MOVE from MACSR MACSR,Rx MACSR,CCR MOVE from MASK MASK,Rx MOVE from SR Dx MOVE to ACC Ry,ACC <#<data>,ACC MOVE to CCR Dy,CCR #<data>,CCR MOVE to MACSR Ry,MACSR #<data>,MACSR MOVE to MASK Ry,MASK #<data>,MASK MOVE to SR Dy,SR #<data>,SR MOVEA <ea>y,Ax MOVEC Ry,Rc MOVEM list,<ea>x <ea>y,list MOVEQ #<data>,Dx MSAC Ry,Rx<shift> Ry,Rx<shift>,<ea>y,Rw MSACL Ry,Rx<shift> Ry,Rx<shift>,<ea>y,Rw MULS <ea>y,Dx 4 OPERAND SIZE OPERATION 16 16 + 32 (R) 32 32 (R) 32 32 32 + 32 (R) 32 32 (R) 32 8,16,32 32 16 32 8 ACC + (Ry Rx){<< 1 | >> 1} (R) ACC ACC + (Ry Rx){<< 1 | >> 1} (R) ACC; (<ea>y{&MASK}) (R) Rw ACC + (Ry Rx){<< 1 | >> 1} (R) ACC ACC + (Ry Rx){<< 1 | >> 1} (R) ACC; (<ea>y{&MASK}) (R) Rw <ea>y (R) <ea>x ACC (R) Rx CCR (R) Dx MACSR (R) Rx MACSR (R)CCR MASK (R) Rx SR (R) Dx Ry (R) ACC #<data> (R) ACC Dy (R) CCR #<data> (R) CCR Ry (R) MACSR #<data> (R) MACSR Ry (R) MASK #<data> (R) MASK Source (R) SR 32 16 32 32 8 32 32 32 16 16,32 (R) 32 32 32 32 8 (R) 32 32 - 16 16 (R) 32 32 (R) 32 32 - 32 32 (R) 32 32 (R) 32 16 x 16 (R) 32 32 x 32 (R) 32 16 x 16 (R) 32 32 x 32 (R) 32 32 32 none 32 32 MULU <ea>y,Dx NEG NEGX NOP NOT OR ORI PEA PULSE REMS <ea>x <ea>x none <ea> Dy,<ea>x <ea>y,Dx #<data>,Dx <ea> none <ea>y,Dx:Dw REMU <ea>y,Dx:Dw 32 RTE RTS Scc none none Dx none none 8 STOP #<data> 16 32 32 none 32 Source (R) Destination Ry (R) Rc Listed Registers (R) Destination Source (R) Listed Registers Sign-extended Immediate Data(R) Destination ACC - (Ry Rx){<< 1 | >> 1} (R) ACC ACC - (Ry Rx){<< 1 | >> 1} (R) ACC, (<ea>y{&MASK}) (R) Rw ACC - (Rw Rx){<< 1 | >> 1} (R) ACC ACC - (Rw Rx){<< 1 | >> 1} (R) ACC; (<ea>y{&MASK}) (R) Rw Source Destination (R) Destination Signed operation Source Destination (R) Destination Unsigned operation 0 Destination (R) Destination 0 Destination X (R) Destination PC + 2 (R) PC; Synchronize Pipelines ~ Destination (R) Destination Source | Destination (R) Destination Immediate Data | Destination (R) Destination SP 4 (R) SP; Address of <ea> (R) (SP) Set PST= $4 Dx/<ea>y (R) Dw {32-bit Remainder} Signed operation Dx/<ea>y (R) Dw {32-bit Remainder} Unsigned operation (SP+2) (R) SR; SP+4 (R) SP; (SP) (R) PC; SP + FormatField (R) SP (SP) (R) PC; SP + 4 (R) SP If Condition True, Then 1's (R) Destination; Else 0's (R) Destination Immediate Data (R) SR; Enter Stopped State COLDFIRE 2/2M USEROS MANUAL ADDENDUM MOTOROLA Instruction Set Summary (Continued) INSTRUCTION OPERAND SYNTAX OPERAND SIZE OPERATION SUB Dy,<ea>x <ea>y,Dx <ea>y,Ax #<data>,Dx #<data>,<ea>x Dy,Dx Dn none 32 32 32 32 32 32 16 none Destination - Source(R) Destination TRAPF none #<data> none 16 32 TST UNLK WDDATA WDEBUG <ea>y Ax <ea>y <ea>y 8,16,32 32 8,16,32 2 x 32 SUBA SUBI SUBQ SUBX SWAP TRAP MOTOROLA Destination - Source(R) Destination Destination Immediate Data (R) Destination Destination - Immediate data (R) Destination Destination Source X (R) Destination MSW of Dn (R) LSW of Dn SP 4 (R) SP;PC (R) (SP); SP 2 (R) SP;SR (R) (SP); SP 2 (R) SP; Format (R) (SP); Vector Address (R) PC PC + 2 (R) PC PC + 4 (R) PC PC + 6 (R) PC Set Condition Codes Ax (R)SP; (SP) (R) Ax; SP + 4 (R) SP <ea>y (R)DDATA port <ea>y (R) Debug Module COLDFIRE 2/2M USEROS MANUAL ADDENDUM 5 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. SEMICONDUCTOR PRODUCT INFORMATION