40V Precision Low Power Operational Amplifiers ISL28117, ISL28217, ISL28417 Features The ISL28117, ISL28217 and ISL28417 are a family of very high precision amplifiers featuring low noise vs power consumption, low offset voltage, low IBIAS current and low temperature drift making them the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. * Low Input Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V, Max. Applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls, and industrial controls. * Voltage Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8nV/Hz The ISL28117 single and ISL28217 dual are offered in an 8 Ld SOIC, MSOP and TDFN packages. The ISL28417 is offered in 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN packages. All devices are offered in standard pin configurations and operate over the extended temperature range from -40C to +125C. * Operating Temperature Range. . . . . . . . . . .-40C to +125C Related Literature * Superb Offset TC . . . . . . . . . . . . . . . . . . . . . . . 0.6V/C, Max. * Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 1nA, Max. * Input Bias Current TC. . . . . . . . . . . . . . . . . . . . .5pA/C, Max. * Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 440A * Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V * Small Package Offerings in Single, Dual and Quad * Pb-Free (RoHS Compliant) Applications * Precision Instruments * See AN1508 "ISL281X7SOICEVAL1Z Evaluation Board User's Guide" * See AN1509 "ISL282X7SOICEVAL2Z Evaluation Board User's Guide" * Medical Instrumentation * Spectral Analysis Equipment * Active Filter Blocks * Thermocouples and RTD Reference Buffers * Data Acquisition * Power Supply Control 18 VS = 15V C1 8.2nF V+ - VIN R1 OUTPUT R2 + 1.84k 4.93k 3.3nF C2 FIGURE 1. TYPICAL APPLICATION 1 14 12 10 8 6 4 2 V- SALLEN-KEY LOW PASS FILTER (10kHz) March 23, 2012 FN6632.9 NUMBER OF AMPLIFIERS 16 0 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 VOSTC (V/C) FIGURE 2. VOS TEMPERATURE COEFFICIENT (VOSTC) CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009-2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28117, ISL28217, ISL28417 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VOS (MAX) (V) PACKAGE (Pb-Free) PKG. DWG. # ISL28117FBBZ 28117 FBZ 50 (B Grade) 8 Ld SOIC M8.15E ISL28117FBZ 28117 FBZ -C 100 (C Grade) 8 Ld SOIC M8.15E ISL28117FUBZ 8117Z 70 (B Grade) 8 Ld MSOP M8.118B ISL28117FUZ 8117Z -C 150 (C Grade) 8 Ld MSOP M8.118B ISL28117FRTBZ 8117 75 (B Grade) 8 Ld TDFN L8.3x3K ISL28117FRTZ -C 8117 150 (C Grade) 8 Ld TDFN L8.3x3K ISL28217FBBZ 28217 FBZ 50 (B Grade) 8 Ld SOIC M8.15E ISL28217FBZ 28217 FBZ -C 100 (C Grade) 8 Ld SOIC M8.15E Coming Soon ISL28217FUBZ 8217Z TBD (B Grade) 8 Ld MSOP M8.118B ISL28217FUZ 8217Z -C 150 (C Grade) 8 Ld MSOP M8.118B ISL28217FRTBZ 8217 70 (B Grade) 8 Ld TDFN L8.3x3K ISL28217FRTZ -C 8217 150 (C Grade) 8 Ld TDFN L8.3x3K ISL28417FBBZ 28417 FBZ 120 (B Grade) 14 Ld SOIC MDP0027 ISL28417FBZ 28417 FBZ -C 200 (C Grade) 14 Ld SOIC MDP0027 ISL28417FVBZ 28417 FVZ 120 (B Grade) 14 Ld TSSOP M14.173 ISL28417FVZ 28417 FVZ-C 200 (C Grade) 14 Ld TSSOP M14.173 Coming Soon ISL28417FRZ 28 417FRZ 16 Ld QFN L16.4x4E ISL28117SOICEVAL1Z Evaluation Board ISL28217SOICEVAL2Z Evaluation Board -40 to +125 NOTES: 1. Add "-T*" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217, ISL28417. For more information on MSL please see techbrief TB363. 2 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Pin Configurations ISL28117 (8 LD TDFN) TOP VIEW ISL28117 (8 LD SOIC, MSOP) TOP VIEW NC 1 8 NC -IN 2 7 V+ +IN 3 6 VOUT V- 4 5 NC NC 1 8 NC -IN 2 6 VOUT 5 NC V- 4 ISL28217 (8 LD TDFN) TOP VIEW ISL28217 (8 LD SOIC, MSOP) TOP VIEW 3 V- 4 - + + - 7 VOUT_B -IN_A 2 6 -IN_B +IN_A 3 5 +IN_B V- 4 8 V+ 5 +IN_B ISL28417 (16 LD QFN) TOP VIEW +IN_A 3 VOUT_A 16 11 V- 10 +IN_C +IN_B 5 -IN_B 6 12 +IN_D - + B + C -IN_A 13 12 -IN_D D A +IN_A 2 V+ 3 9 -IN_C 10 V + - 4 11 +IN_D C B +IN_B 3 14 1 8 VOUT_C VOUT_B 7 15 - + V+ 4 13 -IN_D 5 6 VOUT_B D + - - + A - + NC 14 VOUT_D -IN_B -IN_A 2 6 -IN_B + - ISL28417 (14 LD SOIC, TSSOP) TOP VIEW VOUT_A 1 7 VOUT_B - + NC 2 VOUT_A 1 + - -IN_A +IN_A 8 V+ 9 7 8 -IN_C 1 VOUT_D VOUT_A 7 V+ - + +IN 3 VOUT_C - + +IN_C March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Pin Descriptions ISL28117 (8 LD SOIC, MSOP, TDFN) ISL28217 (8 LD SOIC, MSOP, TDFN) ISL28417 (14 LD SOIC, TSSOP) ISL28417 (16 LD QFN) PIN NAME EQUIVALENT CIRCUIT 3 - - - +IN Circuit 1 Amplifier non-inverting input - 3 3 2 +IN_A - 5 5 4 +IN_B - - 10 9 +IN_C - - 12 11 +IN_D 4 4 11 10 V- Circuit 3 Negative power supply 2 - - - -IN Circuit 1 Amplifier inverting input - 2 2 1 -IN_A - 6 6 5 -IN_B - - 9 8 -IN_C - - 13 12 -IN_D 7 8 4 3 V+ Circuit 3 Positive power supply 6 - - - VOUT Circuit 2 Amplifier output - 1 1 15 VOUT_A - 7 7 6 VOUT_B - - 8 7 VOUT_C - - 14 14 VOUT_D 1, 5, 8 - - 13, 16 NC - No internal connection PD PD - PD PD - Thermal Pad - TDFN and QFN packages only. Connect thermal pad to ground or most negative potential. V+ 500 V+ 500 IN- IN+ VCIRCUIT 2 4 V+ CAPACITIVELY COUPLED ESD CLAMP OUT V- CIRCUIT 1 DESCRIPTION V- CIRCUIT 3 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Table of Contents Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications VS 15V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications VS 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISL28117, ISL28217 and ISL28417 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . License Statement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 19 19 19 19 19 20 20 20 Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package Outline Drawing (M8.15E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Package Outline Drawing (M8.118B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline Drawing (L8.3x3K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Outline Drawing (MDP0027) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outline Drawing (M14.173). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Package Outline Drawing (L16.4x4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ....42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V Max/Min Input current for Input Voltage >V+ or 130dB over-temperature. The minimum CMRR performance over the -40C to +125C temperature range is >120dB for power supply voltages from 5V (10V) to 15V (30V). Input Performance The super-beta NPN input pair provides excellent frequency response while maintaining high input precision. High NPN beta (>1000) reduces input bias current while maintaining good frequency response, low input bias current and low noise. Input bias cancellation circuits provide additional bias current reduction to <1nA, and excellent temperature stabilization. Figures 11 through 18 show the high degree of bias current stability at 5V and 15V supplies that is maintained across the -40C to +125C temperature range. The low bias current TC also produces very low input offset current TC, which reduces DC input offset errors in precision, high impedance amplifiers. The +25C maximum input offset voltage (VOS) for the "B" grade is 50V and 100V for the "C" grade. Input offset voltage temperature coefficients (VOSTC) are a maximum of 0.6V/C for the "B" and 0.9V/C for the "C" grade. Figures 3 through 6 show the typical gaussian-like distribution over the 5V to 15V supply range and over the full temperature range. The VOS temperature behavior is smooth (Figures 7 through 10) maintaining constant TC across the entire temperature range. Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails, series connected 500 current limiting resistors and an anti-parallel diode pair across the inputs (Figure 53). - 500 VIN VOUT + 500 RL V- FIGURE 53. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN The series resistors limit the high feed-through currents that can occur in pulse applications when the input dV/dT exceeds the 0.5V/s slew rate of the amplifier. Without the series resistors, the input can forward-bias the anti-parallel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. Figure 48 provides an example of distortion free large signal response using a 4VP-P input pulse with an input rise time of <1ns. The series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40V) without damage. In applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails, current limiting resistors may be needed at the input terminal to limit the current through the power supply ESD diodes to 20mA max. Output Current Limiting The output current is internally limited to approximately 45mA at +25C and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only 1 amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long term reliability. Figures 27 and 28 show the current limit variation with temperature. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28117, ISL28217 and ISL28417 are immune to output phase reversal, even when the input voltage is 1V beyond the supplies. Unused Channels The ISL28217 is a dual op-amp. If the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel oscillates if the input and output pins are floating. This results in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the inverting input and ground the positive input, as shown in Figure 54. - + FIGURE 54. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 19 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Power Dissipation License Statement It is possible to exceed the +150C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: The information in this SPICE model is protected under the United States copyright laws. Intersil Corporation hereby grants users of this macro-model hereto referred to as "Licensee", a nonexclusive, nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. (EQ. 1) T JMAX = T MAX + JA xPD MAXTOTAL where: * PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) * PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S x I qMAX + ( V S - V OUTMAX ) x -----------------------R L (EQ. 2) where: * TMAX = Maximum ambient temperature * JA = Thermal resistance of the package * PDMAX = Maximum power dissipation of 1 amplifier * VS = Total supply voltage The Licensee may not sell, loan, rent, or license the macromodel, in whole, in part, or in modified form, to anyone outside the Licensee's company. The Licensee may modify the macromodel to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided "AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE." In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. * IqMAX = Maximum quiescent supply current of 1 amplifier * VOUTMAX = Maximum output voltage swing of the application ISL28117, ISL28217 and ISL28417 SPICE Model Figure 55 shows the SPICE model schematic and Figure 56 shows the net list for the ISL28117, ISL28217 and ISL28417 SPICE model for a Grade "B" part. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC parameters are VOS, IOS, total supply current and output voltage swing. The model uses typical parameters given in the "Electrical Specifications" Table beginning on page 6. The AVOL is adjusted for 155dB with the dominate pole at 0.02Hz. The CMRR is set (210dB, fcm = 10Hz). The input stage models the actual device to present an accurate AC representation. The model is configured for ambient temperature of +25C. Figures 57 through 67 show the characterization vs simulation results for the Noise Voltage, Closed Loop Gain vs Frequency, Closed Loop Gain vs RL, Large Signal Step Response, Open Loop Gain Phase and Simulated CMRR vs Frequency. 20 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 . V++ V++ R3 R4 4.45k 4.45k 4 CASCODE 5 Q4 C4 2pF Vin- VIN- - + D1 3 SUPERB DX EOS 1 IOS Mirror VCM + - 5E11 + - En Vmid 9 IEE 200E-6 R2 Vc + - + - Q3 0.3nA 290 C5 2pF 8 7 5E11 C6 1.2pF R17 In+ VIN+ 5 6 R1 0.1V 25 4 Q1 Q2 24 DN CASCODE Q5 2 SUPERB V5 D12 IEE1 96E-6 + VOS - 13E-6 V-VCM Voltage Noise Input Stage V++ V++ 10 + - 4 5 D2 DX + V1 - 1.86V G3 13 + - R5 1 D4 DX + V3 - 1.86V 11 G5 R7 1.99e10 Vg 12 - R8 G4 V2 1.86V + + - + D3 DX + V-VCM R6 1 G2 1ST Gain Stage 14 - 17 Vc 1.99e10 V4 1.86V R10 2.1E3 C3 400pF 15.9159E R11 1 Vmid Vc Vmid + - R9 2.1E3 C2 400pF L1 R12 1 G6 18 VCM D5 DX Vg + - G1 L2 15.9159E V-- 2nd Gain Stage Mid Supply Ref Common Mode Gain Stage V++ E2 22 ISY 0.44mA Vg D6 DX 23 20 G7 + V5 1.12V V- V6 21 + DX - D7 1.12V G8 + + E3 V- V-- D10 DY + G9 + - R15 90 - + - D9 DX + + - D8 DX V+ D11 DY VOUT VOUT R16 90 + - V+ G10 Output Stage Supply Isolation Stage FIGURE 55. SPICE SCHEMATIC 21 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 *ISL28117 Macromodel - covers following *products *ISL28117 *ISL28217 *ISL28417 **Revision History: *Revision C, LaFontaine January 31, 2012 *Model for Noise, quiescent supply currents, *CMRR 210dB, fcm=10Hz, AVOL 155dB *f=0.02Hz, SR = 0.5V/us, output voltage *clamp and short ckt current limit. * *Copyright 2012 by Intersil Corporation Refer *to data sheet "LICENSE STATEMENT", Use *of this model indicates your acceptance with *the terms and provisions in the License *Statement. *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance *characteristics under a wide range of *external circuit configurations using *compatible simulation platforms - such as *iSim PE. ** *Device performance features supported by *this model *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances *Open loop gain and phase *Closed loop bandwidth and frequency *response *Loading effects on closed loop frequency *response *Input noise terms including 1/f effects *Slew rate *Input and Output Headroom limits to I/O *voltage swing *Supply current at nominal specified supply *voltages ** *Device performance features NOT *supported by this model: *Harmonic distortion effects *Disable operation (if any) *Thermal effects and/or over temperature *parameter variation *Limited performance variation vs. supply *voltage is modeled *Part to part performance variation due to *normal process parameter spread *Any performance difference arising from *different packaging * source : * +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28117 Vin+ Vin- V+ V- VOUT * source ISL28107subckt * *Voltage Noise E_En IN+ VIN+ 25 0 1 R_R17 25 0 290 D_D12 24 25 DN V_V7 24 0 0.1 * *Input Stage I_IOS IN+ VIN- DC 0.08E-9 C_C6 IN+ VIN- 1.2E-12 R_R1 VCM VIN- 5e11 R_R2 IN+ VCM 5e11 Q_Q1 2 VIN- 1 SuperB Q_Q2 3 8 1 SuperB Q_Q3 V-- 1 7 Mirror Q_Q4 4 6 2 Cascode Q_Q5 5 6 3 Cascode R_R3 4 V++ 4.45e3 R_R4 5 V++ 4.45e3 C_C4 VIN- 0 2e-12 C_C5 8 0 2e-12 D_D1 6 7 DX I_IEE 1 V-- DC 200e-6 I_IEE1 V++ 6 DC 96e-6 V_VOS 9 IN+ 8e-6 E_EOS 8 9 VC VMID 1 * *1st Gain Stage G_G1 V++ 11 4 5 8.129384e-2 G_G2 V-- 11 4 5 8.129384e-2 R_R5 11 V++ 1 R_R6 V-- 11 1 D_D2 10 V++ DX D_D3 V-- 12 DX V_V1 10 11 1.86 V_V2 11 12 1.86 * *2nd Gain Stage G_G3 V++ VG 11 VMID 2.83e-3 G_G4 V-- VG 11 VMID 2.83e-3 R_R7 VG V++ 1.99e10 R_R8 V-- VG 1.99e10 C_C2 VG V++ 4e-10 C_C3 V-- VG 4e-10 D_D4 13 V++ DX D_D5 V-- 14 DX V_V3 13 VG 1.86 V_V4 VG 14 1.86 * *Mid supply Ref R_R9 VMID V++ 2.1E3 R_R10 V-- VMID 2.1E3 I_ISY V+ V- DC 0.44E-3 E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 3.162277 G_G6 V-- VC VCM VMID 3.162277 R_R11 VC 17 1 R_R12 18 VC 1 L_L1 17 V++ 15.9159E-3 L_L2 18 V-- 15.9159E-3 * *Output Stage with Correction Current Sources G_G7 VOUT V++ V++ VG 1.11e-2 G_G8 V-- VOUT VG V-- 1.11e-2 G_G9 22 V-- VOUT VG 1.11e-2 G_G10 23 V-- VG VOUT 1.11e-2 D_D6 VG 20 DX D_D7 21 VG DX D_D8 V++ 22 DX D_D9 V++ 23 DX D_D10 V-- 22 DY D_D11 V-- 23 DY V_V5 20 VOUT 1.12 V_V6 VOUT 21 1.12 R_R15 VOUT V++ 9E1 R_R16 V-- VOUT 9E1 * .model SuperB npn + is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50 + re=0.065 rc=35 cje=1.5E-12 cjc=2E-12 + kf=0 af=0 .model Cascode npn + is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0 .model Mirror pnp + is=4E-15 bf=150 va=50 ik=138E-3 rb=185 + re=0.101 rc=180 cje=1.34E-12 +cjc=0.44E-12 kf=0 af=0 .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28117 FIGURE 56. SPICE NET LIST 22 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Characterization vs Simulation Results 100 VS = 18.2V AV = 1 INPUT NOISE VOLTAGE (nV/Hz) INPUT NOISE VOLTAGE (nV/Hz) 100 10 1 1 10 100 1k FREQUENCY (Hz) 10k 10 1.0 1.0 100k AV = 1000 60 100k Rg = 100, Rf = 100k AV = 1000 Rg = 1k, Rf = 100k VS = 20V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 30 20 40 AV = 10 20 AV = 10 Rg = 10k, Rf = 100k AV = 1 0 Rg = OPEN, Rf = 0 -10 10 100 VS = 15V CL = 4pF RL = 10k VOUT = 50mVP-P AV = 100 Rg = 10k, Rf = 100k 10 0 Rg = 1k, Rf = 100k GAIN (dB) GAIN (dB) 10k FIGURE 58. SIMULATED INPUT NOISE VOLTAGE Rg = 100, Rf = 100k 50 10k 1k 100k 1M AV = 1 -10 10 10M Rg = OPEN, Rf = 0 100 FREQUENCY (Hz) FIGURE 59. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY 0 -3 GAIN (dB) RL = 4.99k -2 RL = 1k -4 -7 -8 10 10M RL = 10k 0 -1 -6 1.0M 1 RL = 10k 1 -5 1.0k 10k 100k FREQUENCY (Hz) FIGURE 60. SIMULATED CLOSED LOOP GAIN vs FREQUENCY 2 GAIN (dB) 1.0k 70 70 40 100 FREQUENCY (Hz) FIGURE 57. CHARACTERIZED INPUT NOISE VOLTAGE 60 10 VS = 20V RL = 499 RL = 1k -2 -4 VS = 15V CL = 4pF CL = 4pF RL = 499 -6 AV = +1 AV = +1 RL = 100 VOUT = 50mVP-P 100 RL = 4.99k 1k 10k 100k VOUT = 50mVP-P 1M 10M FREQUENCY (Hz) FIGURE 61. CHARACTERIZED CLOSED LOOP GAIN vs R L 23 -8 10 100 RL =100 1.0k 10k 100k FREQUENCY (Hz) 1.0M 10M FIGURE 62. SIMULATED CLOSED LOOP GAIN vs R L March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Characterization vs Simulation Results (Continued) 3 2.4 2.0 2 1.6 INPUT VS = 15V, RL =10k 0.8 0.4 0 -0.4 -0.8 CL = 4pF AV = +1 VOUT = 4VP-P -1.2 -1.6 -2.0 -2.4 0 10 20 30 40 50 60 TIME (s) 70 80 90 -1 -3 100 CL = 4pF AV = +1 VOUT = 4VP-P 0 20 40 60 80 100 TIME (s) FIGURE 64. SIMULATED LARGE SIGNAL 10V STEP RESPONSE 200 OPEN LOOP GAIN (dB)/PHASE () OPEN LOOP GAIN (dB)/PHASE () 0 -2 FIGURE 63. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = 15V 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.1m 1m 10m 100m OUTPUT 1 LARGE SIGNAL (V) LARGE SIGNAL (V) 1.2 PHASE GAIN 1 10 100 1k 10k 100k 1M 10M 100M 160 PHASE 120 80 40 GAIN 0 -40 1.0m 10m 0.1 1 FREQUENCY (Hz) 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 65. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY FIGURE 66. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY 250 CMRR (dB) 200 150 100 50 1m 10m 0.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 67. SIMULATED CMRR vs FREQUENCY 24 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION February 23, 2012 FN6632.9 CHANGE "Ordering Information" on page 2: Removed "Coming soon" from ISL28417FVZ and changed Part Marking column from "28417 FVZ" to 28417 FVZ-C". Changed "-40 to +125" to "200 C-grade" Added new Part Number ISL28417 FVBZ Electrical Spec changes: VOS Description Section: page 6 & page 8: Changed "Input Offset Voltage; SOIC Package" to Input Offset Voltage; SOIC, TSSOP Package" TCVOS Description section: page 7 & page 9: Changed;Input Offset Voltage Temperature Coefficient; SOIC Package to Input Offset Voltage Temperature Coefficient; SOIC, TSSOP Package TCIOS Conditions section: page 7 & page 9: Changed "ISL28417 SOIC B and C Grade" to "ISL28417 SOIC, TSSOP B and C Grade". February 10, 2012 "Ordering Information" on page 2: Updated Pkg. Dwg. # for ISL28117FUBZ, ISL28117FUZ, ISL28217FUBZ & ISL28217FUZ from M8.118 to M8.118B Updated Pkg. Dwg. # for ISL28117FRTBZ, ISL28117FRTZ, ISL28217FRTBZ & ISL28217FRTZ from L8.3x3A to L8.3x3K Updated Pkg. Dwg. # for ISL28417FRZ from L16.4x4 to L16.4x4E "Thermal Information" on page 6: Added JA and JC for 16 Ld QFN and 14 Ld TSSOP Figure 52, "% OVERSHOOT vs LOAD CAPACITANCE, VS = 15V" on page 18: X-Axis (Capacitance pF) values 1k and 10k were shifted 1 decade to the right. Shifted 1 decade to the left and added new label "100k" at the extreme right (where the "10k" value was located). Added dual and quad to the "SPICE NET LIST" on page 22. "Package Outline Drawing (M8.118B)" on page 30: Changed from M8.118 to M8.118B Top View: Package width & height changed from 3.00.05 to 3.00.1 Package height from lead to lead changed from 4.90.15 to 4.90.2 Side View 2: Lead thickness changed from 0.09-0.20 to 0.150.05mm Side View 1: Package height changed from 0.850.10 to 0.860.05 Changed lead width from 0.25-0.036 to 0.23-0.36 Detail X: Foot of lead length changed from 0.550.15 to 0.530.10 "Package Outline Drawing (L8.3x3K)" on page 31: Changed from L8.3x3A to L8.3x3K Bottom View: Changed lead height from 0.30.1 to 0.40.05 Changed lead width from 0.300.05 to 0.250.05 Land Pattern: Changed lead width from 0.30 to 0.25 25 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION October 11, 2011 FN6632.8 October 7, 2011 CHANGE Figure 27 added "Positive" to Short Circuit Current title Figure 28 added "Negative" to Short Circuit Current title Figure 36 y axis label units changed from (nV/Hz) to (nV/Hz) Figure 37 y axis label units changed from pA/hz to pA/Hz Figure 31, 33 changed from VOUT vs Temperature to VOH vs Temperature Figure 32, 34 changed from VOUT vs Temperature to VOL vs Temperature Table of Contents on page 5 updated to list all package outline drawings Changed POD M14.15 to MDP0027 Changed TCIos for ISL28417 SOIC grade B and C on pages 7 and 9 from 3.5pA/C to 4.0pA/C 1. Pg 2 Ordering Information: a.Added ordering information rows for ISL28417FBBZ (B grade) and ISL28417FBZ (C grade). b. Add Table of Contents 2. Pg 5 Abs Max and Thermal Information Tables: a. Added HBM, MM, and CDM ESD levels for the `417 b. Added JA and JC values for the 14 Ld SOIC 3. Pg 6 15V electrical Specs a. Added ISL28417 B & C grade VOS and limits b. Added ISL28417 B & C grade TCVOS and limits c. Added ISL28417 B & C grade TCIOS and limits 4. Pg 7 a. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV typ to 130dB and 143dB respectively 5. Pg 8 5V electrical Specs a. Added ISL28417 B & C grade VOS and limits 6. Pg 9 a. Added ISL28417 B & C grade TCVOS and limits b. Added ISL28417 B & C grade TCIOS and limits c. Converted AVOL limits and units from 3kV/mV Min and 14kV/mV Typ to 130dB and 143dB respectively 7. Pg 17 Applications Information a. Added Unused Channels paragraph and Figure 54. July 12, 2011 FN6632.7 1. Releasing ISL28217FUZ MSOP Grade C package. Remove 'Coming Soon' from Order Information Table 2. Page 5, added: Machine Model (ISL28217 MSOP only). . . . . 300V 3. Under Electrical Spec 15V and 5V tables, changed Typical Rise Time and Fall Time from: Rise Time 100ns, Fall Time 120ns, to: Rise Time 130ns, Fall Time 130ns. 4. Under Electrical Spec 15V and 5V table for Vos and TCVos, added in row for ISL28217 MSOP Grade C package. Added Vos and TCVos limits for 25C and Full Temp. 5. For Typical performance curves for Vos Histograms, added note that histogram is based on ISL28217FBBZ for Grade B figures and ISL28217FBZ for Grade C figures. (Figures 3-6, added part number label to graph below Vs) 6. Under Electrical Spec 15V and 5V tables, changed TYP for Open Loop Gain from 18,000V/mV to 14,000V/mV December 2, 2010 FN6632.6 1. Updated "Ordering Information" table on page 2. Removed Coming Soon for ISL28117FRTBZ and ISL28117FUBZ parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively). 2. Corrected part marking in "Ordering Information" table on page 2 for ISL28117FRTZ from 8117 -C to -C 8117 3. Corrected part marking in "Ordering Information" table on page 2 for ISL28217FRTZ from 8217 -C to -C 8217 4. Updated Tape & Reel note in "Ordering Information" table on page 2 from "Add "-T7", "-T7A" or "-T13" suffix for tape and reel." to new standard "Add "-T*" suffix for tape and reel." The "*" covers all possible tape and reel options 5. Updated "Electrical Specifications" Table for "VOS" on page 6 and "TCVOS" on page 7 a. Added data row for Offset Voltage; MSOP Grade B Package; ISL28117 b. Added data row for Offset Voltage; TDFN Grade B Package; ISL28117 c. Added data row for Input Offset Voltage Temperature Coefficient; MSOP Grade B Package; ISL28117 d. Added data row for Input Offset Voltage Temperature Coefficient; TDFN Grade B Package; ISL28117 6. Removed "Temperature data established by characterization" from common conditions of spec table. Removed note "Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested." from Min Max columns of spec table. Replaced with new standard note in Min Max columns, "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." 26 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE August 31, 2010 FN6632.5 1. General changes: a. Added in Quad devices to the datasheet for SOIC, TSSOP and QFN packages. b. Added in TDFN packages for single and dual devices. c. Added in new VOS and TCVOS limits for TDFN packages d. Added Tja and Tjc Notes for TDFN Package which are "direct attach (Tja) " and "bottom (Tjc)" 2. Specific changes: a. Added in ISL28417 to title and front page info on page 1 b. Added in ISL28117FRTZ, ISL28117FRTBZ, ISL28217FRTZ, ISL28217FRTBZ, ISL28417FBZ, ISL28417FVZ, and ISL28417FRZ packages to Ordering information on page 2 and page 2. Added in -T7 and -T7A tape and reel extensions where applicable. c. Added in TDFN, 14 Ld SOIC, 14 Ld TSSOP and 16 Ld QFN to pin configurations on page 3 and page 3. d. Updated Pin Descriptions tables with new added in packages on page 4. e. Abs Max Table added in thermal packaging info for TDFN packages on page 6. f. Electrical Specifications Table - Added two new line items for VOS spec. TDFN package ISL28217 Grade B limits 70uV 25C and 140uV full temp. TDFN package ISL28x17 Grade C limits 150uV 25C and 250uV full temp on page 6 and page 8. g. Electrical Specifications Table - Added two new line items for TCVOS spec. TDFN package ISL28217 Grade B limits 0.7uV/C full temp. TDFN package ISL28x17 Grade C limits 1uV/C on page 7 and page 9. h. Added in PODs for L8.3x3A, M14.15, M14.173, and L16.4x4 March 18, 2010 FN6632.4 1. Updated "Ordering Information" on page 2 by adding two rows for MSOP packages ISL28117FUBZ and ISL28117FUZ, which are scheduled to release Q2 2010. Added Pinout accordingly. 2. Added POD for MSOP M8.118 to the end of datasheet 3. In "Ordering Information" on page 2, Separated each part number with it's own specific -T7 and -T13 suffix and removed "Add "-T7" or "-T13" suffix for Tape and Reel." from Note 1. 4. Updated 15 and 5V Electrical Specification table with the following edits: A) Separated VOS specs for SOIC and MSOP Grade C packages. Added new VOS specs for MSOP Grade C package. B) Separated TCVOS specs for SOIC and MSOP Grade C packages. Added new TCVOS specs for MSOP Grade C package. 5. Added "Thermal Information" on page 6 for ISL28117 MSOP package. March 3, 2010 Added "Related Literature" on page 1. Added Evaluation Boards to "Ordering Information" on page 2. Added Theta JC values to "Thermal Information" on page 6. Added applicable Theta JC Note 7. Updated Theta JA for ISL28217 8 Ld SOIC from 115C/W to 105C/W. January 21, 2010 Part marking in "Ordering Information" on page 2 changed as follows: ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ" ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C" ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ" ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C" December 24, 2009 On page 10: Changed label in Figure 3 from "VS = +5V" to "VS = 5V" On page 10: Changed label in Figure 4 from "VS = +15V" to "VS = 15V" November 25, 2009 Changed Typical VOS spec from "13" to "8" (B Grade), "19" to "4" (C Grade), IB from "0.18" to "0.08, IOS from "0.3" to "0.08". Edited Spice Schematic - L1 from "95.4957" to "15.9159E", R1 from "6k" to 1, R9 from "1" to "2.1E3", R10 from "1" to "2.1E3, R12 from "6k" to "1", L2 from "95.4957" to "15.9159E". Edited Spice Net List - Changed Revision from "A" to "B", Date change from "October 29th 2009" to "November 20th 2009", added after AOL "SR = 0.5V/sec, Input Stage changed in I_IOS from "0.3E-9" to 0.08E-9", V_VOS "13e-6" to "8e-6", Mid supply Ref R_R9 and R_R10 changed "1" to "2.1E3", Common Mode Gain Stage with Zero change in G_G5 and G_G6 "5.27046e-15" to "3.162277", R_R11 and R_R12 "6.3" to "1", L_L1 and L_L2 "95.4957" to "15.9159E-3" November 12, 2009 FN6632.3 27 Updated Typical Performance Curves Figure 5, 7, 9, 11, 13, 15, 17 and 19. Added Spice Model and license statement. Replaced typical application schematic . March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. (Continued) DATE REVISION CHANGE October 16, 2009 FN6632.2 On page 2 "Ordering Information", changed the following: a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B". Corrected part marking for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B" B) Updated package outline drawing to most recent revision (no changes were made to package dimensions; land pattern was added and dimensions were moved from table onto drawing) c) Added "Add "-T7" or "-T13" suffix for tape and reel." to the tape and reel Note 1. d) added Note 3 callout to all parts (Note 3 reads: "For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217. For more information on MSL please see techbrief TB363.") e) removed "Coming Soon" from ISL28117FBBZ, ISL28117FBZ & ISL28217FBBZ devices October 8, 2009 FN6632.1 1. Removed "very" from "...low noise.." 1st sentence, page 1. 2. Removed "Low" from 6th bullet under features, page 1. 3. Modified typical characteristics curves to show conservative performance. Specific channel designations removed. On temperature curves, changed formatting to indicate range from typical value. Changes include: a. Removed former Figures 1, 3, 5, 7, 9, 10, 13, 14, 17, 18, 21, 22, 25, 26, 29, 30, 33, 34, 37 & 38 (all Channel A curves) b. Replaced former Figures 19, 20, 23, 24, 27, 28, 31, 32, 35, 36, 39 & 40 with new Figures 9 thru 20 (all "conservative channels") c. Added Figures 30, 31, 32 4. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same graphic) 5. Added temp labels to Figures 28 & 29 September 3, 2009 FN6632.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28117, ISL28217, ISL28417 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 28 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Package Outline Drawing (M8.15E) M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 0.10 A DETAIL "A" 0.22 0.03 B 6.0 0.20 3.90 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45 4 4 0.43 0.076 1.27 0.25 M C A B SIDE VIEW "B" TOP VIEW 1.75 MAX 1.45 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 0.075 SIDE VIEW "A 0.63 0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 29 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Package Outline Drawing (M8.118B) M8.118B 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 1, 3/12 3.00.10mm 5 A D 8 4.90.20mm DETAIL "X" 3.00.10mm 5 1.10 MAX 0.150.05mm PIN# 1 ID SIDE VIEW 2 1 2 B 0.65mm BSC TOP VIEW 0.95 REF 0.860.05mm H GAUGE PLANE C 0.25 SEATING PLANE 0.23 - 0.36mm 0.08 M C A-B D 0.10 0.05mm 33 0.10 C 0.53 0.10mm SIDE VIEW 1 DETAIL "X" (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 30 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Package Outline Drawing (L8.3x3K) L8.3x3K 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 9/11 2X 1.95 3.00 6X 0.65 A B 1 PIN #1 INDEX AREA 3.00 6 6 PIN 1 INDEX AREA (4X) 1.50 0.10 0.15 8 TOP VIEW 8X 0.25 0.05 0.40 0.05 4 0.10 M C A B 2.30 0.10 BOTTOM VIEW SEE DETAIL "X" C 0.10 C 0.75 0.05 0 . 203 REF 5 C 0 . 02 NOM. 0 . 05 MAX. 0.08 C SIDE VIEW DETAIL "X" ( 2.30) ( 1.95) NOTES: ( 8X 0.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured (1.50) ( 2.90 ) between 0.15mm and 0.20mm from the terminal tip. PIN 1 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be (6x 0.65) ( 8 X 0.25) either a mold or mark feature. TYPICAL RECOMMENDED LAND PATTERN 7. 31 Compliant to JEDEC MO-229 WEEC-2 except for the foot length. March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Small Outline Package Family (SO) A D h X 45 (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL "X" 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4 4 DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300") (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150") 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 32 March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Package Outline Drawing (M14.173) M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0-8 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN 33 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. March 23, 2012 FN6632.9 ISL28117, ISL28217, ISL28417 Package Outline Drawing (L16.4x4) L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 6, 02/08 4X 1.95 4.00 12X 0.65 A B 13 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 16 1 4.00 12 2 . 10 0 . 15 9 4 0.15 (4X) 5 8 TOP VIEW 0.10 M C A B +0.15 16X 0 . 60 -0.10 4 0.28 +0.07 / -0.05 BOTTOM VIEW SEE DETAIL "X" 0.10 C 1.00 MAX C BASE PLANE ( 3 . 6 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 10 ) ( 12X 0 . 65 ) ( 16X 0 . 28 ) C 0 . 2 REF 5 ( 16 X 0 . 8 ) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 34 March 23, 2012 FN6632.9