LT4275CHMS#PBF - ANALOG DEVICES

LT4275

4275f

Typical applicaTion

FeaTures DescripTion

LTPoE++/PoE+/PoE

PD Controller

The LT

4275 is a pin-for-pin compatible family of IEEE

802.3 and LTPoE++ powered device (PD) controllers.

The LT4275A employs a proprietary LTPoE++ classification

scheme, delivering 38.7W, 52.7W, 70W or 90W of power

at the PD RJ45 connector. The LT4275A is fully compat-

ible with IEEE 802.3. The LT4275B is an IEEE 802.3at

compliant, Type 2 (PoE+) PD delivering up to 25.5W. The

LT4275C is an IEEE 802.3af compliant, Type 1 (PoE) PD

delivering up to 13W.

The LT4275 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

P-channel MOSFET. A low RDS(ON) MOSFET also maxi-

mizes power delivery and efficiency, reduces power and

heat dissipation, and eases thermal design. Startup inrush

current is adjustable with an external capacitor. The LT4275

also includes a power good output, on-board signature

resistor, undervoltage lockout, and thermal protection. The

LT4275A/LT4275B drives a single opto-coupler to indicate

the power level of the attached PSE. Pin-selectable sup-

port for non-standard low voltage operation is provided.

Auxiliary power override is supported with the AUX pin.

The LT4275A can be configured to support all possible

LTPoE++, 802.3at and 802.3af power levels with external

component changes.

L, LT, LTC , LT M, Linear Technology and the Linear logo are registered trademarks and

LTPoE++ and Hot Swap are trademarks of Linear Technology Corporation. All other trademarks

are the property of their respective owners.

LTPoE++ 90W Powered Device Interface

applicaTions

n IEEE 802.3af/at and LTPoE++™ Powered Device

(PD) Controller

n LTPoE++ Supports Power Levels Up to 90W

n LT4275A Supports All of the Following Standards:

n LTPoE++ 38.7W, 52.7W, 70W and 90W

n IEEE 802.3at 25.5W Compliant

n IEEE 802.3af Up to 13W Compliant

n LT4275B is IEEE 802.3at/af Compliant

n LT4275C is IEEE 802.3af Compliant

n 100V Absolute Maximum Input Voltage

n Wide Junction Temperature Range (–40°C to 125°C)

n Overtemperature Protection

n Integrated Signature Resistor

n External Hot Swap™ N-Channel MOSFET for Lowest

Power Dissipation and Highest System Efficiency

n Programmable Aux Power Support as Low as 9V

n Optional Support of Non-Standard Low Voltage PoE

n Available in 10-Lead MSOP and 3mm × 3mm DFN

Packages

n High Power Wireless Data Systems

n Outdoor Security Camera Equipment

n Commercial and Public Information Displays

n High Temperature Industrial Applications

LT4275 Family

MAX DELIVERED

POWER

LT4275 GRADE

A B C

LTPoE++ 90W l

LTPoE++ 70W l

LTPoE++ 52.7W l

LTPoE++ 38.7W l

25.5W l l

13W l l l

LT4275A

VPORT HSGATE

GND

4275 TA01a

IEEEUVLO

HSSRC

AUX

RCLASS

RCLASS++

RCLS++

PWRGD

T2P

RCLS

CPD

0.1µF

VPORT

DATA

PAIR

SPARE

PAIR

RUN

47nF

3.3k

FDMC86102

VIN

VOUT

–

ISOLATED

POWER

SUPPLY

OPTO PSE TYPE

(TO µP)

–

CPORT

VAUX (9V TO 60V)

LT4275

4275f

absoluTe MaxiMuM raTings

VPORT, HSSRC Voltages ......................... –0.3V to 100V

HSGATE Current.................................................. ±20mA

IEEEUVLO, RCLASS,

RCLASS++ Voltages ....... –0.3V to 8V (and ≤ VPORT)

AUX Current ........................................................ ±1.4mA

T2P, PWRGD Voltage ............................... –0.3V to 100V

T2P, PWRGD Current ...............................................5mA

(Notes 1, 3)

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING*

MAX PD

POWER PACKAGE DESCRIPTION TEMPERATURE RANGE

LT4275AIDD#PBF LT4275AIDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LT4275AHDD#PBF LT4275AHDD#TRPBF LGBS 90W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT4275AIMS#PBF LT4275AIMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 85°C

LT4275AHMS#PBF LT4275AHMS#TRPBF LTGBT 90W 10-Lead Plastic MSOP –40°C to 125°C

LT4275BIDD#PBF LT4275BIDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LT4275BHDD#PBF LT4275BHDD#TRPBF LGBV 25.5W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT4275BIMS#PBF LT4275BIMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 85°C

LT4275BHMS#PBF LT4275BHMS#TRPBF LTGBW 25.5W 10-Lead Plastic MSOP –40°C to 125°C

LT4275CIDD#PBF LT4275CIDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 85°C

LT4275CHDD#PBF LT4275CHDD#TRPBF LGBX 13W 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT4275CIMS#PBF LT4275CIMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 85°C

LT4275CHMS#PBF LT4275CHMS#TRPBF LTGBY 13W 10-Lead Plastic MSOP –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

TOP VIEW

GND

DD PACKAGE

10-LEAD (3mm × 3mm) PLASTIC DFN

1VPORT

HSGATE

HSSRC

PWRGD

T2P/NC*

IEEEUVLO

AUX

RCLASS

RCLASS++/NC*

GND

TJMAX = 150°C, θJC = 5°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB GND

IEEEUVLO

AUX

RCLASS

RCLASS++/NC*

GND

VPORT

HSGATE

HSSRC

PWRGD

T2P/NC*

TOP VIEW

MS PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, θJC = 45°C/W

* RCLASS++ is not connected in the LT4275B/C versions. T2P is not connected in the LT4275C version.

pin conFiguraTion

Operating Junction Temperature Range (Note 4)

LT4275AI/LT4275BI/LT4275CI ..............–40°C to 85°C

LT4275AH/LT4275BH/LT4275CH ....... –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 sec.) ..................300°C

LT4275

4275f

elecTrical characTerisTics

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: Signature resistance specifications do not include resistance

added by the external diode bridge which can add as much as 1.1k to the

port resistance.

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VPORT Operating Input Voltage At VPORT Pin l23 60 V

VSIG VPORT Signature Range At VPORT Pin l1.5 10 V

VCLASS VPORT Classification Range At VPORT Pin l12.5 21 V

VMARK VPORT Mark Range At VPORT Pin, Preceded by VCLASS l5.6 10 V

VPORT Aux Mode Range At VPORT Pin, AUX > VAUXT l8 60 V

Signature/Class Hysteresis Window l1.0 V

VRESET Reset Threshold l2.6 5.6 V

VHSON Hot Swap Turn-On Voltage IEEEUVLO = 0V

IEEEUVLO Open

27 37

29 V

VHSOFF Hot Swap Turn-Off Voltage IEEEUVLO = 0V

IEEEUVLO Open

21.5 31

22.5 V

Hot Swap On/Off Hysteresis Window l3 V

Supply Current

Supply Current VPORT = HSSRC = 57V l2 mA

Supply Current During Classification VPORT = 17.5V, RCLASS and RCLASS++ Open l0.4 0.7 1.1 mA

Supply Current During Mark Event VMARK l0.5 2.2 mA

Signature and Classification

Signature Resistance VSIG (Note 2) l23.7 24.4 25.2 kΩ

Signature Resistance During Mark Event VMARK (Note 2) l5.8 8.3 11 kΩ

VRCLS RCLASS/RCLASS++ Operating Voltage –10mA ≥ IRCLASS ≥ –36mA, VCLASS l1.32 1.40 1.43 V

Classification Stability Time VPORT Step to 17.5V, RCLASS = 34.8Ω l2 ms

Analog/Digital Interface

VAUXT AUX Threshold l6.1 6.3 6.5 V

IAUXH AUX Pin Hysteresis Current AUX = 6.1V l4 5.8 8 µA

T2P Output Low 1mA Load (LT4275A/LT4275B Only) l0.8 V

PWRGD Output Low 1mA Load l0.8 V

PWRGD Leakage Current PWRGD = 60V l5 µA

T2P Leakage Current T2P = 60V l5 µA

Hot Swap Control

IGPU HSGATE Pull-Up Current VHSGATE – VHSSRC = 5V, VPORT > 42V, Out of Pin l18 22 27 µA

VGOC HSGATE Open Circuit Voltage VHSGATE – VHSSRC, 0µA to 10µA Load with Respect

to HSSRC

l10 18 V

HSGATE Pull-Down Current VHSGATE – VHSSRC = 5V l200 µA

Timing

fT2P T2P Frequency After PWRGD Valid, if LTPoE++ PSE Is Mutually

Identified

l690 840 990 Hz

Note 3: All voltages with respect to GND unless otherwise noted. Positive

currents are into pins; negative currents are out of pins unless otherwise

noted.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

LT4275

4275f

Typical perForMance characTerisTics

Signature Resistance

vs Input Voltage VPORT Hot Swap Thresholds Reset Threshold

PWRGD, T2P Output Low

Voltage vs Current VPORT Classification Thresholds T2P Frequency

VPORT Current vs VPORT Voltage

25k Detection Range

VPORT Hot Swap Thresholds Supply Current During Power-On

VPORT VOLTAGE (V)

VPORT CURRENT (mA)

0.2

0.3

0.4

0.5

0.1

4275 G01

1062 4

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

30 100

4275 G02

12575–25 50250

IEEEUVLO = 0V

Hot Swap OFF

Hot Swap ON

VPORT VOLTAGE (V)

SUPPLY CURRENT (mA)

1.0

1.5

2.0

0.5

055

4275 G03

605040 45

T = –40°C

T = 25°C

T = 75°C

T = 125°C

VPORT VOLTAGE (V)

SIGNATURE RESISTANCE (kΩ)

25.25

25.75

26.25

24.75

24.25

23.75

4275 G04

973 5

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

24.5

26.0

27.5

29.0

23.0

21.5 100

4275 G05

12575–25 50250

IEEEUVLO = FLOAT

Hot Swap OFF

Hot Swap ON

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

3.6

4.1

5.1

4.6

5.6

3.1

2.6 100

4275 G06

12575–25 50250

CURRENT (mA)

VOLTAGE (V)

4275 G07

531 2

T = –40°C

T = 25°C

T = 75°C

T = 125°C

TEMPERATURE (°C)

–50

VPORT VOLTAGE (V)

11.0

11.5

12.0

12.5

10.5

10.0 100

4275 G08

12575–25 50250

DETECT OR MARK TO CLASS

CLASS TO MARK

TEMPERATURE (°C)

–50

T2P FREQUENCY (Hz)

840

740

890

940

990

790

690 100

4275 G09

12575–25 50250

LT4275

4275f

pin FuncTions

IEEEUVLO (Pin 1): Hot Swap Turn-on Threshold Level

Control. Connect to ground for IEEE compliant turn-on

and turn-off (UVLO) voltage thresholds. Leave open for

lower turn-on and turn-off voltage thresholds.

AUX (Pin 2): Auxiliary Sense. Assert AUX via a resistive

divider from the auxiliary power input to set the voltage

at which the auxiliary supply takes over. Asserting AUX

pulls down HSGATE, disconnects the signature resistor,

disables classification and floats the PWRGD pin. The

AUX pin sinks IAUXH when below its threshold voltage of

VAUXT to provide hysteresis. Tie to GND when not used.

RCLASS (Pin 3): Programmable PoE Classification Resis-

tor. See Table 1.

RCLASS++ (Pin 4, LT4275A Only): Programmable

LTPoE++ Classification Resistor. This pin is not connected

on the LT4275B/LT4275C. See Table 1.

GND (Pin 5): Ground Pin. Must be soldered to PCB GND.

T2P (Pin 6, LT4275A/LT4275B Only): PSE Type Indica-

tor, Open-Drain Output. T2P floats for a 13W PSE. T2P

pulls down for a 25.5W PSE. T2P pulls down at fT2P with

a 50% (typical) duty cycle to indicate the presence of an

LTPoE++ PSE. T2P is valid after PWRGD is active. This pin

is not connected on the LT4275C. See the Applications

Information section for behavior when using the AUX pin.

PWRGD (Pin 7): Power Good Indicator, Open-Drain Output.

Pulls down during VCLASS and inrush.

HSSRC (Pin 8): External Hot Swap MOSFET Source. Con-

nect to source of the external MOSFET.

HSGATE (Pin 9): External Hot Swap MOSFET Gate Control,

Output. Connect to gate of the external MOSFET.

VPORT (Pin 10): PD interface upper power rail and external

Hot Swap MOSFET drain connection.

Exposed Pad (Pin 11, DFN Package Only): GND. Must

be soldered to PCB GND.

block DiagraM

4275 BD

CONTROL

LOGIC

CLASSIFICATION

LOGIC

VOLTAGE AND

CURRENT REFERENCES

CHARGE

PUMP

OVERTEMP

GND

VPORT VPORT

VGOC

6.3V

1.4V 1.4V

–

–EN

–

VPORT

AUX

RCLASS RCLASS++

T2P

HSSRC

HSGATE

PWRGD

IEEEUVLO

LT4275

4275f

applicaTions inForMaTion

OVERVIEW

Power over Ethernet (PoE) continues to gain popularity as

products take advantage of DC power and high speed data

available from a single RJ45 connector. Powered device

(PD) equipment vendors are running into the 25.5W power

limit established by the IEEE 802.3 standard. The LT4275A

allows higher power while maintaining backwards com-

patibility with existing PSE systems. The LT4275 utilizes

a low RDS(ON) N-channel MOSFET to maximize efficiency

and delivered power. Heat is also reduced, easing thermal

design.

MODES OF OPERATION

The LT4275 has several modes of operation depending

on the input voltage sequence applied to the VPORT pin.

These modes include 25kΩ signature detection, classifica-

tion, mark, inrush and powered on.

DETECTION

During detection, the PSE looks for a 25kΩ signature

resistor which identifies the device as a PD. The PSE will

apply two voltages in the range of 2.8V to 10V and measure

the corresponding currents. Figure 1 shows the detection

voltages. The PSE calculates the signature resistance using

a ∆V/∆I measurement technique.

The LT4275 presents its precision, temperature-compen-

sated 24.4k resistor between the VPORT and GND pins,

allowing the PSE to recognize a PD is present and request-

ing power to be applied. The LT4275 signature resistor is

smaller than 25k to compensate for the additional series

resistance introduced by the IEEE required bridge.

CLASSIFICATION

The detection/classification process varies depending on

whether the PSE is Type 1, Type 2, or LTPoE++. A Type 2

PSE may use Type 1 classification signaling and later

renegotiate a higher power classification with the PD over

the data layer.

A Type 1 PSE, after a successful detection, may apply a

classification probe voltage of 15.5V to 20.5V and mea-

sure current.

A Type 2 PSE may declare the availability of high power

by performing 2-event (Physical Layer) classification

or by communicating over the (Data Link Layer) high

speed data line. A Type 2 PD must recognize both types

of communication. Since Layer 2 communications takes

place directly between the PSE and the PD application, the

LT4275A/LT4275B responsibility ends with supporting

2-event classification.

In 2-event classification, a Type 2 PSE probes for power

classification twice as shown in Figure 2. The LT4275A or

LT4275B recognizes this and pulls the T2P pin down to

signal the load that Type 2 power is available. If an LT4275A

senses an LTPoE++ PSE it alternates between pulling T2P

down and floating T2P at a rate of fT2P.

Figure 1. Type 1 Detect/Class Signaling Waveform

Figure 2. Type 2 Detect/Class Signaling Waveform

4275 F01

VPORT

VHSON

VHSOFF

VCLASSMIN

VSIGMAX

VSIGMIN

VRESET

DETECT

CLASS

POWER ON

4275 F01

VPORT

VHSON

VHSOFF

VCLASSMIN

VSIGMAX

VSIGMIN

VRESET

DETECT

1ST CLASS

1ST MARK 2ND MARK

2ND CLASS

POWER ON

LT4275

4275f

applicaTions inForMaTion

Table 1. Classification Codes, Power Levels and Resistor Selection

CLASS

PD POWER

AVAILABLE PD TYPE

NOMINAL CLASS

CURRENT

LT4275 GRADE CAPABILITY RESISTOR

A B C RCLS RCLS++

0 13W Type 1 <0.4mA    Open Open

1 3.84W Type 1 10.5mA    140Ω Open

2 6.49W Type 1 18.5mA    76.8Ω Open

3 13W Type 1 28mA    49.9Ω Open

4 25.5W Type 2 40mA   34.8Ω Open

4* 38.7W LTPoE++ 40mA Open 34.8Ω

4* 52.7W LTPoE++ 40mA 140Ω 46.4Ω

4* 70W LTPoE++ 40mA 76.8Ω 64.9Ω

4* 90W LTPoE++ 40mA 49.9Ω 118Ω

*An LTPoE++ PD will be classified as class 4 by an IEEE 802.3 compliant PSE.

LT P oE++ CLASSIFICATION

The LT4275A allows higher power allocation while main-

taining backwards compatibility with existing PSE systems

by extending the classification signaling of IEEE 802.3.

Linear Technology PSE controllers that are capable of

LTPoE++ are listed in the Related Parts section. IEEE PSEs

will classify an LTPoE++ PD as a Type 2 PD.

SIGNATURE CORRUPT DURING MARK

During the mark state, the LT4275 presents <11kΩ to the

port as required by the IEEE specification.

INRUSH AND POWERED ON

Once the PSE detects and optionally classifies the PD, the

PSE then powers on the PD. When the port voltage rises

above the VHSON threshold, it begins to source IGPU out of

the HSGATE pin. This current flows into an external capaci-

tor (CGATE in Figure 3) that causes a voltage to ramp up the

gate of the external MOSFET. The external MOSFET acts as

a source follower and ramps the voltage up on the output

bulk capacitor (CPORT in Figure 3) thereby determining the

inrush current (IINRUSH in Figure 3).

To meet IEEE requirements, design IINRUSH to be approxi-

mately 100mA. See equation below:

IINRUSH =IGPU •CPORT

CGATE

The LT4275 internal charge pump provides an N-channel

MOSFET solution, eliminating a larger and more costly

P-channel FET. The low RDS(ON) MOSFET also maximizes

LT4275A

HSGATE

GND

4275 F03

VPORT HSSRC

CGATE

3.3k

CPORT

VPORT

IINRUSH

Figure 3. Programming IINRUSH

power delivery and efficiency, reduces power and heat

dissipation, and eases thermal design.

The PWRGD pin is held low by its open drain output until

HSGATE charges up to approximately 7V above HSSRC.

The PWRGD pin is used to hold off the isolated power

supply until inrush is complete and the external MOSFET

is fully enhanced. The HSGATE pin will remain high and

the PWRGD pin pulled down until the port voltage falls

below VHSOFF or the AUX pin is above VAUXT.

AUXILIARY SUPPLY OVERRIDE

If the AUX pin is held above VAUXT, the LT4275 enters

auxiliary power supply override mode. In this mode

the signature resistor is disconnected, classification is

disabled, HSGATE is pulled down, and the PWRGD pin is

allowed to float. The T2P pin pulls down on the LT4275A/

LT4275B when no RCLS++ resistor is present. The T2P pin

alternates between pulling down and floating at fT2P on the

LT4275A when the RCLS++ resistor is present.

LT4275

4275f

applicaTions inForMaTion

The AUX pin allows for setting the auxiliary supply turn on

(VAUXON) and turn off (VAUXOFF) voltage thresholds. The

auxiliary supply hysteresis voltage (VAUXHYS) is set by

sinking current (IAUXH) only when the AUX pin voltage is

less than VAUXT. Use the following equations to set VAUXON

and VAUXOFF via R1 and R2 in Figure 4.

Figure 4. AUX Threshold and Hysteresis Calculation

Transient Voltage Suppressor

The LT4275 specifies an absolute maximum voltage of

100V and is designed to tolerate brief overvoltage events.

However, the pins that interface to the outside world can

routinely see excessive peak voltages. To protect the

LT4275, install a unidirectional transient voltage suppres-

sor (TVS) such as an SMAJ58A between the port voltage

and GND. This TVS must be mounted near the LT4275.

For extremely high cable discharge and surge protection

contact Linear Technology Applications.

Classification Resistor (RCLS and RCLS++)

The RCLS resistors set the classification load current cor-

responding to the PD power classification. Select the value

of RCLS from Table 1 and connect the resistor between the

RCLASS pin and GND, or float the RCLASS pin if class 0

is required. The resistor tolerance must be 1% or better to

avoid degrading the overall accuracy of the classification

circuit. For LTPoE++ use the LT4275A and select the value

of RCLS++ from Table 1 in addition to RCLS.

Power Good Interface

The LT4275 provides a power good signal (PWRGD) to

simplify the isolated power supply design. The power good

signal is used to delay isolated power supply startup until

the CPORT capacitor is fully charged.

Exposed Pad

The LT4275A/LT4275B/LT4275C DFN package has an

exposed pad that is internally electrically connected to

GND. The exposed pad may only be connected to GND

on the printed circuit board.

LAYOUT CONSIDERATIONS

Avoid excessive parasitic capacitance on the RCLASS

pin and place resistor RCLS close to the LT4275. For the

LT4275A, place RCLS++ nearby as well.

It is strictly required for maximum protection to place the

input capacitor (CPD) and transient voltage suppressor as

close to the LT4275 as possible.

LT4275A

GND

4275 F04

AUX

VAUX

–

R1=VAUXON −VAUXOFF

IAUXH =VAUXHYS

IAUXH

R2 =R1

VAUXOFF

VAUXT −1











R1≥VAUX(MAX) −VAUXT

1.4mA

THERMAL PROTECTION

The IEEE 802.3 specification requires a PD to withstand

any applied voltage from 0V to 57V indefinitely. During

classification, however, the power dissipation in the LT4275

may be as high as 1.5W. The LT4275 can easily tolerate

this power for the maximum IEEE timing but will overheat

if this condition persists abnormally.

The LT4275 includes a thermal protection feature which

protects itself from excessive heating. If the junction

temperature exceeds the overtemperature threshold, the

LT4275 pulls down the HSGATE and PWRGD pins and

disables classification.

EXTERNAL INTERFACE AND COMPONENT SELECTION

Input Diode Bridge

The input diode bridge introduces a voltage drop that affects

the voltage range for each mode of operation. The LT4275

is designed to tolerate these voltage drops. The voltages

shown in the Electrical Specifications are measured at the

LT4275 package pins.

Input Capacitor

A 0.1µF capacitor is needed from VPORT to GND to meet

an input impedance requirement in IEEE 802.3.

LT4275

4275f

Typical applicaTions

IEEE 802.3af (Type 1) 13W Powered Device

LT4275A/LT4275B/LT4275C

VPORT HSGATE

GND

4275 TA02

IEEEUVLO

HSSRC

RCLASS

RCLASS++

PWRGD

T2P

AUX

RCLS

CPD

0.1µF

RUN

47nF

3.3k

FDN8601

SMAJ58A

VIN

VOUT

–

ISOLATED

POWER

SUPPLY

–

ETHERNET

MAGNETICS

CPORT

VPORT

LT4275A/LT4275B

VPORT HSGATE

GND

4275 TA03

IEEEUVLO

HSSRC

RCLASS

RCLASS++

PWRGD

T2P

AUX

RCLS

CPD

0.1µF

RUN

47nF

3.3k

FDN8601

SMAJ58A

VIN

VOUT

–

ISOLATED

POWER

SUPPLY

OPTO PSE TYPE

(TO µP)

–

ETHERNET

MAGNETICS

CPORT

VPORT

IEEE 802.3at (Type 2) 25.5W Powered Device

LTPoE++ 38.7W to 90W Powered Device

LT4275A

VPORT HSGATE

GND

4275 TA04

IEEEUVLO

HSSRC

RCLASS

RCLASS++

RCLS++

PWRGD

T2P

AUX

RCLS

CPD

0.1µF

RUN

47nF

3.3k

FDMC86102

SMAJ58A

VIN

VOUT

–

ISOLATED

POWER

SUPPLY

OPTO PSE TYPE

(TO µP)

–

WÜRTH

749022016

CPORT

VPORT

LT4275

4275f

package DescripTion

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

LT4275

4275f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

MS Package

10-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1661 Rev E)

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MSOP (MS) 0307 REV E

0.53 ± 0.152

(.021 ± .006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ± 0.152

(.193 ± .006)

0.497 ± 0.076

(.0196 ± .003)

REF

8910 76

3.00 ± 0.102

(.118 ± .004)

(NOTE 3)

3.00 ± 0.102

(.118 ± .004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.23

(.206)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ± 0.127

(.035 ± .005)

RECOMMENDED SOLDER PAD LAYOUT

0.305 ± 0.038

(.0120 ± .0015)

TYP

0.50

(.0197)

BSC

0.1016 ± 0.0508

(.004 ± .002)

LT4275

4275f

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2012

LT 0712 • PRINTED IN USA

relaTeD parTs

Typical applicaTion

PART NUMBER DESCRIPTION COMMENTS

LTC4257-1 IEEE 802.3af PD Interface Controller Internal 100V, 400mA Switch, Dual Current Limit, Programmable Class

LTC4263 Single IEEE 802.3af PSE Controller Internal FET Switch

LTC4265 IEEE 802.3at PD Interface Controller Internal 100V, 1A Switch, 2-Event Classification Recognition

LTC4266 Quad IEEE 802.3at PoE PSE Controller With Programmable ICUT/ILIM, 2-Event Classification

LTC4266A Quad LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3af and IEEE 802.3at PDs.

With Programmable ICUT/ILIM, 2-Event Classification

LTC4266C Quad IEEE 802.3af PSE Controller With Programmable ICUT/ILIM, 1-Event Classification

LTC4267-3 IEEE 802.3af PD Interface with Integrated

Switching Regulator Internal 100V, 400mA Switch, Programmable Class, 300kHz Constant Frequency PWM

LTC4269-1 IEEE 802.3af PD Interface with Integrated

Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, Aux Support

LTC4269-2 IEEE 802.3af PD Interface with Integrated

Forward Switching Regulator 2-Event Classification, Programmable Class, Synchronous Forward Controller, 100kHz

to 500kHz, Aux Support

LTC4270/LTC4271 12-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs

LTC4274 Single IEEE 802.3at PoE PSE Controller With Programmable ICUT/ILIM, 2-Event Classification

LTC4274A Single LTPoE++ PSE Controller Provides Up to 90W. Backwards Compatible with IEEE 802.3 PDs. With Programmable

ICUT/ILIM, 2-Event Classification

LTC4274C Single IEEE 802.3af PSE Controller With Programmable ICUT/ILIM, 1-Event Classification

LTC4278 IEEE 802.3af PD Interface with Integrated

Flyback Switching Regulator 2-Event Classification, Programmable Class, Synchronous No-Opto Flyback Controller,

50kHz to 250kHz, 12V Aux Support

LTC4290/LTC4271 8-Port PoE/PoE+/LTPoE++ PSE Controller Transformer Isolation, Supports IEEE 802.3af, IEEE 802.3at and LTPoE++ PDs

25W PD Solution with 12VDC and 24VAC Auxiliary Input

LT4275A/LT4275B

VPORT HSGATE

4275 TA05

HSSRC

AUX

RCLASS

IEEEUVLO

GND PWRGD

T2P

34.8Ω

931k

SMAJ58A

158k

47nF

3.3k

FDN8601

MMSD4148

(2plcs)

B2100

(4plcs)

OPTO PSE TYPE

(TO µP)

TO ISOLATED

POWER SUPPLY RUN

TO ISOLATED

POWER SUPPLY

8.2Ω

0.1µF

470µF

VAUX

9V TO 57VDC

OR 24VAC

WÜRTH

7499511001

1–12

TO PHY

B2100

(8plcs)