HYS72D128320GU-6-B - Infineon Technologies

Never stop thinking.

HYS64D64300[G/H]U–[5/6]–B

HYS72D64300[G/H]U–[5/6]–B

HYS64D128320[G/H]U–[5/6]–B

HYS72D128320[G/H]U–[5/6]–B

184-Pin Unbuffered Dual-In-Line Memory Modules

UDIMM

DDR SDRAM

Data Sheet, Rev. 1.0, May. 2004

Memory Products

Edition 2004-05

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

81669 München, Germany

Attention please!

The information herein is given to describe certain components and shall not be considered as a guarantee of

characteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure

of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support

devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may

be endangered.

Never stop thinking.

HYS64D64300[G/H]U–[5/6]–B

HYS72D64300[G/H]U–[5/6]–B

HYS64D128320[G/H]U–[5/6]–B

HYS72D128320[G/H]U–[5/6]–B

184-Pin Unbuffered Dual-In-Line Memory Modules

UDIMM

DDR SDRAM

Data Sheet, Rev. 1.0, May. 2004

Memory Products

Template: mp_a4_v2.0_2003-06-06.fm

HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B

Revision History: Rev. 1.0 2004-05

Previous Version: Rev. 0.5

Page Subjects (major changes since last revision)

7 Added Non-Green Modules DDR400 & DDR333 and removed DDR266

8,12ff editorial changes

22,23 Updated IDD currents to final

24,27,30,33 Update SPD Codes

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all?

Your feedback will help us to continuously improve the quality of this document.

Please send your proposal (including a reference to this document) to:

techdoc.mp@infineon.com

Data Sheet 5 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table of Contents

Data Sheet 6 Rev. 1.0, 2004-05

184-Pin Unbuffered Dual-In-Line Memory Modules

UDIMM HYS64D64300[G/H]U–[5/6]–B

HYS72D64300[G/H]U–[5/6]–B

HYS64D128320[G/H]U–[5/6]–B

HYS72D128320[G/H]U–[5/6]–B

1Overview

1.1 Features

• 184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Workstation main

memory applications

• One rank 64M x 64, 64M ×72 and two ranks 128M ×64, 128M ×72 organization

• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply

• Built with 512 Mbit DDR SDRAM in P-TSOPII-66-1 package

• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)

• Auto Refresh (CBR) and Self Refresh

• All inputs and outputs SSTL_2 compatible

• Serial Presence Detect with E2PROM

• JEDEC standard MO-206 form factor: 133.35 mm ×31.75 mm ×4.00 mm max.

• Jedec standard reference layout

• Gold plated contacts

• DDR400 speed grade supported

• Lead-free

Table 1 Performance

1.2 Description

The HYS64D64300[G/H]U–[5/6]–B, HYS72D64300[G/H]U–[5/6]–B, HYS64D128320[G/H]U–[5/6]–B, and

HYS72D128320[G/H]U–[5/6]–B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules

(UDIMM) organized as 64M ×64, 128M ×64 for non-parity and 64M ×72,128M ×72 for ECC main memory

applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of

decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD)

based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with

configuration data and the second 128 bytes are available to the customer

Part Number Speed Code –5 –6Unit

Speed Grade Component DDR400B DDR333B —

Module PC3200–3033 PC2700–2533 —

max. Clock Frequency @CL3 fCK3 200 166 MHz

@CL2.5 fCK2.5 166 166 MHz

@CL2 fCK2 133 133 MHz

Data Sheet 7 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Overview

Note: All part numbers end with a place code designating the silicon-die revision. Reference information available

on request. Example: HYS72D64300HU-6-B, indicating rev. B dies are used for SDRAM components. The

Compliance Code is printed on the module labels describing the speed sort (for example “PC2700”), the

latencies and SPD code definition (for example “20330” means CAS latency of 2.0 clocks, RCD1) latency of

3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card

used for this module.

Table 2 Ordering Information

Type Compliance Code Description SDRAM Technology

PC3200 (CL=3.0)

HYS64D64300GU–5–B PC3200U–30330–A0 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300GU–5–B PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320GU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

PC2700 (CL=2.5)

HYS64D64300GU–6–B PC2700U–25330–A0 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300GU–6–B PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320GU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

PC3200 (CL=3.0)

HYS64D64300HU–5–B PC3200U–30330–A0 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300HU–5–B PC3200U–30330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320HU–5–B PC3200U–30330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

PC2700 (CL=2.5)

HYS64D64300HU–6–B PC2700U–25330–A0 one rank 512 MB DIMM 512 Mbit (×8)

HYS72D64300HU–6–B PC2700U–25330–A0 one rank 512 MB ECC-DIMM 512 Mbit (×8)

HYS64D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB DIMM 512 Mbit (×8)

HYS72D128320HU–6–B PC2700U–25330–B0 two ranks 1 GB ECC-DIMM 512 Mbit (×8)

1) RCD: Row-Column-Delay

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 8 Rev. 1.0, 2004-05

2 Pin Configuration

The pin configuration of the Unbuffered DDR SDRAM

DIMM is listed by function in Table 3 (184 pins). The

abbreviations used in columns Pin and Buffer Type are

explained in Table 4 and Table 5 respectively. The pin

numbering is depicted in Figure 1.

Table 3 Pin Configuration of UDIMM

Pin# Name Pin

Type

Buffer

Type

Function

Clock Signals

137 CK0 I SSTL Clock Signals 2:0

Note: For clock net

loading see block

diagram, CK0 is

NC on 1R

NC NC –

16 CK1 I SSTL

76 CK2 I SSTL

138 CK0 I SSTL Complement Clock

Signals 2:0

Note: For clock net

loading see block

diagram, CK0 is

NC on 1R

NC NC –

17 CK1 I SSTL

75 CK2 I SSTL

21 CKE0 I SSTL Clock Enable Rank 0

111 CKE1 I SSTL Clock Enable Rank 1

Note: 2-rank module

NC NC – Note: 1-rank module

Control Signals

157 S0 I SSTL Chip Select Rank 0

158 S1 I SSTL Chip Select Rank 1

Note: 2-rank module

NC NC – Note: 1-rank module

154 RAS I SSTL Row Address Strobe

65 CAS I SSTL Column Address

Strobe

63 WE I SSTL Write Enable

Address Signals

59 BA0 I SSTL Bank Address Bus

2:0

52 BA1 I SSTL

48 A0 I SSTL Address Bus 11:0

43 A1 I SSTL

41 A2 I SSTL

130 A3 I SSTL

37 A4 I SSTL

32 A5 I SSTL

125 A6 I SSTL

29 A7 I SSTL

122 A8 I SSTL Address Bus 11:0

27 A9 I SSTL

141 A10 I SSTL

AP I SSTL

118 A11 I SSTL

115 A12 I SSTL Address Signal 12

Note: Module based on

256 Mbit or larger

dies

NC NC – Note: 128 Mbit based

module

167 A13 I SSTL Address Signal 13

Note: 1 Gbit based

module

NC NC – Note: Module based on

512 Mbit or

smaller dies

Data Signals

2 DQ0 I/O SSTL Data Bus 63:0

4 DQ1 I/O SSTL

6 DQ2 I/O SSTL

8 DQ3 I/O SSTL

94 DQ4 I/O SSTL

95 DQ5 I/O SSTL

98 DQ6 I/O SSTL

99 DQ7 I/O SSTL

12 DQ8 I/O SSTL

13 DQ9 I/O SSTL

19 DQ10 I/O SSTL

20 DQ11 I/O SSTL

105 DQ12 I/O SSTL

106 DQ13 I/O SSTL

109 DQ14 I/O SSTL

110 DQ15 I/O SSTL

23 DQ16 I/O SSTL

24 DQ17 I/O SSTL

28 DQ18 I/O SSTL

31 DQ19 I/O SSTL

114 DQ20 I/O SSTL

117 DQ21 I/O SSTL

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

Data Sheet 9 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

121 DQ22 I/O SSTL Data Bus 63:0

123 DQ23 I/O SSTL

33 DQ24 I/O SSTL

35 DQ25 I/O SSTL

39 DQ26 I/O SSTL

40 DQ27 I/O SSTL

126 DQ28 I/O SSTL

127 DQ29 I/O SSTL

131 DQ30 I/O SSTL

133 DQ31 I/O SSTL

53 DQ32 I/O SSTL

55 DQ33 I/O SSTL

57 DQ34 I/O SSTL

60 DQ35 I/O SSTL

146 DQ36 I/O SSTL

147 DQ37 I/O SSTL

150 DQ38 I/O SSTL

151 DQ39 I/O SSTL

61 DQ40 I/O SSTL

64 DQ41 I/O SSTL

68 DQ42 I/O SSTL

69 DQ43 I/O SSTL

153 DQ44 I/O SSTL

155 DQ45 I/O SSTL

161 DQ46 I/O SSTL

162 DQ47 I/O SSTL

72 DQ48 I/O SSTL

73 DQ49 I/O SSTL

79 DQ50 I/O SSTL

80 DQ51 I/O SSTL

165 DQ52 I/O SSTL

166 DQ53 I/O SSTL

170 DQ54 I/O SSTL

171 DQ55 I/O SSTL

83 DQ56 I/O SSTL

84 DQ57 I/O SSTL

87 DQ58 I/O SSTL

88 DQ59 I/O SSTL

174 DQ60 I/O SSTL

175 DQ61 I/O SSTL

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

178 DQ62 I/O SSTL Data Bus 63:0

179 DQ63 I/O SSTL

44 CB0 I/O SSTL Check Bit 0

Note: ECC type module

NC NC – Note: Non-ECC module

45 CB1 I/O SSTL Check Bit 1

Note: ECC type module

NC NC – Note: Non-ECC module

49 CB2 I/O SSTL Check Bit 2

Note: ECC type module

NC NC – Note: Non-ECC module

51 CB3 I/O SSTL Check Bit 3

Note: ECC type module

NC NC – Note: Non-ECC module

134 CB4 I/O SSTL Check Bit 4

Note: ECC type module

NC NC – Note: Non-ECC module

135 CB5 I/O SSTL Check Bit 5

Note: ECC type module

NC NC – Note: Non-ECC module

142 CB6 I/O SSTL Check Bit 6

Note: ECC type module

NC NC – Note: Non-ECC module

144 CB7 I/O SSTL Check Bit 7

Note: ECC type module

NC NC – Note: Non-ECC module

5 DQS0 I/O SSTL Data Strobe Bus 7:0

Note: See block

diagram for

corresponding

DQ signals

14 DQS1 I/O SSTL

25 DQS2 I/O SSTL

36 DQS3 I/O SSTL

56 DQS4 I/O SSTL

67 DQS5 I/O SSTL

78 DQS6 I/O SSTL

86 DQS7 I/O SSTL

47 DQS8 I/O SSTL Data Strobe 8

Note: ECC type module

NC NC – Note: Non-ECC module

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 10 Rev. 1.0, 2004-05

97 DM0 I SSTL Data Mask Bus 7:0

107 DM1 I SSTL

119 DM2 I SSTL

129 DM3 I SSTL

149 DM4 I SSTL

159 DM5 I SSTL

169 DM6 I SSTL

177 DM7 I SSTL

140 DM8 I SSTL Data Mask 8

Note: ECC type module

NC NC – Note: Non-ECC module

EEPROM

92 SCL I CMOS Serial Bus Clock

91 SDA I/O OD Serial Bus Data

181 SA0 I CMOS Slave Address Select

Bus 2:0

182 SA1 I CMOS

183 SA2 I CMOS

Power Supplies

1VREF AI – I/O Reference Voltage

184 VDDSPD PWR – EEPROM Power

Supply

15,

22,

30,

54,

62,

77,

96,

104,

112,

128,

136,

143,

156,

164,

172,

180

VDDQ PWR – I/O Driver Power

Supply

38,

46,

70,

85,

108,

120,

148,

168

VDD PWR – Power Supply

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

11,

18,

26,

34,

42,

50,

58,

66,

74,

81,

89,

93,

100,

116,

124,

132,

139,

145,

152,

160,

176

VSS GND – Ground Plane

Other Pins

82 VDDID OODVDD Identification

Note: Pin in tristate,

indicating VDD

and VDDQ nets

connected on

PCB

10,

71,

90,

101,

102,

103,

113,

163,

173

NC NC – Not connected

Pins not connected on

Infineon UDIMMs

Table 3 Pin Configuration of UDIMM (cont’d)

Pin# Name Pin

Type

Buffer

Type

Function

Data Sheet 11 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 1 Pin Configuration 184-Pin, UDIMM

Table 4 Abbreviations for Pin Type

Abbreviation Description

I Standard input-only pin. Digital levels.

O Output. Digital levels.

I/O I/O is a bidirectional input/output signal.

AI Input. Analog levels.

PWR Power

GND Ground

NC Not Connected

Table 5 Abbreviations for Buffer Type

Abbreviation Description

SSTL Serial Stub Terminated Logic (SSTL2)

LV-CMOS Low Voltage CMOS

CMOS CMOS Levels

OD Open Drain. The corresponding pin has 2

operational states, active low and tristate,

and allows multiple devices to share as a

wire-OR.

MPPD0030

Pin 002

Pin 006

Pin 010

Pin 014

Pin 018

Pin 022

Pin 026

Pin 030

Pin 034

Pin 038

Pin 004

Pin 008

Pin 012

Pin 016

Pin 020

Pin 024

Pin 028

Pin 032

Pin 036

Pin 040

DQ00

DQ02

DQS1

VSS

VDDQ

DQ01

DQ03

DQ08

CK1

DQ11

DQ17

DQ18

DQS3

DQ27

Pin 044

Pin 048

Pin 052

Pin 056

Pin 060

Pin 064

Pin 068

Pin 072

Pin 076

Pin 080

Pin 084

Pin 088

Pin 092

Pin 096

Pin 100

Pin 104

Pin 108

Pin 112

Pin 116

Pin 120

Pin 124

Pin 128

Pin 132

Pin 136

Pin 140

Pin 144

Pin 148

Pin 152

Pin 156

Pin 160

Pin 164

Pin 168

Pin 172

Pin 176

Pin 180

Pin 184

CB00/NC

BA1

DQS4

DQ35

DQ41

DQ42

DQ48

CK2

DQ51

DQ57

DQ59

SCL

DM8/NC

CB7/NC

VDDSPD

Pin 042

Pin 046

Pin 050

Pin 054

Pin 058

Pin 062

Pin 066

Pin 070

Pin 074

Pin 078

Pin 082

Pin 086

Pin 090

Pin 094

Pin 098

Pin 102

Pin 106

Pin 110

Pin 114

Pin 118

Pin 122

Pin 126

Pin 130

Pin 134

Pin 138

Pin 142

Pin 146

Pin 150

Pin 154

Pin 158

Pin 162

Pin 166

Pin 170

Pin 174

Pin 178

Pin 182

VDDQ

DQS6

DQS7

DQ04

DQ06

DQ13

DQ15

DQ20

A11

DQ28

CB4/NC

CK0/NC

CB06/NC

DQ36

DQ38

RAS

S1 /NC

DQ47

DQ53

DQ54

DQ60

DQ62

SA1

Pin 001

Pin 005

Pin 009

Pin 013

Pin 017

Pin 021

Pin 025

Pin 029

Pin 033

Pin 037

Pin 003

Pin 007

Pin 011

Pin 015

Pin 019

Pin 023

Pin 027

Pin 031

Pin 035

Pin 039

VREF

DQS0

DQ09

CK1

CKE0

DQS2

DQ24

A04

DQ10

DQ16

DQ19

DQ25

DQ26

Pin 043

Pin 047

Pin 051

Pin 055

Pin 059

Pin 063

Pin 067

Pin 071

Pin 075

Pin 079

Pin 083

Pin 087

Pin 091

Pin 095

Pin 099

Pin 103

Pin 107

Pin 111

Pin 115

Pin 119

Pin 123

Pin 127

Pin 131

Pin 135

Pin 139

Pin 143

Pin 147

Pin 151

Pin 155

Pin 159

Pin 163

Pin 167

Pin 171

Pin 175

Pin 179

Pin 183

DQS8/NC

CB03/NC

DQ33

BA0

DQS5

CK2

DQ50

DQ56

DQ58

SDA

DQ05

DQ07

DM1

CKE1/NC

A12/NC

DM2

DQ23

DQ29

DQ30

CB5/NC

DQ37

DQ39

DQ45

DM5

A13/NC

DQ55

DQ61

DQ63

SA2

Pin 041

Pin 045

Pin 049

Pin 053

Pin 057

Pin 061

Pin 065

Pin 069

Pin 073

Pin 077

Pin 081

Pin 085

Pin 089

Pin 093

Pin 097

Pin 101

Pin 105

Pin 109

Pin 113

Pin 117

Pin 121

Pin 125

Pin 129

Pin 133

Pin 137

Pin 141

Pin 145

Pin 149

Pin 153

Pin 157

Pin 161

Pin 165

Pin 169

Pin 173

Pin 177

Pin 181

CB01/NC

CB02/NC

DQ32

DQ34

DQ40

CAS

DQ43

DQ49

VDDQ

DM0

DQ12

DQ14

DQ21

DQ22

DM3

DQ31

CK0/NC

A10/AP

DM4

DQ44

DQ46

DQ52

DM6

DM7

SA0

VDDQ

VDD

VSS

VDDID

FRONTSIDE

BACKSIDE

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 12 Rev. 1.0, 2004-05

Figure 2 Block Diagram UDIMM Raw Card A ×64, 1 Rank, ×8

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 5.1

Ω±

Table 6 Address Format

Density Organization Memory

Ranks

SDRAMs # of

SDRAMs

# of row/bank/

columns bits

Refresh Period Interval

512 MB 64M ×64 1 64M ×88 13/2/11 8K 64ms7.8µs

512 MB 64M ×72 1 64M ×88 13/2/11 8K 64ms7.8µs

1GB 128M×64 2 64M ×8 16 13/2/12 8K 64 ms 7.8 µs

1GB 128M×72 2 64M ×8 18 13/2/12 8K 64 ms 7.8 µs

MPBD1011

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D2 DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0 - BA1: SDRAMs D0 - D7

A0 - An: SDRAMs D0 - D7

RAS: SDRAMs D0 - D7

CAS: SDRAMs D0 - D7

WE: SDRAMs D0 - D7

CKE: SDRAMs D0 - D7

BA0 - BA1

A0 - An

RAS

CAS

CKE0

VDD: SPD EEPROM E0

VDD/VDDQ: SDRAMs D0 - D7

VREF: SDRAMs D0 - D7

VSS: SDRAMs D0 - D7

Strap: see Note 1

VDDSPD

VDD/VDDQ

VREF

VSS

VDDID

SCL

SAD

SA0

SA1

SA2

VSS

SCL

SAD

Table 7 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 2 SDRAMs —

CK1, CK1 3 SDRAMs —

CK2, CK2 3 SDRAMs —

Data Sheet 13 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 3 Block Diagram UDIMM Raw Card B (x64, 2 Ranks, x8)

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 3

Ω±

MPBD1031

BA0 - BA1: SDRAMs D0 - D15

A0 - An: SDRAMs D0 - D15

RAS: SDRAMs D0 - D15

CAS: SDRAMs D0 - D15

WE: SDRAMs D0 - D15

CKE: SDRAMs D0 - D7

CKE:SDRAMs D8 - D15

BA0 - BA1

A0 - An

RAS

CAS

CKE0

CKE1

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

D0 D8

D10

D11

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D15

D14

D13

DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

D12

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

VDD: SPD EEPROM E0

VDD/VDDQ: SDRAMs D0 - D15

VREF: SDRAMs D0 - D15

VSS: SDRAMs D0 - D15

Strap: see Note 1

VDDSPD

VDD/VDDQ

VREF

VSS

VDDID

SCL

SAD

SA0

SA1

SA2

VSS

SCL

SAD

Table 8 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 4 SDRAMs —

CK1, CK1 6 SDRAMs —

CK2, CK2 6 SDRAMs —

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 14 Rev. 1.0, 2004-05

Figure 4 Block Diagram UDIMM Raw Card A ×72, 1Rank, ×8, ECC

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 5.1

Ω±

MPBD1001

DM0

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM1

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

D2 DM5

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM4

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM3

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM6

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM8

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM7

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0 - BA1: SDRAMs D0 - D8

A0 - An: SDRAMs D0 - D8

RAS: SDRAMs D0 - D8

CAS: SDRAMs D0 - D8

WE: SDRAMs D0 - D8

CKE: SDRAMs D0 - D8

BA0 - BA1

A0 - An

RAS

CAS

CKE0

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM CS

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

VDD: SPD EEPROM E0

VDD/VDDQ: SDRAMs D0 - D8

VREF: SDRAMs D0 - D8

VSS: SDRAMs D0 - D8

Strap: see Note 1

VDDSPD

VDD/VDDQ

VREF

VSS

VDDID

SCL

SAD

SA0

SA1

SA2

VSS

SCL

SAD

Table 9 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 3 SDRAMs —

CK1, CK1 3 SDRAMs —

CK2, CK2 3 SDRAMs —

Data Sheet 15 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Figure 5 Block Diagram UDIMM Raw Card B ×72, 2Ranks, ×8, ECC

Note:

1. VDD = VDDQ, therefore VDDID strap open

2. DQ, DQS, DM resistors are 22

Ω±

3. BAn, An, RAS, CAS, WE resistors are 3

Ω±

MPBD1021

DM1/DQS10

DQS1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM2/DQS11

DQS2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM3/DQS12

DQS3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

D10

D11

D12

DM8/DQS17

DQS8

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

D17

SCL

SAD

SA0

SA1

SA2

VSS

SCL

SAD

VDD: SPD EEPROM E0

VDD/VDDQ: SDRAMs D0 - D17

VREF: SDRAMs D0 - D17

VSS: SDRAMs D0 - D17

DM: SDRAMs D0 - D17

VDDSPD

VDD/VDDQ

VREF

VSS

VDDID

Strap: see Note 1

DM0/DQS9

DQS0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DM6/DQS15

DQS6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM7/DQS16

DQS7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM4/DQS13

DQS4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

D15

D14

D13

DM5/DQS14

DQS5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

D16

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

BA0 - BA1: SDRAMs D0 - D17

A0 - An: SDRAMs D0 - D17

RAS: SDRAMs D0 - D17

CAS: SDRAMs D0 - D17

WE: SDRAMs D0 - D17

CKE: SDRAMs D0 - D8

CKE:SDRAMs D9 - D17

BA0 - BA1

A0 - An

RAS

CAS

CKE0

CKE1

Table 10 Clock Signal Loads

Clock Input Number of SDRAMs Note

CK0, CK0 6 SDRAMs —

CK1, CK1 6 SDRAMs —

CK2, CK2 6 SDRAMs —

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Pin Configuration

Data Sheet 16 Rev. 1.0, 2004-05

Figure 6 Clock Net Wiring

6 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

DRAM2

DRAM3

DRAM4

DRAM5

DRAM6

4 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

DRAM2

Cap.

DRAM5

DRAM6

3 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

Cap.

DRAM3

Cap.

DRAM5

Cap.

2 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

DRAM1

Cap.

DRAM5

Cap.

1 DRAM Loads

R = 120 Ω ± 5%

DIMM

Connector

Cap.

DRAM3

Cap.

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 17 Rev. 1.0, 2004-05

10042003-RYU3-RQON

3 Electrical Characteristics

3.1 Operating Conditions

Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This

is a stress rating only, and functional operation should be restricted to recommended operation

conditions. Exposure to absolute maximum rating conditions for extended periods of time may

affect device reliability and exceeding only one of the values may cause irreversible damage to

the integrated circuit.

Table 11 Absolute Maximum Ratings

Parameter Symbol Values Unit Note/ Test

Condition

min. typ. max.

Voltage on I/O pins relative to VSS VIN, VOUT –0.5 – VDDQ +

0.5

V–

Voltage on inputs relative to VSS VIN –1 – +3.6 V –

Voltage on VDD supply relative to VSS VDD –1 – +3.6 V –

Voltage on VDDQ supply relative to VSS VDDQ –1 – +3.6 V –

Operating temperature (ambient) TA0–+70°C–

Storage temperature (plastic) TSTG -55 – +150 °C–

Power dissipation (per SDRAM component) PD–1–W–

Short circuit output current IOUT –50–mA–

Table 12 Electrical Characteristics and DC Operating Conditions

Parameter Symbol Values Unit Note/Test Condition 1)

Min. Typ. Max.

Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤166 MHz

Device Supply Voltage VDD 2.5 2.6 2.7 V fCK >166MHz

Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤166 MHz 3)

Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz

2)3)

EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —

Supply Voltage, I/O Supply

Voltage

VSS,

VSSQ

00V—

Input Reference Voltage VREF 0.49 ×

VDDQ

0.5 ×

VDDQ

0.51 ×

VDDQ

V4)

I/O Termination Voltage

(System)

VTT VREF – 0.04 VREF + 0.04 V 5)

Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 8)

Input Low (Logic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 8)

Input Voltage Level,

CK and CK Inputs

VIN(DC) –0.3 VDDQ + 0.3 V 8)

Input Differential Voltage,

CK and CK Inputs

VID(DC) 0.36 VDDQ + 0.6 V 8)6)

VI-Matching Pull-up

Current to Pull-down

Current

VIRatio 0.71 1.4 — 7)

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 18 Rev. 1.0, 2004-05

10042003-RYU3-RQON

Input Leakage Current II–2 2 µA Any input 0 V ≤VIN ≤VDD;

All other pins not under test

=0V

8)9)

Output Leakage Current IOZ –5 5 µA DQs are disabled;

0V ≤ VOUT ≤ VDDQ 8)

Output High Current,

Normal Strength Driver

IOH — –16.2 mA VOUT = 1.95 V 8)

Output Low

Current, Normal Strength

Driver

IOL 16.2 — mA VOUT = 0.35 V 8)

1) 0 °C ≤ TA ≤ 70 °C

2) DDR400 conditions apply for all clock frequencies above 166 MHz

3) Under all conditions, VDDQ must be less than or equal to VDD.

4) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.

5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal

to VREF, and must track variations in the DC level of VREF.

6) VID is the magnitude of the difference between the input level on CK and the input level on CK.

7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the

maximum difference between pull-up and pull-down drivers due to process variation.

8) Inputs are not recognized as valid until VREF stabilizes.

9) Values are shown per DDR SDRAM component

Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test

Condition 1)

DDR400B DDR333

Min. Max. Min. Max.

DQ output access time from CK/CK tAC –0.5 +0.5 –0.7 +0.7 ns 2)3)4)5)

DQS output access time from CK/CK tDQSCK –0.6 +0.6 –0.6 +0.6 ns 2)3)4)5)

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5)

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 2)3)4)5)

Clock Half Period tHP min. (tCL, tCH)min. (tCL, tCH)ns 2)3)4)5)

Clock cycle time tCK 5 8 — — ns CL = 3.0

2)3)4)5)

6 12 7.5 12 ns CL = 2.5

2)3)4)5)

7.5 12 7.5 12 ns CL = 2.0

2)3)4)5)

DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)

DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)

Control and Addr. input pulse width

(each input)

tIPW 2.2 — 2.2 — ns 2)3)4)5)6)

Table 12 Electrical Characteristics and DC Operating Conditions (cont’d)

Parameter Symbol Values Unit Note/Test Condition 1)

Min. Typ. Max.

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 19 Rev. 1.0, 2004-05

10042003-RYU3-RQON

DQ and DM input pulse width (each

input)

tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)

Data-out high-impedance time from

CK/CK

tHZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)

Data-out low-impedance time from CK/

tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)

Write command to 1st DQS latching

transition

tDQSS 0.75 1.25 0.75 1.25 tCK 2)3)4)5)

DQS-DQ skew (DQS and associated

DQ signals)

tDQSQ — +0.40 — +0.45 ns TSOPII

2)3)4)5)

Data hold skew factor tQHS — +0.50 — +0.55 ns TSOPII

2)3)4)5)

DQ/DQS output hold time tQH tHP –tQHS tHP –tQHS ns 2)3)4)5)

DQS input low (high) pulse width (write

cycle)

tDQSL,H 0.35 — 0.35 — tCK 2)3)4)5)

DQS falling edge to CK setup time

(write cycle)

tDSS 0.2 — 0.2 — tCK 2)3)4)5)

DQS falling edge hold time from CK

(write cycle)

tDSH 0.2 — 0.2 — tCK 2)3)4)5)

Mode register set command cycle time tMRD 2—2—tCK 2)3)4)5)

Write preamble setup time tWPRES 0—0—ns

2)3)4)5)8)

Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)9)

Write preamble tWPRE 0.25 — 0.25 — tCK 2)3)4)5)

Address and control input setup time tIS 0.6 — 0.75 — ns fast slew rate

3)4)5)6)10)

0.7 — 0.8 — ns slow slew

rate

3)4)5)6)10)

Address and control input hold time tIH 0.6 — 0.75 — ns fast slew rate

3)4)5)6)10)

0.7 — 0.8 — ns slow slew

rate

3)4)5)6)10)

Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5)

Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)

Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)

Active to Active/Auto-refresh command

period

tRC 55 — 60 — ns 2)3)4)5)

Auto-refresh to Active/Auto-refresh

command period

tRFC 70 — 72 — ns 2)3)4)5)

Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)

Precharge command period tRP 15 — 18 — ns 2)3)4)5)

Active to Autoprecharge delay tRAP tRCD – tRASmin ns 2)3)4)5)

Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test

Condition 1)

DDR400B DDR333

Min. Max. Min. Max.

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 20 Rev. 1.0, 2004-05

10042003-RYU3-RQON

Active bank A to Active bank B

command

tRRD 10 — 12 — ns 2)3)4)5)

Write recovery time tWR 15 — 15 — ns 2)3)4)5)

Auto precharge write recovery +

precharge time

tDAL tCK 2)3)4)5)11)

Internal write to read command delay tWTR 2—1—tCK 2)3)4)5)

Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5)

Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5)

Average Periodic Refresh Interval tREFI —7.8—7.8 µs2)3)4)5)12)

1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2.5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V

(DDR400)

2) Input slew rate ≥ 1 V/ns for DDR400, DDR333

3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference

level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.

4) Inputs are not recognized as valid until VREF stabilizes.

5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT.

6) These parameters guarantee device timing, but they are not necessarily tested on each device.

7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred

to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).

8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.

A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were

previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,

DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but

system performance (bus turnaround) degrades accordingly.

10) Fast slew rate ≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/

ns, measured between VIH(ac) and VIL(ac).

11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock

cycle time.

12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.

Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700

Parameter Symbol –5 –6 Unit Note/ Test

Condition 1)

DDR400B DDR333

Min. Max. Min. Max.

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 21 Rev. 1.0, 2004-05

10042003-RYU3-RQON

3.2 Current Conditions and Specification

IDD Conditions

Parameter Symbol

Operating Current 0

one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;

address and control inputs changing once every two clock cycles.

IDD0

Operating Current 1

one bank; active/read/precharge; Burst Length = 4; see component data sheet.

IDD1

Precharge Power-Down Standby Current

all banks idle; power-down mode; CKE ≤ VIL,MAX

IDD2P

Precharge Floating Standby Current

CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;

address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.

IDD2F

Precharge Quiet Standby Current

CS ≥ VIHMIN, all banks idle; CKE ≥VIH,MIN; VIN = VREF for DQ, DQS and DM;

address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.

IDD2Q

Active Power-Down Standby Current

one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM.

IDD3P

Active Standby Current

one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC =tRAS,MAX;

DQ, DM and DQS inputs changing twice per clock cycle;

address and control inputs changing once per clock cycle.

IDD3N

Operating Current Read

one bank active; Burst Length = 2; reads; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT =0mA

IDD4R

Operating Current Write

one bank active; Burst Length = 2; writes; continuous burst;

address and control inputs changing once per clock cycle;

50% of data outputs changing on every clock edge;

CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B

IDD4W

Auto-Refresh Current

tRC = tRFCMIN, burst refresh

IDD5

Self-Refresh Current

CKE ≤ 0.2 V; external clock on

IDD6

Operating Current 7

four bank interleaving with Burst Length = 4; see component data sheet.

IDD7

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 22 Rev. 1.0, 2004-05

10042003-RYU3-RQON

Table 14 IDD Specification for HYS[64/72]D[64/128][300/320]HU–5–B

Product Type

HYS64D64300HU–5–B

HYS64D64300GU–5–B

HYS72D64300HU–5–B

HYS72D64300GU–5–B

HYS64D128320HU–5–B

HYS64D128320GU–5–B

HYS72D128320HU–5–B

HYS72D128320GU–5–B

Unit Note 1)2)

1) DRAM component currents only

2) Test condition for maximum values: VDD =2.7V, TA=10°C

Organization 512MB 512MB 1GB 1GB

×64 ×64 ×64 ×72

1 Rank 1 Rank 2 Ranks 2 Ranks

–5 –5 –5 –5

Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max.

IDD0 800 920 900 1040 1110 1300 1250 1460 mA 3)

3) The module IDDx values are calculated from the component IDDx data sheet values as:

m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank

modules

IDD1 880 1040 990 1170 1190 1420 1340 1590 mA 3)4)

4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on

load conditions

IDD2P 20 40 30 40 50 70 50 80 mA 5)

5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

IDD2F 240 290 270 320 480 580 540 650 mA 3)

IDD2Q 150 210 170 230 300 420 340 470 mA 5)

IDD3P 100 130 110 140 190 260 220 290 mA 5)

IDD3N 310 380 350 420 620 750 700 850 mA 5)

IDD4R 800 960 900 1080 1110 1340 1250 1500 mA 3)4)

IDD4W 840 1000 950 1130 1150 1380 1300 1550 mA 3)

IDD5 1920 2320 2160 2610 2230 2700 2510 3030 mA 3)

IDD6 23 46 26 51 46 91 52 103 mA 5)

IDD7 2480 2920 2790 3290 2790 3300 3140 3710 mA 3)4)

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Electrical Characteristics

Data Sheet 23 Rev. 1.0, 2004-05

10042003-RYU3-RQON

[

Table 15 IDD Specification for HYS[64/72]D[64/128][300/320]HU–6–B

Product Type

HYS64D64300HU–6–B

HYS64D64300GU–6–B

HYS72D64300HU––6–B

HYS72D64300GU–6–B

HYS64D128320HU–6–B

HYS64D128320GU–6–B

HYS72D128320HU–6–B

HYS72D128320GU–6–B

Unit Note 1)2)

1) DRAM component currents only

2) Test condition for maximum values: VDD =2.7V, TA=10°C

Organization 512MB 512MB 1 GB 1 GB

×64 ×72 ×64 ×72

1 Rank 1 Rank 2 Ranks 2 Ranks

–6 –6 –6 –6

Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max.

IDD0 720 840 810 950 1000 1170 1130 1310 mA 3)

3) The module IDDx values are calculated from the component IDDx data sheet values as:

m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank

modules

IDD1 760 920 860 1040 1040 1250 1170 1400 mA 3)4)

4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on

load conditions

IDD2P 20 30 30 40 50 60 50 70 mA 5)

5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]

IDD2F 200 240 230 270 400 480 450 540 mA 5)

IDD2Q 140 190 150 220 270 380 310 430 mA 5)

IDD3P 90 120 100 140 180 240 200 270 mA 5)

IDD3N 280 330 320 370 560 660 630 740 mA 5)

IDD4R 680 840 770 950 960 1170 1080 1310 mA 3)4)

IDD4W 720 880 810 990 1000 1210 1130 1360 mA 3)

IDD5 1720 2040 1940 2300 2000 2370 2250 2660 mA 3)

IDD6 23 46 26 51 46 91 52 103 mA 5)

IDD7 2200 2600 2480 2930 2480 2930 2790 3290 mA 3)4)

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 24 Rev. 1.0, 2004-05

4SPDContents

Table 16 SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B

Product Type

HYS64D64300GU–5–B

HYS72D64300GU–5–B

HYS64D128320GU–5–B

HYS72D128320GU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 01 01 02 02

6 Data Width (LSB) 40 48 40 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 50 50 50 50

10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 50

11 Error Correction Support 00 02 00 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 08 00 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 1C 1C 1C 1C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60 60

24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50 50

25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75

Data Sheet 25 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

26 tAC SDRAM @ CLmax -1 [ns] 50 50 50 50

27 tRPmin [ns] 3C 3C 3C 3C

28 tRRDmin [ns] 28 28 28 28

29 tRCDmin [ns] 3C 3C 3C 3C

30 tRASmin [ns] 28 28 28 28

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 60 60 60 60

33 tAH, tCH [ns] 60 60 60 60

34 tDS [ns] 40 40 40 40

35 tDH [ns] 40 40 40 40

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 37 37 37 37

42 tRFCmin [ns] 41 41 41 41

43 tCKmax [ns] 28 28 28 28

44 tDQSQmax [ns] 28 28 28 28

45 tQHSmax [ns] 50 50 50 50

46 not used 00 00 00 00

47 DIMM PCB Height 00 00 00 00

48 - 61 not used 00 00 00 00

62 SPD Revision 00 00 00 00

63 Checksum of Byte 0-62 3E 50 3F 51

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 - 71 JEDEC ID Code of Infineon (2 -8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 37 36 37

74 Part Number, Char 2 34 32 34 32

75 Part Number, Char 3 44 44 44 44

76 Part Number, Char 4 36 36 31 31

Table 16 SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)

Product Type

HYS64D64300GU–5–B

HYS72D64300GU–5–B

HYS64D128320GU–5–B

HYS72D128320GU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 26 Rev. 1.0, 2004-05

77 Part Number, Char 5 34 34 32 32

78 Part Number, Char 6 33 33 38 38

79 Part Number, Char 7 30 30 33 33

80 Part Number, Char 8 30 30 32 32

81 Part Number, Char 9 47 47 30 30

82 Part Number, Char 10 55 55 47 47

83 Part Number, Char 11 35 35 55 55

84 Part Number, Char 12 42 42 35 35

85 Part Number, Char 13 20 20 42 42

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 16 SPD Codes for HYS[64/72]D[64/128][300/320]GU–5–B (cont’d)

Product Type

HYS64D64300GU–5–B

HYS72D64300GU–5–B

HYS64D128320GU–5–B

HYS72D128320GU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

Data Sheet 27 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B

Product Type

HYS64D64300HU–5–B

HYS72D64300HU–5–B

HYS64D128320HU–5–B

HYS72D128320HU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 01 01 02 02

6 Data Width (LSB) 40 48 40 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 50 50 50 50

10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50 50 50

11 Error Correction Support 00 02 00 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 08 00 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 1C 1C 1C 1C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60 60

24 tAC SDRAM @ CLmax -0.5 [ns] 50 50 50 50

25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75

26 tAC SDRAM @ CLmax -1 [ns] 50 50 50 50

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 28 Rev. 1.0, 2004-05

27 tRPmin [ns] 3C 3C 3C 3C

28 tRRDmin [ns] 28 28 28 28

29 tRCDmin [ns] 3C 3C 3C 3C

30 tRASmin [ns] 28 28 28 28

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 60 60 60 60

33 tAH, tCH [ns] 60 60 60 60

34 tDS [ns] 40 40 40 40

35 tDH [ns] 40 40 40 40

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 37 37 37 37

42 tRFCmin [ns] 41 41 41 41

43 tCKmax [ns] 28 28 28 28

44 tDQSQmax [ns] 28 28 28 28

45 tQHSmax [ns] 50 50 50 50

46 not used 00 00 00 00

47 DIMM PCB Height 00 00 00 00

48 - 61 not used 00 00 00 00

62 SPD Revision 00 00 00 00

63 Checksum of Byte 0-62 3E 50 3F 51

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 37 36 37

74 Part Number, Char 2 34 32 34 32

75 Part Number, Char 3 44 44 44 44

76 Part Number, Char 4 36 36 31 31

77 Part Number, Char 5 34 34 32 32

Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)

Product Type

HYS64D64300HU–5–B

HYS72D64300HU–5–B

HYS64D128320HU–5–B

HYS72D128320HU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

Data Sheet 29 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

78 Part Number, Char 6 33 33 38 38

79 Part Number, Char 7 30 30 33 33

80 Part Number, Char 8 30 30 32 32

81 Part Number, Char 9 48 48 30 30

82 Part Number, Char 10 55 55 48 48

83 Part Number, Char 11 35 35 55 55

84 Part Number, Char 12 42 42 35 35

85 Part Number, Char 13 20 20 42 42

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 17 SPD Codes for HYS[64/72]D[64/128][300/320]HU–5–B (cont’d)

Product Type

HYS64D64300HU–5–B

HYS72D64300HU–5–B

HYS64D128320HU–5–B

HYS72D128320HU–5–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC3200U–30330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 30 Rev. 1.0, 2004-05

Table 18 SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B

Product Type

HYS64D64300GU–6–B

HYS72D64300GU–6–B

HYS64D128320GU–6–B

HYS72D128320GU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 01 01 02 02

6 Data Width (LSB) 40 48 40 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60

10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70

11 Error Correction Support 00 02 00 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 08 00 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 0C 0C 0C 0C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75

24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70

25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00

26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00

Data Sheet 31 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

27 tRPmin [ns] 48 48 48 48

28 tRRDmin [ns] 30 30 30 30

29 tRCDmin [ns] 48 48 48 48

30 tRASmin [ns] 2A 2A 2A 2A

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 75 75 75 75

33 tAH, tCH [ns] 75 75 75 75

34 tDS [ns] 45 45 45 45

35 tDH [ns] 45 45 45 45

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 3C 3C 3C 3C

42 tRFCmin [ns] 48 48 48 48

43 tCKmax [ns] 30 30 30 30

44 tDQSQmax [ns] 2D 2D 2D 2D

45 tQHSmax [ns] 55 55 55 55

46 not used 00 00 00 00

47 DIMM PCB Height 00 00 00 00

48 - 61 not used 00 00 00 00

62 SPD Revision 00 00 00 00

63 Checksum of Byte 0-62 42 54 43 55

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 37 36 37

74 Part Number, Char 2 34 32 34 32

75 Part Number, Char 3 44 44 44 44

76 Part Number, Char 4 36 36 31 31

77 Part Number, Char 5 34 34 32 32

Table 18 SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)

Product Type

HYS64D64300GU–6–B

HYS72D64300GU–6–B

HYS64D128320GU–6–B

HYS72D128320GU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 32 Rev. 1.0, 2004-05

78 Part Number, Char 6 33 33 38 38

79 Part Number, Char 7 30 30 33 33

80 Part Number, Char 8 30 30 32 32

81 Part Number, Char 9 47 47 30 30

82 Part Number, Char 10 55 55 47 47

83 Part Number, Char 11 36 36 55 55

84 Part Number, Char 12 42 42 36 36

85 Part Number, Char 13 20 20 42 42

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 18 SPD Codes for HYS[64/72]D[64/128][300/320]GU–6–B (cont’d)

Product Type

HYS64D64300GU–6–B

HYS72D64300GU–6–B

HYS64D128320GU–6–B

HYS72D128320GU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

Data Sheet 33 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Table 19 SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B

Product Type

HYS64D64300HU–6–B

HYS72D64300HU–6–B

HYS64D128320HU–6–B

HYS72D128320HU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

0 Programmed SPD Bytes in E2PROM 80 80 80 80

1 Total number of Bytes in E2PROM 08 08 08 08

2 Memory Type (DDR = 07h) 07 07 07 07

3 Number of Row Addresses 0D 0D 0D 0D

4 Number of Column Addresses 0B 0B 0B 0B

5 Number of DIMM Ranks 01 01 02 02

6 Data Width (LSB) 40 48 40 48

7 Data Width (MSB) 00 00 00 00

8 Interface Voltage Levels 04 04 04 04

9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60

10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70

11 Error Correction Support 00 02 00 02

12 Refresh Rate 82 82 82 82

13 Primary SDRAM Width 08 08 08 08

14 Error Checking SDRAM Width 00 08 00 08

15 tCCD [cycles] 01 01 01 01

16 Burst Length Supported 0E 0E 0E 0E

17 Number of Banks on SDRAM Device 04 04 04 04

18 CAS Latency 0C 0C 0C 0C

19 CS Latency 01 01 01 01

20 Write Latency 02 02 02 02

21 DIMM Attributes 20 20 20 20

22 Component Attributes C1 C1 C1 C1

23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75

24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70

25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00

26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

Data Sheet 34 Rev. 1.0, 2004-05

27 tRPmin [ns] 48 48 48 48

28 tRRDmin [ns] 30 30 30 30

29 tRCDmin [ns] 48 48 48 48

30 tRASmin [ns] 2A 2A 2A 2A

31 Module Density per Rank 80 80 80 80

32 tAS, tCS [ns] 75 75 75 75

33 tAH, tCH [ns] 75 75 75 75

34 tDS [ns] 45 45 45 45

35 tDH [ns] 45 45 45 45

36 - 40 not used 00 00 00 00

41 tRCmin [ns] 3C 3C 3C 3C

42 tRFCmin [ns] 48 48 48 48

43 tCKmax [ns] 30 30 30 30

44 tDQSQmax [ns] 2D 2D 2D 2D

45 tQHSmax [ns] 55 55 55 55

46 not used 00 00 00 00

47 DIMM PCB Height 00 00 00 00

48 - 61 not used 00 00 00 00

62 SPD Revision 00 00 00 00

63 Checksum of Byte 0-62 42 54 43 55

64 JEDEC ID Code of Infineon (1) C1 C1 C1 C1

65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00 00 00

72 Module Manufacturer Location xx xx xx xx

73 Part Number, Char 1 36 37 36 37

74 Part Number, Char 2 34 32 34 32

75 Part Number, Char 3 44 44 44 44

76 Part Number, Char 4 36 36 31 31

77 Part Number, Char 5 34 34 32 32

Table 19 SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B

Product Type

HYS64D64300HU–6–B

HYS72D64300HU–6–B

HYS64D128320HU–6–B

HYS72D128320HU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

Data Sheet 35 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

SPD Contents

78 Part Number, Char 6 33 33 38 38

79 Part Number, Char 7 30 30 33 33

80 Part Number, Char 8 30 30 32 32

81 Part Number, Char 9 48 48 30 30

82 Part Number, Char 10 55 55 48 48

83 Part Number, Char 11 36 36 55 55

84 Part Number, Char 12 42 42 36 36

85 Part Number, Char 13 20 20 42 42

86 Part Number, Char 14 20 20 20 20

87 Part Number, Char 15 20 20 20 20

88 Part Number, Char 16 20 20 20 20

89 Part Number, Char 17 20 20 20 20

90 Part Number, Char 18 20 20 20 20

91 Module Revision Code 0x 0x 0x 0x

92 Test Program Revision Code xx xx xx xx

93 Module Manufacturing Date Year xx xx xx xx

94 Module Manufacturing Date Week xx xx xx xx

95 - 98 Module Serial Number (1 - 4) xx xx xx xx

99 - 127 not used 00 00 00 00

Table 19 SPD Codes for HYS[64/72]D[64/128][300/320]HU–6–B

Product Type

HYS64D64300HU–6–B

HYS72D64300HU–6–B

HYS64D128320HU–6–B

HYS72D128320HU–6–B

Organization 512 MB 512 MB 1 GByte 1 GByte

×64 ×72 ×64 ×72

1 Rank (×8) 1 Rank (×8) 2 Ranks (×8) 2 Ranks (×8)

Label Code PC2700U–25330

JEDEC SPD Revision Rev 0.0 Rev 0.0 Rev 0.0 Rev 0.0

Byte# Description HEX HEX HEX HEX

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Package Outlines

Data Sheet 36 Rev. 1.0, 2004-05

5 Package Outlines

Figure 7 Raw Card A DDR UDIMM HYS64D64300HU-[5/6/7]-B (1 Rank Module)

1.27 1±0.05 0.1 BA C

Detail of contacts

3 MIN.

2.5

±0.2

3.8

±0.13

±0.1

1.8 A

0.1 CB

17.8

184

1.27±0.1

0.4

31.75

±0.13

2.7 MAX.

6.62

±0.1

2.36

64.77

95 x

CBA

ø0.1

6.35

120.651.27 =

2.175

49.53

±0.1

40.1 ABC

128.95

133.35 B

0.15 A C

Burr max. 0.4 allowed

L-DIM-184-32

Data Sheet 37 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Package Outlines

Figure 8 Raw Card A DDR UDIMM HYS72D64300HU-[5/6/7F]-B (1 Rank Module)

192

±0.13

±0.05

1.27 0.1 BA C

Detail of contacts

0.2

3 MIN.

3.8

2.5

±0.2

1.8

±0.1

0.1 B

17.8

184

±0.1

0.1 ACB

128.95

133.35

2.7 MAX.

0.15 BA C

6.35

±0.1

2.36

64.77

ø0.1 C

A B

1.27x95 120.65=

2.175

6.62

49.53

92 B

±0.13

31.75

1.27

±0.1

0.4

Burr max. 0.4 allowed

1) On ECC modules only

L-DIM-184-30

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Package Outlines

Data Sheet 38 Rev. 1.0, 2004-05

Figure 9 Raw Card B DDR UDIMM HYS64D128320HU-[5/6/7]-B (2 Ranks Module)

4CB

0.1 A

±0.1

2.36

±0.1 C

64.77

ø0.1 A B

133.35

128.95

1.27x=

2.175

6.62

120.65

6.35 1.27

0.15

4 MAX.

49.53

0.4

31.75

±0.13

±0.1

A C

0.1

Detail of contacts

0.2

1.27

3.8 ±0.13

3 MIN.

±0.2

2.5

1±0.05 0.1 ACB

1.8 ±0.1 BA C 184

17.8

Burr max. 0.4 allowed

L-DIM-184-33

Data Sheet 39 Rev. 1.0, 2004-05

HYS[64/72]D[64300/128320][G/H]U–[5/6]–B

Unbuffered DDR SDRAM Modules

Package Outlines

Figure 10 Raw Card B DDR UDIMM HYS72D128320HU-[5/6/7/-B (2 Rank Module)

11 9292

±0.1

1.27

4 MAX.

0.4

0.1 B C

133.35

128.95 A

0.15 B C

±0.1

±0.13

31.75

64.77

2.36 ±0.1 ø0.1

6.35

95 x 1.27 = 120.65

6.62

CB 2.175

49.53

±0.05

1.27

0.2

Detail of contacts

0.1 ABC

2.5

±0.2

17.8

18493

±0.13

3.8

3 MIN.

±0.1

1.8 BA

0.1 C

Burr max. 0.4 allowed

1) On ECC modules only

L-DIM-184-31

Published by Infineon Technologies AG