11/04/08 1
PD-60329
IR3820MPbF
HIGHLY INTEGRATED 12A
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
•Wide Input Voltage Range 2.5V to 21V
•Wide Output Voltage Range 0.6V to 12V
•Continuous 12A Load Capability
•600kHz High Frequency Operation
•Programmable Over-Curre nt Protec tion
•Programmable PGood Output
•Hiccup Current Limit
•Precision Reference Voltage (0.6V)
•Programmable So ft-St art
•Pre-Bias Start-up
•Thermal Protection
•Thermally Enhanced Package
•Small Size 5mmx6mm QFN
•Pb-Free (Ro HS C ompliant)
Fig. 1. Typical application diagram
Description
The IR3820 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard switching controller and MOSFETs
make the IR3820 a space-efficient solution,
providing accurate power delivery for low output
voltage applications.
The IR3820 operates from a single 4.5V to 14V
input supply and generates an output voltage
adjustable from 0.6V to 0.75*Vin at loads up to
12A.
A versatile regulator offering programmability of
startup time, power good threshold and current
limit, the IR3820’s fixed 600kHz switching
frequency allows the use of small external
components.
The IR3820 also features important protection
functions, such as Pre-Bias startup, hiccup
current limit and thermal shutdown to provide the
required system level securi ty in the event of fault
conditions.
Applications
•Distributed Point-of-Loads
•Server and Workstations
•Embedded Systems
•Storage Systems
•DDR Applications
•Graphics Cards
•Game Consoles
•Computing Peripheral Voltage Regulators
SupIRBuckTM
11/04/08 2
PD-60329
IR3820MPbF
PACKAGE INFORMATION
5mm x 6mm POWER QFN
12
VIN
11
SW
10
PGnd
15
AGnd
1234567
8
9
14
13
Vsns FB COMP AGnd AGnd SS OCSet
PGood
VCC
VC
HG
Fig. 2: Package outline (Top view)
W/C2θ
W/C35θ
o
PCBJ
o
JA =
=
-
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
•V
IN Supply Voltage -0.3V to 24V
• Vcc Supply Voltage -0.3V to 16V
• Vc Supply Voltage -0.3V to 30V
• SW -0.3V to 30V
• PGood -0.3V to 16V
• Fb,COMP,SS,Vsns -0.3V to 3.5V
•OCSet 10mA
• AGnd to PGnd -0.3V to +0.3V
• Storage Temperature Range -65°C To 150°C
• Operating Junction Temperature Range -40°C To 150°C
• ESD Classification JEDEC, JESD22-A114
• Moisture Sensitivity Level JEDEC Level 3 @ 260oC
Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum
Rating” conditions for extended periods may affect device reliability.
400015IR3820MTRPbFM
750
PARTS PER
REEL
15
PIN
COUNT
IR3820MTR1PbF
PACKAGE
DESCRIPTION
M
PACKAGE
DESIGNATOR
ORDERING INFORMATI ON
11/04/08 3
PD-60329
IR3820MPbF
Block Diagram
Fig. 3. Simplified block diagram of the IR3820.
11/04/08 4
PD-60329
IR3820MPbF
Pin Description
Pin Name Description
1 Vsns PGood sense pin. Use two external resistors to program the power
good threshold.
2 Fb Inverting input to the error amplifier. This pin is co nnected directly to the
output of the re gulator via resistor divider to set the output voltage and
provide feedback to the error amplifier.
3 Comp Output of error amplifier.
4 AGnd Signal ground for internal reference and control circuitry.
5 AGnd Signal ground for internal reference and control circuitry.
6 SS/SD Soft start / shutdown. This pin provides user programmable soft-start
function. Connect an external capa cit or from this pin to signa l ground
(AGnd) to set the start up time of the output voltage. The converter can
be shutdown by pulling this pin below 0.3V.
7 OCSet Current limit set point. A resistor from this pin to SW pin will set the
current limit thresho ld.
8 V
CC
This pin provides biasing voltage for the internal blocks of the IC. It also
powers the low side driver. A minimum of 0.1uF, high frequency
capacitor must be connected from this pin to power ground (PGnd).
9 PGood
Power Good status pin. Output is open colle ctor. Connect a pull up
resistor from this pin to Vcc.
10 PGnd Power Ground. This pin serves as a separated ground for the MOSFET
drivers and should be connected to the system’s power ground plane.
11 SW
Switch node. This pin is connected to the output inductor
12 V
IN
Inpu t voltage con nection pin
13 HG This pin is connected to the high side Mosfet gate. Connect a small
capacitor from this pin to switch node (SW ).
14 V
C
This pin powers the high side driver and must be connected to a voltage
higher than input voltage. A minimum of 0.1uF high frequency capacitor
must be connected from this pin to the power ground (PGnd).
15 AGnd Signal ground for internal reference and control circuitry.
Pins 4, 5 and 15 ne ed to be conne cted together on system board.
11/04/08 5
PD-60329
IR3820MPbF
Recommended Operating Con ditions
Parameter Symbol Test Condition Min TYP MAX Units
Power Los s
Power Loss P
loss
Vcc=V
in
=12V, Vc=24V, V
o
=1.8V,
I
o
=12A, L=0.6uH, Note3 3.7 W
MOSFET R
ds(on)
Top Switch R
ds(on)_Top
I
D
=13A, Tj(MOSFET)=25
o
C 6.9 8.7
Bottom Switch R
ds(on)_Bot
I
D
=13A, Tj(MOSFET)=25
o
C
6.9 8.7
mΩ
Reference Voltag e
Feedback Voltage V
FB
0.6 V
0
o
C<Tj<105
o
C -1.35 +1.35 % Accuracy
-40
o
C<Tj<105
o
C, Note2 -1.5 +1.5 %
Supply Current
V
CC
Supply Current (Static)
I
CC(Static)
SS=0V, No Switching 10 13
V
C
Supply Current
(Static) I
C(Static)
SS=0V, No Switching 4.5 7
V
CC
Supply Current
(Dynamic)
I
CC(Dynamic)
SS=3V, V
c
=24V, V
cc
=V
in
=12V.
V
o
=1.8V, Io=0A 21 30
V
C
Supply Current
(Dynamic) I
C(Dynamic)
SS=3V, V
c
=24V, V
cc
=V
in
=12V.
V
o
=1.8V, Io=0A 21 30
mA
Under Voltage Lockout
V
CC
-Start-Threshold V
CC
_UVLO(R) Supply ramping up 4.0 4.4
V
CC
-Stop-Threshold V
CC
_UVLO(F) Supply ramping down 3.7 4.1
V
CC
-Hystere s i s Supply ramping up and down 0.15 0.25 0.3
V
C
-Start-Threshold V
C
_UVLO(R) Supply ramping up 3.1 3.5
V
C
-Stop-Threshold V
C
_UVLO(F) Supply ramping down 2.85 3.25
V
C
-Hysteresis Supply ramping up and down 0.15 0.2 0.25
V
Electrical Specifications
Unless otherwise specified, these specification apply over Vin=Vcc=Vc=12V, 0oC<Tj(Ic)<105oC.
Typical values are specifie d at Ta= 2 5 oC.
Symbol Definition Min Max Units
V
in
Input Voltage 2.5 21
V
cc
Supply Voltage 4.5 14
V
c
Supply Voltage Vin + 5V 28
V
o
Output Voltage 0.6 12
V
I
o
Note1
Output Current 0 12 A
T
j
Junction Temperature -40 125
o
C
11/04/08 6
PD-60329
IR3820MPbF
Note1: Continuous output current det erm in ed b y input a nd ou tput voltag e s et ting a nd the the rm al environme nt.
Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note3: Guaranteed by Design but not tested in production.
Parameter SYM Test Condition Min TYP MAX Units
Oscillator
Frequency F
S
540 600 660 kHz
Ramp Amplitude V
ramp
Note3
1.25 V
Min Pulse Width D
min(ctrl)
Note3
80 ns
Max Duty Cycle D
max
Fb=0V 75 %
Error Amplifier
Input Bias Current I
FB1
SS=3V -0.1 -0.5
Input Bias Current I
FB2
SS=0V 20 35 50
Source/Sink Current I(source/Sink) 50 70 90
μA
Transconductance gm 1000 1300 1600
μmho
Soft Start/SD
Soft Start Current I
SS
SS=0V 15 20 28 μA
Shutdown Output
Threshold SD 0.25 V
Power Good
Vsns Low Trip Point Vsns(trip) Vsns R amping Down 0.35 0.38 0.41 V
Hysteresis PGood(Hys) 15 27.5 40 mV
PGood Output Low
Voltage PG(voltage) I
PGood
=4mA 0.25 0.5 V
Input Bias Current Isns 0 0.3 1 μA
Over Current Protection
OCSET Current I
OCSET
15 20 26
Hiccup Current I
Hiccup
Note3
3
μA
Hiccup Duty Cycle Hiccup(duty) I
Hiccup
/ I
SS
,
Note3
15 %
Thermal Shutdown
Thermal Shutdown
Threshold
Note3
140
Thermal Shutdown
Hysteresis
Note3
20
o
C
11/04/08 7
PD-60329
IR3820MPbF
TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC)
Icc(static)
7.0
8.0
9.0
10.0
11.0
12.0
13.0
-40-20020406080100120
Temp[oC]
[mA]
Ic(static)
2.0
3.0
4.0
5.0
6.0
7.0
-40 -20 0 20 40 60 80 100 120
Temp[oC]
[mA]
Icc(dynamic)
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
-40 -20 0 20 40 60 80 100 120
Temp[oC]
[mA]
Ic(dynamic)
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
-40-200 20406080100120
Temp[oC]
[mA]
Vfb
585.0
590.0
595.0
600.0
605.0
-40 -20 0 20 40 60 80 100 120
Temp[oC]
[mV]
ISS
15.0
17.0
19.0
21.0
23.0
25.0
27.0
-40 -20 0 20 40 60 80 100 120
Temp[oC]
[uA]
Transconductance
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
-40-200 20406080100120
Temp[oC]
[mmho]
IOCSET
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
25.0
26.0
-40 -20 0 20 40 60 80 100 120
Temp[oC]
[uA]
11/04/08 8
PD-60329
IR3820MPbF
Circuit Description
THEORY OF OPERATION
The IR3820 is a voltage mode PWM
synchronous regulator and operates with a fixed
600kHz switching frequency, allowing the use of
small external components.
The output voltage is set by feedback pin (Fb)
and the internal reference voltage (0.6V). These
are two inputs to error amplifier. The error signal
between these two inputs is amplified and it is
compared to a fixed frequency linear sawtooth
ramp.
A trailing edge modulation is used for generating
fixed frequency pulses (PWM) which drives the
internal N-channel MOSFETs.
The internal oscillator circuit uses on-chip
circuitry, eliminating the need for external
components.
The IR3820 operates with single input voltage
from 4.5V to 14V allow ing an extended opera ting
input voltage range.
The over-current protection is performed by
sensing current through the RDS(on) of low side
MOSFET. This method enhances the converter ’s
efficiency and reduces cost by eliminating a
current sense resistor. The current limit is
programmable by using an external resistor.
Under-Voltage Lockout
The under-voltage lockout circuit monitors the
two input supplies (Vcc and Vc) and assures that
the MOSFET driver outputs remain in the off
state whenever the supply voltage drops below
set thresholds. Lockout occurs if Vcc or Vc fall
below 4.3V and 3.3V respectively. Normal
operation resumes once Vcc and Vc rise above
the set values.
Thermal Shutdown
Temperature sensing is provided inside the
IR3820. The trip threshold is typically set to
140oC. When trip threshold is exceeded, thermal
shutdown turns off both MOSFETs. Thermal
shutdown is not latched and automatic restart is
initiated when the sensed temperature drops
within the operating range. There is a 20oC
hysteresis in the thermal shutdown threshold.
Pre-Bias Startup
The IR3820 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
The output starts in asynchronous fashion and
keeps the synchronous MO SFET off until the first
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
start up.
Depending on system configuration, a specific
amount of output capacitors may be required to
prevent discharging the output voltage.
Fig. 4: Pre-Bias start up
Vo
Time
V
Pre-Bias Voltage
Shutdown
The output can be shutdown by pulling the soft-
start pin below 0.3V. This can easily be done by
using an external small signal transistor. During
shutdown both MOSFET drivers will be turned
off. Normal operation will resume by cycling soft
start pin.
Power Good
The IR3820 provides an open collector power
good signal which reports the status of the
output. The output is sensed through the
dedicated Vsns pin. The power good threshold
can be externally programmed using two external
resistors. The power good comparator is
internally set to 0.38V (ty pical).
11/04/08 9
PD-60329
IR3820MPbF
Soft-Start
The IR3820 has programmable soft-start to
control the output voltage rise and limit the in rush
current during start-up.
To ensure correct start-up, the soft-start
sequence initiates when Vcc and Vc rise above
their threshold and generate the Power On
Ready (POR) signal. The soft-start function
operates by sourcing current to charge an
external capacitor to about 3V.
Initially, the soft-start function clamps the output
of error amplifier by injecting a current (40uA)
into the Fb pin and generates a voltage about
0.96V (40ux24K) across the negative input of
error amplifier (s ee figure 5).
The magnitude of the injec ted cur rent is inve rse ly
proportional to the voltage at the soft-start pin . As
the soft-start voltage ramps up, the injected
current decreases linearly and so does the
voltage at negative input of error amplifier.
When the soft-start capacitor is around 1V, the
voltage at the positive input of the error amplifier
is approximately 0.6V.
The output of error amplifier will start increasing
and generating the first PWM s ignal. As the soft-
start capacitor voltage continues to rise up, the
current flowing into the Fb pin will keep
decreasing.
The feedback voltage increases linearly as the
soft start voltage ramps up. When soft-start
voltage is around 2V, the output voltage reaches
the steady state and the injected current is zero.
Figure 6 shows the theoretical operating
waveforms during soft-start.
The output voltage start-up time is the time
period when soft-start capacitor voltage
increases from 1V to 2V.
The start-up time will be dependent on the size of
the external soft-start capacitor and can be
estimated by :
Fig. 5: Soft-Start circuit for IR3820
Fig. 6: Theoretical operation waveforms
during soft-start
20uA
40uA
POR
Erro r Amp
SS/SD
Fb
Comp 24K
0.6V
24K
3V
So ft-S ta rt
Voltage
Voltage at negative input
of Error Amp
Voltage at Fb pin
Current flowing
into F b p in
40uA
0uA
0V 0.6V
≅
0.96V
0.6V
0V
3V
≅
2V
≅
1V
Output of UVLO
POR
For a given start-up time, the soft-start capacitor
can be estimated as:
V1V2
C
T
μA20
ss
start −=∗
)1 --(msTA20C startSS )(*
μ
≅
11/04/08 10
PD-60329
IR3820MPbF
Over-Current Protection
The over-current protection is performed by
sensing current through the RDS(on) of the low
side MOSFET. This method enhances the
converter’s efficiency and reduces cost by
eliminating a current sense resistor. As shown in
figure 7, an external resistor (RSET) is connected
between OCSet pin and the inductor point which
sets the current limit set point.
The internal current source develops a voltage
across RSET. When the low side MOSFET is
turned on, the inductor current flows through the
Q2 and results a voltage which is given by:
Fig. 7: Connection of over-current sensing resistor
Fig. 8: 3uA current source for discharging
soft-start capacitor during hiccup
An over cu rrent is detected if the OCSet p in goes
below ground. This trips the OCP comparator
and cycles the soft start function in hiccup mode.
The hiccup is performed by charging and
discharging the soft-start capacitor in a certain
slope rate. As shown in figure 8 a 3uA current
source is used to discharge the soft-start
capacitor.
The OCP comparator resets after every soft start
cycle. The converter stays in this mode until the
overload or short circuit is removed. The
converter will automatically recover.
)) --(I(R)R(IV LDS(on)OCSetOCSetOCSet 2∗−∗=
0)I(R)R(IV LDS(on)OCSetOCSetOCSet =∗
−
∗=
)3 --(
R
IR
II
onDS
OCSetOCSet
criticalLSET
)(
)(
∗
==
Fig. 9: OCset pin during normal condition
Ch1: Inductor point, Ch3:OCSet
The value of R SET should be checked in an ac tual
circuit to ensure that the over-current protection
circu it activates as expected. The IR3820 cur rent
limit is designed primarily as disaster preventing,
and doesn't operate as a precision current
regulator.
The critical inductor current can be calculated by
setting:
IOCSet*ROCSet Blanking time
Deadtime
Clamp voltage
The OCP circu i t starts sampling current when the
low gate drive is about 3V. The OCSet pin is
internally clamped about 1.5V during on time of
high side gate to prevent false trigging, figure 9
shows the OC Set pin during one switching cycle.
As shown, there is about 150ns delay to mask
the dead time. Since this node contains switching
noises, this delay also functions as a filter.
11/04/08 11
PD-60329
IR3820MPbF
Application Information
Design Example:
The following example is a typical application for
the IR3820. The application circuit is shown in
page 17.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.6V. The divider is
ratioed to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
When an exte rnal resi stor di vider is connected to
the output as shown in figure 10.
Equation (4) can be rewritten as:
For the calculated values of R8 and R9see
feedback compensation section.
kHz600F
mV30ΔV
A12I
V8.1V
)maxV,2.13V,(12V
s
o
o
o
in
=
=
=
=
≤
)4 --(
R
R
1VV
9
8
refo ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+∗=
Fig. 10: Typical application of the IR3820 for
programming the output voltage
)5 --(
VV
V
RR
refO
ref
89 ⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
∗=
Soft-Start Programming
The soft-start timing can be programmed by
selecting the soft-start capacitance value. The
start-up time of the converter can be calculated
by using:
Where Tstart is the desired start-up time (ms)
For a start-up time of 11ms, the soft-start
capacitor will be 0.22uF.
Vc supply for single inp ut voltage
To drive the high-side switch, it is necessary to
supply a gate voltage a t least 4V greater than the
bus voltage. This is achieved by using a charge
pump configuration as shown in figure 11. This
method is simple and inexpensive. The opera tion
of the circuit is as follows: when the lower
MOSFET is turned on, the capacitor (C1) is
pulled down to ground and charges, up to VBUS
value, through the diode (D1). The bus voltage
will be added to this voltage when upper
MOSFET turns on in next cycle, and providing
supply voltage (Vc) through diode (D2). Vc is
approximately:
Capacitors in the range of 0.1uF are generally
adequate for most applications. The diodes must
be a fast recovery device to minimize the amount
of charge fed back from the charge pump
capacitor into VBUS. The diodes need to be able
to block the full power rail voltage, which is seen
when the high side MOSFET is switched on. For
low voltage application, schottky diodes can be
used to minimiz e forward drop across the diodes
at start up.
Fig. 11: Charge pump circuit to generate
Vc voltage
(
)
)6 --(VVV2V 2D1DbusC
+
−
∗
≅
)1 --(TA20C startSS *
μ
≅
Fb
IR3624 V
OUT
R
9
R
8
IR3820
11/04/08 12
PD-60329
IR3820MPbF
Input Capacitor Selection
The input filter capacitor should be selected
based on how much ripple the supply can
tolerate on the DC input line. The ripple current
generated during the on time of upper MOSFET
should be provided by the input capacitor. The
RMS value of this ripple is expressed by:
Where:
D is the D uty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
For Io=12A and D=0.15, the IRMS=4.28A.
Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
results in better efficiency,
Use 5x10uF, 16V ceramic capacitors from
Panasonic.
Inductor Selection
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes a large ripple
current, resulting in the smaller size, faster
response to a load transient but poor efficiency
and high output noise. Generally, the selec tion of
the inductor value can be reduced to the desired
maximum ripple current in the inducto r . The
optimum point is usually found between 20% and
50% ripple of the output current.
For the buck conver ter, the inductor value for the
desired operating ripple current can be
determined using the following:
Where:
)7 --(D1DII oRMS )( −∗∗=
in
o
V
V
D=
s
oin F
1
Dt
t
i
LVV ∗=∗=−
Δ
Δ
Δ
;
)( i
Δ
()
)8 --(
FiV
V
VVL
sin
o
oin *
Δ
∗
∗−=
cycle DutyD
time on Turnt
frequency SwitchingF
current ripple Inductori
Voltage OutputV
voltage input MaximumV
s
o
in
=
=
=
=
=
=
Δ
Δ
If , then the output inductor will be:
L = 0.6uH
Delta MPL-104 series provides a range of
inductors in different values and low profile
suitable for large currents.
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitor s ’ type and va lues.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent
Series Inductance (ESL) are other contributing
components. These components can be
described as:
Since the output capacito r has a majo r ro le in the
overall performance of the converter and
determine the result of transient response,
selection of the capacitor is critical. The IR3820
can perform well with all types of capacitors.
As a rule the capacitor must have low enough
ESR to meet output ripple and load transient
requirements, yet have high enough ESR to
satisfy stability requirements.
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore a ceramic capacitor is
selected due to the low ESR and small size. Six
of the Panasonic ECJ2FB0J226M (22uF, 6.3V,
X5R and EIA 0805 case size) are a good choice.
In the case of tantalum or low ESR electrolytic
capacitors, the ESR dominates the output
voltage ripple, equation (9) can be used to
calculate the required ESR for the specific
voltage ripple.
)%(40 o
Ii
≈
Δ
current ripple InductorI
ripple voltage OutputV
FC8
I
V
ESL
L
V
V
-(9)- ESRIV
VVVV
L
o
so
L
Co
in
ESLo
LESRo
CoESLoESRoo
=
=
=
⎟
⎠
⎞
⎜
⎝
⎛
=
=
+
+
=
Δ
Δ
Δ
Δ
Δ
ΔΔ
Δ
Δ
Δ
Δ
**
*
*
)(
)(
)(
)()()(
11/04/08 13
PD-60329
IR3820MPbF
Feedback Compensation
The IR3820 is a voltage mode controller; the
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45o).
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter expressed as foll ows:
Figure 13 shows gain and phase of the LC filter.
Since we alr eady have 180ophase shift from the
output filter alone, the system risks being
unstable.
The IR3820’s erro r amplifie r is a differential -input
transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.
The error amplifier can be compensated e ither in
type II or typeIII compensation. When it is used in
type II compensation the transconductance
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5k Hz to 50kH z
which is essential for an acceptable phase
margin.
(11)---
CLπ2
1
F
oo
LC =
Gain
F
LC
0dB
Phase
0
F
LC
-180
Frequency Frequency
-40dB/decade
Fig. 13: Gain and Phase of LC filter
The ESR zero of the output capacitor expressed
as follows:
The transfer function (Ve/Vo) is given by:
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero expressed by:
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First sele ct the desired zero -crossover fr equency
(Fo):
Use the following equation to calculate R3:
Where:
Vin = Maximum Input Voltage
Vosc = Oscillator Ramp Voltage
Fo= Crossover Frequency
FESR = Zero Frequency of the Output Capacitor
FLC = Resonant Frequency of the Output Filter
R8and R9= Feedback Resistor Dividers
gm= Error Amplifier Transconductance
(12
)
---
CESR2
1
F
o
ESR **
π
∗
=
Fig. 14: TypeII compensation network
and its asymptotic gain plot
(13)---
sC
CsR1
*
RR
R
*g)s(H
4
43
89
9
m
+
+
=
()
[]
(15)---
CR2
1
F
(14)--- R*
RR
R
gsH
43
z
3
89
9
m
**
*
π
=
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
(
)
soESRo F1/10~1/5F and FF *
≤
>
(16)---
g*R*F*V
)RR(*F*F*V
R
m9
2
LCin
98ESRoosc
3
+
=
Ve
V
OUT
V
REF
R
9
R
8
R
3
C
4
E/A
F
Z
H(s) dB
Frequency
Gain(dB)
Fb Comp
C
POLE
11/04/08 14
PD-60329
IR3820MPbF
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
Use equations (15) and (16) to calculate C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
The additional pole is given by:
The pole sets to one half of switching frequency
which results in the capacitor CPOLE:
For a general solution for unconditional stability
for any type of output capacitor s, in a wide range
of ESR values we should implement local
feedback with a compensation network (type III).
The typically used compensation network for
voltage-mode controller is shown in figure 15.
In such a configuration, the transfer function is
given by:
The error amplifier gain is independent of the
transconductance under the following condition:
By replacing Zin and Zfaccording to figure 15, the
transformer function can be expressed as:
(17)---
CL2
1
750F
F75F
oo
z
LCz
*
*.
%
π
=
=
As known, the transconductance amplifier has
high impedance (current source) output,
therefore, consideration should be taken when
loading the error amplifier output. It may exceed
its source/sink output current capability, so that
the amplifier will not be able to swing its output
voltage over the necessary range.
The compensation network has three poles and
two zeros and they are expressed as follows:
Cross over frequency is expressed as:
CC
CC
R2
1
F
POLE4
POLE4
3
P
+
=*
**
π
2
F
F For
FR*
1
C
1
FR
1
C
s
P
s3
4
s3
POLE
<<
≅
−
=*
**
π
π
Fig.15: Compensation network with local
feedback and its asymptotic gain plot
INm
fm
o
e
Zg1
Zg1
V
V
+
−
=
(
)
[]
)(*
*
*)(
*
)(
)(
710
34
34
3
108743
348 CsR1
CC
CC
sR1
RRsC1CsR1
CCsR
1
sH
+
⎥
⎦
⎤
⎢
⎣
⎡⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
+
+
++
+
=
871087
2z
43
1z
33
34
34
3
3P
710
2P
1P
RC2
1
RRC2
1
F
CR2
1
F
CR2
1
CC
CC
R2
1
F
CR2
1
F
0F
**)(**
**
**
*
*
**
ππ
π
π
π
π
≅
+
=
=
≅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
=
=
=
ooosc
in
73o CL2
1
V
V
CRF **
***
π
=
(18)--- 1Z*g and 1Z*g inmfm >>>>
V
OUT
V
REF
R
9
R
8
R
10
C
7
C
3
C
4
R
3
Ve
F
Z
1
F
Z
2
F
P
2
F
P
3
E/A
Z
f
Z
IN
Frequency
Gain(dB)
H(s) dB
Fb Comp
11/04/08 15
PD-60329
IR3820MPbF
Based on the frequency of the zero generated by
the output capacitor and its ESR versus
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of crossover
frequency.
Select crossover frequency:
Fo=80kHz
Since: FLC<Fo<Fs/2<FESR, type III method B is
selected to place the poles and zeros.
The followin g d esig n rules will give a crossover
frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.
The DC gain will be large enough to provide high
DC-r egulation accuracy (typically - 5dB to -12dB).
The phase marg in should be greater than 45ofor
overall stab ility.
Desired Phase Boost:
Ceramic
FLC<Fo<Fs/2<FESR
Type III(PID)
Method B
Tantalum,
ceramic
FLC<Fo<FESR<Fs/2
Type III(PID)
Method A
Electrolytic
, Tantalum
FLC<FESR<Fo<Fs/2
Typ II(PI)
Output
capacitor
FESR vs. Fo
Compensator
type
Ω=Ω==
Ω=Ω==
Ω=
Ω==
===
===
Ω=
=
=
==
=
Θ
Θ+
=
=
Θ+
Θ
=
K1.30R :Select ,K20.30R ;R*
VV
V
R
K4.60R:Select ,K7.60R ;R
F*C*2
1
R
K96.1R :Select
g
1
R check ,K
95.1R ;
F*C*2
1
R
:R and R ,R Calculate
pF39C :Select ,pF77.41C ;
R*F*2
1
C
nF8.1C :Select 1.78nF,C ;
R*F*2
1
C
:C and C Calculate
K 2.701R :Select
g
2
R check ,KΩ57.12=R ,
V*
C
V*C*L*F*2
R
180pFC :Select
F*0.5F and F*5.0F :Select
kHz7.453F
Sin1
Sin1
*FF
kHz1.14F
Sin1
Sin1
*FF
998
refo
ref
9
8810
2Z7
8
10
m
1010
2P7
10
9810
33
33P
3
44
3
Z1
4
34
3
m
33
in7
OSCooo
3
7
sP32ZZ1
2P
o2P
2Z
o2Z
-
-
≥
≥
-
-
π
π
π
π
π
o
max 70Θ=
Table1- The compensation type and location
of FESR versus Fo
The details of these compensation types are
discussed in applica tion note AN -1043 wh ich can
be downloaded from IR’s website at www.irf.com.
For this design we have:
Vin=12V
Vo=1.8V
Vosc=1.25V
Vref=0.6V
gm=1000umoh
Lo=0.6uH
Co=6x22uF, ESR=0.5mOhm
Fs=600kHz
The value of the capacitance used in the
compensator design must be the small signal
value. For instance, the small signal capacitance
of the 22uF capac itor used in this design is 12uF
at 1.8 VDC bias and 600 kH z frequency. It i s this
value that must be used for all computations
related to the compensation. The small signal
value may be obtained from the manufacturer’s
datasheets, design tools or SPICE models.
Alternatively, they may also be inferred from
measuring the power stage transfer function of
the converter and measuring the double pole
frequency FLC and using equation (11) to
compute the small signal Co.
These result to:
FLC=24.21kHz
FESR=4.4MHz
Fs/2=300kHz
(
)
soESRo F1/10~1/5F and FF *
≤
<
11/04/08 16
PD-60329
IR3820MPbF
Setting the Power Good Threshold
Power Good threshold can be programmed by
using two external resistors (see figure 16).
The following formula can be used to set the
threshold:
Where:
0.38V is reference of the in ternal comparato r
0.9*Vout is selectable threshold for power good,
for this desig n it is 1.62 V.
Select R1=10KOhm
Using (18): R2=3.06KOhm
Select R2=3.09K
Use a pull up resistor (4.99K) from PGood pin to
Vcc.
Programmin g the Current-Limit
The Current-Limit threshold can be set by
connecting a resistor (RSET) from drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
The RDS(on) has a positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to power ground (PGnd)
for noise rejection purposes.
-(3)-
R
IR
=I=I
DS(on)
OCSetOCSet
)L(criticalSET
∗
Layout Consideration
The layout is ver y important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas.
The inductor, output capacitor and the IR3820
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor dire c tl y to
the Vin pin of IR3820. To reduce the ESR replace
the single input capacitor with two parallel units.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to thei r
respective pins. It is important to place the
feedback components including feedback
resis tors and co mpensation components close to
Fb and Comp pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4 -layers PC B. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias.
)19 --(*R
V38.0*V9.0
V38.0
R1
out
2-
=
10.5KΩ=R=R
20.1A=2.1A1.5)(12A=I
FLV
V
)VV(i
current ripple Inductor :i
Current Output Max:I
:where
2
i
)5.1(I=I
V for usedis 5V if
MOSFET side-low for mΩ 9.3 Use :Note
Dependency eTemperatur:
:Where
10.35mΩ=.516.9mΩ6.9mΩ=R
7OCSet
SET
sin
o
oin
o
oSET
cc
DS(on)
+∗
∗∗
∗=Δ
Δ
Δ
+∗
∗=∗
-
υ
υ
11/04/08 17
PD-60329
IR3820MPbF
Typical Application for IR3820
12V to 1.8V @ 12A
Fig.16: Typical Application circuit for 12V to 1.8V at 12A using ceramic output capacitors
11/04/08 18
PD-60329
IR3820MPbF
PCB Metal and Compo nents Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead wi dth. The
minimum lead to lead spacing should be ≥0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard
extension. The outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal
to maximum part pad length and width. However, the minimum metal to metal spacing
should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper
and no less than 0.23mm for 3 oz. Copper.
11/04/08 19
PD-60329
IR3820MPbF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to
the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
11/04/08 20
PD-60329
IR3820MPbF
Stencil Design
• The Stencil apertures for the lead lands should be approximately 80% of the area of
the lead lads. Reducing the amount of solder deposited will minimize the
occurrences of lead shorts. If too much solder is deposited on the center pad the part
will float and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to
the solder resist opening minus an annular 0.2mm pull back to decrease the
incidence of shorting the center land to the lead lands when the part is pushed into
the so lder paste.
11/04/08 21
PD-60329
IR3820MPbF
IR WORLD HEADQUART ERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been design ed and qualifie d for the Consumer m arket.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 10/07
