LMH6882 General Purpose, Dual, Differential Amplifier With Gain Control General Description Features The LMH6882 is a general purpose high performance differential amplifier with gain control. One of its main features is that it is very easy to use compared to traditional differential amplifier. These amplifiers normally present configuration challenges to obtain desired gain, noise figure, linearity and impedance all at once. The LMH6882 can easily be configured to address these challenges. The LMH6882 is optimized to provide a best in class figure of merit (FOM) for dynamic range. This figure of merit is defined as the difference between the IIP3 and the NF which is one term in the spurious free dynamic range equation. The LMH6882 is targeted to work in a broad range of applications. The easy to use features combined with its high performance design make it suitable for communication applications as well as instrumentation applications. The LMH6882 is fabricated in TI's CBiCMOS8 proprietary complementary silicon germanium process and is available in a space saving, thermally enhanced 36-pin Lead Quad LLP package for higher performance. Small Signal Bandwidth: 2400MHz OIP3 @ 100 MHz: 42dBm HD2 @ 200 MHz: -65dBc Voltage Gain: 26dB Noise Figure: 9.7dB Dynamic Range Figure of Merit: 6.3dB Gain Range: 26dB to 6dB Parallel and Serial Gain Control Power Down Small footprint LLP Package Also Available as a Single: LMH6881 Applications General Purpose Differential Amplifier Differential ADC Driver Wideband Direct Conversion SAW Filter Buffer/Driver Twisted Pair Cable Driver Performance Curve Dynamic Range Performance 50 20 45 40 16 35 DRF = IIP3 - NF 12 30 25 20 8 15 10 4 OIP3 Noise Figure Dynamic Range Figure 5 0 6 0 8 10 12 14 16 18 20 22 24 26 30202292 SPITM is a trademark of Motorola, Inc. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 302022 SNOSC84 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Table of Contents General Description .............................................................................................................................. 1 Features .............................................................................................................................................. 1 Applications ......................................................................................................................................... 1 Performance Curve ............................................................................................................................... 1 Absolute Maximum Ratings .................................................................................................................... 4 Operating Ratings (Note 1) .................................................................................................................... 4 Connection Diagram ............................................................................................................................. 6 Ordering Information ............................................................................................................................. 6 Typical Performance Characteristics ....................................................................................................... 8 Application Information ........................................................................................................................ 14 INTRODUCTION ......................................................................................................................... 14 BASIC CONNECTIONS ............................................................................................................... 15 INPUT CHARACTERISTICS ......................................................................................................... 16 OUTPUT CHARACTERISTICS ..................................................................................................... 17 DIGITAL CONTROL .................................................................................................................... 19 PARALLEL INTERFACE .............................................................................................................. 19 SPI COMPATIBLE SERIAL INTERFACE ........................................................................................ 20 USB2ANY SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE ................................................... 23 SPISU2 SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE ....................................................... 23 THERMAL MANAGEMENT .......................................................................................................... 23 INTERFACING TO AN ADC ......................................................................................................... 24 ADC Noise Filter .................................................................................................................. 24 POWER SUPPLIES ..................................................................................................................... 24 COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS ................................................. 25 Application Board ........................................................................................................................ 26 Physical Dimensions ........................................................................................................................... 27 List of Figures FIGURE 1. LMH6882 Typical Application ...................................................................................................... FIGURE 2. LMH6882 Block Diagram ............................................................................................................ FIGURE 3. Basic Connections Schematic, Differential Input ................................................................................ FIGURE 4. Basic Connections Schematic, Single Ended ................................................................................... FIGURE 5. Differential LC Conversion Circuit ................................................................................................. FIGURE 6. Differential Output Voltage .......................................................................................................... FIGURE 7. Power Gain vs Filter ImpedanceMatching Resistor Loss = 6dB .............................................................. FIGURE 8. Single Ended Input, DC coupledCommon Mode Voltage Divider on Output ............................................... FIGURE 9. Differential Input, DC coupledCommon Mode Voltage Divider on Output .................................................. FIGURE 10. Single Ended Input, Differential Output Cable Driver ......................................................................... FIGURE 11. Parallel Mode Connection ........................................................................................................ FIGURE 12. Serial Interface Protocol (SPI compatible) ...................................................................................... FIGURE 13. Internal Operation of the SDO pin ................................................................................................ FIGURE 14. Read Timing ......................................................................................................................... FIGURE 15. Write TimingData Written to SDI Pin ............................................................................................ FIGURE 16. Sample Filter ......................................................................................................................... FIGURE 17. .......................................................................................................................................... 2 14 14 15 16 16 17 17 18 18 18 20 21 21 22 22 24 26 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Copyright (c) 1999-2012, Texas Instruments Incorporated 3 LMH6882 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 2) Human Body Model Charged Device Model Positive Supply Voltage (Pin 3) Differential Voltage between Any Two Grounds Analog Input Voltage Range Digital Input Voltage Range Output Short Circuit Duration (one pin to ground) Junction Temperature Storage Temperature Range Soldering Information 1 kV 250V -0.6V to 5.5V <200 mV -0.6V to 5.5V -0.6V to 5.5V Infinite +150C -65C to +150C Infrared or Convection (30 sec) Operating Ratings 260C (Note 1) Supply Voltage (Pin 3) Differential Voltage Between Any Two Grounds Analog Input Voltage Range, AC Coupled Temperature Range (Note 3) 4.75V to 5.25V <10 mV 0V to V+ -40C to +85C Thermal Properties Package Thermal Resistance (Note 9) (JA) 39C/W 36pin LLP 5V Electrical Characteristics (JC) 7.3C/W (Note 4) The following specifications apply for single supply with V+ = 5V, Maximum Gain (26dB), RL = 200, Boldface limits apply at temperature extremes. Symbol Parameter Min (Note 6) Conditions Typ (Note 5) Max (Note 6) Units Dynamic Performance 3dBBW -3dB Bandwidth NF Noise Figure VOUT= 2 VPPD 2.4 GHz Source = 100 9.7 dB OIP3 Output Third Order Intercept Point f = 100 MHz, VOUT = 4 dBm per tone 42 dBm Output Third Order Intercept Point f = 200 MHz, VOUT = 4 dBm per tone 40 OIP2 Output Second Order Intercept Point POUT= 4 dBm per Tone, f1 =112.5 MHz, f2=187.5 MHz 76 dBm IMD3 Third Order Intermodulation Products f = 100 MHz, VOUT = 4 dBm per tone -76 dBc Third Order Intermodulation Products f = 200 MHz, VOUT = 4 dBm per tone -72 P1dB 1dB Compression Point 17 dBm HD2 Second Order Harmonic Distortion f = 200 MHz, VOUT =4dBm -65 dBc HD3 Third Order Harmonic Distortion f = 200 MHz, VOUT =4dBm -74 dBc CMRR Common Mode Rejection Pin = -15 dBm, f = 100 MHz -40 dBc RIN Input Resistance Differential 100 RIN Input Resistance Single Ended, 50 termination on unused input 50 VICM Input Common Mode Voltage Self Biased 2.5 Analog I/O 4 V Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Symbol ROUT Parameter Conditions Min (Note 6) Typ (Note 5) Max (Note 6) Units Maximum Input Voltage Swing Volts peak to peak, differential 2 VPPD Maximum DIfferential Output Voltage Swing Differential, f < 10MHz 6 VPPD Output Resistance Differential, f = 100MHz 0.4 Maximum Voltage Gain Gain Code = 0 26 dB Minimum Gain Gain Code = 80d or 50h 6 dB Gain Parameters Gain Steps 80 Gain Step Size 0.25 dB Gain Step Error Any two adjacent steps over entire range 0.125 dB Gain Step Phase Shift Any two adjacent steps over entire range 3 Degrees 20 ns 15 ns Gain Step Switching Time Enable/ Disable Time Settled to 90% level Power Requirements ICC Supply Current P Power 200 1 270 mA W ICC Disabled Supply Current 25 mA All Digital Inputs Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS, 5V CMOS VIL Logic Input Low Voltage 0.4 V VIH Logic Input High Voltage 2.0-5.0 V IIH Logic Input High Input Current Digital Input Voltage = 2.0V -9 A IIL Logic Input Low Input Current Digital Input Voltage = 0.4V -47 A Parallel Mode Timing tGS Setup Time 3 ns tGH Hold Time 3 ns 50 MHz Serial Mode fCLK SPI Clock Frequency 50% duty cycle, ATE tested @ 20MHz 10 Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Note 3: The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the electrical tables under conditions different than those tested Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material. Note 6: Limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 7: Negative input current implies current flowing out of the device. Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. Note 9: Junction to ambient (JA) thermal resistance measured on JEDEC 4 layer board. Junction to case (JC) thermal resistance measured at exposed thermal pad; package is not mounted to any PCB. Note 10: LMH6881 devices have been used for some typical performance plots. Due to differences in packaging there are small differences in performance. Copyright (c) 1999-2012, Texas Instruments Incorporated 5 LMH6882 Connection Diagram 36-Pin LLP 30202203 Top View Ordering Information Package 36-Pin LLP Part Number Package Marking LMH6882SQE L6882 LMH6882SQ Transport Media NSC Drawing 250 Units Tape and Reel 2k Units Tape and Reel SQA36A Pin Descriptions Pin Number Symbol Pin Category Description 11,12, 16,17 INPD, INMD Analog Input Differential inputs 100 10,13, 15,17 INPS, INMS Analog INPUTt Single ended inputs 50 35,34 ,30,29 OUTP, OUTM Analog Output Differential outputs, low impedance 5,6,22, 23 GND Ground Ground pins. Connect to low impedance ground plane. All pin voltages are specified with respect to the voltage on these pins. The exposed thermal pad is internally bonded to the ground pins. 3,4,24, 25 VCC Power Power supply pins. Valid power supply range is 4.75V to 5.25V. Thermal/ Ground Thermal management/ Ground Digital Input 0= Parallel Mode, 1 = Serial Mode Analog I/O Power Exposed Center Pad Digital Inputs 27 6 SPI Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Pin Number Symbol Pin Category Description Parallel Mode Digital Pins, SPI= Logic Low 14, 7,8,9,21,29,19 D0, D1, D2, D3, D4,D5,D6 Digital Input Attenuator control, D0 = 0.25dB, D6 = 16dB 1 SD Digital Input Shutdown 0 = amp on, 1 = amp off Serial Mode Digital Pins, SPI= Logic High SPITM Compatible 14 SDO Digital Output- Open Emitter Serial Data Output (Requires external bias.) 7 SDI Digital Input Serial Data In 9 CS Digital Input Chip Select (active low) 8 CLK Digital Input Clock Copyright (c) 1999-2012, Texas Instruments Incorporated 7 LMH6882 Typical Performance Characteristics (TA = 25C, V+ = 5V, RL = 200, Maximum Gain, Unless Specified).(Note 10) Frequency Response over Gain Range OIP3 vs Gain Setting 35 50 30 45 25 40 OIP3 (dBc) GAIN (dB) 20 15 10 5 35 30 0 -5 25 -10 -15 f = 100 MHz POUT = 4dBm 20 1 10 100 1k FREQUENCY (MHz) 10k 6 8 10 12 14 16 18 20 22 24 26 VOLTAGE GAIN (dB) 30202287 OIP3 vs Output Power 30202253 Dynamic Range Figure vs Gain Setting 50 50 20 45 40 OIP3 (dBm) 45 16 35 DRF = IIP3 - NF 30 40 12 25 8 20 15 35 10 OIP3 Noise Figure Dynamic Range Figure 5 30 0 -4 -2 0 2 4 6 8 10 OUTPUT POWER, EACH TONE (dBm) 6 4 0 8 10 12 14 16 18 20 22 24 26 30202261 30202292 OIP3 vs Frequency OIP3 vs Supply Voltage 50 50.0 45 OIP3 (dBm) OIP3 (dBm) 45.0 40 35 30 40.0 35.0 25 26 dB 16 dB 6 dB 20 0 100 200 300 FREQUENCY (MHz) 30.0 400 30202256 8 26 dB 16 dB 6 dB 4.50 4.75 5.00 5.25 SUPPLY VOLTAGE (V) 5.50 30202255 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 OIP3 vs Temperature OIP2 vs Gain Setting 50 90 85 80 OIP2 (dBm) OIP3 (dBm) 45 40 35 f = 100 MHz POUT = 4dBm 70 65 60 30 - 40 C 25 C 85 C 25 6 75 f1 = 187.5 MHz f2 = 112.5 MHz PPOUT = 4dBm 55 50 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 6 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 30202273 30202293 Supply Current vs Temperature Maximum Gain vs Temperature 100 27.0 26.5 98 MAXIMUM GAIN (dB) SUPPLY CURRENT (mA) 99 97 96 95 94 93 92 26.0 25.5 25.0 24.5 91 90 f = 100 MHz POUT = 4.5dBm 24.0 -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (C) -45 -30 -15 0 15 30 45 60 75 90 TEMPERATURE (C) 30202258 30202259 HD2 vs Frequency, Differential Input -20 -20 26 dB 16 dB 6 dB -30 26 dB 16 dB 6 dB -30 -40 -40 -50 -50 HD3 (dBc) HD2 (dBc) HD3 vs Frequency, Differential Input -60 -70 -80 POUT=4dBm -60 -70 -80 -90 -90 POUT= 4 dBm -100 0 -100 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 30202226 Copyright (c) 1999-2012, Texas Instruments Incorporated 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 30202227 9 LMH6882 HD2 vs Frequency, Single Ended Input -20 HD3 vs Frequency, Single Ended Input -30 26 dB 16 dB 6 dB -30 -40 -50 -50 HD3 (dBc) HD2 (dBc) 26 dB 16 dB 6 dB -40 -60 -70 -60 -70 -80 -80 POUT=4dBm -90 -90 -100 POUT = 4dBm -100 0 50 100 150 200 250 300 350 400 FREQUENCY (MHz) 0 100 200 300 FREQUENCY (MHz) 400 30202224 30202225 HD2 & HD3 vs Gain Setting Differential Input -50 HD2 HD3 -60 HD2 & HD3vs Gain Setting Single Ended Input -30 f = 100 MHz POUT = 4dBm f = 100 MHz -40 -50 HD2, HD3 (dBc) -70 -80 -90 -100 -60 -70 -80 -90 -110 -100 -120 -110 6 8 10 12 14 16 18 20 22 24 26 6 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 30202263 30202271 HD2 vs Output Power -20 HD3 vs Output Power -10 26 dB 21 dB 10 dB -30 -30 -40 -50 HD3 (dBc) HD2 (dBc) -40 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 0 2 4 6 8 10 12 14 OUTPUT POWER (dBm) 16 30202220 10 26 dB 21 dB 10 dB -20 0 2 4 6 8 10 POUT (dBm) 12 14 16 30202221 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Gain Step Amplitude Error 1.0 50 MHz 200 MHz PHASE CHANGE (Degrees) ATTENUATOR STEP SIZE (dB) 0.5 Gain Step Phase Error 0.4 0.3 0.2 0.1 Step 0 = 26dB Step 80 = 6dB 0.0 Step 0 = 26 dB Step 80 = 6 dB 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 50 MHz 200 MHz -3.0 0.0010.0020.0030.0040.0050.0060.0070.0080.00 ATTENUATION STEP (SPI MODE) 0 10 20 30 40 50 60 70 80 ATTENUATION STEP (SPI MODE) 30202236 30202239 Cumulative Amplitude Error 0.5 3 50 MHz 200 MHz 0.4 0.3 PHASE ERROR (Degrees) AMPLITUDE ERROR (dB) Cumulative Phase Error 0.2 0.1 0.0 -0.1 -0.2 -0.3 Step 0 = 26 dB Step 80 = 6 dB -0.4 -0.5 Step 0 = 26 dB Step 80 = 6 dB 2 1 0 -1 -2 -3 -4 50 MHz 200 MHz -5 0 10 20 30 40 50 60 70 80 ATTENUATION STEP (SPI MODE) 0 10 20 30 40 50 60 70 ATTENUATION STEP (SPI MODE) 30202237 30202238 Noise Figure vs Gain Setting, Single Ended Input 30 20 25 18 NOISE FIGURE (dB) NOISE FIGURE (dB) Noise Figure vs Gain Setting 80 20 15 10 5 Single Ended Input f = 100MHz 16 14 12 10 8 0 6 6 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 30202250 Copyright (c) 1999-2012, Texas Instruments Incorporated 6 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 30202245 11 LMH6882 Noise Figure vs Frequency Shutdown Timing Using SD Pin 3 NOISE FIGURE (dB) 10 3 Enable Pin Output 12 2 2 VOUT (V) 8 6 4 1 1 0 0 2 0 0 200 400 600 800 FREQUENCY (MHz) -1 -1 1000 ENA PIN (V) 14 -2 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 30202251 30202248 Gain Step Timing, 16dB Step Parallel Mode 4 3 2 1 2 0 1 VOUT (V) 3 -1 2 1 1 0 0 -1 0 3 D2 Pin Output 2 A4 PIN (V) VOUT (V) 3 D3 Pin Ouptut -2 -1 -1 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) -2 0 10 20 30 40 50 60 70 80 90 100 TIME (ns) 30202242 30202243 Differential Input Impedance 0 125 -10 100 INPUT IMPEDANCE () CMRR (dB) CMRR vs Frequency -20 -30 -40 -50 R jX 75 50 25 0 -25 -60 -50 1 10 100 FREQUENCY (MHz) 1k 30202241 12 D2 PIN (V) 5 Gain Step Timing, 8dB Step Parallel Mode 0 400 800 1200 1600 FREQUENCY (MHz) 2000 30202275 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Differential Output Impedance 60 50 50 40 OUTPUT IMPEDANCE () INPUT IMPEDANCE () Single Ended Input Impedance R jX 40 30 20 10 0 -10 R jX 30 20 10 0 -10 -20 -30 -40 -20 -50 0 400 800 1200 1600 FREQUENCY (MHz) 2000 0 400 800 1200 1600 FREQUENCY (MHz) 30202288 30202276 Power Sweep Crosstalk 0 20 -10 f = 100 MHz Gain = 26dB -20 CROSSTALK (dBc) 15 POUT (dBm) 2000 10 5 0 -30 -40 -50 -60 -70 -80 -90 -5 -100 -25 -20 -15 -10 PIN (dBm) -5 0 10 30202285 100 1k FREQUENCY (MHz) 10k 30202291 Channel A to Channel B Gain and Phase Matching Gain Phase GAIN MATCHING (dB) 1.4 1.6 1.4 1.2 1.2 1.0 1.0 0.8 f = 100 MHz CH A - CHB 0.6 0.8 0.6 0.4 0.4 0.2 0.2 0.0 PHASE MATCHING (Degrees) 1.6 0.0 6 8 10 12 14 16 18 20 22 24 26 GAIN SETTING (dB) 30202296 Copyright (c) 1999-2012, Texas Instruments Incorporated 13 LMH6882 Application Information 30202234 FIGURE 1. LMH6882 Typical Application INTRODUCTION The LMH6882 is a fully differential amplifier optimized for signal path applications up to 1000 MHz. The LMH6882 has a 100 input and a low impedance output. The gain is digitally controlled over a 20dB range from 26dB to 6dB. The LMH6882 is designed to replace fixed gain differential amplifiers with a single, flexible gain device. It has been designed to provide good noise figure and OIP3 over the entire gain range. This design feature is highlighted by the Dynamic Range Figure (DRF). The DRF is defined as the input thrid order intercept point (IIP3) minus the noise figure (NF). Traditional variable gain amplifiers generally have the best OIP3 and NF performance at maximum gain only. 30202232 FIGURE 2. LMH6882 Block Diagram 14 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 BASIC CONNECTIONS A voltage between 4.75 V and 5.25 V should be applied to pins 3, 4, 24, 25. Each supply pin should be decoupled with a low inductance, surface-mount ceramic capacitor of 0.01uF as close to the device as possible. When vias are used to connect the bypass capacitors to a ground plane the vias should be used in pairs to help minimize parasitic inductance. Using pairs of bypass capacitors will also help reduce parasitic inductance between the amplifier power pins and ground. The LMH6881 has internally terminated inputs. The INMD and INPD pins are intended to be the differential input pins and are terminated with a 100 Ohm differential resistor. The INMS and INPS pins are intended to be used for single ended inputs and have been designed to support single ended termination of 50 Ohms (active termination). If the single ended input pins are used for a differential signal the internal termination will appear to be a 36 Ohm differential load. When using the LMH6881 differential input pins the unused single ended input pins should be left disconnected. Likewise when the single ended input pins are used the differential input pins should be left disconnected. Unused input pins should not be terminated or connected to ground. The outputs of the LMH6882 need to be biased close to 2.5V for best performance. The actual voltage of the output pins is set by the OCM pin. There is a gain of 2 between the OCM pin and the output pins so that the OCM voltage should be close to 1.25V. The input pins are self biased to 2.5V. When using the LMH6882 for DC coupled applications make sure to keep the input and output common mode voltages close to the 2.5V requirement. When using the LMH6882 in parallel mode the gain can be set in 2dB increments. If fixed gain is desired the pins can be strapped to ground or VCC as required. For finer gain control the LMH6882 supports SPI compliant digital control which allows the gain to be set in 0.25dB increments between 26dB and 6dB. The gain is defined as voltage gain. If power gain is required the source and load resistances need to be factored into the gain calculation. The LMH6882 has a shutdown pin to enable power savings when the amplifier is not being used. For example, in a time division duplex (TDD) system the receiver may be shutdown during transmit to save power and to protect the receive analog to digital converter (ADC) from overload signals. 30202201 FIGURE 3. Basic Connections Schematic, Differential Input Copyright (c) 1999-2012, Texas Instruments Incorporated 15 LMH6882 30202294 FIGURE 4. Basic Connections Schematic, Single Ended INPUT CHARACTERISTICS The LMH6882 input impedance is set by internal resistors to a nominal 100. Process variations will result in a range of values. At higher frequencies parasitic reactances will start to impact the impedance. This characteristic will also depend on board layout and should be verified on the customer's system board. At the maximum gain of 26dB the input signal will be much smaller than the output and the output may saturate or clip well before the input reaches the maximum signal amplitude. If the input is over driven, the input signal cannot swing more than 0.5V below the negative supply voltage (normally 0V) nor should it exceed the positive supply voltage. The input signal will clip and cause severe distortion if it is too large. Because the input stage self biases to approximately mid rail the supply voltage will impose the limit for input voltage swing. At higher frequencies the LMH6882 input impedance is not purely resistive. The LMH6882 input may also be a different value than desired. This would be the case when connecting the LMH6882 directly to a mixer. It is possible to make narrow band LC impedance transform circuits to match the LMH6882 to other impedances. As an example Figure 5 shows a circuit that coverts 200 Ohms to 100 Ohms at 200MHz. For an easy way to calculate the L and C circuit values there are several options for online tools or downloadable programs. The following tool might be helpful. http://www.circuitsage.com/matching/matcher2.html Excel can also be used for simple circuits; however, the "Analysis ToolPak" add-in must be installed to calculate complex numbers. 30202269 FIGURE 5. Differential LC Conversion Circuit 16 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 OUTPUT CHARACTERISTICS The LMH6882 has a low impedance output very similar to a traditional Op-amp output. This means that a wide range of loads can be driven with good performance. Matching load impedance for proper termination of filters is as easy as inserting the proper value of resistor between the filter and the amplifier. This flexibility makes system design and gain calculations very easy. By using a differential output stage the LMH6882 can achieve very large voltage swings on a single 5V supply. This is illustrated in Figure 6. This figure shows how a voltage swing of 5VPPD is realized while only swinging 2.5 VPP on each output. The LMH6882 can swing up to 10 VPPD which is sufficient to drive most ADCs to full scale while using a matched impedance anti alias filter between the amplifier and the ADC. The LMH6882 has been designed for AC coupled applications and has been optimized for operation above 5 MHz. 5.0 4.5 4VPPD 4.0 VOUT (V) 3.5 3.0 2.5 2VPP 2.0 1.5 1.0 Out Plus Out Minus Differential Vout 0.5 0.0 0.000.631.261.892.523.153.784.415.045.676.30 PHASE ANGLE (Radians) 30202266 FIGURE 6. Differential Output Voltage Like most closed loop amplifiers the LMH6882 output stage can be sensitive to capacitive loading. Best practise is to place the external termination resistors as close to the amplifier output pins as possible. Due to reactive components between the output and the filter input it may be desirable to use even smaller value resistors than a simple calculation would indicate. For instance, at 200 MHz resistors of 30 Ohms provide slightly better OIP3 performance on the LMH6882EVAL evaluation board and may also provide a better match to the filter input. The ability of the LMH6882 to drive low impedance loads while maintaining excellent OIP3 performance creates an opportunity to greatly increase power gain and drive low impedance filters. This gives the system designer much needed flexibility in filter design. In many cases using a lower impedance filter will provide better component values for the filter. Another benefit of low impedance filters is that they are less likely to be influenced by circuit board parasitic reactances such as pad capacitance or trace inductance. The LMH6881 is a voltage amplifier. Power gain is dependent on load conditions. See Figure 7 for details on power gain with respect to different load conditions. The graph was prepared for the 26dB gain setting. Other gain settings will behave with the same. POWER GAIN AT LOAD (dB) 24 22 20 18 16 14 12 0 100 200 300 LOAD IMPEDANCE () 400 30202279 FIGURE 7. Power Gain vs Filter Impedance Matching Resistor Loss = 6dB Copyright (c) 1999-2012, Texas Instruments Incorporated 17 LMH6882 Printed circuit board (PCB) design is critical to high frequency performance. In order to ensure output stability the load matching resistors should be placed as close to the amplifier output pins as possible. This allows the matching resistors to mask the board parasitics from the amplifier output circuit. An example of this is shown in Figure 8. Also note that there the low pass filter uses center tapped capacitors. Having capacitors to ground provides a path for high frequency, common mode energy to dissipate. This is equally valuable for the ADC, so there are also capacitors to ground on the ADC side of the filter. The LMH6881EVAL evaluation board is available to serve a guide for system board layout. See also application note AN-2235 for more details. 30202268 FIGURE 8. Single Ended Input, DC coupled Common Mode Voltage Divider on Output 30202283 FIGURE 9. Differential Input, DC coupled Common Mode Voltage Divider on Output 30202240 FIGURE 10. Single Ended Input, Differential Output Cable Driver 18 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 DIGITAL CONTROL The LMH6882 will support two modes of control, parallel mode and serial mode (SPI compatible). Parallel mode is fastest and requires the most board space for logic line routing. Serial mode is compatible with existing SPI compatible systems. The LMH6882 has gain settings covering a range of 20 dB. To avoid undesirable signal transients the LMH6882 should not be powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs. While the full gain range is available in parallel mode both channels must be set to the same gain. If independent channel control is desired SPI mode must be used. The LMH6882 was designed to interface with 2.5V to 5V CMOS logic circuits. If operation with 5V logic is required care should be taken to avoid signal transients exceeding the DVGA supply voltage. Long, unterminated digital signal traces are particularly susceptible to these transients. Signal voltages on the logic pins that exceed the device power supply voltage may trigger ESD protection circuits and cause unreliable operation. Some pins on the LMH6882 have different functions depending on the digital control mode. These functions will be described in the sections to follow. Pins with Dual Functions Pin SPI = 0 SPI = 1 7 D1 SDI 14 D0 SDO* 8 D2 CLK 9 D3 CS (active low) Pin 4 requires external bias. See Serial Mode Section for Details. PARALLEL INTERFACE Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control lines. To place the LMH6882 into parallel mode the SPI pin (pin 5) is set to the logical zero state. Alternately the SPI pin can be connected directly to ground. The attenuator control pins are internally biased, but not all pins are biased to the same voltage, for best results all digital pins should be actively driven to the desired state. The SPI pin has a weak internal resistor to ground. The SD pin will bias to a low logic state which puts both amplifiers in the ON or active state. The LMH6882 has a 7-bit gain control bus. Data from the gain control pins is immediately sent to the gain circuit (i.e. gain is changed immediately). To minimize gain change glitches all gain pins should change at the same time. Gain glitches could result from timing skew between the gain set bits. This is especially the case when a small gain change requires a change in state of three or more gain control pins. If necessary the DVGA could be put into a disabled state while the gain pins are reconfigured and then brought active when they have settled. PIN Name Gain Step Size (dB) 14 D0 0.25 7 D1 0.5 8 D2 1 9 D3 2 21 D4 4 20 D5 8 19 D6 16 Gain combinations that exceed 80 will result in minimum gain of 6dB. The SD pin is provided to reduce power consumption by disabling the highest power portions of the LMH6882. The gain register will preserve the last active gain setting during the disabled state. For individual channel control see the SPI control section. Copyright (c) 1999-2012, Texas Instruments Incorporated 19 LMH6882 30202217 FIGURE 11. Parallel Mode Connection SPI COMPATIBLE SERIAL INTERFACE The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The LMH6882 serial interface is a generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers and DSP controllers.Using only 4 wires for both channels allows for significant board space savings. The trade off for this reduced board complexity is slower response time in gain state changes. For systems where gain is changed only infrequently or where only slow gain changes are required serial mode is the best choice. To place the LMH6882 into serial mode the SPI pin (Pin 5) should be put into the logic high state. Alternatively the SPI pin an be connected directly to the 5V supply bus. The serial mode is active when the SPI pin is set to a logic 1 state. In this configuration the pins function as shown in the pin description table. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out, and serial chip select (CS). The chip select pin is active low. The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode. The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge; and to source the output data on the SDO pin on the falling edge. The user may disable clock and hold it in the low state, as long as the clock pulse-width minimum specification is not violated when the clock is enabled or disabled. The CS pin is the chip select pin. This pin is active low, the chip is selected in the logic low state. Each assertion starts a new register access - i.e., the SDATA field protocol is required. The user is required to de-assert this signal after the 16th clock. If the CSb pin is de-asserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shiftedin and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the deasserted pulse - which is specified in the Electrical Specifications section. The SDI pin is the input pin for the serial data. It must observe setup / hold requirements with respect to the SCLK. Each cycle is 16-bits long The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when CSb is asserted. Upon CSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges. Upon power-up, the default register address is 00h. The SDO pin requires external bias for clock speeds over 1MHz. See Figure 13 for details on sizing the external bias resistor. Because the SDO pin is a high impedance pin, the board capacitance present at the pin will restrict data out speed that can be achieved. For a RC limited circuit the frequency is ~ 1/ (2*Pi*RC). As shown in the figure resistor values of 300 to 2000 Ohms are recommended. Each serial interface access cycle is exactly 16 bits long as shown in Figure 12. Each signal's function is described below. the read timing is shown in Figure 14, while the write timing is shown in Figure 15. 20 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 30202212 FIGURE 12. Serial Interface Protocol (SPI compatible) 30202214 FIGURE 13. Internal Operation of the SDO pin R/Wb Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation. Reserved Not used. Must be set to 0. ADDR: Address of register to be read or written. DATA In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted. In a read operation this field is ignored. Copyright (c) 1999-2012, Texas Instruments Incorporated 21 LMH6882 30202211 FIGURE 14. Read Timing Read Timing Data Output on SDO Pin Parameter Description tCSH Chip select hold time tCSS Chip select setup time tOZD Initial output data delay tODZ High impedance delay tOD Output data delay 30202210 FIGURE 15. Write Timing Data Written to SDI Pin 22 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Write Timing Data Input on SDI Pin Parameter Description tPL Minimum clock low time (clock duty dycle) tPH Minimum clock high time (clock duty cycle) tSU Input data setup time tH Input data hold time Address R/W Name Default Value Hex (Dec) 0 R Revision ID 1 (1) 1 R Product ID 21 (33) 2 R/W Power Control 0 (0) 3 R/W Attenuation A 50 (80) 4 R/W Attenuation B 50 (80) 5 R/W Channel Control 3 (3) Serial Word Format for Register 2: Power Control 7 6 5 4 3 2 1 0 RES RES CHA1 CHB1 CHA2 CHB2 RES RES CHA1 and CHA2 = 0 for ON, CHA1 and CHA2 = 1 for OFF CHB1 and CHB2 = 0 for ON, CHB1 and CHB2 = 1 for OFF Serial Word Format for Registers 3, 4: Gain Control 7 6 5 4 3 RES Gain = 26 -- (register value * 0.25) valid range is 0 to 80 2 1 0 Serial Word Format for Register 5: Channel Control 7 RES 6 5 4 3 2 1 1 SYNC Load A Load B The Channel Control register controls how registers 3 and 4 work. When the SYNC bit is set to 1 both channel A and channel B are set to the gain indicated in register 3. When the SYNC bit is set to zero register 3 controls channel A and register 4 controls channel B. When the Load A bit is zero data written to register 3 does not transfer to channel A. When the Load A bit is set to 1 the gain of channel A is set equal to the value indicated in register 3. The Load B bit works the same for channel B and register 4. USB2ANY SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE The LMH6882EVAL evaluation board comes with the USB2ANY USB to SPI control board and supporting software. The USB2ANY board will connect to the LMH6882 evaluation board with the included adapter and provides a simple way to test and evaluate the SPI interface. For more details refer to the LMH6882EVAL user's guide. The evaluation board user's guide provides instructions on connecting the USB2ANY board to the evaluation board. SPISU2 SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE NOTE: The SPISU2 board is obsolete, the following paragraph is for legacy systems only. Also available separately from the LMH6882EVAL evaluation board is a USB to SPI control board and supporting software. The SPISU2 board will connect directly to the LMH6882 evaluation board and provides a simple way to test and evaluate the SPI interface. For more details refer to the LMH6882EVAL user's guide. The evaluation board user's guide provides instructions on connecting the SPISU2 board and for configuring the TinyI2CSPI software. THERMAL MANAGEMENT The LMH6882 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It is recommended, but not necessary, that the exposed pad be connected to the supply ground plane. In any case, the thermal dissipation of the device is largely dependent on the attachment of this pad to the system printed circuit board (PCB). The exposed pad should be attached to as much copper on the PCB as possible, preferably external copper. However, it is also very important to maintain good high speed layout practices when designing a system board. Please refer to the LMH6882 evaluation board for suggested layout techniques. The LMH6882EVAL evaluation board was designed for both signal integrity and thermal dissipation. The LMH6882EVAL has eight layers of copper. The inner copper layers are one ounce copper and are as solid as design constraints allow. The exterior copper layers are one ounce copper in order to allow fine geometry etching. The benefit of this board design is significant. Copyright (c) 1999-2012, Texas Instruments Incorporated 23 LMH6882 Applying a heat sink to the package will also help to remove heat from the device. The ATS-54150K-C2-R0 heat sink, manufactured by Advanced Thermal Solutions, provided good results in lab testing. Using both a heat sink and a good board thermal design will provide the best cooling results. If a heat sink will not fit in the system design, the external case can be used as a heat sink. INTERFACING TO AN ADC The LMH6882 was designed to be used with high speed ADCs such as the THS5400. As shown in the Typical Application on page 1, DC coupling provides the best flexibility especially for first Nyquist applications. The inputs of the LMH6882 will self bias to the optimum voltage for normal operation. The internal bias voltage for the inputs is approximately mid rail which is 2.5V with the typical 5V power supply condition. If DC coupling is not required it is usually easier to AC couple the amplifier to other stages. ADC Noise Filter Below are schematics and a table of values for second order Butterworth response filters for some common IF frequencies. These filters, shown in Figure 16, offer a good compromise between bandwidth, noise rejection and cost. This filter topology is the same as is used on the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12, 14 and 16 bit analog to digital converters shown in the table. Filter Component Values Center Frequency 75 MHz 150 MHz 180 MHz 250 MHz Bandwidth 40 MHz 60 MHz 75 MHz 100 MHz R1, R2 L1, L2 90 390 nH 90 370 nH 90 300 nH 90 225 nH C1, C2 10 pF 3 pF 2.7 pF 1.9 pF C3 22 pF 19 pF 15 pF 11 pF L5 220 nH 62 nH 54 nH 36 nH R3, R4 100 100 100 100 Resistor values are approximate, but have been reduced due to the internal 10 Ohms of output resistance per pin. 30202213 FIGURE 16. Sample Filter POWER SUPPLIES The LMH6882 was designed primarily to be operated on 5V power supplies. The voltage range for V+ is 4.75V to 5.25V. Power supply accuracy of 2.5% or better is advised. When operated on a board with high speed digital signals it is important to provide isolation between digital signal noise and the LMH6882 inputs. The SP16160CH1RB reference board provides an example of good board layout. 24 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS Product Number Max Sampling Rate (MSPS) Resolution Channels ADC12L063 62 12 SINGLE ADC12DL065 65 12 DUAL ADC12L066 66 12 SINGLE ADC12DL066 66 12 DUAL CLC5957 70 12 SINGLE ADC12L080 80 12 SINGLE ADC12DL080 80 12 DUAL ADC12C080 80 12 SINGLE ADC12C105 105 12 SINGLE ADC12C170 170 12 SINGLE ADC12V170 170 12 SINGLE ADC14C080 80 14 SINGLE ADC14C105 105 14 SINGLE ADC14DS105 105 14 DUAL ADC14155 155 14 SINGLE ADC14V155 155 14 SINGLE ADC16V130 130 16 SINGLE ADC16DV160 160 16 DUAL ADC08D500 500 8 DUAL ADC08500 500 8 SINGLE ADC08D1000 1000 8 DUAL ADC081000 1000 8 SINGLE ADC08D1500 1500 8 DUAL ADC081500 1500 8 SINGLE ADC08(B)3000 3000 8 SINGLE ADC08L060 60 8 SINGLE ADC08060 60 8 SINGLE ADC10DL065 65 10 DUAL ADC10065 65 10 SINGLE ADC10080 80 10 SINGLE ADC08100 100 8 SINGLE ADCS9888 170 8 SINGLE ADC08(B)200 200 8 SINGLE ADC11C125 125 11 SINGLE ADC11C170 170 11 SINGLE Copyright (c) 1999-2012, Texas Instruments Incorporated 25 LMH6882 Application Board 30202295 FIGURE 17. 26 Copyright (c) 1999-2012, Texas Instruments Incorporated LMH6882 Physical Dimensions inches (millimeters) unless otherwise noted 36-Pin Package NS Package Number SQA36A Copyright (c) 1999-2012, Texas Instruments Incorporated 27 Notes Copyright (c) 1999-2012, Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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