LMK00301SQE/NOPB - NATIONAL SEMICONDUCTOR

LMH6882

General Purpose, Dual, Differential Amplifier With Gain Control

General Description

The LMH6882 is a general purpose high performance differ-

ential amplifier with gain control. One of its main features is

that it is very easy to use compared to traditional differential

amplifier. These amplifiers normally present configuration

challenges to obtain desired gain, noise figure, linearity and

impedance all at once. The LMH6882 can easily be config-

ured to address these challenges.

The LMH6882 is optimized to provide a best in class figure of

merit (FOM) for dynamic range. This figure of merit is defined

as the difference between the IIP3 and the NF which is one

term in the spurious free dynamic range equation.

The LMH6882 is targeted to work in a broad range of appli-

cations. The easy to use features combined with its high

performance design make it suitable for communication ap-

plications as well as instrumentation applications.

The LMH6882 is fabricated in TI’s CBiCMOS8 proprietary

complementary silicon germanium process and is available in

a space saving, thermally enhanced 36-pin Lead Quad LLP

package for higher performance.

Features

●Small Signal Bandwidth: 2400MHz

●OIP3 @ 100 MHz: 42dBm

●HD2 @ 200 MHz: −65dBc

●Voltage Gain: 26dB

●Noise Figure: 9.7dB

●Dynamic Range Figure of Merit: 6.3dB

●Gain Range: 26dB to 6dB

●Parallel and Serial Gain Control

●Power Down

●Small footprint LLP Package

●Also Available as a Single: LMH6881

Applications

●General Purpose Differential Amplifier

●Differential ADC Driver

●Wideband Direct Conversion

●SAW Filter Buffer/Driver

●Twisted Pair Cable Driver

Performance Curve

Dynamic Range Performance

6 8 10 12 14 16 18 20 22 24 26

DRF = IIP3 - NF

OIP3

Noise Figure

Dynamic Range Figure

30202292

SPI™ is a trademark of Motorola, Inc.

PRODUCTION DATA information is current as of

publication date. Products conform to specifications per

the terms of the Texas Instruments standard warranty.

Production processing does not necessarily include

testing of all parameters.

Table of Contents

General Description .............................................................................................................................. 1

Features .............................................................................................................................................. 1

Applications ......................................................................................................................................... 1

Performance Curve ............................................................................................................................... 1

Absolute Maximum Ratings .................................................................................................................... 4

Operating Ratings (Note 1).................................................................................................................... 4

Connection Diagram ............................................................................................................................. 6

Ordering Information ............................................................................................................................. 6

Typical Performance Characteristics ....................................................................................................... 8

Application Information ........................................................................................................................ 14

INTRODUCTION ......................................................................................................................... 14

BASIC CONNECTIONS ............................................................................................................... 15

INPUT CHARACTERISTICS ......................................................................................................... 16

OUTPUT CHARACTERISTICS ..................................................................................................... 17

DIGITAL CONTROL .................................................................................................................... 19

PARALLEL INTERFACE .............................................................................................................. 19

SPI COMPATIBLE SERIAL INTERFACE ........................................................................................ 20

USB2ANY SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE ................................................... 23

SPISU2 SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE ....................................................... 23

THERMAL MANAGEMENT .......................................................................................................... 23

INTERFACING TO AN ADC ......................................................................................................... 24

ADC Noise Filter .................................................................................................................. 24

POWER SUPPLIES ..................................................................................................................... 24

COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS ................................................. 25

Application Board ........................................................................................................................ 26

Physical Dimensions ........................................................................................................................... 27

List of Figures

FIGURE 1. LMH6882 Typical Application ...................................................................................................... 14

FIGURE 2. LMH6882 Block Diagram ............................................................................................................ 14

FIGURE 3. Basic Connections Schematic, Differential Input ................................................................................ 15

FIGURE 4. Basic Connections Schematic, Single Ended ................................................................................... 16

FIGURE 5. Differential LC Conversion Circuit ................................................................................................. 16

FIGURE 6. Differential Output Voltage .......................................................................................................... 17

FIGURE 7. Power Gain vs Filter ImpedanceMatching Resistor Loss = 6dB .............................................................. 17

FIGURE 8. Single Ended Input, DC coupledCommon Mode Voltage Divider on Output ............................................... 18

FIGURE 9. Differential Input, DC coupledCommon Mode Voltage Divider on Output .................................................. 18

FIGURE 10. Single Ended Input, Differential Output Cable Driver ......................................................................... 18

FIGURE 11. Parallel Mode Connection ........................................................................................................ 20

FIGURE 12. Serial Interface Protocol (SPI compatible) ...................................................................................... 21

FIGURE 13. Internal Operation of the SDO pin ................................................................................................ 21

FIGURE 14. Read Timing ......................................................................................................................... 22

FIGURE 15. Write TimingData Written to SDI Pin ............................................................................................ 22

FIGURE 16. Sample Filter ......................................................................................................................... 24

FIGURE 17. .......................................................................................................................................... 26

LMH6882

Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for

availability and specifications.

ESD Tolerance (Note 2)

Human Body Model 1 kV

Charged Device Model 250V

Positive Supply Voltage (Pin 3) −0.6V to 5.5V

Differential Voltage between Any

Two Grounds <200 mV

Analog Input Voltage Range −0.6V to 5.5V

Digital Input Voltage Range −0.6V to 5.5V

Output Short Circuit Duration

(one pin to ground) Infinite

Junction Temperature +150°C

Storage Temperature Range −65°C to +150°C

Soldering Information

Infrared or Convection (30 sec) 260°C

Operating Ratings (Note 1)

Supply Voltage (Pin 3) 4.75V to 5.25V

Differential Voltage Between Any Two Grounds <10 mV

Analog Input Voltage Range,

AC Coupled 0V to V+

Temperature Range (Note 3) −40°C to +85°C

Thermal Properties

Package Thermal Resistance (Note 9)(θJA) (θJC)

36pin LLP 39°C/W 7.3°C/W

5V Electrical Characteristics (Note 4)

The following specifications apply for single supply with V+ = 5V, Maximum Gain (26dB), RL = 200Ω, Boldface limits apply at

temperature extremes.

Symbol Parameter Conditions Min

(Note 6)

Typ

(Note 5)

Max

(Note 6)Units

Dynamic Performance

3dBBW −3dB Bandwidth VOUT= 2 VPPD 2.4 GHz

NF Noise Figure Source = 100Ω 9.7 dB

OIP3 Output Third Order Intercept Point f = 100 MHz, VOUT = 4 dBm per tone 42 dBm

Output Third Order Intercept Point f = 200 MHz, VOUT = 4 dBm per tone 40

OIP2 Output Second Order Intercept

Point

POUT= 4 dBm per Tone, f1 =112.5 MHz,

f2=187.5 MHz

76 dBm

IMD3 Third Order Intermodulation

Products

f = 100 MHz, VOUT = 4 dBm per tone −76 dBc

Third Order Intermodulation

Products

f = 200 MHz, VOUT = 4 dBm per tone −72

P1dB 1dB Compression Point 17 dBm

HD2 Second Order Harmonic Distortion f = 200 MHz, VOUT =4dBm −65 dBc

HD3 Third Order Harmonic Distortion f = 200 MHz, VOUT =4dBm −74 dBc

CMRR Common Mode Rejection Pin = −15 dBm, f = 100 MHz −40 dBc

Analog I/O

RIN Input Resistance Differential 100 Ω

RIN Input Resistance Single Ended, 50Ω termination on

unused input

50 Ω

VICM Input Common Mode Voltage Self Biased 2.5 V

LMH6882

Symbol Parameter Conditions Min

(Note 6)

Typ

(Note 5)

Max

(Note 6)Units

Maximum Input Voltage Swing Volts peak to peak, differential 2 VPPD

Maximum DIfferential Output

Voltage Swing

Differential, f < 10MHz 6 VPPD

ROUT Output Resistance Differential, f = 100MHz 0.4 Ω

Gain Parameters

Maximum Voltage Gain Gain Code = 0 26 dB

Minimum Gain Gain Code = 80d or 50h 6 dB

Gain Steps 80

Gain Step Size 0.25 dB

Gain Step Error Any two adjacent steps over entire range ±0.125 dB

Gain Step Phase Shift Any two adjacent steps over entire range ±3 Degrees

Gain Step Switching Time 20 ns

Enable/ Disable Time Settled to 90% level 15 ns

Power Requirements

ICC Supply Current 200 270 mA

P Power 1 W

ICC Disabled Supply Current 25 mA

All Digital Inputs

Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS, 5V CMOS

VIL Logic Input Low Voltage 0.4 V

VIH Logic Input High Voltage 2.0-5.0 V

IIH Logic Input High Input Current Digital Input Voltage = 2.0V −9 μA

IIL Logic Input Low Input Current Digital Input Voltage = 0.4V −47 μA

Parallel Mode Timing

tGS Setup Time 3 ns

tGH Hold Time 3 ns

Serial Mode

fCLK SPI Clock Frequency 50% duty cycle, ATE tested @ 20MHz 10 50 MHz

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.

Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)

Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is

PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.

Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the

electrical tables under conditions different than those tested

Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will

also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.

Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality

Control (SQC) methods.

Note 7: Negative input current implies current flowing out of the device.

Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.

Note 9: Junction to ambient (θJA) thermal resistance measured on JEDEC 4 layer board. Junction to case (θJC) thermal resistance measured at exposed thermal

pad; package is not mounted to any PCB.

Note 10: LMH6881 devices have been used for some typical performance plots. Due to differences in packaging there are small differences in performance.

LMH6882

Connection Diagram

36-Pin LLP

30202203

Top View

Ordering Information

Package Part Number Package Marking Transport Media NSC Drawing

36-Pin LLP LMH6882SQE L6882 250 Units Tape and Reel SQA36A

LMH6882SQ 2k Units Tape and Reel

Pin Descriptions

Pin Number Symbol Pin Category Description

Analog I/O

11,12, 16,17 INPD, INMD Analog Input Differential inputs 100Ω

10,13, 15,17 INPS, INMS Analog INPUTt Single ended inputs 50Ω

35,34 ,30,29 OUTP, OUTM Analog Output Differential outputs, low impedance

Power

5,6,22, 23 GND Ground Ground pins. Connect to low impedance ground

plane. All pin voltages are specified with respect

to the voltage on these pins. The exposed

thermal pad is internally bonded to the ground

pins.

3,4,24, 25 VCC Power Power supply pins. Valid power supply range is

4.75V to 5.25V.

Exposed Center

Pad

Thermal/ Ground Thermal management/ Ground

Digital Inputs

27 SPI Digital Input 0= Parallel Mode, 1 = Serial Mode

LMH6882

Pin Number Symbol Pin Category Description

Parallel Mode Digital Pins, SPI= Logic Low

14, 7,8,9,21,29,19 D0, D1, D2, D3,

D4,D5,D6

Digital Input Attenuator control, D0 = 0.25dB, D6 = 16dB

1 SD Digital Input Shutdown 0 = amp on, 1 = amp off

Serial Mode Digital Pins, SPI= Logic High

SPI™ Compatible

14 SDO Digital Output- Open Emitter Serial Data Output (Requires external bias.)

7 SDI Digital Input Serial Data In

9 CS Digital Input Chip Select (active low)

8 CLK Digital Input Clock

LMH6882

Typical Performance Characteristics (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, Unless

Specified).(Note 10)

Frequency Response over Gain Range

1 10 100 1k 10k

-15

-10

-5

GAIN (dB)

FREQUENCY (MHz)

30202287

OIP3 vs Gain Setting

6 8 10 12 14 16 18 20 22 24 26

OIP3 (dBc)

VOLTAGE GAIN (dB)

f = 100 MHz

POUT = 4dBm

30202253

OIP3 vs Output Power

-4 -2 0 2 4 6 8 10

OIP3 (dBm)

OUTPUT POWER, EACH TONE (dBm)

30202261

Dynamic Range Figure vs Gain Setting

6 8 10 12 14 16 18 20 22 24 26

DRF = IIP3 - NF

OIP3

Noise Figure

Dynamic Range Figure

30202292

OIP3 vs Frequency

0 100 200 300 400

OIP3 (dBm)

FREQUENCY (MHz)

26 dB

16 dB

6 dB

30202256

OIP3 vs Supply Voltage

4.50 4.75 5.00 5.25 5.50

30.0

35.0

40.0

45.0

50.0

OIP3 (dBm)

SUPPLY VOLTAGE (V)

26 dB

16 dB

6 dB

30202255

LMH6882

OIP3 vs Temperature

6 8 10 12 14 16 18 20 22 24 26

OIP3 (dBm)

GAIN SETTING (dB)

f = 100 MHz

POUT = 4dBm

- 40 °C

25 °C

85 °C

30202273

OIP2 vs Gain Setting

6 8 10 12 14 16 18 20 22 24 26

OIP2 (dBm)

GAIN SETTING (dB)

f1 = 187.5 MHz

f2 = 112.5 MHz

PPOUT = 4dBm

30202293

Supply Current vs Temperature

-45 -30 -15 0 15 30 45 60 75 90

100

SUPPLY CURRENT (mA)

TEMPERATURE (°C)

30202258

Maximum Gain vs Temperature

-45 -30 -15 0 15 30 45 60 75 90

24.0

24.5

25.0

25.5

26.0

26.5

27.0

MAXIMUM GAIN (dB)

TEMPERATURE (°C)

f = 100 MHz

POUT = 4.5dBm

30202259

HD2 vs Frequency, Differential Input

0 50 100 150 200 250 300 350 400

-100

-90

-80

-70

-60

-50

-40

-30

-20

HD2 (dBc)

FREQUENCY (MHz)

POUT= 4 dBm

26 dB

16 dB

6 dB

30202226

HD3 vs Frequency, Differential Input

0 50 100 150 200 250 300 350 400

-100

-90

-80

-70

-60

-50

-40

-30

-20

HD3 (dBc)

FREQUENCY (MHz)

POUT=4dBm

26 dB

16 dB

6 dB

30202227

LMH6882

HD2 vs Frequency, Single Ended Input

0 50 100 150 200 250 300 350 400

-100

-90

-80

-70

-60

-50

-40

-30

-20

HD2 (dBc)

FREQUENCY (MHz)

POUT=4dBm

26 dB

16 dB

6 dB

30202224

HD3 vs Frequency, Single Ended Input

0 100 200 300 400

-100

-90

-80

-70

-60

-50

-40

-30

HD3 (dBc)

FREQUENCY (MHz)

POUT = 4dBm

26 dB

16 dB

6 dB

30202225

HD2 & HD3 vs Gain Setting

Differential Input

6 8 10 12 14 16 18 20 22 24 26

-120

-110

-100

-90

-80

-70

-60

-50

f = 100 MHz

POUT = 4dBm

HD2

HD3

30202263

HD2 & HD3vs Gain Setting

Single Ended Input

6 8 10 12 14 16 18 20 22 24 26

-110

-100

-90

-80

-70

-60

-50

-40

-30

HD2, HD3 (dBc)

GAIN SETTING (dB)

f = 100 MHz

30202271

HD2 vs Output Power

0 2 4 6 8 10 12 14 16

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

HD2 (dBc)

OUTPUT POWER (dBm)

26 dB

21 dB

10 dB

30202220

HD3 vs Output Power

0 2 4 6 8 10 12 14 16

-110

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

HD3 (dBc)

POUT (dBm)

26 dB

21 dB

10 dB

30202221

LMH6882

Gain Step Amplitude Error

0.0010.0020.0030.0040.0050.0060.0070.0080.00

0.0

0.1

0.2

0.3

0.4

0.5

ATTENUATOR STEP SIZE (dB)

ATTENUATION STEP (SPI MODE)

Step 0 = 26dB

Step 80 = 6dB

50 MHz

200 MHz

30202236

Gain Step Phase Error

0 10 20 30 40 50 60 70 80

-3.0

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

PHASE CHANGE (Degrees)

ATTENUATION STEP (SPI MODE)

Step 0 = 26 dB

Step 80 = 6 dB

50 MHz

200 MHz

30202239

Cumulative Amplitude Error

0 10 20 30 40 50 60 70 80

-0.5

-0.4

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

AMPLITUDE ERROR (dB)

ATTENUATION STEP (SPI MODE)

Step 0 = 26 dB

Step 80 = 6 dB

50 MHz

200 MHz

30202237

Cumulative Phase Error

0 10 20 30 40 50 60 70 80

-5

-4

-3

-2

-1

PHASE ERROR (Degrees)

ATTENUATION STEP (SPI MODE)

Step 0 = 26 dB

Step 80 = 6 dB

50 MHz

200 MHz

30202238

Noise Figure vs Gain Setting

6 8 10 12 14 16 18 20 22 24 26

NOISE FIGURE (dB)

GAIN SETTING (dB)

30202250

Noise Figure vs Gain Setting, Single Ended Input

6 8 10 12 14 16 18 20 22 24 26

NOISE FIGURE (dB)

GAIN SETTING (dB)

Single Ended Input

f = 100MHz

30202245

LMH6882

Noise Figure vs Frequency

0 200 400 600 800 1000

NOISE FIGURE (dB)

FREQUENCY (MHz)

30202251

Shutdown Timing

Using SD Pin

0 10 20 30 40 50 60 70 80 90 100

-1

-2

-1

VOUT (V)

TIME (ns)

ENA PIN (V)

Enable Pin

Output

30202248

Gain Step Timing, 16dB Step

Parallel Mode

0 10 20 30 40 50 60 70 80 90 100

-1

-2

-1

VOUT (V)

TIME (ns)

A4 PIN (V)

D3 Pin

Ouptut

30202242

Gain Step Timing, 8dB Step

Parallel Mode

0 10 20 30 40 50 60 70 80 90 100

-1

-2

-1

VOUT (V)

TIME (ns)

D2 PIN (V)

D2 Pin

Output

30202243

CMRR vs Frequency

1 10 100 1k

-60

-50

-40

-30

-20

-10

CMRR (dB)

FREQUENCY (MHz)

30202241

Differential Input Impedance

0 400 800 1200 1600 2000

-50

-25

100

125

INPUT IMPEDANCE (Ω)

FREQUENCY (MHz)

30202275

LMH6882

Single Ended Input Impedance

0 400 800 1200 1600 2000

-20

-10

INPUT IMPEDANCE (Ω)

FREQUENCY (MHz)

30202288

Differential Output Impedance

0 400 800 1200 1600 2000

-50

-40

-30

-20

-10

OUTPUT IMPEDANCE (Ω)

FREQUENCY (MHz)

30202276

Power Sweep

-25 -20 -15 -10 -5 0

-5

POUT (dBm)

PIN (dBm)

f = 100 MHz

Gain = 26dB

30202285

Crosstalk

10 100 1k 10k

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

CROSSTALK (dBc)

FREQUENCY (MHz)

30202291

Channel A to Channel B Gain and Phase Matching

6 8 10 12 14 16 18 20 22 24 26

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

GAIN MATCHING (dB)

GAIN SETTING (dB)

PHASE MATCHING (Degrees)

f = 100 MHz

CH A - CHB

Gain

Phase

30202296

LMH6882

Application Information

30202234

FIGURE 1. LMH6882 Typical Application

INTRODUCTION

The LMH6882 is a fully differential amplifier optimized for signal path applications up to 1000 MHz. The LMH6882 has a 100Ω input

and a low impedance output. The gain is digitally controlled over a 20dB range from 26dB to 6dB. The LMH6882 is designed to

replace fixed gain differential amplifiers with a single, flexible gain device. It has been designed to provide good noise figure and

OIP3 over the entire gain range. This design feature is highlighted by the Dynamic Range Figure (DRF). The DRF is defined as

the input thrid order intercept point (IIP3) minus the noise figure (NF). Traditional variable gain amplifiers generally have the best

OIP3 and NF performance at maximum gain only.

30202232

FIGURE 2. LMH6882 Block Diagram

LMH6882

BASIC CONNECTIONS

A voltage between 4.75 V and 5.25 V should be applied to pins 3, 4, 24, 25. Each supply pin should be decoupled with a low

inductance, surface-mount ceramic capacitor of 0.01uF as close to the device as possible. When vias are used to connect the

bypass capacitors to a ground plane the vias should be used in pairs to help minimize parasitic inductance. Using pairs of bypass

capacitors will also help reduce parasitic inductance between the amplifier power pins and ground.

The LMH6881 has internally terminated inputs. The INMD and INPD pins are intended to be the differential input pins and are

terminated with a 100 Ohm differential resistor. The INMS and INPS pins are intended to be used for single ended inputs and have

been designed to support single ended termination of 50 Ohms (active termination). If the single ended input pins are used for a

differential signal the internal termination will appear to be a 36 Ohm differential load.

When using the LMH6881 differential input pins the unused single ended input pins should be left disconnected. Likewise when

the single ended input pins are used the differential input pins should be left disconnected. Unused input pins should not be

terminated or connected to ground.

The outputs of the LMH6882 need to be biased close to 2.5V for best performance. The actual voltage of the output pins is set by

the OCM pin. There is a gain of 2 between the OCM pin and the output pins so that the OCM voltage should be close to 1.25V.

The input pins are self biased to 2.5V. When using the LMH6882 for DC coupled applications make sure to keep the input and

output common mode voltages close to the 2.5V requirement.

When using the LMH6882 in parallel mode the gain can be set in 2dB increments. If fixed gain is desired the pins can be strapped

to ground or VCC as required. For finer gain control the LMH6882 supports SPI compliant digital control which allows the gain to

be set in 0.25dB increments between 26dB and 6dB. The gain is defined as voltage gain. If power gain is required the source and

load resistances need to be factored into the gain calculation.

The LMH6882 has a shutdown pin to enable power savings when the amplifier is not being used. For example, in a time division

duplex (TDD) system the receiver may be shutdown during transmit to save power and to protect the receive analog to digital

converter (ADC) from overload signals.

30202201

FIGURE 3. Basic Connections Schematic, Differential Input

LMH6882

30202294

FIGURE 4. Basic Connections Schematic, Single Ended

INPUT CHARACTERISTICS

The LMH6882 input impedance is set by internal resistors to a nominal 100Ω. Process variations will result in a range of values.

At higher frequencies parasitic reactances will start to impact the impedance. This characteristic will also depend on board layout

and should be verified on the customer’s system board.

At the maximum gain of 26dB the input signal will be much smaller than the output and the output may saturate or clip well before

the input reaches the maximum signal amplitude. If the input is over driven, the input signal cannot swing more than 0.5V below

the negative supply voltage (normally 0V) nor should it exceed the positive supply voltage. The input signal will clip and cause

severe distortion if it is too large. Because the input stage self biases to approximately mid rail the supply voltage will impose the

limit for input voltage swing.

At higher frequencies the LMH6882 input impedance is not purely resistive. The LMH6882 input may also be a different value than

desired. This would be the case when connecting the LMH6882 directly to a mixer. It is possible to make narrow band LC impedance

transform circuits to match the LMH6882 to other impedances. As an example Figure 5 shows a circuit that coverts 200 Ohms to

100 Ohms at 200MHz. For an easy way to calculate the L and C circuit values there are several options for online tools or down-

loadable programs. The following tool might be helpful.

http://www.circuitsage.com/matching/matcher2.html

Excel can also be used for simple circuits; however, the “Analysis ToolPak” add-in must be installed to calculate complex numbers.

30202269

FIGURE 5. Differential LC Conversion Circuit

LMH6882

OUTPUT CHARACTERISTICS

The LMH6882 has a low impedance output very similar to a traditional Op-amp output. This means that a wide range of loads can

be driven with good performance. Matching load impedance for proper termination of filters is as easy as inserting the proper value

of resistor between the filter and the amplifier. This flexibility makes system design and gain calculations very easy.

By using a differential output stage the LMH6882 can achieve very large voltage swings on a single 5V supply. This is illustrated

in Figure 6. This figure shows how a voltage swing of 5VPPD is realized while only swinging 2.5 VPP on each output. The LMH6882

can swing up to 10 VPPD which is sufficient to drive most ADCs to full scale while using a matched impedance anti alias filter between

the amplifier and the ADC. The LMH6882 has been designed for AC coupled applications and has been optimized for operation

above 5 MHz.

0.000.631.261.892.523.153.784.415.045.676.30

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

VOUT (V)

PHASE ANGLE (Radians)

2VPP

4VPPD

Out Plus

Out Minus

Differential Vout

30202266

FIGURE 6. Differential Output Voltage

Like most closed loop amplifiers the LMH6882 output stage can be sensitive to capacitive loading. Best practise is to place the

external termination resistors as close to the amplifier output pins as possible. Due to reactive components between the output and

the filter input it may be desirable to use even smaller value resistors than a simple calculation would indicate. For instance, at 200

MHz resistors of 30 Ohms provide slightly better OIP3 performance on the LMH6882EVAL evaluation board and may also provide

a better match to the filter input.

The ability of the LMH6882 to drive low impedance loads while maintaining excellent OIP3 performance creates an opportunity to

greatly increase power gain and drive low impedance filters. This gives the system designer much needed flexibility in filter design.

In many cases using a lower impedance filter will provide better component values for the filter. Another benefit of low impedance

filters is that they are less likely to be influenced by circuit board parasitic reactances such as pad capacitance or trace inductance.

The LMH6881 is a voltage amplifier. Power gain is dependent on load conditions. See Figure 7 for details on power gain with

respect to different load conditions. The graph was prepared for the 26dB gain setting. Other gain settings will behave with the

same.

0 100 200 300 400

POWER GAIN AT LOAD (dB)

LOAD IMPEDANCE (Ω)

30202279

FIGURE 7. Power Gain vs Filter Impedance

Matching Resistor Loss = 6dB

LMH6882

Printed circuit board (PCB) design is critical to high frequency performance. In order to ensure output stability the load matching

resistors should be placed as close to the amplifier output pins as possible. This allows the matching resistors to mask the board

parasitics from the amplifier output circuit. An example of this is shown in Figure 8. Also note that there the low pass filter uses

center tapped capacitors. Having capacitors to ground provides a path for high frequency, common mode energy to dissipate. This

is equally valuable for the ADC, so there are also capacitors to ground on the ADC side of the filter. The LMH6881EVAL evaluation

board is available to serve a guide for system board layout. See also application note AN-2235 for more details.

30202268

FIGURE 8. Single Ended Input, DC coupled

Common Mode Voltage Divider on Output

30202283

FIGURE 9. Differential Input, DC coupled

Common Mode Voltage Divider on Output

30202240

FIGURE 10. Single Ended Input, Differential Output Cable Driver

LMH6882

DIGITAL CONTROL

The LMH6882 will support two modes of control, parallel mode and serial mode (SPI compatible). Parallel mode is fastest and

requires the most board space for logic line routing. Serial mode is compatible with existing SPI compatible systems.

The LMH6882 has gain settings covering a range of 20 dB. To avoid undesirable signal transients the LMH6882 should not be

powered on with large inputs signals present. Careful planning of system power on sequencing is especially important to avoid

damage to ADC inputs.

While the full gain range is available in parallel mode both channels must be set to the same gain. If independent channel control

is desired SPI mode must be used.

The LMH6882 was designed to interface with 2.5V to 5V CMOS logic circuits. If operation with 5V logic is required care should be

taken to avoid signal transients exceeding the DVGA supply voltage. Long, unterminated digital signal traces are particularly sus-

ceptible to these transients. Signal voltages on the logic pins that exceed the device power supply voltage may trigger ESD

protection circuits and cause unreliable operation.

Some pins on the LMH6882 have different functions depending on the digital control mode. These functions will be described in

the sections to follow.

Pins with Dual Functions

Pin SPI = 0 SPI = 1

7 D1 SDI

14 D0 SDO*

8 D2 CLK

9 D3 CS (active low)

Pin 4 requires external bias. See Serial Mode Section for Details.

PARALLEL INTERFACE

Parallel mode offers the fastest gain update capability with the drawback of requiring the most board space dedicated to control

lines. To place the LMH6882 into parallel mode the SPI pin (pin 5) is set to the logical zero state. Alternately the SPI pin can be

connected directly to ground.

The attenuator control pins are internally biased, but not all pins are biased to the same voltage, for best results all digital pins

should be actively driven to the desired state. The SPI pin has a weak internal resistor to ground. The SD pin will bias to a low logic

state which puts both amplifiers in the ON or active state.

The LMH6882 has a 7-bit gain control bus. Data from the gain control pins is immediately sent to the gain circuit (i.e. gain is changed

immediately). To minimize gain change glitches all gain pins should change at the same time. Gain glitches could result from timing

skew between the gain set bits. This is especially the case when a small gain change requires a change in state of three or more

gain control pins. If necessary the DVGA could be put into a disabled state while the gain pins are reconfigured and then brought

active when they have settled.

PIN Name Gain Step Size (dB)

14 D0 0.25

7 D1 0.5

8 D2 1

9 D3 2

21 D4 4

20 D5 8

19 D6 16

Gain combinations that exceed 80 will result in minimum gain of 6dB.

The SD pin is provided to reduce power consumption by disabling the highest power portions of the LMH6882. The gain register

will preserve the last active gain setting during the disabled state. For individual channel control see the SPI control section.

LMH6882

30202217

FIGURE 11. Parallel Mode Connection

SPI COMPATIBLE SERIAL INTERFACE

The serial interface allows a great deal of flexibility in gain programming and reduced board complexity. The LMH6882 serial

interface is a generic 4-wire synchronous interface that is compatible with SPI type interfaces that are used on many microcontrollers

and DSP controllers.Using only 4 wires for both channels allows for significant board space savings. The trade off for this reduced

board complexity is slower response time in gain state changes. For systems where gain is changed only infrequently or where

only slow gain changes are required serial mode is the best choice. To place the LMH6882 into serial mode the SPI pin (Pin 5)

should be put into the logic high state. Alternatively the SPI pin an be connected directly to the 5V supply bus.

The serial mode is active when the SPI pin is set to a logic 1 state. In this configuration the pins function as shown in the pin

description table. The SPI interface uses the following signals: clock input (CLK), serial data in (SDI), serial data out, and serial

chip select (CS). The chip select pin is active low.

The SD pin is inactive in the serial mode. This pin can be left disconnected for serial mode.

The CLK pin is the serial clock pin. It is used to register the input data that is presented on the SDI pin on the rising edge; and to

source the output data on the SDO pin on the falling edge. The user may disable clock and hold it in the low state, as long as the

clock pulse-width minimum specification is not violated when the clock is enabled or disabled.

The CS pin is the chip select pin. This pin is active low, the chip is selected in the logic low state. Each assertion starts a new

register access - i.e., the SDATA field protocol is required. The user is required to de-assert this signal after the 16th clock. If the

CSb pin is de-asserted before the 16th clock, no address or data write will occur. The rising edge captures the address just shifted-

in and, in the case of a write operation, writes the addressed register. There is a minimum pulse-width requirement for the de-

asserted pulse - which is specified in the Electrical Specifications section.

The SDI pin is the input pin for the serial data. It must observe setup / hold requirements with respect to the SCLK. Each cycle is

16-bits long

The SDO pin is the data output pin. This output is normally at a high impedance state, and is driven only when CSb is asserted.

Upon CSb assertion, contents of the register addressed during the first byte are shifted out with the second 8 SCLK falling edges.

Upon power-up, the default register address is 00h. The SDO pin requires external bias for clock speeds over 1MHz. See Figure

13 for details on sizing the external bias resistor. Because the SDO pin is a high impedance pin, the board capacitance present at

the pin will restrict data out speed that can be achieved. For a RC limited circuit the frequency is ~ 1/ (2*Pi*RC). As shown in the

figure resistor values of 300 to 2000 Ohms are recommended.

Each serial interface access cycle is exactly 16 bits long as shown in Figure 12. Each signal's function is described below. the read

timing is shown in Figure 14, while the write timing is shown in Figure 15.

LMH6882

30202212

FIGURE 12. Serial Interface Protocol (SPI compatible)

30202214

FIGURE 13. Internal Operation of the SDO pin

R/Wb Read / Write bit. A value of 1 indicates a read operation, while a value of 0 indicates a write operation.

Reserved Not used. Must be set to 0.

ADDR: Address of register to be read or written.

DATA In a write operation the value of this field will be written to the addressed register when the chip select pin is deasserted.

In a read operation this field is ignored.

LMH6882

30202211

FIGURE 14. Read Timing

Read Timing

Data Output on SDO Pin

Parameter Description

tCSH Chip select hold time

tCSS Chip select setup time

tOZD Initial output data delay

tODZ High impedance delay

tOD Output data delay

30202210

FIGURE 15. Write Timing

Data Written to SDI Pin

LMH6882

Write Timing

Data Input on SDI Pin

Parameter Description

tPL Minimum clock low time (clock duty dycle)

tPH Minimum clock high time (clock duty cycle)

tSU Input data setup time

tHInput data hold time

Address R/W Name Default Value Hex (Dec)

0 R Revision ID 1 (1)

1 R Product ID 21 (33)

2 R/W Power Control 0 (0)

3 R/W Attenuation A 50 (80)

4 R/W Attenuation B 50 (80)

5 R/W Channel Control 3 (3)

Serial Word Format for Register 2: Power Control

7 6 5 4 3 2 1 0

RES RES CHA1 CHB1 CHA2 CHB2 RES RES

CHA1 and CHA2 = 0 for ON, CHA1 and CHA2 = 1 for OFF

CHB1 and CHB2 = 0 for ON, CHB1 and CHB2 = 1 for OFF

Serial Word Format for Registers 3, 4: Gain Control

7 6 5 4 3 2 1 0

RES Gain = 26 — (register value * 0.25) valid range is 0 to 80

Serial Word Format for Register 5: Channel Control

7 6 5 4 3 2 1 1

RES SYNC Load A Load B

The Channel Control register controls how registers 3 and 4 work. When the SYNC bit is set to 1 both channel A and channel B

are set to the gain indicated in register 3. When the SYNC bit is set to zero register 3 controls channel A and register 4 controls

channel B. When the Load A bit is zero data written to register 3 does not transfer to channel A. When the Load A bit is set to 1

the gain of channel A is set equal to the value indicated in register 3. The Load B bit works the same for channel B and register 4.

USB2ANY SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE

The LMH6882EVAL evaluation board comes with the USB2ANY USB to SPI control board and supporting software. The USB2ANY

board will connect to the LMH6882 evaluation board with the included adapter and provides a simple way to test and evaluate the

SPI interface. For more details refer to the LMH6882EVAL user's guide. The evaluation board user's guide provides instructions

on connecting the USB2ANY board to the evaluation board.

SPISU2 SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE

NOTE: The SPISU2 board is obsolete, the following paragraph is for legacy systems only.

Also available separately from the LMH6882EVAL evaluation board is a USB to SPI control board and supporting software. The

SPISU2 board will connect directly to the LMH6882 evaluation board and provides a simple way to test and evaluate the SPI

interface. For more details refer to the LMH6882EVAL user's guide. The evaluation board user's guide provides instructions on

connecting the SPISU2 board and for configuring the TinyI2CSPI software.

THERMAL MANAGEMENT

The LMH6882 is packaged in a thermally enhanced package. The exposed pad is connected to the GND pins. It is recommended,

but not necessary, that the exposed pad be connected to the supply ground plane. In any case, the thermal dissipation of the device

is largely dependent on the attachment of this pad to the system printed circuit board (PCB). The exposed pad should be attached

to as much copper on the PCB as possible, preferably external copper. However, it is also very important to maintain good high

speed layout practices when designing a system board. Please refer to the LMH6882 evaluation board for suggested layout tech-

niques.

The LMH6882EVAL evaluation board was designed for both signal integrity and thermal dissipation. The LMH6882EVAL has eight

layers of copper. The inner copper layers are one ounce copper and are as solid as design constraints allow. The exterior copper

layers are one ounce copper in order to allow fine geometry etching. The benefit of this board design is significant.

LMH6882

Applying a heat sink to the package will also help to remove heat from the device. The ATS-54150K-C2–R0 heat sink, manufactured

by Advanced Thermal Solutions, provided good results in lab testing. Using both a heat sink and a good board thermal design will

provide the best cooling results. If a heat sink will not fit in the system design, the external case can be used as a heat sink.

INTERFACING TO AN ADC

The LMH6882 was designed to be used with high speed ADCs such as the THS5400. As shown in the Typical Application on page

1, DC coupling provides the best flexibility especially for first Nyquist applications.

The inputs of the LMH6882 will self bias to the optimum voltage for normal operation. The internal bias voltage for the inputs is

approximately mid rail which is 2.5V with the typical 5V power supply condition. If DC coupling is not required it is usually easier

to AC couple the amplifier to other stages.

ADC Noise Filter

Below are schematics and a table of values for second order Butterworth response filters for some common IF frequencies. These

filters, shown in Figure 16, offer a good compromise between bandwidth, noise rejection and cost. This filter topology is the same

as is used on the ADC14V155KDRB High IF Receiver reference design board. This filter topology works best with the 12, 14 and

16 bit analog to digital converters shown in the table.

Filter Component Values

Center Frequency 75 MHz 150 MHz 180 MHz 250 MHz

Bandwidth 40 MHz 60 MHz 75 MHz 100 MHz

R1, R2 90Ω 90Ω 90Ω 90Ω

L1, L2 390 nH 370 nH 300 nH 225 nH

C1, C2 10 pF 3 pF 2.7 pF 1.9 pF

C3 22 pF 19 pF 15 pF 11 pF

L5 220 nH 62 nH 54 nH 36 nH

R3, R4 100Ω 100Ω 100Ω 100Ω

Resistor values are approximate, but have been reduced due to the internal 10 Ohms of output resistance per pin.

30202213

FIGURE 16. Sample Filter

POWER SUPPLIES

The LMH6882 was designed primarily to be operated on 5V power supplies. The voltage range for V+ is 4.75V to 5.25V. Power

supply accuracy of 2.5% or better is advised. When operated on a board with high speed digital signals it is important to provide

isolation between digital signal noise and the LMH6882 inputs. The SP16160CH1RB reference board provides an example of good

board layout.

LMH6882

COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS

Product Number Max Sampling Rate (MSPS) Resolution Channels

ADC12L063 62 12 SINGLE

ADC12DL065 65 12 DUAL

ADC12L066 66 12 SINGLE

ADC12DL066 66 12 DUAL

CLC5957 70 12 SINGLE

ADC12L080 80 12 SINGLE

ADC12DL080 80 12 DUAL

ADC12C080 80 12 SINGLE

ADC12C105 105 12 SINGLE

ADC12C170 170 12 SINGLE

ADC12V170 170 12 SINGLE

ADC14C080 80 14 SINGLE

ADC14C105 105 14 SINGLE

ADC14DS105 105 14 DUAL

ADC14155 155 14 SINGLE

ADC14V155 155 14 SINGLE

ADC16V130 130 16 SINGLE

ADC16DV160 160 16 DUAL

ADC08D500 500 8 DUAL

ADC08500 500 8 SINGLE

ADC08D1000 1000 8 DUAL

ADC081000 1000 8 SINGLE

ADC08D1500 1500 8 DUAL

ADC081500 1500 8 SINGLE

ADC08(B)3000 3000 8 SINGLE

ADC08L060 60 8 SINGLE

ADC08060 60 8 SINGLE

ADC10DL065 65 10 DUAL

ADC10065 65 10 SINGLE

ADC10080 80 10 SINGLE

ADC08100 100 8 SINGLE

ADCS9888 170 8 SINGLE

ADC08(B)200 200 8 SINGLE

ADC11C125 125 11 SINGLE

ADC11C170 170 11 SINGLE

LMH6882

Application Board

30202295

FIGURE 17.

LMH6882

Physical Dimensions inches (millimeters) unless otherwise noted

36-Pin Package

NS Package Number SQA36A

LMH6882

Notes

Incorporated

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265