CY7C63201 - Cypress Semiconductor

PRELIMINARY

fax id: 3401

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

Cypress Semiconductor Corporation • 3901 North First Street • San Jo se • CA 95134 • 408-943-2600

October 1996 - Revised June 26, 1997

1CY7C63000

CY7C63000

CY7C63001

CY7C63100

CY7C63101

CY7C63200

CY7C63201

Universal Serial Bus Microcontroller

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

TABLE OF CONTENTS

1.0 FEATURES .....................................................................................................................................4

2.0 FUNCTIONAL OVERVIEW .............................................................................................................4

3.0 PIN DEFINITIONS ...........................................................................................................................6

4.0 PIN DESCRIPTION .........................................................................................................................7

5.0 FUNCTIONAL DESCRIPTION ........................................................................................................7

5.1 Memory Orga nization ....................................................................................................................7

5.1.1 P ro gr am Memo ry Org anizatio n ............ ......... .......... ........... ........ ............. ...... .............. ....... .................7

5.1.2 Secur ity Fu se Bit . ... ......... ....... ....... ......... ....... ...... ....... ....... ....... ..... ....... ....... ....... ....... .............................7

5.1.3 Data Me mory Or gan izati on . ..... ....... ....... ....... ..... ....... ....... ......... ....... ....... ........ ....... ....... ........................9

5.2 I/O Register Summa ry ...................................................................................................................9

5.3 Reset . ............................................................................................................................................10

5.3.1 P ower-O n Reset (PO R) ....... ...................................... ....... ...................................... ....... ......................10

5.3.2 Watch Do g Reset (WDR) ... . ...................................... ....... ...................................... ....... ......................11

5. 3. 3 U SB B u s Re se t .. .. ........ ............ .............. ............ .............. ............ ........... ........ ....................................11

5.4 On-chip Timer ..............................................................................................................................11

5.5 General Purpose I/O Ports ..........................................................................................................12

5.6 Instant-on Feature (Suspend Mode) ..........................................................................................14

5.7 XTALIN/XTALOUT ........................................................................................................................14

5.8 Interrupts ......................................................................................................................................15

5.8.1 I n terrup t Latency . . .............. ..... .............. ....... ............ ......... .......... ........... ........ ....................................16

5.8.2 G P IO Interrup t . ............. ............ ..................... ............ ................... ................... ....................................16

5.8.3 USB Interru pt ... ....... ......... ....... ....... ........ ....... ..... ....... ....... ....... ..... ....... ......... ....... ................................17

5.8.4 Tim er Inte rrup t ..... ..... ... ...... ... ... ....... .... ... ....... .... ... ..... .... ..... ..... .... ... ..... ...... ... ... ....... .............................17

5.8.5 Wake-up Inte rrupt ........ ............ ......... ............ ......... .......... ........... ........ ............ ....... .............................17

5.9 USB Engine ..................................................................................................................................17

5.9.1 USB Enu merati on Process ..... ....... ....... ....... ..... ....... ....... ....... ....... ....... ....... ......... ....... ....... ................18

5.9.2 End Point 0 ..........................................................................................................................................18

5.9.2.1 End Point 0 Receive .................................................................................................................................... 18

5.9.2.2 End Point 0 Transmit ............................................. ...................................................................................... 18

5.9.3 End Point 1 ..........................................................................................................................................20

5.9.3.1 End Point 1 Transmit ............................................. ...................................................................................... 20

5.9.4 USB Status and Contro l .. ... ..... ....... ....... ....... ......... ....... ....... ........ ....... ....... ..... ....... ....... ......................20

5.10 Inst ruc tio n Set Sum ma ry .. ........................................................................................................21

6.0 ABSOLUTE MAXIMUM RATINGS ...............................................................................................22

7.0 DC CHARACTERISTICS ..............................................................................................................22

8.0 SWITCHING CHARACTERISTICS ...............................................................................................23

9.0 ORDERING INFORMATION .........................................................................................................24

10.0 PACKAGE DIA GRAMS ..............................................................................................................25

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

TABLE OF FIGURES

Figure 5-1. Program Memory Space ...... ............................................................................................. 8

Figure 5-2. Data Memory Spa ce .......................................................................................................... 9

Figure 5-3. Status and Control Register (Address 0xFF)................................................................ 10

Figure 5-4. Watch Dog Reset (WDR)................................................................................................. 11

Figure 5-5. Timer Register (Address 0x23)....................................................................................... 11

Figure 5-6. Timer Bl ock Di agram....................................................................................................... 12

Figure 5-7. Port 0 Data Register (Address 0x 00) . ............................................................................ 12

Figure 5-8. Port 1 Data Register (Address 0x 01) . ............................................................................ 12

Figure 5-9. Block Diagram of an I/O Line.......................................................................................... 13

Figure 5-10. Port 0 Pull-Up Register (Address 0x08)....................................................................... 13

Figure 5-11. Port 1 Pull-Up Register (Address 0x09)....................................................................... 13

Fi gure 5-12. Port I sink Re gis ter for One GPI O Line........ ....... ....... ........ ........... ....... ....... ........ .......... 14

Figure 5-13. The Cex t Register (Addr ess 0x22) ............................................................................... 14

Figure 5-14. Clock Oscillator On-chi p Circuit .. ................................................................................ 1 4

Figure 5-15. Global I nterrupt Enable Register (Address 0x20).... ................................................... 1 5

Fi gure 5-16. I nterrupt Contr oller Logic Block Dia gram...... ............................................................. 15

Figure 5-17. Port 0 Interrupt Enable Register (Address 0x04)........................................................ 16

Figure 5-18. Port 1 Interrupt Enable Register (Address 0x05)........................................................ 16

Figure 5-19. GPI O Interrupt L ogic Block Diagram... ........................................................................ 17

Figure 5-20. USB Device Address Register (Address 0x12)........................................................... 18

Figure 5-21. USB End Point 0 RX Register (Address 0x14)............................................................ 18

Figure 5-22. USB Engine Response to SETUP and OUT transaction s on End P o int 0................ 19

Figure 5-23. USB End Point 0 TX C onfiguration Register (Address 0x10).................................... 19

Figure 5-24. USB End Point 1 TX C onfiguration Register (Address 0x11).................................... 20

Figure 5-25. USB Sta t us and Control Re gister (Address 0x13)... ................................................... 2 0

Figure 8-1. Clock Timing.................................................................................................................... 24

Figure 8-2. USB Data Signal Timing.................................................................................................. 24

TABLE OF TABLES

Table 5-1. I/O Register Summary.........................................................................................................9

Table 5-2. Output Control Truth Table..............................................................................................1 3

Ta ble 5-3. Interrupt Ve ctor Assi gnment s.. .... ....... ........... ....... ....... ........ ........... ....... ....... ........ ........ ...16

Table 5-4. Instruction Set Map...........................................................................................................21

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

1.0 Features

• Low-cost solution for low- s peed USB peri pherals such as mouse, joystick, and gamepad

• USB Specification Compliance

—Conform s to USB 1.5 Mbps Specification, Version 1.0

—Conforms to USB HID Specification, Version 1.0

—Su pports 1 device addr ess and 2 endpoints

• 8-bit RISC microcontroller

—Harvard archit ecture

—6 MHz external ceramic resonator or clock crystal

—1 2 MHz internal o perati o n

—USB optimized instruction set

• Internal memory

— 1 28 b y tes o f R A M

—2K bytes of EPROM (CY7C63000, CY7C63100, CY7C63200)

—4K bytes of EPROM (CY7C63001, CY7C63101, CY7C63201)

• I/O ports

—Integrated USB transceivers

—Up to 16 Schmitt tr igger I/O pins w ith internal pull-up

—Up to 8 I/O pi n s with LED drive capability

—Special purpose I/O mode supports optimization of photo transistor and LED in mouse application

—Maskable Interrupts on all I/O pin s

• 8-bit free-running timer

• Watc hdog tim er ( WDT)

• Internal power-on reset (POR)

• Impro v ed output drivers to reduce EMI

• Operating voltage from 4.0V to 5.25VDC

• Operating temperature from 0 to 70 degree Celsius

• Avail able in space saving and l ow cost 18- pin PDIP, 20-pin PDIP, 20-pin SOIC, and 24-pi n SOIC packages

• Windowed packages also avail a ble t o suppor t program development: 18, 20, and 24-pin Windowed CerDIP

• Industry standard programmer support

2.0 Functional Overview

The CY7C63xxx is a family of 8-bit RISC One Time Programmable (O TP) micr ocontr ol lers with a built-i n 1. 5-Mbps USB seri al

interface engine. The microcontroller features 35 i nstructions which are o pt imized for USB appli cations. There is 128 bytes of

onboard RAM ava ilable incorporated into e ach microcontroller . The Cypress USB Controller accepts a 6 MHz ceramic reso nator

or a 6 MHz crystal as its cl o ck source. Th i s clock is doubled within the chip to provide a 12 MH z clo ck for the microprocessor.

The microcontroll er featur es two ports of up to si xteen general purpose I/Os (GPIOs). Each GPI O pin ca n be used to generate

an interrupt to the microcontroller. Additionally, all pins in Port 1 are equipped with programmable drivers strong enough to drive

LEDs. The GPIO ports f eature low EMI emissions as a result of controlled rise and fall times, and unique output driver circuits in

the micro controller. Th e Cypress microcontroll es have a range of GPIOs to fit various applications; the CY7C630xx has twelve

GPIO, the CY7C631xx has sixteen GPIO, and the CY7C632xx has ten GPIO. Notice that each part has eight ‘low-current’ ports

(Port 0)with the remaining ports (Port 1) being ‘high-curren t’

The twelve G PIO CY7C6300x is available in is a 20-pin PDIP (- PC), 20-pin SOIC ( -SC), and a 20- pin Windowed CerDIP. The

sixteen GPIO CY7C6310x is available in a 2 4-pin SOIC (-SC) and a 24-pin Windowed CerDIP (-SC). The ten GPIO CY7C63 20x

is available in an 18-pin PDIP (-PC) and an 18-pin Windowed CerDIP (-WC).

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

PinConfigurations (Top View)

Logic Block Diagram

6311–1

USB

D+,D–

PORT

P0.0–P0.7

Interrupt

Controller 0 PORT

P1.0–P1.7

8-bit

RISC

OSC RAM

128 Byte

EPROM

2 K/4K Byte

913

P0.0

P0.1

P0.2

P0.3

P1.0

P1.2

VSS

CEXT

P0.4

P1.1

P0.6

P0.7

D+

P1.3

D-

VCC

DIP/SOIC/

P0.5

VPP

XTALIN XTALOUT

10 11

core

Power

8-bit

Timer

on Reset Engine

Watch

Timer

911

P0.0

P0.1

P0.2

P0.3

P1.0

VSS

VPP

XTALIN

P0.4

P1.1

P0.6

P0.7

D-

D+

VCC

XTALOUT

DIP/

P0.5

CEXT

Dog

6 MHz

RESONATOR

11 15

P0.0

P0.1

P0.2

P0.3

P1.0

P1.2

VSS

CEXT

P0.6

P1.5

P1.1

P1.3

D+

P1.7

D–

VCC

24-pin

P0.7

VPP

XTALIN XTALOUT

12 13

P1.4

P1.6

23 P0.4

P0.5

AAAA

AAA

AAAA

AAA

INSTANT-ON

NOW<TM>

R/CEXT

VCC/VSS

SOIC/

20-pin18-pin

Windowed CerDIP Wind owed CerDIP Windowed CerDIP

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

3.0 Pin Definitions

Name I/O 18-Pin 20-Pin 24-pin Description

P0.0 I/O 1 1 1 Port 0 bit 0

P0.1 I/O 2 2 2 Port 0 bit 1

P0.2 I/O 3 3 3 Port 0 bit 2

P0.3 I/O 4 4 4 Port 0 bit 3

P0.4 I/O 18 20 24 Port 0 bit 4

P0.5 I/O 17 19 23 Port 0 bit 5

P0.6 I/O 16 18 22 Port 0 bit 6

P0.7 I/O 15 17 21 Port 0 bit 7

P1.0 I/O 5 5 5 Port 1 bit 0

P1.1 I/O 14 16 20 Port 1 bit 1

P1.2 I/O – 6 6 Port 1 bit 2

P1.3 I/O – 15 19 Port 1 bit 3

P1.4 I/O – – 7 Port 1 bit 4

P1.5 I/O – – 18 Port 1 bit 5

P1.6 I/O – – 8 Port 1 bit 6

P1.7 I/O – – 17 Port 1 bit 7

XTALIN I 9 10 12 Crystal / Ceramic resonator in or external clock input

XTALOUT O 10 11 13 Crystal / Ceramic resonator out

CEXT I/O 8911 Connects to external R/C timing circ uit for optional suspend

wakeup

D+ I/O 13 14 16 USB data+

D– I/O 12 13 15 USB data–

VPP –7810 Programming voltage supply, tie to ground during normal

operation

VCC –11 12 14 Voltage supply

VSS – 6 7 9 Ground

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.0 Functional Description

The Cyp ress CY7C63 000/1, CY7C6310 0/1, a nd CY7C6 3200/1 USB m icrocontrollers are optimize d for human-interface comput-

er peripherals such as a mouse, joystick, and gamepad. Cypress USB microcontrollers conform to the low-speed (1.5 Mbps)

requirements of the USB Specification version 1.0. Each micorc ontroller is a self-c ontained unit with a USB interface engine, USB

tra nsceivers, an 8-bit RISC microcontroller , a clock oscillator , timers , and program memories. It supports one USB device a ddre ss

and two end points.

The 6 MHz clock generated by the on-chip oscillator is stepped up t o 12 MHz to drive the microcontrol ler. A RI SC archit e cture

with 35 instructio ns is chosen t o provide the best balance between performance and pro duct cost .

5.1 Mem ory Or gan izati on

The memory in the USB Controller is organized into user program memory in EPROM space and data memory in SRAM space.

5.1.1 Program Memory Organization

The 14-bit Program Counter (PC) is capable of addressing 16K bytes of program space. However, the program space of the

CY7C63000, CY7C63100 and CY7C63200 is 2K bytes. For applications requiring more program space, the CY7C63001,

CY7C6 3101 and CY7C6320 1 each offer 4K bytes of EPROM. The program memory space is divided into two functional groups:

Interrupt Vectors and pr o gram code.

The interrupt vectors occupy the first 16 bytes of the program space. Each vector is 2 bytes long. After a reset, the Program

Counter points to l ocati o n zer o of the program space.

Figure 5-1

shows the organizat ion of the Program memory Space.

5.1.2 Security Fuse Bit

The Cypress USB microcontroller includes a security fuse bit. When the security fuse is programmed, the EPROM program

memory outputs 0xFF to the EPROM programmer, th us protecting the user’s code.

4. 0 Pin Des cripti o n

Name Description

VDD 1 pin. Co nnects to the USB power source or to a no minal 5V power supply. Actual VCC range ca n vary

between 4.0V and 5.25V

VSS 1 pin. Connects to ground

VPP 1 pin. Used in programming th e on-chip EPROM. This pin should be tied to ground during normal

operations.

XTALIN 1 pin. Input from an external ceramic resonator, crystal, or cloc k

XTALOUT 1 pin. Return path f or the cer amic resonator or cr ystal

P0.0–P0.7,

P1.0–P1.7 16 pins. P0. 0–P0.7 are t h e 8 I /O lines in Port 0. P1.0–P1.7 are the 8 I/ O li n es i n Port 1. Please note

that P1.0–P1.1 are s upported in the CY7C6320x and P1.0–P1.3 are s upported in the CY7C6300x . Al l

I/O pi ns are pulled up internally by 16KΩ resistors. However, the sink curr ent of each pin can be

programmed to one of sixteen levels. Besides functioni ng as general purpose I/O li nes, each pin can

be programme d as an interrupt input. The interrupt is edge-trigger ed, with programma ble polarity.

D+, D– 2 pins. Open-drain I/O wit h 2 pins. Bidir ecti onal USB data lines. An e xternal 7.5 KΩ resistor must be

connected between the D– pin and VCC to select low-speed USB operati on.

CEXT 1 pin. Open-drain output with Schmitt trigger input. The input is connected to a level-sensitive (HIGH)

interrupt. CEX T may be c onnec ted to an external RC to generate a wake -up from Su spend mode. See

Section 5.6.

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

after reset Address

PC 0x0000 Reset Vector

0x0002 Inter rupt Vector - 128 µs

0x0004 Inter rupt Vector - 1.024 ms

0x0006 Inter rupt Vector - USB Endpoi nt 0

0x0008 Inter rupt Vector - USB Endpoi nt 1

0x000A Reserved

0x000C Inter rupt Vector - GPIO

0x000E Inter rupt Vector - Cext

0x0010 On-chip program Memory

0x07FF 2K ROM (CY7C63000, CY7C63100,CY7C63200)

0x0FFF 4K ROM (CY7C63001, CY7C63101, CY7C63201)

Figure 5-1. Program Mem ory Space

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.1.3 Data Memory Organization

The USB Control ler i n cludes 128 byt e s of data RAM. The upper 16 bytes of the data memor y are used as USB FIFOs for End

Point 0 and E nd Poi nt 1. Each e nd poi nt i s associated wit h an 8-byte FIFO.

The USB contr oller includes two pointers into data RAM, t he Pr ogram Stack Pointer (PSP) an d the Data Stack Pointer (DSP).

The va lue of PSP after rese t is 0x0 0. The PSP i s incremented by 2 whenev er a CALL in struc tion is exec ute d and i t is decremented

by 2 whenever a RET instruction is used.

The DSP is pre-decremented by 1 w henever a PUSH instruction is executed and it i s incremented by 1 af ter a POP instruction

is used. The default value of the DSP af ter reset is 0x00 , which would cause the first PUSH to write into USB FIFO space for End

Point 1. Therefor e, the DSP should be mapped to a locatio n such as 0x70 before init iating any dat a stack operations. R efer to

the Reset section for more informat ion about DSP re-mapping after reset.

Figure 5-2

illustrates the Data Memory Space.

5.2 I/O Reg ister S umm ar y

I /O registers are a ccessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) i nstructions.

after reset

Address

DSP PSP 0x00

0x02

0x04

0x6E

DSP 0x70 USB FIFO - Endpoint 0

0x77

0x78 USB FIFO - Endpoint 1

0x7F

Figure 5-2. Data Memory Space

Table 5-1. I/O Register Summary

Port 0 Data 0x00 R/W General purpose I/O Port (low curre nt)

Port 1 Data 0x01 R/W General purpose I/O Port ( high current)

Port 0 I nterr upt Enabl e 0x04 W Interrupt enable for pins in Port 0

Port 1 I nterr upt Enabl e 0x05 W Interrupt enable for pins in Port 1

Port 0 Pull-up 0x08 W Pul l-up resistor contr ol for Port 0 pins

Port 1 Pull-up 0x09 W Pul l-up resistor contr ol for Port 1 pins

USB EP 0 TX Config. 0x10 R/W USB End Point 0 transmit configuration

USB EP 1 TX Config. 0x11 R/W USB End Point 1 transmit configuration

USB Device Address 0x12 R/W USB device address

USB Status & Control 0x 13 R/W USB status and control

USB EP 0 RX Status 0x14 R/W USB End Point 0 receive status

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.3 Reset

The USB Controller supports thre e types o f resets. All registers are restored to their default states during a res et. The USB De vice

Address is set to 0 and all interrupts are disabled. In addition, the Program Stack Pointer (PSP) is set to 0x00 and the Data Stack

Pointer (DSP) is set to 0x00. The user should set the DSP t o locatio n 0x70 to reserv e 16 bytes of FIFO space. The assembly

instructions to do so are:

Mov A, 70h ; Move 70 hex i nto Accum ulator, use 70 instead of 6F because th e dsp is

; always decremented by 1 before data transfer in the PUSH instruction

Swap A, dsp ; Move Accumulator value into dsp

The three reset types are:

1. Power On Reset (POR)

2. Watch Dog Reset (WDR)

3. USB Reset

The occurrence of a reset is record ed in the Status and Control Register located at I/O address 0xFF (

Figure 5-3

). Reading and

writing this register a re supported by the IORD and IOWR instruc tions . Bits 1, 2, and 7 are reserved an d must be written as zeros

during a write. During a read , rese rved bit positions should be ignored. Bits 4, 5, and 6 are used t o record the occurrence of POR,

USB and WDR Reset respect ively. The firmware can i nterr ogate these bits to determine the cause of a reset. Bit 0 is th e “R un”

control, clearing t his bit will stop the micro controller. Once this bit is set to low, on l y a reset can set this bi t HI GH.

The micro cont roller resumes execution f rom ROM a ddr ess 0X00 after a reset unless the Suspend bit (bit 3) of the St atu s an d

Control Register is set. Sett ing the Suspend bit stops the clock oscillator and t he interr u pt timer s as well as powering-down the

microcontroller. The detectio n of any USB activity will ter m in ate th e suspend condition.

5.3.1 Power-On Reset (POR)

Power On Reset (POR) occurs e very time the power to the device is switched on. Bit 4 of the Status and Control Register is set

to rec ord this event (the registe r contents are set to 00011001 by the POR). The USB Controller is placed in s uspen ded mode at

the end of POR to conserve power (mos t d evice functions suc h as the clock oscillator , the timers, an d the interrupt logic are turned

off in the suspend mode). Only a non-idle USB Bus state will termi nate the suspend mode and begin normal operati ons.

Global Interrupt Enable 0x20 R/W Global Interrupt Enable

Watch Dog Timer 0x21 W Watch Dog Timer clear

Cext Clear 0x22 R/W External R-C Timing circuit control

Timer 0x23 R Free-running timer

Port 0 I sink 0x30-0x37 W Inpu t sink current co ntrol for Port 0 pins. The re is one

Isink register for each pin. Address of the Isink register

for pin 0 is located at 0x30 and the r egister address

for pin 7 is located at 0x37

Port 1 I sink 0x38-0x3B W Inpu t sink current co ntrol for Port 1 p ins. There is one

Isink register for each pin. Address of the Isink register

for pin 0 is located at 0x38 and the r egister address

for pin 3 is located at 0x3B

Status & Control 0xFF R/W Processor status and control

76543210

WR/W R/W R/W R/W W W R/W

Reserved Watch Dog

Reset USB Reset Power-on

Reset Suspend Reserved Reserved Run

Figure 5-3. Status and Cont rol Register (Addres s 0 xFF)

Table 5-1. I/O Register Summary (continued)

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.3.2 Watch Dog Reset (WDR)

The Watch Dog Timer Reset (WDR) occurs when the Most Significant Bit of the 4-bit Watch Dog Timer Register transitions from

LOW to HIGH. Writing any value to t he write-only Watch Dog Restart Register at 0x21 will clear the timer. The Wa tch D og timer

is clocked by a 1.024 ms clock from the free runn ing timer . If 8 clock s occur between writes to the timer, a WDR occurs. Bit 6 of

the Status and Control Register will be set to record the event. A Watch Dog Timer Reset lasts for 8.192 ms after which the

microcontroller begins execution at ROM address 0x00. The USB transmitter is disabled by a Watch Dog Reset because the

USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The

transmitter remains disabled unti l the WDR bit in th e Status and Control Register is reset to 0 by firmware.

Figure 5-4. Watch Dog Reset (WDR)

5.3.3 USB Bus Reset

The USB Controller recognizes a USB Reset when a Single En ded Ze ro (SE0) condition persists for longer than 8 micro-se conds.

SE0 is defined as the condition in which both the D+ line and the D– line are LOW. Bit 5 of th e Status and Co ntrol Register will

be set to record this event. If the USB rese t ha ppens while the device is susp ended (su ch as a fter a POR), the suspe nd condition

will be cleared and the clock oscillator will be restarted. However, the microcontroller is not released until the USB reset is

removed.

5. 4 O n -chip Ti m er

The USB Contr oller i s equip ped wi th an 8-bit fr ee-running timer driven by a clock one-sixth the crystal fre quency. Bits 0 through

7 of the cou nte r are reada ble from the read-only T imer Register located at I/O address 0x23. The T ime r Register is cleared du ring

a Power-On Reset.

Figure 5-5

illustrates the format of this register and

Figure 5-6

is it s block diagram.

With a 6 MHz crystal, the t imer resolution is 1 µs.

The timer generates two interrupts: the 128 µs interrupt and the 1.024 ms interrupt.

76543210

RRRRRRRR

Count 7 Count 6 Count 5 Count 4 Count 3 Count 2 Count 1 Count 0

Figure 5-5. Timer Register (Address 0x23)

last write to

Watchdog Ti mer

No write to WD T

goes high

Execution begi ns at

Reset Vector 0X00

8.192 ms 8.192 m s

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.5 General Pu rpo se I/O Port s

Interface with per ipherals is conducted via 12 GPIO signals. These 12 signals are divided into two ports: Port 0 and Port 1. Port

0 cont ains eight lines (P0.0–P0.7) and Port 1 cont ains up to eigth lines (P1.0–P1.7), depending on the package. Both ports can

be accessed by the IORD, IOWR and IOWX in structions. The Port 0 data register is located at I/ O a ddress 0x00 while the Port

1 data register is located at I/ O address 0x01. The c ontents of both registers are set HIGH d uring a reset. Refer to

Figures 5-7

and

5-8

for the fo rmats of the data registers. In addition to supp orting general input/output functions, each I/O line can trigger an

interrupt to the microcontroller. Please refer to t he interrupt secti on for more det ails.

Each GPIO line includes an internal 16 KΩ res istor. This resistor provides both the pull-up function an d slew control. Two factors

govern the e nabling and disabling of e ach re sistor: the state of its associated Port Pull- up register bit and the state of th e Data

The output is HIGH when a “1” is written to the Data Register and the Port Pull-up re gister is “0”. Writing a “0” to the Data Register

will disable the Pull-up resistor and out p ut a LOW regar dle ss of the sett ing in the Port Pull-up Register. The output will go to a

high -Z state if the Data Register bit and the Port Pull-up Register bit are both “1”.

Figure 5-9

illustrates the block diagram of one

I/O line. The Port Isink Register is used to control the output current level and it is described later in this section.

Table 5-2

is the

Output Control truth table.

Figure 5-6. Timer Block Diagram

76543210

R/W R/W R/W R/W R/W R/W R/W R/W

P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0

Fig ure 5- 7. Port 0 Data Register (Address 0x00)

76543210

R/W R/W R/W R/W R/W R/W R/W R/W

P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0

Fig ure 5- 8. Port 1 Data Register (Address 0x01)

10 97

10 crystal clock/6

1.024 ms interrupt

128 µs interrupt

To Timer Register

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

To configure a GPIO pin as an input, a “1” should be writ ten to the Port Data Register bit associated with that pin to disable the

pull down function of the Isink DAC (see

Figure 5-9

).When the Port Data Register is read, the bit value will be a “1” if the voltage

on the pin is gr eater than the Schmitt trigger threshold and “0” if below the threshold. In applicati ons where an internal pull-up is

required, the 16K-Ω pu l l-up r e sistor can be engaged by writ ing a “ 0” to the appropr iate bit i n the Port Pull-Up Re gister.

Both Port 0 and Port 1 Pull-up registers are write only (see

Figures 5-10

and

5-11

). Port 0 Pull-up is located at I/O address 0x08

and Por t 1 Pull-up is mapped to address 0x09. The co ntents of the Port Pull-up register s are cleare d during reset, allowing the

outputs to be controlled by the state of the Data Registers. The Por t p ul l-up registers also selects the polarity of tr ansit ion t hat

generate s a GPIO interrupt. A “0” sel ects a HIGH to LOW t ransiti on while a “1” sel ects a LOW to HI GH transition.

Writi n g a “0” to t he Data Register will drive the output LOW. I n stead of providing a fix ed output drive, the USB C ontroll er allow s

the user to select an out put sink current level for each I/O pin. The sink current of each output is contr olled b y a dedicated Port

Isink Register. The lower 4 bits of this register contain a code selecting one of sixteen sink current leve ls. The upper 4 bits of the

Figure 5-12

Figure 5-9. Block Diagram of an I/O Line

Table 5-2. Out put Control Truth Table

Data Register Port Pull- up Register O utput at I /O Pin

0 0 Sink Current (‘0’)

0 1 Sink Current (‘0’)

1 0 Pull- up R esist or (‘1’)

1 1 Hi-Z

76543210

WWWWWWWW

Pull P0.7 Pull P0.6 Pull P0.5 Pull P0.4 Pull P0.3 Pull P0.2 Pull P0.1 Pull P 0.0

Figure 5-10. Port 0 Pull-Up Register (Address 0x08)

7 6 5 4 3 2 1 0

W W W W W W W W

Pull P1.7 Pull P1.6 Pull P1.5 Pull P1.4 Pull P1.3 Pull P1.2 Pull P1.1 Pull P1.0

Figure 5-11. Port 1 Pull -Up Register (Addr ess 0x09)

GPIO

VCC

Isink

DAC

Port Isink

Port Data

Port Pull-Up

16 KΩ

Schmitt

Trigger

Data Bus

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Port 0 is a low c urrent port suitable for connecting ph oto transistors. Port 1 is a high current port capab le o f LED drive. See section

7.0 for current ranges. 0000 is the lowest drive strength. 1111 is the highest.

The write-only sink current control regist ers for P ort 0 outputs are a ssigned from I/O address 0x30 to 0x37 with the control bits

for P00 starting at 0x30. Port 1 sink current control registers continue from I/O address 0x38 to 0x3B. All sink current contr ol

registers are cleared during a reset, resulting in the minimum drive setting.

5.6 Instant-o n Feature (Suspen d Mode )

The USB Co ntroller can b e placed in a low-power state by sett ing the Suspend b it (bit 3) of the Status and Co ntrol reg is ter . Almost

all logic blocks i n t he de vi ce are turned off except the USB re cei ver, the GPIO interr upt l ogic, an d the Cext int errupt logic. The

clock oscillator as well as the free-running and watch dog timers ar e shut down.

The suspend mode will be terminated when one of the three following conditions occur:

1. USB activity

2. A GPIO interrupt

3. Cext interrupt

The clock os cillator, GPIO and timers restart immediat ely on exiting suspend mode. The USB engine and microcontroller return

to a fully functional state at most 256 us l ater. The microcontroller will e xecute the instru ction foll owin g the I/O write that placed

the device into suspend mode bef ore servicing any int errupt requests.

Both the GPIO interrupt and t h e Cext interrupt allow the USB C ontroll er t o wake-u p periodically and poll potentiometers, optic s,

and other system components while maintaining a very low average power consumption.

To us e Cext to generate an “Instant-on” interrupt, the pin is co nnected to ground with an external capacitor and connected to VCC

with an external resistor. A “0” is written to the Cext register located at I/O address 0x22 to discharge the capacitor. A “1” is then

written to disable the open-drai n outpu t d river . A Schmitt tr igger input circuit monitors the input an d generates a wake-up interrupt

when the input vol tage rises above the input threshold. By changing the val ues of the ext ernal resistor and capacitor, the user

can f ine tune the ch arge rate of the R-C timing circuit. The format o f the Cex t register is shown in

Figure 5-13

. Reading the register

returns the value of the Cext pin. During a reset , the Cext is HIGH.

5.7 XTALIN/XTALOUT

XT ALIN and XT ALOUT are the crystal oscillator pins . A 6 MHz cry stal or ceramic resonator sho uld be conne cted to these pins.The

feedback capacitors and bias resistor are intern al to the IC.

Figure 5-14. Clock Oscillator On-chip Circui t

7 6 5 4 3 2 1 0

W W W W W W W W

Isink7 Isink6 Isink5 Isink4 Isink3 Isink2 Isink1 Isink0

Figure 5-12. Port Isink Register for One GPIO Line

7 6 5 4 3 2 1 0

R/W

Reserved Reserved Reserved Reserved Reserved Reserved Reserved Cext

Figure 5-13. The Cext Register (A ddress 0x22)

XTALOUT

XTALIN

fxtal

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.8 Interrupts

Interrupts ar e generated by t he General Purpose I /O lines, the Cext pin, the internal timer, and the USB engine. All interrupts

except Reset are maskab le by the Global Interrupt Ena ble Register. Access t o this register is accomplished via IORD, IOWR and

IOWX instr uctions to address 0x20. Writing a “1” to a bit position enables the interrupt associated with that position. During a

reset, the contents the Interrupt Enable Register are cleared, disabling all interrupts.

Figure 5-15

illustrates the format of the

Global Interrupt Enable Register.

The interrupt controller contains a separate latch for each interrupt exc ept the Wake-up interrup t. Whe n an in terrupt is generated

it is latched as a pending i nterrupt. It will stay as a pending interrupt until it is serviced or a reset occurs. The Wake-up interrupt

is not latched, and is pending whenever the Cext pin is high. A pending interrupt will only generate an interrupt request if it is

enabled in t h e Global Interrupt Enable Register. The hi g hest priority interrupt request will be serviced following the execution of

the current instruction.

When servicing an interrupt, t he hardwar e will first disabl e all interr upt s by cleari ng the Global Interrupt Enable Register. Next,

the interru pt latch of the current interrupt is cleared. This i s followed by a CALL in struction to the ROM address associated wi th

the interrupt being serviced (i.e., the Inter rupt Vector). T he in st ruction in the interr upt table is ty pic al ly a JMP instructi on t o the

address of the Interrupt Service Routine (ISR). The user can re-enable interrupts in the interrupt service routine by writ ing to the

appropriate bits in the Global Interrupt Enable Register. Interrupts can be nested to a level limited only by the available stack

space.

Figure 5-16. Interrupt Controller Logic Block Diagram

The Program Co unter value as well as the Carry and Zero flags (CF, ZF) are a utomatically s tored onto the Program Stack by the

CALL i nstruction as part of the interrupt acknowledge process. The user firmwar e is responsible for insuring that t h e pr o cessor

state is preserved and restored during an int errupt. For example the PUSH A instruction shoul d be used as the first command in

the ISR to s ave t he accumulator value and the POP A instruction shoul d be used just before the RET instr uctio n to restore the

accumulator value. The pr ogram counter CF and ZF are re stored when the RET instruction is execut ed.

The Interrupt Vectors supported by t he USB Controller are listed in

Table 5-3

. Interrupt Vector 0 (Reset) has the highest priority,

Interrupt Vector 7 has the l owest priority. Because the JMP instructi o n is 2 bytes l ong, the i nterr u pt vectors occupy 2 bytes.

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

Wake-up

Interrupt

Enable

GPIO

Interrupt

Enable

Reserved USB EP1

Interrupt

Enable

USB EP0

Interrupt

Enable

1.024 ms

Interrupt

Enable

128 us

Interrupt

Enable

Reserved

Figure 5-15. Global Interrupt E nable Register (Addres s 0x20)

CLR

Global

Int errup t

Interrupt

Ack no wledge

IRQ

128 µs CLR

Interrupt

Priority

Encoder

Enable [7:0]

En able [1]

l ogi c 1

128µs

Interrupt

Ena bl e

CLR CLR

En able [6]

GPIO

Interrupt

128 µs IRQ

1 ms CLR

1 m s IRQ

End P0 CLR

End P0 IRQ

End P1 IRQ

End P1 CLR

GPIO CLR

GPIO IRQ

Wake-up IRQ

Vector

Enable [7]

CEXT

CLK

logic 1

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.8.1 Interrupt Latency

Interrupt latency can be calculated from the following equation:

Interrupt Latency = (Number of clock cycles remaining in the current instruction) + (10 clock cycles for the CALL instruction) +

(5 clock cycles for the JMP instruction)

For example, if a 5 clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the

Interrupt S ervice Routine will execute a min. of 16 cl ocks (1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is issued.

The interrupt latches ar e sampled at the r ising e dge of t he last clock cycle in t he current instr uctio n.

5.8.2 GPIO Interrupt

The Gen era l Purp ose I/O interrupts are g enerated by s ignal t ransitions at the Port 0 and Port 1 I/O pins. GPIO interrupts are e dge

sensitive with pro grammable interrupt polarities. Setting a bit HIGH in the Po rt Pull-up Register (see

Figure 5-10

and

5-11

) selects

a LOW to HIGH interrupt trigger for the correspon ding port pin. Setting a b it LOW activates a HIGH to LOW interrupt trigger. Each

GPIO interrupt is m askable on a per-pin basis by a dedicated bit i n the Port Interru pt Enable Regi ster. Writi n g a “1” en ables the

interrupt.

Figure 5-17

and

Figure 5-18

illustrat e the format of the Port Interrupt Enable Registers for Port 0 and Port 1 located at

I/O address 0x04 and 0x05 respect ively. These writ e only registers are cleare d d uring re set, t h us disabli n g all GPIO inter rupts.

A block diagram of the GPIO interrupt logic is shown in

Figure 5-19

. Th e bit setting in the Port Pull-up Register selects the interrupt

polarity. If the se lec ted signal polarity is detected on th e I/O pin a HIGH signal is generated. If the Port Interrupt Enable bit for this

pin is HIGH and no other port pins are requesting interrupts, then the 12-input OR gate will issue a LOW to HIGH signal to clock

the GPIO interrupt flip flop. The output of the flip flop is further qualified by the Global GPIO Interrupt Enable bit before it is

processed by the Interrupt Prior ity Encoder. Bot h the GPIO interrupt flip flop and the Global GPIO E nable bit are clear ed during

GPIO interrupt acknowledge by on-chip har dw are.

Table 5-3. Interrupt Vector Assignments

Inter rupt Vector Number ROM Address Function

00x00 Reset

10x02 128 µs timer interrupt

20x04 1.024 ms tim er interrupt

30x06 USB e nd poi nt 0 interru pt

40x08 USB e nd poi nt 1 interru pt

50x0A Reserved

60x0C GPIO interrupt

70x0E Wake-up interrupt

76543210

WWWWWWWW

P0.7 Int En P0.6 Int En P0.5 Int En P0.4 Int En P0.3 Int En P0.2 Int En P0.1 Int En P0.0 Int En

Figure 5-17. Port 0 Interrupt Enable Register (Address 0x04)

76543210

WWWWWWWW

P1.7 Int En P1.6 Int En P1.5 Int En P1.4 Int En P1.3 Int En P1.2 Int En P1.1 Int En P1.0 Int En

Figure 5-18. Port 1 Interrupt Enable Register (Address 0x05)

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Pleas e note that if o ne port pin triggered an interrup t, no other port pins can cause a GPIO interrupt un til that port pin has returned

to its inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign

interrupt pri ority to differ ent port pins and the P ort Interrupt Enable Re gisters are n ot cl ear ed during the interrupt acknowledge

process. When a GPIO interrupt is serviced, the ISR must poll the ports to determin e which pin caused the int errupt.

5.8.3 USB Interrupt

A USB End Po int 0 interrup t is generated after the h ost ha s written data to End Point 0 or afte r th e USB Controller ha s transmitted

a packet from End Point 0 a nd receives an ACK from the host. An OUT pac ket f rom the host which is NAKd by the USB Controller

will not generate an interrupt. This interrupt is masked by the USB EP0 Interr upt Enable bit (bit 3) of the Global Interrupt Enable

A USB End Poi nt 1 interru pt is generated after the USB Controller has t ransmit ted a packet from En d Point 1 a n d h a s r e ceived

an ACK from the h ost. This interrupt is ma sked by the USB EP1 Interrupt Enable bit (bit 4) of the Global Interrupt Enable Register .

5.8.4 Timer Interrupt

There are two timer interrupts: the 1 28 µs inter rupt and the 1.024 ms interrupt. They are masked by bits 1 and 2 of the Global

Interrupt Enable Register respectively. The user should disable both timer interrupts before going into the suspend mode to

avoid possible conflicts between servicing the interrupts first or the suspend request first.

5.8.5 Wake-up Inter rupt

A wake-up interrupt is generated when the Cext pin i s HIGH. It is l evel s ensitive a nd is not lat ched to the interrupt contr oller. It

can be masked by the Wake-up Interrupt Enable bit (bit 7) of the Global Inter rupt Enable Register. This i nterru pt can be used to

perform periodic checks on attached peripherals when the USB Controll er is placed in the low- power su spend mode. See the

Instant-On Feature section for more details.

5.9 USB Engine

The USB engine includes the Serial Interface Engine (SIE) and the low-speed USB I/O transceivers. The SIE block performs

most of the USB interface functio ns with only minimal support from the microcontroller core. Two end points are supported. End

Point 0 is used to re ceive and transmit control (including setup) packets while End Point 1 is only used to transmit data packets.

The USB SIE pro cesses USB bus a ctivity at the transaction level in dependently. It does all the NRZI encoding/decoding and bit

stuff ing/unstuffing. I t also determines t o ken type, checks address and endpoi nt values, generate s and checks CRC v alues and

controls the flow of data byt es be tw een the bus and the End Point FIFOs.

Figure 5-19. GPIO Interrupt Logic Block Diagram

Port

Pull-Up

1= L➞H

0= H➞L12-Input

OR Gate

GPIO Interrupt

Flip Flop

CLR

GPIO

1 = Enable

0 = Di sa ble Port Interrupt

En abl e Regi ste r

1 = Enable

0 = Disable

Interrupt

Acknowledge

Global

GPIO Interrupt

Enable

Interrupt

Priority

Encoder

IRQ

Interrupt

Vector

CLR

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

The f irmware handles highe r lev el and function specific tasks. During c ontrol transfers the firmware mus t interpret device requests

and respond correctly. It also must coordinate Suspend/Resume, verify and select DATA toggle values, and perform function

specific tasks.

The USB engine and the firmware communicate though the E nd Point FIFOs, USB End Point inter rupts, and the USB re gisters

described in the sections below.

5.9.1 USB Enumeration Process

The USB Controller provides a USB Device Address Register at I/O location 0x12. Reading and writing this register is achieved

via the IORD and IOWR instructions. The register contents are cleared during a reset, setting the USB address of the USB

Controller to 0.

Figure 5-20

shows t he format of the USB Addr e ss Regist er.

Typical enumerat ion steps:

1. T he host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.

2. T he USB Contr oller d ecodes the r equest and retr ieves i ts Device descriptor from the program memory space.

3. Th e h ost computer performs a control read sequ ence and the USB Controller re sponds by send ing the Device descriptor over

the USB bus.

4. After receiving the descriptor, the host compu ter sends a SETUP packet follo wed by a DATA packe t to address 0 ass ign ing a

new USB address to the device.

5. Th e USB Controller stores the new addres s in its USB Device Ad dress Register a fter the no-da ta control sequence c ompletes.

6. T he host sends a req uest for the Device descr iptor using the new USB a ddress.

7. T he USB Contr oller d ecodes the r equest and r etr ieves th e Device descriptor from the program memory.

8. The host performs a control read sequence and the USB Controller responds by sending its Device descriptor over the USB

bus.

9. T he host gen er ate s control reads to the USB Controller to request the Config uration and Report descriptors.

10.T he USB Contr oller ret rieves the descriptor s from its program space and returns the data to th e host over t h e USB.

11.Enumeration i s complete after the host has received all the descriptors.

5.9.2 End Point 0

All USB devices are required to have an end point number 0 that is used to initial ize and m ani pulate the de vi ce. End Point 0

provides access to the device’s configur ation information and allows generic USB status and control accesses.

End Point 0 can re ceive and transm it data. Both receiv e a nd transmit data share the same 8-b yte End Point 0 FIFO l ocated at

data memory space 0x70 to 0x77. Received data may overwrite the data previously in the FIFO.

5.9.2.1 End Point 0 Receive

After receiving a packet and placing the data into the E nd Point 0 FIFO , the USB C ont roller updates the USB End Point 0 RX

register to record the receive status and then g enerates an USB End Point 0 interrupt. The format of the End Point 0 RX Register

is shown in

Figure 5-21

This is a read/wr ite register l ocated at I /O addr es s 0x14. Any writ e to this register wi ll clear al l bits except bit 3 which remains

unchanged. All bits ar e cleared durin g reset.

Bit 0 is set to 1 when a SETUP token for End Point 0 is rece ived. Once set to a 1 this bit remains high until it is cleared by an I/O

write or a reset. While the data following a SETUP is b eing received by the USB e ngine, th is bit will no t be cleared by an I /O write.

User firmware writes to the USB FIFOs are disabled when bit 0 is set. This prevents SETUP data from being overwritten.

76543210

R/W R/W R/W R/W R/W R/W R/W

Reserved ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

Figure 5-20. USB Device Address Register (Address 0x12)

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R R/W R/W R/W

Count 3 Count 2 Count 1 Count 0 Data Tog gle IN OUT SETUP

Figure 5-21. USB End Point 0 RX Register (Address 0x14)

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Bits 1 and 2 are updated whenever a valid token is r ecei ved on End Point 0. Bit 1 is set to 1 if an OUT token is received and

cleared to 0 if any other token i s receive d. Bit 2 is s et to 1 if an IN token is received a nd cleared to 0 if any other token is received .

Bit 3 shows the Data Toggle status of DATA packets received on End Point 0. This bit is updated for DATA following SETUP

tokens and for DATA f ollowing OUT tokens if Stall (bi t 5 of 0x10) i s not set and either EnableOuts or St atusOuts (bits 3 and 4 of

0x13) are set.

Bits 4 to 7 are the count of the number of bytes received in a DATA packet. The two CRC bytes are included in the count, so the

count value is two greater t han the number of data bytes received. The count is always updated and the data is always stored in

the FIFO for DATA p acke ts f ollowing a SETUP tok en. The count for DATA following an OUT token i s updated i f Stall (bit 5 of 0x10)

is 0 and ei ther EnableOuts or StatusOuts (bits 3 and 4 of 0x13) are 1. The DATA following an OUT will be written into the FIF O

if EnableOuts is set to 1 and St all a nd StatusOuts ar e 0.

A maximum of 8 bytes are written into the End Point 0 FIFO. If there are le ss the 8 by tes of data the CRC is written into the FIFO.

Due to reg is ter space li mitation s, the Receive Data Invalid bit is located in the USB End Point 0 TX Configuration Register. Refer

to t he End Point 0 Transmit section for details. This bit is set by t h e SIE if a n error is detecte d in a received DATA packet.

The table below summarizes the USB Engine response to SETUP and OUT transactions on End Point 0. In the Data Packet

column ‘Error ’ represents a pa cket wit h a CRC, PID or bit st uff ing er ror, or a packet with more than 8 bytes of data. ‘Vali d’ is a

packet without a n Error. ‘Status’ is a packet that is a valid control read Status s tage, while ‘N/Status’ is not a correct Status stage

(see section 5.9.4). T he ‘Sta ll’ bit is desc ribed is sec tion 5.9.2.2. The ‘StatusOuts’ and ‘En ableOuts’ bits are described in section

5.9.4.

5.9.2.2 En d Point 0 Transmit

The USB End P oint 0 TX Register located at I/O address 0x 10 controls data tr ansmi ssion from End Point 0 (see

Figure 5-23

This is a read/write re gister. All bits are cleared during reset.

Bits 0 to 3 indicate t he numbers of data bytes to be transmitte d during an IN packet , valid values are 0 t o 8 inclusive.

Bit 4 indicates that a received DATA packet error (CRC, PID, or bitstuffing er ror) occurred during a SETUP or OUT data phase.

Setting the Stall bit (bit 5) will stall IN and OUT packets. This bit is cleared whe never a SETUP packet is received by End Point 0.

Bit 6 (D ata 1/0) must be set to either 0 or 1 to select the DATA packet’s toggle stat e, 0 for DATA0, 1 f or DATA 1.

Cont rol Bit Setti n gs Received Packets USB Engine Response

Stall Status Out Enable Out Token

Type Data

Packet FIFO Wr ite Toggle

Update Count

Update Interrupt Reply

- - - SETUP Valid Yes Yes Yes Yes ACK

- - - SETUP Error Yes Yes Yes Yes None

0 0 1 OUT Valid Yes Yes Yes Yes ACK

0 0 1 OUT Error Yes Yes Yes Yes None

0 0 0 OUT Valid No No No No NAK

0 0 0 OUT Error No No No No None

1 0 0 OUT Valid No No No No STALL

1 0 0 OUT Error No No No No None

0 1 0 OUT Status No Yes Yes Yes ACK

0 1 0 OUT N/Status No Yes Yes Yes STALL

0 1 0 OUT Error No Yes No No None

Figur e 5-22. USB Engine R esponse to SETUP and OUT transactions on End Point 0

7 6 5 4 3 2 1 0

R/W R/W R/W R/W R/W R/W R/W R/W

Enable

Respond to IN

packets

Data 1/0 Stall Data Invalid Count 3 Count 2 Count 1 Count 0

Figure 5-23. USB End Poi nt 0 TX Configur ation Re gister (Addre ss 0x10)

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

After t he tr ansmit data has been loaded into the FI FO, bit 6 should be set according to t he data t o ggle state and bit 7 set to “1”.

This en ables the USB Controller to respond to an IN packet. Bit 7 is cleared an d an End Point 0 interrupt is generated by the SIE

once the host acknowledges the data transmission. Bit 7 is also cleared when a SETUP token is received. The Interrupt Service

Routine can check bit 7 to co nfirm that the data tra nsfer was successful.

5.9.3 End Point 1

End Point 1 is capable of transmit only. The data t o be transmitted is stored in the 8-byte End Point 1 F IFO located a t da ta memory

space 0x78 to 0x7F.

5.9.3.1 En d Point 1 Transmit

T ransmission is controlled by the US B End Point 1 TX Register located at I/O address 0x11 (see

Figure 5-24

). This is a read /wr ite

Bits 0 to 3 indicate t he numbers of data bytes to be transmitte d during an IN packet , valid values are 0 t o 8 inclusive.

Bit 4 must be set before End Point 1 can be used. I f this bit i s cleared, the USB Controller will ignore all tr affic to End P oint 1.

Setti ng the St all bit ( bit 5) will stall IN a nd OUT packets unt il this bit i s cleared.

Bit 6 (D ata 1/0) must be set to either 0 or 1 depending on the data packet’s toggle state, 0 for DATA0, 1 for DATA 1.

After t he tr ansmit data has been loaded into the FI FO, bit 6 should be set according to t he data t o ggle state and bit 7 set to “1”.

This en ables the USB Controller to respond to an IN packet. Bit 7 is cleared an d an End Point 1 interrupt is generated by the SIE

once the host acknowledges the data transmission.

5.9.4 USB Status and Control

USB status and control is regulated b y USB Status and Control Re gi ster l ocated at I/O addre ss 0x13 as shown in

Figure 5-2 5

This is a read/write re gister. All reserved bits must be writte n to zero. All bits in the register are clear e d during re set.

Bit 0 will be set by the SIE if any USB activity except idle (D+ LOW, D– HIGH) is detected. The user program should check and

clear this bit periodically to detect any lo ss of bus activit y. Wr iting a 0 to this bit clears it. Writing a 1 does not change its value.

Bit 1 is used to force the on-chip USB transmitter to th e K state which will send a Resume signal to the host.

Bit 2 is a reserved bit that m ust be set to 0.

Bit 3 is used to automatically respond t o the Status stage OUT of a control read transfer on End Point 0. A valid Stat us stage

OUT contains a DATA1 packet with 0 bytes of data. If the StatusOuts bit is set , t he USB engin e will respond to a valid Status

stage OUT with an ACK, a nd any other OUT with a STAL L. The data is not written into the FI FO when this bit i s set. This bit is

cleared when a SETUP token is received b y End Point 0.

Bit 4 is used t o enable t h e receiving of End Point 0 OUT packets. When this bit is set to 1, the data fr om an OUT tr ansaction to

be written into the End Point 0 FIFO and the USB en gine re spond s wi th an ACK. If this bit is 0, data will not b e written to the FIFO

and the r esponse is a NAK. This bit is cleare d following a SETUP or OUT transaction.

76543210

R/W R/W R/W R/W R/W R/W R/W R/W

Enable

Respond to IN

packets

Data 1/0 Stall End Point 1

Enable Count 3 Count 2 Count 1 Count 0

Figure 5-24. USB End Point 1 TX Configuration Register (Address 0x11)

76543210

R/W R/W R/W R/W

Reserved Reserved Reserved Enable Outs StatusOuts Reserved Force

Resume B u s Activit y

Figure 5-25. USB Status and Contr ol Re gister (Addre ss 0x13)

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

5.10 Instruction Set Summary

Table 5-4. Inst ructi on Set Map

MNEMONIC operand opcode cycles MNEMONIC operand opcode cycles

HALT 00 7 NOP 20 4

ADD A,expr data 01 4 INC A acc 21 4

ADD A,[expr] direct 02 6 INC X x 22 4

ADD A,[X+expr] index 03 7 INC [expr] direct 23 7

ADC A,expr data 04 4 INC [X+expr] index 24 8

ADC A,[expr] direct 05 6 DEC A acc 25 4

ADC A,[X+expr] index 06 7 DEC X x 26 4

SUB A,expr data 07 4 DEC [expr] direct 27 7

SUB A,[expr] direct 08 6 DEC [X+expr ] index 28 8

SUB A,[X+expr] index 09 7 I ORD expr address 29 5

SBB A,expr data 0A 4 I OWR expr address 2A 5

SBB A,[expr] direct 0B 6 POP A 2B 4

SBB A,[X+expr] index 0C 7 POP X 2C 4

OR A,expr data 0D 4 PUSH A 2D 5

OR A,[expr] direct OE 6 PUSH X 2E 5

OR A,[X+expr] index 0F 7 SWAP A,X 2F 5

AND A,expr data 10 4 S WAP A,D SP 30 5

AND A,[expr] direct 11 6 MOV [expr],A direct 31 5

AND A,[X+expr] index 12 7 MOV [X+expr],A index 32 6

XOR A,expr data 13 4 OR [expr],A direct 33 7

XOR A,[expr] direct 14 6 OR [X+expr],A index 34 8

XOR A,[X+expr] index 15 7 AND [expr],A direct 35 7

CMP A,expr data 16 5 AND [X+expr], A index 36 8

CMP A,[expr] direct 17 7 XOR [expr],A direct 37 7

CMP A,[X+expr] index 18 8 XOR [X+expr],A index 38 8

MO V A,expr data 19 4 I OWX [X+expr] index 39 6

MOV A,[expr] direct 1A 5 CPL 3A 4

MOV A,[X+expr] index 1B 6 ASL 3B 4

MO V X,expr data 1C 4 ASR 3C 4

MOV X,[expr] direct 1D 5 RLC 3D 4

IPRET addr 1E 13 RRC 3E 4

XPAGE 1F 4 RET 3F 8

JMP addr 8x 5 JC addr Cx 5

CALL addr 9x 10 JNC addr Dx 5

JZ addr Ax 5 JACC addr Ex 7

JNZ addr Bx 5 INDEX addr Fx 14

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

6.0 Absolute Maximum Ratings

Storage Temperature ......................................................................................................................................... –65oC to +150oC

Ambient Temperature with Power Applied.................................................................................. ............................ –0oC to +70oC

Supply volta ge on VCC relativ e to VSS............. .. ....................................... ....................................... .......................–0.5V to +7.0V

DC input voltage........................................................................................................................................... –0.5V to +VCC+0.5V

DC voltage applied to outputs in High Z state........................................... .................................................... –0.5V to +VCC+0.5V

Max. output current into Port 1 pins..................................................... ....................................... ..... .......... .......... ............ .... 60 m A

Max. output current into non-Port 1 pins............................. ..... ...................................................... ....... .......... .......... ....... ... 1 0 mA

Power dissipation........................................................................................................................ ............. ............ ............ ..300 mW

Static discharge volta ge ..... ................. .......... ....... .......... ................. ................. ............ ..... ............ ...................... ..... ....... .. >2000V

Latch-u p current .. ....... .......... ....... ..... .......... ....... .......... ....... .......... ....... .......... ....... .......... ........ ........................................ >200 mA

7.0 DC Characteristics Fosc = 6 MHz; Operating Tem perature = 0 to 7 0°C

Parameter Min Max Units Conditions

General

Vcc Operating Volt a ge 4.0 5. 25 V

Vmax Maximum applied voltag e –0.5 6.5 V

ICC Vcc Operating Supply Current 50 mA

ISB1 Supply Current - Suspend Mode 10 0 µA Oscillator off, D– > Voh min

ISB2 Supply Current - Star t-up M ode 4 mA Vcc = 5.0V

Vpp Programming Voltage (disabled) –0.4 0.4 V

tstart Resonator Start-up Interval 256 µsV

cc = 5.0V, ceramic resonator

tint1 Internal timer #1 interrupt per iod 12 8 128 µs

tint2 Internal ti mer #2 interrupt period 1.024 1.024 m s

twatch WatchDog timer period 7.168 8.192 m s

Power On Reset

Vrst POR Voltage 2.0 3.4 V NOTE [2, 6]

tvccs VCC reset slew 0.5 100 m s linear ramp VCC: 0 to Vrst

USB Interface

Voh Stati c Output High 2.8 3.6 V 15 k ± 5% Ω to Gnd [3, 4]

Vol Stati c Output Low 0.3 V NOTE 4

General Purpose I/O

Rup Pull-u p resistance 8K 24 K Ωs

Isink0(0) Port 0 sink current (0), lowest current 0.1 0.3 mA Vout = 2.0 V DC, Port 0 only [4]

Isink0(F) Port 0 sink current (F), highest current 0.5 1.5 mA Vout = 2.0 V DC, Port 0 only [4]

Isink1(0) Port 1 sink current (0), lowest current 1.6 4.8 mA Vout = 2.0 V DC, Port 1 only [4]

Isink1(F) Port 1 sink current (F), highest current 8 24 mA Vout = 2.0 V DC, Port 1 only [4]

Irange Sink current max/min 4.5 5.5 Vout = 2.0 V DC, Port 0 or 1 [1, 10]

Ilin Differential nonlinearity 0.5 lsb Port 0 or Port 1 [5]

Iil Input leakage current 50 nA CEXT only

Iol Sink current 6 18 mA CEXT only

Notes:

1. Per Table 7-6 of revision 1.0 of USB s pecification, for Cload of 100–350pF.

2. Power on Reset will occur until the voltage on VCC increases above Vrst.

3. Rx: external idle resistor, 7.5 KΩ, 2%, to VCC.

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

8.0 Switching Characteristics

Notes:

4. 4.35 V to 5.25 V VCC.

5. Measured as largest step size vs nominal according to measured full scale and zero programmed values.

6. POR can occur only once per applied VCC, if VCC drops below V rst, POR wi ll not re-oc cur . VCC must return to 0.0V before POR will be re-applied on a subsequent

VCC ramp.

7. Low to High transition

8. This parameter is guaranteed, but not tested.

9. Tratio = Isink1(n)/Isink0(n) for the same n

10. Irange = Isink(F)/Isink(O) for port 0 or 1 output

tsink Current sink response time 0.8 µs Full scale transiti on

General Purpose I/O (continued)

Tratio Tracking Ratio Port1 to Port0 13.6 18.4 Vout = 2.0V[9]

Imax Port 1 max sink current 60 mA Summed over all Port 1 bits

Pmax Port 1 & CEXT sink mode dissipation 25 mW Per pin

Vith Input Threshold Voltage 45% 65% Vc c All ports and Cext [7]

VHInput Hysteresi s Volt a ge 6% 12% Vcc All ports and Cext [8]

VOL1 Output LO W Voltage, C ext pin 0.4 V VCC = Min., IOL = 2mA

VOL2 Output LO W Voltage, C ext pin 2.0 V VCC = Min., IOL = 5mA

Parameter Description Min. Max. Unit

tCYC Input clock cycle time 166.67 166.67 ns

tCH Clock HIGH time 0.45 tCYC ns

tCL Clock LOW t ime 0.45 tCYC ns

trTransition Rise Time [1, 4, 8] 75 300 ns

tfTransition Fall Time [1, 4, 8] 75 300 ns

7.0 DC Characteristics (continued) Fosc = 6 MHz; Operating Temperature = 0 to 70°C

Parameter Min Max Units Conditions

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Document #: 38- 00557-D

Figure 8-1. Clock Tim ing

Figure 8-2. USB Data Signal Timing

9.0 Ordering Inf ormation

Orderi ng Co de EPROM

Size Number

of GPIO Package Ty pe Operating

Range

CY7C63000-PC 2KB 12 20-Pin (300-Mil) PDIP Commercial

CY7C63000-SC 2KB 12 20-Pin (300-Mil) SOIC Commercial

CY7C63001-PC 4KB 12 20-Pin (300-Mil) PDIP Commercial

CY7C63001-SC 4KB 12 20-Pin (300-Mil) SOIC Commercial

CY7C63001-WC 4KB 12 20-Pin (300-Mil) Windowed CerDIP Commercial

CY7C63100-SC 2KB 16 24-Pin (300-Mil) SOIC Commercial

CY7C63101-SC 4KB 16 24-Pin (300-Mil) SOIC Commercial

CY7C63101-WC 4KB 16 24-Pin (300-Mil) Windowed CerDIP Commercial

CY7C63200-PC 2KB 10 18-Pin (300-Mil) PDIP Commercial

CY7C63201-PC 4KB 10 18-Pin (300-Mil) PDIP Commercial

CY7C63201-WC 4KB 10 18-Pin (300-Mil) Windowed CerDIP Commercial

CLOCK

tCYC

tCL

tCH

90%

10%

90%

10%

D−

D+trtf

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Package Diagrams

20-Lead (300-Mil) Windowed CerDIP W6

MIL-STD-1835 D-8 Config. A

18-Lead (300-Mil) Molded DIP

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

Package Diagrams (co ntinued)

20-Lead (300-Mil) Molded DIP

20-Lead (300-Mil) Molded SOIC

CY7C63000/CY7C63001

CY7C63100/CY7C63101

CY7C63200/CY7C63201

PRELIMINARY

of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor do es it convey or im ply an y li cens e under p atent or other rights . Cy press Semi conductor does not authori ze

its products for use as critical components in life- support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (co ntinued)

24-Lead (300-Mil) Molded SOIC

24-Lead (300-Mil) Windowed CerDIP W14

MIL-STD-1835 D-9 Config. A