CM1213A01SO - ON SEMICONDUCTOR

November, 2018 − Rev. 15

1Publication Order Number:

CM1213A/D

CM1213A, SZCM1213A

1, 2 and 4-Channel

Low Capacitance

ESD Protection Arrays

Product Description

The CM1213A family of diode arrays has been designed to provide

ESD protection for electronic components or subsystems requiring

minimal capacitive loading. These devices are ideal for protecting

systems with high data and clock rates or for circuits requiring low

capacitive loading. Each ESD channel consists of a pair of diodes in

series which steer the positive or negative ESD current pulse to either

the positive (VP) or negative (VN) supply rail. A Zener diode is

embedded between VP and VN, offering two advantages. First, it

protects the VCC rail against ESD strikes, and second, it eliminates the

need for a bypass capacitor that would otherwise be needed for

absorbing positive ESD strikes to ground. The CM1213A will protect

against ESD pulses up to 12 kV per the IEC 61000−4−2 standard.

Features

•One, Two, and Four Channels of ESD Protection

Note: For 6 and 8−channel Devices, See the CM1213 Datasheet

•Provides ESD Protection to IEC61000−4−2 Level 4

♦±12 kV Contact Discharge

•Low Channel Input Capacitance of 0.85 pF Typical

•Minimal Capacitance Change with Temperature and Voltage

•Channel Input Capacitance Matching of 0.02 pF Typical is Ideal for

Differential Dignals

•Each CH (I/O) Pin Can Withstand Over 1000 ESD Strikes*

•SZ Prefix for Automotive and Other Applications Requiring Unique

Site and Control Change Requirements; AEC−Q101 Qualified and

PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Applications

•USB2.0 Ports at 480 Mbps in Desktop PCs, Notebooks and Peripherals

•IEEE1394 Firewire® Ports at 400 Mbps/800 Mbps

•DVI Ports, HDMI Ports in Notebooks, Set Top Boxes, Digital TVs,

LCD Displays

•Serial ATA Ports in Desktop PCs and Hard Disk Drives

•PCI Express Ports

•General Purpose High−Speed Data Line ESD Protection

*Standard test condition is IEC61000−4−2 level 4 test circuit with each pin subjected to ±8 kV contact discharge for 1000 pulses. Discharges

are timed at 1 second intervals and all 1000 strikes are completed in one continuous test run. The part is then subjected to standard production

test to verify that all of the tested parameters are within spec after the 1000 strikes.

MARKING DIAGRAMS

SOT23−3

SO SUFFIX

CASE 318

www.onsemi.com

SOT−143

SR SUFFIX

CASE 318A

SC70−6

S7 SUFFIX

CASE 419AD

XXXMG

MSOP−10

MR SUFFIX

CASE 846AE

XXXMG

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

(Note: Microdot may be in either location)

SC−74

SO SUFFIX

CASE 318F

See detailed ordering, marking and shipping information in the

package dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

XXXX

AYWG

XXXX = Specific Device Code

A = Assembly Location

Y = Year

W = Work Week

G= Pb−Free Package

CM1213A, SZCM1213A

www.onsemi.com

CH4 VP

CH3

CH1 CH2

CM1213A−04MR

CM1213A−04S7

CH1

CM1213A−02SR

CM1213A−02SO

CH2

BLOCK DIAGRAM

CH1

CM1213A−01SO

Table 1. ORDERING INFORMATION

Device Marking Package Shipping†

CM1213A−01SO 231 SOT23−3

(Pb−Free)

3,000 / Tape & Reel

SZCM1213A−01SO*

CM1213A−02SR D232 SOT143−4

(Pb−Free)

3,000 / Tape & Reel

SZCM1213A−02SR*

CM1213A−02SO 233 SC−74

(Pb−Free)

3,000 / Tape & Reel

CM1213A−04S7 D38 SC70−6

(Pb−Free)

3,000 / Tape & Reel

CM1213A−04MR D237 MSOP−10

(Pb−Free)

4,000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP

Capable.

CM1213A, SZCM1213A

www.onsemi.com

Table 2. PIN DESCRIPTIONS

1−Channel, 3−Lead SOT23−3 Package (CM1213A−01SO)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 VPPWR Positive Voltage Supply Rail

3 VNGND Negative Voltage Supply Rail

2−Channel, 4−Lead SOT143−4 Package (CM1213A−02SR)

Pin Name Type Description

1 VNGND Negative Voltage Supply Rail

2 CH1 I/O ESD Channel

3 CH2 I/O ESD Channel

4 VPPWR Positive Voltage Supply Rail

2−Channel, SC−74 Package (CM1213A−02SO)

Pin Name Type Description

1 NC −No Connect

2 VN GND Negative Voltage Supply Rail

3 CH1 I/O ESD Channel

4 CH2 I/O ESD Channel

5 NC −No Connect

6 VP PWR Positive Voltage Supply Rail

4−Channel, 6−Lead SC70−6 (CM1213A−04S7)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 VNGND Negative Voltage Supply Rail

3 CH2 I/O ESD Channel

4 CH3 I/O ESD Channel

5 VPPWR Positive Voltage Supply Rail

6 CH4 I/O ESD Channel

4−Channel, 10−Lead MSOP−10 Package (CM1213A04MR)

Pin Name Type Description

1 CH1 I/O ESD Channel

2 NC −No Connect

3 VPPWR Positive Voltage Supply Rail

4 CH2 I/O ESD Channel

5 NC −No Connect

6 CH3 I/O ESD Channel

7 NC −No Connect

8 VNGND Negative Voltage Supply Rail

9 CH4 I/O ESD Channel

10 NC −No Connect

PACKAGE/PINOUT DIAGRAMS

Top View

CH1

CH2

CH4

CH356

10−Lead MSOP−10

Top View

CH1 (1)

VN (3)

3−Lead SOT23−3

VP (2)

Top View

CH1 (2)

VP (4)

4−Lead SOT143−4

VN (1)

CH2 (3)

Top View

CH2

6−Lead SC70−6

CH3

CH1 1

6 CH4

Top View

CH1 (3)

NC (5)

6−Lead SC−74

VN (2)

CH2 (4)

NC (1) VP (6)

231 D232 D38233 D238

CM1213A, SZCM1213A

www.onsemi.com

SPECIFICATIONS

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter Rating Units

Operating Supply Voltage (VP − VN) 5.5 V

Operating Temperature Range –40 to +150 °C

Storage Temperature Range –65 to +150 °C

DC Voltage at any channel input (VN − 0.5) to (VP + 0.5) V

Package Power Rating

SOT23−3, SOT143−4, SC−74, and SC70−6 Packages

MSOP−10 Package

225

400

ESD

IEC 61000−4−2 Contact

IEC 61000−4−2 Air

ISO 10605 330 pF / 330 W Contact

ISO 10605 330 pF / 2 kW Contact

ISO 10605 150 pF / 2 kW Contact

±12

±9

±22

±25

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

Table 4. ELECTRICAL OPERATING CHARACTERISTICS (Note1)

Symbol Parameter Conditions Min Typ Max Units

VP (VRWM)Operating Supply Voltage (VP−VN) 3.3 5.5 V

IPOperating Supply Current VP pin to VN pin, (VP = 3.3 V, VN = 0 V) 8.0 mA

ILEAK Channel Leakage Current CH pin to VN pin, TA = 25°C;

(VP = 5 V, VN = 0 V)

0.1 1.0 mA

VFDiode Forward Voltage

Top Diode

Bottom Diode

IF = 8 mA; TA = 25°C

0.60

0.80

0.95

VBR Breakdown Voltage IT = 10 mA, CH pin to VN pin 6.5 9.0 V

CIN Channel Input Capacitance At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V

(Note 2)

0.85 1.2 pF

DCIN Channel Input Capacitance Matching At 1 MHz, VP = 3.3 V, VN = 0 V, VIN = 1.65 V

(Note 2)

0.02 pF

VCL Channel Clamp Voltage

Positive Transients

Negative Transients

TA = 25°C, IPP = 1A, tP = 8/20 ms

(Note 2) +10

–1.7

RDYN Dynamic Resistance

Positive Transients

Negative Transients

IPP = 1A, tP = 8/20 ms

Any I/O pin to Ground

(Note 2)

0.9

0.5

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

1. All parameters specified at TA = 25°C unless otherwise noted.

2. Standard IEC 61000−4−2 with CDischarge = 150 pF, RDischarge = 330 W, VP = 3.3 V, VN grounded.

3. These measurements performed with no external capacitor on VP (VP floating).

CM1213A, SZCM1213A

www.onsemi.com

PERFORMANCE INFORMATION

Input Channel Capacitance Performance Curves

Figure 1. Typical Variation of CIN vs. VIN

(f = 1 MHz, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN, 255C)

Figure 2. Typical Variation of CIN vs. Temp

(f = 1 MHz, VIN = 30 mV, VP = 3.3 V, VN = 0 V, 0.1 F Chip Capacitor between VP and VN)

CM1213A, SZCM1213A

www.onsemi.com

PERFORMANCE INFORMATION (Cont’d)

Typical Filter Performance (nominal conditions unless specified otherwise, 50 Ohm Environment)

Figure 3. Insertion Loss (S21) vs. Frequency (0 V DC Bias, VP=3.3 V)

Figure 4. Insertion Loss (S21) vs. Frequency (2.5 V DC Bias, VP=3.3 V)

CM1213A, SZCM1213A

www.onsemi.com

APPLICATION INFORMATION

Design Considerations

In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic

series inductances on the Supply/Ground rails as well as the signal trace segment between the signal input (typically

a connector) and the ESD protection device. Refer to Application of Positive ESD Pulse between Input Channel and Ground,

which illustrates an example of a positive ESD pulse striking an input channel. The parasitic series inductance back to the power

supply is represented by L1 and L2. The voltage VCL on the line being protected is:

VCL = Fwd Voltage Drop of D1 + VSUPPLY + L1 x d(IESD) / dt + L2 x d(IESD) / dt

where IESD is the ESD current pulse, and VSUPPLY is the positive supply voltage.

An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge

per the IEC61000−4−2 standard results in a current pulse that rises from zero to 30 Amps in 1 ns. Here d(IESD)/dt can be

approximated by DIESD/Dt, or 30/(1x10−9). So just 10 nH of series inductance (L1 and L2 combined) will lead to a 300 V

increment in VCL!

Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically

increased negative voltage on the line being protected.

The CM1213A has an integrated Zener diode between VP and VN. This greatly reduces the effect of supply rail inductance

L2 on VCL by clamping VP at the breakdown voltage of the Zener diode. However, for the lowest possible VCL, especially when

VP is biased at a voltage significantly below the Zener breakdown voltage, it is recommended that a 0.22 mF ceramic chip

capacitor be connected between VP and the ground plane.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Note “Design Considerations for ESD Protection”, in the Applications section.

ÇÇÇÇÇÇ

POSITIVE SUPPLY RAIL

CHANNEL

INPUT

GROUND RAIL

CHASSIS GROUND

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ONE

CHANNEL

CM1213

D1L1

L2VCC

VCL

0.22 mF

PATH OF ESD CURRENT PULSE IESO

0 A

25 A

Figure 5. Application of Positive ESD Pulse between Input Channel and Ground

SOT−23 (TO−236)

CASE 318−08

ISSUE AS DATE 30 JAN 201

SCALE 4:1

XXXMG

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

GENERIC

MARKING DIAGRAM*

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH.

MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF

THE BASE MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,

PROTRUSIONS, OR GATE BURRS.

SOLDERING FOOTPRINT

VIEW C

0.25

SEE VIEW C

DIM

AMIN NOM MAX MIN

MILLIMETERS

0.89 1.00 1.11 0.035

INCHES

A1 0.01 0.06 0.10 0.000

b0.37 0.44 0.50 0.015

c0.08 0.14 0.20 0.003

D2.80 2.90 3.04 0.110

E1.20 1.30 1.40 0.047

e1.78 1.90 2.04 0.070

L0.30 0.43 0.55 0.012

0.039 0.044

0.002 0.004

0.017 0.020

0.006 0.008

0.114 0.120

0.051 0.055

0.075 0.080

0.017 0.022

NOM MAX

STYLE 22:

PIN 1. RETURN

2. OUTPUT

3. INPUT

STYLE 6:

PIN 1. BASE

2. EMITTER

3. COLLECTOR

STYLE 7:

PIN 1. EMITTER

2. BASE

3. COLLECTOR

STYLE 8:

PIN 1. ANODE

2. NO CONNECTION

3. CATHODE

STYLE 9:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 10:

PIN 1. DRAIN

2. SOURCE

3. GATE

STYLE 11:

PIN 1. ANODE

2. CATHODE

3. CATHODE−ANODE

STYLE 12:

PIN 1. CATHODE

2. CATHODE

3. ANODE

STYLE 13:

PIN 1. SOURCE

2. DRAIN

3. GATE

STYLE 14:

PIN 1. CATHODE

2. GATE

3. ANODE

STYLE 15:

PIN 1. GATE

2. CATHODE

3. ANODE

STYLE 16:

PIN 1. ANODE

2. CATHODE

3. CATHODE

STYLE 17:

PIN 1. NO CONNECTION

2. ANODE

3. CATHODE

STYLE 18:

PIN 1. NO CONNECTION

2. CATHODE

3. ANODE

STYLE 19:

PIN 1. CATHODE

2. ANODE

3. CATHODE−ANODE

STYLE 23:

PIN 1. ANODE

2. ANODE

3. CATHODE

STYLE 20:

PIN 1. CATHODE

2. ANODE

3. GATE

STYLE 21:

PIN 1. GATE

2. SOURCE

3. DRAIN

STYLE 1 THRU 5:

CANCELLED

STYLE 24:

PIN 1. GATE

2. DRAIN

3. SOURCE

STYLE 25:

PIN 1. ANODE

2. CATHODE

3. GATE

STYLE 26:

PIN 1. CATHODE

2. ANODE

3. NO CONNECTIO

STYLE 27:

PIN 1. CATHODE

2. CATHODE

3. CATHODE

2.10 2.40 2.64 0.083 0.094 0.104

HE0.35 0.54 0.69 0.014 0.021 0.027

c0 −−− 10 0 −−− 10

T°°°°

(Note: Microdot may be in either location)

TOP VIEW

SIDE VIEW END VIEW

2.90

0.80

DIMENSIONS: MILLIMETERS

0.90

PITCH

3X 0.95

RECOMMENDED

STYLE 28:

PIN 1. ANODE

2. ANODE

3. ANODE

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98ASB42226B

ON SEMICONDUCTOR STANDARD

SOT−23 (TO−236)

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98ASB42226B

PAGE 2 OF 2

ISSUE REVISION DATE

AJ ADDED STYLE 27. REQ. BY P. LEM. 07 JUL 2004

AK OBSOLETED −09 VERSION. REQ. BY D. TRUHITTE. 14 SEP 2004

AL ADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ.

BY HONG XIAO. 27 MAY 2005

AM REDREW LEAD SIDE VIEW. REQ BY DARRELL TRUHITTE. 26 AUG 2005

AN REINTRODUCED LABELS FOR DIMENSION C. REQ. BY D. TRUHITTE. 14 OCT 2005

AP ADDED THETA DEGREE VALUES TO DIMENSION TABLE. REQ. BY D. TRUHITTE. 17 NOV 2009

AR MODIFIED DIMENSIONS C AND L. REQ. BY M. YOU. 10 OCT 2016

AS ADDED STYLE 28. REQ. BY E. ESTILLER. 30 JAN 2018

January, 2018 − Rev. AS Case Outline Number

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

SOT−143

CASE 318A−06

ISSUE U

DATE 07 SEP 2011

SCALE 4:1

XXX MG

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

GENERIC

MARKING DIAGRAM*

DIM

MIN MAX

2.80 3.05

MILLIMETERS

E1 1.20 1.40

A0.80 1.12

b0.30 0.51

b1 0.76 0.94

e1.92 BSC

L0.35 0.70

c0.08 0.20

L2 0.25 BSC

e1 0.20 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH. MINIM

UM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE

MATERIAL.

4. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PRO

TRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS,

AND GATE BURRS SHALL NOT EXCEED 0.25 PER SIDE.

DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR

PROTRUSION. INTERLEAD FLASH AND PROTRUSION SHALL

NOT EXCEED 0.25 PER SIDE.

5. DIMENSIONS D AND E1 ARE DETERMINED AT DATUM H.

6. DATUMS A AND B ARE DETERMINED AT DATUM H.

STYLE 1:

PIN 1. COLLECTOR

2. EMITTER

3. EMITTER

4. BASE

STYLE 2:

PIN 1. SOURCE

2. DRAIN

3. GATE 1

4. GATE 2

STYLE 6:

PIN 1. GND

2. RF IN

3. VREG

4. RF OUT

STYLE 3:

PIN 1. GROUND

2. SOURCE

3. INPUT

4. OUTPUT

STYLE 4:

PIN 1. OUTPUT

2. GROUND

3. GROUND

4. INPUT

STYLE 7:

PIN 1. SOURCE

2. GATE

3. DRAIN

4. SOURCE

STYLE 8:

PIN 1. SOURCE

2. GATE

3. DRAIN

4. N/C

STYLE 5:

PIN 1. SOURCE

2. DRAIN

3. GATE 1

4. SOURCE

STYLE 9:

PIN 1. GND

2. IOUT

3. VCC

4. VREF

STYLE 10:

PIN 1. DRAIN

2. N/C

3. SOURCE

4. GATE

STYLE 11:

PIN 1. SOURCE

2. GATE 1

3. GATE 2

4. DRAIN

(Note: Microdot may be in either location)

A-B

0.20 DC

0.10 C

SIDE VIEW SEATING

PLANE

SOLDERING FOOTPRINT

0.75

DIMENSIONS: MILLIMETERS

0.54

1.92

RECOMMENDED

A1 0.01 0.15

TOP VIEW

3X b

AA1 C

END VIEW

SEATING

PLANE

L2 L

GAUGE

PLANE

DETAIL A

2.70

0.20

0.96

E2.10 2.64

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0

Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98ASB42227B

ON SEMICONDUCTOR STANDARD

SOT−143

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98ASB42227B

PAGE 2 OF 2

ISSUE REVISION DATE

UREDREW TO JEDEC STANDARDS. ADDED SOLDER FOOTPRINT. REQ. BY D.

TRUHITTE.

07 SEP 2011

September, 2011 − Rev. 06U

Case Outline Number:

318A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

SC−74

CASE 318F−05

ISSUE N DATE 08 JUN 2012

SCALE 2:1

STYLE 1:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. CATHODE

5. ANODE

6. CATHODE

456

0.05 (0.002)

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH

THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM

THICKNESS OF BASE MATERIAL.

4. 318F−01, −02, −03, −04 OBSOLETE. NEW STANDARD 318F−05.

STYLE 2:

PIN 1. NO CONNECTION

2. COLLECTOR

3. EMITTER

4. NO CONNECTION

5. COLLECTOR

6. BASE

XXX MG

XXX = Specific Device Code

M = Date Code

G= Pb−Free Package

GENERIC

MARKING DIAGRAM*

STYLE 3:

PIN 1. EMITTER 1

2. BASE 1

3. COLLECTOR 2

4. EMITTER 2

5. BASE 2

6. COLLECTOR 1

STYLE 4:

PIN 1. COLLECTOR 2

2. EMITTER 1/EMITTER 2

3. COLLECTOR 1

4. EMITTER 3

5. BASE 1/BASE 2/COLLECTOR 3

6. BASE 3

STYLE 5:

PIN 1. CHANNEL 1

2. ANODE

3. CHANNEL 2

4. CHANNEL 3

5. CATHODE

6. CHANNEL 4

STYLE 6:

PIN 1. CATHODE

2. ANODE

3. CATHODE

4. CATHODE

5. CATHODE

6. CATHODE

STYLE 7:

PIN 1. SOURCE 1

2. GATE 1

3. DRAIN 2

4. SOURCE 2

5. GATE 2

6. DRAIN 1

STYLE 8:

PIN 1. EMITTER 1

2. BASE 2

3. COLLECTOR 2

4. EMITTER 2

5. BASE 1

6. COLLECTOR 1

0.7

0.028

1.9

0.074

0.95

0.037

2.4

0.094

1.0

0.039

0.95

0.037

ǒmm

inchesǓ

SCALE 10:1

*This information is generic. Please refer to

device data sheet for actual part marking.

Pb−Free indicator, “G” or microdot “ G”,

may or may not be present.

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

DIM

AMIN NOM MAX MIN

MILLIMETERS

0.90 1.00 1.10 0.035

INCHES

A1 0.01 0.06 0.10 0.001

b0.25 0.37 0.50 0.010

c0.10 0.18 0.26 0.004

D2.90 3.00 3.10 0.114

E1.30 1.50 1.70 0.051

e0.85 0.95 1.05 0.034

0.20 0.40 0.60 0.008

0.039 0.043

0.002 0.004

0.015 0.020

0.007 0.010

0.118 0.122

0.059 0.067

0.037 0.041

0.016 0.024

NOM MAX

2.50 2.75 3.00 0.099 0.108 0.118

HE− −

0°10°0°10°

STYLE 9:

PIN 1. EMITTER 2

2. BASE 2

3. COLLECTOR 1

4. EMITTER 1

5. BASE 1

6. COLLECTOR 2

(Note: Microdot may be in either location)

STYLE 10:

PIN 1. ANODE/CATHODE

2. BASE

3. EMITTER

4. COLLECTOR

5. ANODE

6. CATHODE

STYLE 11:

PIN 1. EMITTER

2. BASE

3. ANODE/CATHODE

4. ANODE

5. CATHODE

6. COLLECTOR

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

NEW STANDARD:

DESCRIPTION:

98ASB42973B

ON SEMICONDUCTOR STANDARD

SC−74

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98ASB42973B

PAGE 2 OF 2

ISSUE REVISION DATE

DCHANGE OF OWNERSHIP FROM MOTOROLA TO ON SEMICONDUCTOR.

DIM A WAS: 2.70−3.10 MM/0.1063−0.1220 IN.

DIM C WAS: 1.000−1.30 MM/0.0394−0.0511IN

DIM D WAS: 0.25−0.40 MM/0.0098−0.0157 IN. REQ. BY D. TRUHITTE

14 MAR 01

ECHANGED “USED ON” WAS: SC−59, 6 LEAD. REQ.BY D. TRUHITTE. 27 MAR 01

FADDED STYLE 3. REQ. BY S. BACHMAN. 23 APR 01

GADDED STYLE 4. REQ. BY S. BACHMAN. 28 AUG 02

HADDED STYLE 5. REQ. BY B. BLACKMON. 21 OCT 02

JADDED STYLE 6. REQ. BY B. BLACKMON. 09 JAN 03

KADDED STYLES 7 & 8. REQ. BY S. CHANG 03 JUN 03

LADDED NOMINAL VALUES AND UPDATED GENERIC MARKING DIAGRAM. REQ. BY

HONG XIAO. 27 MAY 05

MADDED STYLE 9. REQ. BY W. MEADOWS. 11 APR 2006

NADDED STYLES 10 & 11. REQ. BY Y. KALDERON. 08 JUN 2012

June, 2012 − Rev. N Case Outline Number

318F