HM534251B Series 262144-word x 4-bit Multiport CMOS Video RAM The HM534251B is a 1-Mbit multiport video RAM equipped with a 256-kword x 4-bit dynamic RAM and a 512-word x 4-bit SAM (serial access memory). Its RAM and SAM operate independently and asynchronously. It can transfer data between RAM and SAM and has write mask function. Features * Multiport organization Asynchronous and simultaneous operation of RAM and SAM capability RAM: 256 kword x 4 bit SAM: 512 word x 4 bit * Access time RAM: 60 ns/70 ns/80 ns/100 ns max SAM: 20 ns/22 ns/25 ns/25 ns max * Cycle time RAM: 125 ns/135 ns/150 ns/180 ns min SAM: 25 ns/25 ns/30 ns/30 ns min * Low power Active RAM: 413 mW max SAM: 275 mW max Standby 38.5 mW max * High-speed page mode capability * Mask write mode capability * Bidirectional data transfer cycle between RAM and SAM capability * Real time read transfer cycle capability * 3 variations of refresh (8 ms/512 cycles) RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible Ordering Information Type No. Access time Package --------------------------------------------- HM534251BJ-6 60 ns 400-mil 28-pin HM534251BJ-7 70 ns plastic SOJ HM534251BJ-8 80 ns (CP-28D) HM534251BJ-10 100 ns --------------------------------------------- HM534251BZ-6 60 ns 400-mil 28-pin HM534251BZ-7 70 ns plastic ZIP HM534251BZ-8 80 ns (ZP-28) HM534251BZ-10 100 ns --------------------------------------------- HM534251BT-6 60 ns 8 mm x 14 mm HM534251BT-7 70 ns 32-pin TSOP HM534251BT-8 80 ns type I HM534251BT-10 100 ns (TFP-32DA) --------------------------------------------- HM534251BR-6 60 ns 8 mm x 14 mm HM534251BR-7 70 ns 32-pin TSOP HM534251BR-8 80 ns type I reverse HM534251BR-10 100 ns (TFP-32DAR) --------------------------------------------- HM534251B Series HM534251B Series Pin Arrangement HM534251BJ Series SC SI/O0 SI/O1 DT/OE I/O0 I/O1 WE NC RAS A8 A6 A5 A4 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 HM534251BT Series 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS SI/O3 SI/O2 SE I/O3 I/O2 NC CAS NC A0 A1 A2 A3 A7 NC I/O2 I/O3 SE SI/O2 SI/O3 VSS NC NC SC SI/O0 SI/O1 DT/OE I/O0 I/O1 WE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CAS NC A0 A1 A2 A3 A7 NC NC VCC A4 A5 A6 A8 RAS NC 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC RAS A8 A6 A5 A4 VCC NC NC A7 A3 A2 A1 A0 NC CAS (Top View) (Top View) HM534251BZ Series I/O2 SE SI/O3 SC SI/O1 I/O0 WE RAS A6 A4 A7 A2 A0 CAS HM534251BR Series 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 NC I/O3 SI/O2 VSS SI/O0 DT/OE I/O1 NC A8 A5 VCC A3 A1 NC WE I/O1 I/O0 DT/OE SI/O1 SI/O0 SC NC NC VSS SI/O3 SI/O2 SE I/O3 I/O2 NC 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Top View) (Bottom View) Pin Description Pin name Function --------------------------------------------- A0 - A8 Address inputs --------------------------------------------- I/O0 - I/O3 RAM port data inputs/outputs --------------------------------------------- SI/O0 - SI/O3 SAM port data inputs/outputs --------------------------------------------- RAS Row address strobe --------------------------------------------- CAS Column address strobe --------------------------------------------- WE Write enable --------------------------------------------- Pin name Function --------------------------------------------- DT/OE Data transfer/Output enable --------------------------------------------- SC Serial clock --------------------------------------------- SE SAM port enable --------------------------------------------- VCC Power supply --------------------------------------------- VSS Ground --------------------------------------------- NC No connection --------------------------------------------- 2 HM534251B Series HM534251B Series Block Diagram A0 - A8 Row Address Buffer Refresh Counter Serial Address Counter Sense Amplifier & I/O Bus SAM I/O Bus Memory Array Data Register Column Decoder Row Decoder Input Data Control Mask Register Serial Output Buffer SAM Column Decoder Column Address Buffer Serial Input Buffer SI/O0 - SI/O3 Output Buffer Timing Generator I/O0 - I/O3 RAS CAS DT/OE WE SC SE Input Buffer 3 HM534251B Series Pin Functions RAS (input pin): RAS is a basic RAM signal. It is active in low level and standby in high level. Row address and signals as shown in table 1 are input at the falling edge of RAS. The input level of these signals determine the operation cycle of the HM534251B. Table 1. Operation Cycles of the HM534251B Input level at the falling edge of RAS -------------------------- CAS DT/OE WE SE Operation mode --------------------------------------------- L X X X CBR refresh --------------------------------------------- H L L L Write transfer --------------------------------------------- H L L H Pseudo transfer --------------------------------------------- H L H X Read transfer --------------------------------------------- H H L X Read/mask write --------------------------------------------- H H H X Read/write --------------------------------------------- Note: X : Don't care. CAS (input pin): Column address is fetched into chip at the falling edge of CAS. CAS controls output impedance of I/O in RAM. A0-A8 (input pins): Row address is determined by A0-A8 level at the falling edge of RAS. Column address is determined by A0-A8 level at the falling edge of CAS. In transfer cycles, row address is the address on the word line which transfers data with SAM data register, and column address is the SAM start address after transfer. WE (input pin): WE pin has two functions at the falling edge of RAS and after. When WE is low at the falling edge of RAS, the HM534251B turns to mask write mode. According to the I/O level at the time, write on each I/O can be masked. (WE level at the falling edge of RAS is don't care in read cycle.) When WE is high at the falling edge of RAS, a normal write cycle is executed. After that, WE switches read/write cycles as in a standard DRAM. In a transfer cycle, the direction of transfer is determined by WE level at the falling edge of RAS. When WE is low, data is transferred HM534251B Series from SAM to RAM (data is written into RAM), and when WE is high, data is transferred from RAM to SAM (data is read from RAM). I/O0 - I/O3 (input/output pins): I/O pins function as mask data at the falling edge of RAS (in mask write mode). Data is written only to high I/O pins. Data on low I/O pins are masked and internal data are retained. After that, they function as input/output pins as those of a standard DRAM. DT/OE (input pin): DT/OE pin functions as DT (data transfer) pin at the falling edge of RAS and as OE (output enable) pin after that. When DT is low at the falling edge of RAS, this cycle becomes a transfer cycle. When DT is high at the falling edge of RAS, RAM and SAM operate independently. SC (input pin): SC is a basic SAM clock. In a serial read cycle, data outputs from an SI/O pin synchronously with the rising edge of SC. In a serial write cycle, data on an SI/O pin at the rising edge of SC is fetched into the SAM data register. SE (input pin): SE pin activates SAM. When SE is high, SI/O is in the high impedance state in serial read cycle and data on SI/O is not fetched into the SAM data register in serial write cycle. SE can be used as a mask for serial write because internal pointer is incremented at the rising edge of SC. SI/O0-SI/O3 (input/output pins): SI/Os are input/output pins in SAM. Direction of input/output is determined by the previous transfer cycle. When it was a read transfer cycle, SI/O outputs data. When it was a pseudo transfer cycle or write transfer cycle, SI/O inputs data. Operation of HM534251B RAM Read Cycle (DT/OE high and CAS high at the falling edge of RAS) Row address is entered at the RAS falling edge and column address at the CAS falling edge to the device as in standard DRAM. Then, when WE is high and DT / OE is low while CAS is low, the selected address data outputs through I/O pin. At the falling edge of RAS, DT/OE and CAS become high to distinguish RAM read cycle from transfer cycle and CBR refresh cycle. Address access time (t AA ) and RAS to column address delay time (tRAD) specifications are added to enable highspeed page mode. 4 HM534251B Series RAM Write Cycle (Early Write, Delayed Write, Read-Modify-Write) (DT/OE high and CAS high at the falling edge of RAS) * Normal Mode Write Cycle ( WE high at the falling edge of RAS) When CAS and WE are set low after driving RAS low, a write cycle is executed and I/O data is written in the selected addresses. When all 4 I/Os are written, WE should be high at the falling edge of RAS to distinguish normal mode from mask write mode. If WE is set low before the CAS falling edge, this cycle becomes an early write cycle and I/O becomes in high impedance. Data is entered at the CAS falling edge. If WE is set low after the CAS falling edge, this cycle becomes a delalyed write cycle. Data is input at the WE falling. I/O does not become high impedance in this cycle, so data should be entered with OE in high. If WE is set low after tCWD (min) and tAWD (min) after the CAS falling edge, this cycle becomes a read-modify-write cycle and enables read/write at the same address in one cycle. In this cycle also, to avoid I/O contention, data should be input after reading data and driving OE high. * Mask Write Mode (WE low at the falling edge of RAS) If WE is set low at the falling edge of RAS, the cycle becomes a mask write mode cycle which writes only to selected I/O. Whether or not an I/O is written depends on I/O level (mask data) at the falling edge of RAS. Then the data is written in high I/O pins and masked in low ones and internal data is retained. This mask data is effective during the RAS cycle. So, in high-speed page mode cycle, the mask data is retained during the page access. High-Speed Page Mode Cycle (DT/OE high and CAS high at the falling edge of RAS) High-speed page mode cycle reads/writes the data of the same row address at high speed by toggling CAS while RAS is low. Its cycle time is one third of the random read/write cycle. Note that address access time (tAA), RAS to column address delay HM534251B Series time (tRAD), and access time from CAS precharge (tACP) are added. In one RAS cycle, 512-word memory cells of the same row address can be accessed. It is necessary to specify access frequency within tRASP max (100 s). Transfer Operation The HM534251B provides the read transfer cycle, pseudo transfer cycle and write transfer cycle as data transfer cycles. These transfer cycles are set by driving CAS high and DT/OE low at the falling edge of RAS. They have following functions: (1) Transfer data between row address and SAM data register (except for pseudo transfer cycle) Read transfer cycle: RAM to SAM Write transfer cycle: SAM to RAM (2) Determine SI/O state Read transfer cycle: SI/O output Pseudo transfer cycle and write transfer cycle: SI/O input (3) Determine first SAM address to access after transferring at column address (SAM start address). SAM start address must be determined by read transfer cycle or pseudo transfer cycle after power on, and determined for each transfer cycle. Read Transfer Cycle (CAS high, DT/OE low and WE high at the falling edge of RAS) This cycle becomes read transfer cycle by driving DT/OE low and WE high at the falling edge of RAS . The row address data (512 x 4-bit) determined by this cycle is transferred to SAM data register synchronously at the rising edge of DT/OE. After the rising edge of DT/OE, the new address data outputs from SAM start address determined by column address. In read transfer cycle, DT/OE must be risen to transfer data from RAM to SAM. This cycle can access SAM even during transfer (real time read transfer). In this case, the timing tSDD (min) specified between the last SAM access before transfer and DT/OE rising edge and tSDH (min) specified between the first SAM access and DT/OE rising edge must be satisfied. (See figure 1.). 5 HM534251B Series HM534251B Series RAS CAS Xi Address DT/OE Yj L t SDD t SDH SC Yj SI/O SAM Data before Transfer Yj + 1 SAM Data after Transfer Figure 1. Real Time Read Transfer When read transfer cycle is executed, SI/O becomes output state by first SAM access. Input must be set high impedance before tSZS (min) of the first SAM access to avoid data contention. Pseudo Transfer Cycle (CAS high, DT/OE low, WE low and SE high at the falling edge of RAS) Pseudo transfer cycle switches SI/O to input state and set SAM start address without data transfer to RAM. This cycle starts when CAS is high, DT/OE low, WE low and SE high at the falling edge of RAS. Data should be input to SI/O later than tSID (min) after RAS becomes low to avoid data contention. SAM access becomes enabled after tSRD (min) after RAS becomes high. In this cycle, SAM access is inhibited during RAS low, therefore, SC must not be risen. Write Transfer Cycle (CAS high, DT/OE low, WE low and SE low at the falling edge of RAS) Write transfer cycle can transfer a row of data input by serial write cycle to RAM. The row address of data transferred into RAM is determined by the address at the falling edge of RAS. The column address is specified as the first address for serial write after terminating this cycle. Also in this cycle, SAM access becomes enabled after tSRD (min) after RAS becomes high. SAM access is inhibited during RAS low. In this period, SC must not be risen. Data transferred to SAM by read transfer cycle can be written to other address of RAM by write transfer cycle. However, the address to write data must be the same MSB of row address (AX8) as that of the read transfer cycle. SAM Port Operation Serial Read Cycle SAM port is in read mode when the previous data transfer cycle is read transfer cycle. Access is synchronized with SC rising, and SAM data is output from SI/O. When SE is set high, SI/O becomes high impedance, and the internal pointer is incremented by the SC rising. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. 6 HM534251B Series Serial Write Cycle If previous data transfer cycle is pseudo transfer cycle or write transfer cycle, SAM port goes into write mode. In this cycle, SI/O data is fetched into data register at the SC rising edge like in the serial read cycle. If SE is high, SI/O data isn't fetched into data register. Internal pointer is incremented by the SC rising, so SE high can be used as mask data for SAM. After indicating the last address (address 511), the internal pointer indicates address 0 at the next access. Refresh RAM Refresh RAM, which is composed of dynamic circuits, requires refresh to retain data. Refresh is executed by accessing all 512 row addresses within 8 ms. There are three refresh cycles: (1) RAS-only refresh cycle, (2) CAS-before-RAS (CBR) refresh cycle, and (3) Hidden refresh cycle. Besides them, the cycles which activate RAS such as read/write cycles or transfer cycles can refresh the row address. Therefore, no refresh cycle is required when all row addresses are accessed within 8 ms. (1) HM534251B Series RAS-Only Refresh Cycle: RAS-only refresh cycle is executed by activating only RAS cycle with CAS fixed to high after inputting the row address (= refresh address) from external circuits. To distinguish this cycle from data transfer cycle, DT / OE must be high at the falling edge of RAS. (2) CBR Refresh Cycle: CBR refresh cycle is set by activating CAS before RAS. In this cycle, refresh address need not to be input through external circuits because it is input through an internal refresh counter. In this cycle, output is in high impedance and power dissipation is lowered because CAS circuits don't operate. (3) Hidden Refresh Cycle: Hidden refresh cycle executes CBR refresh with the data output by reactivating RAS when DT/OE and CAS keep low in normal RAM read cycles. SAM Refresh SAM parts (data register, shift register and selector), organized as fully static circuitry, require no refresh. Absolute Maximum Ratings Item Symbol Rating Unit ----------------------------------------------------------------------------------------------- Terminal voltage*1 VT -1.0 to +7.0 V ----------------------------------------------------------------------------------------------- Power supply voltage*1 VCC -0.5 to +7.0 V ----------------------------------------------------------------------------------------------- Short circuit output current Iout 50 mA ----------------------------------------------------------------------------------------------- Power dissipation PT 1.0 W ----------------------------------------------------------------------------------------------- Operating temperature Topr 0 to +70 C ----------------------------------------------------------------------------------------------- Storage temperature Tstg -55 to +125 C ----------------------------------------------------------------------------------------------- Note: 1. Relative to VSS. 7 HM534251B Series HM534251B Series Recommended DC Operating Conditions (Ta = 0 to +70C) Item Symbol Min Typ Max Unit ----------------------------------------------------------------------------------------------- Supply voltage*1 VCC 4.5 5.0 5.5 V ----------------------------------------------------------------------------------------------- Input high voltage*1 VIH 2.4 -- 6.5 V ----------------------------------------------------------------------------------------------- Input low voltage*1 VIL -0.5*2 -- 0.8 V ----------------------------------------------------------------------------------------------- Notes: 1. All voltages referenced to VSS. 2. -3.0 V for pulse width < 10 ns. DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM534251B -------------------------------------- -6 -7 -8 -10 Test conditions -------- -------- -------- -------- ------------------------------ Item Symbol Min Max Min Max Min Max Min Max Unit RAM port SAM port ----------------------------------------------------------------------------------------------- Operating ICC1 -- 75 -- 70 -- 60 -- 55 mA RAS, CAS SC = VIL, SE = VIH current ---------------------------------------------------- cycling ------------------ ICC7 -- 125 -- 120 -- 100 -- 95 mA tRC = min SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- Standby ICC2 -- 7 -- 7 -- 7 -- 7 mA RAS, CAS SC = VIL, SE = VIH current ---------------------------------------------------- = VIH ------------------ ICC8 -- 50 -- 50 -- 40 -- 40 mA SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- RAS-only ICC3 -- 75 -- 70 -- 60 -- 55 mA RAS cycling SC = VIL, SE = VIH refresh ---------------------------------------------------- CAS = VIH ------------------ current ICC9 -- 125 -- 120 -- 100 -- 95 mA tRC = min SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- Page mode ICC4 -- 80 -- 80 -- 70 -- 65 mA CAS cycling SC = VIL, SE = VIH current ---------------------------------------------------- RAS = VIL ------------------ ICC10 -- 130 -- 130 -- 110 -- 105 mA tPC = min SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- CAS-before- ICC5 -- 50 -- 45 -- 40 -- 35 mA RAS cycling SC = VIL, SE = VIH RAS refresh ---------------------------------------------------- tRC = min ------------------ current ICC11 -- 100 -- 95 -- 80 -- 75 mA SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- Data ICC6 -- 80 -- 75 -- 65 -- 60 mA RAS, CAS SC = VIL, SE = VIH transfer ---------------------------------------------------- cycling ------------------ current ICC12 -- 130 -- 125 -- 105 -- 100 mA tRC = min SE = VIL, SC cycling tSCC = min ----------------------------------------------------------------------------------------------- 8 HM534251B Series HM534251B Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) (cont) HM534251B -------------------------------------- -6 -7 -8 -10 Test conditions -------- -------- -------- -------- ------------------------------ Item Symbol Min Max Min Max Min Max Min Max Unit RAM port SAM port ----------------------------------------------------------------------------------------------- Input leakage ILI -10 10 -10 10 -10 10 -10 10 A current ----------------------------------------------------------------------------------------------- Output leakageILO -10 10 -10 10 -10 10 -10 10 A current ----------------------------------------------------------------------------------------------- Output high VOH 2.4 -- 2.4 -- 2.4 -- 2.4 -- V IOH = -2 mA voltage ----------------------------------------------------------------------------------------------- Output low VOL -- 0.4 -- 0.4 -- 0.4 -- 0.4 V IOL = 4.2 mA voltage ----------------------------------------------------------------------------------------------- Note: 1. ICC depends on output loading condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once while RAS is low and CAS is high. Capacitance (Ta = 25C, VCC = 5 V, f = 1 MHz, Bias: Clock, I/O = VCC, address = VSS) Item Symbol Min Typ Max Unit ----------------------------------------------------------------------------------------------- Address CI1 -- -- 5 pF ----------------------------------------------------------------------------------------------- Clock CI2 -- -- 5 pF ----------------------------------------------------------------------------------------------- I/O, SI/O CI/O -- -- 7 pF ----------------------------------------------------------------------------------------------- AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) *1, *16 Test Conditions * Input rise and fall time: 5 ns * Output load: See figures * Input pulse levels : VSS to 3.0 V I OH = - 2 mA * Input timing reference levels: 0.8 V, 2.4 V * Output timing reference levels: 0.8 V, 2.0 V +5V I OH = - 2 mA I OL = 4.2 mA I OL = 4.2 mA I/O Note: *1 100 pF Output Load (A) 1. Including scope & jig. +5V SI / O *1 50 pF Output Load (B) 9 HM534251B Series HM534251B Series Common Parameter HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- Random read or write cycle time tRC 125 -- 135 -- 150 -- 180 -- ns ----------------------------------------------------------------------------------------------- RAS precharge time tRP 55 -- 55 -- 60 -- 70 -- ns ----------------------------------------------------------------------------------------------- RAS pulse width tRAS 60 10000 70 10000 80 10000 100 10000 ns ----------------------------------------------------------------------------------------------- CAS pulse width tCAS 20 -- 20 -- 20 -- 25 -- ns ----------------------------------------------------------------------------------------------- Row address setup time tASR 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Row address hold time tRAH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- Column address setup time tASC 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Column address hold time tCAH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- 2 RAS to CAS delay time tRCD 20 40 20 50 20 60 20 75 ns ----------------------------------------------------------------------------------------------- RAS hold time referenced to CAS tRSH 20 -- 20 -- 20 -- 25 -- ns ----------------------------------------------------------------------------------------------- CAS hold time referenced to RAS tCSH 60 -- 70 -- 80 -- 100 -- ns ----------------------------------------------------------------------------------------------- CAS to RAS precharge time tCRP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 3 Transition time (rise to fall) tT 3 50 3 50 3 50 3 50 ns ----------------------------------------------------------------------------------------------- Refresh period tREF -- 8 -- 8 -- 8 -- 8 ms ----------------------------------------------------------------------------------------------- DT to RAS setup time tDTS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- DT to RAS hold time tDTH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 4 Data-in to CAS delay time tDZC 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 4 Data-in to OE delay time tDZO 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 5 Output buffer turn-off delay tOFF1 -- 20 -- 20 -- 20 -- 20 ns referenced to CAS ----------------------------------------------------------------------------------------------- 5 Output buffer turn-off delay tOFF2 -- 20 -- 20 -- 20 -- 20 ns referenced to OE ----------------------------------------------------------------------------------------------- 10 HM534251B Series HM534251B Series Read Cycle (RAM), Page Mode Read Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- 6, 7 Access time from RAS tRAC -- 60 -- 70 -- 80 -- 100 ns ----------------------------------------------------------------------------------------------- 7, 8 Access time from CAS tCAC -- 20 -- 20 -- 20 -- 25 ns ----------------------------------------------------------------------------------------------- 7 Access time from OE tOAC -- 20 -- 20 -- 20 -- 25 ns ----------------------------------------------------------------------------------------------- 7, 9 Address access time tAA -- 35 -- 35 -- 40 -- 45 ns ----------------------------------------------------------------------------------------------- Read command setup time tRCS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 10 Read command hold time tRCH 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 10 Read command hold time tRRH 10 -- 10 -- 10 -- 10 -- ns referenced to RAS ----------------------------------------------------------------------------------------------- 2 RAS to column address delay time tRAD 15 25 15 35 15 40 15 55 ns ----------------------------------------------------------------------------------------------- Column address to RAS lead time tRAL 35 -- 35 -- 40 -- 45 -- ns ----------------------------------------------------------------------------------------------- Column address to CAS lead time tCAL 35 -- 35 -- 40 -- 45 -- ns ----------------------------------------------------------------------------------------------- Page mode cycle time tPC 45 -- 45 -- 50 -- 55 -- ns ----------------------------------------------------------------------------------------------- CAS precharge time tCP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- Access time from CAS precharge tACP -- 40 -- 40 -- 45 -- 50 ns ----------------------------------------------------------------------------------------------- Page mode RAS pulse width tRASP 60 100000 70 100000 80 100000 100 100000 ns ----------------------------------------------------------------------------------------------- 11 HM534251B Series HM534251B Series Write Cycle (RAM), Page Mode Write Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- 11 Write command setup time tWCS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write command hold time tWCH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Write command pulse width tWP 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Write command to RAS lead time tRWL 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- Write command to CAS lead time tCWL 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- 12 Data-in setup time tDS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 12 Data-in hold time tDH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- WE to RAS setup time tWS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- WE to RAS hold time tWH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- Mask data to RAS setup time tMS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Mask data to RAS hold time tMH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- OE hold time referenced to WE tOEH 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- Page mode cycle time tPC 45 -- 45 -- 50 -- 55 -- ns ----------------------------------------------------------------------------------------------- CAS precharge time tCP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 13 CAS to data-in delay time tCDD 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- Page mode RAS pulse width tRASP 60 100000 70 100000 80 100000 100 100000 ns ----------------------------------------------------------------------------------------------- 12 HM534251B Series HM534251B Series Read-Modify-Write Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- Read-modify-write cycle time tRWC 175 -- 185 -- 200 -- 230 -- ns ----------------------------------------------------------------------------------------------- RAS pulse width tRWS 110 10000 120 10000 130 10000 150 10000 ns (read-modify-write cycle) ----------------------------------------------------------------------------------------------- 14 CAS to WE delay time tCWD 45 -- 45 -- 45 -- 50 -- ns ----------------------------------------------------------------------------------------------- 14 Column address to WE delay time tAWD 60 -- 60 -- 65 -- 70 -- ns ----------------------------------------------------------------------------------------------- 12 OE to data-in delay time tODD 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- 6, 7 Access time from RAS tRAC -- 60 -- 70 -- 80 -- 100 ns ----------------------------------------------------------------------------------------------- 7, 8 Access time form CAS tCAC -- 20 -- 20 -- 20 -- 25 ns ----------------------------------------------------------------------------------------------- 7 Access time from OE tOAC -- 20 -- 20 -- 20 -- 25 ns ----------------------------------------------------------------------------------------------- 7, 9 Address access time tAA -- 35 -- 35 -- 40 -- 45 ns ----------------------------------------------------------------------------------------------- RAS to column address delay time tRAD 15 25 15 35 15 40 15 55 ns ----------------------------------------------------------------------------------------------- Read command setup time tRCS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Write command to RAS lead time tRWL 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- Write command to CAS lead time tCWL 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- Write command pulse width tWP 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- 12 Data-in setup time tDS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- 12 Data-in hold time tDH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- OE hold time referenced to WE tOEH 20 -- 20 -- 20 -- 20 -- ns ----------------------------------------------------------------------------------------------- 13 HM534251B Series HM534251B Series Refresh Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- CAS setup time tCSR 10 -- 10 -- 10 -- 10 -- ns (CAS-before-RAS refresh) ----------------------------------------------------------------------------------------------- CAS hold time tCHR 10 -- 10 -- 10 -- 10 -- ns (CAS-before-RAS refresh) ----------------------------------------------------------------------------------------------- RAS precharge to CAS hold time tRPC 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- Read Transfer Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- DT hold time referenced to RAS tRDH 50 10000 60 10000 65 10000 80 10000 ns ----------------------------------------------------------------------------------------------- DT hold time referenced to CAS tCDH 20 -- 20 -- 20 -- 25 -- ns ----------------------------------------------------------------------------------------------- DT hold time referenced to tADH 25 -- 25 -- 30 -- 30 -- ns column address ----------------------------------------------------------------------------------------------- DT precharge time tDTP 20 -- 20 -- 20 -- 30 -- ns ----------------------------------------------------------------------------------------------- DT to RAS delay time tDRD 65 -- 65 -- 70 -- 80 -- ns ----------------------------------------------------------------------------------------------- SC to RAS setup time tSRS 25 -- 25 -- 30 -- 30 -- ns ----------------------------------------------------------------------------------------------- 1st SC to RAS hold time tSRH 60 -- 70 -- 80 -- 100 -- ns ----------------------------------------------------------------------------------------------- 1st SC to CAS hold time tSCH 25 -- 25 -- 25 -- 25 -- ns ----------------------------------------------------------------------------------------------- 1st SC to column address hold time tSAH 40 -- 40 -- 45 -- 50 -- ns ----------------------------------------------------------------------------------------------- Last SC to DT delay time tSDD 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- 1st SC to DT hold time tSDH 10 -- 10 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Serial data-in to 1st SC delay time tSZS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Serial clock cycle time tSCC 25 -- 25 -- 30 -- 30 -- ns ----------------------------------------------------------------------------------------------- SC pulse width tSC 5 -- 5 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- SC precharge time tSCP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 14 HM534251B Series HM534251B Series Read Transfer Cycle (cont) HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- 15 SC access time tSCA -- 20 -- 22 -- 25 -- 25 ns ----------------------------------------------------------------------------------------------- Serial data-out hold time tSOH 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Serial data-in setup time tSIS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Serial data-in hold time tSIH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- RAS to column address delay time tRAD 15 25 15 35 15 40 15 55 ns ----------------------------------------------------------------------------------------------- Column address to RAS lead time tRAL 35 -- 35 -- 40 -- 45 -- ns ----------------------------------------------------------------------------------------------- DT high hold time from RAS precharge tDTHH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- Pseudo Transfer Cycle, Write Transfer Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- SE setup time referenced to RAS tES 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- SE hold time referenced to RAS tEH 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- SC setup time referenced to RAS tSRS 25 -- 25 -- 30 -- 30 -- ns ----------------------------------------------------------------------------------------------- RAS to SC delay time tSRD 20 -- 20 -- 25 -- 25 -- ns ----------------------------------------------------------------------------------------------- Serial output buffer turn-off time tSRZ 10 40 10 40 10 45 10 50 ns referenced to RAS ----------------------------------------------------------------------------------------------- RAS to serial data-in delay time tSID 40 -- 40 -- 45 -- 50 -- ns ----------------------------------------------------------------------------------------------- Serial clock cycle time tSCC 25 -- 25 -- 30 -- 30 -- ns ----------------------------------------------------------------------------------------------- SC pulse width tSC 5 -- 5 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- SC precharge time tSCP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 15 SC access time tSCA -- 20 -- 22 -- 25 -- 25 ns ----------------------------------------------------------------------------------------------- 15 HM534251B Series HM534251B Series Pseudo Transfer Cycle, Write Transfer Cycle (cont) HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- 15 SE access time tSEA -- 20 -- 22 -- 25 -- 25 ns ----------------------------------------------------------------------------------------------- Serial data-out hold time tSOH 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Serial write enable setup time tSWS 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Serial data-in setup time tSIS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Serial data-in hold time tSIH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Serial Read Cycle, Serial Write Cycle HM534251B ---------------------------------------- -6 -7 -8 -10 -------- -------- -------- -------- Item Symbol Min Max Min Max Min Max Min Max Unit Notes ----------------------------------------------------------------------------------------------- Serial clock cycle time tSCC 25 -- 25 -- 30 -- 30 -- ns ----------------------------------------------------------------------------------------------- SC pulse width tSC 5 -- 5 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- SC precharge width tSCP 10 -- 10 -- 10 -- 10 -- ns ----------------------------------------------------------------------------------------------- 15 Access time from SC tSCA -- 20 -- 22 -- 25 -- 25 ns ----------------------------------------------------------------------------------------------- 15 Access time from SE tSEA -- 20 -- 22 -- 25 -- 25 ns ----------------------------------------------------------------------------------------------- Serial data-out hold time tSOH 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- 5 Serial output buffer turn-off tSEZ -- 20 -- 20 -- 20 -- 20 ns time referenced to SE ----------------------------------------------------------------------------------------------- Serial data-in setup time tSIS 0 -- 0 -- 0 -- 0 -- ns ----------------------------------------------------------------------------------------------- Serial data-in hold time tSIH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Serial write enable setup time tSWS 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Serial write enable hold time tSWH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- Serial write disable setup time tSWIS 5 -- 5 -- 5 -- 5 -- ns ----------------------------------------------------------------------------------------------- Serial write disable hold time tSWIH 15 -- 15 -- 15 -- 15 -- ns ----------------------------------------------------------------------------------------------- 16 HM534251B Series Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. HM534251B Series AC measurements assume tT = 5 ns. When tRCD > tRCD (max) or tRAD > tRAD (max), access time is specified by tCAC or tAA. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition time tT is measured between VIH and VIL. Data input must be floating before output buffer is turned on. In read cycle, read-modify-write cycle and delayed write cycle, either tDZC (min) or tDZO (min) must be satisfied. tOFF1 (max), tOFF2 (max) and tSEZ (max) are defined as the time at which the output acheives the open circuit condition (VOH -100 mV, VOL +100 mV). Assume that tRCD < tRCD (max) and tRAD < tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. When tRCD > tRCD (max) and tRAD < tRAD (max), access time is specified by tCAC. When tRCD < tRCD (max) and tRAD > tRAD (max), access time is specified by tAA. If either tRCH of tRRH is satisfied, operation is guaranteed. When tWCS > tWCS (min), the cycle is an early write cycle, and I/O pins remain in an open circuit (high impedance) condition. These parameters are specified by the later falling edge of CAS or WE. Either tCDD (min) or tODD (min) must be satisfied because output buffer must be turned off by CAS or OE prior to applying data to the device when output buffer is on. When tAWD > tAWD (min) and tCWD > tCWD (min) in read-modify-write cycle, the data of the selected address outputs to an I/O pin and input data is written into the selected address. tODD (min) must be satisfied because output buffer must be turned off by OE prior to applying data to the device. Measured with a load circuit equivalent to 2 TTL loads and 50 pF. After power-up, pause for 100 s or more and execute at least 8 initialization cycle (normal memory cycle or refresh cycle), then start operation. 17 HM534251B Series HM534251B Series Timing Waveforms *17 Read Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t CAS t RCD CAS t RAD t ASR t RAL t RAH t ASC Row Address t CAL t CAH Column t RCS WE t RRH t RCH t CAC t AA t CDD t OFF1 t RAC I/O (Output) Valid Dout t OAC t DZC I/O (Input) t OFF2 t DZO t DTS t DTH DT/OE Note17: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) Invalid Dout Early Write Cycle t RC t RAS t RP RAS t CRP t CSH t RCD CAS Address t ASR t WS I/O (Input) t ASC t CAH Column t WH t WCS t WCH *1 WE I/O (Output) t RAH Row t RSH t CAS High-Z t MS t MH Mask Data t DTS t DTH t DS t DH Valid Din DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 18 HM534251B Series HM534251B Series Delayed Write Cycle t RC t RAS t RP RAS CAS t CAS t ASR t RAH Address t CAH Columun t RWL t WH t CWL t WP *1 WE I/O (Input) t ASC Row t WS I/O (Output) t CRP t CSH t RSH t RCD t MS t MH t DS t DZC Mask Data t DTH t DTS t DH Valid Din t OEH t OFF2 t ODD DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. Read-Modify-Write Cycle t RWC t RP t RWS RAS t CRP t RCD CAS t RAD t ASR Address Row t WS I/O (Input) t ASC t CAH Columun t WH t AWD t CWD t RCS t RWL t CWL t WP t CAC t AA *1 WE I/O (Output) t RAH t RAC Valid Dout t MS t MH t DZC Mask Data t DTS t DTH t DZO t OAC t OFF2 t ODD t DS t DH Valid Din t OEH DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 19 HM534251B Series HM534251B Series Page Mode Read Cycle t RC t RASP RAS t CSH t RCD t CAS CAS t RAD t ASR Address Row Columun t RCS WE t PC t CAS t ASC Columun t AA t ACP t CAC I/O (Input) t RRH t RCH t RCS t RCH t AA t ACP t CAC t OFF1 Valid Dout Valid Dout t CDD t OAC t OFF2 t DZC t CAL t CAH t ASC Columun t RCS t RCH t CRP t RAL t CAL t CAH t RAC t OFF1 t AA t CAC I/O (Output) t RSH t CAS t CP t CP t CAL t CAH t RAH t ASC t RP t DZC t OAC t OFF1 Valid Dout t CDD t OFF2 t DZC t OAC t CDD t DZO t DTH t DTS DT/OE Page Mode Write Cycle (Early Write) t RC t RP t RASP RAS t PC t CSH t RCD CAS Address t ASR t RAH t ASC t CP t CAS t CAH t ASC Row Column t WS t WH t WCS t WCH WE I/O (Output) t CAS t RSH t CAS t CP t CAH t ASC t CRP t CAH Column Column t WCS t WCH t WCS t WCH *1 High-Z t MS I/O (Input) t MH t DS Mask Data t DTS t DH Valid Din t DS t DH Valid Din t DS t DH Valid Din t DTH DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. 20 HM534251B Series HM534251B Series Page Mode Write Cycle (Delayed Write) t RC t RASP t RP RAS t CSH t PC t RCD CAS t ASR t RAH t ASC Address t ASC t ASC t CAH Column t CRP t CAH Column t RWL t CWL t CWL t WH t RSH t CAS t CP t CAS t WP t CWL t WP t WP *1 WE I/O (Output) t CAH Column Row t WS t CP t CAS t MS I/O (Input) t MH t DS Mask Data t DH Valid Din t DS t DH t DS Valid Din t DH Valid Din t OEH t DTS DT/OE Note: 1. This cycle becomes a normal mode write cycle when WE is high and a mask write cycle when WE is low. RAS-Only Refresh Cycle t RC t RP t RAS RAS t RPC t CRP CAS t ASR t RAH Row Address t OFF1 I/O (Output) t CDD I/O (Input) t OFF2 t ODD t DTS t DTH DT/OE 21 HM534251B Series HM534251B Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC t CP t RP t RAS t RPC t CSR t CHR t CSR Inhibit Falling Transition CAS Address WE t OFF1 I/O (Output) High-Z DT/OE Hidden Refresh Cycle t RC t RAS t RC t RP t RAS t RP RAS t RCD CAS t ASR Address t RSH t CHR t CRP t RAD t RAL t RAH t ASC t CAH Row Column t RCS t RRH t CAC WE t AA t RAC I/O (Output) t OFF1 Valid Dout t DZC I/O (Input) t DTS t OAC t OFF2 t DZO t DTH DT/OE 22 HM534251B Series HM534251B Series Read Transfer Cycle (1) t RC t RP t RAS RAS t CRP t CSH t RCD t RSH t CAS CAS t RAD t RAH t ASR Address Row t WS t RAL t ASC t CAH SAM Start Address t WH WE t DTHH High-Z I/O (Output) t CDH t DTS t DRD t ADH t RDH t DTP DT/OE t SCC t SCC t SDD SC SI/O (Output) t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCA t SOH Valid Sout t SCC t SDH t SC t SCA t SOH Valid Sout Previous Row t SCC t SCP t SOH Valid Sout New Row SI/O (Input) 23 HM534251B Series HM534251B Series Read Transfer Cycle (2) t RC t RAS t RP RAS t CSH t CRP t RCD t RSH t CAS CAS t ASR Address t RAD t RAH t CAH Sam Start Address Row t WS t RAL t ASC t WH WE t DTHH High-Z I/O (Output) t DTS t DRD t DTP t DTH DT/OE t SCH t SAH t SRS t SDH t SC t SCP t SIS t SIH t SCA t SCA t SRH SI/O (Input) t SCP Inhibit Rising Transition SC SI/O (Output) t SCC t SC t SOH t SZS Valid Sout Valid Sin 24 HM534251B Series HM534251B Series Pseudo Transfer Cycle t RC t RAS t RP RAS t CSH t CRP t RSH t RCD t CAS CAS t RAH t ASR t WS t CAH SAM Start Address Row Address t ASC t WH WE High - Z I/O (Output) t DTS t DTH DT/OE t ES t SEZ t EH t SWS SE t SRS t SRD t SCP t SC t SCA t SOH Valid Sout t SRZ Valid Sout t SID SI/O (Input) t SCP Inhibit Rising Transition SC SI/O (Output) t SCC t SC t SIS t SIH Valid Sin t SIS t SIH Valid Sin 25 HM534251B Series HM534251B Series Write Transfer Cycle t RC t RAS t RP RAS t CRP t CSH t RSH t RCD t CAS CAS t RAH t ASR Row Address t WS t WH t DTS t DTH t ASC t CAH SAM Start Address WE High-Z I/O (Output) DT/OE t ES t EH t SWS SE t SRS t SRD t SWS t SC SC SI/O (Output) SI/O (Input) t SCP t SCC t SC t SCP Inhibit Rising Transition t SIS t SIH Valid Sin t SIS t SIH Valid Sin t SIS t SIH Valid Sin 26 HM534251B Series HM534251B Series Serial Read Cycle SE tSCC SC SI/O (Output) tSCC tSC tSCP tSC tSCA tSOH tSCP tSC tSC tSCA tSOH tSEA tSEZ Valid Sout tSCC tSCP tSCA Valid Sout Valid Sout Valid Sout Serial Write Cycle tSWIS tSWH tSWIH tSWS SE tSCC tSC tSCP SC tSIS SI/O (Input) tSIH Valid Sin tSCC tSC tSCC tSC tSCP tSIS tSC tSCP tSIH Valid Sin tSIS tSIH Valid Sin 27