EFR32MG12 Gecko Multi-Protocol

Wireless SoC Family Data Sheet

The Gecko multi-protocol family of SoCs is part of the Wireless

Gecko portfolio. Gecko SoCs are ideal for enabling energy-friendly

multi-protocol, multi-band networking for IoT devices.

The single-die solution provides industry-leading energy efficiency, ultra-fast wakeup

times, a scalable power amplifier, and no-compromise MCU features.

Gecko applications include:

KEY FEATURES

Low-Energy Sensor Interface & Multi-

channel Capacitive Sense Interface

• Autonomous Hardware Crypto Accelerator

and True Random Number Generator

• Integrated PA with up to 19 dBm (2.4

GHz) or 20 dBm (Sub-GHz) TX power

• Integrated balun for 2.4 GHz

• Robust peripheral set and up to 65 GPIO

• IoT Multi-Protocol Devices

• Connected Home

Counter and

32-bit bus

Peripheral Reflex System

Low Energy

General

Purpose I/O

Pin Reset

EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active

Clock Management

Capacitive Sense

Sensor Interface Op-Amp

Radio Transceiver

The EFR32MG12 highlighted features are listed below.

• 256 kB RAM data memory

• 2.4 GHz and Sub-GHz radio operation

• Transmit power:

• 2.4 GHz radio: Up to 19 dBm

• Sub-GHz radio: Up to 20 dBm

• 11 mA RX current at 250 kbps, DSSS-OQPSK, 2.4 GHz

• 10.0 mA RX current at 1 Mbps, GFSK, 2.4 GHz

• 8.4 mA RX current at 38.4 kbps, GFSK, 169 MHz

• 8.5 mA TX current at 0 dBm output power at 2.4 GHz

• -91.3 dBm sensitivity at 2 Mbit/s GFSK, 2.4 GHz

• -102.7 dBm sensitivity at 250 kbps DSSS-OQPSK, 2.4 GHz

• -126.2 dBm sensitivity at 600 bps, GFSK, 915 MHz

• -120.6 dBm sensitivity at 2.4 kbps, GFSK, 868 MHz

• -107.4 dBm sensitivity at 4.8 kbps, OOK, 433 MHz

• -112.2 dBm sensitivity at 38.4 kbps, GFSK, 169 MHz

• 2/4 (G)FSK with fully configurable shaping

• BPSK / DBPSK TX

• OOK / ASK

Sub-GHz @ 20 dBm 1024 256 46 QFN68 -40 to +85°C

Sub-GHz @ 20 dBm 1024 256 31 QFN48 -40 to +85°C

EFR32MG12P332F1024GL125-C Bluetooth LE

2.4 GHz @ 10 dBm 1024 256 65 BGA125 -40 to +85°C

EFR32MG12P232F1024GL125-C Bluetooth LE

2.4 GHz @ 19 dBm 1024 128 65 BGA125 -40 to +85°C

EFR32MG12P232F1024GM68-C Bluetooth LE

2.4 GHz @ 19 dBm 1024 128 46 QFN68 -40 to +85°C

Sub-GHz @ 20 dBm 1024 128 31 QFN48 -40 to +85°C

EFR32MG12P132F1024GL125-C Bluetooth LE

2.4 GHz @ 10 dBm 1024 128 65 BGA125 -40 to +85°C

EFR32MG12P132F512GM68-C Bluetooth LE

2.4 GHz @ 10 dBm 512 64 46 QFN68 -40 to +85°C

Pin Count

Package – M (QFN), L (BGA)

Flash Memory Size in kB

Feature Set Code – r2r1r0

r2: Reserved

r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)

r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)

Sub-GHz RF

Capacitive

Port K

Port J

Port I

Port B

Port A

Mux & FB

DC-DC

Management

Serial Wire

3.2 Radio

The Gecko family features a highly configurable radio transceiver supporting a wide range of wireless protocols, including Zigbee,

3.7.5 Low Energy Sensor Interface (LESENSE)

available in energy mode EM2, in addition to EM0 and EM1, making it ideal for sensor monitoring in applications with a strict energy

3.8 Security Features

3.8.1 General Purpose Cyclic Redundancy Check (GPCRC)

The GPCRC block implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The suppor-

ted 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the

needs of the application.

3.8.2 Crypto Accelerator (CRYPTO)

The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-

port AES encryption and decryption with 128- or 256-bit keys, ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and

3.8.3 True Random Number Generator (TRNG)

The TRNG is a non-deterministic random number generator based on a full hardware solution. The TRNG is validated with NIST800-22

and AIS-31 test suites as well as being suitable for FIPS 140-2 certification (for the purposes of cryptographic key generation).

Note: TRNG operation is only supported at VSCALE2. TRNG cannot be used at VSCALE0.

3.8.4 Security Management Unit (SMU)

The Security Management Unit (SMU) allows software to set up fine-grained security for peripheral access, which is not possible in the

Memory Protection Unit (MPU). Peripherals may be secured by hardware on an individual basis, such that only priveleged accesses to

the peripheral's register interface will be allowed. When an access fault occurs, the SMU reports the specific peripheral involved and

can optionally generate an interrupt.

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption

is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The

ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the

programmable threshold.

3.9.3 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 Msps. The output

sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple samples.

The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide range of

3.9.4 Capacitive Sense (CSEN)

The CSEN peripheral is a dedicated Capacitive Sensing block for implementing touch-sensitive user interface elements such a

switches and sliders. The CSEN peripheral uses a charge ramping measurement technique, which provides robust sensing even in

or scan through multiple pins and store results to memory through DMA. Several channels can also be shorted together to measure the

combined capacitance or implement wake-on-touch from very low energy modes. Hardware includes a digital accumulator and an aver-

aging filter, as well as digital threshold comparators to reduce software overhead.

ksps, 12-bit converter. The opamps are used in conjunction with the VDAC, to provide output buffering. One opamp is used per single-

ended channel, or two opamps are used to provide differential outputs. The VDAC may be used for a number of different applications

such as sensor interfaces or sound output. The VDAC can generate high-resolution analog signals while the MCU is operating at low

frequencies and with low total power consumption. Using DMA and a timer, the VDAC can be used to generate waveforms without any

CPU intervention. The VDAC is available in all energy modes down to and including EM3.

3.9.7 Operational Amplifiers

The opamps are low power amplifiers with a high degree of flexibility targeting a wide variety of standard opamp application areas, and

are available down to EM3. With flexible built-in programming for gain and interconnection they can be configured to support multiple

common opamp functions. All pins are also available externally for filter configurations. Each opamp has a rail to rail input and a rail to

rail output. They can be used in conjunction with the VDAC peripheral or in stand-alone configurations. The opamps save energy, PCB

The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:

• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz

• Memory Protection Unit (MPU) supporting up to 8 memory segments

• Up to 1024 kB flash program memory

• Up to 256 kB RAM data memory

• Configuration and event handling of all peripherals

• 2-pin Serial-Wire debug interface

3.11.2 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable

from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code

is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a

The Linked Direct Memory Access (LDMA) controller allows the system to perform memory operations independently of software. This

3.12 Memory Map

The EFR32MG12 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.

Figure 3.2. EFR32MG12 Memory Map — Core Peripherals and Code Space

3.13 Configuration Summary

The features of the EFR32MG12 are a subset of the feature set described in the device reference manual. The table below describes

device specific implementation of the features. Remaining modules support full configuration.

Table 3.2. Configuration Summary

US3_TX, US3_RX, US3_CLK, US3_CS

TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]

WTIMER0 with DTI WTIM0_CC[2:0], WTIM0_CDTI[2:0]

• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.

• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-

er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.

4.1.1 Absolute Maximum Ratings

Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of

the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-

Voltage on any supply pin VDDMAX -0.3 — 3.8 V

Voltage ramp rate on any

supply pin

DC voltage on any GPIO pin VDIGPIN 5V tolerant GPIO pins1 2 3-0.3 — Min of 5.25

Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V

Input RF level on pins

2G4RF_IOP and

Absolute voltage on Sub-

GHz RF pins

Total current into VDD power

Total current into VSS

ground lines

Current per I/O pin IIOMAX Sink — — 50 mA

1. When a GPIO pin is routed to the analog block through the APORT, the maximum voltage = IOVDD.

2. Valid for IOVDD in valid operating range or when IOVDD is undriven (high-Z). If IOVDD is connected to a low-impedance source

3. To operate above the IOVDD supply rail, over-voltage tolerance must be enabled according to the GPIO_Px_OVTDIS register.

4.1.2 Operating Conditions

When assigning supply sources, the following requirements must be observed:

• VREGVDD must be greater than or equal to AVDD, DVDD, RFVDD, PAVDD and all IOVDD supplies.

• VREGVDD = AVDD

• DVDD ≤ AVDD

4.1.5.2 Current Consumption 3.3 V using DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC

output. T = 25 °C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode1

mode with all peripherals dis-

abled, DCDC in Low Noise

CCM mode3

abled and voltage scaling

enabled, DCDC in Low

Noise CCM mode3

Current consumption in EM1

mode with all peripherals dis-

abled, DCDC in Low Noise

DCM mode1

Noise DCM mode1

enabled, DCDC in LP mode4

Current consumption in EM3

mode, with voltage scaling

Current consumption in

4.1.5.3 Current Consumption 1.8 V without DC-DC Converter

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 1.8 V. T = 25 °C. DCDC is off.

Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

mode with all peripherals dis-

mode with all peripherals dis-

abled and voltage scaling

2. CMU_LFRCOCTRL_ENVREF = 1, CMU_LFRCOCTRL_VREFUPDATE = 1

4.1.5.4 Current Consumption Using Radio 3.3 V with DC-DC

Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V. T = 25

°C. Minimum and maximum values in this table represent the worst conditions across process variation at T = 25 °C.

ceive mode, active packet

reception (MCU in EM1 @

4.1.6 Wake Up Times

Table 4.9. Wake Up Times

Wake up from EM4S1tEM4S_WU Executing from flash — 291 — µs

Time from release of reset

source to first instruction ex-

Power mode scaling time tSCALE VSCALE0 to VSCALE2, HFCLK =

4.1.7 Brown Out Detector (BOD)

DVDD BOD hysteresis VDVDDBOD_HYST — 18 — mV

DVDD BOD response time tDVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs

AVDD BOD threshold VAVDDBOD AVDD rising — — 1.8 V

AVDD BOD hysteresis VAVDDBOD_HYST — 20 — mV

AVDD BOD response time tAVDDBOD_DELAY Supply drops at 0.1V/µs rate — 2.4 — µs

EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V