ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
PRELIMINARY
UM017001-0404
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Modular Development Kit
User Manual
PRELIMINARY UM017001-0404
ii
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126
Telephone: 408.558.8500
Fax: 408.558.8300
www.zilog.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the compa n ie s with which they are asso ciated.
©2004 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REP RESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Safeguards
iii
Safeguards
The following precautions must be observed when working with the
devices described in this document.
Always use a grounding strap to prevent damage resulting from
electrostatic discharge (ESD).
Caution:
eZ80F91 Modular Development Kit
User Manual
PRELIMINARY UM017001-0404
iv
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Table of Contents
v
Table of Contents
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Kit Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
eZ80F91 Modular Development Kit Overview . . . . . . . . . . . . . . . . . . . .3
eZ80Acclaim! MDS Adapter Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
eZ80F91 Mini Enet Module Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .5
eZ80Acclaim! MDS Adapter Board Jumper Settings . . . . . . . . . . . . . .20
eZ80F91 Mini Enet Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fast Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
eZ80F91 Mini Enet Module Memory . . . . . . . . . . . . . . . . . . . . . . . 2 4
External Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Reset Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
IrDA Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Internal On-Chip Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Flash Loader Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
ZDS II. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
IrDA Port Not Working . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contacting ZiLOG Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . .31
eZ80F91 Modular Development Kit
User Manual
PRELIMINARY UM017001-0404
vi
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
eZ80Acclaim! MDS Adapter Board Schematic . . . . . . . . . . . . . . . 33
eZ80F91 Mini Enet Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Customer Feedback Form. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY List of Figures
vii
List of Figures
Figure 1. eZ80Acclaim! MDS Adapter Board Block Diagram . . . . . .3
Figure 2. eZ80F91 Mini Enet Module Block Diagram . . . . . . . . . . . .4
Figure 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Mini-Module Connector J1 Pin Configuration
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Figure 4. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2 . . . . . . . . . . . . . . . . . . . . . .10
Figure 5. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1 . . . . . . . . . . . . . . .14
Figure 6. eZ80Acclaim! MDS Adapter Board
I/O External Connector JP2 . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 7. Possible Bus Contention without Fast Buffer . . . . . . . . . . .23
Figure 8. eZ80Acclaim MDS Adapter Board Schematic (1 of 2) . . .33
Figure 9. eZ80Acclaim! MDS Adapter Board Schematic (2 of 2) . . .34
Figure 10. eZ80F91 Mini Enet Module Schematic (1 of 2) . . . . . . . . .35
Figure 11. eZ80F91 Mini Enet Module Schematic (2 of 2) . . . . . . . . .36
eZ80F91 Modular Development Kit
User Manual
PRELIMINARY UM017001-0404
viii
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY List of Tables
ix
List of Tables
Table 1. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Connector J1 Identification. . . . . . . . . . . . . . 7
Table 2. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2 Identification . . . . . . . . . . 1 1
Table 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1 Identification . . . .15
Table 4. eZ80Acclaim! MDS Adapter Board
I/O External Connector JP21 Identification . . . . . . . . . . . .19
Table 5. eZ80Acclaim MDS Adapter Board
Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 6. Shunt JP1, eZ80F91 Mini Enet Module . . . . . . . . . . . . . . .28
eZ80F91 Modular Development Kit
User Manual
PRELIMINARY UM017001-0404
x
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Introduction
1
Introduction
The eZ80F91 Modular Development Kit provides a general-purpose plat-
form for creating a design based on ZiLOG’s eZ80F91 microcontroller.
The eZ80F91 is a memb e r of ZiLOG’s eZ80Acclaim!™ product family,
which offers on-chip Flash capability. The eZ80F91 Modular Develop-
ment Kit features an eZ80F91 Mini Enet Module and an eZ80Acclaim!
MDS Adapter Board onto which the module mounts.
Kit Features
The key features of the eZ80F91 Modular Development Kit are:
•
eZ80F91 Mini Enet Module:
– eZ80F91 device operating at 50 MHz, with 256 KB of internal
Flash memory and 8 KB of internal SRAM memory.
– 128 KB of off-chip SRAM memory.
– On-chip Ethernet Media Access Controller (EMAC).
– Ethernet port and PHY.
– Real-Time Clock with battery backup.
– Footprint for an SIR IrDA transceiver.
– Two 56-pin mini-module connectors for attachment to the
eZ80Acclaim! MDS adapter board.
•
eZ80Acclaim! MDS Adapter Board:
– Footprint for 2M x 8 external Flash memory such as
AM29LV160D.
– Footprint for 10-bit bus switch such as 74CBTLV3384 to su pport
external Flash.
– RS232 connector with interface circuit for UART0.
– ZDI and JTAG debug connectors.
eZ80F91 Modular Development Kit
User Manual
Kit Features PRELIMINARY UM017001-0404
2
– Two 56-pin mini-module connectors.
– Two 60-pin interface connectors for connection to an external
application or development board (not supplied).
– 32-pin header and footprint for a GPRS modem.
– One green 3.3 OK LED.
– One yellow Test LED and pushbutton.
– 5VDC external power supply.
•
Serial Smart Cable
•
eZ80Acclaim!™ Software and Documentation CD-ROM
•
ZiLOG ZTP TCP/IP stack CD-ROM
•
Schematics for the eZ80F91 Mini Enet Module and eZ80Acclaim!
MDS adapter boar d.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Introduction
3
eZ80F91 Modular Development Kit Overview
The purpose of the eZ80F91 Modular Development Kit is to provide the
design engineer with a set of tools for designing an application based on
the eZ80F91 microcontroller.
A block diagram of the eZ80Acclaim! MDS adapter board is shown in
Figure 1.
Figure 1. eZ80Acclaim! MDS Adapter Board Block Diagram
Flash Memory
(not installed)
External 60-pin Headers (two)
External 60-pin Headers (two)
Power Supply
RS232
ZDI
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Modular Development Kit OverviewPRELIMINARY UM017001-0404
4
Figure 2 provides a block d i agram of the eZ80F91 Mini Enet Module.
Figure 2. eZ80F91 Mini Enet Module Block Diagram
Schematics for the eZ80F91 Mini Enet Module and eZ80Acclaim! MDS
adapter board are provided in the Schematics section starting on page 33.
Ethernet PHY
128KB SRAM
56-Pin Connector J1
SIR IrDA
(not installed)
eZ80F91
EMAC
F91 Bus
MII F91 Bus consists of 24 bits of
address, 8 bits of data, 32 bits
of GPIO and control signals.
56-Pin Connector J2
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
5
eZ80Acclaim! MDS Adapter Board
This section describes functions of the eZ80Acclaim! MDS adapter
board.
eZ80F91 Mini Enet Module Interface
The eZ80F91 Mini Enet Module interface on the eZ80Acclaim! MDS
adapter board consists of two 56-pin mini-module receptacles.
Almost all of these receptacles’ signals are connected directly to the CPU.
Three input signals offer opt ions to the application developer by disabling
certain functions of the eZ80F91 Mini Enet Module.
These three input signals are:
•
Disable IrDA (DIS_IrDA) (used only if you have installed an external
SIR IrDA transceiver onto the eZ80F91 Mini Enet Module)
•
F91_WE
•
RTC_VDD
A description of these three signals follows.
Disable IrDA. When the DIS_IrDA input signal is pulled Low, the IrDA
transceiver located on the eZ80F91 Mini Enet Module is disabled. As a
result, UART0 can be used with the RS232 or the RS485 interfaces on the
eZ80® Development Platform.
F91_WE. When the F91_WE signal is active Low, internal Flash on the
eZ80F91 chip is enabled for writing. This signal is inverted from the
F91_WP signal on the eZ80F91 chip.
RTC_VDD. RTC_VDD is a test point for the Real Time Clock power sup-
ply.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
6
Peripheral Bus Mini-Module Connector, J1
Figure 3 illustrates the pin layout of the 56-pin Peripheral Bus Mini-Mod-
ule Connector, J1, on the eZ80Acclaim! MDS adapter board. Table 1
identifies the pins and their functions.
Figure 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Mini-Module Connector J1 Pin Configuration
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
7
Table 1. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Connector J1 Identification1,2
Pin # Symbol Signal Direction Active Level eZ80F91 Signal Note
3 A6 Bidirectional n/a Yes
4 A0 Bidirectional n/a Yes
5 A7 Bidirectional n/a Yes
6 A2 Bidirectional n/a Yes
7 A8 Bidirectional n/a Yes
8 A1 Bidirectional n/a Yes
9 A102 Bidirectional n/a Yes
10 A3 Bidirectional n/a Yes
13 RD Output Low Yes
14 D5 Bidirectional n/a Yes
15 D1 Bidirectional n/a Yes
16 D4 Bidirectional n/a Yes
17 D0 Bidirectional n/a Yes
18 D2 Bidirectional n/a Yes
19 A17 Bidirectional n/a Yes
20 D6 Bidirectional n/a Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80Acclaim! MDS adapter board sche-
matics on pages 33 through 34.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23
should be below 10 pF to satisfy the timi ng requirements for the eZ80 CPU. All unused inputs
should be pulled to either V
DD
or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be
deactivated via software in the eZ80F91’s Peripheral Power-Down Register.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
8
23 A19 Bidirectional n/a Yes
24 A18 Bidirectional n/a Yes
25 A21 Bidirectional n/a Yes
26 A20 Bidirectional n/a Yes
27 A23 Bidirectional n/a Yes
28 CS0 Output Low Yes
29 CS3 Output Low Yes
33 F91_WE Input Low No Jumper on board
34 CS0 Output Low Yes
35 D3 Bidirectional n/a Yes
36 RTC_V
DD
Input n/a Yes
39 D7 Bidirectional n/a Yes
40 HALT_SLP Output Low Yes
41 A13 Bidirectional n/a Yes
42 WR Ouput Low Yes
43 A12 Bidirectional n/a Yes
Table 1. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Connector J1 Identification 1,2 (Continued)
Pin # Symbol Signal Direction Active Level eZ80F91 Signal Note
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80Acclaim! MDS adapter board sche-
matics on pages 33 through 34.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23
should be below 10 pF to satisfy the timing requirements for the eZ80 CPU. All unused inputs
should be pulled to either V
DD
or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be
deactivated via software in the eZ80F91’s Peripheral Power-Down Register.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
9
44 A11 Bidirectional n/a Yes
45 A14 Bidirectional n/a Yes
46 A9 Bidirectional n/a Yes
49 A16 Bidirectional n/a Yes
50 A5 Bidirectional n/a Yes
51 A15 Bidirectional n/a Yes
52 A4 Bidirectional n/a Yes
Table 1. eZ80Acclaim! MDS Adapter Board
Peripheral Bus Connector J1 Identification 1,2 (Continued)
Pin # Symbol Signal Direction Active Level eZ80F91 Signal Note
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80Acclaim! MDS adapter board sche-
matics on pages 33 through 34.
2. Additional note: external capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23
should be below 10 pF to satisfy the timi ng requirements for the eZ80 CPU. All unused inputs
should be pulled to either V
DD
or GND, depending on their inactive levels to reduce power
consumption and to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be
deactivated via software in the eZ80F91’s Peripheral Power-Down Register.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
10
I/O Mini-Module Connector, J2
Figure 4 illustrates the pin layout of the 56-pin Peripheral Bus Mini-
Module Connector , J1, on the eZ80Acclaim! MDS adapter board. Table 2
identifies the pins and their functions.
Figure 4. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
11
Table 2. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
1 PA3 Bidirectional n/a Yes
2 PA4 Bidirectional n/a Yes
3 PA7 Bidirectional n/a Yes
4 PA5 Bidirectional n/a Yes
5 PB5 Bidirectional n/a Yes
6 PA0 Bidirectional n/a Yes
7 PB6 Bidirectional n/a Yes
8 PA1 Bidirectional n/a Yes
10 EZ80CLK Output n/a Yes
11 PB1 Bidirectional n/a Yes
12 PB7 Bidirectional n/a Yes
13 PC4 Bidirectional n/a Yes
14 PB3 Bidirectional n/a Yes
15 PA6 Bidirectional n/a Yes
16 PC7 Bidirectional n/a Yes
17 PB4 Bidirectional n/a Yes
18 PA2 Bidirectional n/a Yes
21 PB3 Bidirectional n/a Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground
nets are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
12
22 PB0 Bidirectional n/a Yes
23 PC6 Bidirectional n/a Yes
24 PC5 Bidirectional n/a Yes
25 PC3 Bidirectional n/a Yes
26 PC1 Bidirectional n/a Yes
27 PC2 Bidirectional n/a Yes
28 PC0 Bidirectional n/a Yes
31 TMS Input n/a Yes
32 PD7 Bidirectional n/a Yes
33 PD6 Bidirectional n/a Yes
34 PD5 Bidirectional n/a Yes
35 PD3 Bidirectional n/a Yes
36 PD4 Bidirectional n/a Yes
37 TRSTN Input Low Yes
38 TRIGOUT Output n/a Yes
41 TCK Input n/a Yes
42 PD1 Bidirectional n/a Yes
43 TDI Bidirectional n/a Yes
Table 2. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground
nets are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
13
44 PD0 Bidirectional n/a Yes
45 PD2 Bidirectional n/a Yes
46 TDO Output n/a Yes
49 DIS_IRDA Input Low No
50 IICSCL I/O n/a Yes
51 WAIT Input Low Yes
52 IICSDA I/O n/a Yes
53 RST I/O Low Yes
54 NMI Input Low Yes
Table 2. eZ80Acclaim! MDS Adapter Board
I/O Mini-Module Connector J2 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground
nets are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
14
Peripheral Bus External Connector JP1
Figure 5 illustrates the pin layout of Peripheral Bus External Connector
JP2 in the 60-pin header on the eZ80Acclaim! MDS adapter board.
Table 3 identifies the pins and their functions.
Figure 5. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
15
Table 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
1-4, 6, 8,
35 unused n/a n/a n/a
5TRSTN
Input Low Yes
11 A6 Bidirectional n/a Yes
12 A0 Bidirectional n/a Yes
13 A10 Bidirectional n/a Yes
14 A3 Bidirectional n/a Yes
17 A8 Bidirectional n/a Yes
18 A7 Bidirectional n/a Yes
19 A13 Bidirectional n/a Yes
20 A9 Bidirectional n/a Yes
21 A15 Bidirectional n/a Yes
22 A14 Bidirectional n/a Yes
23 A18 Bidirectional n/a Yes
24 A16 Bidirectional n/a Yes
25 A19 Bidirectional n/a Yes
27 A2 Bidirectional n/a Yes
28 A1 Bidirectional n/a Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets
are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
16
29 A11 Bidirectional n/a Yes
30 A12 Bidirectional n/a Yes
31 A4 Bidirectional n/a Yes
32 A20 Bidirectional n/a Yes
33 A5 Bidirectional n/a Yes
34 A17 Bidirectional n/a Yes
36 DIS_FLASH Input Low No
37 A21 Bidirectional n/a Yes
39 A22 Bidirectional n/a Yes
40 A23 Bidirectional n/a Yes
41 CS0 Output Low Yes
42 CS1 Output Low Yes
43 CS2 Output Low Yes
44-49 D[0:5] Bidirectional n/a Yes
51 D7 Bidirectional n/a Yes
52 D6 Bidirectional n/a Yes
53 MREQ Output Low Yes
54 IOREQ Output Low Yes
Table 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets
are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
17
56 RD Ouput Low Yes
57 WR Output Low Yes
58 INSTRD Output Low Yes
59 BUSACK Output Low Yes
60 BUSREQ Input Low Yes
Table 3. eZ80Acclaim! MDS Adapter Board
Peripheral Bus External Connector JP1 Identification1
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets
are omitted from this table. The entire interface is represented in the
eZ80Acclaim! MDS adapter board schematics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini Enet Module Interface PRELIMINARY UM017001-0404
18
I/O External Connector JP2
Figure 6 illustrates the pin layout of the I/O Connector in the 60-pin
header on the eZ80Acclaim! MDS adapter board. Table 4 identifies the
pins and their functions.
Figure 6. eZ80Acclaim! MDS Adapter Board
I/O External Connector JP2
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
19
Table 4. eZ80Acclaim! MDS Adapter Board
I/O External Connector JP21 Identification
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
1 - 8 PA7 to PA0 Bidirectional n/a Yes
11 - 18 PB7 to PB0 Bidirectional n/a Yes
20 - 27 PC7 to PC0 Bidirectional n/a Yes
28, 29 PD7, PD6 Bidirectional n/a Yes
31 - 36 PD5 to PD0 Bidirectional n/a Yes
37 TDO Output n/a Yes
38 TDI I/O n/a Yes
40 TRIGOUT Output n/a Yes
41 TCK Input n/a Yes
42 TMS Input n/a Yes
43 RTC_V
DD
Input n/a Yes
44 EZ80CLK Output n/a Yes
45 IICSCL I/O n/a Yes
47 IICSDA I/O n/a Yes
49 FLASHWE Input Low No
51 CS3 Output Low Yes
52 DIS_IRDA Input Low No
53 RST I/O Low Yes
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80Acclaim! MDS adapter board schemat-
ics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
eZ80Acclaim! MDS Adapter Board Jumper SettingsPRELIMINARY UM017001-0404
20
eZ80Acclaim! MDS Adapter Board Jumper Settings
The eZ80Acclaim! MDS adapter board contains four jumpers that are
described in Table 5.
54 WAIT Input Low Yes
57 HALT_SLP Output Low Yes
58 NMI Input Low Yes
60 unused n/a n/a n/a
Table 4. eZ80Acclaim! MDS Adapter Board
I/O External Connector JP21 Identification (Continued)
Pin # Symbol Signal Direction Active Level eZ80F91 Signal2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80Acclaim! MDS adapter board schemat-
ics on pages 33 through 34.
2. The Power and Ground nets are connected directly to the eZ80F91 device.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80Acclaim! MDS Adapter Board
21
Table 5. eZ80Acclaim MDS Adapter Board
Jumper Settings
Jumper Name Position Function Affected Device
J4, FL_EN IN (Default) On-board Flash is enabled On- board Flash
(when installed)
OUT On-board Flash is disabled
J6, FL_WEN1IN On-board Flash is disabled
for writing. On-board Flash
(when installed)
OUT On-board Flash is enabled
for writing
J8, RS232-1 DIS IN RS232 output on connector
P2 is disabled DB9 connec to r
P2
OUT RS232 output on connector
P2 is enabled
J9, IRDA_DIS2IN (Defau lt) IrDA transceiver on
eZ80F91 Mini Enet Module
is disabled
IrDA transceiver
(when installed)
OUT IrDA transceiver on
eZ80F91 Mini Enet Module
is enabled
Notes:
1. If AM29LV160 is used, J6 and R6 should be OUT. If AT49BV162 is used, R6
should be IN, and J6 should be OUT.
2. Jumper J9 functions only when user has installed IrDA transceiver on eZ80F91
Mini Enet Module.
eZ80F91 Modular Development Kit
User Manual
eZ80F91 Mini En et Module PRELIMINARY UM017001-0404
22
eZ80F91 Mini Enet Module
This section describes the eZ80F91 Mini Enet Module hardware, its inter-
faces and key components, including the CPU, real-time clock, and mem-
ory.
Functional Description
The eZ80F91 Mini Enet Module is a compact, high-performance module
specially designed for the rapid development and deployment of embed-
ded systems.
Despite its small footprint, the eZ80F91 Mini Enet Module provides a
CPU, Flash memory, Ethernet interface, SRAM, and a real-time clock.
This module is powered by the eZ80F91 microcontroller, a member of
ZILOG’s eZ80Acclaim!™ product family.
Fast Buffer
A Fast Buffer is located on the data bus to Flash memory. The pur pose o f
this Fast Buffer is to avoid bus contention that can exist due to the slow
turn-off time of Flash memory and the fast bus turn-around time of the
eZ80F91 device (a generic feature of the eZ80Acclaim!™ family when is
used in native mode). The discussion that follows references Figure 7.
Bus contention can occur when two or more devices drive a common bus.
CS0 on the eZ80F91 device drives the Flash CE. Upon accessing Flash
memory, CS0 is driven High a maximum of 8.8 ns after the next rising
edge of the CPU Clock (T6—please refer to the External Memory Read
Timing diagram in the eZ80F91 Product Specification (PS0192) for assis-
tance). The Flash turn-off time (TOD) is 25 ns—the duration from OE or
CE going High to Flash output drivers in a high-impedance state. For fur-
ther information, see the MT28F008 data sheet on www.micron.com.
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80F91 Mini Enet Module
23
Essentially, after the eZ80F91 device accesses Flash memory, a time
duration of 8.8 ns + 25 ns = 33.8 ns can transpire before Flash mem ory
stops driving the data bus. At that time, the eZ80F91 device is well into
the next bus cycle. Assuming this next cycle is the Memory Write cycle,
then the data output of the eZ80F91 device is valid not later than
T3 = 7.5 ns, and the write pulse is asserted not later than 4.5 ns after the
falling edge of the CPU Clock (14.5 ns from the rising edge if the CPU
Clock is 50 MHz). The duration of bus contention, TCON, is 33.8 ns –
7.5 ns = 26.3 ns. Refer to the External Memory Write Timing diagram in
the eZ80F91 Product Specification (PS0192) for assi stance.
Figure 7. Possible Bus Contention without Fast Buffer
T6
T3
T4
T
Data In Data Out
OD
Bus Contention
CPU Clock
CS0
CS1
eZ80F91 Data Bus
Flash Data Bus
RD
WR
eZ80F91 Modular Development Kit
User Manual
Operational Description PRELIM INARY UM017001-0404
24
With the addition of a Fast buffer, Flash turn-off time is reduced from
25 ns to 5.5 ns. Bus contention can still occur, but the amount of time it
consumes is not TCON = 26.3 ns but rather T CON = (8.8 ns – 7.5 ns + 5.5 ns)
= 6.8 ns. At this faster rate, data that is being written does not become cor-
rupted because the write pulse is not yet asserted.
As of the date of publication of this document, ZiLOG has not completed
an analysis of the effect that this 6.8 ns period of bus contention has on the
design. An Application Note from Cypress Semiconductor titled NoBL
SRAM and Bus Contention further explains this bus contention issue.
Operational Description
The purpose of the eZ80F91 Mini Enet Module as a feature of the
eZ80F91 Modular Development Kit is to provide application developers
with a design platform that enables them to make use of such eZ80F91
device features of the as on-chip EMAC, SRAM, Flash, etc.
eZ80F91 Mini Enet Module Memory
Static RAM
The eZ80F91 Mini Enet Module features 128 KB of fast SRAM. Access
speed is typically 12 ns, allowing zero-wait-state operation at 50 MHz.
With the CPU at 50 MHz, SRAM can be accessed with zero wait states in
eZ80 mode. CS1_CTL (CS1) can be set to 08h (no wait states).
The eZ80F91 Mini Enet Module is shipped with SRAM po wered from
the same power supply as the eZ80F91 device. The SRAM may also be
powered separately by battery. To power SRAM from battery:
1. Remove R15
2. Ensure that R14 is in place.
3. Connect battery (-) to GND.
4. Connect battery (+) to J10.
Note:
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80F91 Mini Enet Module
25
Flash Memory
The eZ80F91 Mini Enet Module features 256 KB of on-chip Flash mem-
ory, which can be programmed a single byte at a time, or in bursts of up to
256 bytes. Write operations can be pe rformed using either memory or I/O
instructions. Erasing bytes in Flash memory returns them to a value of
FFh. Both the MASS ERASE and PAGE ERASE operations are self-
timed by the Flash controller, leaving the CPU free to execute other oper-
ations in parallel. Upon power -up, the on-chi p Flash memory is located in
the address range 000000h–03FFFFh. Four wait states are programmed
in Flash control register F8h.
On-chip Flash memory is prioritized over all external Chip Selects, can be
enabled or disabled (power-on enabled), and can be programmed within
any 256 KB address space in the 16 MB address range.
The eZ80F91 Mini Enet Module features the following memory configu-
rations:
•
On-chip SRAM: 8 KB
•
Off-chip SRAM: 128 KB
•
On-chip Flash: 256 KB
Refer to the eZ80F91 Product Specification, PS0192, for details on pro-
gramming internal Flash memory.
External Flash Memory
The eZ80F91 Mini Enet Modu le provides a footprint for 2MB of external
Flash. The module supports additional external Flash devices via the full
system bus, which is available on the expansion interface connectors.
Reset Generator
A supervisory chip on the eZ80Acclaim! MDS adapter board is connected
to the eZ80F91 Reset input pin via pin 53 of mini-module connector J2..
It performs reliable Power-On Reset functions, generating a reset pulse
eZ80F91 Modular Development Kit
User Manual
Operational Description PRELIM INARY UM017001-0404
26
with a duration of 200 ms if the power supply drops below 2.93 V. This
reset pulse ensures that the board always starts in a defined condition. The
RESET pin on the I/O connector reflects the status of the RESET line. It
is a bidirectional pin for resetting external peripheral components or for
resetting the eZ80F91 Modular Development Kit with a low-impedance
output (e.g. a 100-Ohm push button).
IrDA Transceiver
The eZ80F91 Mini Enet Module is shipped without an IrDA transceiver
installed.
If you install an on-board transceiver, such as the ZiLOG ZHX1810, it is
connected to PD0 (TX), PD1 (RX), and PD2 (Shutdown, IR_SD). The
IrDA transceiver is of the LED type 870 nm Class 1.
The IrDA transceiver is accessible via the IrDA controller attached to
UART0 on the eZ80F91 device.
To use the UART0 as a console or to save power, the transceiver can be
disabled by the software or by an off-board signal when using the proper
jumper selection. The transceiver is disabled by setting PD2 (IRDA_SD)
High or by pulling the DIS_IRDA pin on the I/O connector Low. The
shutdown feature is used for power savings. To enable the IrDA trans-
ceiver, DIS_IRDA is left floating and PD2 is pulled Low.
The RxD and TxD signals on the transceiver perform the same functions
as a standard RS232 port. However, these signals are processed as IrDA
3/16 coding pulses (sometimes called IrDA encoder/decoder pulses).
When the IrDA function is enabled, the final output to the RxD and TxD
pins are routed through the 3/16 pulse generator.
Another signal that is used in the eZ80F91 Mini Enet Mod ule’s IrDA sys-
tem is Shut_Down (SD). The SD pin is connected to PD2 on the eZ80F91
Mini Enet Module. The IrDA control software on the user’s wireless
device must enable this pin to wake the IrDA transceiver. The SD pin
must be set Low to enable the IrDA transceiver. On the eZ80F91 Mini
Enet Module, a two-input OR gate is used to allow an external pin to shut
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY eZ80F91 Mini Enet Module
27
down the IrDA transceiver. Both pins must be set Low to enable this func-
tion.
The eZ80F91 Mini Enet Module features an Infrared Encoder/Decoder
register that configures the IrDA function. This register is located at
address 0BFh in the internal I/O register map.
The Infrared Encoder/Decoder register contains three control bits. Bit 0
enables or disables the IrDA encoder/decoder block. Bit 1, if it is set,
enables received data to pass into the UART0 Receive FIFO data buffer.
Bit 2 is a test function that provides a loopback sequence from the TxD
pin to the RxD input.
Bit 1, the Receive Enable bit, is used to block data from filling up the
Receive FIFO when the eZ80F91 Mini Enet Module is transmitting data.
Because IrDA signal passes through the air as its transmiss i on medium,
transmitted data can also be received. This Receive Enable bit prevents
this data from being received. After the eZ80F91 Mini Enet Module com-
pletes transmitting, this bit is changed to allow for incoming messages.
The code that follows provides an example of how this function is
enabled on the eZ80F91 Mini Enet Module.
//Init_IRDA
// Make sure to first set PD2 as a port bit, an output and set it Low.
PD_ALT1 &= 0xFC; // PD0 = uart0tx, PD1 = uart0_rx
PD_ALT2 |= 0x03; // Enable alternate function
UART_LCTL0= 0x80; // Select dlab to access baud rate generator
BRG_DLRL0=0x2F; // Baud rate Masterclock/(16*baudrate)
BRG_DLRH0=0x00; // High byte of baud rate
UART_LCTL0=0x00; // Disable dlab
UART_FCTL0=0xC7; // Clear tx fifo, enable fifo
UART_LCTL0=0x03; // 8bit, N, 1 stop
IR_CTL = 0x03; // enable IRDA Encode/decode and Receive
// enable bit.
eZ80F91 Modular Development Kit
User Manual
Internal On-Chip Flash Memory PRELIMINARY UM017001-0404
28
//IRDA_Xmit
IR_CTL = 0x01; //Disable receive
Putchar(0xb0); //Output a byte to the uart0 port.
Internal On-Chip Flash Memory
To program the 32K boot block on the internal on-chip Flash memory,
shunt JP1 on the eZ80F91 Mini Enet Module must be installed. Table 6
lists the settings shunt JP1.
Flash Loader Utility
The Flash Loader utility integrated within ZDS II allows the user a conve-
nient way to program on-chip Flash memory. Please refer to the ZiLOG
Developer Studio—eZ80Acclaim! User Manual (UM0144) for more
details.
Table 6. Shunt JP1, eZ80F91 Mini Enet Module
Symbol Jumper Name Shunt
Status Function Affected Devic e
JP1 F91_WE In (Default) On-chip Flash is enabled for
writing to boot block. On-chip Flash
Out On-chip Flash memory boot block
is write-protected. On-chip Flash
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY ZDS II
29
ZDS II
ZiLOG Developer Studio II (ZDS II) Integrated Development Environ-
ment is a complete stand-alone system that provides a state-of-the-art
development environment. Based on the Windows® Win98SE/NT4.0-
SP6/Win2000-SP2/WinXP user interfaces, ZDS II integrates a language-
sensitive editor , project manager , C-Compiler , assembler, linker , librarian,
and source-level symbolic debugger that supports the eZ80F91 device.
For more information on ZDS II, refer to the ZiLOG Developer Studio—
eZ80Acclaim!™ User Manual, UM0144.
eZ80F91 Modular Development Kit
User Manual
ZDS II PRELIMINARY UM017001-0404
30
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Troubleshooting
31
Troubleshooting
Overview
Before contacting ZiLOG Customer Support to submit a problem report,
please follow these simple steps. If a hardware failure is suspected, con-
tact a local ZiLOG representative for assistance.
IrDA Port Not Wo rking
If you plan on using the IrDA transceiver on the eZ80F91 Mini Enet
Module, make sure the hardware is set up as follows:
•
Jumper J9 on the eZ80Accaim! MDS adapter board must be OFF (to
enable the control gate that drives the IrDA device)
•
Set port pin PD2 Low. When this port pin and Jumper J9 are turned
OFF, the IrDA device is enabled.
•
Disable the RS232 output by installing a shunt on jumper J8 on the
eZ80Acclaim! MDS adapter board.
Contacting ZiLOG Customer Support
For additional troubleshooting solutions, see ZDS II Online Help.
For valuable information about hardware and software development tools,
visit ZiLOG Customer Support online. Download the latest released ver-
sion of ZiLOG Developer Studio!
Get the latest software updates from ZiLOG as soon as they are available!
eZ80F91 Modular Development Kit
User Manual
Contacting ZiLOG Customer Support PRELIMINARY UM017001-0404
32
UM017001-0404 PRELIMINARY Schematics
e
Z80F9
1
M
o
d
u
l
ar
D
eve
l
opmen
t
Kit
User Manual
33
Schematics
eZ80Acclaim! MDS Adapter Board Schematic
Figures 8 and 9 provide a schematic for the eZ80Acclaim! MDS adapter board.The SRAM chip U2 and buff er U1 are not instal led; they are shown
for reference purposes only.
Figure 8. eZ80Acclaim MDS Adapter Board Schematic (1 of 2)
GPRS MODEM
CONNECTOR
S
ZDI
INTERFACE
24
26
connector
2
connector
1
MINI MODULE CONNECT
ORS
RESET
JTAG
INTERFACE
TEST
TEST
DIS IRD
A
96C0945-001
eZ80 Acclaim! Pl
atform
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126
B
Title
Si
ze
Document Number
PC2_RTS1 PC2
PC0_TX
D1
PC0
VCC_33V
TDI
PC7_RI1
PC7
PC1_RXD1
PC1
PRSTn
PC3_CTS1 PC3
TDO
TM
S
GND
PC5_DSR1
PC5
PC4_DTR1
PC4
TCK
PC6_DCD1
PC6
PRSTn
TDI
TCK
GND
VCC_33V
GND
GND
-RD
GND
PC7
PD2
PB7
IICSCL
PB3
PD6
-HALT_SLP
-CS1
-WR
PA1
PC3
PD5
-FLASHWE
VCC_33V
A3
A1
D4
GND
D1
A20
-NMI
PB4
-CS3
GND
A23
-MREQ
A10
-TRSTN
PB2
PC5
PA6
PB1
VCC_33V
D3
A12
-BUSREQ
-F91_WE
-BUSACK
A4
A14
TCK
GND
PB0
PC0
D7
A19
A8
-IOREQ
D5
-DIS_FLASH
PB6
PA4
PC1
PB5
A15
VCC_33V
RTC_VDD
GND
PD3
-CS0
GND
PA7
A0
A17
-DIS_IRDA
PC2
-RST
D0
EZ80CLK
PA2
A18
VCC_33V
IICSDA
D6
PA5
TRIGOUT
TDO
A11
VCC_33V
D2
A7
PD4
A21
-INSTRD
PD0
PD7
A6
PA0
TDI
PC4
A5
A2
PD1
A9
A13
GND
-WAIT
A22
PA3
-CS2
GND
VCC_33V
GND
A16
PC6
TM
S
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
-RST
-RD
FLASH_EN
-WR
GND
F_D0
F_D1
F_D2
F_D3
F_D4
F_D5
F_D6
F_D7
VCC_33V
VCC_33V
GND
VCC_33V
GND
TVCC_RESETn
-RST
PB3
PB5
GND
GND
D2
D7
F_D0
GND
D6
F_D1
-CS3
VCC_33V
VCC_33V
GND
VCC_33V
F_D2
F_D5
VCC_33V
GND
D1
F_D3
GND
D0
GND
D4
GND
VCC_33V
F_D7
F_D4
GND
D3
D5
F_D6
FLASH_EN
VCC_33V
GND
-DIS_IRDA
A21
D1
D3
A21
A3
PA5
GND
GND
PB5
PC7
TRIGOUT
GND
PD1
VCC_33V
PC6
D6
GND
-RST
PD4
A17
A16
PD0
-WR
D4
PC3
A13
PA0
VCC_33V
PB1
A11
PA7
GND
VCC_SRAM
VCC_33V
-RD
A4
GND
A8
PA1
A7
GND
-CS3
-F91_WE
PC2
-WAIT
TCK
GND
GND
VCC_33V
PB6
-TRSTN
A20
A15
A0
VCC_33V
PD2
TDO
D0
IICSCL
GND
GND
A18
GND
A6
A10
PB7
PB3
PD5
-CS2
IICSDA
-DIS_IRDA
-CS0
A1
VCC_33V
A22
A14
GND
PA3
A5
A12
GND
GND
PC0
PB4
GND
PC1
PD6
PA2
PD7
A9
VCC_SRAM
D5
PD3
VCC_33V
GND
-HALT_SLP
PC4
EZ80CLK
TM
S
A2
RTC_VDD
PA4
D2
D7
PB2
A19
PB0
PC5
GND
PA6
TDI
-NMI
A23
VCC_SRAM
VCC_CUST
VCC_SRAM
-RST
VCC_5V
PB6
PD2PD3 PD0PD1
GND
J3
HEADER 32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
R3
330
J1
HEADER 28x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
C2
0.001uF
J12
HEADER 2
1
2
J2
HEADER 28x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
J11
HEADER 9
1
2
P1
12
34
56
78
9
10
11 12
13 14
C3
0.1uF
J5
Header 3x2
12
34
56
S2
1 2
R8
1K
U3A
TC74LVT
125
23
14
1
7
J10
HEADER 1
1
D1
LED YEL
21
R5
10K
R7
10K
J4
HEADER 2
1
2
R4
10K
U1
74CBTLV3384/SO
1
1213 24
2
5
6
9
10
16
15
19
20
23
3
4
7
8
11
14
17
18
21
22
1OE
GND
2OE
VCC
1B1
1B2
1B3
1B4
1B5
2B2
2B1
2B3
2B4
2B5
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
1N5817
CR1
21
R2
220
R1
10K
J6
HEADER 2
1
2
J9
HEADER 2
1
2
C1
0.001uF
U4A
TC74LVC08
1
2
3
147
R14
0
JP2
HEADER 30x2/SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
U2
Am29LV160D
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
12 15
28
26
11
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
10
13
14 37
27
46
47
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
RESET
RY/BY
OE
CE
WE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15/A-1
NC
NC
VPP
VCC
GND
GND
BYTE
S1
SW PUSHBUTTON
1 2
VL1
R6
10K
R15
0
JP1
HEADER 30x2/SM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
UM017001-0404 PRELIMINARY Schematics
e
Z80F9
1
M
o
d
u
l
ar
D
eve
l
opmen
t
Kit
User Manual
34
Figure 9. eZ80Acclaim! MDS Adapter Board Schematic (2 of 2)
RS232-1 DI
S
POWER SUPPLY
3.3 O
K
ZiLOG, Inc.
GND
GND
RxD0
RTS0
GND
VCC_33V
3.3V
5V
VCC_5V
VCC_33V
GND
VCC_33V
GND
GND
VCC_33V
TxD0
CTS0
GND
GND
GND
PD0
PD3
PD2
PB6
VCC_5V
VCC_33V
PD1
VCC_33V
J8
1
2
U4B
TC74LVC08
4
56
147
U8C
74LV05
56
C8
0.1uF
C9
0.1uF
U3B
TC74LVT
125
5 6
14
4
7
D2
GREEN
21
U8A
74LV05
12
147
U3D
TC74LVT
125
12 11
14
13
7
U8D
74LV05
98
U4D
TC74LVC08
12
13 11
147
U3C
TC74LVT
125
9 8
14
10
7
U5
LT1086-3.3/TO220
1
3 2
GND
VIN
VOUT
R13
10K
P2
DB9 FEMALE
5
9
4
8
3
7
2
6
1
R9
680
U8E
74LV05
1110
+
C5
22uF
R12
10K
C10
0.1uF
C12
0.1uF
J7
PWR JACK
2
3
1
+
C6
22/6.3
R11
10K
C4
0.1
C11
0.1uF
C7
0.1
U8B
74LV05
34
F1
RXE
160
R10
10K
U6
MAX3
222
1
2
4
5
6
13
12
15
10
3
7
17
8
16
9
20
1918
11
14
EN
C1+
C1-
C2+
C2-
T1IN
T2IN
R1OUT
R2OUT
V+
V-
T1OUT
T2OUT
R1IN
R2IN
SHDN
VCCGND
NC
NC
U8F
74LV05
1312
U4C
TC74LVC08
9
10
8
147
UM017001-0404 PRELIMINARY Schematics
e
Z80F9
1
M
o
d
u
l
ar
D
eve
l
opmen
t
it
User Manual
35
eZ80F91 Mini Enet Module
Figures 10 through 11 diagram the layout of the eZ80F91 Mini Enet Module. The IrDA device is not installed on the module; it appears for refer-
ence purposes only.
Figure 10. eZ80F91 Mini Enet Module Schematic (1 of 2)
connector 2connector 1
=
(MMA 02
04)
-F91_
WE
CONNECTO
RS
ZiLOG, Inc.
-RD
D[0..7]
A[0..23]
-WR
-RST
-NMI
-CS[0..3]
PB[0..7]
IICSDA
PC[0..7]
TCK
IICSCL
PD[0..7]
IICSDA
IICSCL
-DIS_IRDA
IR_SD
PD2
IRDA_SD
PD0
IRDA_SD
PD1
-F91_WP
PA[0..7]
TDI
-WAIT
A6
D7
-RD
A5
A12
A11
A13
D0
A15
A8
A7
-CS1
A16
A4
-WR
D1
D5
A9
A10
D4
D2
D3
D6
A14
TRIGOUT
TM
S
TD
O
-TRST
N
RTC_VDD
eZ80CLK
-HALT_SL
P
GND
GND
A1
A3
A0
A2
D4
A21
-HALT_SL
P
-CS0
A20
VCC_33V
PC7
PA4
IICSDA
TCK
PC6PC5
PB4
GND
GND
-RST
TM
S
PD6
-TRS
TN
PB1
-NMI
PC1
GND
PA1
PD4
TDI
PA2
PB7
PA7
TRIGOUT
VCC_33V
-DIS_IRDA
GND
PA6
PD7
PD5
-WAIT
PD0
PB0
PC0
PB6
PA0
GND
IICSCL
GND
PC3
PA5
PC4
PB3
PC2
PD1
PB2
PA3
PD2
VCC_33V
EZ80CLK
VCC_33V
GND
A14
A2
VCC_33V
VCC_33V
GND
A6
GND
A5
A8
A17
D7
GND
GND
A13
A3
VCC_33V
D5
-CS2
A4
D1
GND
D0
-WR
D3
VCC_33V
-F91_WE
VCC_33V
A19
GND
VCC_SRAMVCC_SRAM
RTC_VDD
A22
A0
GND
-F91_WE
VCC_SRAM
A10
-CS3
D2
A11
VCC_33V
GND
A18
A7
GND
A9
GND
A1
A15
A16
A23
A12
TDO
-RD
D6
GND
GND
GND
PB5
PD3
A[0:23]
D[0:7]
-CS[0:3]
IICSDA
IICSCL
PA[0:7]
-RST
-RD
-WR
PB[0:7]
PD[0:7]
PC[0:7]
-WAIT
-NMI
TDI
TCK
-F91_WP
VCC_33V
GND
TRIGOUT
TMS
TDO
-TRST
N
RTC_VDD
eZ80CLK
-HALT_SL
P
GND
VCC_33V
VCC_33v
VCC_33V
VCC_33V
J1
HEADER 28x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
R4
68R
R1
10K
R7
10K
U1A
SN74LVC2G04
1 7
4 8
C1
330nF
R11
10K
U4
SN74AHC1G32
1
24
53
J2
HEADER 28x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
U1C
SN74LVC2G04
6 2
JP1
HEADER 2
1
2
R5
2R7
R3
4.7K
C3
0.1uF
C2
0.001uF
R6
2.2K
R8
10K
U1B
SN74LVC2G04
3 5
R9
10K
R2
4.7K
U3
IDT71V124S/SO
5
19
28
20
18
17
29
12
31
9
1
2
3
4
13
14
15
16
21
30
32
6
7
10
11
22
23
26
27
25
8
24
CS
A10
OE
A11
A9
A8
A13
WE
A15
GND
A0
A1
A2
A3
A4
A5
A6
A7
A12
A14
A16
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
VCC
VCC
U2
ZHX181
0
2
4
3
1
5
6
0
TXD
SD
RXD
LEDA
VCC
GND
T
UM017001-0404 PRELIMINARY Schematics
e
Z80F9
1
M
o
d
u
l
ar
D
eve
l
opmen
t
it
User Manual
36
Figure 11. eZ80F91 Mini Enet Module Schematic (2 of 2)
Make sure that power
connections
and nets VDD_PLL and
VDDC have
the shortest route
possible
IN
T
CPU & P
HY
96C
0942-001
A
eZ80F91 Ethe
rnet Mini Module.
ZiLOG, Inc.
532 Race Street. San Jose,CA 95126. 408.558.8500
B
22
Friday, February 27, 2004
Title
Siz
e
Document Number
Re
v
Date:
Sheet
of
D0
D1
D2
D3
D5
D7
D4
D6
A6
A1
A3
A0
A2
A5
A7
A4
A14
A9
A11
A8
A10
A13
A15
A12
A22
A17
A19
A16
A18
A21
A23
A20
MDC
TXD2
TXD0
TXD3
TXD1
TX
ER
MDI0
TX
EN
PA1
PA6
PA4
PA7
PA5
PA2
PA0
PA3
PB1
PB6
PB4
PB7
PB5
PB2
PB0
PB3
PD1
PD6
PD4
PD7
PD5
PD2
PD0
PD3
TM
S
-WAIT
-BUSREQ
TCK
-NMI
-TRST
N
-RST
TDI
-F91_WP
CRS
RXD
0
RXER
RXD
3
COL
RXDV
RXD
1
RXCL
K
RXD
2
TXCL
K
FILT_IN
XIN
-CS1
-WR
-RD
-CS0
-CS2
-CS3
SCL
SDA
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
TX-
RX
+
RX
-
VCC_33V
VCC_33V
GND
-LEDLNK
-SPEED
VCC_33V
GND
VCC_33V
XO
UT_O
VCC_33V
VDDC
GND
GND
RXER
VDD_PLL
TX-
GND
TXD2
TX
ER
RXCL
K
RXD
3
GND
RX
+
COL
TXD3
MDC
GND
RX
-
TXCL
K
VDDC
RXDV
TXD1
TX
EN
VCC_33V
-RST
VCC_33V
TX+
CRS
TXD0
RXD
2
RXD
0
GND
RXD
1
GND
VCC_33V
GND
TX+
GND
GND
VCC_33V
-LEDLNK
GND
RTC_VDD
GND
-SPEED
VCC_33V
VDDC
GND
GND
VCC_33V
MDI0
VCC_33V
TRIGOUT
TD
O
eZ80CLK
-HALT_SL
P
PD[0:7]
PC[0:7]
PB[0:7]
PA[0:7]
IICSDA
IICSCL
-CS[0:3]
-WR
-RD
A[0:23]
D[0:7]
-WAIT
TM
S
TCK
TDI
-RST
-F91_WP
RTC_VDD
-NMI
VCC_33V
GND
-TRS
TN
GND
VCC_33V
C13
0.1uF
P1
HFJ11-2450E
1
4
2
3
5
6
8
9
10
12
11
TX+
TXCT
TX-
RX+
RXCT
RX-
GND
AN1
CT1
CT2
AN2
R12
10K
+
C10
10uF
C24
0.1uF
JP2
Header 1
1
C39
0.1uF
U6
eZ80F91_BGA
A1
B1
B2
C3
D4
E5
D2
D1
D3
F6
E1
E4
F1
F2
F3
F4
G1
F5
H1
H2
G4
H3
J1
G5
L2
K3
J4
M3
L3
H5
L4
M4
L6
M7
H7
L9
K9
L10
J6
K6
A2
M5
L5
K5
J5
J3
K1
K2
L1
A11
A12
B7
C7
D7
A6
B6
E7
A3
B3
D8
A7
D6
A4
E6
B4
D5
C4
C5
C6
J10
H11
H12
A5
B8
C1
C10
E2
E11
G2
H10
H9
J2
J11
K4
K7
B5
B12
C2
C8
D9
E3
G3
G6
G12
H4
H6
F9
J12
K8
M2
M11
A8
F7
C9
A9
B9
E8
B10
A10
C11
C12
D10
E9
D11
F8
D12
E10
E12
G8
F10
F11
F12
G9
G10
G11
H8
K11
K12
J9
K10
L11
L12
M12
M9
B11
M10
J8
L7
M6
J7
L8
M8
M1
G7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
WAIT
BUSREQ
TMS
TCK
TDI
TRSTN
NMI
RESET
WP
IORQ
MRQ
RD
WR
CS0
CS1
CS2
CS3
SCL
SDA
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
MII_TXER
MII_MDC
MII_MDIO
MII_CRS
MII_COL
MII_RXER
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
MII_RXCLK
MII_TXCLK
FILT_IN
XIN
XOUT
VDD
VDD
VDD
VDD
VDD
VDD
VDD
PLL_VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PA7_PWM3
PA6_PWM2_EC1
PA5_PWM1_TOUT1
PA4_PWM0_TOUT0
PA3_PWM3_OC3
PA2_PWM2_OC2
PA1_PWM1_OC1
PA0_PWM0_OC0
PB7_MOSI
PB6_MISO
PB5_ICB3
PB4_ICA2
PB3_SCK
PB2_SS
PB1_IC1
PB0_IC0_EC0
PC7_RI1
PC6_DCD1
PC5_DSR1
PC4_DTR1
PC3_CTS1
PC2_RTS1
PC1_RXD1
PC0_TXD1
PD7_RI0
PD6_DCD0
PD5_DSR0
PD4_DTR0
PD3_CTS0
PD2_RTS0
PD1_RXD0_IRRXD
PD0_TXD0_IRTXD
HALT_SLP
PHI
TDO
TRIGOUT
BUSACK
INSTRD
RTC_VDD
RTC_XOUT
RTC_XIN
VDD
PLL_VSS
C31
0.001uF
C5
22pF
R20
49.9
C11
0.056uF
C14
0.1uF
C27
0.001uF
C21
0.1uF
C40
0.1uF
C32
0.001uF
C16
0.1uF
FB1
Ferrite Bead
1 2
C6
22pF
R21
49.9
C12
270pF
C15
0.1uF
C25
0.001uF
C28
0.001uF
C41
0.1uF
R13
6.81K 1%
C22
18pF
C33
0.001uF
U5
KS8721B
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32
33
34
37
35
36
38
39
40
41
42
43
44
45
46
47
48
MDIO
MDC
RXD3/PHYAD1
RXD2/PHYAD2
RXD1/PHYAD3
RXD0/PHYAD4
VCC
GND
RXDV/PCS_LPBK
RXC
RXER/ISO
GND
VDDC
TXER
TXC/REFCLK
TXEN
TXD0
TXD1
TXD2
TXD3
COL/RMII
CRS/RMII_BTB
GND
VCC
INT/PHYADD0
LED0/TEST
LED1/SPD100/noFEF
LED2/DUPLEX
LED3/NWAYEN
PD
VDDRX
RX-
RX+
FXSD/FXEN
REXT
GND
GND
VDDRCV
GND
TX-
TX+
VDDTX
GND
GND
XO
XI
VDDPLL
RST
C17
0.1uF
C7
0.1uF
FB2
Ferrite Bead
1 2
Y3
32.768KHz
R22
49.9
R18
499
+
C20
47uF
C26
0.001uF
C29
0.001uF
R23
220
R19
33
R15
1K
C51
22pF
Y1
25 MHz
C18
0.001uF
+
C8
10uF
C9
0.1uF
C38
0.1uF
R25
49.9
R26
4.7K
+
C19
47uF
R16
1K
Y2
5MHz
C30
0.001uF
C23
18pF
R24
220
C52
22pF
eZ80F91 Modular Development Kit
User Manual
UM017001-0404 PRELIMINARY Customer Feedback Form
37
Customer Feedback Form
If you note any inaccuracies while reading this User Manual, please copy and complete this form,
then mail or fax it to ZiLOG (see Return Information, below). We also welcome your sugges-
tions!
Customer Informat io n
Return Information
ZiLOG
System Te st/Customer Support
532 Race Street
San Jose, CA 95126
Phone: (408) 558-8500
Fax: (408) 558-8536
ZiLOG Customer Support
Problem Description or Suggestion
Provide a complete description of th e problem or your suggestion. If you are reporting a specific
problem, include all steps leading up to the occurrence of the problem. Attach additional pages as
necessary.
eZ80F91 Modular De velopm e nt Kit
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Name Country
Company Phone
Address Fax
City/State/Zip E-Mail