LHF00L02 - Sharp Electronics Corp.

®

Integrated Circuits Group

LHF00L02

Flash Memory

8M (1MB × 8)

(Model No.: LHF00L02)

Spec No.: FM037004

Issue Date: June 18, 2003

PRODUCT SPECIFICATIONS

LHF00L02

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction,

full or in part, of this material is prohibited without the express written permission of the company.

• When using the products covered herein, please observe the conditions written herein and the precautions outlined in

the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly

adhere to these conditions and precautions.

(1) The products covered herein are designed and manufactured for the following application areas. When using the

products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure

to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph

(3).

• Office electronics

• Instrumentation and measuring equipment

• Machine tools

• Audiovisual equipment

• Home appliance

• Communication equipment other than for trunk lines

(2) Those contemplating using the products covered herein for the following equipment which demands high

reliability, should first contact a sales representative of the company and then accept responsibility for

incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring

reliability and safety of the equipment and the overall system.

• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment

• Mainframe computers

• Traffic control systems

• Gas leak detectors and automatic cutoff devices

• Rescue and security equipment

• Other safety devices and safety equipment, etc.

(3) Do not use the products covered herein for the following equipment which demands extremely high performance

in terms of functionality, reliability, or accuracy.

• Aerospace equipment

• Communications equipment for trunk lines

• Control equipment for the nuclear power industry

• Medical equipment related to life support, etc.

(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales

representative of the company.

• Please direct all queries regarding the products covered herein to a sales representative of the company.

Rev. 0.05

                                                                       LHF00L02                                                                  1
CONTENTS
PAGE
Product Description.................................................  4
Device Operation.....................................................  6
1 Mode Selection.................................................  6
2 LPC Mode ........................................................  6
2.1 CE#, LFRAME#........................................  6
2.2 Abort Mechanism ......................................  6
3 Status Polling DQ7 (LPC Mode, A/A Mode)...  6
4 Toggle Bit DQ6 (LPC Mode, A/A Mode)  ........ 7
5 LPC Memory Cycle Field Definitions  ............. 7
6 Multi Byte Read (LPC Mode)  .......................... 9
7 Multiple Device Selection (LPC Mode) ......... 10
8 General Purpose Inputs 
(GPI) Register (LPC Mode)............................ 11
9 Product Identifier Codes 
(LPC Mode, A/A Mode)................................  12
10 Lock Registers (LPC Mode, A/A Mode) .....  12
11 Write Protection............................................  13
11.1 TBL# and WP# Hardware Write 
Protection (LPC Mode)  ........................ 13
11.2 Whole Block Lock Software Write 
Protection (LPC Mode, A/A Mode)  ..... 13
PAGE
12 Memory Map................................................  14
13 A/A Mode.....................................................  15
14 Command Definitions ..................................  16
15 Status Register Definition ............................. 17
Electrical Specifications ........................................ 18
1 Absolute Maximum Ratings ........................... 18
2 Operating Conditions  ..................................... 18
2.1 Capacitance .............................................. 18
2.2 AC Input/Output Test Conditions ............ 19
2.3 DC Characteristics ................................... 20
2.4 AC Characteristics (LPC Mode)  ............. 22
2.5 Reset and Abort Operations (LPC Mode)  29
2.6 AC Characteristics (A/A Mode) .............. 31
2.7 Reset Operations (A/A Mode) ................. 35
Rev. 0.05

LHF00L02 2

LHF00L02

8Mbit (1Mbit×8)

LPC Flash MEMORY

 Conforms to Intel LPC Interface Specification 1.0

 Optimized Array Blocking Architecture

• Fifteen 64-KByte Uniform Blocks

• Eight 8-KByte Boot Sectors

• Boot Sector Data Protection

for each 8-KByte sector

• Full Chip Erase for A/A Mode Only

 VCC=3.0V-3.6V Operation

 Extended Cycling Capability

• Minimum 100,000 Block Erase Cycles

 Low Power Consumption (LPC Interface)

• Standby Current : 15µA (Max.)

• Read Current : 15mA (Max.)

• Erase or Program Current : 25mA (Max.)

 Erase or Program Operation

• Byte Program Time : 25µs (Typ.)

• Sector Erase Time : 0.6s (Typ.)

• Block Erase Time : 1.2s (Typ.)

• Full Chip Erase Time : 40s (Typ.)

• Sector Rewrite Time : 0.8s (Typ.)

• Block Rewrite Time : 2.8s (Typ.)

 Operating Temperature 0°C to +85°C

 CMOS Process (P-type silicon substrate)

 Two Operational Modes

• Low Pin Count (LPC) Interface mode

for In-System operation

• Address/Address Multiplexed Interface (A/A) Mode

for production erasing and programming

 LPC Interface Mode

• 5 signal communication interface

supporting byte Read and Write

• 33MHz clock frequency operation

• WP# and TBL# pins provide hardware data

protection for entire chip and/or boot sector

• Status Polling and Toggle Bit for End-of-Write

detection

• 5 GPI pins for system design flexibility

• ID pins for multi-chip selection

 Multi Byte Read Mode (LPC)

• Max. 128-Byte Sequential Read Operation

for data transfer

 A/A Interface Mode

• 11 pin multiplexed address and

8-pin data I/O interface

• Supports fast In-System or PROM programming

for manufacturing

 CMOS and PCI I/O Compatibility

 32-Lead TSOP (Normal Bend)

 ETOXTM* Flash Technology

 Not designed or rated as radiation hardened

* ETOX is a trademark of Intel Corporation.

Rev. 0.05

LHF00L02 3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

32-LEAD TSOP

STANDARD PINOUT

8mm x 13.4mm

TOP VIEW

MODE

A

10

R/C#

A

8

RST#

A

9

A

7

A

6

A

5

A

4

V

CC

NC

RY/BY#

17

18

19

20

21

22

23

24

32

31

30

29

28

27

26

25

WE#

A

3

A

2

A

1

GND

DQ

7

DQ

6

DQ

5

DQ

4

DQ

3

DQ

2

DQ

1

DQ

0

OE#

A

0

V

CC

(INIT#)

(LFRAME#)

(NC)

(CE#)

(MODE)

(GPI

4

)

(LCLK)

(V

CC

)

(RY/BY#)

(RST#)

(GPI

3

)

(GPI

2

)

(GPI

1

)

(GPI

0

)

(WP#)

(TBL#)

(V

CC

)

(RES)

(LAD

3

)

(LAD

2

)

(GND)

(LAD

1

)

(LAD

0

)

(ID

0

)

(ID

1

)

(ID

2

)

(ID

3

)

Figure 1. 32-Lead TSOP (Normal Bend) Pinout

Symbols inside ( ) are those for LPC mode.

Rev. 0.05

LHF00L02 4

1 Product Description

The product is offered in 32-Lead TSOP (Normal Bend)

package. Refer to Figure 1 for pinouts and Table 1 for pin

descriptions.

Table 1. Pin Descriptions

Symbol Type Interface Name and Function

A/A LPC

RST# INPUT ΟΟ

RESET: When low (VIL), RST# resets internal automation and inhibits erase

and program operations, which provides data protection. RST#-high (VIH)

enables normal operation. After power-up or reset mode, the device is

automatically set to read array mode.

MODE INPUT ΟΟ

MODE: This pin determines which interface is operational. This pin must be

held high (VIH) for A/A mode and low (VIL) for LPC mode. This pin is

internally pulled-down with a resistor between 20KΩ-100KΩ.

INIT# INPUT ΟINITIALIZE: This is the second reset pin for in-system use. This pin is

internally combined with the RST# pin; If this pin or RST# pin is driven low,

identical operation is exhibited.

CE# INPUT ΟCHIP ENABLE: This signal must be asserted to select the device. When CE# is

low, the device is enabled. When CE# is high, the device is placed in low power

standby mode.

LFRAME# INPUT ΟFRAME: To indicate start of a data transfer operation. This pin is also used to

abort an LPC cycle in progress.

LAD3-LAD0INPUT/

OUTPUT ΟADDRESS AND DATA: To provide LPC control signals, as well as addresses

and command Inputs data/Outputs data.

LCLK INPUT ΟCLOCK: To provide a clock input to the control unit.

ID3-ID0INPUT Ο

IDENTIFICATION INPUTS: These four pins are part of the mechanism that

allows multiple parts to be attached to the same bus. The strapping of these pins

is used to identify the component. These pins are internally pulled-down with a

resistor between 20KΩ-100KΩ.

GPI4-GPI0INPUT ΟGENERAL PURPOSE INPUTS: These individual inputs can be used for

additional board flexibility. The state of these pins can be read through GPI

registers.

TBL# INPUT Ο

TOP BOOT LOCK: When low, prevents erasing and programming to the boot

sectors at top (highest address) of memory. When TBL# is high, it disables

hardware data protection for the boot sectors. This pin cannot be left

unconnected.

WP# INPUT ΟWRITE PROTECT: When low, prevents erasing and programming to all blocks

other than boot sector. When WP# is high, it disables hardware data protection

for these blocks. This pin cannot be left unconnected.

RES ΟRESERVED: These pins must be left unconnected.

Rev. 0.05

LHF00L02 5

OE# INPUT ΟOUTPUT ENABLE: Gates the device’s outputs during a read cycle.

WE# INPUT ΟWRITE ENABLE: Controls writes to the memory array. Data is latched on the

rising edge of WE#.

R/C# INPUT ΟROW/COLUMN SELECT: For A/A interface mode, this pin determines

whether the address pins are porting to the row address, or to the column

address.

A10-A0INPUT ΟADDRESS INPUTS: Inputs for low-order addresses during read and write

operations. Addresses are internally latched by R/C# during an erase or program

cycle. These addresses share the same pins as the high-order address inputs.

DQ7-DQ0INPUT/

OUTPUT Ο

DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles,

outputs data during memory array, status register and identifier code reads. Data

pins float to high-impedance (High Z) when the chip or outputs are deselected.

Data is internally latched during an erase or program cycle.

RY/BY#

OPEN

DRAIN

OUTPUT

ΟΟ

READY/BUSY#: This output pin is a reflection bit 7 in the status register. This

pin is used to determine the erase or program completion. This pin must be

pulled-up with an external resistor on board.

VCC SUPPLY ΟΟ

DEVICE POWER SUPPLY (3.0V-3.6V): With VCC≤VLKO, all write attempts

to the flash memory are inhibited. Device operations at invalid VCC voltage

(refer to DC Characteristics) produce spurious results and should not be

attempted.

GND SUPPLY ΟΟGROUND: Do not float any ground pins.

NC ΟΟNO CONNECT: Lead is not internally connected; it may be driven or floated.

Table 1. Pin Descriptions

Symbol Type Interface Name and Function

A/A LPC

Rev. 0.05

(Continued)

LHF00L02 6

2 Device Operation

2.1 Mode Selection

The product can operate in two distinct interface modes:

• The LPC interface mode for In-System erasing and

programming

• Address/Address Multiplexed (A/A) interface mode

for factory erasing and programming

The state of the device’s MODE pin determines which

interface is in use. If the MODE pin is set to logic high,

the device is in A/A mode; while if the MODE pin is set

low, the device is in the LPC mode. The MODE selection

pin must be configured prior to device operation.

2.2 LPC Mode

The LPC mode uses a 5-signal communication interface,

4-bit address/data bus, LAD3-LAD0, and a control line,

LFRAME#, to control operations of the product. Cycle

type operations such as Memory Read and Memory Write

are defined in Intel Low Pin Count Interface

Specification, Rev.1.0. Erase and Program commands

sequences are incorporated into the standard LPC

memory cycles.

LPC signals are transmitted via the 4-bit Address/Data

bus (LAD3-LAD0), and follow a particular sequence,

depending on whether they are Read or Write operations.

The standard LPC memory cycle is defined in Table 2 and

Table 3.

2.2.1 CE#, LFRAME#

The CE# pin, enables and disables the product,

controlling read and write access of the device. To enable

the product, the CE# pin must be driven low one cycle

prior to LFRAME# being driven low. For write (erase or

program) cycles, the CE# pin must remain low during the

internal operation. When CE# is high, the product is

placed in standby mode.

The LFRAME# signifies the start of a frame or the

termination of a broken frame. Asserting LFRAME# for

one or more clock cycle and driving a valid "START"

value on LAD3-LAD0 will initiate device operation. The

device enters standby mode when LFRAME# and CE#

are high and no internal operation is in progress.

2.2.2 Abort Mechanism

If LFRAME# is driven low for 4 clock cycles during a

LPC cycle, the cycle will be terminated and the device

will wait for the "ABORT" command. To return the

device to the ready mode, the host must drive the LAD3-

LAD0 with "1111b" ("ABORT" command) while

LFRAME# is driven low, and LAD3-LAD0 must remain

unchanged until LFRAME# goes to VIH (refer to Figure

18). When an abort procedure is performed between the

two command write cycles, such as sector/block erase or

byte program, the device turns the bus around to the host

but the termination of command for the internal operation

is not guaranteed. If the system needs to abort after the

first command cycle, the host must write "FFH" and

check the status register after performing the abort

procedure. Status register indicates the termination of

internal operation and error conditions. If abort occurs

during the internal write cycle, the data may be

incorrectly programmed or erased. It is required to wait

for the write operation to complete prior to initiation of

the abort command. It is recommended to check the write

status with status polling (DQ7) or toggle bit (DQ6). One

other option is to wait for the fixed write time to expire.

2.3 Status Polling DQ7

(LPC Mode, A/A Mode)

When the product device is in the automatic internal

operation (program, erase, etc.), WSM (Write State

Machine) status bit DQ7 (SR.7) will produce a "0". Once

the internal operation is completed, DQ7 will produce a

"1". The SR.7 bit can be polled to find the end of the

operation. The other status bits (SR.5-0) should not be

checked until the WSM completes the operation and the

status bit SR.7 is "1". Refer to Table 13 for the status

register definition.

Rev. 0.05

LHF00L02 7

Rev. 0.05

2.4 Toggle Bit DQ6

(LPC Mode, A/A Mode)

During the automatic internal operation (program, erase,

etc.), any consecutive attempts to read DQ6 (SR.6) will

produce alternating "0"s and "1"s, i.e., toggling between

"0" and "1". When the internal operation is completed, the

toggling will stop.

2.5 LPC Memory Cycle Field Definitions

Table 2. LPC Read Cycle Field Definitions

Field Clocks LAD3-LAD0

Direction Description

START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle.

CYCTYPE 1 INPUT

Cycle Type: Indicates the type of cycle. LAD3-LAD2 must be "01b" for

memory cycle. LAD1 indicates the direction of the transfer: "0b" for read.

LAD0 is reserved for future implementation.

ADDR 8 INPUT

Address Phase for Memory Cycle: LPC supports the 32-bit address protocol. It

is transferred most significant nibble first. All the values of A31-A24 must be set

to "1". For A23-A20 values, refer to Table 6.

TAR 2

INPUT

then

High Z

Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b"

during the first clock and to drive LAD3-LAD0 to High Z during the second

clock by the host.

Sync 1-3 OUTPUT

Sync: Synchronize to host or peripheral by adding wait states. "0000b" means

Ready, "0101b" means Short Wait. The product supports three types of wait

states: "no-wait", "1-wait", or "2-waits".

Data 2 OUTPUT Data Phase: The data byte is transferred least significant nibble first.

(DQ3-DQ0 on LAD3-LAD0 first, DQ7-DQ4 on LAD3-LAD0 last.)

TAR 2

OUTPUT

then

High Z

Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b"

during the first clock and to drive LAD3-LAD0 to High Z during the second

clock by the Flash Memory.

LHF00L02 8

Table 3. LPC Write Cycle Field Definitions

Field Clocks LAD3-LAD0

Direction Description

START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle.

CYCTYPE 1 INPUT

Cycle Type: Indicates the type of cycle. LAD3-LAD2 must be "01b" for

memory cycle. LAD1 indicates the direction of the transfer: "1b" for write.

LAD0 is reserved for future implementation.

ADDR 8 INPUT

Address Phase for Memory Cycle: LPC supports the 32-bit address protocol. It

is transferred most significant nibble first. All the values of A31-A24 must be set

to "1". For A23-A20 values, refer to Table 6.

Data 2 INPUT Data Phase: The data byte is transferred least significant nibble first.

(DQ3-DQ0 on LAD3-LAD0 first, DQ7-DQ4 on LAD3-LAD0 last.)

TAR 2

INPUT

then

High Z

Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b"

during the first clock and to drive LAD3-LAD0 to High Z during the second

clock by the last components driving LAD3-LAD0.

Sync 1 OUTPUT Sync: The product only supports "0000b" Ready sync.

TAR 2

OUTPUT

then

High Z

Turn-Around: It indicates a turn-around cycle to drive LAD3-LAD0 to "1111b"

during the first clock and to drive LAD3-LAD0 to High Z during the second

clock by the Flash Memory.

Rev. 0.05

LHF00L02 9

Rev. 0.05

2.6 Multi Byte Read (LPC Mode)

The product provides Multi Byte Read operation in LPC

mode. Multi Byte Read mode enables two or more byte

of sequential read at one operation cycle. This increases

data transfer rate compared with normal memory read

operation. The transfer multi-byte size can be selected

from four types.

Table 4. LPC Multi Byte Read Cycle Field Definitions

Field Clocks LAD3-LAD0

Direction Description

START 1 INPUT Start of Cycle: "0000b" appears on LPC bus to indicate the start of cycle.

CYCTYPE 1 INPUT Cycle Type: "1100b" = Multi Byte Read

MSIZE 1 INPUT

Transfer Multi-Byte Size: LAD1-LAD0Transfer Byte Size

00 2 byte

01 8 byte

10 32 byte

11 128 byte

ADDR 8 INPUT Address: Start address of Multi Byte Read: A31-A0.

TAR 2 INPUT

then

High Z

Turn-Around: "1111b" and

High Z

Sync 1 N+1 OUTPUT Sync: "0101b" = Short Wait

"0000b" = Ready

(N: the number of Short Wait)

Data 1 2 OUTPUT Data Phase: First byte; DQ3-DQ0 on LAD3-LAD0 (1st. cycle)

DQ7-DQ4 on LAD3-LAD0 (2nd. cycle)

Sync M (N+1) × MOUTPUT

Sync: "0101b" = Short Wait

"0000b" = Ready

(N: the number of Short Wait)

(M: the number of Multi Byte)

Data M 2 × MOUTPUT

Data Phase: Multi byte; DQ3-DQ0 on LAD3-LAD0 (1st. cycle)

DQ7-DQ4 on LAD3-LAD0 (2nd. cycle)

TAR 2 OUTPUT

then

High Z

Turn-Around: "1111b" and

High Z

Table 5. LPC Multi Byte Read Bandwidth [ f(CLK)=33MHz ]

128-Byte Multi Byte Read Clocks Unit 128-Byte Normal Read Clocks Unit

START 1 START 1

× 128

CYCTYPE 1 CYCTYPE 1

MSIZE+ADDR 9 ADDR 8

TAR 2 TAR 2

Sync (no-wait) 1 × 128 Sync (no-wait) 1

Data 2 Data 2

TAR 2 TAR 2

Total Clocks 399 Total Clocks 17 × 128

Transfer Time 12 µs Transfer Time 65 µs

Bandwidth 10.69 MByte/s Bandwidth 1.96 MByte/s

LHF00L02 10

2.7 Multiple Device Selection (LPC Mode)

Multiple LPC Flash devices may be strapped to increase

memory densities in a system. LPC protocol of the

product supports up to 8 LPC Flash devices.

The four ID pins, ID3-ID0, allow up to 8 devices to be

attached to the same bus by using different ID strapping

in a system. If the product is used as a boot device, ID3-

ID0 must be strapped as "000x", all subsequent devices

should use a sequential up-count strapping (i.e., "000x",

"001x", "010x", "011x", etc.). ID0 is not used and may be

either "0" or "1".

Rev. 0.05

Device 6

Device 7

16Mbit

Boot Device 0

Device 1

16Mbit

. . .

Figure 2. Multiple LPC Device Mapping

Table 6. ID Strapping Values (LPC Mode)

Device No. ID3-ID0A23 A22 A21-A20

0 (Boot device) 000x

1Read:

1 = Memory Read

0 = Register Read

Write:

0 or 1 = Memory Write

11

1 001x 10

2 010x 01

3 011x 00

4 100x

0

11

5 101x 10

6 110x 01

7 111x 00

8Mbit

LHF00L02 11

2.8 General Purpose Inputs (GPI) Register

(LPC Mode)

The GPI_REG (General Purpose Inputs Register) reads

the status of the GPI4-GPI0 pins on the product. Since this

is a pass-through register, there is no default value, only

the state of the pins at power-up. The pins must have

stable data from before the start of the cycle that reads the

GPI_REG until after the cycle is complete. These pins

must not be left to float and they should be driven VIL or

VIH.

Refer to Table 7 for the GPI_REG bits and function, and

Table 8 for memory address location for its respective

device strapping. If this address is input, GPI_REG can

be read also on read identifier codes mode, read status

register mode or read array mode.

Table 7. General Purpose Input Register

Bit Function

7:5 Reserved for future implementation.

4GPI4 : Reads status of general-purpose input pin (Pin 6)

3GPI3 : Reads status of general-purpose input pin (Pin 11)

2GPI2 : Reads status of general-purpose input pin (Pin 12)

1GPI1 : Reads status of general-purpose input pin (Pin 13)

0GPI0 : Reads status of general-purpose input pin (Pin 14)

Table 8. Memory Map for General Purpose Input Register Addresses

Device No. GPI_REG

0 (Boot device) FFBC0100H

1 FFAC0100H

2 FF9C0100H

3 FF8C0100H

4 FF3C0100H

5 FF2C0100H

6 FF1C0100H

7 FF0C0100H

Rev. 0.05

LHF00L02 12

2.9 Product Identifier Codes

(LPC Mode, A/A Mode)

The product identifier codes identify the device as the

product and manufacturer as SHARP.

• In LPC mode:

The Read Identifier Codes command is unnecessary and

only an address shown in Table 9 is required. However,

A22 must be "0" in this operation. The operation by the

command is also possible if the Read Identifier Codes

command is written. Any command is acceptable not only

when A22="1" but also when A22="0".

• In A/A mode:

The Read Identifier Codes command is necessary. Refer

to Table 12 for the command definitions.

2.10 Lock Registers (LPC Mode, A/A Mode)

The product offers double write protection. The boot lock

provides hardware write protection for each 8-Kbyte boot

sector. Furthermore, the whole block lock provides

software write protection for all sectors and blocks. The

write protection status is controlled by each lock bit.

Refer to "2.11 Write Protection" for details. The

protection status can be checked through the lock

registers.

NOTES:

1. A31-A20 are not used in A/A mode.

2. A22 must be "0" when the registers are read in LPC mode.

3. A23, A21-A20 correspond to the address for ID strapping (refer to Table 6).

4. DQ7-DQ2 are reserved for future implementation.

5. The registers shown above must not be read while the WSM is busy.

Table 9. LPC Flash Registers Configuration Map (1), (5)

Device Address

Register Name Protected Address

Range [A19-A0]

Default

Value Type

Notes

A23 (3) A22 (2) [A21-A20] (3) [A19-A0]

1

or

0

(Register

Access)

11

or

10

or

01

or

00

XX002H Whole Block Lock Register FFFFFH - 00000H DQ1 = 1 RO 4

FE002H Block Lock Register (Sector 7) FFFFFH - FE000H DQ0 = 0 RO 4

FC002H Block Lock Register (Sector 6) FDFFFH - FC000H DQ0 = 0 RO 4

FA002H Block Lock Register (Sector 5) FBFFFH - FA000H DQ0 = 0 RO 4

F8002H Block Lock Register (Sector 4) F9FFFH - F8000H DQ0 = 0 RO 4

F6002H Block Lock Register (Sector 3) F7FFFH - F6000H DQ0 = 0 RO 4

F4002H Block Lock Register (Sector 2) F5FFFH - F4000H DQ0 = 0 RO 4

F2002H Block Lock Register (Sector 1) F3FFFH - F2000H DQ0 = 0 RO 4

F0002H Block Lock Register (Sector 0) F1FFFH - F0000H DQ0 = 0 RO 4

C0100H LPC General Purpose

Input Register N/A N/A RO

00001H Device Code Register N/A C9H RO

00000H Manufacturer Code Register N/A B0H RO

Rev. 0.05

LHF00L02 13

2.11 Write Protection

2.11.1 TBL# and WP# Hardware Write

Protection (LPC Mode)

The top boot lock (TBL#) and write protect (WP#) pins

are provided for hardware write protection of the memory

area in the product. TBL# pin is used to write protection

of 8 boot sectors (8Kbytes) at the highest memory address

range for the product. WP# pin is used for the remaining

blocks in the flash memory.

An active low signal at the TBL# pin prevents erase and

program operations of the boot sectors. TBL# protection

is effective only to the sector to which the boot lock bit is

set. When TBL# pin is held high, the write protection of

the boot sectors is disabled. The WP# pin serves the same

function for the remaining blocks of the memory array.

The TBL# and WP# pins write protection functions

operate independently of one another.

Both TBL# and WP# pins must be set to their required

protection states prior to starting an erase or program

operation. A logic level change occurring at the TBL# or

WP# pin during an erase or program operation could

cause unpredictable results.

2.11.2 Whole Block Lock Software Write

Protection (LPC Mode, A/A Mode)

The whole block lock is provided for software write

protection of the memory area in the product. Whole

block lock protects all sectors and blocks in the device by

lock bit. The lock bit is set to locked state in an initial

state after power-up or reset operation. The lock bit must

be cleared to unlocked state before starting erase or

program operation. The lock bit is cleared by clear whole

block lock bit operation. After erase or program operation

is finished, the memory array can be protected by set

whole block lock bit operation.

NOTES:

1. Lock Bit : "1" = Locked State, "0" = Unlocked State

Table 10. Write Protection Alternatives

Operation Whole Block

Lock Bit (1) TBL# Boot

Lock Bit (1) WP# Effect

Sector Erase or

Block Erase or

Full Chip Erase or

Byte Program

1X X X

All sectors and blocks are

Locked.

0

VIL 1 X Boot sector is Locked.

VIL 0 X Boot sector is Unlocked.

VIH XX

All boot sectors are

Unlocked

VIH XVIL The remaining blocks other than

boot sectors are Locked

VIH XVIH All sectors and blocks are

Unlocked

Rev. 0.05

LHF00L02 14

Rev. 0.05

2.12 Memory Map

TBL# for Boot Sector 0 - 7

8Kbyte Boot Sector 0

64Kbyte Block 0

64Kbyte Block 1

64Kbyte Block 2

64Kbyte Block 3

64Kbyte Block 4

64Kbyte Block 5

64Kbyte Block 6

64Kbyte Block 7

64Kbyte Block 8

64Kbyte Block 9

64Kbyte Block 10

64Kbyte Block 11

64Kbyte Block 13

64Kbyte Block 12

64Kbyte Block 14

8Kbyte Boot Sector 1

8Kbyte Boot Sector 2

8Kbyte Boot Sector 3

8Kbyte Boot Sector 4

8Kbyte Boot Sector 5

8Kbyte Boot Sector 6

8Kbyte Boot Sector 7

00000H

10000H

20000H

30000H

40000H

50000H

60000H

70000H

80000H

90000H

A0000H

B0000H

C0000H

D0000H

E0000H

EFFFFH

F0000H

F2000H

F4000H

F6000H

F8000H

FA000H

FC000H

FE000H

FFFFFH

64Kbyte

Block 15

WP# for Block 0 - 14

Top Boot

Figure 3. Memory Map

LHF00L02 15

Rev. 0.05

2.13 A/A Mode

Commands are used to initiate the memory operation

functions of the device. The data portion of the software

command sequence is latched on the rising edge of WE#.

During the software command sequence, the row address

is latched on the falling edge of R/C# and the column

address is latched on the rising edge of R/C#.

NOTES:

1. X can be VIL or VIH for control pins and addresses.

2. DQ refers to DQ7-DQ0.

3. RST# at GND±0.2V ensures the lowest power consumption.

4. Command writes involving sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block

lock bit, set boot lock bit and clear boot lock bits are reliably executed when VCC=3.0V-3.6V.

5. Refer to Table 12 for valid DIN during a write operation.

6. Never hold OE# low and WE# low at the same timing.

Table 11. Operation Modes Selection (1)

Mode Notes RST# OE# WE# Address DQ (2)

Read Array 6 VIH VIL VIH AIN DOUT

Output Disable VIH VIH VIH X High Z

Standby VIH VIH VIH X High Z

Reset 3 VIL X X X High Z

Read Identifier Codes 6 VIH VIL VIH Refer to

Table 9

Refer to

Table 9

Read Status Register 6 VIH VIL VIH AIN DOUT

Write 4, 5, 6 VIH VIH VIL AIN DIN

Figure 4. Block Diagram

16M bit

Flash Cell Array

Y-Decoder

X-Decoder

I/O Buffers and Data Latches

Address Buffers

and Latches

Control Logic

Command

User

Interface

LPC

Interface

LAD

3

-LAD

0

LCLK

LFRAME#

ID

3

-ID

0

R/C#

A

10

-A

0

DQ

7

-DQ

0

OE#

WE#

CE#RST#MODE

GPI

4

-GPI

0

TBL#

WP#

INIT#

8Mbit

LHF00L02 16

Rev. 0.05

2.14 Command Definitions

NOTES:

1. Bus operations are defined in Table 11.

2. Any command is acceptable not only when A22="1" but also when A22="0" in LPC mode.

X=Any valid address within the device.

IA=Identifier codes address (Refer to Table 9).

BA=Address within the sector/block for sector/block erase.

WA=Address of memory location for program.

SA=Address within the boot sector for set boot lock bit.

3. ID=Data to be read from identifier codes. (Refer to Table 9).

SRD=Data to be read from status register. Refer to Table 13 for a description of the status register bits.

WD=Data to be programmed at location WA.

4. The device returns to the read array mode even after Clear Status Register command or reset operation by RST#/INIT#.

5. Following the Read Identifier Codes command, read operations access manufacturer code, device code and block lock

configuration code (Refer to Table 9). The identifier codes must not be read while the WSM is busy.

6. Sector/block erase, full chip erase and byte program operations cannot be executed to boot sector when TBL# goes to VIL.

Sector/block erase, full chip erase and byte program operations cannot be executed to blocks other than boot sector when

WP# goes to VIL.

7. Whole block lock bit must be cleared when executing sector/block erase, full chip erase and byte program operations.

Sector/block erase, full chip erase and byte program operations cannot be executed if whole block lock bit is set.

8. Supported in A/A Mode only. Any boot sector which is locked by boot lock bit is protected from alteration. Boot lock bit

should be cleared before performing an erase operation.

9. Either 40H or 10H are recognized as the program first bus cycle command.

10. Lock bit can be set to each sector within the boot block (block 15). Since this lock bit is non-volatility, it holds the lock

state even after power-off or reset.

11. All boot lock bits of each sector are cleared at a time.

SA=Address within the boot sector (F0000H-FFFFFH).

12. Commands other than those shown above are reserved by SHARP for future device implementations and should not be

used.

Table 12. Command Definitions (12)

Command

Interface Bus

Cycles

Req’d

Notes

First Bus Cycle Second Bus Cycle

A/A LPC Oper(1) Addr(2) Data Oper(1) Addr(2) Data(3)

Read Array O O 1 4 Write X FFH

Read Identifier Codes O O ≥ 2 5 Write X 90H Read IA ID

Read Status Register O O 2 Write X 70H Read X SRD

Clear Status Register O O 1 4 Write X 50H

Sector/Block Erase O O 2 6,7 Write BA 20H Write BA D0H

Full Chip Erase O 2 6,7,8 Write X 30H Write X D0H

Byte Program O O 2 6,7,9 Write X 40H or

10H Write WA WD

Set Whole Block Lock Bit O O 2 Write X 60H Write X BBH

Clear Whole Block Lock Bit O O 2 7 Write X 60H Write X DBH

Set Boot Lock Bit O O 2 10 Write X 60H Write SA 01H

Clear Boot Lock Bits O O 2 11 Write X 60H Write SA D0H

LHF00L02 17

Rev. 0.05

2.15 Status Register Definition

Table 13. Status Register Definition

WSMS TB ECLS PSLS PVEVS R DPS R

76543210

SR.7 = WRITE STATE MACHINE STATUS (WSMS)

1 = Ready

0 = Busy

SR.6 = TOGGLE BIT (TB)

Toggling between "0" and "1" during the erase or

program operation.

SR.5 = SECTOR/BLOCK ERASE, FULL CHIP ERASE

AND CLEAR BOOT LOCK BITS STATUS

(ECLS)

1 = Error in Sector/Block Erase, Full Chip Erase or Clear

Boot Lock Bits

0 = Successful Sector/Block Erase, Full Chip Erase or

Clear Boot Lock Bits

SR.4 = BYTE PROGRAM AND SET BOOT LOCK

BIT STATUS (PSLS)

1 = Error in Byte Program or Set Boot Lock Bit

0 = Successful Byte Program or Set Boot Lock Bit

SR.3 = PROGRAM VOLTAGE OR ERASE VOLTAGE

STATUS (PVEVS)

1 = Invalid Program or Erase Voltage Detect,

Operation Abort

0 = Program or Erase Voltage OK

SR.2 = RESERVED FOR FUTURE ENHANCEMENTS (R)

SR.1 = DEVICE PROTECT STATUS (DPS)

1 = Erase or Program Attempted on a Locked Block by

TBL#, WP# or Block Lock Bit, Operation Abort

0 = Unlocked

SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)

NOTES:

Check SR.7 or SR.6 or RY/BY# to determine sector/block

erase, full chip erase, byte program, set whole block lock bit,

clear whole block lock bit, set boot lock bit or clear boot lock

bits completion. SR.5, SR.4, SR.3 and SR.1 are invalid while

SR.7="0".

If both SR.5 and SR.4 are "1"s after a sector/block erase, full

chip erase, set whole block lock bit, clear whole block lock

bit, set boot lock bit and clear boot lock bits attempt, an

improper command sequence was entered.

SR.3 indicates the program or erase voltage conditions. The

program or erase voltage is the internal voltage which is used

for the program or erase operation in the flash memory. SR.3

does not provide a continuous indication of the program or

erase voltage level. The WSM interrogates and indicates the

program or erase voltage level only after Sector/Block Erase,

Full Chip Erase, Byte Program, Set Boot Lock Bit and Clear

Boot Lock Bits command sequences.

SR.1 does not provide a continuous indication of block lock

bit. The WSM interrogates TBL#, WP# or block lock bit only

after Sector/Block Erase, Full Chip Erase or Byte Program

command sequences. It informs the system, depending on the

attempted operation, if the block is locked.

SR.2 and SR.0 are reserved for future use and should be

masked out when polling the status register.

LHF00L02 18

Rev. 0.05

3 Electrical Specifications

3.1 Absolute Maximum Ratings*

Operating Temperature

During Read, Erase and Program ...... 0°C to +85°C (1)

Storage Temperature

During under Bias............................... -10°C to +85°C

During non Bias................................ -65°C to +125°C

Voltage On Any Pin

(except VCC)............................ -0.5V to VCC+0.5V (2)

VCC Supply Voltage ........................... -0.2V to +3.9V (2)

Output Short Circuit Current ........................... 100mA (3)

*WARNING: Stressing the device beyond the "Absolute

Maximum Ratings" may cause permanent

damage. These are stress ratings only. Operation

beyond the "Operating Conditions" is not

recommended and extended exposure beyond the

"Operating Conditions" may affect device

reliability.

NOTES:

1. Operating temperature is for commercial temperature

product defined by this specification.

2. All specified voltages are with respect to GND.

Minimum DC voltage is -0.5V on input/output pins and

-0.2V on VCC pin. During transitions, this level may

undershoot to -2.0V for periods <20ns. Maximum DC

voltage on input/output pins is VCC+0.5V which,

during transitions, may overshoot to VCC+2.0V for

periods <20ns.

3. Output shorted for no more than one second. No more

than one output shorted at a time.

3.2 Operating Conditions

NOTES:

1. Refer to DC Characteristics tables for voltage range-specific specification.

3.2.1 Capacitance (1) (TA=+25°C, f=1MHz)

NOTE:

1. Sampled, not 100% tested.

Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions

TAOperating Temperature 0+25+85°C Ambient Temperature

VCC VCC Supply Voltage 1 3.0 3.3 3.6 V

Sector/Block Erase Cycling 100,000 Cycles

Symbol Parameter Min. Typ. Max. Unit Condition

CIN Input Capacitance 710pF VIN=0.0V

CI/O Input / Output Capacitance 912pF VI/O=0.0V

LHF00L02 19

Rev. 0.05

3.2.2 AC Input/Output Test Conditions

TEST POINTS1.5 1.5INPUT

3.0

0.0

AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0".

Input timing begins and output timing ends at 1.5V. Input rise and fall times (10% to 90%) < 5ns.

OUTPUT

Figure 5. Transient Input/Output Reference Waveform for VCC=3.0V-3.6V

Table 14. Configuration Capacitance Loading Value

Test Configuration CL (pF)

VCC=3.0V-3.6V 30

DEVICE

UNDER

TEST

RL=3.3KΩ

CL

1.3V

OUT

CL Includes Jig

Capacitances.

1N914

Figure 6. Transient Equivalent Testing Load Circuit

LHF00L02 20

Rev. 0.05

3.2.3 DC Characteristics

VCC=3.0V-3.6V

Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions

ILI Input Load Current 1 -1 +1 µA

VCC=VCCMax.,

VIN/VOUT=VCC or

GND

ILID

Input Load Current

for MODE, ID3-ID0 pins 1-200 +200µA

ILO Output Leakage Current 1 -1 +1 µA

ICCS1

VCC Standby Current

(LPC Interface) 1, 2, 5 5 15 µA

CMOS Inputs,

VCC=VCCMax.,

CE#=VIH,

RST#=VCC±0.2V

ICCS2

VCC Standby Current

(LPC Interface) 1, 2, 5 5 15 µA

CMOS Inputs,

VCC=VCCMax.,

CE#=VIL,

f(CLK)=33MHz

LFRAME#

=VIH,

RST#=VCC±0.2V

ICCRY

VCC Ready Mode Current

(LPC Interface) 1, 2, 5 5 8 mA

CMOS Inputs,

VCC=VCCMax.,

CE#=VIL,

f(CLK)=33MHz

LFRAME#

=VIL,

RST#=VCC±0.2V

ICCS3

VCC Standby Current

(A/A Interface) 1, 2, 5 5 8 mA

CMOS Inputs,

VCC=VCCMax.,

RST#=VCC±0.2V,

R/C#=OE#=WE#=VIH

ICCD VCC Reset Current 1515µARST#=GND±0.2V,

IOUT (RY/BY#)=0mA

ICCR1

VCC Read Current

(LPC Interface) 1, 2 15 mA

CMOS Inputs,

VCC=VCCMax.,

CE#=LFRAME#=VIL,

f(CLK)=33MHz,

IOUT=0mA

ICCR2

VCC Read Current

(A/A Interface) 1, 2 15 mA

CMOS Inputs,

VCC=VCCMax.,

f=4MHz, IOUT=0mA

ICCW

VCC Byte Program, Set Boot Lock Bit

Current 1, 2, 4 25 mA CMOS Inputs,

VCC=VCCMax.

ICCE

VCC Sector/Block Erase, Full Chip

Erase, Clear Boot Lock Bits Current 1, 2, 4 25 mA CMOS Inputs,

VCC=VCCMax.

LHF00L02 21

Rev. 0.05

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.3V and TA=+25°C

unless VCC is specified.

2. CMOS inputs are either VCC±0.2V or GND±0.2V.

3. Sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block lock bit, set boot lock bit and

clear boot lock bits operations are inhibited when VCC≤VLKO. These operations are not guaranteed outside the specified

voltage (VCC=3.0V-3.6V).

4. Sampled, not 100% tested.

5. Includes RY/BY#.

VCC=3.0V-3.6V

Symbol Parameter Notes Min. Max. Unit Test Conditions

VIH Input High Voltage 4 0.5×

VCC

+ 0.5 VVCC=VCCMax.,

VIL Input Low Voltage 4 -0.5 0.3×

VCC VVCC=VCCMin.,

VOH Output High Voltage 4 0.9×

VCC VVCC=VCCMin.,

IOH=-0.5mA

VOL Output Low Voltage 4, 5 0.1×

VCC

VVCC=VCCMin.,

IOL=1.5mA

VLKO VCC Lockout Voltage 32.0 V

DC Characteristics (Continued)

LHF00L02 22

Rev. 0.05

3.2.4 AC Characteristics (LPC Mode) (1)

NOTES:

1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. Typical values measured at VCC=3.3V and TA=+25°C. Assumes TBL#, WP# and corresponding lock bits are not set.

Subject to change based on device characterization.

3. Sampled, not 100% tested.

4. Excludes external system-level overhead.

AC Characteristics (LPC Mode)

VCC=3.0V~3.6V, TA=0°C~+85°C

Symbol Parameter

Notes

Min. Typ.(2) Max. Unit

tCYC Clock Cycle Time 30 ns

tHIGH LCLK High Time 11 ns

tLOW LCLK Low Time 11 ns

LCLK Slew Rate (peak-to-peak) 1 4 V/ns

tSU Data Set-up Time to Clock Rising 9 ns

tDH Data Hold Time from Clock Rising 0 ns

tFSU LFRAME# Set-up Time to Clock Rising 18 ns

tFDH LFRAME# Hold Time from Clock Rising 2 ns

tVA L Clock Rising to Data Valid 2 15 ns

tON Clock Rising to Output in Low Z 3 2 ns

tOFF Clock Rising to Output in High Z 3 28 ns

tWQV1 Byte Program Time 3, 4 25 200 µs

tWQV2 Sector Erase Time 3, 4 0.6 5 s

tWQV3 Block Erase Time 3, 4 1.2 6 s

tWQV4 Full Chip Erase Time 3, 4 40 200 s

tSWBL Set Whole Block Lock Bit Time 3, 4 5 8 µs

tCWBL Clear Whole Block Lock Bit Time 3, 4 5 8 µs

tSTBL Set Boot Lock Bit Time 3, 4 35 200 µs

tCTBL Clear Boot Lock Bits Time 3, 4 0.4 1 s

LHF00L02 23

LCLK

0.3V

CC

0.4V

CC

0.5V

CC

0.6V

CC

0.2V

CC

tCYC

tHIGH

tLOW

0.4V

CC

peak-to-peak

(Min.)

Rev. 0.05

tON

tOFF

LAD3-LAD0

(Float Output Data)

LAD3-LAD0

(Valid Output Data)

LCLK

tVAL

VIH

VIL

VOH

VOL

Inputs

Valid

LAD3-LAD0

(Valid Input Data)

tDH

tSU

LCLK

VIH

VIL

Figure 8. Output Timing Parameters

Figure 9. Input Timing Parameters

Figure 7. LCLK Waveform

LHF00L02 24

Rev. 0.05

Figure 10. Read Cycle Timing Diagram (LPC Mode)

Figure 11. Write Cycle Timing Diagram (LPC Mode)

A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b D[7:4]D[3:0]

TAR

Start

Memory

Read

Cycle Address TAR Sync Data Next Start

t

CYC

t

VAL

t

SU

t

DH

2 Clocks

Load Address in 8 Clocks Data Out 2 Clocks

LCLK

RST#

CE#

LFRAME#

LAD

3

-LAD

0

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IH

, V

OH

V

IL

, V

OL

0000b 010Xb

1 Clock 1 Clock

0000b

1 Clock 1 Clock

A[31:28] A[27:24]

NOTE 1

NOTE 1. All the values of A[31:24] must be "1".

t

FSU

t

FDH

A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] D[7:4] Tri-State

1111b

D[3:0]

TAR

Start

Memory

Write

Cycle Address TAR Sync

Data Next Start

t

CYC

t

SU

t

DH

2 Clocks

Load Address in 8 Clocks

LCLK

RST#

CE#

LFRAME#

LAD

3

-LAD

0

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock 1 Clock

0000b

1 Clock 1 Clock

0000b

Load Data in 2 Clocks

A[31:28] A[27:24]

NOTE 1

NOTE 1. All the values of A[31:24] must be "1".

t

FSU

t

FDH

LHF00L02 25

0000 b 1100 b A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111 b Tri- State 0000 b D[7:4]D[3:0]

Start

Multi Byte

Read

Cycle Address (Start address) TAR Sync

1st.

Byte Data

1 Clock 1 Clock 2 ClocksLoad Address in 8 Clocks 1 Clock Data Out 2 Clocks

LCLK

RST#

CE#

LFRAME#

LAD3-LAD00000 b D[7:4]D[3:0]

2nd.

Byte DataSync

In the case of 128-byte Multi Byte Read ( no-wait )

MSIZE

XX11

0000 b D[7:4]D[3:0] TAR

Sync

127th.

Byte Data

Data Out 2 Clocks

LCLK

LAD3-LAD00000 b D[7:4]D[3:0]

Sync

1 Clock

0000 b

Sync

D[7:4]D[3:0] 0000 b D[7:4]D[3:0]

128th.

Byte Data (the last byte)

In the case of 128-byte Multi Byte Read ( no-wait )

LFRAME#

CE#

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IL

, V

OL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

, V

OH

V

IL

, V

OL

V

IH

, V

OH

A[31:28] A[27:24]

NOTE 1

NOTE 1. All the values of A[31:24] must be "1".

In the case of an input of the transfer size exceeding the last address

0000 b TAR

Sync

127th.

Byte Data

LCLK

LAD

3

-LAD

00000 b

Sync

0000 b

Sync

D[7:4]D[3:0] 0000 b

128th.

Byte Data (the last byte)

125th.

Byte Data

126th.

Byte Data

(Data for the

last address)

1111 b 1111 b 1111 b 1111 b 1111 b 1111 b

Sync

"1111b" is presented on Data field until the last byte.

V

IH

V

IL

V

IH

, V

OH

V

IL

, V

OL

Figure 12. Multi Byte Read Cycle Timing Diagram (LPC Mode)

Figure 13. Multi Byte Read Exceeding the Last Address (LPC Mode)

Rev. 0.05

LHF00L02 26

Rev. 0.05

Figure 14. Byte Program Cycle Timing Diagram (LPC Mode)

A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b

D[7:4]

D[3:0]

TAR

Start

Memory

Write

Cycle Address (WA) TAR Sync

Data Start next

2 Clocks

Load Address in 8 Clocks

LCLK

RST#

CE#

LFRAME#

LAD3-LAD0

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock

0000b

1 Clock 1 Clock

A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Tri-State 0000b

D[7:4]D[3:0]

TAR

Start

Memory

Write

Cycle Address (WA) TAR SyncData

2 Clocks

Load Address in 8 Clocks

LCLK

RST#

CE#

LFRAME#

LAD3-LAD0

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock

1 Clock 1 Clock

1st.

Load Data "40" in 2 Clocks

Command

Load Data in 2 Clocks

2nd.

Internal

Operation Start

1 Clock

A[31:28] A[27:24]

NOTE 1

A[31:28] A[27:24]

NOTE 1. All the values of A[31:24] must be "1".

LHF00L02 27

Rev. 0.05

Figure 15. Sector/Block Erase Cycle Timing Diagram (LPC Mode)

A[23:20] A[19:16] A[15:12] 1111b Tri-State 0000b

D[7:4]

D[3:0]

TAR

Start

Memory

Write

Cycle Address (BA) TAR Sync

Data Start next

2 Clocks

Load Address in 8 Clocks

LCLK

RST#

CE#

LFRAME#

LAD

3

-LAD

0

V

IH

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock

0000b

1 Clock 1 Clock

LCLK

RST#

CE#

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

1st.

Load Data "20" in 2 Clocks

Command

1 Clock

NOTE 2

XXXX XXXX XXXX

A[23:20] A[19:16] A[15:12] 1111b Tri-State 0000b

D[7:4]D[3:0]

TAR

Start

Memory

Write

Cycle Address (BA) TAR SyncData

2 Clocks

Load Address in 8 Clocks

LFRAME#

LAD

3

-LAD

0

V

IH

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock

1 Clock 1 Clock Load Data "D0"in 2 Clocks

2nd.

Internal

Operation Start

NOTE 2

XXXX XXXX XXXX

NOTE 1. All the values of A[31:24] must be "1".

NOTE 2. BA = Sector / Block Address : A11-A0 may be "0" or "1".

A[27:24]A[31:28]

NOTE 1

A[31:28] A[27:24]

LHF00L02 28

Rev. 0.05

Figure 16. Status Polling, Toggle Bit Timing Diagram (LPC Mode)

LCLK

RST#

CE#

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

A[23:20] A[19:16] A[15:12] 1111b Tri-State 0000b

D[7:4]D[3:0]

TAR

Start

Memory

Write

Cycle Address TAR SyncData

2 Clocks

Load Address in 8 Clocks

LFRAME#

LAD

3

-LAD

0

V

IH

V

IL

V

IH

V

IL

0000b 011Xb

1 Clock

1 Clock 1 Clock Load Data "D" in 2 Clocks

Internal Operation

Start

XXXX XXXX XXXX

RY/BY# V

OL

High Z

Write the last command (Program, Erase, etc.) to the device in LPC mode.

LCLK

RST#

CE#

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

A[23:20] A[19:16] A[15:12] 1111b Tri-State 0000b

TAR

Start

Memory

Cycle Address TAR Sync Data

2 Clocks

Load Address in 8 Clocks

LFRAME#

LAD

3

-LAD

0

V

IH

V

IL

V

IH

, V

OH

V

IL

, V

OL

0000b 010Xb

1 Clock

1 Clock 1 Clock Data Out 2 Clocks

RY/BY#

V

OL

During internal Operation (Program, Erase, etc.) which has not completed.

A[11:18] A[7:4] A[3:0] XXXXb

Next Start

0000b

1 Clock

LCLK

RST#

CE#

V

IH

V

IH

V

IL

V

IL

V

IH

V

IL

A[23:20] A[19:16] A[15:12] 1111b Tri-State 0000b

TAR

Start

Memory

Cycle Address TAR Sync Data

2 Clocks

Load Address in 8 Clocks

LFRAME#

LAD

3

-LAD

0

V

IH

V

IL

0000b 010Xb

1 Clock

1 Clock 1 Clock Data Out 2 Clocks

RY/BY#

Internal Operation (Program, Erase, etc.) completes.

A[11:18] A[7:4] A[3:0] XXXXb

Next Start

0000b

1 Clock

Read

V

OH

V

OH

V

IH

, V

OH

V

IL

, V

OL

V

OL

High Z

V

OH

D7#, D6#, XX

D7, D6, XX

NOTE 1. All the values of A[31:24] must be "1".

A[31:28] A[27:24]

NOTE 1

A[31:28] A[27:24]

LHF00L02 29

Rev. 0.05

3.2.5 Reset and Abort Operations (LPC Mode)

NOTES:

1. The device may reset if tRSTP < 100ns, but this is not guaranteed.

2. Sampled, not 100% tested.

3. There will be a latency of tRSTE if a reset/abort procedure is performed during an internal operation.

4. If RST#/INIT# asserted while a sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole

block lock bit, set boot lock bit and clear boot lock bits operations are not executing, the reset will complete within 100ns.

Reset and Abort Characteristics (LPC Mode)

VCC=3.0V~3.6V, TA=0°C~+85°C

Symbol Parameter Notes Min. Max. Unit

tPRSTH VCC 3.0V stable to RST#/INIT# High 2 100 ns

tPRSTL VCC 3.0V stable to RST#/INIT# Low 21 ms

tKRST Clock stable to RST#/INIT# Low 2 100 µs

tRSTP RST#/INIT# Pulse Width Low 1, 2 100 ns

RST#/INIT# Slew Rate 2 50 mV/ns

tRSTF RST#/INIT# Low to Output in High Z 2 48 ns

tRSTL RST#/INIT# High to LFRAME# Low 2, 3 1 µs

tABTL Abort Command to LFRAME# Low 2 60 ns

tRSTE RST#/INIT# Low to Reset during internal operation 2, 4 30 µs

LHF00L02 30

Rev. 0.05

Figure 17. Reset Operation by RST#/INIT# Timing Diagram (LPC Mode)

Figure 18. Abort Operation Timing Diagram (LPC Mode)

LCLK

V

CC

t

RSTP

RST# / INIT#

Erase or Program

operation aborted

t

PRSTL

t

RSTF

t

RSTE

RY/BY#

During Erase or Program

High Z

t

RSTL

LAD

3

-LAD

0

LFRAME#

V

IH

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

V

IL

V

OL

High Z

V

OH

V

CC

(Min.)

GND

t

PRST

H

t

KRST

LCLK

tABTL

LAD

3

-LAD

0

LFRAME#

Peripheral must stop driving 1111b

: ABORT command

Start

4 Clocks

V

IH

V

IH

V

IH

V

IL

V

IL

V

IL

0000b

LHF00L02 31

Rev. 0.05

3.2.6 AC Characteristics (A/A Mode) (1)

NOTES:

1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.

2. OE# may be delayed up to tAA − tOE after the rising edge of R/C# without impact to tAA.

3. Sampled, not 100% tested.

Read Characteristics (A/A Mode)

VCC=3.0V~3.6V, TA=0°C~+85°C

Symbol Parameter

Notes

Min. Max. Unit

tRC Read Cycle Time 250 ns

tRSTA RST# High Recovery to Row Address 1 µs

tAS Address Setup to R/C# 50 ns

tAH Address Hold from R/C# 50 ns

tAA Address to Output Delay 2 100 ns

tOE OE# to Output Delay 2 60 ns

tOLZ OE# to Output in Low Z 3 0 ns

tOHZ OE# to Output in High Z 3 35 ns

tOH Output Hold from Address 3 0 ns

LHF00L02 32

Rev. 0.05

Figure 19. Read Cycle Timing Diagram (A/A Mode)

Addresses

RST#

R/C#

WE#

Row Address

Data Valid

t

RSTA

Column Address

Row Address

Column Address

OE#

t

RC

t

AS

t

AH

t

AH

t

AS

DQ

7

-DQ

0

t

OLZ

t

OE

t

AA

t

OH

t

OHZ

VIH

VIL

VIH

VIL

VIH

VOL

VOH

High Z High Z

VIL

LHF00L02 33

Rev. 0.05

NOTES:

1. Typical values measured at VCC=3.3V and TA=+25°C. Assumes TBL#, WP# and corresponding lock bits are not set.

Subject to change based on device characterization.

2. The timing characteristics for reading the status register during sector/block erase, full chip erase, byte program, set whole

block lock bit, clear whole block lock bit, set boot lock bit and clear boot lock bits operations are the same as during read-

only operations. Refer to Read Characteristics (A/A Mode) for read-only operations.

3. Sampled, not 100% tested.

4. Refer to Table 12 for valid address and data for sector/block erase, full chip erase, byte program, set whole block lock bit,

clear whole block lock bit, set boot lock bit and clear boot lock bits.

5. Excludes external system-level overhead.

Write Characteristics (A/A Mode)

VCC=3.0V~3.6V, TA=0°C~+85°C

Symbol Parameter Notes Min. Typ.(1) Max. Unit

tWC Write Cycle Time 200 ns

tRSTA RST# High Recovery to Row Address 30 µs

tAS Address Setup to R/C# 4 50 ns

tAH Address Hold from R/C# 50 ns

tCWH R/C# to WE# High Time 50 ns

tOES OE# High Setup Time 20 ns

tOEH OE# High Hold Time 20 ns

tOEP OE# to Status Polling Delay 2 40 ns

tOET OE# to Toggle Bit Delay 2 40 ns

tWP WE# Pulse Width Low 100 ns

tWPH WE# Pulse Width High 100 ns

tDS Data Setup to WE# High 4 50 ns

tDH Data Hold from WE# High 5 ns

tIDA ID Access Time 150 ns

tRB WE# High to RY/BY# going Low 3 100 ns

tWQV1 Byte Program Time 3, 5 25 200 µs

tWQV2 Sector Erase Time 3, 5 0.6 5 s

tWQV3 Block Erase Time 3, 5 1.2 6 s

tWQV4 Full Chip Erase Time 3, 5 40 200 s

tSWBL Set Whole Block Lock Bit Time 3, 5 5 8 µs

tCWBL Clear Whole Block Lock Bit Time 3, 5 5 8 µs

tSTBL Set Boot Lock Bit Time 3, 5 35 200 µs

tCTBL Clear Boot Lock Bits Time 3, 5 0.4 1 s

LHF00L02 34

Rev. 0.05

Figure 20. Write Cycle Timing Diagram (A/A Mode)

Addresses

RST#

R/C#

OE#

Row Address

Data Valid

tRSTA

Column Address

WE#

tAS tAH

tAH tAS

DQ7-DQ0

High Z

tDS tDH

tCWH tWPH

tOEH

tWP

tOES

Row Address Column Address

SRD Valid

ID Valid

Data Valid

tWQV1,2,3,4

tRB

RY/BY#

VIH

VIL

VIH

VIL

VIH

, V

OH

VIL

, V

OL

VOL

V

OH

High Z High Z

tWC

tIDA

LHF00L02 35

Rev. 0.05

3.2.7 Reset Operations (A/A Mode)

NOTES:

1. The device may reset if tRSTP < 100ns, but this is not guaranteed.

2. Sampled, not 100% tested.

3. There will be a latency of tRSTE if a reset procedure is performed during an internal operation.

4. If RST# asserted while a sector/block erase, full chip erase, byte program, set whole block lock bit, clear whole block lock

bit, set boot lock bit and clear boot lock bits operations are not executing, the reset will complete within 100ns.

Reset Characteristics (A/A Mode)

VCC=3.0V~3.6V, TA=0°C~+85°C

Symbol Parameter Notes Min. Max. Unit

tPRSTH VCC 3.0V stable to RST# High 2 100 ns

tPRSTL VCC 3.0V stable to RST# Low 21 ms

tRSTP RST# Pulse Width Low 1, 2 100 ns

RST# Slew Rate 2 50 mV/ns

tRSTF RST# Low to Output in High Z 2 48 ns

tRSTA RST# High to Row Address Valid 2, 3 1 µs

tRSTE RST# Low to Reset during erase or program operation 2, 4 30 µs

LHF00L02 36

Rev. 0.05

Figure 21. Reset Operation Timing Diagram (A/A Mode)

Addresses

VCC

tRSTP

R/C#

RST#

Row Address

Erase or Program

operation aborted

tPRSTL

tRSTF

tRSTA

tRSTE

RY/BY#

Data Valid

V

CC

(Min.)

V

IH

V

IH

V

IH

GND

V

IL

V

IL

V

IL

V

OH

V

OL

DQ

7

-DQ

0

V

OL

VOH

High Z

t

PRST

H

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.

Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited

Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied.

ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND

FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible,

for any incidental or consequential economic or property damage.

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Phone: (1) 360-834-2500

Fax: (1) 360-834-8903

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Division of Sharp Electronics (Europe) GmbH

Sonninstrasse 3

20097 Hamburg, Germany

Phone: (49) 40-2376-2286

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Electronic Components & Devices

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Phone: (81) 6-6621-1221

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(Taiwan) Corporation

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Phone: (886) 2-2577-7341

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Alexandra Technopark,

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Phone: (65) 271-3566

Fax: (65) 271-3855

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Phone: (82) 2-711-5813 ~ 8

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(Shanghai) Co., Ltd.

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Phone: (86) 21-5854-7710/21-5834-6056

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Head Office:

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200131 P.R. China

Email: smc@china.global.sharp.co.jp

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3rd Business Division,

17/F, Admiralty Centre, Tower 1

18 Harcourt Road, Hong Kong

Phone: (852) 28229311

Fax: (852) 28660779

www.sharp.com.hk

Shenzhen Representative Office:

Room 13B1, Tower C,

Electronics Science & Technology Building

Shen Nan Zhong Road

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Phone: (86) 755-3273731

Fax: (86) 755-3273735