MB39C006APN-G-AMEFE1 - FUJITSU

1. General description

The NVT2001/02 are bi directional volt age level transla tors operational fro m 1.0 V to 3.6 V

(Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage translations be tween

1.0 V and 5 V without the need for a direction pin in open-drain or push -pull applications.

Bit widths ranging from 1-bit or 2-bit are offered for level translation application with

transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a

pull-up of 197 .

When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance

connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the

switch allows connections to be made with minimal propagation delay. Assuming the

higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is

limited to the voltage set by VREF A. When the An port is HIGH, the Bn port is pulled to the

drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows a

seamless translation between higher and lower voltages selected by the user witho ut the

need for directional control.

When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn I/O,

respectively, allowing bidirectional data flow between ports. When EN is LOW, the

translator switch is off, and a high-impe dance state exists between ports. The EN input

circuit is designed to be supplied by Vref(B). To ensure the high-impedanc e state during

power-up or power-down, EN must be LOW.

All channels have the same electrical characteristics and there is minimal deviation from

one output to another in voltage or propagation delay. This is a benefit over discrete

transistor voltage translation solutions, since the fabrication of the switch is symmetrical.

The translator provides excellent ESD protection to lower voltage devices, and at the

same time protects less ESD-resistant devices.

2. Features and benefits

Provides bidirectional voltage translation with no direction pin

Less than 1.5 ns maximum propagation delay

Allows voltage level translation between:

1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)

1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)

1.8 V Vref(A) and 3.3 V or 5 V Vref(B)

2.5 V Vref(A) and 5 V Vref(B)

3.3 V Vref(A) and 5 V Vref(B)

NVT2001; NVT2002

Bidirectional voltage level translator for open-drain and

push-pull applications

Rev. 2 — 26 October 2011 Product data sheet

Product data sheet Rev. 2 — 26 October 2011 2 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

Low 3.5  ON-state connection between input and output ports provides less signal

distortion

5 V tolerant I/O ports to support mixed-mode signal operation

High-impedance An and Bn pins for EN = LOW

Lock-up free operation

Flow through pinout for ease of printed-circuit board trace routing

ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

Packages offered: TSSOP, XQFN, XSON

3. Ordering information

[1] ‘X’ will change based on date code.

[2] GTL2002 = NVT2002.

4. Functional diagram

Table 1. Ordering information

Tamb =





C to +85



Type number Topside

mark Number

of bits Package

Name Description Version

NVT2001GM N1X[1] 1 XSON6 plastic extremely thin small outline package; no leads;

6 terminals; body 1 1.45 0.5 mm SOT886

NVT2002DP[2] N2002 2 TSSOP8 plastic thin shrink small outline package; 8 leads;

body width 3 mm SOT505-1

NVT2002GD[2] N02 2 XSON8U plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 20.5 mm SOT996-2

NVT2002GF[2] N2 2 XSON8 extremely thin small outline package; no leads;

8 terminals; body 1.35 10.5 mm SOT1089

Fig 1. Logic diagram of NVT2001; NVT2002 (positive logic)

002aae132

VREFA

GND

VREFB

NVT20xx

Product data sheet Rev. 2 — 26 October 2011 3 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

5. Pinning information

5.1 Pinning

5.1.1 1-bit in XSON6 package

5.1.2 2-bit in TSSOP8, XSON8U and XSON8 packages

Fig 2. Pin confi gurat io n for XSON6

NVT2001GM

VREFA

002aae211

GND

VREFB

Transparent top view

Fig 3. Pin configuration for TSSOP8 Fig 4. Pin configuration for XSON8U

Fig 5. Pin confi gurat io n for XSON8

NVT2002DP

GND EN

VREFA VREFB

A1 B1

A2 B2

002aae214

002aae215

NVT2002GD

Transparent top view

GND

VREFA

VREFB

002aaf317

NVT2002GF

Transparent top view

VREFA

GND

VREFB

A2 B2

Product data sheet Rev. 2 — 26 October 2011 4 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

5.2 Pin description

[1] 1-bit NVT2001 available in XSON6 package.

[2] 2-bit NVT2002 available in TSSOP8, XSON8U, XSON8 packages.

6. Functional description

Refer to Figure 1 “Logic diagr am of NVT2001; NVT2002 (positive logic)”.

6.1 Function table

[1] EN is controlled by the Vref(B) logic levels and should be at least 1 V higher than Vref(A) for best translator

operation.

Table 2. Pin description

Symbol Pin Description

NVT2001[1] NVT2002[2]

GND 1 1 ground (0 V)

VREFA 2 2 low-voltage side reference supply voltage for An

A1 3 3 low-voltage side; connect to VREFA through a pull-up

resistor

A2 - 4

B1 4 6 high-voltage side; connect to VREFB through a pull-up

resistor

B2 - 5

VREFB 5 7 high-voltage side reference supply voltage for Bn

EN 6 8 switch enable input; connect to VREFB and pull-up

through a high resistor

Table 3. Function selection (example)

H = HIGH level; L = LOW level.

Input EN[1] Function

HAn=Bn

L disconnect

Product data sheet Rev. 2 — 26 October 2011 5 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

7. Application design-in information

The NVT2001/02 can be used in level translation applications for interfacing devices or

systems operating at different interface voltages with one another. The NVT2001/02 is

ideal for use in applications whe re an open-dra in driver is conne cted to the dat a I/Os. The

NVT2001/02 can also be used in applica tions where a push-pu ll driver is connected to the

data I/Os.

7.1 Enable and disable

The NVT20xx has an EN input that is used to disable the device by setting EN LOW,

which places all I/Os in the high-impedance state.

[1] All typical values are at Tamb =25C.

(1) The applied voltages at Vref(A) and Vpu(D) should be such that Vref(B) is at least 1 V higher than

Vref(A) for best translator operation.

Fig 6. Typical application circ uit (switch always enabled)

Table 4. Application operating condition s

Refer to Figure 6.

Symbol Parameter Conditions Min Typ[1] Max Unit

Vref(B) reference voltage (B) Vref(A) +0.6 2.1 5 V

VI(EN) input voltage on pin EN Vref(A) +0.6 2.1 5 V

Vref(A) reference voltage (A) 0 1.5 4.4 V

Isw(pass) pass switch current - 14 - mA

Iref reference current transistor - 5 - A

Tamb ambient temperature operating in

free-air 40 - +85 C

002aae134

VREFA

GND

VREFB

8EN

NVT2002

200 kΩ

RPU RPU

pu(D)

= 3.3 V

(1)

C-BUS

DEVICE

SCL

SDA

GND

ref(A)

= 1.8 V

(1)

RPU RPU

C-BUS

MASTER

SCL

SDA

GND

Product data sheet Rev. 2 — 26 October 2011 6 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

(1) In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A) should be

such that Vref(B) is at least 1 V higher than Vref(A) for best translator operation.

(2) Note that the enable time and the disable time are essentially controlled by the RC time constant of

the capacitor and the 200 k resistor on the EN pin.

Fig 7. Typical application circ uit (switch enable control)

Fig 8. Bidirectional translation to multiple higher voltage levels

002aae135

VREFA

GND

VREFB

8EN

NVT2002

200 kΩ

RPU RPU

pu(D)

= 3.3 V

C-BUS

DEVICE

SCL

SDA

GND

ref(A)

= 1.8 V

(1)

RPU RPU

C-BUS

MASTER

SCL

SDA

GND

off

3.3 V enable signal

(1)

(2)

VREFB

002aae133

200 kΩ

CHIPSET I/O

VCC

5 V

totem pole or

open-drain I/O

GND

VREFA

B3 VCC

3.3 V

CPU I/O

VCORE

1.8 V

1.5 V

1.2 V

1.0 V

NVT20XX

CHIPSET I/O

SW B4A4

B5A5 SW

SW B6A6

Product data sheet Rev. 2 — 26 October 2011 7 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

7.2 Bidirectional translation

For the bidirectional clamping configuration (higher volt age to lower voltage or lower

voltage to h igher voltage), the EN input m ust be connected to VREFB and both pins pulled

to HIGH side Vpu(D) through a pull-up resistor (typically 200 k). This allows VREFB to

regulate the EN input. A filter capacitor on VREFB is recommended. The master output

driver can be totem pole or open-drain (pull-up resistors may be required) and the slave

device output can b e totem pole or open-drain (pu ll-up resistors are requ ired to pull the Bn

outputs to Vpu(D)). However, if either output is totem-pole, data must be unidirectional or

the outputs must be 3-stateable and be controlled by some direction-control mechanism

to prevent HIGH-to-LOW contentions in either dire ction. If both output s ar e open-drain, n o

direction control is needed.

The reference supply voltage (Vref(A)) is connected to the processor core power supply

voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V Vpu(D)

power supply, and Vref(A) is set between 1.0 V and (Vpu(D) 1 V), the output of ea ch An

has a maximum output voltage equal to VREFA, and the output of each Bn has a

maximum output voltage equal to Vpu(D).

7.3 Sizing pull-up resistor

The pull-up resistor value needs to limit the current through the pass transistor when it is

in the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the

current through the p ass transistor is higher than 15 mA, the pass volt age also is higher in

the ON state. To set the curre nt through each pass transistor at 15 mA, the pull-up resistor

value is calculated as:

Table 5 summarizes resistor reference voltages and currents at 15 mA, 10 mA, and 3 mA.

The resistor values shown in the +10 % column or a larger value should be used to

ensure that the p ass voltage of the tra nsistor would be 350 mV or less. The external driver

must be able to sink the total current from the resistors on both sides of the NVT20xx

device at 0.175 V, althou g h th e 15 mA only applies to current flowing through the

NVT20xx device.

[1] +10 % to compensate for VCC range and resistor tolerance.

RPU Vpu D 0.35 V–

0.015 A

--------------------------------------

Table 5. Pull-up resistor values

Calculated for VOL = 0.35 V; assumes output driver VOL = 0.175 V at stated current.

Vpu(D) Pull-up resistor value ()

64 mA 32 mA 15 mA 10 mA 3mA

Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1] Nominal +10 %[1]

5 V 310 341 465 512 1550 1705

3.3 V 197 217 295 325 983 1082

2.5 V 143 158 215 237 717 788

1.8 V 97 106 145 160 483 532

1.5 V 77 85 115 127 383 422

1.2 V 57 63 85 94 283 312

Product data sheet Rev. 2 — 26 October 2011 8 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

7.3.1 Maximum frequency calculation

The maximum freq uency is tota lly dependent u pon the sp ecifics of the application and the

device can operate > 33 MHz. Basically, the NVT20xx behaves like a wire with the

additional characte ristics of transistor device physics and should be capable of performing

at higher frequencies if used correctly.

Here are some guidelines to follow that will help maximize the performance of the device:

•Keep trace length to a minimum by placing the NVT20xx close to the processor.

•The trace length should have a time of flight less than half of the transition time to

reduce ringing an d re fle ctio n s .

•The faster the edge of the signal, the higher the chance for ringing.

•The higher the drive strength (up to 15 mA), the higher the frequency the device can

use.

In a 3.3 V to 1.8 V direction level shift, if the 3.3 V side is being driven by a totem pole type

driver no pull-up resistor is needed on the 3.3 V side. The capacitance and line length of

concern is on the 1.8 V side since it is driven through the ON resistance of the NVT20xx.

If the line length on the 1.8 V side is long enough there can be a reflection at the

chip/terminating end of the wir e when the transition time is shorter than the time of flight of

the wire because the NVT20xx looks like a high-impedance compared to the wire. If the

wire is not too long and the lumped capacitance is not excessive the signal will only be

slightly degraded by the series resistance added by passing through the NVT20xx. If the

lumped capacitance is large the rise time will deteriorate, the fall time is much less

affected and if the rise time is slowed down too much the duty cycle of the clock will be

degraded and at some point the clock will no longer be useful. So the principle design

consideration is to minimize the wire length and the capacitance on the 1.8 V side fo r the

clock path. A pull-u p resistor on the 1.8 V side can also be used to tr ade a slower fall tim e

for a faster rise time and can also reduce the overshoot in some cases.

7.3.1.1 Example maximum frequency

Question — W e need to make the PL L area of a new line card backwards comp atible and

need to need to convert one GTL signal to LVTTL, invert it, and convert it back to GTL.

The signal we want to convert is random in nature but will mostly be around 19 MHz with

very long periods of inactivity where either a HIGH or LOW state will be maintained. The

traces are 1 or 2 inches lon g with tra ce capacitance of about 2 pF pe r inch .

Answer — The frequency of the NVT20xx is limited by the capacitance of the part, the

capacitance of the traces and the pull-u p resistors used. The limiting ca se is pr obably th e

LOW-to-HIGH transition in the GTL to LVTTL direction, and there the use of the lowest

acceptable resistor values will minimize the rise time delay. Assuming 50 pF capacitance

and 220  resistance, the RC time constant is 11 ns (50 pF 220 ). With 19 MHz

corresponding to 50 ns period the NVT20xx will support this application.

Product data sheet Rev. 2 — 26 October 2011 9 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

8. Limiting values

[1] The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp

current ratings are observed.

[2] Low duty cycle pulses, not DC because of heating.

9. Recommended operating conditions

[1] Vref(A) Vref(B) 1 V for best results in level shifting applications.

10. Static characteristics

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Over operating free-air temperature range.

Symbol Parameter Conditions Min Max Unit

Vref(A) reference voltage (A) 0.5 +6 V

Vref(B) reference voltage (B) 0.5 +6 V

VIinput voltage 0.5[1] +6 V

VI/O voltage on an input/output pin 0.5[1] +6 V

Ich channel current (DC) - 128 mA

IIK input clamping current VI<0V 50 - mA

IOK output clamping current [2] 50 +50 mA

Tstg storage temperature 65 +150 C

Table 7. Operating conditions

Symbol Parameter Conditions Min Max Unit

VI/O voltage on an input/output pin An, Bn 0 5.5 V

Vref(A) reference voltage (A) VREFA [1] 05.4V

Vref(B) reference voltage (B) VREFB [1] 05.5V

VI(EN) input voltage on pin EN 0 5.5 V

Isw(pass) pass switch current - 64 mA

Tamb ambient temperature operating in free-air 40 +85 C

Table 8. Static characteristics

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

VIK input clamping voltage II=18 mA; VI(EN) =0V - - 1.2 V

IIH HIGH-level input current VI=5V; V

I(EN) =0V - - 5 A

Ci(EN) input capacitance on pin EN VI= 3 V or 0 V - 7.1 - pF

Cio(off) off-state input/output capacitance An, Bn; VO=3Vor0V;

VI(EN) =0V - 46pF

Cio(on) on-state input/output capacitance An, Bn; VO=3Vor0V;

VI(EN) =3V - 9.3 12.5[2] pF

Product data sheet Rev. 2 — 26 October 2011 10 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

[1] All typical values are at Tamb =25C.

[2] Not production tested, maximum value based on characterization data of typical parts.

[3] Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is

determined by the lowest voltage of the two terminals.

[4] See curves in Figure 9 for typical temperature and VI(EN) behavior.

[5] Guaranteed by design.

Ron ON-state resistance An, Bn; VI=0V;I

O=64mA;

VI(EN) =4.5V [3][4][5] 12.45.0

VI=2.4V; I

O=15mA;

VI(EN) =4.5V [3][4] -4.87.5

Table 8. Static characteristics …continued

Tamb =





C to +85



C, unless otherwise specified.

Symbol Parameter Conditions Min Typ[1] Max Unit

a. IO=64mA; V

I=0V b. I

O=15mA; V

I=2.4V; V

I(EN) =4.5V

c. IO=15mA; V

I= 2.4 V; VI(EN) =3.0V d. I

O=15mA; V

I=1.7V; V

I(EN) =2.3V

Fig 9. Typical ON-state resistance versus ambient temperature

Tamb (°C)

−40 100−20

002aaf313

0 20 40 60 80

Ron(typ)

(Ω)

VI(EN) = 1.5 V

2.3 V

3.0 V

4.5 V

Tamb (°C)

−40 100−20

002aaf314

0 20 40 60 80

Ron(typ)

(Ω)

Tamb (°C)

−40 100−20

002aaf315

0 20 40 60 80

Ron(typ)

(Ω)

Tamb (°C)

−40 100−20

002aaf316

0 20 40 60 80

Ron(typ)

(Ω)

Product data sheet Rev. 2 — 26 October 2011 11 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

11. Dynamic characteristics

11.1 Open-drain drivers

[1] See graphs based on Ron typical and Cio(on) +C

L=50pF.

Table 9. Dynamic characteristics for open-drain drivers

Tamb =





Cto+85



C; VI(EN) =V

ref(B); Rbias(ext) = 200 k



; CVREFB =0.1



F; unless otherwise

specified.

Symbol Parameter Conditions Min Typ Max Unit

Refer to Figure 12

tPLH LOW to HIGH

propagation delay from (input) Bn

to (output) An [1] Ron  (CL + Cio(on))ns

tPHL HIGH to LOW

propagation delay from (input) Bn

to (output) An Ron  (CL + Cio(on))ns

Fig 10. AC test setup Fig 11. Example of typical AC waveform

002aaf347

DUT

EN VREFB

VREFA

1.5 V

200 kΩ

SIGNAL

GENERATOR

5.5 V

0.1 μF

1.5 V swing

50 pF 450 Ω

500 Ω

6.6 V

1 V/div

40 ns/div

002aaf348

GND

a. Load circuit b. Timing diagram; high-impedance scope probe

used

S2 = translating down, and same voltage.

CL includes probe and jig capacitance.

All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Zo=50; tr2ns; t

f2ns.

The outputs are measured one at a time, with one transition per measurement.

Fig 12. Load circuit for outputs

002aab845

VTT

S2 (open)

from output under test

002aab846

input

output

Product data sheet Rev. 2 — 26 October 2011 12 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

12. Performance curves

tPLH up-translation is typically dominated by the RC time constant, i.e.,

CL(tot) RPU =50pF197 = 9.85 ns, but the Ron CL(tot) =50pF5=0.250ns.

tPHL is typically domina te d by the external pull-d o wn dr ive r + Ron, which is typically small

compared to the tPLH in an up-translation case.

Enable/disable times are dominated by the RC time constant on the EN pin since the

transistor turn off is on the order of ns, but the enable RC is on the order of ms.

Fall time is dominated by the external pull-down driver with only a slight Ron addition.

Rise time is dominated by the RPU CL.

Skew time within the part is virtually non-existent, dominated by the difference in bond

wire lengths, which is typically small compared to the board-level ro uting differences.

Maximum data rate is dominated by the system cap acitance and pull-up resistors.

(1) VI(EN) = 1.5 V; IO=64mA; V

I=0V.

(2) VI(EN) = 4.5 V; IO=15mA; V

I=2.4V.

(3) VI(EN) = 2.3 V; IO=64mA; V

I=0V.

(4) VI(EN) = 3.0 V; IO=64mA; V

I=0V.

(5) VI(EN) = 4.5 V; IO=64mA; V

I=0V.

Fig 13. Typical capacitance versus pr opagation delay

C (pF)

0 1008040 6020

002aaf349

0.4

0.2

0.6

0.8

tPD

(ns)

(1)

(2)

(3)

(5)

(4)

Product data sheet Rev. 2 — 26 October 2011 13 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

13. Package outline

Fig 14. Package outline SOT886 (XSON6)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT886 MO-252

SOT886

04-07-15

04-07-22

DIMENSIONS (mm are the original dimensions)

XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 1.5

1.4 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

6×

(2)

4×

(2)

Product data sheet Rev. 2 — 26 October 2011 14 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

Fig 15. Package outline SOT505-1 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.45

0.25 0.28

0.15 3.1

2.9 3.1

2.9 0.65 5.1

4.7 0.70

0.35 6°

0°

0.1 0.10.10.94

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.7

0.4

SOT505-1 99-04-09

03-02-18

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1

1.1

pin 1 index

Product data sheet Rev. 2 — 26 October 2011 15 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

Fig 16. Package outline SOT996-2 (XSON8U)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT996-2 - - -- - -

SOT996-2

07-12-18

07-12-21

UNIT A

max

mm 0.5 0.05

0.00 0.35

0.15 3.1

2.9 0.5 1.5 0.5

0.3 0.6

0.4 0.1 0.05

DIMENSIONS (mm are the original dimensions)

XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

0 1 2 mm

scale

b D

2.1

1.9

E e e1L L1

0.15

0.05

L2v w

0.05

y y1

0.1

eAC B

vMCw M

terminal 1

index area

B A

detail X

AA1

Product data sheet Rev. 2 — 26 October 2011 16 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

Fig 17. Package outline SOT1089 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1089 MO-252

sot1089_po

10-04-09

10-04-12

Unit

mm max

nom

min

0.5 0.04 1.40

1.35

1.30

1.05

1.00

0.95 0.55 0.35 0.35

0.30

0.27

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm SOT1089

A1bL

0.40

0.35

0.32

0.20

0.15

0.12

DEee

0 0.5 1 mm

scale

terminal 1

index area

detail X

terminal 1

index area

(4×)(2)

(8×)(2)

Product data sheet Rev. 2 — 26 October 2011 17 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

14. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reflow

soldering description”.

14.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

14.2 Wave and reflow soldering

W ave soldering is a joinin g technology in which the joint s are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature profile. Leaded packages,

packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

•Board specifications, including the board finish, solder masks and vias

•Package footprints, including solder thieves and orientation

•The moisture sensitivity level of the packages

•Package placement

•Inspection and repair

•Lead-free soldering versus SnPb soldering

14.3 Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and flux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

•Solder bath specifications, including temperature and impurities

Product data sheet Rev. 2 — 26 October 2011 18 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

14.4 Reflow soldering

Key characteristics in reflow soldering are:

•Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to

higher minimum peak temperatures (see Figure 18) than a SnPb process, thus

reducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reflow temperature profile; this profile includes preheat, reflow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enoug h for the solder to make reliable solder joint s (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classified in accordance with

Table 10 and 11

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 18.

Table 10. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350  350

< 2.5 235 220

 2.5 220 220

Table 11. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (C)

Volume (mm3)

< 350 350 to 2000 > 2000

< 1.6 260 260 260

1.6 to 2.5 260 250 245

> 2.5 250 245 245

Product data sheet Rev. 2 — 26 October 2011 19 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

15. Soldering: reflow soldering footprint for SOT1089

MSL: Moisture Sensitivity Level

Fig 18. Temperature profiles for large and small components

001aac844

temperature

time

minimum peak temperature

= minimum soldering temperature

maximum peak temperature

= MSL limit, damage level

peak

temperature

Fig 19. SOT1089 reflow soldering footprint

sot1089_fr

Footprint information for reflow soldering of XSON8 package SOT1089

solder resist

occupied area

solder paste = solder land

Dimensions in mm

0.15

(8×)

0.35

(3×)

0.25

(8×)

0.5

(8×)

0.6

(8×)

0.7 1.4

1.4

Product data sheet Rev. 2 — 26 October 2011 20 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

16. Abbreviations

17. Revision history

Table 12. Abbreviations

Acronym Description

CDM Charged Device Model

ESD ElectroStatic Discharge

GTL Gunning Transceiver Logic

HBM Human Body Model

I2C-bus Inter-Integrated Circuit bus

I/O Input/Output

LVTTL Low Voltage Transistor-Transistor Lo gic

MM Machine Model

PRR Pulse Repetition Rate

RC Resistor-Capacitor network

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

NVT2001_NVT20 02 v.2 2011102 6 Product data sheet - NVT2001_NVT2002 v.1

Modifications: •Section 2 “Features and benefits”, 10th bullet item: removed phrase “200 V MM per

JESD22-A115”

•Type number NVT2002GM (XQFN8U, SOT902-1) removed from data sheet; this affects:

–Section 2 “Features and benefits”, last bullet item: removed “XQFN”

–Section 5.1.2 “2- bit in TSSOP8, XSON8U and XSON8 packages”: removed pin

configuration for XQFN8U

–Table 2 “Pin description”, Table note [2]: removed “XQFN8U”

–Section 13 “ Package outline”: removed package outline SOT902 -1

•Type number NVT2 002TL (HXSON8U, SOT983-1) removed from data sheet; this affects:

–Section 2 “Features and benefits”, last bullet item: removed “HXSON”

–Section 5.1.2 “2- bit in TSSOP8, XSON8U and XSON8 packages”: removed pin

configuration for HXSON8U

–Table 2 “Pin description”, Table note [2]: removed “HXSON8U”

–Section 13 “ Package outline”: removed package outline SOT983 -1

NVT2001_NVT20 02 v.1 201008 30 Product data sheet - -

Product data sheet Rev. 2 — 26 October 2011 21 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

18. Legal information

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsisten cy or conf lict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

18.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indire ct, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charge s) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descript i ons, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suit able for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or application s and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as def ined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby exp r essly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from competent authorities.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification fo r product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 2 — 26 October 2011 22 of 23

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product cl aims resulting from custome r design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

18.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors NVT2001; NVT2002

Bidirectional voltage level translator

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 26 October 2011

Document identifier : NVT2001_NVT2002

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

20. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.1.1 1-bit in XSON6 package. . . . . . . . . . . . . . . . . . 3

5.1.2 2-bit in TSSOP8, XSON8U and

XSON8 packages. . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

6 Functional description . . . . . . . . . . . . . . . . . . . 4

6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 App lication design -in information . . . . . . . . . . 5

7.1 Enable and disable. . . . . . . . . . . . . . . . . . . . . . 5

7.2 Bidirectional translation . . . . . . . . . . . . . . . . . . 7

7.3 Sizing pull-up resistor . . . . . . . . . . . . . . . . . . . . 7

7.3.1 Maximum frequency calculation. . . . . . . . . . . . 8

7.3.1.1 Example maximum frequency . . . . . . . . . . . . . 8

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

9 Recommended operating conditions. . . . . . . . 9

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9

11 Dynamic characteristics . . . . . . . . . . . . . . . . . 11

11.1 Open-drain drivers . . . . . . . . . . . . . . . . . . . . . 11

12 Performance curves . . . . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

14 Soldering of SMD packages . . . . . . . . . . . . . . 17

14.1 Introduction to soldering. . . . . . . . . . . . . . . . . 17

14.2 Wave and reflow soldering . . . . . . . . . . . . . . . 17

14.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 17

14.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 18

15 Soldering: reflow soldering footprint for

SOT1089 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

16 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

17 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20

18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21

18.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21

18.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

18.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

18.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

19 Contact information. . . . . . . . . . . . . . . . . . . . . 22

20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23