Revised March 2000 DM74LS85 4-Bit Magnitude Comparator General Description Features These 4-bit magnitude comparators perform comparison of straight binary or BCD codes. Three fully-decoded decisions about two, 4-bit words (A, B) are made and are externally available at three outputs. These devices are fully expandable to any number of bits without external gates. Words of greater length may be compared by connecting comparators in cascade. The A > B, A < B, and A = B outputs of a stage handling less-significant bits are connected to the corresponding inputs of the next stage handling more-significant bits. The stage handling the leastsignificant bits must have a high-level voltage applied to the A = B input. The cascading path is implemented with only a two-gate-level delay to reduce overall comparison times for long words. Typical power dissipation 52 mW Typical delay (4-bit words) 24 ns Ordering Code: Order Number Package Number Package Description DM74LS85M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS85N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Connection Diagram (c) 2000 Fairchild Semiconductor Corporation DS006379 www.fairchildsemi.com DM74LS85 4-Bit Magnitude Comparator August 1986 DM74LS85 Function Table Comparing Cascading Inputs Inputs Outputs A3, B3 A2, B2 A1, B1 A0, B0 A>B A<B A=B A>B A<B A3 > B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 > B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A3 = B3 A2 = B2 A1 > B1 X X X X H L L A3 = B3 A2 = B2 A1 < B1 X X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H A3 = B3 A2 = B2 A1 = B1 A0 = B0 H H L L L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L L H H L H = HIGH Level, L = LOW Level, X = Don't Care Logic Diagram www.fairchildsemi.com 2 A=B Supply Voltage Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage 7V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current -0.4 mA IOL LOW Level Output Current 8 mA TA Free Air Operating Temperature 70 C 2 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = -18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min 2.7 IOL = 4 mA, VCC = Min II IIH IIL Typ (Note 2) Max Units -1.5 V 3.4 V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max A<B Input Voltage VI = 7V A>B 0.1 Others 0.3 20 0.1 HIGH Level VCC = Max A<B Input Current VI = 2.7V A>B 20 Others 60 LOW Level VCC = Max A<B -0.4 Input Current VI = 0.4V A>B -0.4 Others -1.2 IOS Short Circuit Output Current VCC = Max (Note 3) ICC Supply Current VCC = Max (Note 4) V -20 10 mA A mA -100 mA 20 mA Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all outputs OPEN, A = B grounded and all other inputs at 4.5V. 3 www.fairchildsemi.com DM74LS85 Absolute Maximum Ratings(Note 1) DM74LS85 Switching Characteristics at VCC = 5V and TA = 25C Symbol Parameter From To Number of Input Output Gate Levels RL = 2 k CL = 15 pF Min tPLH Propagation Delay Time Any A or B A < B, LOW-to-HIGH Level Output Data Input A>B tPLH 42 4 40 40 3 30 40 A=B 4 30 40 A < B or A = B A>B 1 22 26 ns A < B or A = B A>B 1 17 26 ns A=B A=B 2 20 25 ns A=B A=B 2 17 26 ns A > B or A = B A<B 1 22 26 ns A > B or A = B A<B 1 17 26 ns Any A or B A < B, HIGH-to-LOW Level Output Data Input A>B Propagation Delay Time tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Units Max 36 Propagation Delay Time LOW-to-HIGH Level Output CL = 50 pF Min 3 A=B tPHL Max 4 ns ns DM74LS85 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com DM74LS85 4-Bit Magnitude Comparator Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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