Low Cost, General-Purpose
High Speed JFET Amplifier
AD825
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
High speed
41 MHz, −3 dB bandwidth
125 V/µs slew rate
80 ns settling time
Input bias current of 20 pA and noise current of 10 fA/√Hz
Input voltage noise of 12 nV/√Hz
Fully specified power supplies: ±5 V to ±15 V
Low distortion: −76 dB at 1 MHz
High output drive capability
Drives unlimited capacitance load
50 mA min output current
No phase reversal when input is at rail
Available in 8-lead SOIC
APPLICATIONS
CCDs
Low distortion filters
Mixed gain stages
Audio amplifiers
Photo detector interfaces
ADC input buffers
DAC output buffers
CONNECTION DIAGRAMS
NC = NO CONNECT
AD825
TOP VIEW
(Not to Scale)
NC
1
–IN
2
+IN
3
–
V
S4
NC
8
+V
S
7
OUTPUT
6
NC
5
00876-E-001
Figure 1. 8-Lead Plastic SOIC (R) Package
NC
1
NC
2
NC
3
–INPUT
4
+INPUT
5
–V
S6
NC
7
NC
8
NC
10
NC
16
NC
15
NC
14
+V
S
13
OUTPUT
12
NC
11
NC
9
AD825
TOP VIEW
(Not to Scale)
NC = NO CONNECT
00876-E-002
Figure 2. 16-Lead Plastic SOIC (R-16) Package
GENERAL DESCRIPTION
The AD825 is a superbly optimized operational amplifier for
high speed, low cost, and dc parameters, making it ideally suited
for a broad range of signal conditioning and data acquisition
applications. The ac performance, gain, bandwidth, slew rate,
and drive capability are all very stable over temperature. The
AD825 also maintains stable gain under varying load
conditions.
The unique input stage has ultralow input bias current and
input current noise. Signals that go to either rail on this high
performance input do not cause phase reversals at the output.
These features make the AD825 a good choice as a buffer for
MUX outputs, creating minimal offset and gain errors.
The AD825 is fully specified for operation with dual ±5 V and
±15 V supplies. This power supply flexibility, and the low supply
current of 6.5 mA with excellent ac characteristics under all
supply conditions, makes the AD825 well-suited for many
demanding applications.
00876-E-003
10V 200ns
10V
Figure 3. Performance with Rail-to-Rail Input Signals
AD825
Rev. F | Page 2 of 12
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Pin Configurations ........................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Driving Capacitive Loads .............................................................. 10
Theory of Operation ...................................................................... 10
Input Consideration................................................................... 10
Grounding and Bypassing......................................................... 10
Second-Order Low-Pass Filter.................................................. 11
Outline Dimensions ....................................................................... 12
Ordering Guide........................................................................... 12
REVISION HISTORY
10/04—Data Sheet Changed from Rev. E to Rev. F
Changes to Figure 1......................................................................... 1
Changes to Figure 4......................................................................... 5
Changes to Figure 21....................................................................... 8
3/04—Data Sheet Changed from Rev. D to Rev. E
Changes to Specifications............................................................... 3
Addition of 16-Lead SOIC Pin Configuration ............................ 5
Changes to Figure 27....................................................................... 9
Updated Outline Dimensions...................................................... 12
Updated Ordering Guide.............................................................. 12
2/01—Data Sheet Changed from Rev. C to Rev. D
Addition of 16-lead SOIC package (R-16)
Connection Diagram ...................................................................... 4
Addition to Absolute Maximum Ratings ..................................... 4
Addition to Ordering Guide (R-16).............................................. 4
Addition of 16-lead SOIC package (R-16)
Outline Dimensions......................................................................11
AD825
Rev. F | Page 3 of 12
SPECIFICATIONS
All limits are determined to be at least four standard deviations away from mean value. At TA = 25°C, VS = ±15 V, unless otherwise noted.
Table 1.
AD825A
Parameter Conditions VS Min Typ Max Unit
DYNAMIC PERFORMANCE
Unity Gain Bandwidth ±15 V 23 26 MHz
Bandwidth for 0.1 dB Flatness Gain = +1 ±15 V 18 21 MHz
−3 dB Bandwidth Gain = +1 ±15 V 44 46 MHz
Slew Rate RLOAD = 1 kΩ, G = +1 ±15 V 125 140 V/µs
Settling Time to 0.1% 0 V to 10 V Step, AV = −1 ±15 V 150 180 ns
to 0.1% 0 V to 10 V Step, AV = −1 ±15 V 180 220 ns
Total Harmonic Distortion FC = 1 MHz, G = −1 ±15 V −77 dB
Differential Gain Error NTSC ±15 V 1.3 %
(RLOAD = 150 Ω) Gain = +2
Differential Phase Error NTSC ±15 V 2.1 Degrees
(RLOAD = 150 Ω) Gain = +2
INPUT OFFSET VOLTAGE ±15 V 1 2 mV
T
MIN to TMAX 5 mV
Offset Drift 10 µV/°C
INPUT BIAS CURRENT ±15 V 15 40 pA
T
MIN 5 pA
T
MAX 700 pA
INPUT OFFSET CURRENT ±15 V 20 30 pA
T
MIN 5 pA
T
MAX 440 pA
OPEN-LOOP GAIN VOUT = ±10 V ±15 V
R
LOAD = 1 kΩ 70 76 dB
V
OUT = ±7.5 V ±15 V
R
LOAD = 1 kΩ 70 76 dB
V
OUT = ±7.5 V ±15 V
R
LOAD = 150 kΩ (50 mA Output) 68 74 dB
COMMON-MODE REJECTION VCM = ±10 ±15 V 71 80 dB
INPUT VOLTAGE NOISE f = 10 kHz ±15 V 12 nV/√Hz
INPUT CURRENT NOISE f = 10 kHz ±15 V 10 fA/√Hz
INPUT COMMON-MODE VOLTAGE RANGE ±15 V ±13.5 V
OUTPUT VOLTAGE SWING RLOAD = 1 kΩ ±15 V 13 ±13.3 V
R
LOAD = 500 Ω ±15 V 12.9 ±13.2 V
Output Current ±15 V 50 mA
Short-Circuit Current ±15 V 100 mA
INPUT RESISTANCE 5 ×1011 Ω
INPUT CAPACITANCE 6 pF
OUTPUT RESISTANCE Open Loop 8 Ω
POWER SUPPLY
Quiescent Current ±15 V 6.5 7.2 mA
T
MIN to TMAX ±15 V 7.5 mA
AD825
Rev. F | Page 4 of 12
All limits are determined to be at least four standard deviations away from mean value. At TA = 25°C, VS = ±5 V unless otherwise noted.
Table 2.
AD825A
Parameter Conditions VS Min Typ Max Unit
DYNAMIC PERFORMANCE
Unity Gain Bandwidth ±5 V 18 21 MHz
Bandwidth for 0.1 dB Flatness Gain = +1 ±5 V 8 10 MHz
−3 dB Bandwidth Gain = +1 ±5 V 34 37 MHz
Slew Rate RLOAD = 1 kΩ, G = −1 ±5 V 115 130 V/µs
Settling Time to 0.1% −2.5 V to +2.5 V ±5 V 75 90 ns
to 0.01% −2.5 V to +2.5 V ±5 V 90 110 ns
Total Harmonic Distortion FC = 1 MHz, G = −1 ±5 V −76 dB
Differential Gain Error NTSC ±5 V 1.2 %
(RLOAD = 150 Ω) Gain = +2
Differential Phase Error NTSC ±5 V 1.4 Degrees
(RLOAD = 150 Ω) Gain = +2
INPUT OFFSET VOLTAGE ±5 V 1 2 mV
T
MIN to TMAX 5 mV
Offset Drift 10 µV/°C
INPUT BIAS CURRENT ±5 V 10 30 pA
T
MIN 5 pA
T
MAX 600 pA
INPUT OFFSET CURRENT ±5 V 15 25 pA
T
MIN 5 pA
Offset Current Drift TMAX 280 pA
OPEN-LOOP GAIN VOUT = ±2.5 ±5 V
R
LOAD = 500 Ω 64 66 dB
R
LOAD = 150 Ω 64 66 dB
COMMON-MODE REJECTION VCM = ±2 V ±5 V 69 80 dB
INPUT VOLTAGE NOISE f = 10 kHz ±5 V 12 nV/√Hz
INPUT CURRENT NOISE f = 10 kHz ±5 V 10 fA/√Hz
INPUT COMMON-MODE VOLTAGE RANGE ±5 V ± 3.5 V
OUTPUT VOLTAGE SWING RLOAD = 500 Ω +3.2 ±3.4 V
R
LOAD = 150 Ω ±5 V +3.1 ±3.2 V
Output Current ±5 V 50 mA
Short-Circuit Current 80 mA
INPUT RESISTANCE 5 ×1011 Ω
INPUT CAPACITANCE 6 pF
OUTPUT RESISTANCE Open Loop 8 Ω
POWER SUPPLY
Quiescent Current ±5 V 6.2 6.8 mA
T
MIN to TMAX ±5 V 7.5 mA
POWER SUPPLY REJECTION VS = ±5 V to ±15 V 76 88 dB
AD825
Rev. F | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation1
Small Outline (R) See Figure 6
Input Voltage (Common Mode) ±VS
Differential Input Voltage ±VS
Output Short-Circuit Duration See Figure 6
Storage Temperature Range (R, R-16) −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature Range
(Soldering 10 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1 Specification is for device in free air:
8-lead SOIC package: θJA = 155°C/W
16-lead SOIC package: θJA = 85°C/W
PIN CONFIGURATIONS
NC = NO CONNECT
AD825
TOP VIEW
(Not to Scale)
NC
1
–IN
2
+IN
3
–
V
S4
NC
8
+V
S
7
OUTPUT
6
NC
5
00876-E-001
Figure 4. 8-Lead SOIC
NC
1
NC
2
NC
3
–INPUT
4
+INPUT
5
–V
S6
NC
7
NC
8
NC
10
NC
16
NC
15
NC
14
+V
S
13
OUTPUT
12
NC
11
NC
9
AD825
TOP VIEW
(Not to Scale)
NC = NO CONNECT
00876-E-002
Figure 5. 16-Lead SOIC
AMBIENT TEMPERATURE (°C)
2.0
1.5
0
–50 90–40–30–20–100 102030 5060708040
1.0
0.5 8-LEAD SOIC PACKAGE
T
J
= 150°C
MAXIMUM POWER DISSIPATION (W)
2.5
16-LEAD SOIC PACKAGE
00876-E-004
Figure 6. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD825
Rev. F | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
R
L
= 150ΩR
L
= 1kΩ
SUPPLY VOLTAGE (V)
20
–20 0182
OUTPUT SWING (V)
4 6 8 10 12 14 16
15
0
–5
–10
–15
10
5
00876-E-005
Figure 7. Output Voltage Swing vs. Supply Voltage
LOAD RESISTANCE (Ω)
0 100
OUTPUT SWING (V)
15
0
–5
–10
–15
10
5
200 300 400 500 600 700 800 900 1000
V
S
= ±15V
V
S
= ±15V
V
S
= ±5V
00876-E-006
Figure 8. Output Voltage Swing vs. Load Resistance
SUPPLY VOLTAGE (±V)
7.0
6.5
5.0020
FREQUENCY (Hz)
100
1
0.01
100 10M1k
OUTPUT IMPEDANCE (Ω)
10k 100k 1M
10
0.1
00876-E-008
2
SUPPLY CURRENT (mA)
4 6 8 10 12 14 16 18
6.0
5.5
–40°
+25°
+85°
00876-E-007
Figure 9. Quiescent Supply Current vs. Supply Voltage
for Various Temperatures
Figure 10. Closed-Loop Output Impedance vs. Frequency
TEMPERATURE (°C)
35
–60 140
–40
UNITY GAIN BANDWIDTH (MHz)
–20 0 20 40 80 100 120
30
15
10
5
0
25
20
20
40
60
80
PHASE MARGIN (°C)
60
BANDWIDTH
PHASE MARGIN
00876-E-009
Figure 11. Unity Gain Bandwidth and Phase Margin vs. Temperature
FREQUENCY (Hz)
80
70
0
1k 100M10k
OPEN-LOOP GAIN (dB)
100k 1M 10M
60
50
10
40
30
20
OPEN-LOOP PHASE (Degrees)
180
135
90
45
0
V
S
= ±15V
V
S
= ±5V
00876-E-010
Figure 12. Open-Loop Gain and Phase Margin vs. Frequency
AD825
Rev. F | Page 7 of 12
LOAD RESISTANCE (
Ω
)
80
75
60
10 10k1k
OPEN-LOOP GAIN (dB)
70
65
V
S
= ±15V
V
S
= ±5V
00876-E-011
Figure 13. Open-Loop Gain vs. Load Resistance
FREQUENCY (Hz)
10k 10M100k
PSR (dB)
1M
10
0
–90
–10
–20
–30
–40
–50
–60
–70
–80
–PSRR
+PSRR
00876-E-012
Figure 14. Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
10 10M1k
CMR (dB)
100k
130
120
30
110
100
90
80
70
60
50
40
100 10k 1M
V
S
= ±15V
V
S
= ±5V
00876-E-013
Figure 15. Common-Mode Rejection vs. Frequency
FREQUENCY (Hz)
30
20
0
10k 100k
OUTPUT VOLTAGE (V p-p)
1M 10M
10
R
L
= 1kΩ
R
L
= 150Ω
00876-E-014
Figure 16. Large Signal Frequency Response; G = +2
OUTPUT SWING (0 to ±V)
200
80
010 –108
SETTLING TIME (ns)
6 4 2 0 –2 –4 –6 –8
180
100
60
20
140
120
40
160
0.01%
0.1%
0.01%
0.1%
00876-E-015
Figure 17. Output Swing and Error vs. Settling Time
FREQUENCY (Hz)
–50
–55
–85
100k 10M1M
DISTORTION (dB)
–60
–65
–70
–75
–80
SECOND
THIRD
00876-E-016
Figure 18. Harmonic Distortion vs. Frequency
AD825
Rev. F | Page 8 of 12
TEMPERATURE (°C)
100
–60 140
–40
SLEW RATE (V/µs)
–20 0 20 40 80 100 120
80
20
0
60
40
120
140
160
±5V
±15V
60
00876-E-017
Figure 19. Slew Rate vs. Temperature
1k 100k 10M10k 1M
V
OUT
V
IN
V
S
±5V
±15V
0.1dB FLATNESS
10MHz
21MHz
FREQUENCY (Hz)
GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
00876-E-018
Figure 20. Closed-Loop Gain vs. Frequency, Gain = +1
1k 100k 10M10k 1M
V
OUT
V
IN
V
S
±5V
±15V
0.1dB FLATNESS
7.7MHz
9.8MHz
FREQUENCY (Hz)
GAIN (dB)
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
00876-E-019
1kΩ1kΩ
Figure 21. Closed-Loop Gain vs. Frequency, Gain = −1
TEKTRONIX
P6204 FET
PROBE
HP PULSE (LS)
OR
FUNCTION (SS)
GENERATOR 50ΩR
L
V
OUT
V
IN
TEKTRONIX
7A24
PREAMP
AD825
7
4
3
6
2
+V
S
0.01µF
10µF
–V
S
0.01µF
10µF
00876-E-020
Figure 22. Noninverting Amplifier Connection
5V
5V
100ns
00876-E-021
Figure 23. Noninverting Large Signal Pulse Response, RL = 1 kΩ
200mV
200mV
50ns
00876-E-022
Figure 24. Noninverting Small Signal Pulse Response, RL = 1 kΩ
AD825
Rev. F | Page 9 of 12
5V
5V
100ns
00876-E-023
Figure 25. Noninverting Large Signal Pulse Response, RL = 150 Ω
200mV
200mV
50ns
00876-E-024
Figure 26. Noninverting Small Signal Pulse Response, RL = 150 Ω
TEKTRONIX
P6204 FET
PROBE
HP PULSE
GENERATOR
50Ω
R
IN
1kΩ
R
L
V
OUT
V
IN
TEKTRONIX
7A24
PREAMP
AD825
7
4
3
6
2
+V
S
0.01µF
10µF
–V
S
0.01µF
10µF
00876-E-025
1kΩ
Figure 27. Inverting Amplifier Connection
5V
5V
100ns
00876-E-026
Figure 28. Inverting Large Signal Pulse Response, RL = 1 kΩ
00876-E-027
50ns200mV
200mV
Figure 29. Inverting Small Signal Pulse Response, RL = 1 kΩ
AD825
Rev. F | Page 10 of 12
DRIVING CAPACITIVE LOADS
The internal compensation of the AD825, together with its high
output current drive, permits excellent large signal performance
while driving extremely high capacitive loads.
TEKTRONIX
P6204 FET
PROBE
HP PULSE
GENERATOR
50Ω
R
IN
1kΩ
C
L
V
OUT
V
IN
TEKTRONIX
7A24
PREAMP
AD825
7
4
3
6
2
+V
S
0.01µF
10µF
–V
S
0.01µF
10µF
00876-E-028
1kΩ
Figure 30. Inverting Amplifier Driving a Capacitive Load
INPUT
OUTPUT
5V
5V
500ns
00876-E-029
Figure 31. Inverting Amplifier Pulse Response
While Driving a 400 pF Capacitive Load
THEORY OF OPERATION
The AD825 is a low cost, wideband, high performance FET
input operational amplifier. With its unique input stage design,
the AD825 ensures no phase reversal, even for inputs that
exceed the power supply voltages, and its output stage is
designed to drive heavy capacitive or resistive loads with small
changes relative to no load conditions.
The AD825 (Figure 32) consists of common-drain, common-
base FET input stage driving a cascoded, common-base
matched NPN gain stage. The output buffer stage uses emitter
followers in a Class AB amplifier that can deliver large current
to the load while maintaining low levels of distortion.
POS
NEG
VNEG
VPOS
VOUT
C
F
00876-E-030
Figure 32. Simplified Schematic
The capacitor, CF, in the output stage, enables the AD825 to
drive heavy capacitive loads. For light loads, the gain of the
output buffer is close to unity, CF is bootstrapped, and not much
happens. As the capacitive load is increased, the gain of the
output buffer is decreased and the bandwidth of the amplifier is
reduced through a portion of CF adding to the dominant pole.
As the capacitive load is further increased, the amplifier’s
bandwidth continues to drop, maintaining the stability of the
AD825.
INPUT CONSIDERATION
The AD825 with its unique input stage ensures no phase
reversal for signals as large as or even larger than the supply
voltages. Also, layout considerations of the input transistors
ensure functionality even with a large differential signal.
The need for a low noise input stage calls for a larger FET
transistor. One should consider the additional capacitance that
is added to ensure stability. When filters are designed with the
AD825, one needs to consider the input capacitance (5 pF to
6 pF) of the AD825 as part of the passive network.
GROUNDING AND BYPASSING
The AD825 is a low input bias current FET amplifier. Its high
frequency response makes it useful in applications, such as
photodiode interfaces, filters, and audio circuits. When
designing high frequency circuits, some special precautions are
in order. Circuits must be built with short interconnects, and
resistances should have low inductive paths to ground. Power
supply leads should be bypassed to common as close as possible
to the amplifier pins. Ceramic capacitors of 0.1 µF are
recommended.
AD825
Rev. F | Page 11 of 12
SECOND-ORDER LOW-PASS FILTER
A second-order Butterworth low-pass filter can be implemented
using the AD825 as shown in Figure 33. The extremely low bias
currents of the AD825 allow the use of large resistor values and,
consequently, small capacitor values without concern for
developing large offset errors. Low current noise is another
factor in permitting the use of large resistors without having to
worry about the resultant voltage noise.
With the values shown, the corner frequency will be 1 MHz.
The equations for component selection are shown below. Note
that the noninverting input (and the inverting input) has an
input capacitance of 6 pF. As a result, the calculated value of C1
(12 pF) is reduced to 6 pF.
R1f
C1
CUTOFF
π
=2
414.1
()
R1f
faradsC2
CUTOFF
π
=2
707.0
(
)
Ωk100Ωk10 toTypicallySelectedUserR2R1 ==
A plot of the filter frequency response is shown in Figure 34;
better than 40 dB of high frequency rejection is provided.
AD825
C3
0.1µF
C4
0.1µF
V
OUT
V
IN
C2
6pF
–5V
C1
24pF
R1
9.31kΩ
R2
9.31kΩ
+5V
00876-E-031
Figure 33. Second-Order Butterworth Low-Pass Filter
FREQUENCY (Hz)
10k 100M100k
HIGH FREQUENCY REJECTION (dB)
1M 10M
0
–10
–20
–30
–40
–50
–60
–70
–80
00876-E-032
Figure 34. Frequency Response of Second-Order Butterworth Filter
AD825
Rev. F | Page 12 of 12
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARIT
Y
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
Figure 35. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body (R-8)
Dimensions shown in millimeters (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AA
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
16 9
8
1
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
10.50 (0.4134)
10.10 (0.3976)
8°
0°
0.75 (0.0295)
0.25 (0.0098) × 45°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COPLANARITY
0.10
Figure 36. 16-Lead Standard Small Outline Package [SOIC]
Wide Body (R-16)
Dimensions shown in millimeters (inches)
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD825AR −40°C to +85°C 8-Lead SOIC R-8
AD825AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD825AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8
AD825AR-16 −40°C to +85°C 16-Lead SOIC R-16
AD825AR-16-REEL −40°C to +85°C 16-Lead SOIC, 13" Tape and Reel R-16
AD825AR-16-REEL7 −40°C to +85°C 16-Lead SOIC, 7" Tape and Reel R-16
AD825ARZ-161−40°C to +85°C 16-Lead SOIC R-16
AD825ARZ-16-REEL1 −40°C to +85°C 16-Lead SOIC, 13" Tape and Reel R-16
AD825ARZ-16-REEL71 −40°C to +85°C 16-Lead SOIC, 7" Tape and Reel R-16
AD825ACHIPS Die
1 Z = Pb-free part.
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C00876–0–10/04(F)
