Exar Corporation 48720 Kato Road, Fremont CA, 94538 • ( 510) 668-7000 • FAX (510) 668-7017 • www.exar .co m
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
JANUARY 2007 REV. V1.2.0
GENERAL DESCRIPTION
The XRT86VL32 is a two-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redundancy). The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86VL32
provides protection from power failures and hot
swapping.
The XRT86VL32 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/ E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDL C buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Lin k bits of the inboun d T1/E1/J1 frames .
The X RT86VL32 f ull y me ets all of the l ate st T 1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT& T TR 6 2411 (12-90) T R54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, J T G706 , I.431. Ex ten sive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
APPLICATIONS AND FEATU RES (NEXT PAGE)
FIGURE 1. XRT86VL32 2-CHANNEL DS1 (T1/E1/J1) FRAMER/L IU C OMBO
Performance
Monitor
PRBS
Generator &
Analyser
HDLC/LAPD
Controllers
LIU &
Loopback
Control
DMA
Interface
Signaling &
Alarms JTAG
WR
ALE_AS
RD
RDY_DTACK
μP
Select
A[13:0]D[7:0]
Microprocessor
Interface
4
3
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Local PCM
Highway
ST-BUS
2-Frame
Slip Buffer
Elastic Store
Tx Ser i a l
Data In Tx LIU
Interface
2-Frame
Slip Buffer
Elastic Store
Rx LIU
Interface
Rx Framer
Rx Serial
Data O u t
RTIP
RRING
TTIP
TRING
External Data
Link Controller
Tx Overhead In Rx Overhead Out
XRT86VL32
1 of 2-channels
Tx Frame r
LLB LB
System (Terminal) Side
Line Side
1:1 Turns Ratio
1:2 Turns Ratio
Memory I n te l/Mo to r o l a µ P
Configuration, Control &
Status Monitor
RxLOS
TxON
INT
XRT86VL32
2
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
APPLICATIONS
•High-Density T1/E1/J1 interfaces for Mu ltiplexers, Switches, LAN Routers and Digital Modems
•SON ET/SDH termina l or Add/Drop multiplexers (ADMs)
•T1/E1/J1 add/drop multiplexers (MUX)
•Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
•Digital Access Cross-conn ec t System (DACs)
•Digital Cross-co nnect Systems (DCS)
•Frame Relay Switches and Acce ss Devices (FRADS)
•ISDN Primary Rate Interfaces (PRA)
•PBXs and PCM chann el bank
•T3 channelized access concentrators and M13 MUX
•Wireless base station s
•ATM equip men t with integrated DS1 interfaces
•Multichannel DS1 Test Equipment
•T1/E1/J1 Perform ance Moni toring
•Voice over packet gateways
•Routers
FEATURES
•Two independent, full duplex DS1 Tx and Rx Framer/LIUs
•Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx prov ide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
•Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 2-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•Programm able output clocks for Fractional T1/E1/J1
•Supp orts Channel Associated Signal ing (CAS)
•Supp orts Comm on Channel S igna lling (CCS )
•Supp orts ISDN Primary Rate Interface (ISDN PRI) signaling
•Extracts and inserts robbed bit signaling (RBS)
•3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte
buffers (buffer 0 / buff er 1)
•HDLC Controllers Support SS7
•Timeslot assignabl e HDLC
•V5.1 or V5.2 In te r face
•Autom atic Performance Report Ge neration (PM ON Status) ca n be inserted into the transm it LAP D interface
every 1 secon d or fo r a single transmission
•Alarm Indication Signal with Customer Installation signature (AIS-CI)
•Remote Alarm Indication with Customer Installation (RAI-CI)
•Gapped Clock interface m ode for Transmit and Receive.
XRT86VL32
3
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
•Intel/Motorola and Power PC interfaces for configuration, control and status monitoring
•Parallel search algorithm for fast fra me synchronizat ion
•W ide choice of T1 framing structures: SF/D4 , ESF, SLC®96, T1DM and N-Frame (non-signaling)
•Direct access to D and E channels for fast transm ission of data link information
•PRBS , QRSS , and Network Loop Code generation and det ection
•Program m able Interrupt output pin
•Supp orts programmed I/O and DMA modes of Read-Write access
•Each framer block encodes and decodes the T1/E1/J1 Frame serial data
•Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•Detects OOF, LOF, LOS errors and COFA conditions
•Loopbacks: Local (LLB) and Line remote (LB)
•F ac ilitates Inv er s e Mult ip lex ing for AT M
•Performance monitor with one second polling
•Boun dary scan (IEEE 1149.1) JTAG test port
•Accepts external 8kHz Sync reference
•1.8V Inne r Core
•3.3V CMO S operation with 5V tolera nt inputs
•225-pin P BGA package with -40°C to +85°C operation
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL32IB 22 5 Plast ic Ball Grid Array -40°C to +85°C
XRT86VL32
A
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
LIST OF PARAGRAPHS
1. 0 REGISTER DESCRIPTIO NS - T1 MODE .... .............. ..... .............. ..... .............. ..... .............. .... ..................9
2.0 LINE INT ERFACE UNIT (LIU SECTION) REGISTERS .......................................................................124
XRT86VL32
I
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
LIST OF TABLES
Tab l e 1 :: Re g i s te r Su m m a ry ....... ..... ..... ... .... ..... ... ..... .... ..... ... ..... .... ..... ... ..... .... ..... ... ..... ..... .. ..... ..........................................4
Table 2:: Clock Select Register(CSR) Hex Address: 0xn100 ... .. .....9
Table 3:: Line Interface Control Register (LICR) Hex Address: 0xn101 ............... 11
Table 4:: Framin g Select Register (FSR) Hex Address: 0xn107 ....................13
Table 5:: Alarm Gener ation Regis ter ( AG R) Hex Addr ess: 0xn108 ......................15
Table 6:: yellow alarm durati on and format wh en one second rule is not enforced .... ..... .. ..... .......... .. ..... .. ..... .. ...............16
Tab l e 7 :: y el lo w alarm fo rma t w h e n o ne se c o n d ru le is enfo rc e d ....... ..... ..... .. ..... ..... ... ..... .... ..... ... ..... .... ..... .....................17
Table 8:: Synchr onization MUX Register (SMR) Hex Address: 0xn109 ...................19
Table 9:: Transmi t Si gnaling and Data Link Select Register (TS DLS R) Hex Address :0xn10A ..... ...............22
Table 10:: Framing Control Register (FCR) Hex Address: 0xn10B ..................24
Table 11:: Receive Signaling & Data Link Select Register (RSDLSR) Hex Address: 0xn10C ....................25
Table 12:: Receive Signaling Change Register 0 (RSCR 0) Hex Address: 0xn10D ...........27
Table 13:: Receive Signaling Change Register 1(RSCR 1) Hex Address: 0xn10E .......27
Table 14:: Receive Signaling Change Register 2 (RSCR 2) Hex Addre ss: 0xn10F .........27
Table 15:: Receive In Frame Register (RIFR) Hex Address: 0xn112 ...................28
Table 16:: Data Link Control Register (DLCR1) Hex Address: 0xn113 ....................28
Table 17:: Trans mit Data Link Byte Count Regi ster (TDLBCR1) Hex Address: 0xn114 ... .. ...............31
Table 18:: Receive Data Link Byte Count Register (RDLBCR1) Hex Address: 0xn115 ..... .. ............32
Table 19:: Slip Buffer Control Register (SBCR) Hex Address: 0xn116 ......................33
Table 20:: FIFO Lat ency Register (FFOLR) Hex Address: 0xn117 ................34
Table 21:: DMA 0 (W ri te) Configu ration Regi ster (D0WCR) Hex Address: 0xn118 .......... ........35
Table 22:: DMA 1 (Read) Configu rat ion Registe r (D1RCR) Hex Address: 0xn119 ..................36
Table 23:: Interrupt Control Register (ICR) Hex Address: 0xn11A ......................37
Table 24:: LAPD Select Register (LAP DSR) Hex Address: 0 xn11B .................37
Table 25:: Customer Installation Alar m Gener ation Regis ter (CIAGR) Hex Address: 0xn1 1C .... ..... ....... ........38
Table 26:: Performance Report Cont rol Register (PRCR) Hex Address: 0xn11D ...... ....... ........39
Table 27:: Gapped Clock Control Regi ster (GCCR) Hex Addre ss: 0xn11E ..................40
Table 28:: Trans mit Interface Control Register (TICR) Hex Address:0xn120 .... .. ...............41
Tab l e 2 9: : Tra n smit In te rfa c e Sp e ed Wh e n Mu ltip le x ed M o de is Disa b le d (T xMU X E N = 0) ... .. ..... ... .... ..... ..... ... .... ..... ... .43
Table 30:: Transmit Interface Speed when Multiplexed Mode is Enab led (TxMUXEN = 1) ............................................44
Table 31:: PRBS Control & Status Regi ster (PRBSCSR0) Hex Address: 0xn 121 ...............45
Table 32:: Receive Interface Control Register (RICR) Hex Address: 0xn122 ..............47
Table 33:: Receive Interface Speed W hen M ultiplexed Mode is Disabled (TxMUXEN = 0) ............................................49
Table 34:: Recei ve Int erface Speed when M ultiplexed Mode is Enabled (TxMUXEN = 1) .... ..... .. .......... .. .. ..... ....... ..... ...50
Table 35:: PRBS Control & Status Register (P RBSCSR1) Hex Address: 0xn123 ...... ....... ........51
Table 36:: Loopback Code Control Regis ter (LCCR) Hex Address: 0xn124 ................53
Table 37:: Trans mit Loopback Coder Register (TLCR) Hex Address: 0 xn125 ...... ........55
Table 38:: Recei ve Loopback Activation Code Register (RLACR) Hex Address: 0xn126 ..... .. ..... .. ...55
Table 39:: Receive Loopback Deactivat ion Code Re gister (RLDCR) Hex Address: 0xn127 ........... ........55
Table 40:: Defect Detection Enable Register (DDER) Hex Address: 0xn129 ...............56
Table 41:: Transmit SPRM Control Register (TSPRMCR) Hex Address: 0xn142 .................56
Table 42:: Data Link Control Regi ster (DLCR2) Hex Address: 0xn143 ...................57
Table 43:: Transmit Data Link Byte Count Register (TDLBCR2) Hex Address: 0xn144 ...................59
Table 44:: Receive Data Link Byte Count Regis ter (RDLBCR2) Hex Address: 0xn145 .... .. ............60
Table 45:: Data Link Control Register (DLCR3) Hex Address: 0xn153 ..................61
Table 46:: Transmit Data Link Byte Count Register (TDLBCR3) Hex Address: 0xn154 ...................63
Table 47:: Receive Data Link Byte Count Regis ter (RDLBCR3) Hex Address: 0xn155 .... .. ............64
Table 48:: Device ID Register (DEVID) Hex Address: 0xn1FE ............65
Table 49:: Revision ID Register (REVID) Hex Address: 0xn1FF ........... 65
Table 50:: Transmit Channel Cont rol Register 0-23 (TCCR 0-23) Hex Address: 0xn300 t o 0xn317 .....................66
Table 51:: Trans mit User Code Regist er 0- 23 (TUCR 0-23) Hex Address: 0xn320 to 0 xn337 ........ ........68
Table 52:: Trans mit Signaling Control Regi ster 0-23 (TSCR 0-23) Hex Address: 0xn340 to 0xn357 ... ............ ........69
Table 53:: Recei ve Channel Control Register 0- 23 (RCCR 0-23) Hex Address: 0xn360 to 0xn377 ..... ..............71
Table 54:: Receive User Code Register 0-23 ( RUCR 0-23) Hex Addre ss: 0xn380 to 0xn397 .... .. ........73
Table 55:: Receive Signaling Control Register 0-23 (RSCR 0-23) Hex Addr ess: 0xn3A0 to 0xn3B7 ....................74
Table 56:: Recei ve Substitution Signaling Register 0-23 (RSSR 0-23) Hex Addr ess: 0xn3C0 to 0xn3D7 ..... ..............76
Table 57:: Receive Signaling Array Register 0 to 23 (RSAR 0-23) Hex Address: 0Xn500 to 0 xn517 ........... ........77
Table 58:: LAPD Buffer 0 Contr ol Register (LAPDBCR0) Hex Address: 0xn600 ..... .. ............ .................78
XRT86VL32
II
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
Table 59:: LAPD Buffer 1 Contr ol Register (LAPDBCR1) Hex Address: 0xn700 .... ............ ......................78
Table 60:: PMON Receive Li ne Code Violation Counter MSB (RLCVCU) Hex Address: 0xn900 ....... ..........79
Table 61:: PMON Receive Li ne Code Violati on Counter LSB (RLCVCL) Hex Address: 0xn901 .. ..............79
Table 62:: PMON Receive Framing Alignment Bit Error Counter MSB (RFAECU) Hex Address: 0xn902 ...................80
Table 63:: PMON Receive Framing Alignment Bit Error Counter LSB (RFAECL) Hex Address: 0xn903 ....................80
Table 64:: PMON Receive Severely Errored Frame Counter (RSEFC) Hex Address: 0xn90 4 ...................81
Table 65:: PMON Recei ve CRC-6 BI T Erro r Count er - MSB (RSBBECU) Hex Addres s: 0xn905 ............ .....82
Table 66:: PMON Recei ve CRC-6 Bit Error Counter - LSB (RSBBECL) Hex Address: 0xn906 .. .. ....... .....82
Table 67:: PMON Receive Slip Counter (RSC) Hex Address: 0xn909 ............... 83
Table 68:: PMON Receive Loss of Frame Counter (RLFC) Hex Address: 0xn90A .. ..... .. .. ..... 83
Table 69:: PMON Receive Change of Frame Alig nment Counter (RCFAC) Hex Address: 0xn90B .. .. .. ..........83
Table 70:: PMON LAPD1 Frame Check Sequence Error Counter 1 (LFCSEC1) Hex Address: 0xn90C . ................ 84
Table 71:: PRBS Bit Error Counter MSB (PBECU) Hex Address: 0xn90D ................. 84
Table 72:: PRBS Bit Error Counter LSB (PBECL) Hex Address: 0xn90E ....... .......... 84
Table 73:: Transmit Slip Counter (TSC) Hex Address: 0xn90F .... .......... .85
Table 74:: Excess ive Zero Violati on Counter MSB (EZVCU) Hex Address: 0xn910 ....... ..........85
Table 75:: Excessive Zero Violation Counter LSB (EZVCL) Hex Address: 0xn911 ..... .. ..... ..... 85
Table 76:: PMON LAPD2 Frame Check Sequence Error Counter 2 (LFCSEC2) Hex Address: 0xn91C . ................ 86
Table 77:: PMON LAPD2 Frame Check Sequence Error Counter 3 (LFCSEC3) Hex Address: 0xn92C . ................ 86
Table 78:: Block Interrupt Status Register (BISR) Hex Address: 0xnB00 .................... 87
Table 79:: Block Interrupt Enable Register (BIER) Hex Address: 0xnB01 ................... 89
Table 80:: Alarm & Error Interrupt Status Register (AEISR) Hex Address: 0xnB02 .....................91
Table 81:: Alarm & Error Interrupt Enable Register (AEIER) Hex Address: 0xnB03 ...................... 93
Table 82:: Framer Interrupt Status Register (FISR) Hex Address: 0xnB04 ................... 94
Table 83:: Framer Interrupt Enable Register (FIER) Hex Address: 0xnB05 ................... 96
Table 84:: Data Link Status Register 1 (DLSR1) Hex Address: 0xnB06 ................ 98
Table 85:: Data Link Interrupt Enable Register 1 (DLIER1) Hex Address: 0xnB07 ....... .......... 100
Table 86:: Slip Buffer Interrupt Status Register (SBISR) Hex Address: 0xnB08 ...................102
Tab l e 8 7: : Slip B uf fe r In ter ru p t En ab le Re gi st e r (S B IE R) Hex A d dr e ss : 0x nB0 9 .. .. ..... . ........ 105
Table 88:: Recei ve Loopback Code Interrupt and Status Register (RLCISR) Hex Address: 0xnB0A ...................107
Table 89:: Recei ve Loopback Code Interrupt Enab le Regi ster (RLCIER) Hex Address: 0xnB0B ....... .. ..... .. ...108
Table 90:: Excessive Zero Status Register (EXZSR) Hex Address: 0xnB0E ................109
Table 91:: Excessive Zero Enable Register ( EXZER) Hex Address: 0xnB0F ....... ....... 109
Table 92:: SS7 Status Register for LAPD1 (SS7SR1) Hex Address: 0xnB10 ................ 110
Tab l e 9 3: : S S7 E n a bl e Re g iste r fo r L AP D 1 (S S7 E R 1 ) Hex A ddress : 0 xn B 1 1 ... .. ......... 110
Table 94:: RxLOS/CRC Interrupt Status Register (RLCISR) Hex Address: 0xn B 12 ....... ........111
Table 95:: RxLOS/CRC Interrupt Enable Regi ster (RLCIER) Hex Address: 0xnB 13 ....... ........111
Table 96:: Data Link Status Register 2 (DLSR2) Hex Address: 0xnB16 ............... 112
Table 97:: Data Link Interrupt Enable Register 2 (DLIER2) Hex Address: 0xnB17 ....... .......... 114
Table 98:: SS7 Status Register for LAPD2 (SS7SR2) Hex Address: 0xnB18 ................ 116
Tab l e 9 9: : S S7 E n a bl e Re g iste r fo r L AP D 2 (S S7 E R 2 ) Hex A d dr e ss : 0x nB1 9 .. ... ..... ...... 116
Table 100:: Data Link Status Register 3 (DLSR3) Hex Address: 0xnB26 ............. 117
Table 101:: Data Link Interrupt Enable Register 3 (DLIER3) Hex Address: 0xnB27 .............. 119
Table 102:: SS7 Status Register for LAPD3 (SS7SR3) Hex Address: 0xnB28 ............. 121
Table 103:: SS7 Enable Register for LAPD3 (SS7ER3) Hex Address: 0xnB29 ............121
Table 104:: Customer Installation Alarm Status Register (CIASR) Hex Address: 0xnB40 .................. 122
Table 105:: Customer Installation Alarm Status Register (CIAIER) Hex Address: 0xnB41 ..................123
Table 106:: LIU Channe l Cont rol Register 0 (LI UCCR0) Hex Address : 0x0Fn0 ............124
Table 107:: Equal izer Contro l and Tr ansm it Line Build Out ...... .......... .. .. ..... .. .................... .. .................... ...................... 126
Table 108:: LIU Channe l Cont rol Register 1 (LI UCCR1) Hex Address: 0x0Fn1 .... ....... 127
Table 109:: LIU Channe l Cont rol Register 2 (LI UCCR2) Hex Address : 0x0Fn2 ............129
Table 110:: LIU Channe l Cont rol Register 3 (LI UCCR3) Hex Address: 0x0Fn3 .... ....... 131
Table 111:: LIU Channe l Cont rol Interrupt Enable Register (LIUCCIER) Hex Address: 0x0Fn4 ..... ............133
Table 112:: LIU Channel Cont rol Status Register (LIUCCSR) Hex Address: 0x0Fn5 .... .. .. ........135
Table 113:: LIU Channel Cont rol Interrupt Status Register (LIUCCISR) Hex Address: 0x0Fn6 ..... .. .............138
Table 114:: LIU Channe l Cont rol Cable Loss Register (LI UCCCCR) Hex Addres s: 0x0Fn7 ..... .. ........139
Table 115:: LIU Channe l Cont rol Arbitrary Register 1 (LIUCCAR1) Hex Address: 0x0Fn8 ..... .............140
Table 116:: LIU Channe l Cont rol Arbitrary Register 2 (LIUCCAR2) Hex Address: 0x0Fn9 ...... .. .............140
Table 117:: LIU Channe l Cont rol Arbitrary Register 3 (LIUCCAR3) Hex Address: 0x0FnA .... .. ....... ........140
Table 120:: LIU Channe l Cont rol Arbitrary Register 6 (LIUCCAR6) Hex Address: 0x0FnD ...... ...............141
XRT86VL32
III
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
Table 118:: LIU Channe l Cont rol Arbitrary Regist er 4 (L IUCCAR4) Hex Address: 0x0FnB .....................141
Table 119:: LIU Channe l Cont rol Arbitrary Register 5 (LIUCCAR5) Hex Address: 0x0FnC .... .................141
Table 121:: LIU Channe l Cont rol Arbitrary Regist er 7 (L IUCCAR7) Hex Address: 0x0FnE .....................142
Table 122:: LIU Channe l Cont rol Arbitrary Regist er 8 (L IUCCAR8) Hex Address: 0x0FnF ...... .. .............142
Table 123:: LIU Global Control Register 0 (LIUGCR0) Hex Address: 0x0FE0 .............143
Table 124:: LIU Global Control Register 1 (LIUGCR1) Hex Address: 0x0FE1 .............144
Table 125:: LIU Global Control Register 2 (LIUGCR2) Hex Address: 0x0FE2 .............145
Table 126:: LIU Global Control Register 3 (LIUGCR3) Hex Address: 0x0FE4 .............146
Table 127:: LIU Global Control Register 4 (LIUGCR4) Hex Address: 0x0FE9 .............147
Table 128:: LIU Global Control Register 5 (LIUGCR5) Hex Address: 0x0FEA .............148
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
DESCRIPTION OF THE CONTROL REGISTERS - T 1 MODE
All address on this reg ister desc ription is shown in HEX format, wh ere n ind icate s channels 0 and 2 in the 2-
channel device.
TABLE 1: R EGISTER SUMMARY
FUNCTION SYMBOL HEX
Control Registe rs (0xn100 - 0xn1FF)
Clock and Select Regi ster CSR 0xn100
Line Interface Control Register LICR 0xn101
Reserved -0xn102 - 0xn106
Fram ing Select Reg ist er FSR 0xn107
Alarm Generation Register AGR 0xn108
Synchronization MUX Register SMR 0xn109
Tr ansmit Signaling and Data Link Sel ect Register TSDLSR 0xn10A
Framing Control Register FCR 0xn10B
Receive Signal ing & Data Link Select Register RSDLSR 0xn10C
Receive Signal ing Change Register 0 RSCR0 0xn10D
Receive Signal ing Change Register 1 RSCR1 0xn10E
Receive Signal ing Change Register 2 RSCR2 0xn10F
Reserved - E1 mode only -0xn110 -
0xn111
Receive In-Fr ame Register RIFR 0xn112
Data Link Control Register 1 DLCR1 0xn113
Tra nsm it Data Li nk Byte Count Regist er 1 TDLBCR1 0xn114
Receive Data Link Byte Count Register 1 RDLBCR1 0xn115
Sli p Buffer Cont rol Regist er SBCR 0xn116
FIFO Latency Regist er FIFOLR 0xn117
DMA 0 (Write) Configuration Re gister D0WCR 0xn118
DMA 1 (Read ) Conf iguration Register D1RCR 0xn119
Interrupt Control Register ICR 0xn11A
LAPD Select Register LAPDSR 0xn11B
Customer Installa tion Alarm Generation Register CIAGR 0xn11C
Performance Report Control Register PRCR 0xn11D
Gap ped Clock Control Register GCCR 0xn11E
Transmit Interfa ce Control Register TICR 0xn120
PRBS Contro l & Status - Register 0 PRBSCSR0 0xn121
XRT86VL32
5
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
Receive Inter face Control Register RICR 0xn122
PRBS Contro l & Status - Register 1 PRBSCSR1 0xn123
Loopback Code Control Register LCCR 0xn124
Transmit Loopback Code Register TLCR 0xn125
Receive Loopb ack Activation Code Regis ter RLACR 0xn126
Receive Loopb ack Deactivation Code Register RLDCR 0xn127
Defect Detection Enable Register DDER 0xn129
Reserved - E1 mode only -0xn130 - 0xn13F
Tra nsm it SPRM Control Register TSPRMCR 0xn142
Data Link Control Register 2 DLCR2 0xn143
Tra nsm it Data Li nk Byte Count Regist er 2 TDLBCR2 0xn144
Receive Data Link Byte Count Register 2 RDLBCR2 0xn145
Data Link Control Register 3 DLCR3 0xn153
Tra nsm it Data Li nk Byte Count Regist er 3 TDLBCR3 0xn154
Receive Data Link Byte Count Register 3 RDLBCR3 0xn155
De vice ID Register DEVID 0xn1FE
Revision Number Register REVID 0xn1FF
Time Slot (payload) Cont rol (0xn300 - 0xn3FF)
Tra nsm it Channel Cont rol Regist er 0-23 TCCR 0-23 0xn300 - 0xn317
Tr ansmit User Code Regi ster 0-23 TUCR 0-23 0xn320 - 0xn337
Tran s m i t Si gna l ing C ontro l R egi ster 0-2 3 TSCR 0-23 0xn340 - 0xn357
Receive Channe l Cont rol Register 0- 23 RCCR 0-23 0xn360 - 0xn377
Receive User Code Register 0-23 RUCR 0-23 0xn380 - 0xn397
Receive Signaling Control Register 0- 23 RSCR 0-23 0xn3A0 - 0xn3B7
Receive Substitution Signaling Register 0-23 RSSR 0-23 0xn3C0 - 0xn3D7
Receive Signaling Array (0xn500 - 0xn51F)
Receive Signaling Array Register 0 RSAR0-23 0xn500 -
0xn517
LAPDn Bu ffer 0
LAPD Buffer 0 Control Register LAPDBCR0 0xn600 -
0xn660
LAPDn Bu ffer 1
LAPD Buffer 1 Control Register LAPDBCR1 0xn700 -
0xn760
TABLE 1: R EGISTER SUMMARY
FUNCTION SYMBOL HEX
XRT86VL32
6
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
Performance Monitor
Receive Line Code Vi olation Counter: MSB RLCVCU 0xn900
Receive Line Code Vi olation Cou nter: LSB RLCVCL 0xn901
Receive Frame Ali gnm ent Error Counter: MSB RFAECU 0xn902
Receive Frame Ali gnm ent Error Counter: LSB RFAECL 0xn903
Receive Severely Errored Frame Counter RSEFC 0xn904
Recei ve Synchroniz ati on Bit (CRC-6) Error Counter: MSB RSBBECU 0xn905
Receive Synchron iz ati on Bit (CRC-6) Error Counter: LSB RSBBECL 0xn906
Reserved - E1 Mode Only 0xn907 - 0xn908
Receive Slip Counter RSC 0xn909
Receive Loss of Frame Counter RLFC 0xn90A
Receive Change of Frame Al ignment Counter RCOAC 0xn90B
LAPD Frame Check Sequence Error counter 1 LFCSEC1 0xn90C
PRBS bit Error Counter: MSB PBECU 0xn90D
PRBS bit Error Counter: LSB PBECL 0xn90E
Tra nsm it Slip Counter TSC 0xn90F
Excessive Zero Violation Counte r: MSB EZ V C U 0xn910
Excessive Zero Violation Counte r: LSB EZVCL 0xn911
LAPD Frame Check Sequence Error counter 2 LFCSEC2 0xn91C
LAPD Frame Check Sequence Error counter 3 LFCSEC3 0xn92C
Interrupt Generation/ Enable Register Ad dress Map (0xnB00 - 0xnB4 1)
Block Interrupt Status Register BISR 0xnB00
Block Inter rupt Enable Regi ster BIER 0xnB01
Alarm & Error Interrupt Status Register AEISR 0xnB02
Alarm & Error Interrupt Enable Register AEIER 0xnB03
Framer Interrupt Status Register FISR 0xnB04
Framer Interrupt Enable Register FIER 0xnB05
Data Link Status Register 1 DLSR1 0xnB06
Data Link Interrupt Enable Register 1 DLIER1 0xnB07
Sli p Buffer Interr upt Stat us Register SBISR 0xnB08
Sli p Buffer I nterrupt Enable Register SBIER 0xnB09
Receive Loopb ack code Interr upt and Status Register RLCISR 0xnB0A
Receive Loopback code Interrupt Enable Register RLCIER 0xnB0B
TABLE 1: R EGISTER SUMMARY
FUNCTION SYMBOL HEX
XRT86VL32
7
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
Reserved - E1 Mode Only -0xnB0C - 0xnB0D
Excessive Zero Status Register EXZSR 0xnB0E
Excessive Zero Enable Regist er EXZER 0xnB0F
SS7 Status Regi ster for LAPD 1 SS7SR1 0xnB10
SS7 Enabl e Register for LAPD 1 SS7ER1 0xnB11
RxLOS/CRC In ter rupt Status Register RLCISR 0xnB12
RxLOS/CRC In ter rupt Enable Register RLCIER 0xnB13
Data Link Status Register 2 DLSR2 0xnB16
Data Link Interrupt Enable Register 2 DLIER2 0xnB17
SS7 Status Regi ster for LAPD 2 SS7SR2 0xnB18
SS7 Enabl e Register for LAPD 2 SS7ER2 0xnB19
Data Link Status Register 3 DLSR3 0xnB26
Data Link Interrupt Enable Register 3 DLIER3 0xnB27
SS7 Status Regi ster for LAPD 3 SS7SR3 0xnB28
SS7 Enabl e Register for LAPD 3 SS7ER3 0xnB29
Customer Installa ti on Alarm Status Register CIASR 0xnB40
Customer Installa ti on Alarm Inter rupt Enable Regi ster CIAIER 0xnB41
LIU Register Summary - Channel Control Registers
LIU Channel Control Register 0 LIUCCR0 0x0Fn0
LIU Channel Control Register 1 LIUCCR1 0x0Fn1
LIU Channel Control Register 2 LIUCCR2 0x0Fn2
LIU Channel Control Register 3 LIUCCR3 0x0Fn3
LIU Channel Control Interru pt Enabl e Register LIUCCIER 0x0Fn4
LIU Channel Control Status Registe r LIUCCSR 0x0Fn5
LIU Channel Control Interru pt Stat us Register LIUCCISR 0x0Fn6
LIU Channel Control Cable Loss Register LIUCCCCR 0x0Fn7
LIU Channel Control Arbi trary Regi ster 1 LIUCCAR1 0x0Fn8
LIU Channel Control Arbi trary Regi ster 2 LIUCCAR2 0x0Fn9
LIU Channel Control Arbi trary Regi ster 3 LIUCCAR3 0x0FnA
LIU Channel Control Arbi trary Regi ster 4 LIUCCAR4 0x0FnB
LIU Channel Control Arbi trary Regi ster 5 LIUCCAR5 0x0FnC
LIU Channel Control Arbi trary Regi ster 6 LIUCCAR6 0x0FnD
LIU Channel Control Arbi trary Regi ster 7 LIUCCAR7 0x0FnE
TABLE 1: R EGISTER SUMMARY
FUNCTION SYMBOL HEX
XRT86VL32
8
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
LIU Channel Control Arbi trary Regi ster 8 LIUCCAR8 0x0FnF
Reserved -0x0F80 -
0x0FDF
LIU Register Summary - Global Control Registers
LIU Global Control Regi ster 0 LIUGCR0 0x0FE0
LIU Global Control Regi ster 1 LIUGCR1 0x0FE1
LIU Global Control Regi ster 2 LIUGCR2 0x0FE2
LIU Global Control Regi ster 3 LIUGCR3 0x0FE4
LIU Global Control Regi ster 4 LIUGCR4 0x0FE9
LIU Global Control Regi ster 5 LIUGCR5 0x0FEA
Reserved -0x0FEB -
0x0FFF
TABLE 1: R EGISTER SUMMARY
FUNCTION SYMBOL HEX
XRT86VL32
9
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1.0 REGISTER DESCRIPTIONS - T1 MODE
All address on this re gister description is shown in HEX format, where n indicates channels 0 and 2 in the
2-channel device
TABLE 2: CLOCK SELECT REGISTER(CSR) HEX ADDRESS: 0Xn100
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7LCV I n se r t R/W 0Li ne Code Violati on Insertion
This bi t i s used to force a Lin e Code Violati on (LCV) on the transm it
output of TTIP/TR ING.
A “0” to “1” transition o n thi s bit will cause a si ngle LCV to be inserted
on the tr ansm it output of TTIP/TRING.
6Set T1 Mode R/W 0T1 Mode select
This bi t is used to progr am the i ndividual channel t o operate in eit her
T1 or E1 mode.
0 = Configures the selected chan nel to operate in E1 mode.
1 = Configures the selected chan nel to operate in T1 mode.
5 Sync All Transmit-
ters to 8kHz R/W 0Sync All Transmit Framers to 8kHz
This bi t permits the user to co nfigure each of the two (2) Trans m it T1
Framer blocks to synchronize their “transmit output” fr am e alignment
with the 8kHz signal that is derived from the MCLK PLL, as described
below.
0 - Disables the “Sync all Transmit Framers to 8kHz” feature for all 2
channels.
1 - Enables the “Sync all Transmit Framers to 8kHz” fea ture for all 2
channels.
NOTE: Writing to this bit in register 0x0100 will enable this feature for
all 2 channels.
NOTE: This bit is only active if the MCLK PLL is used as the “Timing
Source” for the Transmit T1 Framer” blocks. CSS[1:0] of this
register allows users to select the transmit source of the
framer.
4Clock Loss Detect R/W 1Cl ock Loss Detect Enable/ D isable Select
This bi t enables a cloc k loss protect ion featur e for the Framer when-
ever the recovered line clock is used as the timing source for the trans-
mit sect ion. If the LIU loses cl ock recover y, the Cloc k Dist ribut ion Bloc k
will detect thi s occurr ence and automat ically begin to use the internal
clock derived from MCLK PLL as the Transmit source, unt il the LIU is
able to regain cl ock recove ry.
0 = Disabl es the clock loss p rotection featur e.
1 = Enables the c lock loss protecti on feature.
NOTE: This bit needs to be enabled in order to detect the clock closs
detection in terrupt st atus (address: 0xnB00, bit 5)
3:2 Reserved R/W 00 Reserved
XRT86VL32
10
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1:0 CSS[1:0] R/W 01 Clock Source Select
These bits select the tim ing source for the Tran sm it T1 Framer block.
These bits can al so determine the direction of TxSERCLK, TxSYNC,
and TxMS YNC in base rate operation mode (1.544MHz Clock mode) .
In Base Rate (1.54 4MHz Clock Mode):
TABLE 2: CLOCK SELECT REGISTER(CSR) HEX ADDRESS: 0Xn100
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
N
OTE: TxSYNC/TxMSYNC can be programmed as input or outpu
t
depending on the sett ing of SYNC INV bit in Regist er Address
0xn109, bit 4. Please see Register Description for the
Synchronization Mux Register (SMR - 0xn109) Table 8.
N
OTES: In High-Speed or multiplexed modes, TxSERCLK, TxSYNC,
a
nd TxM SYNC are all configur ed as INPUTS onl y.
CSS[1:0] TRANSMIT SOURCE FOR THE
TRANSMIT T1 FRAMER BLOCK DIRECTION OF
TXSERCLK
00/11 Loop Timing Mode
The recovered line clock is cho-
sen as the timing source.
Output
01 External Timing M ode
The Tra nsm it Serial Input Clock
fro m the TxSERCLK_n input pi n is
chosen as the timing source.
Input
10 Internal Ti m ing Mode
The MCLK PLL is chosen as the
timing source.
Output
XRT86VL32
11
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 3: LINE INTERFACE CONTROL REGISTER (LICR) HEX ADDRESS: 0XN101
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7FORCE_LOS R/W 0Force Transmit LOS (To the Line Side)
This bi t permits the user to configur e the transmit direct ion circuitry
(wit hin the channel) to transm it the LOS patt ern to the remote termina l
equipment, as described below.
0 - Configures the transmit directi on circuitry to tr ansmit “normal” traffi c.
1 - Confi gures the transmit direction circuit ry to transmi t the LOS
Pattern.
6Reserved R/W 0Single Rail Mode
This bi t can only be set if the LIU Block is also set to single rai l mode.
See Register 0x0FE0, bit 7.
0 - Dual Rail
1 - Single Rail
5:4 LB[1:0] R/W 00 Framer Loopback Selecti on
These bits are used to select any of the following loop-back modes f or
the framer section. For LIU loopback modes , see the LIU configuration
registers.
3:2 Reserved R/W 0Reserved
LB[1:0] TYPES OF LOOPBACK SELECTED
00 Normal Mode (No LoopBack)
01 Framer Local LoopBack:
When fram er l ocal loopback is enabled, the tra nsm it
PCM input dat a is looped back to the recei ve PCM out-
put data. The receive input data at RTI P/RRING is
ignore d whil e an All O nes Signal is transmitted out to
the line interface.
10 Framer Far -End (Remote) Line LoopBack:
When fram er remote loopback is enabled, the digital
data enters the f ramer inter face, however does not
enter the framing blocks. The receive digital data from
the LIU is allowed to pass through the LIU Decoder/
Encoder circuitry befo re returni ng to the line interface.
11 Framer Payload LoopBack:
When fram er payload loopback is enabled, t he raw
data within the receiv e time slot s are looped back to the
transmit framer block where the dat a is re-f ramed
according to the transmit ti ming.
XRT86VL32
12
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1Encode B8ZS R/W 0Encode AMI o r B8ZS/HDB3 Line Code Select
This bi t enables or di sables the B8ZS/HDB3 en coder on the trans m it
path.
0 = Enables t he B8ZS encoder.
1 = Disabl es the B8ZS encoder.
NOTE: When B8ZS encoder is disabled, AMI line code is used.
0Decode AM I/ B8ZS R/W 0Decode AMI o r B8ZS/HDB3 Line Code Select
This bi t enables or di sables the B8ZS/HDB3 de coder on the recei ve
path.
0 = Enables t he B8ZS decoder.
1 = Disabl es the B8ZS decoder.
NOTE: When B8ZS decoder is disabled, AMI line code is received.
TABLE 3: LINE INTERFACE CONTROL REGISTER (LICR) HEX ADDRESS: 0XN101
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
13
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 4: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0Xn107
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Signaling update on
Superframe Boundaries R/W 0Enable Robbed-Bit Signaling Update on Superframe Boundary
on Both Transmit and Receive Direction
This bit enables or disables robbed-bit signaling update on the
superframe boun dary for both the transmit and receive si de of the
framer.
On the Receive Side :
If sig naling update is enabled , si gnaling data on the recei ve side
(RxSIG pin and Signali ng Array Register - RSAR) wi ll be updated on
the superframe boundary, otherwise, signaling data will be updated
as soon as it is received.
On the Transmit Side:
If sig naling update is enabled , any si gnaling data ch anges on the
transmit side will be transmitt ed on the superframe bounda ry, other-
wise, signaling data will be transmitt ed as soon as it is changed.
0 - Disabl es the si gnaling update feature for both transmit and
receive.
1 - Enables t he signaling update feature for both transmit and
receive.
6Force CRC Errors R/W 0Force CRC Err ors (To the Line Si de)
This bit permits the user to force the T ransmi t T1 Framer block to
transmit CRC errors within the outb ound T1 data-st ream, as depi cted
below.
0 - Disables CRC error transmi ssion on the outbound T1 stream.
1 - Enables CRC error transmission on the outbound T1 stream.
5J1_MODE R/W 0J1 Mo de
This bit is used to confi gure the device in J1 m ode. Once the device
is configured in J1 mode, the following two changes will happen:
1. CRC calcul ation is done in J1 form at. The J1 CRC6 calcula-
tion is based o n the actual values of all 4632 bits in a T 1 m ulti-
frame includi ng Fe bits instead of assum ing all Fe bi ts to be a
one in T1 for m at.
2. Receive a nd Transmit Yellow Ala rm sig nal format is int er-
preted per the J1 st andard. (J1-SF or J1-ESF)
0 - Configures the device in T 1 mode . (Def ault)
1 - Configures the device in J 1 mod e.
NOTE: Users can select between J1-SF or J1-ESF by setting this bit
and the T1 Framing Mode Select Bits[2:0] (Bits 2-0 within
thi s register).
4ONEONLY R/W 0Allow Only One Sync Candidate
This bit is used to specif y one of the synchronization cri teria that the
Receive T1 Framer block employs.
0 - Allows the Re ceive T1 Framer to select any one of t he winne rs in
the matching process when there are two or more valid synchroniza-
tion patter ns appear in the req uired time fram e.
1 - Allows the Rec eive T1 Fram er t o declare success of match when
there i s only o ne candidate left i n the re quired time fram e.
XRT86VL32
14
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3FASTSYNC R/W 0Faster Sync Alg orithm
This bit is used to specif y one of the synchronization cri teria that the
Receive T1 Fr ame r block employs. If this “Faster Sync Algorithm” is
enabled, the Receive T1 Framer Block will declare synchronization
earli er. The table bel ow specifie s the number of consecutive frames
with cor rect F-bits that the T1 Receive framer mu st r eceive in order
to decla re “SYNC” when FASTSYNC is enabled or disabled.
0 - Disables FASTSYNC featur e.
1 - Enables FASTSYNC feature.
2-0 FSl[2:0] R/W 000 T1 Framing Mode Select [2:0]
These th ree bit s permi t the user to se lec t the exact T 1 f raming f ormat
that th e channel is to operate in.
Bit 2 is MSB and Bit 0 is LSB. The followi ng table shows the five dif-
ferent framing formats that can be selected by configuring these
three bi ts acco rdi ngly.
NOTE: Changing Framing formats 'on the fly' will cause the Receive
T1 Framer block to undergo a “Reframe” event.
TABLE 4: FRAMING SELECT REGISTER (FSR) HEX ADDRESS: 0Xn107
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
Framing Fa st Sync
= 0 FastSync
= 1
ESF 96 48
SF 48 24
N48 24
SLC
®
96 48 24
Framing FS[2] FS[1] FS[0]
ESF 0 X X
SF 101
N110
T1DM 111
SLC
®
96 100
XRT86VL32
15
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 5: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0Xn108
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Yellow Alarm -
One Second
Rule
R/W 0One-Second Yellow Alarm Rule Enf orcement
This bit is used to enforce the one-second yellow alarm rule according to the yel-
low al arm (RAI) tran sm ission duration per the ANSI st andar ds.
If t he one second alarm rule is enforced, the followi ng will happen:
1. RAI will be transmitted for at least one second for both ESF and SF.
2. There must be a minimum of one second delay between termination
of th e first RAI and the initiation of a subsequent RAI.
3. ALARM_ENB bit (see description of bit 6 of this register) controls the
duration of RAI.
4. YEL[0] & YEL[1] (see description of bits 5-4 of this register) controls the
format of RAI.
If the one second alarm rule is NOT enforced, the following will h appen:
1. RAI will be transmitted for at least one second for ESF and SF.
2. Minimum one second delay between termination of the first RAI and the
ini tiati on of t he subsequent RAI is NOT enforced.
3. YEL[0] and YEL[1] bits (see description of bits 5-4 of this register) are used
to control the duration AND the format of RAI transmission.
0 - The one-second yel low alarm rule is NO T enforced.
1 - The one-second yellow alarm rule is enforced.
NOTE: When setting this bit to ‘0’, yellow alarm transmission will be backward
compatible with the XRT86L38 device. XRT86L38 does not support the
one-secon d yellow alarm ru le.
6ALARM_ENB R/W 0Yellow Alarm Transm ission Enable
This bit i s used to control the duration of yellow alarm (RAI) when the one-second
yellow alar m rule is enforced (bit 7 of this regi ster set t o’1’).
When the one-second yellow alarm rule is not enf orced (bit 7 of this register set
to’0’), the duration of the RAI is controlled by the YEL[0] and YEL[1] bits (bits 5- 4
of this regi ster).
If the one-second al arm rule is enforc ed:
0 - Stop the transm ission of yel low alarm (see description of bit s 5-4).
1 - Start the transmission of yellow alarm (see description of bits 5-4).
NOTE: This bit h as no function if the one secon d alar m rul e is not enforc ed.
XRT86VL32
16
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
5-4 YEL[1:0] R/W 00 Yellow Alarm (RAI) Duration and Format
The exact fun ction of the se bi ts depend s on whether or not the one- second yel low
alarm rule is enforced. ( Bit 7 of this register). The decoding of these bits are
explained in Ta ble 6 and Ta ble 7 below .
TABLE 5: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0Xn108
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 6: YELLOW ALARM DURATION AND FORMAT WHEN ONE SECOND RULE IS NOT
ENFORCED
YEL[1:0] YELLOW ALARM DURATION AND FORMAT
00 Disable the transm ission of yellow alarm
01 SF or N mode:
RAI is transmitted as b it 2 = 0 (second MSB) in all DS0 data chan-
nel.
T1DM mode:
RAI is transmitted as Y-bit = 0 (6th bit in the SYNC byte).
ESF mode:
1. If YEL[0] bit is set ’high’ for a duration shorter or equal to the
time required to transmit 255 patterns of
1111_1111_0000_0000 on the 4-kbit/s data link bits (M1-
M12), RAI is transmitted for 255 patterns.of
1111_1111_0000_0000 (approximately 1 second)
2. If YEL[0] bit is set ’high’ for a duration longer than the time
required to transmit 255 patterns of 1111_1111_0000_0000
on the 4-kbit/s data link bits (M1-M12), RAI transmission
c o n tinue s u n til YEL [0] bit is set ’low’.
3. If YEL[0] bit forms another pulse during the RAI
transmission, it resets the pattern counter and extends the
RAI duration for another 255 patterns of
1111_1111_0000_0000. (approximatel y 1 second)
10 SF mode:
RAI is transmitt ed as a “1” in t he Fs bit of f rame 12 (This is RAI for
J1 SF standard).
T1DM mode:
RAI is transmitted as Y-bit = 0 (6th bit in the SYNC byte).
ESF mode:
RAI is co ntrolle d by the dur ation of YEL[1 ] bi t. This allows cont inu-
ous RAI of any length.
11 SF, N, and T1DM mode:
RAI for m at i s the same as described above when YEL[1:0] is set
to’01’.
ESF mode:
RAI duration is t he sam e as describe d above when YEL[1:0] is se t
to’01’, except that format of RAI is transmitted as 255 patterns of
1111_1111_1111_1111 (sixteen ones) on the 4kbits/s data l ink bits
instead of 255 pattern s of 1111_1111_0000_0000.
NOTE: 255 patterns of 1111_1111_1111_111 is the J1 ESF RA
I
standard)
XRT86VL32
17
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
5-4 YEL[1:0] R/W 00 (Continued)
TABLE 5: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0Xn108
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 7: YELLOW ALARM FORMAT WHEN ONE SECOND RULE IS ENFORCED
YEL[1:0] YELLOW ALARM FORMAT
00 Disable the transmission of yellow alarm
01 SF or N mode:
RAI is transmi tted a s bit 2 = 0 (s econd MSB) in a ll DS0 d ata c hannel.
T1DM mode:
RAI is transmitted as Y-bit = 0 (6th bit in the SYNC byte).
ESF mode:
YEL[1:0] cont ro ls the format of RAI. When YEL[1:0] is set to ’01’, RAI
is tran sm it ted as 255 pa tterns of 1111_1111_0000_0000 on the 4-
kbit/ s data link ( M 1-M12) (app roximately 1 second ).
ALARM_ENB (Bit 6 of this regi ster) cont rol s the durati on of RAI as
descri bed below:
1. If ALARM_ENB bit is set ’high’ for a duration shorter or equa
l
to the time required to transmit 255 pattern o
f
1111_1111_0000_0000 on the 4-kbit/s data l ink (M1-M12), RA
I
is tran sm it ted for 255 patterns. (approximatel y 1 second)
2. If ALARM_ENB bit is set ’high’ for a duration longer than the
time required to transmit 255 patterns o
f
1111_1111_0000_0000 on the 4-kbit/s data l ink (M1-M12), RA
I
conti nues until ALARM_ENB bit is set ’low’.
3. If ALARM_ENB forms another pulse during an alarm
transmission, it resets the pattern counter and extends the
RAI duration for another 255 patterns.(approximately 1
second)
NOTE: A minimum of one second delay between termination of the
first RAI and the initi ati on of a subsequent RAI is enforced.
10 SF mode:
RAI is tran smitt ed as a “1” in the Fs bi t of frame 1 2 (Th is is RAI for J 1
SF standard).
T1DM mode:
RAI is transmitted as Y-bit = 0 (6th bit in the SYNC byte).
ESF mode:
RAI is control led by the duration of ALARM_ENB bit. This allows
continuous RAI of any length.
11 SF, N, and T1DM mode:
RAI format is the same as described above when YEL[1:0] is set
to’01’.
ESF mode:
RAI duration is the same as described above when YEL[1:0] i s set
to’01’, except that format of RAI is transmitted as 255 patterns of
1111_1111_1111_1111 on the 4kbits/s data link bits (J1 ESF stan-
dard) in stead of 255 patterns of 1111_1111_0000_0000.
XRT86VL32
18
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3-2 Transmit AIS
Pattern
Select[1:0]
R/W 00 Transmit AIS Pattern Select[1:0]:
These two bits permit the user to do the following.
1. To select t he appropriate AIS Pattern that the Transmit T1 Framer block will
transmit to the remote terminal equipment, and
2. To command (via Software Control) the Tr ansmit T1 Framer bl ock to transmit
that particula r AIS Pattern to the remote terminal equipment, as depicted below.
NOTE: For normal operation (e.g., to configure the Transmit T1 Framer block to
transmit normal T1 traf fi c) the user should set this bit to “[X, 0]”
1-0 AIS Defect
Declaration
Crit e ria [1 :0 ]
R/W 00 AIS Defect Decl aration Criteria[1: 0]:
These bi t s permi t the user to speci fy the t ypes of AIS Patt erns that the Recei ve T1
Framer block mu st det ect before it will decl are the AIS defect condition.
TABLE 5: ALARM GENERATION REGISTER (AGR) HEX ADDRESS: 0Xn108
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
AISG[1:0] TYPES OF AIS PATTERNS T RANSMITTED
00/10 Disable AI S Alarm Genera ti on
The Transmi t T1 Framer block wi ll transmit “ normal” T1
traffic to the remote terminal equipment.
01 Enable Unframed AIS Alarm Generation
Transmi t T1 Fra me r bl ock will transm it an Unframed All
Ones Pattern, as an AIS Pattern.
11 Enable Framed AIS Alarm Gen eration
Transmi t T1 Fra me r bl ock will transm it a Framed, All
Ones Patter n, as the AIS Pattern.
AISD[1:0] AIS Defect Declaration Criteria
00/10 AIS Detectio n Disable d
AIS Defe ct Condi tion will NOT be declared.
01 Enable Unframed and Framed AIS Alarm Detection
ReceiveT1 Framer block will detect both Unframed and
Framed AIS patter n
11 Enable Framed AIS Alarm Detection
Receive T1 Framer block will detec t only Framed AIS pat-
tern
XRT86VL32
19
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 8: SYNCHRONIZATION MUX R EGISTER (SMR) HEX ADDRESS: 0Xn109
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6MFRAMEALIGN R/W 0Tr a nsmit M u lt ifra m e Syn c A lig n m e n t
This bit forces Tran sm it T1 framer block to align with th e backplane
multiframe boundary (TxMSYNC_n).
0 = Do not force the tra nsm it T1 framer block to align with t he TxM-
SYNC signal.
1 = Force the transmit T1 framer block to align with the TxMSYNC
signal.
NOTE: Thi s bit is not used in base ra te (1.544M Hz Clock) mode.
5MSYNC R/W OTransmit Super Frame Boundary
This bit prov id es an o ption to use the t ransm it single frame bou ndary
(TxSYNC) as the transmit multi-frame boundary (TxMSYNC) in high
speed or mu lt iplexed modes. In 1.544MHz clock mode (base rate),
the TxMSYNC is used as the transmit superframe boundary, i n othe r
clock modes (i.e. high speed or multiplexed modes), TxMSYNC is
used as an input transmi t clock for t he backplane interface.
0 = Configures the TxSYNC as a single frame boundary.
1 = Configures the TxSYNC as a superframe boundary (TxMSYNC)
in high-speed or multiplexed mode.
NOTE: Thi s bit is not used in base ra te (1.544M Hz Clock) mode.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4Transmit Frame Sync
Select R/W 0Transmit Frame Sync Select
This bit permits the user to conf igure the Syst em -Side Terminal
Equipment or the T1 T ransmit Framer to dictate whenever the Trans-
mit T1 Fra mer blo ck wil l i niti ate i ts g ener ation and trans mission of t he
very next T1 frame. If the system side controls, then al l of the fol low -
ing will be true.
1. The corresponding TxSync_n and TxMSync_n pins will function
as input pins.
2. The Transm it T1 Framer block wil l i nitiat e it s generation of a new
T1 frame whenever it samples the corr esponding “TxSync_n” input
pin “high” (via the TxSerClk_n input cl ock signal).
3. The Transm it T1 Framer block wil l i nitiat e it s generation of a new
Multi frame wheneve r it sam ples the corr esponding “TxMSync_n”
input pin “high”.
This bi t can also b e used to select the direction of the transmit si ngle
frame boundary (TxSYNC) and multi-frame boundary (TxMSYNC)
dependin g on whe ther TxSERCL K is chos en as the t i ming sour ce for
the tran sm it section of t he framer. (C SS[1:0] = 01 in register 0xn100)
If TxSERCLK is chosen as the timing source:
0 = Configures TxSYNC and TxM SYNC as inputs. (Syst em Side
Controls)
1 = Configures TxSYNC and TxM SYNC as outputs. (Chip Controls)
If either Recovered Line Clock, MCLK PLL is chosen as the tim-
ing source:
0 = Configures TxSYNC and TxM SYNC as outputs. (Chip Controls)
1 = Configures TxSYNC and TxM SYNC as inputs. (Syst em Side
Controls)
NOTE: TxSERCLK is chosen as the transmit clock if CSS[1:0] of the
Clock Select Register (Register Address: 0xn100) is set to
b01. Recovered Clock is chosen as the transmit clock if
CSS[1:0] is set to b00 or b11; Internal Clock i s chosen as the
transmit clock if CSS[1:0] is set to b10.
3 - 2 Reserved - - Reserved
TABLE 8: SYNCHRONIZATION MUX R EGISTER (SMR) HEX ADDRESS: 0Xn109
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1CRC-6 Bits Source
Select R/W 0CRC-6 Bits Source Select
This bit permits the user to specify the sourc e of the CRC-6 bits,
within t he outbound T1 data-stream, as depicted below.
0 - Configures the T ransmi t T1 Fra me r block to internally compute
and inser t the CRC-6 bits wit hin the outbound T1 data-str eam.
1 - Configures the T ransmi t T1 Framer block t o externall y accept
data from the TxSer_n inp ut pin, and t o insert t his data into t he CRC-
6 bits within the outbound T1 data-stream.
This bit is ignor ed if CRC Multiframe Alignment i s dis abled
0Framing Bits Source
Select R/W 0Framing Bits Source Sel ect
This bit is used to specify the source for the Framin g bits that wil l be
inserted into the outbound T1 frames. The Framing bits can be gen-
erated i nternall y or insert ed from the transmit seri al input pi n.
(TxSER_n inp ut pi n)
0 = Configures the Transmit T1 Framer bl ock to internally generate
and insert the Frami ng bits into the outbound T1 data stream.
1 = Configures the Transmit T1 Framer block to externally accept
framing bit s from the TxSer_n input pi n, and to inser t this dat a to the
outbound T1 data-stream.
TABLE 8: SYNCHRONIZATION MUX R EGISTER (SMR) HEX ADDRESS: 0Xn109
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 9: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0Xn10A
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6Reserved - - Reserved
5-4 TxDLBW[1:0] R/W 00 Transmit Data Link Bandwidth[1:0]
These two bits are used to select the bandwidth for data link mes-
sage transmission. Data Li nk m essages can be transmitted at a
4kHz rat e or at a 2 kHz rate on o dd or eve n f raming bi ts depen ding on
the configuration of these t hree bits. The table bel ow specifies the
four di fferent configurations.
NOTE: This bit only applies to T1 ESF framing format. For SLC96
and N framing formats, FDL is a 4kHz data link channel. For
T1DM, FDL is a 8kHz dat a link channel.
3-2 TxDE[1:0] R/W 00 Tr ansmit D/E TimeSlot Source Select[1:0]:
These two bits specify the sour ce for transmit D/E time slots. The
table below shows t he different sour ces from which D/E time slots
can be inserted.
TXDLBW[1:0] TRANSMIT DATA LINK BANDWIDTH SELECTED
00 Data link bits are i nserted in every frame. Fac il ity
Data Link Bits (FDL) is a 4kHz data link channel.
01 Data link bi ts are inserted in eve ry other fra me .
Facilit y Dat a Link Bits (FDL) i s a 2kHz data link
channel carried by odd frami ng bits (Frames
1,5,9.....)
10 Data link bi ts are inserted in eve ry other fra me .
Facilit y Dat a Link Bits (FDL) i s a 2kHz data link
channel carried by even framing bit s (Frames
3,7,11.....)
11 Reserved
TXDE[1:0] SOURCE FOR TRANSMIT D/E TIMESLOTS
00 TxSER_n input pin - The D/E time slots are
inserted fr om the transmit serial dat a input pin
(TxSER_n) pin.
01 T r ansmit L APD Control ler - The D/ E time sl ots are
inserted from LAPD Contr oller.
10 Reserved
11 TxFRTD_n - The D/E time sl ots are inserted from
the transmit fractional input pin.
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1-0 TxDL[1:0] R/W 00 Transmit Data Link Source Select [1:0]
These two bits specify the sour ce for data link bits that will be
inser ted in t he outboun d T1 frames. The t able b elow shows t he three
different sources from which data link bits can be inserted.
TABLE 9: TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) HEX ADDRESS:0Xn10A
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TXDL[1:0] SOURCE FOR DATA LINK BITS
00 Trans mit LAPD Controller #1 / SLC9 6 Buffer - The
Data Li nk bits are inser ted fro m the T ransmit LAPD
Controller #1 or SLC96 Buffer.
NOTE: LAPD Controller #1 is the only LAPD
controller that can be used to transport
LAPD messag es through the data lin k bit s
01 TxSER_n input pin - The Data Link bits are
inserted fro m the transmit ser ial data input pi n
(TxSER_n) pin.
10 TxOH_n input pin - The Data Link bits are inserted
from the t ransmit overhead input pin. (TxOH_n)
11 Data Link bit s are forced to 1.
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 10: FRAMING CONTROL REGISTER (FCR) HEX ADDRESS: 0Xn10B
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reframe R/W 0Force Reframe
A ‘0’ to ‘ 1’ transi ti on will fo rce the Receiv e T1 Framer to restart the syn-
chronization process. This bi t field is automatically clea red (set to 0)
after frame synchronization is reached.
6Frami ng with CRC
Checking R/W 1Framing with CRC Checking in ESF
This bi t per mits the user to include CRC verification as a part of the
“T1/ESF Framing Alignm ent” process. If t he user enables this feature,
then the Receive T1 Framer block will also check and verify that the
incoming T1 data-stream cont ains correc t CRC dat a, prior to decl ari ng
the “I n-Frame” condition.
0 - CRC Verif ication is NOT included in the “Framing Alignment” pro-
cess.
1 - Receive T1 Framer block will also che ck for correct CRC values
prior to declaring the “In-Frame” condition.
5-3 LOF Tolerance[2:0] R/W 000 LOF Defect Declar ation Tolerance[ 2:0]:
These bits al ong with the LOF_RANGE[2:0] bi ts are used to defi ne the
LOF Defect Declarat ion c ri teria. The Receive T1 Framer block will
declare the LOF defect condit ion anytime it detect s
“LOF_Tolerance[2:0] ” out of “LOF_Range[2:0] framing bit er rors within
the incoming T1 data-stream.
The recommended LOF_TOLR value is 2.
NOTE: A “ 0” value f or LO F_TO LR i s intern ally bl ock ed. A LO F_T OLR
value must be spec ified.
2-0 LOF_Range[2:0] R/W 011 LOF Def ect Decl aration Range[2:0]:
These bits along with the “LO F_Tolerance[2:0] bits are used to define
the “ LOF Def ect Decl aration” cr iteria. The Re ceive T1 Framer bl ock wil l
declare the LOF Defect condition anyt ime it has recei ved
“LOF_Tolerance[2:0] out of “LOF_Range[2:0] f raming bit errors, within
the incoming T1 data-stream.
The recommended LOF_ANG value is 5.
NOTE: A “0” value for LOF_RANG is internally blocked. A LOF_RANG
value must be spec ified.
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 11: RECEIVE S IGNALING & DATA LINK SELECT REGISTER (RSDLSR) HEX ADDRESS: 0Xn10C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6Reserved - - Reserved
5-4 RxDLBW[1:0] R/W 00 Receiv e D ata Link B a ndw idth[ 1:0]:
These two bits select the ba ndwidth for data link message reception.
Data Link messages can be received at a 4kHz rate or at a 2kHz rate
on odd or even framing bits depending on the conf igurati on of these
bits. The t able below specifies the di fferent configurations.
NOTE: This bit only applies to T1 ESF framing format. For SLC96 and
N framing for m ats, FDL is a 4kHz data li nk channel. For T1DM ,
FDL is a 8kHz dat a link channel .
3-2 RxDE[1:0] R/W 00 Receive D/E Time-Slot Destination Select[1:0]:
These bits permit the user to specify th e “destination” circuitry that will
receive and process the D/E-Ti me-slot within the incoming T1 data-
stream.
RXDLBW[1:0] RECEIVE DATA LINK BANDWIDTH SELECTED
00 Received Data link bits are extracted in every
frame. Fac il ity Data Link Bi ts (FDL) is a 4kHz data
link channel.
01 Received Data link bits are extracted in every
other frame. Facility Data Link Bits (FDL) is a 2kHz
data link channel carried by odd f raming bits
(Frames 1,5,9.....)
10 Received Data link bits are extracted in every
other frame. Facility Data Link Bits (FDL) is a 2kHz
data link channel carried by even framing bi ts
(Frames 3,7,11.....)
11 Reserved
RXDE[1:0] DESTINATION CIRCUITRY FOR
RECEIVE D/E TIME-SLOT
00 RxSER_n output p in - The D/E time slots are out-
put to the recei ve serial data output pin (RxSER_n)
pin.
01 Receive LAPD Contr oll er Block - The D/E time
slots are output to Receive LAPD Controller Block.
10 Reserved
11 RxFRTD_n output pi n- The D/ E time sl ots are
output to the receive fracti onal output pin.
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1-0 RxDL[1:0] R/W 00 Receive Data-Link Dest ination Select[1:0]:
These bits specify the destinat ion circuitry, that is used to pr ocess the
Data-Link data, within the incoming T1 data-stream.
TABLE 11: RECEIVE S IGNALING & DATA LINK SELECT REGISTER (RSDLSR) HEX ADDRESS: 0Xn10C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
RXDL[1:0] DESTINATION CIRCUITRY FOR RECEIVE DATA-LINK
00 Receive LAPD Contr oll er Block # 1 and
RxSER_n - The Data Li nk bits are routed to the
Receive LAPD Controller block #1 and the
RxSER_n output p in
NOTE: LAPD Controller #1 is the only LAPD
controller that can be used to extract
LAPD message s thr ough the data li nk bits
01 RxSER_n- The Data Link bits are routed to the
RxSER_n output p in.
10 RxOH_n and RxSER_n - The Data Link bit s are
routed to the RxOH_n and RxSER_n outpu t pi ns.
11 Da ta L in k bits ar e fo r ce d to 1.
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 12: RECEIVE SIGNALING CHANGE REGISTER 0 (RSCR 0) HEX ADDRESS: 0Xn10D
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Ch. 0 RUR 0These bits indicate whether the Channel Associated signal ing data,
associated wit h Time-Slot s 0 through 7 within the incoming T1 d ata-
stream, has changed since the last read of thi s register, as depicted
below.
0 - CAS data (for T ime-slot s 0 through 7) has NOT changed since the
last read of this r egister.
1 - CAS data (for T ime-slot s 0 through 7) HAS change d since the last
read of this register.
NOTES: This regi ster is onl y active if the i ncom ing T1 data-stream is
using Channel Associated Signaling.
6Ch. 1 RUR 0
5Ch.2 RUR 0
4Ch.3 RUR 0
3Ch.4 RUR 0
2Ch.5 RUR 0
1Ch.6 RUR 0
0Ch.7 RUR 0
TABLE 13: RECEIVE SIGNALING CHANGE REGISTER 1(RSCR 1) HEX ADDRESS: 0Xn10E
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Ch.8 RUR 0These bits indicate whether the Channel Associated signal ing data,
associated wit h Time-Slot s 8 through 15 wit hin the incomi ng T1 data-
stream, has changed since the last read of thi s register, as depicted
below.
0 - CAS data (for Tim e-slot s 8 through 15) has NO T changed since the
last read of this r egister.
1 - CAS data (for Time -sl ots 8 thr ough 15) HAS chang ed since the last
read of this register.
This register is only active if the incomi ng T1 data-stream is using
Channel Associated Si gnaling.
6Ch.9 RUR 0
5Ch.10 RUR 0
4Ch.11 RUR 0
3Ch.12 RUR 0
2Ch.13 RUR 0
1Ch.14 RUR 0
0Ch.15 RUR 0
TABLE 14: RECEIVE SIGNALING CHANGE REGISTER 2 (RSCR 2) HEX ADDRESS: 0Xn10F
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Ch.16 RUR 0These bits indi cate whether the Ch annel Assoc iat ed signa li ng data, associ-
ated with Time-Slots 16 through 23 within the incoming T1 data-stream, has
changed since the last read of this register, as depicted below.
0 - CAS data (for Time-slots 16 through 23 ) has NOT changed since the l ast
read of this register.
1 - CAS data (for Time-slots 16 through 23) HAS changed since the last read
of this regi ster.
NOTE: This register is only active if the incoming T1 data-stream is using
Channel Associated Signaling.
6Ch.17 RUR 0
5Ch.18 RUR 0
4Ch.19 RUR 0
3Ch.20 RUR 0
2Ch.21 RUR 0
1Ch.22 RUR 0
0Ch.23 RUR 0
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 15: RECEIVE IN FRAME REGISTER (RIFR) HEX ADDRESS: 0Xn112
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7In Frame RO 0In Frame State
This READ-ONLY bit indicates whether the Receive T1 Framer block is
currently decl aring the “In-Frame” condition with the incoming T1 data-
stream.
0 - Indicates that the Receive T1 Framer block is currently declaring the
LOF (Loss of Frame) Defect condition.
1 - Indicates that the Receive T1 Fr am er block is currently declaring itself
to be in the “In- Frame” cond ition.
6-0 Reserved - - Reserved (E1 Mode Only )
TABLE 16: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0 Xn113
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7SLC-96 Data Link
Enable R/W 0SLC®96 DataLink Enable
This bit permits the user to conf igure the channel to suppor t the
transmission and recepti on of the “SLC-96 ty pe” of data-link mes -
sage.
0 - Channel does not support the tr ansmiss ion and recepti on of
“SLC-96” type of data-link messages. Regular SF framing bits will
be transmitted.
1 - Channel supports the transmission and recept ion of the “ SLC-
96” type of data-link messages.
This bit is only acti ve if the channel has been configured to operate
in either t he SLC-96 or the ESF Framing formats.
6MOS ABORT Disabl e R/W 0MOS ABORT Disable:
This bit permits the user to either enable or di sable the “Aut om atic
MOS ABORT” featur e wit hi n Transmit HDLC Control ler # 1. If the
user enables this feat ure, then Transm it HDLC Co ntrolle r bl ock # 1
will aut omatically transmit the ABORT Sequence (e.g., a zero fol-
lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-
tions from tr ansmitting a MOS type of message, to transmi tting a
BOS type of message.
If the use r di sables this feature, th en the T ransmit HDLC Contr oll er
Block # 1 will NOT transmit the ABORT sequence, whenever i t
abruptl y transit ions from tr ansm itti ng a MOS- type of messa ge to
transmi tting a BOS-ty pe of message.
0 - Enables th e “Aut om ati c M O S Abort ” feature
1 - Disables the “Automati c M OS Abort” feature
5Rx_FCS_DIS R/W 0Receive Frame Check Sequence (FCS) Verification Enable/Dis-
able
This bit permits th e user to config ure the Receive HDLC Control ler
Block # 1 to c ompute and ver ify t he FCS value withi n each incoming
LAPD message frame.
0 - Enables FCS Verific ati on
1 - Disables FCS Verification
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
4AutoRx R/W 0Auto Receive LAPD Message
This bit config ures the Receive HDLC Controller Block #1 to dis card
any incoming BOS or LAPD Message frame that exactl y match
which is cu rr ently stor ed in t he Receive HDLC1 buffer.
0 = Disables this “AUTO DISCARD” feature
1 = Enabl es this “AUTO D ISCARD” feature.
3Tx_ABORT R/W 0Tr ansmit ABORT
This bit configures the Transmit HDLC Controller Block #1 to trans-
mit an ABORT sequence (st ring of 7 or more consecut ive 1’ s) to the
Remote terminal.
0 - Configures the T ransmit HDLC Contr oller Block # 1 to fu nction
normally (e.g. , not transmit the ABORT sequence).
1 - Configures the T ransmit HDLC Contr oller block # 1 to t ransmit
the ABORT Sequence.
2Tx_IDLE R/W 0Transmit Idle (Flag Sequence Byte)
This bi t configur es the Transmit HDLC Controller Block #1 to uncon-
ditional ly t ra nsmit a repeat ing st ring of Flag Sequ ence octet s (0X7E)
in the data link channel to the Remote terminal. In normal condi-
tions , the Transmit HDLC Contr oller blo ck wil l repeatedly transm it
the Flag Sequence octet whenever there is n o MOS message to
transmit to the remote terminal equipment . However, if the user
invokes this “Transmit Idle Sequence” feature, then the Transmit
HDLC Controller block will UNCONDITIONALLY transmit a repeat-
ing stream of the Flag Sequence octet (thereby overwriting all out-
bound MOS data-link messages).
0 - Configures the T ransmit HDLC Controller Bl ock # 1 to transmit
data-link inf ormation in a “n ormal” manne r.
1 - Configures the Trans mit HDLC Controller block # 1 to trans mit a
repeating string of Flag Sequence Octets (0x7E).
NOTE: This bit is ignored if the Transmit HDLC1 controller is
operating in the BOS Mode - bit 0 (MOS/BOS) within this
reg ist er is set to 0.
TABLE 16: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0 Xn113
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1Tx_FCS_EN R/W 0Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permits th e user to config ure the Transmit HDLC Controller
block # 1 to compute and append FC S octets to the “back-end” of
each outbound MOS data- link message.
0 - Configures the Transmi t HDLC Controller bl ock # 1 to NOT com-
pute and append the FCS octets to the back-end of each outbound
MOS data -l ink message .
1 - Configures the Transmi t HDLC Controller bl ock # 1 TO CO M -
PUTE and app end t he FCS octet s t o the back- end of eac h outbou nd
MOS data -l ink message .
NOTE: This bit is ignored if the transmit HDLC1 controller has been
configured to operate in the BOS mode - bit 0 (MOS/BOS)
withi n th is register is set to 0.
0MOS/BOS R/W 0Message Oriented Sign ali ng/Bit Orien ted Si gnaling Send
This bit permits the user to enable LAPD transmission through
HDLC Contr oller Bl oc k # 1 usi ng ei ther BOS ( Bit-Orie nted Si gna ling)
or MOS (Message-Oriented Signaling) frames.
0 - Transmit HDLC Contr oller block # 1 BOS mess age Send.
1 - Transmit HDLC Contr oller block # 1 MOS message Send.
NOTE: Thi s is not an Enable bit . This bit must be set to "0" each t ime
a BOS is to be sent.
TABLE 16: DATA LINK CONTROL REGISTER (DLCR1) HEX ADDRESS: 0 Xn113
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 17: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR1) HEX ADDRESS: 0Xn114
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxHDLC1 BUFAvai l/
BUFSel R/W 0Transmit HDLC1 Buffer Available/Buffer Select
This bit has different function s, depending upon whether the user is
writing to or readin g from this register, as depict ed below.
If th e us e r is w rit in g data in t o thi s reg i st e r b it:
0 - Confi gures the Tr ansmit HDLC1 Controll er to read out and trans-
mit the data, residing within “ Transmit HDLC1 Buffer # 0", via the
Data Link channel t o the remote termi nal equipm ent.
1 - Confi gures the Tr ansmit HDLC1 Controll er to read out and trans-
mit t he data, residing wi thi n the “Transmit HDLC1 Buffer #1”, via the
Data Link channel t o the remote termi nal equipm ent.
If the user is reading data from this register bit:
0 - Indicates that “Transmit HDLC1 Buffer # 0" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC1 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 1 Buffer # 0" - Address locati on: 0xn600.
1 - Indicates that “Transmit HDLC1 Buffer # 1" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC1 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 1 Buffer # 1" - Address locati on: 0xn700.
NOTE: If one of these Transmit HDLC1 buffers contain a message
which has yet to be completely read-in and processed for
transmission by the Transmit HDLC1 controller, then this bit
will automatically reflect the val ue corresponding to the next
available buffer when it is read. Changing this bit to the in-
use buffer is not permitted.
6-0 TDLBC[6:0] R/W 0000000 Tr ansmit HDLC1 Message - Byte Count
The exact function of these bits d epends on whethe r the T ransmit
HDLC 1 Controller is configur ed to trans mit MOS or BOS mes sages
to the Remote Terminal Equipment.
In BOS MODE:
These bit fiel ds conta in the numbe r of repetit ions the BOS message
must be transmitted b efore the Tra nsm it HDLC1 controller gener-
ates the Transmit End of T ransfer (TxEOT) interrupt and halts trans-
mission. If these fields are set to 00000000, then the BO S message
will be transmitted for an indefinite number of times.
In MOS MODE:
These bit fields contain the length, in number of octets, of the me s-
sage to be transmitted. The length of MOS message specified in
these bits incl ude header bytes such as the SAPI, TEI, Control fiel d,
however, it does not include the FCS bytes.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 18: RECEIVE DATA LINK BYTE COUNT REGISTER (R DLBCR1) HEX ADDRESS: 0Xn115
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RBUFPTR R/W 0Recei ve HDLC1 Buff er-Poin ter
This bit Identifies which Receive HDLC1 buffer contai ns the most
recently received HDLC1 message.
0 - Ind icates that Re ceive HDLC1 Buf fer # 0 cont ains t he c ontent s o f
the most recently received HDLC message.
1 - Ind icates that Re ceive HDLC1 Buf fer # 1 cont ains t he c ontent s o f
the most recently received HDLC message.
6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count
The exact function of these bit s depends on whethe r the Rec eive
HDLC Controller Bl ock #1 is configured to receive MOS or BOS
messages.
In BOS Mode:
These seven bits conta in t he num ber of repetitions the BOS mes-
sage must be received before the Recei ve HDLC1 controll er gener-
ates th e Receive End of T rans fer (Rx EOT) inte rrupt . If t hese bit s are
set to “00 00000”, the message will be re ceived indefinitely and no
Receive End of Tra nsfer (RxEO T) in ter rupt will be generated.
In MOS Mode:
These seven bits conta in t he size in bytes of the HDLC1 message
that has bee n received and wri tt en into the Recei ve HDLC buffer.
The length of MOS message shown in these bits include header
bytes such as the SAPI, TEI, Control field, AND the FCS byt es.
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0Xn116
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxSB_ISFIFO R/W 0Transmit Slip Buffer Mode
This bit permits t he user to configure the Transmit Slip Buffer to function as
either “Sl ip-Buff er” Mode, or as a “FI F O”, as depict ed below.
0 - Confi gures the Transm it Slip Buffer to fun cti on as a “Slip-B uffer” .
1 - Confi gures the Transm it Slip Buffer to fun cti on as a “FIFO”.
NOTE: Transmit slip buffer is only used in high-speed or multiplexed mode
where TxSERCLKn must be configured as inputs only. Users must
make sure that the “Transmit Direction” timing (i.e. TxMSYNC) and
the TxSerClk input clock signal are synchronous to prevent any
transmit slips from occuri ng.
NOTE: The data latency is dictated by FIFO Latency in the FIFO Latency
Register (register 0xn117).
6-5 Reserved - - Reserved
4SB_FORCESF R/W 0Force Signaling Freeze
This bit p ermit s t he user t o fre eze an y signa ling up date on t he Rx SIGn outpu t
pin as well as the Receive Si gnali ng Array Regist er -RSAR (0xn500 -0xn51F)
until this bit is cleared.
0 = Signal ing on RxSIG and RSAR is updated immediately.
1 = Signal ing on RxSIG and RSAR is not updated until this bit i s set to ‘0’.
3SB_SFENB R/W 0Signal Freeze Enabl e Upon Buffe r Slips
T his b it enables si gnaling freeze for one multiframe after the recei ve buffer
slips.
If signaling freeze is enabled, t hen the “Receive Channel” will freeze al l si g-
naling updates on RxSIG pin and RSAR (0xn500-0xn51F) for at least “one-
mult ifr ame” perio d, aft er a “slip-e vent” has been detecte d within the “Rece iv e
Slip Buffer”.
0 = Disabl es signaling freeze for one mult i- frame after receive buff er slips.
1 = Enables signali ng freeze for one mu lti-f rame after receive buffer slip s.
2SB_SDIR R/W 1Slip Buffer (RxSync) Direction Select
This bit permits user to select the direction of the receive frame boundary
(RxSYNC) signal if the receive buffer is enabled. (i.e. SB_ENB[1:0] = 01 or
10). If slip buf fer is bypassed, RxSYNC is always an output pin.
0 = Selects the RxSync signal as an out put
1 = Selects the RxSync signal as an input
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1SB_ENB(1) R/w 0Receive Slip Buffer Mode Select
T hese bits sel ect modes of operation for the receive sl ip buffer. These two
bits also select the directi on of RxSERCLK and RxSYNC i n base clock rate
(2.048MHz). The following tab le shows the corresponding slip buf fer mode s
as well as the direction of the RxSYNC/RxSERCLK according to the setting
of these two bit s.
NOTE: U sers must make sur e that the RxSerClk input pin is synchronized to
the Recovered Clock signal for this particular channel to prevent any
buffer slips from occurring.
0SB_ENB(0) R/W 1
TABLE 20: FIFO LATENCY REGISTER (FFOLR) HEX ADDRESS: 0 Xn117
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-5 Reserved - - Reserved
4-0 Rx Slip B uff er FI FO
Latency[4:0] R/W 00100 Receive Slip Buff er FIFO Latency[4:0]:
These bits permit the user to specify t he “Receive Data” Laten cy (in
terms of RxSer C lk_n clock periods) , whenever the Recei ve Slip
Buffer has been configured to operate in the “FIFO” Mode.
NOTE: These bi ts a re only active i f the Receive Sli p Buffer has been
configured to operate in the FIFO Mode.
TABLE 19: SLIP BUFFER CONTROL REGISTER (SBCR) HEX ADDRESS: 0Xn116
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
SB_ENB
[1:0] RECEIVE SLIP BUFFER
MODE SELECT DIRECTION OF
RXSERCLK DIRECTION OF
RXSYNC
00/1 1 Receive Slip Buffer is
bypassed Output Output
01 Slip Buffer Mode Input Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
10 FIFO Mode.
FIFO data latency
can be programmed
b y the 'FIF O L atenc y
Register' (Address =
0xn117).
Input Depends on the
setting of SB_SDIR
(bit 2 of this register)
If SB_SDIR = 0:
RxSYNC = Output
If SB_SDIR = 1:
RxSYNC = Input
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 21: DMA 0 (WRITE) CONFIGURATION REGISTER (D0WCR) HEX ADDRESS: 0Xn118
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7DMA0 RST R/W 0DMA_0 Reset
This bit resets the transmit DMA (Write) channel 0.
0 = Normal oper ation.
1 = A zero to one t ransition resets the transmit DMA (Wri te) channel 0.
6DMA0 ENB R/W 0DMA_0 Enable
This bit enables the transmit DMA_0 (Write) interface. After a transmit
DMA is enabled, DMA transfers are only re quested when the tr ansm it
buffe r st atus bit s indicate that there is spa ce for a c om plete messa ge
or cell.
The DMA writ e channel is used by the external DMA controller to
transfer data from the external memory to the HDLC buffers within the
T1 Framer. The DMA Write cycle starts by T1 Framer asserting the
DMA Reques t (REQ0) ‘low’, then the exter nal DMA controller should
dri ve the DMA Acknowledge (ACK0) ‘low’ to indicate that it is ready to
start the transfer. The external DMA controller should place new dat a
on the Microprocessor data bus each time the Write Signal is Strobed
low if the WR is configured as a Wr ite Strobe. I f WR is configured as a
direction signal, then the external DMA controller would place new
data on the Microprocessor data bus each tim e the Read Signal (RD)
is Strobed low.
0 = Disabl es the transmit DMA_0 (Wri te) interface
1 = Enables the transmi t DMA_0 (Write) interface
5WR TYPE R/W 0Write Type Select
This bit selects the function of the WR si gnal.
0 = WR functi ons as a direction signal (indicates whether t he current
bus cycle is a read or writ e operation) and RD functions as a data
strobe signal .
1 =WR functi ons as a write strobe signa l
4 - 3 Reserved - - Reserved
2DMA0_CHAN(2) R/W 0Channel Select
These three bit s select which T1 channel wi thi n the XRT86 VL32 uses
the Transmit DMA_0 (W rite) interface.
000 = Channel 0
001 = Reserved
001 = Channel 2
011 = Re serv ed
1 xx = Rese rved
1DMA0_CHAN(1) R/W 0
0DMA0_CHAN(0) R/W 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 22: DMA 1 (READ) CONFIGURATION REGISTER (D1RCR) HEX ADDRESS: 0Xn119
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-6 Reserved - - Reserved
7DMA1 RST R/W 0DMA_1 Reset
This bi t re sets the Receive DMA (Read) Channel 1
0 = Nor mal operation.
1 = A zero to one transition resets t he Receive DMA (Re ad) channel 1.
6DMA1 ENB R/W 0DMA1_ENB
This bi t enables the Receive DMA_1 (Read) interface. After a receive
DMA is enabled, DMA transfers are only requ ested when the recei ve
cell bu ffe r contains a comple te message or cell.
The DMA read channel is used by the T1 Framer t o tr ansfer data from
the HDLC buffers within the T1 Framer to external memory. The DMA
Read cycle starts by T1 Framer asserting t he DMA Request (REQ1)
‘low’, then the ext ernal DMA c ontroller should drive the DMA Acknowl-
edge (ACK1) ‘lo w ’ to indi cate that i t is ready to receiv e the dat a. The
T1 Framer should place new data on the Microprocessor data bus
each time the Read Signal is Strobed low if the RD is con fi gured as a
Read Str obe. If RD is configured as a direction signal , then the T1
Framer would place new dat a on the Microprocessor data bus each
time the Wr ite Signal (WR) is Strobed low.
0 = Disable s the DMA_1 (Read) interface
1 = Enables the DMA_1 (Read) interface
5RD TYPE R/W 0READ Type Select
This bi t selects the function of the RD signal.
0 = RD fu nctions as a Read Strobe si gnal
1 = RD acts as a direction signal (indicates whether the current bus
cycle is a read or write ope ration), and WR works as a data strobe.
4 - 3 Reserved - - Reserved
2DMA1_CHAN(2) R/W 0Channe l Sel ect
These three bits select which T1 channel within the chip uses the
Receive DMA_1 (Read) interface.
000 = Channel 0
001 = Reserved
001 = Channel 2
011 = Reser ved
1xx = Reserved
1DMA1_CHAN(1) R/W 0
0DMA1_CHAN(0) R/W 0
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 23: INTERRUPT CONTROL REGISTER (ICR) HEX ADDRESS: 0Xn11A
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-3 Reserved - - Reserved
2INT_WC_RUR R/W 0I nterrupt Write-to-Clear or Reset -upon-Read Sel ect
This bit configures all Inter rupt S tatus bits to be either Reset Upon
Read or Write-to -Clear
0= Configu res all Interrupt Status bits to be Reset-Upon-Read
(RUR).
1= Configures all Interrupt Status bits to be Write-to-Clear (WC).
1ENBCLR R/W 0Interrupt Enable Auto Clear
This bit configures all interrupt enabl e bits to clear or not clear aft er
reading the interrupt status bit.
0= Configures all Interrupt Enable bits to not cleared after reading
the interrupt status bit. The corresponding Int errupt Enabl e bit will
stay ‘high’ after readi ng the interrupt status bit.
1= Configures all interrupt Enable bits to clear after reading the
inter rupt sta tus bit. The c orrespo nding in terru pt enabl e bit will be set
to ‘low ’ af ter reading the inte rr upt status bit.
0INTRUP_ENB R/W 0Interrupt Enable for Framer _n
This bit enables or disables the ent ire T1 Framer Blo ck for Interrupt
Generation.
0 = Disables the T1 framer block for Interrupt Generation
1 = Enabl es the T1 f ramer block for Interrupt Generation
TABLE 24: LAPD SELECT REGISTER (LAPDSR) HEX ADDRESS: 0Xn11B
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
[7:2] Reserved - - Reserved
[1:0] HDLC Contro ll er
Select[1:0] R/W 0HDLC Controller Select[1:0]:
These bits permit the user to select any of t he three (3) HDLC Con-
trol lers that he/she will use withi n this particular channel, as
depicted below.
00 & 11 - Selects HDLC Controller # 1
01 - Selects HDLC Controll er # 2
10 - Selects HDLC Controll er # 3
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 25: CUSTOMER INSTALLATION ALARM GENERATION REGISTER (CIAGR) HEX ADDRESS: 0Xn11C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
[7:4] Reserved - - Reserved
[3:2] CIAG R/W 00 CI Alarm Transmit (Only in ESF)
These two bit s are used to enabl e or di sable AIS-CI or RAI- CI gen -
eration in T1 ESF mode only.
Alarm Indication Signal-Customer Ins tallat ion (AIS-CI ) and Remote
Alarm In dication- Cust omer Ins tal lati on (RAI- CI) are int ende d for use
in a network to differentiate between an issue within the network or
the Customer Installation (CI).
AIS-CI
AIS-CI is an all ones signal with an em bedded signature of
01111100 11111111 (right-to left) which recurs at 386 bit intervals in-
the DS-1 signal.
RAI-CI
Remote Alar m Indication - Cus tomer Install ati on (RAI -CI) is a repeti-
tive patter n with a period of 1.08 seconds. It com pri ses 0.99 sec-
onds of RAI message (00000000 11111111 Right-to-left) and a 90
ms of RAI-CI signat ure (00111110 11111111 Right to left) to form a
RAI-CI signal . RAI-CI applies t o T1 ESF framing m ode only.
00/11 = Disables RAI-CI or AIS-CI alarms generati on
01 = Enables unf ramed AIS-CI alarm generation
10 = Enables RAI-CI al arm generation
[1:0] CIAD R/W 00 CI Alarm Detect (Only in ESF)
These two b its are used to enable or disabl e RAI-CI or AIS-CI alarm
detection in T1 ESF mode only.
00/11 = Disables the RAI-CI or AIS-CI alar m detection
01 = Enables the unframed AIS-CI alarm detectio n
10 = Enables the RAI-CI al arm detection
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 26: PERFORMANCE REPORT CONTROL REGISTER (PRCR) H EX ADDRESS: 0Xn11D
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7LBO_ADJ_ENB R/W 0T ransmit Line Build Out Auto Adjust me nt:
This bit is used to enable or disable the transmit li ne build out aut o
adjustment feat ure. When the transmitter of the device is sending
AI S cond i tio n , th e tra n s mit lin e bu il d out w ill a u to ma tically be a d ju st
to one setting lower i f this feature is enabled. (Please refer to the
EQC[4:0] bits in regi ster 0x0Fn0 for dif ferent set ti ngs of T ransmit
Line Build O ut) . This feat ure i s designed to for power saving pur-
poses when an AIS signal is being t ransm itted.
1 - Enables th e tra n smit line buil d out auto adjust m ent feature.
0 - Disabl es the t ransmit li ne build out aut o adjustmen t f eature.
NOTE: Thi s feature is only available for T1 shor t haul appli cations.
6RLOS_OUT_ENB R/W 1RLOS Output Enable:
This bit i s used to e nable or disable the Rece ive LOS (RLOS_n) out-
put pins.
0 - Disables the RLOS output pin.
1 - Enables the RLOS output pin.
[5-3] Reserved - - Reserved.
2C/R_BIt R/W 0C/R Bit Control
This bi t allows user to control the v alue of C/R bit within an outgoing
perfor m ance report.
0 - Outgoing C/R bit will be set to’0’
1 - Outgoing C/R bit will be set to’1’
[1:0] APCR R/W 00 Automatic Perfor m ance Control/Res ponse Report
These bits automatically gener ates a summary report of the PMON
status so that i t can be inserte d into an out going LAPD messa ge.
Automatic perfor m ance report can be generated every time these
bits transition from ‘ b00’ to ‘b01‘ or automatically every one second.
The table below descr ibes the dif ferent APCR[1:0] bits setti ngs.
APCR[1:0] SOURCE FOR RECEIVE D/E TIMESLOTS
00/11 No performance report iss ued
01 Si ngle per formance report is issued when
these bits transitions from ‘b00’ to b’01’.
10 Auto ma ti cally is sues a perform ance report
every one second
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 27: GAPPED CLOCK CONTROL REGISTER (GCCR) HEX ADDRESS: 0Xn11E
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7FrOutclk R/W 0Framer Output Clock Reference
This bi t is used to enable or dis able high-s peed T1 rate on the
T1OSCCLK and the E1OS CCLK output pins.
By default, the output clock reference on T1OSCCLK and
E1OSCCLK o utput pins are set to 1 .544MHz/2.048MHz r espectively.
By setti ng this bit to a “1” , t he output clock reference on the
T1OSCLK and the E1O SCCLK are changed to 49.408MHz/
65.536MHz respec ti vely.
0 = Disables high-speed rate to be output on the T1OSCCLK and
E1OSCCLK output pins.
1 = Enables hig h-speed rate t o be output on the T1OSCCLK and
E1OSCCLK output pins.
[6:2] Reserved - - Reserved
1TxGCCR R/W 0Transmit Gapped Clock Interface
This bi t is used to enable or dis able the trans m it g apped clock int er-
face operating at 2.048Mbit/s in DS-1 mode. In this application, 63
gaps ( miss ing dat a) are i nsert ed so that th e overal l bit rat e is red uced
to 1.544Mbit/s.
If the transm it Gapped Clock Int erface is enabl ed:
TxMSYNC is used as the 2.048MHz G apped Clock Input.
TxSER is used as th e 2.048MHz Gapped Data Input.
TxSERCLK must be a 1.544MHz clock input.
0 = Disables the t ransmit gapped clock interface.
1 = Enables the transmit gapped clock interface.
0RxGCCR R/W 0Receive Gapped Clock Int erface
This bi t is used to enable or dis able the recei ve gapped clock inter-
face operating at 2.048Mbit/s in DS-1 mode. In this application, 63
gaps (m issing data) are extract ed so that the overall bit rate is
reduced to 1. 544Mbit/s.
If the Receive G apped Clock Inter face is enabled:
RxSERCLK should be configur ed as a Ga pped clock input at
2.048MHz so that a 2.048MHz G apped Clock can be app li ed to the
Frame r bl ock.
RxSER is used as the 2.048MHz Gapped Data Output. Th e position
of the gaps will be deter m ined by the gaps pl aced on RxSERCLK by
the user.
0 = Disables the Recei ve Gapped Cloc k Int erface
1 = Enables the Receive Gapped Clock Interfa ce
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0Xn120
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxSyncFrD R/W 0Tx Synchronous fractio n data interface
This bi t sel ects whether TxCHCLK or TxSERCLK wil l be used for fracti onal
data inp ut if fr acti onal i nterf ace is en abled. If TxSERCLK i s sel ected t o clock in
fract ional data input , TxCHCLK will be used as an enable si gnal
0 = Fracti onal data Is clocked into the chip using TxChCLK if fractional data
interface i s enabled.
1 = Fracti onal data is clocked into the chip using TxSerClk. TxChCl k is used
as fract ional data enable.
NOTE: The Time Slot Identifier Pins (TxChn[4:0]) still indicates the time slot
number if fractional data interface is not enabl ed. Fractional Interface
can be enabled by setting TxFr1544 to 1
6Reserved - - Reserved
5TxPLClkEnb/
TxSync Is Low R/W 0Transmit payl oad clock enable/TxSYNC is Active Low
This exact funct ion of thi s bit depends on whether the T1 framer i s configured
to operat e in base rate or hi gh speed modes of operation.
If the T1 framer is configure d to operate in base rate - TxPayl oad Clock:
This bi t configures the framer to output a regul ar clock or a payload clock on
the t ransmit seri al cl ock (TxSERCL K) pin wh en TxSERCL K is conf igur ed to be
an output.
0 = Conf igures t he framer to output a 1.544MHz clock on the TxSERCLK pin
when TxSERCLK is configured as an output.
1 = Conf igures t he framer to output a 1.544MHz clock on the TxSERCLK pin
when transmitting payload bits. T here will be gap s on the TxSERCLK output
pin when tr ansm itti ng overhead bits.
If the T1 framer is configure d to operate in high-speed or multiplexed
modes - TxSYNC is Active Low:
This bi t is used to select whether the trans mit frame boundary (TxSYNC) is
active low or active high.
0 = Select s TxSync to be active “High”
1 = Select s TxSync to be active “Low”
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4TxFr1544 R/W 0Fracti onal/Signaling Int erface Enabled
This bi t is used to enable or dis able the trans m it fractional dat a interfac e, sig-
nali ng input, as well as the 32MHz transm it clock and t he transmit overhe ad
Signal output.
0 = Confi gures t he 5 ti me sl ot iden tifier pins ( TxChn[ 4:0]) t o out put the channel
number as usual.
1 = Configures the 5 ti m e slot identifier pins (TxChn[4:0]) to function as the fol -
lowing:
TxChn[0] becomes the Transm it Seria l SI gnaling pin ( TxSIG_n) for si gnaling
inputs. Sig naling data can now be input from the TxSIG pin if configured
appropriately.
TxChn[1] becom es the T rans mit Fractional Data Input pin (TxFrTD_n) for fr ac -
tional data input . Fractional dat a can now be input from th e TxFrTD pi n if con-
figured appropr iately.
TxChn[2] becomes the 32 MHz tra nsm it clock out put
TxChn[3] becomes the Transm it Overhead Signal whi ch pulses high on the
first bit of each multi-frame.
NOTE: This bit has no effect in the high speed or multiplexed modes of
operation. In high-speed or multiplexed modes, TxCHN[0] functions
as TxSIGn for s ignaling input.
3TxICLKINV R/W 0T ransmit Clock Invers ion ( B ackplane Inter face)
This bi t selec ts whet her dat a transi tion will hap pen on the risi ng or fal ling edg e
of the transmit clock.
0 = Select s data transiti on to happen on the ris ing edge of the tr ansm it clock s.
1 = Selects data transition to happen on the fal ling edge of the transmit clocks.
NOTE: This feature is only available for base rate configuration (i.e. non-
highspeed, and non-multiplexed modes).
2TxMUXEN R/W 0Multiplexed Mode Enable
This bi t enables or di sable s the multiplexed mode. When multiplexed mo de is
enable, multi plexed data of four channels at 12.352 or 16.384MHz are dem ul-
tipl exed in side the transm it framer and se nt to 2 cha nnels on t he l ine sid e. The
backplane speed will be running at eit her 12.352 or 16.384MHz depending on
the multiplex ed mo de selected by TxIMODE[1: 0] of thi s register.
0 = Disables the multiplexed mode.
1 = Enables the multiplexed mode.
TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0Xn120
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1-0 TxIMODE[1:0] R/W 00 Transmit Interface M ode selection
This bi t determines the transmit i nterface speed. The exa ct functi on of these
two bit s depends on whether Mult ipl exed mode is enabled or disabl ed.
Table 29 and Table 30 shows the functions of these two bits for non-multi-
plexed and multiplexed modes.:
TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0Xn120
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 29: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED MODE IS
DISABLED (TXMUXEN = 0)
TXIMODE[1:0] TRANSMIT INTERFACE SPEED
00 1.544Mbit/s Base Rate Mode:
T ransmit Backplane interf ace signals include:
TxSERCLK is an inp ut or output clock at 1.544MHz
TxMSYNC is the superframe boundary at 3ms (ESF) or
1.5ms (SF)
TxSYNC is the single frame boundary at 125 us
TxSER is the bas e-r ate data input
01 2.048Mbit/s (High-Speed MVIP Mode) :
Transmit backplane interface signals include:
TxSERCLK is an inp ut cl ock at 1.544MHz
TxMSYNC is the high speed input clock at 2.048MHz to
input high-speed data
TxSYNC can be configured as a si ngle frame or super-
frame bound ary, de pending on the setting of bi t 5 of reg-
ister 0xn109
TxSER is the high-spee d data input
10 4.096Mbit/s High-Speed Mode:
T ransmit Backplane interf ace signals include:
TxSERCLK is an inp ut cl ock at 1.544MHz
TxMSYNC will becom e the high speed inp ut cl ock at
4.096MHz to input hig h-speed data
TxSYNC can be configured as a si ngle frame or super-
frame bound ary, de pending on the setting of bi t 5 of reg-
ister 0xn109
TxSER is the high-spee d data input
11 8.192Mbit/s High-Speed Mode:
T ransmit Backplane interf ace signals include:
TxSERCLK is an inp ut cl ock at 1.544MHz
TxMSYNC will becom e the high speed inp ut cl ock at
8.192MHz to input hig h-speed data
TxSYNC can be configured as a si ngle frame or super-
frame bound ary, de pending on the setting of bi t 5 of reg-
ister 0xn109
TxSER is the high-spee d data input
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1-0 TxIMODE[1:0] R/W 00 (Continued)
Transmit backplane i nterface signals include:
TxSERCLK is an inp ut cl ock at 1.544MHz
TxMSYNC will becom e the highspeed i nput clock at 12. 352 or 16.384MH z to
input high-spe ed mu ltiple xed data on the back-plane interface
TxSYNC can be configured as a si ngle frame or super -frame boundary,
depending on the setting of bit 5 of re gister 0xn109
TxSER is the high-spee d data input
NOTE: In hig h speed m ode, transmit data is sampled on t he rising edge of the
12Mhz or 16MHz clock edge.
TABLE 28: TRANSMIT INTERFACE CONTROL REGISTER (TICR) HEX ADDRESS:0Xn120
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 30: TRANSMIT INTERFACE SPEED WHEN MULTIPLEXED M ODE IS
ENABLED (TXMUXEN = 1)
TXIMODE[1:0] TRANSMIT INTERFACE SPEED
00 Bit- M ult iplexed Mode at 12.3 52M Hz is Enabl ed:
Transmit backplane interface is taking four-channel mul-
tiplexed dat a at a rate of 12.3 52M bit/s from channel 0
and bi t-dem ultiplexing the serial data into 4 channels
and output to the line on channels 0 through 3. The
TxSYNC signal pulses “High” duri ng the f raming bit of
each DS-1 fr am e.
01 Bit- M ult iplexed Mode at 16.3 84M Hz is Enabl ed:
Transmit backplane interface is taking four-channel mul-
tiplexed dat a at a rate of 16.3 84M bit/s from channel 0
and bi t-dem ultiplexing the serial data into 4 channels
and output to the line on channels 0 through 3. The
TxSYNC signal pulses “High” duri ng the f raming bit of
each DS-1 fr am e.
10 HMVIP High-Speed Multiplexed Mode Enabled:
Transmit backplane interface is taking four-channel mul-
tiplexed dat a at a rate of 16.3 84M bit/s from channel 0
and byt e-demultiplexing the serial data into 4 channels
and out put on ch annel s 0 t hrough 3. The TxSYNC sig nal
pulses “High” during the last two bits of the previous DS-
1 frame and the first two bi ts of the cur rent DS-1 frame.
11 H.100 High-Speed Multiple xed Mode Enabled:
Transmit backplane interface is taking four-channel mul-
tiplexed dat a at a rate of 16.3 84M bit/s from channel 0
and byt e-demultiplexing the serial data into 4 channels
and output to the line on channels 0 through 3. The
TxSYNC signal pulses “High” during the last bit of the
previous DS-1 frame and the fi rst bit of the current DS- 1
frame.
XRT86VL32
45
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 31: PRBS CONTROL & STATUS REGISTER (PRBSCSR0) HEX ADDRESS: 0XN121
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 Reserved - - These bits are not used
3PRBS_Switch R/W 0PRBS Switch
This bi t enables or disables the PRBS swit ch function with in t he
XRT86VL32 device.
By enabli ng the PRBS switch fu nction, PRBS functi onality wil l be
switched between the receiv e and tr ansm it framer. T1 Rece ive
framer will generate the PRBS pat tern and inser t it onto the recei ve
backplane interface, and T1 Transmit Fr am er wi ll be mon it oring the
transmit backplane interface for PRBS pat tern and declare PRBS
LOCK if PRBS has locked onto the input pattern.
If PRBS switch is disabl ed, T1 Transmit fr am er will generate the
PRBS pattern to the li ne int erface and the receive framer will be
monitoring the li ne for PRBS/QRTS pattern and de clare PRBS
LOCK if PRBS has locked onto the input pattern.
0 = Disabl es the PRBS Switch Feature.
1 = Enables t he PRBS Switc h Feature.
2BER[1] R/W 0Bit Error Rate
This bit is used to insert PRBS bit error at the rates presented a t the
table below. The exact function of this bit depends on whether
PRBS switc h function is enabled or not. (bit 3 wit hin this regist er).
If t he PRBS swit ch function is dis abled, bit err or wi ll be inserted by
the T1 tr ansm it framer out to the line interface if this bit is enabled.
If t he PRBS swit ch function is enabled, bit error will be in serted by
the T1 receive fr amer out to the receive backpl ane interf ace if this
bit is enabled.
1BER[0] R/W 0
BER[1:0] BI T ERROR RATE
00/11 Disable Bit Error inser tion to the transmit output
or receive backplane interface
01 Bit Error is inser ted to the transm it output or
receive backplane interface at a rate of 1/1000
(one out of one Thousand)
10 Bit Error is inser ted to the transm it output or
recei ve backplane interface at a rate of 1/
1,000,000 (one out of one million)
XRT86VL32
46
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
0UnFramedPRBS R/W 0Unframed PRBS Pattern
This bi t enables or disables unframed PRBS/QRTS p attern genera-
tio n (i.e. All tim eslots and framing bi ts are all PRBS/QRTS data).
The exact function of this bit depends on whether PRBS switch
function is enabled or not. (bit 3 within this register).
If PRBS switch functi on is di sabled, T1 Transm it Framer wi ll gener-
ate an unframed PRBS 15 or QR TS pattern to the line side if t his bit
is enabl ed.
If PRBS swit ch func tion is enab led , T1 Rec eive Fr amer wi ll ge nerate
an unframed PRBS 15 or QRTS pattern to the receive backplane
interface if this bit is enabled.
0 - Enables an unframed PRBS/QRTS p atter n generati on to the line
interface or to the receive backplane interface
1 - Disab les an unframed PRBS/QRTS pat tern gener ation to the line
interface or to the receive backplane interface
TABLE 31: PRBS CONTROL & STATUS REGISTER (PRBSCSR0) HEX ADDRESS: 0XN121
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
47
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 32: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RxSyncFrD R/W 0Receive Synchronous fractio n data interface
This bit sel ects whether RxCHCLK or RxSERCLK will be used for fractional
data output i f receive fract ional interface is ena bled. If RxSERCLK is selected
to clock out fractional data, RxCHCLK will be used as an enable signal
0 = Fracti onal data Is clocked out of the chip using RxChCLK if the receiv e
fractional interface is enabl ed.
1 = Fractional data is clocked out of t he chip using RxSer Clk if the receive
fract ional int erf ace is enabled. RxChClk is used as fr actional data enabl e.
NOTE: The Time Slot Identifier Pins (RxChn[4:0]) still indicates the time slot
number if the receive fractional data interface is not enabled.
Fractional Interface can be enabled by setting RxFr1544 to 1
6Reserved - - Reserved
5RxPLClkEnb/
RxSync i s low R/W 0Receive p ayload clock enable/RxSYNC is Active Low
This exact function of this bit depends on whether t he T1 fram er is configured
to operat e in base rate or high speed modes of oper ation.
If the T1 fram er is conf igured to operate in base rate - TxPayload Clock:
This bit configures the T1 framer to either output a regular clock or a payload
clock on the receive serial clock (RxSERCLK) pin when RxSERCLK is config-
ured to be an out put.
0 = Configures the framer to output a 1.544MHz clock on the RxSERCLK pin
when RxSERCLK is conf igured as an output.
1 = Configures the framer to output a 1.544MHz clock on the RxSERCLK pin
when receiving payload bits . There will be gaps on the RxSERCLK output pin
when recei ving overhead bits.
If the T1 fram er is configured to operate in hi gh-speed or mult iplexed
modes - RxSYNC is Acti ve Low:
This bit is used to select whether the rec eive frame boundary (RxSYNC) is
active low or active high.
0 = Selects RxSync to be active “High”
1 = Selects RxSync to be active “Low”
XRT86VL32
48
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4RxFr1544 R/W 0Receive Fractional /Si gnaling Interface Enabled
This bit is used to enable or disable the re ceive fract ional output inter face,
receive signaling output, the serial channel number output, as well as the
8kHz and the received rec overed clock output. This bit only functions when
the device i s configured in non-high speed or multiplexed modes of opera-
tions.
If the dev ice is configured in base rat e:
0 = Configures the 5 time slot identifier pins (RxChn[4:0]) to output the chan-
nel number in p a rallel as usual.
1 = Configures the 5 time slot identif ier pins (RxChn[4:0]) into the foll owing dif-
ferent functions:
RxChn[0] becomes the Receive Serial SIgnaling output pin (RxSIG_n) for sig-
naling outputs. Signaling data can now be output to the RxSIG pin if config-
ured appropriately.
RxChn[1] becomes the Receive Fractional Data Output pin (RxFrTD_n) for
fract ional data output. Fractional data can now be output to the RxFrT D pin if
configured appropriately.
RxChn[2] outputs the serial channel number
RxChn[3] outputs an 8kHz clock signal.
RxCHN[4] out puts the received rec overed clock signal (1. 544MHz for T1)
NOTE: This bit has no effect in the high speed or multiplexed modes of
operati on. In hi gh-spe ed or multi plexed modes, RxCHN[0] outputs the
Signal ing data and RxCHN[4] outputs the recovered clock.
3RxICLKINV N/A 0Receive Cl ock Inversion (Backplane Interface)
This bi t sele cts whet her dat a transi tion wil l happen on the risi ng or fal li ng edge
of the rec eive clock.
0 = Selects data t ransition to happen on the rising edge of the receive clocks.
1 = Selects data t ransition to happen on the falling edge of the receive clocks.
NOTE: This feature is only available for base rate configuration (i.e. non-
highspeed, or non-multip lexed modes) .
2RxMUXEN R/W 0Receive Multipl exed Mode Enable
This bit enables or disables the multiplexed mode on the rec eive side. When
multi plexed mode i s enable, data of four ch annels from the line si de are multi-
plexed onto one serial strea m inside the recei ve frame r and out put to the
back-pl ane interface on RxSER. The backplane speed wi ll becom e either
12.352MHz or 16.384MHz once mu ltiple xed m ode is enabled.
0 = Disables the m ultiplexed mode.
1 = Enables the multiplexed mode.
TABLE 32: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
49
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1-0 RxIMODE[1:0] R/W 00 Receive Interface Mode Selection[1: 0]
This bit determines the rece ive b a ckplane interface speed. The exact fun c-
tion of these two bits depends on whether Receive Multiplexed mode is
enabled or disable d. Table 33 and Table 34 shows the functions of these two
bits for non-multiplexed and multi plexed modes.:
TABLE 32: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 33: RECEIVE INTERFACE SPEED WHEN MULTIPLEXED MODE IS
DISABLED (TXMUXEN = 0)
RXIMODE[1:0] RECEIVE INTERFACE SPEED
00 1.544Mbit/s Base Rate Mode
Receive backplane interf ace signals include:
RxSERCLK is an input or out put clock at 1.544M Hz
RxSYNC is an input or out put signal whi ch indicat es the
receiv e singe frame boundary
RxSER is the base-rate data output
01 2.048Mbit/s High-Speed MVIP M ode:
Receive backplane interf ace signals include:
RxSERCLK is an input clock at 2.048MHz
RxSYNC is an input signal which indicates th e recei ve
singe fr am e boundary
RxSER is the high-speed data output
10 4.096Mbit/s High-Speed Mode:
Receive backplane interf ace signals include:
RxSERCLK is an input clock at 4.096MHz
RxSYNC is an input signal which indicates th e recei ve
singe fr am e boundary
RxSER is the high-speed data output
11 8.192Mbit/s High-Speed Mode:
Receive backplane interf ace signals include:
RxSERCLK is an input clock at 8.192MHz
RxSYNC is an input signal which indicates th e recei ve
singe fr am e boundary
RxSER is the high-speed data output
XRT86VL32
50
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1-0 RxIMODE[1:0] R/W 00 (Continued):(
Receive backplane interface signals incl ude:
RxSERCLK is a n input clock at eith er 12.3 52MHz or 16.384MHz depend ing on
the sel ected multiplexed mode.
RxSYNC is an input signal which indicates th e multiplex ed frame boundary.
The length of RxSYNC depends on the mul ti plexed mode selected.
RxSER is the high-speed data output
NOTE: In high speed mode, receive data is clocked out on the rising edge of
the 12Mh z or 16MHz clock edge .
TABLE 32: RECEIVE INTERFACE CONTROL REGISTER (RICR) HEX ADDRESS: 0XN122
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TABLE 34: RECEIVE INTERFACE SPEED WHEN MULTIPLEXED MODE IS
ENABLED (TXMUXEN = 1)
TXIMODE[1:0] TRANSMIT INTERFACE SPEED
00 Bit-Multiplexed Mode at 12. 352M Hz is Enabled:
Receive backplane interface is taking data from the four
LIU input channels 0 through 3 and bit-multiplexing the
four- channel data int o one 12 .35 2MHz ser ial strea m and
output on channel 0 of the Receive Serial Output
(RxSER). The RxSYNC signal pulses “High” during the
framing bit of each DS-1 frame.
01 Bit-Multiplexed Mode at 16. 384M Hz is Enabled:
Receive backplane interface is taking data from the four
LIU input channels 0 through 3 and bit-multiplexing the
four- channel data int o one 16 .38 4MHz ser ial strea m and
output to channel 0 of the Recei ve Serial Outp ut
(RxSER). The RxSYNC signal pulses “High” during the
framing bit of each T1 frame.
10 HMVIP High-S peed M ult iplexed Mode Enabled:
Receive backplane interface is taking data from the four
LIU in put cha nnel s 0 th rou gh 3 and byt e-mult iplex ing t he
four- channel data int o one 16 .38 4MHz ser ial strea m and
output to channel 0 of the Recei ve Serial Outp ut
(RxSER). The RxSYNC signal pulses “High” during the
last tw o bit s of the previ ous T1 frame and the first two
bits of the current T1 fram e.
11 H.100 High-Speed Multiplexed Mode Enabled:
Receive backplane interface is taking data from the four
LIU in put cha nnel s 0 th rou gh 3 and byt e-mult iplex ing t he
four- channel data int o one 16 .38 4MHz ser ial strea m and
output to channel 0 of the Recei ve Serial Outp ut
(RxSER). The RxSYNC signal pulses “High” during the
last bit of t he previous T1 fr am e and the first bit of the
current T1 frame.
XRT86VL32
51
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 35: PRBS CONTROL & STATUS REGISTER (PRBSCSR1) HEX ADDRESS: 0XN123
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7PRBSTyp R/W 0PRBS Patt ern Type
This bi t selects the type of PRBS pattern that the T1 T ransmit/
Receive framer will generate or detect. PRBS 15 (X15 + X14 +1)
Polynomial or QRTS (Quasi-Random Test Signal) Pat tern can be
generated by the transmit or receive framer depending on whet her
PRBS switc h function is enabled or not (bit 3 i n register 0xn121).
If the PRBS Switc h function is dis abled, T1 trans mit framer will gen-
erate either PRBS 15 or QR TS pattern and out put to the line in ter-
face. PRBS 15 or QRTS pattern depends on the setting of this bit.
If the PRBS Switch function is enabled, T1 receive framer will gener-
ate either PRBS 15 or QR TS pat tern and output to t he receive back
plane interface. PRBS 15 or Q RTS pattern depends on the setting
of thi s bit.
0 = Enables t he PRBS 15 (X15 + X14 +1) Polynomial generat ion.
1 = Enables the QRTS (Quasi-Random Test Si gnal) patt ern genera-
tion.
6ERRORIns R/W 0Error Insertion
This bi t i s used to insert a singl e PRBS/QRTS error to the tran sm it
or receive output depending on whether PRBS switch function is
enabled or not. (b it 3 in reg ister 0xn121).
If the PRBS Switc h function is dis abled, T1 trans mit framer will
insert a single PRBS/QRTS error and output to the li ne interf ace if
this bit is enabled.
If t he PRBS Switch f unction is enabled, T1 receive framer will ins ert
a singl e PRBS/QRTS err or and output to the receive back pl ane
interface if this bit is enabled.
A ‘0’ to ‘1’ tr ansition will cause one output bit inverted in the PRBS/
QRTS stream.
NOTE: Th is bit only works i f PRBS/QRTS generation is enabled.
5DATAInv R/W 0PRBS Data Invert:
This bi t i nverts the T ransmi t PRBS/QRTS output data and the
Receive PRBS/QR TS input data. The exact function of this bi t
depends on whether PRBS swit ch function is enabled or not. (bi t 3
in regi ster 0xn121).
If the PRBS Switch function is disabled and if this bit is enabled, T1
transmit framer will invert the PRBS/QRTS data before it outputs to
the line interface, and the T1 receive framer will inver t t he incoming
PRBS/QRTS data befor e it rec eives it.
If the PRBS Switch function and this bit are both enabled, T1
receive framer wil l i nvert the PRBS/QRTS data bef ore it outputs to
the line i nterf ace, and the T1 tr ansmit fram er will in vert the incom ing
PRBS/QRTS data befor e it rec eives it.
0 - Transm it and Re ceive Framer will NOT invert the Tra nsm it and
Receive PRBS/QRTS data.
1 - Transm it and Re ceive Framer will invert the Transmit and
Receive PRBS/QRTS data.
XRT86VL32
52
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
4RxPRBSLock RO 0Lock Status
This bi t indicat es whether or not the Recei ve or Tr ansmit PRBS lo ck
has obtained. The exact function of thi s bit depends on whether
PRBS switc h function is enabled or not. (bit 3 in register 0xn121).
If t he PRBS Switch function is disabled, T1 receive framer wil l
declare LOCK if PRBS/QRTS ha s locked onto the input pattern.
If the PRBS Switc h function is dis abled, T1 trans mit framer will
declare LOCK if PRBS/QRTS ha s locked onto the input pattern.
0 = Indic ates the Receive PRBS/QRTS has not Locked onto the
input patterns.
1 = Indic ates the Receive PRBS/QRTS has locked onto the input
patterns.
3RxPRBSEnb R/W 0Receive PRBS Detection/Genera tion Enable
This bi t enables or disables the receive PRBS/QRTS pattern detec-
tio n or genera tion. The exact func tion of th is bit depends on whet her
PRBS switc h function is enabled or not. (bit 3 in register 0xn121).
If t he PRBS swit ch function is disabled and i f th is bi t is enabled, T1
Receive Framer will det ect the incomi ng PRBS/QRTS pa ttern from
the line side and dec lare PRBS/QRTS lock if incom ing data loc ks
onto the PRBS/QRTS pattern.
If t he PRBS swit ch function and this bit are both enabl ed, T1 T rans-
mit Fra mer will detect the inc om ing PRBS/QRTS pattern from the
tran smit backpl ane inte rface and decl are PRBS/QRTS lo ck if incom-
ing dat a locks onto t he PRBS/QRTS pat tern.
0 = Disabl es the Receive PRBS/QRTS pattern detect ion.
1 = Enables t he Receive PRBS/QRTS pattern detection.
2TxPRBSEnb R/W 0Transmit PRBS Generation Enable
This bi t enables or di sables the Transm it PRBS p attern generator.
The exact function of this bit depends on whether PRBS switch
function is enabled or not. (bit 3 in register 0xn121).
If PRBS switch functi on is di sabled, T1 Transm it Framer wi ll gener-
ate the PRBS 15 or QRTS p attern to the line side if th is bit is
enabled.
If PRBS swit ch func tion is enab led , T1 Rec eive Fr amer wi ll ge nerate
the PRBS 15 or QRTS pattern to the receive backplane i nterface i f
this bit is enabled.
0 = Disabl es the Transmit PRBS/QRTS pattern generat or.
1 = Enables t he Tra nsm it PRBS/QRTS pattern generator.
1RxBypass R/W 0Receive Framer Bypass
This bi t enables or di sables the Receive T1 Framer bypass .
0 = Disabl es the Receive T1 frame r Bypass .
1 = Enables the Re ceive T1 Framer Bypass.
0TxBypass R/W 0Transm it Framer Bypass
This bi t enables or di sables the Transmit T1 Fra me r bypass .
0 = Disabl es the T ransmit T1 fr am er Bypass .
1 = Enables the Transmi t T1 Framer Bypass.
TABLE 35: PRBS CONTROL & STATUS REGISTER (PRBSCSR1) HEX ADDRESS: 0XN123
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
53
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 36: LOOPBACK CODE CONTROL REGISTER (LCCR) HEX ADDRESS: 0XN124
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-6 RXLBCALEN[1:0] R/W 00 Receive Loopback Code Activati on Length
This bi t determines the receive loopback code activation length.
There are four lengths supported by the XRT86VL32 as presented
in the table below:
5-4 RXLBCDLEN[1:0] R/W 00 Receive Loopback Code Deactivati on Length
This bi t determines the receive loopback code deacti vation length.
There are four lengths supported by the XRT86VL32 as presented
in the table below
RXLBCALEN[1:0] RECEIVE LOOPBACK CODE ACTIVATION
LENGTH
00 Selects 4-bi t receive loopback code activa-
tion Sequence
01 Selects 5-bi t receive loopback code activa-
tion Sequence
10 Selects 6-bi t receive loopback code activa-
tion Sequence
11 Selects 7-bi t receive loopback code activa-
tion Sequence
RXLBCDLEN[1:0] RECEIVE LOOPBACK CODE DEACTIVATION
LENGTH
00 Selects 4-bit receive loopback code deacti-
vation Sequence
01 Selects 5-bit receive loopback code deacti-
vation Sequence
10 Selects 6-bit receive loopback code deacti-
vation Sequence
11 Selects 7- bit receive loopback code deacti -
vation Sequence
XRT86VL32
54
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3-2 TXLBCLEN[1:0] R/W 00 Transmit Loopback Code Length
This bi t determines transmit loopback code length. There ar e four
lengths supported by the XRT86VL32 as presented in the t able
below
1FRAMED R/W 0Framed Loopback Code
This bit s elect s either fra med or unfra med l oopback c ode g enerati on
in the transmit path.
0 = Selects an “Unframed” loopback code for transmission.
1 = Selects a “fra me d” loopback code for transmission.
0AUTOENB R/W 0Remote Loopback Automatically
This bi t configur es the XRT86VL32 in remote loopback automati-
cally upon detecting the loopback code activation code specifi ed in
the Receive Loopback Code Activat ion Register if Receive activa-
tion loopback code is enabl ed (Register address:0xn126).
The XRT8 6VL32 wi ll c ancel t he remot e loopbac k upon det ectin g the
loopback code deactivation code specified in the Rec eive Loopback
Code Deacti vation register if t he Receive deactivati on loopback
code is enabled. ( R egister address:0xn127)
0 = Disables automatic r em ote loopback upon detecting the receiv e
acti vation code.
1 = Enables automatic remote loopback upon detecting the re ceive
acti vation code.
TABLE 36: LOOPBACK CODE CONTROL REGISTER (LCCR) HEX ADDRESS: 0XN124
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TXLBCLEN[1:0] TRANSMIT LOOPBACK CODE ACTIVATION
LENGTH
00 Selects 4-bi t transm it loopback c ode
Sequence
01 Selects 5-bi t transm it loopback c ode
Sequence
10 Selects 6-bi t transm it loopback c ode
Sequence
11 Selects 7-bi t transm it loopback c ode
Sequence
XRT86VL32
55
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 37: TRANSMIT LOOPBACK CODER REGISTER (TLCR) H EX ADDRESS: 0XN125
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-1 TXLBC[6:0] R/W 1010101 Transmi t Loopback Code
These seven bits determ ine the trans mit loopback code. The MSB
of the transmit loopback code is loaded first for transmission.
0TXLBCENB R/W 0Transmit Loopback Code Enable
This bi t enables loopback co de generation in the transm it path.
Tr ansmit loopback code is generated by writing the transmit loop-
back code in this re gister and enabl ing it usi ng thi s bit. The le ngth
and the format of the transmit loopback code is de termined by the
Loopback Code Control Register (Register address: 0xn124)
0 = Disabl es the transmit loopback code generatio n.
1 = Enables the transmi t l oopback code generati on.
TABLE 38: RECEIVE LOOPBACK ACTIVATION CODE REGISTER (RLACR) HEX ADDRESS: 0XN126
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-1 RXLBAC[6:0] R/W 1010101 Receive activation loopback code
These seven bits det ermine the receive loopback activation code.
The MSB of the receive activation loopback code is received first.
0RXLBACENB R/W 0Receive activation loopback code enable
This bi t enables the receive l oopback activation code detection.
Receive loopback activat ion code is detected by wri ti ng the
expected receive activation l oopback code in this regi ster and
enabling it using this bit.
The length and format o f the Receive loo pback activat ion code is
determined by the Loopback Code Control Register (Register
0xn124).
0 = Disabl es the receive l oopback code activat ion detection.
1 = Enables the r eceive loopback co de activati on detection.
TABLE 39: RECEIVE LOOPBACK DEACTIVATION CODE REGISTER (RLDCR) HEX ADDRESS: 0 XN127
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-1 RXLBDC[6:0] R/W 1010101 Receive deactivation loopback code
These se ven bi ts d ete rmine th e recei ve loopb ack de activ ation c ode.
The MSB of the receive deactivation loopback code is received first.
0RXLBDCENB R/W 0Receive deactivation loopback code enable
This bi t enables the receive l oopback deactivat ion code detection.
Receive loopback deactivation cod e is det ected by writing the
expected receive deactivation loopback code in this register and
enabling it using this bit.
The length and format of the Receive loopback deactivation code is
determined by the Loopback Code Control Register (Register
0xn124).
0 = Disabl es the receive l oopback code deactivation detection.
1 = Enables the r eceive loopback co de deactivation detection.
XRT86VL32
56
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 40: DEFECT DETECTION ENABLE REGISTER (DDER) HEX ADDRESS: 0XN129
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7DEFDET R/W 1For defect detection per ANSI T1. 231-1997 a nd T1.403-1999, use r
should leave thi s bit set to ‘1’.
TABLE 41: TRANSMIT SPRM CONTROL REGISTER (TSPRMCR) HEX ADDRESS: 0 XN142
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
5U1_BIT R/W 0U1 Bit
This bi t provides the content s of the U1 bit within the outgoing
SPRM message .
4U2_BIT R/W 0U2 Bit
This bi t provides the content s of the U2 bit within the outgoing
SPRM message .
3-0 R_BIT R/W 0000 R Bit
This bit pr ovides the contents of the R bit within the outg oing SPRM
message.
XRT86VL32
57
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 42: DATA LINK CONTROL REGISTER (DLCR2) HEX ADDRESS: 0Xn143
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7SLC-96 Data Link
Enable R/W 0SLC®96 DataLink Enable
This bit permits the user to conf igure the channel to suppor t the
transmission and recepti on of the “SLC-96 ty pe” of data-link mes -
sage.
0 - Channel does not support the tr ansmiss ion and recepti on of
“SLC-96” type of data-link messages. Regular SF framing bits will
be transmitted.
1 - Channel supports the transmission and recept ion of the “ SLC-
96” type of data-link messages.
NOTE: This bit is only active if the channel has been configured to
operate in either the SLC-96 or the ESF F raming formats.
6MOS ABORT Disabl e R/W 0MOS ABORT Disable:
This bit permits the user to either enable or di sable the “Aut om atic
MOS ABORT” featur e wit hi n Transmit HDLC Control ler # 2. If the
user enables this feat ure, then Transm it HDLC Co ntrolle r bl ock # 2
will automatical ly transmi t the ABORT Sequenc e (e. g., a zero fol-
lowed by a string of 7 consecutive “1s”) whenever it abruptly transi-
tions from tr ansmitting a MOS type of message, to transmi tting a
BOS type of message.
If the use r di sables this feature, th en the T ransmit HDLC Contr oll er
Block # 2 will NOT transmit the ABORT sequence, whenever i t
abruptl y transit ions from tr ansm itti ng a MOS- type of messa ge to
transmi tting a BOS-t ype of message.
0 - Enables th e “Aut om ati c M O S Abort ” fe ature
1 - Disables the “Automati c M OS Abort” feature
5Rx_FCS_DIS R/W 0Receive Frame Check Sequence (FCS) Verification Enable/Dis-
able
This bit permits th e user to config ure the Receive HDLC Control ler
Block # 2 to c ompute and ver ify t he FCS value withi n each incoming
LAPD message frame.
0 - Enables FCS Verific ati on
1 - Disables FCS Verification
4AutoRx R/W 0Auto Receive LAPD Message
This bit config ures the Receive HDLC Controller Block #2 to dis card
any incoming BOS or LAPD Message frame that exactl y match
which is cu rr ently stor ed in t he Receive HDLC1 buffer.
0 = Disables this “AUTO DISCARD” feature
1 = Enabl es this “AUTO D ISCARD” feature.
3Tx_ABORT R/W 0Tr ansmit ABORT
This bit configures the Transmit HDLC Controller Block # 2 to tran s-
mit an ABORT sequence (st ring of 7 or more consecut ive 1’ s) to the
Remote terminal.
0 - Configures the T ransmit HDLC Contr oller Block # 2 to fu nction
normally (e.g. , not transmit the ABORT sequence).
1 - Configures the T ransmit HDLC Contr oller block # 2 to t ransmit
the ABORT Sequence.
XRT86VL32
58
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2Tx_IDLE R/W 0Transmit Idle (Flag Sequence Byte)
This bi t configur es the Transmit HDLC Controller Block #2 to uncon-
ditional ly t ra nsmit a repeat ing st ring of Flag Sequ ence octet s (0X7E)
in the data link channel to the Remote terminal. In normal condi-
tions , the Transmit HDLC Contr oller blo ck wil l repeatedly transm it
the Flag Sequence octet whenever there is n o MOS message to
transmit to the remote terminal equipment . However, if the user
invokes this “Transmit Idle Sequence” feature, then the Transmit
HDLC Controller block will UNCONDITIONALLY transmit a repeat-
ing stream of the Flag Sequence octet (thereby overwriting all out-
bound MOS data-link messages).
0 - Configures the T ransmit HDLC Controller Bl ock # 2 to transmit
data-link inf ormation in a “n ormal” manne r.
1 - Configures the Trans mit HDLC Controller block # 2 to trans mit a
repeating string of Flag Sequence Octets (0x7E).
NOTE: This bit is ignored if the Transmit HDLC2 controller is
operating in the BOS Mode - bit 0 (MOS/BOS) within this
reg ist er is set to 0.
1Tx_FCS_EN R/W 0Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permits th e user to config ure the Transmit HDLC Controller
block # 2 to compute and append FC S octets to the “back-end” of
each outbound MOS data- link message.
0 - Configures the Transmi t HDLC Controller bl ock # 2 to NOT com-
pute and append the FCS octets to the back-end of each outbound
MOS data -l ink message .
1 - Configures the Transmi t HDLC Controller bl ock # 2 TO CO M -
PUTE and app end t he FCS octet s t o the back- end of eac h outbou nd
MOS data -l ink message .
NOTE: This bit is ignored if the transmit HDLC2 controller has been
configured to operate in the BOS mode - bit 0 (MOS/BOS)
withi n th is register is set to 0.
0MOS/BOS R/W 0Message Oriented Sign ali ng/Bit Orien ted Si gnaling Send
This bit permits the user to enable LAPD transmission through
HDLC Contr oller Bl oc k # 2 usi ng ei ther BOS ( Bit-Orie nted Si gna ling)
or MOS (Message-Oriented Signaling) frames.
0 - Transmit HDLC Contr oller block # 2 BOS mess age Send.
1 - Transmit HDLC Contr oller block # 2 MOS message Send.
NOTE: This is not an Enable bit. This bit must be set to "0" each
time a BOS is to be sent.
TABLE 42: DATA LINK CONTROL REGISTER (DLCR2) HEX ADDRESS: 0Xn143
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
59
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 43: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR2) HEX ADDRESS: 0Xn144
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxHDLC2 BUFAvai l/
BUFSel R/W 0Transmit HDLC2 Buffer Available/Buffer Select
This bit has different function s, depending upon whether the user is
writing to or readin g from this register, as depict ed below.
If th e us e r is w rit in g data in t o thi s reg i st e r b it:
0 - Confi gures the Tr ansmit HDLC2 Controll er to read out and trans-
mit the data, residing within “ Transmit HDLC2 Buffer # 0", via the
Data Link channel t o the remote termi nal equipm ent.
1 - Confi gures the Tr ansmit HDLC2 Controll er to read out and trans-
mit t he data, residing wi thi n the “Transmit HDLC2 Buffer #1”, via the
Data Link channel t o the remote termi nal equipm ent.
If the user is reading data from this register bit:
0 - Indicates that “Transmit HDLC2 Buffer # 0" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC2 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 2 Buffer # 0" - Address locati on: 0xn600.
1 - Indicates that “Transmit HDLC2 Buffer # 1" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC2 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 2 Buffer # 1" - Address locati on: 0xn700.
NOTE: If one of these Transmit HDLC2 buffers contain a message
which has yet to be completely read-in and processed for
transmission by the Transmit HDLC2 controller, then this bit
will automatically reflect the val ue corresponding to the next
available buffer when it is read. Changing this bit to the in-
use buffer is not permitted.
6-0 TDLBC[6:0] R/W 0000000 Tr ansmit HDLC2 Message - Byte Count
The exact function of these bits d epends on whethe r the T ransmit
HDLC 2 Controller is configur ed to trans mit MOS or BOS mes sages
to the Remote Terminal Equipment.
In BOS MODE:
These bit fiel ds conta in the numbe r of repetit ions the BOS message
must be transmitted b efore the Tra nsm it HDLC2 controller gener-
ates the Transmit End of T ransfer (TxEOT) interrupt and halts trans-
mission. If these fields are set to 00000000, then the BO S message
will be transmitted for an indefinite number of times.
In MOS MODE:
These bit fields contain the length, in number of octets, of the me s-
sage to be transmitted. The length of MOS message specified in
these bits incl ude header bytes such as the SAPI, TEI, Control fiel d,
however, it does not include the FCS bytes.
XRT86VL32
60
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 44: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR2) H EX ADDRESS: 0Xn145
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RBUFPTR R/W 0Recei ve HDLC2 Buff er-Poin ter
This bit Identifies which Receive HDLC2 buffer contai ns the most
recently received HDLC2 message.
0 - Ind icates that Re ceive HDLC2 Buf fer # 0 cont ains t he c ontent s o f
the most recently received HDLC message.
1 - Ind icates that Re ceive HDLC2 Buf fer # 1 cont ains t he c ontent s o f
the most recently received HDLC message.
6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count
The exact function of these bit s depends on whethe r the Rec eive
HDLC Controller Bl ock #2 is configured to receive MOS or BOS
messages.
In BOS Mode:
These seven bits conta in t he num ber of repetitions the BOS mes-
sage must be received before the Recei ve HDLC2 controll er gener-
ates th e Receive End of T rans fer (Rx EOT) inte rrupt . If t hese bit s are
set to “00 00000”, the message will be re ceived indefinitely and no
Receive End of Tra nsfer (RxEO T) in ter rupt will be generated.
In MOS Mode:
These seven bits conta in t he size in bytes of the HDLC2 message
that has bee n received and wri tt en into the Recei ve HDLC buffer.
The length of MOS message shown in these bits include header
bytes such as the SAPI, TEI, Control field, AND the FCS byt es.
XRT86VL32
61
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 45: DATA LINK CONTROL REGISTER (DLCR3) HEX ADDRESS: 0Xn153
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7SLC-96 Dat a
Link Enable R/W 0SLC®96 DataLink Enable
This bi t permit s the us er to conf igur e the channel to suppor t the t ran smissi on
and reception of the “SLC-96 type” of data- link message.
0 - Channel does not support the tr ansmiss ion and recepti on of “SLC-96”
type of data-link messages. Regular SF framing bits will be transmitted.
1 - Channel s upports the transmission and reception of t he “SLC-96 ” t ype of
data-link messages.
NOTE: This bit is only active if the channel has been co nfi gured to operate in
either the SLC-96 or the ESF Framing for m ats.
6MOS ABORT
Disable R/W 0MOS ABORT Disabl e:
This bit permits the user to either enable or disable the “Automatic MOS
ABORT” f eature withi n Tr ans mit HDLC Cont roller # 3. I f the u ser enab les th is
feature, then Transmit HDLC Controller block # 3 will automatically transmit
the ABORT Sequence (e.g., a zer o followed by a string of 7 consecutive
“1s”) whenever it abruptly transitions f rom transmitting a MOS type of mes-
sage, to t ransmitting a BO S type of mes sage.
If the u ser disa bles this f eature , then t he Tr ansmi t HDLC Contro ller Bloc k # 3
will NOT transmit the ABORT seq uence, whenev er i t abr uptly tra nsitions
from transmitting a MOS-type of message to transmitting a BOS-type of
message.
0 - Enables th e “Aut om ati c M O S Abort ” feature
1 - Disables the “Automati c M OS Abort” feature
5Rx_FCS_DIS R/W 0Receive Frame Check Sequence (FCS) Verification Enable/Disable
This bi t perm it s the user to configure the Receive HDLC Controller Block # 3
to compute and verify the FCS value wit hin each incoming LAPD message
frame.
0 - Enables FCS Verific ati on
1 - Disables FCS Verification
4AutoRx R/W 0Auto Receive LAPD Message
This bit configures the Receive HDLC Controller Block #3 to discard any
incomin g BOS or LAPD Mes sage fra me that exa ctly mat ch which is current ly
stored in the Receive HDLC3 buffer.
0 = Disables this “AUTO DISCARD” feature
1 = Enabl es this “AUTO D ISCARD” feature.
3Tx_ABORT R/W 0Tr ansmit ABORT
This bit configures the Transmit HDLC Controller Block #3 to transmit an
ABORT seq uence (stri ng of 7 or mor e consecutive 1’s) to the Remote term i-
nal.
0 - Configures the T ransmit HDLC Controller Bl ock # 3 to fu nction normally
(e.g. , not transmit th e ABORT sequence).
1 - Configures the T ransmit HDLC Controller bl ock # 3 to transmit the
ABORT Seque nce.
XRT86VL32
62
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2Tx_IDLE R/W 0Transmit Idle (Flag Sequence Byte)
This bi t configures the Tran sm it HDLC Controller Block #3 to uncondition ally
transmi t a repeatin g str ing of Flag Sequence o ctets (0X7E) in the data link
channel to the Remote terminal. In normal conditions, the Transmit HDLC
Controller block will repeatedly transmit the Flag Sequence oct et w henever
there is no MOS message to transmit to the remote terminal equipment.
However, if the user invokes this “Transmit Idle Sequence” feature, then the
Transmit HDLC Controller block will UNCONDITI ONALLY tra nsmit a repeat-
ing stream of the Flag Sequence octet (thereby overwriting all outbound
MOS data -link messages).
0 - Configures the T ransmit HDLC Contr oller Block # 3 to tr ansmit data-link
information in a “normal” manner.
1 - Configures the T ransmit HDLC Contr oller block # 3 to transmit a repeat-
ing string of Flag Sequence Octets (0x7E).
NOTE: Thi s bit is ign ored if the Transmit HDLC3 cont rol ler is operati ng in the
BOS Mode - bit 0 (MOS/BOS) within this register is set t o 0.
1Tx_FCS_EN R/W 0Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permi ts th e user to conf igure the Tr ansmit HDLC Cont roll er block # 3
to compute and append FCS octets to the “bac k-end” of each out bound
MOS data -l ink message .
0 - Configures the Tran sm it HDLC Contr oller block # 3 to NOT compute and
append the FCS octets to the back-end of each out bound MOS data-link
message.
1 - Configures the Transmi t HDLC Controller block # 3 TO COMPUTE an d
append the FCS octets to the back-end of each out bound MOS data-link
message.
NOTE: This bit is ignored if the transmit HDLC3 controller has been
confi gured to opera te in the BOS mo de - bit 0 (MO S/BOS) within this
register is set to 0.
0MOS/BOS R/W 0Message Oriented Sign ali ng/Bit Orien ted Si gnaling Send
This bit permits the user to enable LAPD transmission through HDLC Con-
troller Block # 3 using either BOS (Bit-Oriented Signaling) or MOS (Mes-
sage-Oriented Si gnaling) f rames.
0 - Transmit HDLC Contr oller block # 3 BOS mess age Send.
1 - Transmit HDLC Contr oller block # 3 MOS message Send.
NOTE: This is n ot an Enable bit. Thi s bit must be set to "0" each ti m e a BOS
is to be sent .
TABLE 45: DATA LINK CONTROL REGISTER (DLCR3) HEX ADDRESS: 0Xn153
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
63
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 46: TRANSMIT DATA LINK BYTE COUNT REGISTER (TDLBCR3) HEX ADDRESS: 0Xn154
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxHDLC3 BUFAvai l/
BUFSel R/W 0Transmit HDLC3 Buffer Available/Buffer Select
This bit has different function s, depending upon whether the user is
writing to or readin g from this register, as depict ed below.
If th e us e r is w rit in g data in t o thi s reg i st e r b it:
0 - Confi gures the Tr ansmit HDLC3 Controll er to read out and trans-
mit the data, residing within “ Transmit HDLC3 Buffer # 0", via the
Data Link channel t o the remote termi nal equipm ent.
1 - Confi gures the Tr ansmit HDLC3 Controll er to read out and trans-
mit t he data, residing wi thi n the “Transmit HDLC3 Buffer #1”, via the
Data Link channel t o the remote termi nal equipm ent.
If the user is reading data from this register bit:
0 - Indicates that “Transmit HDLC3 Buffer # 0" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC3 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 3 Buffer # 0" - Address locati on: 0xn600.
1 - Indicates that “Transmit HDLC3 Buffer # 1" is the next available
buffer. In this case, if the user wishes to write in the content s of a
new “outbound” Data Link M essage in to th e Tra nsm it HDLC3 Mes -
sage Buffer, he/she should proceed to write this message into
“Tran smit HDL C 3 Buffer # 1" - Address locati on: 0xn700.
NOTE: If one of these Transmit HDLC3 buffers contain a message
which has yet to be completely read-in and processed for
transmission by the Transmit HDLC3 controller, then this bit
will automatically reflect the val ue corresponding to the next
available buffer when it is read. Changing this bit to the in-
use buffer is not permitted.
6-0 TDLBC[6:0] R/W 0000000 Tr ansmit HDLC3 Message - Byte Count
The exact function of these bits d epends on whethe r the T ransmit
HDLC 3 Controller is configur ed to trans mit MOS or BOS mes sages
to the Remote Terminal Equipment.
In BOS MODE:
These bit fiel ds conta in the numbe r of repetit ions the BOS message
must be transmitted b efore the Tra nsm it HDLC3 controller gener-
ates the Transmit End of T ransfer (TxEOT) interrupt and halts trans-
mission. If these fields are set to 00000000, then the BO S message
will be transmitted for an indefinite number of times.
In MOS MODE:
These bit fields contain the length, in number of octets, of the me s-
sage to be transmitted. The length of MOS message specified in
these bits incl ude header bytes such as the SAPI, TEI, Control fiel d,
however, it does not include the FCS bytes.
XRT86VL32
64
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 47: RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR3) H EX ADDRESS: 0Xn155
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RBUFPTR R/W 0Recei ve HDLC2 Buff er-Poin ter
This bit Identifies which Receive HDLC3 buffer contai ns the most
recently received HDLC3 message.
0 - Ind icates that Re ceive HDLC3 Buf fer # 0 cont ains t he c ontent s o f
the most recently received HDLC message.
1 - Ind icates that Re ceive HDLC3 Buf fer # 1 cont ains t he c ontent s o f
the most recently received HDLC message.
6-0 RDLBC[6:0] R/W 0000000 Receive HDLC Message - byte count
The exact function of these bit s depends on whethe r the Rec eive
HDLC Controller Bl ock #3 is configured to receive MOS or BOS
messages.
In BOS Mode:
These seven bits conta in t he num ber of repetitions the BOS mes-
sage must be received before the Recei ve HDLC3 controll er gener-
ates th e Receive End of T rans fer (Rx EOT) inte rrupt . If t hese bit s are
set to “00 00000”, the message will be re ceived indefinitely and no
Receive End of Tra nsfer (RxEO T) in ter rupt will be generated.
In MOS Mode:
These seven bits conta in t he size in bytes of the HDLC3 message
that has bee n received and wri tt en into the Recei ve HDLC buffer.
The length of MOS message shown in these bits include header
bytes such as the SAPI, TEI, Control field, AND the FCS byt es.
XRT86VL32
65
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 48: DEVICE ID REGISTER (DEVID) HEX ADDRESS: 0XN1FE
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 DEVID[7:0] RO 0x39 DEVID
This r egister is used to i dentify t he XRT86VL32 Framer/LIU. The
value of this re gister is 0x39h.
TABLE 49: REVISION ID REGISTER (REVID) HEX ADDRESS: 0XN1FF
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 REVID[7:0] RO 00000001 REVID
This re giste r is used to identif y the revi sion number of the XRT86VL32.
The value of this r egister for the first revi sion is A - 0x01h.
NOTE: The content of this register is subject to change when a newer
revision of t he device is iss ued.
XRT86VL32
66
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 50: TRANSMIT CHANNEL CONTROL REGISTER 0-23 (TCCR 0-23) HEX ADDRESS: 0Xn300 TO 0Xn317
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7LAPDcntl[1] R/W 1Transmit LAPD Control
These bits select whic h one of the three Transmit LAPD controll er i s config-
ured to use D/E time slot (Octets 0-23) for transmitting LAPD messages.
The following table pr esents the different settin gs of these two bit s.
NOTE: All three Transmit LAPD Controllers can use D/E timeslots for
transmission. However, only Transmit LAPD Controller 1 can use
datalink for transmission. Register 0xn300 represents D/ E time slot
0, and 0xn317 represents D/E tim e slot 23.
6LAPDcntl[0] R/W 0
5 - 4 TxZERO[1:0] R/W 00 Selects Type of Zero Sup pression
These bits select the ty pe of zero code su ppression used by the
XRT86VL32 device
.
LAPDCNTL[1:0] LAPD CONTROLLER SELECTED
00 Transmi t LAPD Cont rol ler 1
01 Transmi t LAPD Cont rol ler 2
10 The TxDE[1:0 ] bit s in the T ransmit Sign aling and
Data Li nk Select Regist er (TSDLSR - Register
Address - 0xn10A, bit 3-2) determine the data
source for D/E time slots.
11 Transm it LAPD Controll er 3
TXZERO[1:0] TYPE OF ZERO CODE SUPPRESSION SELECTED
00 No zero code suppression is used
01 AT&T bit 7 stuffi ng is used
10 GTE zero code suppression is used. If GTE z ero
code suppression is used, bit 8 i s stuffed in non-sig-
naling frame. Otherwise, bit 7 is stuffed in signaling
frame if signaling bit is zero.
11 DDS zero code suppression is used. The value
0x98 replaces the input data
XRT86VL32
67
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
3-0 TxCond(3:0) R/W 0000 Transmi t Channel Conditi oning for Timeslot 0 to 23
These bits allow the user to subst itute th e input PCM data (Octets 0-23)
with internall y generated Conditio ning Codes prior to tr ansm ission to the
remote terminal equipment on a per-c hannel basis. The tabl e below pre-
sents the different conditioning codes based on the setting of these bi ts.
Register address 0xn300 represents time sl ot 0, and address 0xn317 repre-
sents time slot 23.
TABLE 50: TRANSMIT CHANNEL CONTROL REGISTER 0-23 (TCCR 0-23) HEX ADDRESS: 0Xn300 TO 0Xn317
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TXCOND[1:0] CONDITIONING CODES
0x0 / 0xE Contents of tim eslot octet are unchange d.
0x1 All 8 bit s of the selected timesl ot octet are invert ed (1’s
complemen t)
OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF
0x2 Even bits of the selected timeslot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA
0x3 Odd bit s of t he selected ti m e slot octet are inver ted
OUTPUT = (TIME_SLOT_OCTET) XOR 0x55
0x4 Contents of the selected timeslot octet will be substituted
with the 8 -bit value in the Transmit
Programmable User Code Register (0 xn320-0x n337),
0x5 Contents of the timeslot octet will be substituted with the
value 0x7F (BUSY Code)
0x6 Contents of the timeslot octet will be substituted with the
value 0xFF (VACANT Code)
0x7 Contents of the timeslot octet will be substituted with the
BUSY time slot code (111#_## ##), where ##### is the
Timesl ot number
0x8 Contents of the timeslot octet will be substituted with the
MOOF code (0x1A)
0x9 Contents of the timeslot octet will be substituted with the
A-Law Digital Mil liw att pattern
0xA Contents of the timeslot octet will be substituted with the
μ-Law Digit al Milliwatt pattern
0xB The MSB (bit 1) of input data is inverted
0xC All input data except MSB is inverted
0xD Contents of the timeslot octet will be substituted with the
PRBS X15 + X 14 + 1/QRTS pattern
NOTE: PRBS X15 + X 14 + 1 or QRTS pat tern depends on
PRBSType selected in the register 0xn123 - bit 7
0xF D/E time slot - The TxDE[2:0] bi ts in the Transmit Signal-
ing and Dat a Link Sele ct Register ( 0xn10A) will determine
the data source for D/E time slots.
XRT86VL32
68
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 51: TRANSMIT USER CODE REGISTER 0-23 (TUCR 0-23) HEX ADDRESS: 0Xn320 TO 0Xn337
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 TUCR[7:0] R/W b00010111 Transm it Pr ogrammable User code.
These eight bits all ow users to program any code in thi s register to
replace the input PCM data when the T ransmi t Channel Contr ol
Regist er (TCCR) is configured to repl ace timeslot octet with pro-
grammable us er code. (i.e. if TCCR is set to ‘0x4’ )
The default value of thi s register is an I DLE Code (b00010111).
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 52: TRANSMIT SIGNALING CONTROL REGISTER 0-23 (TSCR 0-23) HEX ADDRESS: 0Xn340 TO 0XN357
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7A (x) R/W See Note Tr ansmit Signaling bit A
This bi t al lows user to prov ide signaling Bit A (Octet s 0-23) if
Robbed-bit signaling is enabled (Rob_Enb bit of this register set to
1) and if signalling data is inserted from TSCR (TxSIGSRC[1:0] =
01 in thi s regi ster).
NOTE: Register 0xn340 represents signaling data for Time Slot 0,
and 0xn357 represents signaling data for Ti m e Slot 23.
6B (y) R/W See Note Tr ansmit Signaling bit B
This bi t al lows user to prov ide signaling Bit B (Octet s 0-23) if
Robbed-bit signaling is enabled (Rob_Enb bit of this register set to
1) and if signalling data is inserted from TSCR (TxSIGSRC[1:0] =
01 in thi s regi ster).
NOTE: Register 0xn340 represents signaling data for Time Slot 0,
and 0xn357 represents signaling data for Ti m e Slot 23.
5C (x) R/W See Note Tr ansmit Signaling bit C
This bi t al lows user to provide signali ng Bit C (Octets 0-23) if
Robbed-bit signaling is enabled (Rob_Enb bit of this register set to
1) and if signalling data is inserted from TSCR (TxSIGSRC[1:0] =
01 in thi s regi ster).
NOTE: Register 0xn340 represents signaling data for Time Slot 0,
and 0xn357 represents signaling data for Ti m e Slot 23.
4D (x) R/W See Note Tr ansmit Signaling bit D
This bi t al lows user to provide signali ng Bit D (Octets 0-23) if
Robbed-bit signaling is enabled (Rob_Enb bit of this register set to
1) and if signalling data is inserted from TSCR (TxSIGSRC[1:0] =
01 in thi s regi ster).
NOTE: Register 0xn340 represents signaling data for Time Slot 0,
and 0xn357 represents signaling data for Ti m e Slot 23.
3Reserved -See Note Reserved
2Rob_Enb R/W See Note Robbed-bit si gnaling enable
This bi t enabl es or disables Robbed-bit signaling transmission. If
robbed-bit si gnaling is enabled, signaling dat a is conveyed in the
8th posi tion of each si gnali ng chan nel by rep lacin g the origi nal LSB
of the voice channel with signaling data.
0 = Disables Robbed-bit signaling.
1 = Enables Robbed-bit signaling.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
NOTE: The default value for register address 0xn340 = 0x01, 0xn341-0xn34F = 0xD0, 0xn350 = 0xB3, 0xn351-0xn35F =
0xD0
1TxSIGSRC[1] R/W See Note Channel signali ng control
These bi ts det ermine t he source f or si gnali ng inf or mation, see t able
below.
0TxSIGSRC[0] R/W See Note
TABLE 52: TRANSMIT SIGNALING CONTROL REGISTER 0-23 (TSCR 0-23) HEX ADDRESS: 0Xn340 TO 0XN357
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
TXSIGSRC[1:0] SIGNALING SOURCE SELECTED
00/11 Signaling data is inserted from input PCM
data (TxSERn pin)
01 Signaling data is inserted from this register
(TSCRs).
10 Signaling data is inser ted from the Transmit
Signal ing i nput p in (TxSIG_n ) if the Transmi t
Signaling Interface bit is enabled (i.e.
TxFr1544 bit = 1 in the T ransmit Interf ace
Control Register (TICR) Register 0 xn120),
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 53: RECEIVE CHANNEL CONTROL REGISTER 0-23 (RCCR 0-23) HEX ADDRESS: 0Xn360 TO 0XN377
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7LAPDcntl[1] R/W 1Receive LAPD Control
These bits select which one of the three Receive LAPD contr oller will be
configured to u se D/E time slot (Octets 0- 23) for receivi ng LAPD m essages .
NOTE: All three LAPD Controller can use D/E timeslots for receiving LAPD
messages. However, only LAPD Controller 1 can use datalink for
reception.
NOTE: Register 0xn360 represents D/E time slot 0, and 0xn377 represents
D/E time slot 23.
6LAPDcntl[0] R/W 0
5-4 RxZERO[1:0] R/W 00 Type of Zero Suppression
These bits select the type of zero code suppression used by the
XRT86VL32 device.
LAPDCNTL[1:0] RECEIVE LAPD CONTROLLER SELECTED
00 Receive LAPD Controller 1
01 Receive LAPD Controller 2
10 The RxDE[1: 0] bits in t he Receive Signaling
and Data Link Select Register (RSDLSR -
Address - 0xn10C) determine the data
source for Receive D/E t ime slots.
11 Receive LAPD Controller 3
RXZERO[1:0] TYPE OF ZERO CODE SUPPRESSION
SELECTED
00 No zero code suppre ssion is used
01 AT&T bit 7 stuffing is used
10 GTE zero code suppres sion is used. If GT E
zero code suppression is used, bit 8 is
stuffed in non-signalin g frame. Otherwise,
bit 7 is stuffed in signal ing frame if signaling
bit is ze ro .
11 DDS zero code suppression is used. The
value 0x98 replaces the input data
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3-0 RxCOND[3:0] R/W 0000 Receive Channel Condit ioning for Timeslot 0 to 23
These bits allo w the user to substit ute the input line data (Octets 0-23) with
inter nally generated Conditioning Codes prior to transmission to the back-
plane interface on a per-channel basis. The t able below presents the dif fer-
ent conditioning codes based on the setting of these bit s.
NOTE: Register address 0xn300 represents time slot 0, and address
0xn317 represents time slot 23.
TABLE 53: RECEIVE CHANNEL CONTROL REGISTER 0-23 (RCCR 0-23) HEX ADDRESS: 0Xn360 TO 0XN377
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
RXCOND[1:0] CONDITIONING CODES
0x0 / 0xE Co ntents of timeslot octet are unchanged.
0x1 All 8 bits of the selected timeslot octet are inv ert ed (1’s
complement)
OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF
0x2 Even bits of th e selected timeslot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA
0x3 Odd bits of the selected time slot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0x55
0x4 Co ntents of t he selected ti m eslot octet will be substitut ed
with the 8 -bit value in the Receive
Programmable User Code Register (0xn380-0xn397) ,
0x5 Contents of the timesl ot octet will be substit uted with the
value 0x7F (BUSY Code)
0x6 Contents of the timesl ot octet will be substit uted with the
value 0xFF (VACANT Code)
0x7 Contents of the timesl ot octet will be substit uted with the
BUSY time sl ot code (111#_####), where ##### is the
Timeslot number
0x8 Contents of the timesl ot octet will be substit uted with the
MOOF code (0x1A)
0x9 Contents of the timesl ot octet will be substit uted with the
A-Law Digital Milliwatt pattern
0xA Co ntents of the timesl ot octet will be substit uted with the
μ-Law Digital Milliwatt pattern
0xB T he MSB (bit 1) of input data is inverted
0xC All input data except MSB is inve rted
0xD Contents of t he ti m eslot octet wil l be substit uted with the
PRBS X15 + X 14 + 1/QRTS pattern
NOTE: PRBS X15 + X 14 + 1 or QRTS patter n depends on
PRBSType selected in the register 0xn123 - bit 7
0xF D/E time slot - The RxDE[ 2:0] bit s in the Transm it Signal-
ing an d Dat a Link Sel ect Register (0xn10C) will determine
the data source for Recei ve D/E time slots.
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 54: RECEIVE USER CODE REGISTER 0-23 (RUCR 0-23) HEX ADDRESS: 0Xn380 TO 0XN397
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 RxUSER[7:0] R/W 11111111 Receive Programm able User code.
These eight bit s allow users to program any code in this register to
replace the received data when the Receive Channel Control Regi s-
ter ( RCCR) is configur ed to replace t imeslot oct et wi th the receiv e
programmable user code. (i.e. if RCCR is set to ‘0x4’)
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 55: RECEIVE SIGNALING CONTROL REGISTER 0-23 (RSCR 0-23) HEX ADDRESS: 0Xn3A0 TO 0XN3B7
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
6SIGC_ENB R/W 0Signaling substitution enable
This bi t enables or di sables signaling substit u ti on on the receive
side on a per channel basis. Once s ignaling substitut ion is enabled,
recei ved signali ng bits ABCD will be substituted with the ABCD val-
ues in the Receive Substitution Si gnaling Register (RSSR).
Signal ing subs ti tution onl y occurs in the out put PCM data
(RxSERn). Receive Signaling Arr ay Register ( RSA R - Addres s
0xn500-0xn5 1F) and the external Signaling bus (RxSIG_n) output
pin will not be aff ected.
0 = Disabl es signaling substi tution on the r eceive side.
1 = Enables si gnaling substitution on th e receive side.
5OH_ENB R/W 0Signaling OH i nterface output enable
This bi t enables or di sables signaling information to outp ut vi a the
Receive Overhead pin (RxOH_n) on a per channel basis. The sig-
naling information in the receive signaling array registers (RSAR -
Address 0xn500-0xn51F) is output to the receive overhead output
pin (RxOH_n) if this bi t i s enabled.
0 = Disabl es signaling informa ti on to output vi a RxOH_ n.
1 = Enables si gnaling informati on to output vi a RxO H_n.
4DEB_ENB R/W 0Per-channel debounce enable
This bi t enables or d isabl es the signa ling debo unce featu re on a p er
channel basis.
When t his feature is enabled, th e per-chann el signaling sta te must
be in the same state for 2 superf rames before the Receive Framer
updates signaling info rmation on the Receive Sign aling Array Regi s-
ter ( RSAR) and the Signaling Pin (R xSIGn). If the si gnaling bits for
two consecutive superframes are not the s am e, the current state of
RSAR and RxSIG will not change.
When t his feature is disabled, RSAR and RxSIG will be up dat ed a s
soon as the receive signali ng bits have changed.
0 = Disabl es the Signaling Debounce fea tur e.
1 = Enables the Signaling Debounce feature.
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
3-2 RxSIGC[1:0]] R/W 00 Signaling conditioning [1:0]
These bi ts al low user to sel ect t he f ormat of signa ling subst ituti on on
a per-channel basi s, as presented in the t able below.
1-0 RxSIGE[1:0] R/W 00 Receive Signaling Extraction [1:0]
These bits control per -channel signaling e xtraction as presented in
the table bel ow. Signal ing infor m ation can be extr acted to the
Receive Signaling Array Register (RSAR), the Receive Signaling
Output pin (RxSIG_n) if the Receive SIgnali ng Interf ace is enable,
or the Recei ve Overhead Interface output (RxOH_n) if OH_ENB bit
is enabl ed. (bit 5 of thi s register ).
TABLE 55: RECEIVE SIGNALING CONTROL REGISTER 0-23 (RSCR 0-23) HEX ADDRESS: 0Xn3A0 TO 0XN3B7
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
RXSIGC[1:0] SIGNALING SUBSTITUTION SCHEMES
00 Substitutes all si gnaling bit s with one.
01 Enables 16-code (A,B,C,D) si gnaling substi-
tution.
Users must write t o bit s 3-0 in the Receive Sig-
nali ng Substitution Register (RSSR) to provide
the 16-c ode (A,B,C, D) signal ing subst itut ion val -
ues.
10 Enables 4-code (A,B) signal ing substitution.
Users must write t o bit s 4-5 in the Receive Sig-
nali ng Substitution Register (RSSR) to provide
the 4-code (A,B) signali ng substitution values.
11 Enables 2-code (A) signaling substitution.
Users must write to bit 6 in the Receive Signal -
ing Substitu ti on Register ( RSS R) to pr ovide the
2-code (A) signaling substit uti on value s.
RXSIGE[1:0] SIGNALING EXTRACTION SCHEMES
00 No signaling i nformation is extra cted.
01 Enables 16-code (A,B,C,D ) signaling
extraction.
All signaling bits A,B,C,D will be extracted.
10 Enables 4-code (A,B) signaling extraction
Only si gnaling bits A,B will be extr acted.
11 Enables 2-code (A) signaling extraction
Only signali ng bit A will be extra cted.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 56: RECEIVE SUBSTITUTION SIGNALING REGISTER 0-23 (RSSR 0-23) HEX ADDRESS: 0Xn3C0 TO 0XN3D7
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 Reserved - - Reserved
3SIG16-A, 4-A, 2-A R/W 016-code/4-code/2-code Signaling Bit A
This bi t provi des the val ue of signa ling bit A to sub stitut e the recei ve
signaling bi t A on a per chan nel basis when 16-code or 4-code or 2-
code signaling substituti on is enabled.
2SIG16-B, 4-B, 2-A R/W 016-code/4-code Signaling Bit B
This bi t provi des the val ue of signa ling bit B to sub stitut e the recei ve
signaling bi t B on a per channel basi s when 16-code or 4-code sig-
nali ng substitution i s enabled.
1SIG16-C, 4-A, 2-A R/W 016-code Signaling Bit C
This bi t prov ides the value of signa ling bi t C to subst itut e the rec eive
signaling bi t C on a per channel basi s when 16-code signaling sub-
stitution is enabled.
0SIG16-D, 4-B, 2-A R/W 016-code Signaling Bit D
This bi t prov ides the value of signa ling bi t D to subst itut e the rec eive
signaling bi t D on a per channel basi s when 16-code signaling sub-
stitution is enabled.
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 57: RECEIVE SIGNALING ARRAY REGISTER 0 TO 23 (RSAR 0-23) HEX ADDRESS: 0Xn500 TO 0Xn517
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 Reserved - - Reserved
3 A RO 0These READ ONLY register s reflect the most recently recei ved sig-
nali ng value (A,B,C,D) associated with timesl ot 0 to 31. If signal ing
debounce feature is enabled, the received signaling state must be
the same for 2 superfr am es before thi s register is updated . If the
signa ling b its fo r two co nsecu tive s uperfr ames a re not the same, the
current value of this register will not be changed.
When Bit 7 within register 0xn107 is set to ’1’, signaling bits in this
register ar e updated on superframe bound ary
If t he signa ling de bounc e featur e is disabl ed o r if Bit 7 withi n regis ter
0xn107 is set to ’0 ’, this regis ter is update d as soon as the received
signaling bi ts have changed.
NOTE: The content of this register only has meaning when robbed-
bit signaling is enabled.
2 B RO 0
1 C RO 0
0 D RO 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 58: LAPD BUFFER 0 CONTROL REGISTER (LAPDBCR0) HEX ADDRESS: 0Xn600
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 LAPD Buff er 0 R/W 0LAPD Buffer 0 (96-Bytes) Auto Inc rementing
This regist er is used to transm it and receive LAPD messages within
buffer 0 of the HDLC controller. Any one of the three HDLC cont rol-
ler can be chosen in the LAPD Select Register (0xn11B) . Users
should determine the next avail able buffer by reading the BUFAVAL
bit ( bit 7 of the T ransmi t Dat a Link Byte Count Regi ster 1 (address
0xn114), Regist er 2 ( 0xn 144) and Regist er 3 (0x n154) dependi ng on
which HDLC cont roller is sel ected. If buffer 0 is avail able, wri ti ng to
buffer 0 will i nsert the message into the out going LAPD frame after
the LAPD message is sent and the data from the tr ansm it buffer
cannot be retrieved.
After detectin g the Rec eive end of transfer i nterrupt (RxEOT), users
should read the RBUFPTR bi t ( bit 7 of the Rec eive Data Li nk Byte
Count Register 1 (ad dress 0xn115 ), Register 2 (0xn145), or Regi s-
ter 3 (0 xn155) depen ding on which HDLC controll er is selec ted) to
determine which buffer contains the received LAPD message ready
to be read. If RBUFPTR bit indicates that buff er 0 is available to be
read, reading buffer 0 (Register 0xn600) continuously will retrieve
the entire received LAPD message.
NOTE: When writing to or reading from Buffer 0, the register is
automatically incremented such that the entire 96 Byte
LAPD message can be written into or read from buffer 0
(Register 0xn600) continuously.
TABLE 59: LAPD BUFFER 1 CONTROL REGISTER (LAPDBCR1) HEX ADDRESS: 0Xn700
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-0 LAPD Buff er 1 R/W 0LAPD Buffer 1 (96-Bytes) Auto Inc rementing
This regist er is used to transm it and receive LAPD messages within
buffer 1 of the HDLC controller. Any one of the three HDLC cont rol-
ler can be is chosen in the LAPD Select Register (0xn11B). Users
should determine the next avail able buffer by reading the BUFAVAL
bit ( bit 7 of the T ransmi t Dat a Link Byte Count Regi ster 1 (address
0xn114), Regist er 2 ( 0xn 144) and Regist er 3 (0x n154) dependi ng on
which HDLC cont roller is sel ected. If buffer 1 is avail able, wri ti ng to
buffer 1 will i nsert the message into the out going LAPD frame after
the LAPD message is sent and the data from the tr ansm it buffer 1
cannot be retrieved.
After detectin g the Rec eive end of transfer i nterrupt (RxEOT), users
should read the RBUFPTR bi t ( bit 7 of the Rec eive Data Li nk Byte
Count Register 1 (ad dress 0xn115 ), Register 2 (0xn145), or Regi s-
ter 3 (0 xn155) depen ding on which HDLC controll er is selec ted) to
determine which buffer contains the received LAPD message ready
to be read. If RBUFPTR bit indicates that buff er 1 is available to be
read, reading buffer 1 (Register 0xn700) continuously will retrieve
the entire received LAPD message.
NOTE: When writing to or reading from Buffer 0, the register is
automatically incremented such that the entire 96 Byte
LAPD message can be written into or read from buffer 0
(Register 0xn600) continuously.
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 60: PMON RECEIVE LINE CODE VIOLATION COUNTER MSB (RLCVCU) HEX ADDRESS: 0Xn900
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RLCVC[15] RUR 0Performance Monitor “Receive L ine Code Violation” 16-bit
Counter - Upper Byte:
These RESET-upon- READ bit s, along with tha t withi n the PMON
Receive Line Code Violation Counter Register LSB combine to
refl ect the cumulative number of inst ances th at Line Code Viol ation
has been detected by the Receive T1 Framer block since the last
read of this register.
This registe r contains the Most Signi ficant by te of this 16-bit of the
Line Code Violat ion coun ter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RLCVC[14] RUR 0
5RLCVC[13] RUR 0
4RLCVC[12] RUR 0
3RLCVC[11] RUR 0
2RLCVC[10] RUR 0
1RLCVC[9] RUR 0
0RLCVC[8] RUR 0
TABLE 61: PMON RECEIVE LINE CODE VIOLATION COUNTER LSB (RLCVCL) HEX ADDRESS: 0Xn901
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RLCVC[7] RUR 0Performance Monitor “Receiv e Line Code Violation” 16-bit
Counter - Lower Byte:
These RESET-upon- READ bit s, along with tha t withi n the PMON
Receive Line Code Violation Counter Register MSB combine to
refl ect the cumulative number of inst ances th at Line Code Viol ation
has been detected by the Receive T1 Framer block since the last
read of this register.
This registe r contains the Least Si gnificant byte of this 16-bit of the
Line Code Violat ion coun ter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RLCVC[6] RUR 0
5RLCVC[5] RUR 0
4RLCVC[4] RUR 0
3RLCVC[3] RUR 0
2RLCVC[2] RUR 0
1RLCVC[1] RUR 0
0RLCVC[0] RUR 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
.
.
TABLE 62: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER MSB ( RFAECU) HEX ADDRESS: 0Xn902
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RFAEC[15] RUR 0Perfor m ance M onitor “Receive Framing Alignment Erro r 16-Bit
counter” - U p p e r Byt e :
These RESET-upon- READ bit s, along with tha t withi n the “P MON
Receive Framing Alignment Error Counter Register LSB” comb ine
to reflect the cumulative number of instances that the Receive
Framing Alignment errors has been detected by the Receive T1
Framer block since the last read of this register.
This registe r contains the Most Signi ficant by te of this 16-bit of the
Receive Framing Alignm ent Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RFAEC[14] RUR 0
5RFAEC[13] RUR 0
4RFAEC[12] RUR 0
3RFAEC[11] RUR 0
2RFAEC[10] RUR 0
1RFAEC[9] RUR 0
0RFAEC[8] RUR 0
TABLE 63: PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER LS B (R FAECL) H EX ADDRESS: 0Xn903
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RFAEC[7] RUR 0Perform ance M onitor “Receive Framing Alignment Error 16-Bit
Counter” - Lower Byte:
These RESET-upon- READ bit s, along with tha t withi n the “P MON
Receive Framing Alignment Error Counter Register MSB” combi ne
to reflect the cumulative number of instances that the Receive
Framing Alignment errors has been detected by the Receive T1
Framer block since the last read of this register.
This registe r contains the Least Si gnificant byte of this 16-bit of the
Receive Framing Alignm ent Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RFAEC[6] RUR 0
5RFAEC[5] RUR 0
4RFAEC[4] RUR 0
3RFAEC[3] RUR 0
2RFAEC[2] RUR 0
1RFAEC[1] RUR 0
0RFAEC[0] RUR 0
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 64: PMON RECEIVE SEVERELY E RRORED FRAME COUNTER (RSEFC) HEX ADDRESS: 0Xn904
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RSEFC[7] RUR 0Per formance Monitor - Receive Sever ely Errored frame Counter
(8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Receive Severely Errored Frames have been
detected by the T1 Framer since the last read of this register.
in T 1 mode, Sever ely Er rored Frame is def ined as h aving f r aming bi t
errors in contiguous windows. In T1 SF mode, SEF is defi ned if Ft
bits have been received consecutively in er ror s for 0.75ms or 6 SF
frames. In T1 ESF mode, SEF is defined if FPS bit have been
received consecutivel y in errors for 3 ms or 24 ESF frames.
6RSEFC[6] RUR 0
5RSEFC[5] RUR 0
4RSEFC[4] RUR 0
3RSEFC[3] RUR 0
2RSEFC[2] RUR 0
1RSEFC[1] RUR 0
0RSEFC[0] RUR 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 65: PMON RECEIVE CRC-6 BIT ERROR COUNTER - MSB (RSBBECU) HEX ADDRESS: 0Xn905
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RSBBEC[15] RUR 0Per form ance Monitor “Rece ive Synchronization Bit Error 16-Bit
Counter” - Upper Byte:
These RESET-upon- READ bit s, along with tha t withi n the “P MON
Receive Sy nchronization Bit Error Counter Register LSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chroni za tion Bit er rors has been detect ed by the Rece iv e T1 Framer
block since the l ast read of this register.
This registe r contains the Most Signi ficant by te of this 16-bit of the
Receive Synchroni zation Bit Err or counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RSBBEC[14] RUR 0
5RSBBEC[13] RUR 0
4RSBBEC[12] RUR 0
3RSBBEC[11] RUR 0
2RSBBEC[10] RUR 0
1RSBBEC[9] RUR 0
0RSBBEC[8] RUR 0
TABLE 66: PMO N RECEIVE CRC-6 BIT ERROR COUNTER - LSB (RSBBECL) HEX ADDRESS: 0Xn906
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RSBBEC[7] RUR 0Per formance Mo nitor “Rece ive Synchronization Bit Error 16-Bit
Counter” - Lower Byte:
These RESET-upon- READ bit s, along with tha t withi n the “P MON
Receive Synchronization Bit Error Counter Regi ster MSB” combine
to reflect the cumulative number of instances that the Receive Syn-
chroni za tion Bit er rors has been detect ed by the Rece iv e T1 Framer
block since the l ast read of this register.
This registe r contains the Least Si gnificant byte of this 16-bit of the
Receive Synchroni zation Bit Err or counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6RSBBEC[6] RUR 0
5RSBBEC[5] RUR 0
4RSBBEC[4] RUR 0
3RSBBEC[3] RUR 0
2RSBBEC[2] RUR 0
1RSBBEC[1] RUR 0
0RSBBEC[0] RUR 0
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 67: PMON RECEIVE SLIP COUNTER (RSC) HEX ADDRESS: 0Xn909
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RSC[7] RUR 0Performance Monitor - Receive Slip Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Receive Slip events have been detected by the T1
Framer since the last read of this register.
NOTE: A slip event is defined as a replication or deletion of a T1
frame by the receiv e sli p buffer.
6RSC[6] RUR 0
5RSC[5] RUR 0
4RSC[4] RUR 0
3RSC[3] RUR 0
2RSC[2] RUR 0
1RSC[1] RUR 0
0RSC[0] RUR 0
TABLE 68: PMON RECEIVE LOSS OF FRAME COUNTER (RLFC) HEX ADDRESS: 0Xn90A
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RLFC[7] RUR 0Performance Monitor - Receive Loss of Frame Counter (8-bit
Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
inst a nces that Receive L oss of Frame condi tion h ave bee n detect ed
by the T1 Framer since the last read of thi s register.
NOTE: This counter counts once every time the Loss of Frame
condition i s declared. This counter provides the capabilit y to
meas ure an accumul ati on of short failure events.
6RLFC[6] RUR 0
5RLFC[5] RUR 0
4RLFC[4] RUR 0
3RLFC[3] RUR 0
2RLFC[2] RUR 0
1RLFC[1] RUR 0
0RLFC[0] RUR 0
TABLE 69: PMON RECEIVE CHANGE OF FRAME ALIGNMENT COUNTER (RCFAC) HEX ADDRESS: 0Xn90B
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RCFAC[7] RUR 0Perform ance Monitor - Receive Change of Frame Alignment
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Receive Change of Framing Alignment have been
detected by the T1 Framer since the last read of this register.
NOTE: C hange of Framing Al ignment (COFA) is declared when the
newly-locked framing pattern is different from the one
offe r e d b y o ff- li ne fra m e r.
6RCFAC[6] RUR 0
5RCFAC[5] RUR 0
4RCFAC[4] RUR 0
3RCFAC[3] RUR 0
2RCFAC[2] RUR 0
1RCFAC[1] RUR 0
0RCFAC[0] RUR 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 70: PMON LAPD1 FRAME CHECK SEQUENCE ERROR COUNTER 1 (LFCSEC1) H EX ADDRESS: 0Xn90C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7FCSEC1[7] RUR 0Perform ance M onitor - LAPD 1 Frame Check Sequence Error
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
inst a nces that Frame Chec k Seque nce Er ror ha ve been det ect ed by
the LAPD Contr oller 1 since the last read of this register.
6FCSEC1[6] RUR 0
5FCSEC1[5] RUR 0
4FCSEC1[4] RUR 0
3FCSEC1[3] RUR 0
2FCSEC1[2] RUR 0
1FCSEC1[1] RUR 0
0FCSEC1[0] RUR 0
TABLE 71: PRBS BIT ERROR COUNTER MSB (PBECU) HEX ADDRESS: 0Xn90D
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7PRBSE[15] RUR 0Performance Monitor - T1 PRBS Bit Error 16-Bit Counter -
Upper Byte:
These RESET-upon- READ bit s, along with tha t withi n the “P MON
T1 PRBS Bit Error Counter Register LSB” combine to reflect the
cumu lative num ber of inst ances tha t the Recei veT1 PRBS Bit errors
has been detected by the Receive T1 Framer block since the last
read of this register.
This registe r contains the Most Signi ficant by te of this 16-bit of the
Receive T1 PRBS Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6PRBSE[14] RUR 0
5PRBSE[13] RUR 0
4PRBSE[12] RUR 0
3PRBSE[11] RUR 0
2PRBSE[10] RUR 0
1PRBSE[9] RUR 0
0PRBSE[8] RUR 0
TABLE 72: PRBS BIT ERROR COUNTER LSB (PBECL) HEX ADDRESS: 0Xn90E
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7PRBSE[7] RUR 0Performance Monitor - T1 PRBS Bit Error 16-Bit Counter -
Lower Byte:
These RESET-upon- READ bit s, along with tha t withi n the “P MON
T1 PRBS Bit Error Counter Register MSB” combine to reflect the
cumu lative num ber of inst ances tha t the Recei veT1 PRBS Bit errors
has been detected by the Receive T1 Framer block since the last
read of this register.
This registe r contains the Least Si gnificant byte of this 16-bit of the
Receive T1 PRBS Bit Error counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6PRBSE[6] RUR 0
5PRBSE[5] RUR 0
4PRBSE[4] RUR 0
3PRBSE[3] RUR 0
2PRBSE[2] RUR 0
1PRBSE[1] RUR 0
0PRBSE[0] RUR 0
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 73: TRANSMIT SLIP COUNTER (TSC) HEX ADDRESS: 0Xn90F
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxSLIP[7] RUR 0Per for m ance M onit or - Transmi t Slip Counter (8-bi t Count er)
These Reset-Upon-Read bit fields reflect the cumulative number of
instances that Transmit Slip events have been det ected by the T1
Framer since the last read of this register.
NOTE: A slip event is defined as a replication or deletion of a T1
frame by the transmit sli p buff er.
6TxSLIP[6] RUR 0
5TxSLIP[5] RUR 0
4TxSLIP[4] RUR 0
3TxSLIP[3] RUR 0
2TxSLIP[2] RUR 0
1TxSLIP[1] RUR 0
0TxSLIP[0] RUR 0
TABLE 74: EXCESSIVE ZERO VIOLATION COUNTER MSB (EZVCU) HEX ADDRESS: 0Xn910
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7EZVC[15] RUR 0Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Upper Byte:
These RESET-upon- READ bit s, along with tha t within the “PMON
T1 Excessive Zero Violation Counte r Regi ster LSB” combine to
refl ect the cum ulative number of inst ances th at t he Re ceiveT1
Excessive Zero Vi olation has been detected by the Receive T1
Framer block since the last read of this register.
This registe r contains the Most Signi ficant by te of this 16-bit of the
Receive T1 Excessive Zero Vi olation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6EZVC[14] RUR 0
5EZVC[13] RUR 0
4EZVC[12] RUR 0
3EZVC[11] RUR 0
2EZVC[10] RUR 0
1EZVC[9] RUR 0
0EZVC[8] RUR 0
TABLE 75: EXCESSIVE ZERO VIOLATION COUNTER LSB (EZVCL) HEX ADDRESS: 0Xn911
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7EZVC[7] RUR 0Performance Monitor - T1 Excessive Zero Violation 16-Bit
Counter - Lower Byte:
These RESET-upon- READ bit s, along with tha t within the “PMON
T1 Excessive Zero Violation Counte r Regi ster MSB” combine to
refl ect the cum ulative number of inst ances th at t he Re ceiveT1
Excessive Zero Vi olation has been detected by the Receive T1
Framer block since the last read of this register.
This registe r contains the Least Si gnificant byte of this 16-bit of the
Receive T1 Excessive Zero Vi olation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter fir st before r eading the LSB counte r i n order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to cl ear the PMON count.
6EZVC[6] RUR 0
5EZVC[5] RUR 0
4EZVC[4] RUR 0
3EZVC[3] RUR 0
2EZVC[2] RUR 0
1EZVC[1] RUR 0
0EZVC[0] RUR 0
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 76: PMON LAPD2 FRAME CHECK SEQUENCE ERROR COUNTER 2 (LFCSEC2) H EX ADDRESS: 0Xn91C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7FCSEC2[7] RUR 0Perform ance M onitor - LAPD 2 Frame Check Sequence Error
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
inst a nces that Frame Chec k Seque nce Er ror ha ve been det ect ed by
the LAPD Contr oller 2 since the last read of this register.
6FCSEC2[6] RUR 0
5FCSEC2[5] RUR 0
4FCSEC2[4] RUR 0
3FCSEC2[3] RUR 0
2FCSEC2[2] RUR 0
1FCSEC2[1] RUR 0
0FCSEC2[0] RUR 0
TABLE 77: PMON LAPD2 FRAME CHECK SEQUENCE ERROR COUNTER 3 (LFCSEC3) H EX ADDRESS: 0Xn92C
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7FCSEC3[7] RUR 0Perform ance M onitor - LAPD 3 Frame Check Sequence Error
Counter (8-bit Counter)
These Reset-Upon-Read bit fields reflect the cumulative number of
inst a nces that Frame Chec k Seque nce Er ror ha ve been det ect ed by
the LAPD Contr oller 3 since the last read of this register.
6FCSEC3[6] RUR 0
5FCSEC3[5] RUR 0
4FCSEC3[4] RUR 0
3FCSEC3[3] RUR 0
2FCSEC3[2] RUR 0
1FCSEC3[1] RUR 0
0FCSEC3[0] RUR 0
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 78: BLOCK INTERRUPT STATUS REGISTER (BISR) HEX ADDRESS: 0XnB00
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved For E1 mode only
6LBCODE RO 0Loopback Code Block Interrupt Sta tus
This bi t i ndicates whether or not t he Loopback Code block has an
interrupt request awaiting service.
0 - Indicates no outstanding Loopback Code Block i nterrupt request
is awai ti ng service
1 - Indi cates the Loopback Code blo ck has an interrupt request
await ing serv ice. Inter rupt Ser vice rou tine sho uld branch to the inter-
rupt source and read the Loopback Code Interr upt Status regis ter
(address 0xnB0A) to clear the interrupt
NOTE: This bit will be reset to 0 after the microprocessor has
performed a read to the Loopback Code Interrupt Status
Register.
5RxClkLOS RO 0Loss of Recovered Clock Interrupt Status
This bi t i ndicates whether or not t he T1 receive fr ame r is currently
declaring the "Loss of Reco vered Clock" interrupt .
0 = I ndicates that the T1 Receive Framer Block is NOT currently
declaring the "Loss of Reco vered Clock" interrupt .
1 = Indic ates that the T1 Receive Framer Block is currently declar -
ing the "Loss of Recovered Clock" interrupt.
NOTE: This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4ONESEC RO 0One Secon d Interrupt St atus
This bi t indicat es whether or not t he T1 receive framer block i s cur-
rently declaring the "One Second" interrupt.
0 = I ndicates that the T1 Receive Framer Block is NOT currently
declaring the "O ne Second" int errupt.
1 = Indic ates that the T1 Receive Framer Block is currently declar -
ing the "O ne Second" int errupt.
3HDLC RO 0HDLC Block Interrupt Status
This bi t i ndicates whether or not t he HDLC block h as any interrupt
request awaiting service.
0 = I ndicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicat es HDL C Block has an int errupt request awai ting serv ice.
Interrupt Service routine should branch to t he interrupt source and
read the corresponding Dat a LInk S ta tus Register s (address
0xnB06, 0xnB16, 0xnB26, 0xnB1 0, 0xnB18, 0xnB28) to clear the
interrupt.
NOTE: This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generat ed the interr upt.
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2SLIP RO 0Sl ip Buf fer Block Interrup t Status
This bi t i ndicates whether or not t he Sli p Buffer block has any out-
standing interrupt request awaiting ser vice.
0 = I ndicates no outstanding Slip Buffer Block interrupt request is
awaiting service
1 = I ndicates Slip Buffer block has an interrupt request awaiting ser-
vice. Inter rupt Service routine should branch to the interrupt source
and read the Slip Buffer Interrupt Status re gister (add ress 0xnB08)
to clear the interrupt
NOTE: This bit will be reset to 0 after the microprocessor has
performed a read to the Slip Buffer Interrupt Status
Register.
1ALARM RO 0Alarm & Error Block Interrupt Status
This bi t i ndicates whether or not the Alarm & Error Block has any
outstandi ng interrupt request awaiting service.
0 = Indic ates no outstan ding interrupt request is awaiting ser vice
1 = Indicates the Alarm & Error Bl ock has an interrupt reque st await-
ing service. Interrupt service rout ine should branch to the i nter rupt
source and read the cor responding alarm and error status regis ters
(address 0xnB02, 0xnB0E, 0xnB40) to clear the interrupt.
NOTE: This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Alarm & Error
Interrupt Status register that generated the interrupt.
0T1 FR A ME RO 0T1 Frame r Bloc k Int errupt Status
This bi t indicat es whether or not t he T1 Framer block has any out-
standing interrupt request awaiting ser vice.
0 = Indic ates no outstan ding interrupt request is awaiting ser vice.
1 = Indicates t he T1 Framer Block has an interru pt request awaiti ng
service. Int errupt service ro uti ne should branch to the int errupt
source and read the T1 Framer status register (address 0xnB04) to
clear the int errupt
NOTE: This bit will be reset to 0 after the microprocessor has
performed a r ead to the T1 Framer Interrupt Status register.
TABLE 78: BLOCK INTERRUPT STATUS REGISTER (BISR) HEX ADDRESS: 0XnB00
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 79: BLOCK INTERRUPT ENABLE REGISTER (BIER) HEX ADDRESS: 0XnB01
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved For E1 mode only
6LBCODE_ENB R/W 0Loopback Code Block interrupt enable
This bi t permits the user to either enable or d isable the Loopback
Code Interrupt Block for interrupt generation.
Wr iting a “0 ” to this reg ister bit will d isabl e the Loo pback Code Block
for i nterrupt generation, a ll Loopback Code interrupts will be dis-
abled for interrupt generation.
If t he user writes a “1” to this regist er bi t, the Loopback Code Inter-
rupts at the “Block Level” wi ll be enabled. However, the individual
Loopback Code interrupts at the “Source Level” still need to be
enabled to in order to generate tha t partic ular inte rrupt to the inter-
rupt pin.
0 - Disables all Loopback Code Interrupt Block interru pt wi thi n the
device.
1 - Enables the Loopback Code interr upt at the “Bl ock-Leve l” .
5RXCLKLOSS R/W 0Loss of Recovered Clock Int errupt Enable
This bi t permits the user to either enable or d isable the Loss of
Recovered Clock Int errupt for interrupt generat ion.
0 - Disables t he Loss of Re covered Cl ock Inter rupt withi n the devi ce.
1 - Enables the Loss of Recovered Clock interrupt at the “Source-
Level”.
4ONESEC_ENB R/W 0One Second Interrupt Enable
This bit permits the user to either enable o r disable the O ne Second
Interrupt for interrupt generation.
0 - Disables the One Second I nterrupt with in t he device.
1 - Enables the One Second interrupt at th e “Source-Level”.
3HDLC_ENB R/W 0HDLC Block Interr upt Enabl e
This bit per mits the user to ei ther enable or disa ble the HDLC Block
for i nterrupt generation.
Wr iting a “0” to th is register bi t wi ll disable the HDLC Block for inter-
rupt generation, all HDLC interr upts wil l be disabled for i nterrupt
generation.
If t he user wr ites a “1” to t his reg ister bit, th e HDLC Block i nter rupt at
the “Block Level” will be enabled. However, the individual HDLC
interrupt s at the “Source Level” st ill need to be enabled in order t o
generate that parti cular int err upt to the interrupt pin.
0 - Disables all SA6 Block interrupt within the devi ce.
1 - Enables the SA6 interru pt at the “Bl ock-Level”.
XRT86VL32
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2SLIP_ENB R/W 0Slip Buffer Block I nter rupt Enable
This bi t permits the user to either enable or dis able the Slip Buffer
Block for interrupt generation.
Wr iting a “0” to th is r egister bit will disabl e the Slip Buf fer Block for
int errupt genera tion, then al l Sl ip Buf fer inte rrupt s wi ll be disab led for
interrupt generation.
If t he user writes a “1” to this regist er bi t, the Slip Buf fer Block inter-
rupt at th e “Bloc k Lev el” wil l be ena ble d. However, the i ndivi dual Sl ip
Buffer int errupts at the “Sour ce Level” sti ll need to be enabl ed in
order to generat e that particula r in terrupt t o the i nterrupt pi n.
0 - Disables all Slip Buffer Blo ck interru pt wi thi n the device.
1 - Enables the Slip Buffer inter rupt at the “Block-Lev el” .
1ALARM_ENB R/W 0Alarm & Error Block Interrupt Enabl e
This bi t permits the user to eith er enable or dis able the Alarm &
Error Block for interrupt gener ation.
Wr iting a “0” to th is register bi t wi ll disable the Alarm & Error Block
for interrupt generation, then all Alarm & Er ror interrupts will be dis-
abled for interrupt generation.
If t he user wr it es a “1” to this register bit, the Alarm & Error Block
int errupt at t he “Block Level” wil l be en abled. Howev er , the indiv idual
Alarm & Error interr upts at the “So urce Level” st ill need to be
enabled in order to generate that particular interrupt to the interrupt
pin.
0 - Disables all Alar m & Error Block interrupt within the devi ce.
1 - Enables the Al arm & Error interrupt at the “Block -Level”.
0T1FRAME_ENB R/W 0T1 Framer Block Ena ble
This bi t permits the user to either enable or d isable the T1 Fra mer
Block for interrupt generation.
Wr iting a “0” to th is regist er bi t wi ll disable the T1 Fr am er Bl ock for
interrupt generation, t hen all T1 Framer interrupts will be disabled
for i nterrupt generation.
If t he user writes a “1” to this regist er bi t, the T1 Framer Bl ock inter-
rup t a t th e “Block Lev el ” w ill b e e nab le d . H o w e ver, t h e ind ivid u al T1
Framer interrupts at the “Source Level” still need to be enabled in
order to generat e that particula r in terrupt t o the i nterrupt pi n.
0 - Disables all T1 Framer Bl ock interr upt within the devi ce.
1 - Enables the T1 Framer inter rupt at the “Block-Level”.
TABLE 79: BLOCK INTERRUPT ENABLE REGISTER (BIER) HEX ADDRESS: 0XnB01
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
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DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 80: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR) HEX ADDRESS: 0XnB02
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Rx OOF
State RO 0Receive Out of Frame Defect State
This READ-ONLY bit indicates whether or not the Recei ve T1 Framer block is
currently decl aring the “Out of Frame” defect condit ion within the in com ing T1
data-stream, as desc ri bed below.
Out of Frame def ect conditi on is declar ed wh en “TOLR” out of “RANG” errors in
the fra ming bit patt ern is detected. (Register 0xn10B)
0 – The Receive T1 Framer block is NOT curren tl y declaring the “Out of Fram e”
defect condition.
1 – The Receive T1 Framer block is currently declar ing the “Out of Frame” defect
condition.
6RxAIS State RO 0Receive Alar m Indi cation Status Defect S tate
This READ-ONLY bit indicates whether or not the Recei ve T1 Framer block is
currently declaring the AIS defect cond it ion withi n the i ncom ing T1 data-stream,
as described below.
AIS defe ct is d eclare d when AIS co nditi on pers ist s for 42 mill isecond s. AIS def ec t
is clea red when AIS c ondition is absent for 42 milli seconds .
0 – The Receive T1 Framer block is NOT currently declaring the AIS defect con-
dition.
1 – The Receive T1 Framer block is currently declaring the AIS defect condition.
5RxYEL
State RO 0Receive Yellow Alarm St ate
This READ-ONLY bit indicates whether or not the Recei ve T1 Framer block is
currently declaring the Yellow Ala rm condition within the incom ing T1 data-
stream, as described below.
Yellow alarm or Remote Alarm Indication (RAI) is declared when RAI condition
persists for 900 milliseconds. Yellow alarm or RAI is cleared immediately when
RAI conditi on is absent even if the T1 Framer is receivi ng T1 Idle or RAI-CI signa-
tures in ESF mode.
0 – The Receive T1 Framer block is NOT curren tl y declaring the Yell ow Alarm
condition.
1 – The Receive T1 Framer block is currently declaring the Yellow Alarm condi-
tion.
4LOS_State RO 0Framer Receiv e Loss of Signal (LOS) State
This READ-ONLY bit indicates whether or not the Receive T1 framer is currently
declaring th e Loss of Signal (LOS) conditi on within the inc om ing T1 data-stream,
as described below
LOS defect i s declared when LO S condition per sists for 175 consecutive bi ts.
LOS defect i s cleared when LOS condition is absent or when the received s ignal
reaches a 12.5% ones density for 175 consecutive bits.
0 = The Receive T1 Framer block is NOT currently declaring the Loss of Signal
(LOS) condition.
1 = The Receive T1 Framer block is cur rently declaring the Loss of Signal (LOS)
condition.
3LCV In t
Status RUR/
WC 0Line Code Violation Interrupt Status.
This Rese t-Upon- Read b it fiel d indi cates whether or not t he Re ceive T1 LIU blo ck
has detected a Line Code Vi olation interrupt since the last read of this register.
0 = Indicates no L ine Code Violation have occ urred since the last read of this reg-
ister.
1 = Indicat es one or more Line Code Violation interrupt has occurred since the
last r ead of this register.
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REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2Rx OOF
State
Change
RUR/
WC 0Change in Receiv e Out of Frame Def ect Condi tion Inter rupt S tatus.
This Reset-Upon-Read bi t field indicates whether or not the “ Change in Receive
Out of Frame Defect Condition” interrupt has occurred since the last read of this
register.
Out of Frame def ect conditi on is declar ed when “TOLR” out of “RANG” errors in
the fra ming bit patt ern is detected. (Register 0xn10B)
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will gener ate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Out of Frame def ect
condition.
2. Whenever the Receive T1 Framer block clears the Out of Frame defect
condition
0 = Indi ca tes th at the “Change i n Re ceive Out of Fr ame de fect c ondit ion” i nterr upt
has not occurred since the last read of this register
1 = Indi ca tes th at the “Change i n Re ceive Out of Fr ame de fect c ondit ion” i nterr upt
has occurred since the last re ad of this register
1RxAIS State
Change RUR/
WC 0Change in Receive AIS Condi tion Interrupt Status.
This Reset-Upon-Read bi t field indicates whether or not the “ Change in Receive
AIS Condit ion” interrupt has occurred since the last read of this regist er.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will gener ate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the AIS condition.
2. Whenever the Receive T1 Framer block clears the AIS condition
0 = Indicat es that the “Change in Receiv e AIS condi tion” in terrupt has not
occurred since the last read of this register
1 = Indicat es that the “Change in Receiv e AIS condi tion” in terrupt has oc curred
since the last rea d of this register
0RxYEL State
Change RUR/
WC 0Change in Receive Yellow Alarm Interrupt Status.
This Reset-Upon-Read bi t field indicates whether or not the “ Change in Receive
Yellow Alarm Condition” interrupt has occurred since the last read of this register.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will gener ate an
interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Yellow Alarm
condition.
2. Whenever the Receive T1 Framer block clears the Yellow Al arm condition
0 = Indicat es that the “Change in Receiv e Yello w Alarm conditi on” interr upt has
not occurred since the last read of this register
1 = Indicat es that the “Change in Receiv e Yello w Alarm conditi on” interr upt has
occurred since the last read of this register
TABLE 80: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR) HEX ADDRESS: 0XnB02
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
93
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 81: ALARM & ERROR INTERRUPT ENABLE REGISTER (AEIER) HEX ADDRESS: 0XnB03
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-5 Reserved - - Reserved (E1 mode only)
4 - - - This bit should be set to’0’ for proper operation.
3LCV ENB R/W 0Line Code violation interrupt enable
This bi t permits t he user to eithe r enable or disable the “Line Code Viola-
tion” interrupt within the XRT86VL32 device. If the user enables this inter-
rupt, then the Recei ve T1 Framer block wi ll ge nerate an int errupt when Li ne
Code V iol ation is detected.
0 = Disabl es the inter rupt generat ion when Line Code Vio lat ion is det ected.
1 = Enables the interrupt generation when Line Code Vio lation is detected.
2RxOOF ENB R/W 0Change in Out o f Frame Defect Condit ion i nterrupt enabl e
This bi t permits t he user to either enable or disable the “Chan ge in Out of
Frame Defect Condition” Int errupt, with in the XRT86VL32 device. If the
user enables this interr upt, then the Receive T1 Framer block will gen erate
an interrupt in response to either one of the following conditions.
1. The instant that the Receive T1 Framer block declares the Out of
Frame def ect condition.
2. The instant that the Receive T1 Framer block clears the Out of
Frame def ect condition.
0 – Disable s the “Change in Out of Fram e Defect Condition” Interrupt.
1 – Enables the “Change in Out of Frame Defec t Condi tion” In terrupt.
1RxAIS ENB R/W 0Change in AIS Condi tion interrupt enable
This bi t permits t he user to eithe r enabl e or disable t he “Change in AIS
Condition” Interrupt, wit hin the XRT86VL32 device. If the user enables thi s
inter rupt, the n the Recei ve T1 Framer block will gene rat e an interrupt in
response to eithe r one of the following condit ions.
1. The instant that the Receive T1 Framer block declares the AIS
condition.
2. The instant that the Receive T1 Framer block clears the AIS
condition.
0 – Disable s the “Ch ange in AIS Condition” Inter rupt .
1 – Enables the “Change in AIS Condition” Interrupt.
0RxYEL ENB R/W 0Change in Yellow alarm Condition interrupt enable
This bi t permits t he user to eithe r enable or disable the “Chan ge in Yellow
Alarm Condi ti on” Inter rupt, within the XRT86VL32 device. If the user
enables this interrupt, then the Receive T1 Fr ame r bl ock will gener ate an
interrupt in response to ei ther one of the following conditions.
1. The instant that the Receive T1 Framer block declares the Yellow
Alarm condi tion.
2. The instant that the Receive T1 Framer block clears the Yellow
Alarm condi tion.
0 – Disable s the “Change in Yellow Alarm Condition” In ter rupt.
1 – Enables the “Change in Yellow Alarm Condition” Interrupt.
XRT86VL32
94
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 82: FRAMER INTERRUPT STATUS REGISTER (FISR) HEX ADDRESS: 0XnB04
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-6 - - - Reserved ( For E1 mode only)
5SIG RUR/
WC 0Change in Signaling Bits Interrupt Status
This Reset-Upon-Read bi t field indicates whether or not the “ Change in
Signal ing Bits” int errup t has occurred si nce the last re ad of th is regist er.
If th is inter rupt i s enabled , then t he Rece ive T1 Fra mer block will gener ate
an interrupt whenever any one of the four signaling bits values (A,B,C,D)
has changed in any one of the 24 channels within the incoming T1
frames. Users can read the signaling change registers (address 0xn10D-
0xn10F) to det ermine which signalling channel has changed.
0 = Ind ica tes t hat th e “Change in Signal ing Bi ts” inte rrupt has not occ urred
since the last rea d of this register.
1 = Indicat es that the “Change in Signaling Bits ” interru pt has occurred
since the last rea d of this register.
NOTE: Thi s bit only has meaning when Robbed-Bit Signali ng is en abled.
4COFA RUR/
WC 0Change of Frame Ali gnment (COFA) Interr upt Status
This Reset-Upon-Read bi t field indicates whether or not the “ Change of
Framing Al ignment (C OFA)” int errupt has occurred si nce the last read of
this register. If thi s interrupt i s enabled, t hen the Receive T1 Framer block
will generate an interrupt whenever the Receive T1 Framer block detects
a Change of Framing Alignment Signal (e.g., the Framing bits have
appeared to move to a dif fer ent locati on within the incoming T1 data
stream).
0 = Indicat es that the “Change of Framing Ali gnm ent (COFA)” inter rupt
has not occurred since the last read of this regis ter.
1 = Indicat es that the “Change of Framing Ali gnm ent (COFA)” inter rupt
has occurred since the last re ad of this register.
3OOF_Status RUR/
WC 0Change in Receiv e Out of Frame Def ect Condi tion Inter rupt S tatus.
This Reset-Upon-Read bi t field indicates whether or not the “ Change in
Receive Out of Frame Defect Condition” int errupt has occurred since the
last r ead of this register.
Out of Frame def ect conditi on is declar ed when “TOLR” out of “RANG”
error s in t he framing bit pattern is detected. (Re gister 0xn10B)
If th is inter rupt i s enabled , then t he Rece ive T1 Fra mer block will gener ate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Out of Frame
defect condition.
2. Whenever the Receive T1 Framer block clears the Out of Frame
defect condition
0 = Indicat es that the “Change in Receiv e Out of Frame defect conditi on”
inter rupt has no t occurred si nce the last read of this re gister
1 = Indicat es that the “Change in Receiv e Out of Frame defect conditi on”
interrupt has occurred since the last read of this register
XRT86VL32
95
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
2FMD RUR/
WC 0Frame Mimic Det ection Interrupt Status
This Reset -Upon- Read bit fiel d indic ates whet her or no t the “ Frame Mimic
Detecti on” interrupt has occurred si nce the last read of this regi ster.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will
generate an inter rupt whenever the Receive T1 Framer block detects the
presence of Frame Mimic bits (i.e., the Payl oad bits have appeared to
mimic the Fr am ing Bit pat ter n within the incoming T1 data stream).
0 = Indicates that the “Frame Mimic Detection” interrupt has not occurred
since the last rea d of this register.
1 = Indicates that the “Frame Mimic Detection” interrupt has occurred
since the last rea d of this register.
1SE RUR/
WC 0Synchronization Bit Error (CRC- 6) I nter rupt Status
This Res et-Upon- Read bi t fi eld i ndicat es whet her or not the “ CRC-6 Err or”
interrupt has occurred since the last read of this register.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will
generate an inter rupt whenever the Receive T1 Framer block detects a
CRC-6 Error within the incoming T1 multiframe.
0 = Indicates that the “CRC-6 Error” interrupt has not occurred since the
last r ead of this register.
1 = Indicates that the “CRC-6 Erro r” interrupt has occurred si nce the last
read of this register.
0FE RUR/
WC 0Framing Error Interrupt Status
This Reset-Upon-Rea d bit field indicates whether or not a “Framing Error”
interrupt has occurred since the last read of this register.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will
generate an interrupt whenever the Rec eive T1 Framer block detects one
or more Frami ng Ali gnm ent Bit Error wi thi n the incoming T1 data str eam .
0 = Indicates that the “Framing Error ” interr upt has not occu rr ed since the
last r ead of this register.
1 = Indicat es that the “F raming Error ” inter rupt has occ urred si nce th e last
read of this register.
NOTE: This bit doesn't not necessarily indicate that synchronization has
been lost.
TABLE 82: FRAMER INTERRUPT STATUS REGISTER (FISR) HEX ADDRESS: 0XnB04
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
96
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 83: FRAMER INTERRUPT ENABLE REGISTER (FIER) HEX ADDRESS: 0XnB05
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
5SIG_ENB R/W 0Change in Signali ng Bits Interrupt Enable
This bi t permits the user to eit her enable or disabl e the “Chan ge in Sig-
nali ng Bit s” In terru pt, withi n the XR T86VL3 2 device. If t he user en ables
this interrupt, then the Receive T1 Frame r bl ock will gener ate an inter-
rupt when it detects a change in the any fo ur signaling bits (A ,B,C,D) in
any one of the 24 signaling channels. Users can read the signaling
change registers (address 0xn 10D-0xn10F) to determine whi ch signal -
li ng channel has changed st ate.
0 - Disables the Change in Signaling Bits I nterrupt
1 - Enables the Change in Signaling Bits Interrupt
NOTE: This bit has no m eaning when Robbed-Bit Signali ng is disabled.
4COFA_ENB R/W 0Chan ge of Framing Alignment (C OFA) Interrupt Enable
This b it per mits t he user t o eithe r enable o r disabl e the “Ch ange in FAS
Framing Alignment (COFA)” Interrupt, withi n the XRT86VL32 device. If
the user enables this interr upt, then the Rec eive T1 Framer block will
generate an interrupt when it detects a Change of Framing Alignment
Signal (e.g., t he Framing bits have appeared to move to a dif ferent
location within the incoming T1 data stream).
0 - Disables the “Change of Framing Ali gnm ent (COFA)” Interrupt .
1 - Enables the “Change of Fram ing Alignment (COFA)” In terrupt.
3OOF_ENB R/W 0Change in Out of Frame Defect Condition interrupt enable
This bit permits the user to ei ther enable o r disable the “Change in O ut
of Frame Defect Condi ti on” Interrupt, within the XRT86 VL32 device. If
the user enables this interr upt, then the Rec eive T1 Framer block will
generate an inte rrupt in res ponse to either one of t he fol lowing condi-
tions.
1. The inst a nt that the Recei ve T1 Framer bloc k declar es the Out of
Frame defect condition.
2. The instant that the Receive T1 Framer block clears the Out of
Frame defect condition.
0 – Disabl es the “Change in Out of Frame Defect Condit ion” Inte rrupt.
1 – Enables the “Change in Out of Frame Defect Condi tion” Int err upt.
2FMD_ENB R/W 0Frame Mimic Detecti on Interrupt E nable
This bit permits the user to either enable or di sable the “Frame Mimic
Detection” Interrupt , wi thi n the XRT8 6VL32 device. I f the user enabl es
this interrupt, then the Receive T1 Frame r bl ock will gener ate an inter-
rupt when it detects the presence of Frame mi m ic bit s (i.e., the payload
bit s have appear ed to mimic the framing bi t patt ern within th e incoming
T1 data stream).
0 - Disables the “Frame Mimic Detection” Interrupt.
1 - Enables the “Frame Mimic Detection” Interrupt.
XRT86VL32
97
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1SE_ENB R/W 0Synchronization Bit (CRC-6) Error Interrupt Enable
This bi t permits the user to eit her enable or dis able the “CRC-6 Error
Detection” Interrupt , wi thi n the XRT8 6VL32 device. I f the user enabl es
this interrupt, then the Receive T1 Frame r bl ock will gener ate an inter-
rupt when it detects a CRC-6 error within the incoming T1 multiframe.
0 - Disables the “CRC-6 Error Detection” Inter rupt.
1 - Enable s the “CRC-6 Err or Detection” Interrupt.
0FE_ENB R/W 0Framing Bit Err or Interrupt Enable
This bi t permits the user to eit her enable or dis able the “Frami ng Ali gn-
ment Bi t Err or Dete ction” Inte rrupt , withi n the XR T86VL3 2 dev ice. If the
user enables thi s in terrupt, then the Receive T1 Fram er block will gen-
erate an interrupt when it detects one or more Framing Align me nt Bi t
error within the incoming T1 dat a stream .
0 - Disables the “Framing Alignment Bit Error Detection” Interrupt.
1 - Enables the “Framing Ali gnment Bit Error Detecti on” Interr upt.
NOTE: Detecting Framing Alignment Bit Error doesn't not necessarily
indicate that synchronization has been lost.
TABLE 83: FRAMER INTERRUPT ENABLE REGISTER (FIER) HEX ADDRESS: 0XnB05
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
98
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 84: DATA LINK STATUS REGISTER 1 (DLSR1) HEX ADDRESS: 0XnB06
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7MSG TYPE RO 0HDLC1 Message Type Identifier
This READ ONLY bit i ndicates the type of dat a li nk message
received by Recei ve HDLC 1 Controll er. T wo types of data li nk m es-
sages are supported within the XRT86VL32 dev ice: Message Ori-
ented Si gnaling (MOS) or Bit-Oriented Signalling (BOS).
0 = Indicates Bit-Ori ented Signa ling (BOS) type data li nk messa ge is
received
1 = Indic ates Message Oriented Signal ing (MOS) type data link
mess age is rece ived
6TxSOT RUR/
WC 0Transmit HDLC1 Contr oll er Start of Transmission (TxSOT)
Interrupt Status
This Reset-Upon- Read bit indi cates whether or n ot the “ Tr ansmit
HDLC1 Controller Start of Tra nsm ission (TxSOT) “Int errupt has
occurred since the last read of this register. Transmit HDLC1 Con-
trol ler wil l decl are thi s inter rupt whe n it has st art ed to tr ansmit a da t a
li nk m essage. For sending large HDLC me ssages, start loading the
next availabl e buffer once this i nterrupt is detect ed.
0 = Transmi t HDLC1 Cont roller Start of Transmission (TxSOT) inter-
rupt has not occurred since t he last read of t his regist er
1 = Transmi t HDLC1 Cont roller Start of Tran sm ission interrupt
(TxSOT) has occurred since the last read of this r egister.
5RxSOT RUR/
WC 0Receive HDLC1 Controll er S tar t of Recept ion (RxSOT) Inter rupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC1 Controller Start of Reception (RxSOT) interrupt has
occurred since the last read of this register. Receive HDLC1 Con-
trol ler will declare t his interrupt when it has st arted to receive a data
link message.
0 = Receive HDLC1 Controller Start of Recepti on (RxSOT) interr upt
has n ot occurred si nce the last read of this register
1 = Receive HDLC1 Controller Start of Recepti on (RxSOT) interr upt
has occurred since the last read of this register
4TxEOT RUR/
WC 0Transmit HDLC1 Controller End of Transmission (TxEOT) Inter-
rupt Status
This Reset-Upon- Read bit indi cates whether or n ot the Transmi t
HDLC1 Controller End of Transm ission (TxEOT) Interrupt has
occurred since the last read of this register. Transmit HDLC1 Con-
trol ler will decl are this i nter rupt when it has comp leted it s tr ansm is-
sion of a da ta link message. For sendi ng large HDLC message s, it
is critical to load the nex t avai lable buffer bef ore this in terrupt
occurs.
0 = Transmi t HDLC1 Cont roller End of Transm ission (TxEOT) inter -
rupt has not occurred since t he last read of t his regist er
1 = Transmi t HDLC1 Cont roller End of Transm ission (TxEOT) inter -
rupt has occurred since t he last read of this register
XRT86VL32
99
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
3RxEOT RUR/
WC 0Receive HDLC1 Controlle r End of Reception (RxEOT) Interrupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC1 Cont roll er End of Rec eptio n (RxEOT) Inter rupt ha s oc curred
since the last read of thi s register. Receive HDLC1 Controller will
declare this interrupt once it has completely received a full data link
message, or once the buffer is full.
0 = Receive HDLC1 Cont rol ler End of Recept ion (RxEOT) interrupt
has n ot occurred si nce the last read of this register
1 = Receive HDLC1 Cont rol ler End of Recept ion (RxEOT) Int err upt
has occurred since the last read of this register
2FCS E r r or RUR/
WC 0FCS Error Inter rupt Status
This Reset-Upon- Read bit indi cates whether or not th e FC S Error
Interrupt has occurred since the last read of this register. Receive
HDLC1 Controll er will decl are thi s interrupt when it has detec ted the
FCS error in th e mos t recently recei ved dat a li nk m essage.
0 = FCS Error interrupt has not occurred since the last read of this
register
1 = FCS Error i nterrupt has occurred since the last read of this regis-
ter
1Rx ABORT RUR/
WC 0Receipt of Abort Sequence Interrupt Status
This Reset-Upon- Read bit indi cates whether or not the Re ceipt of
Abort Sequence int errupt has occurred since last r ead of this regis -
ter. Receive HDLC1 Controller will declar e thi s interr upt i f i t det ects
the Abor t Sequence (i .e. a stri ng of seve n (7) consec utive 1’ s) i n the
incoming data link channel.
0 = Receipt of Abort Sequence interrupt has no t occurred si nce last
read of this register
1 = Receipt of Abort Sequen ce interru pt has occurred si nce last
read of this register
0RxIDLE RUR/
WC 0Receipt of Idle Sequence Interrupt Status
This Reset-Upon- Read bit indi cates whether or not the Re ceipt of
Idle Se quence interrupt has occurred si nce the last read o f this reg-
ister. The Receive HDLC1 Controller will declare this interrupt if it
detects the flag sequence octet (0 x7E) in the incoming data link
channel. If RxIDL E "AND" RxEOT occ ur t ogether, then the entire
HDLC messa ge has been received.
0 = Receipt of Idle Sequence interrupt has not occ urred since last
read of this register
1 = Receipt of Idle Sequence interrupt has occur red since last read
of thi s register.
TABLE 84: DATA LINK STATUS REGISTER 1 (DLSR1) HEX ADDRESS: 0XnB06
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
100
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 85: DATA LINK INTERRUPT ENABLE REGISTER 1 (DLIER1) HEX ADDRESS: 0XnB07
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6TxSOT ENB R/W 0Transmit HDLC1 Co ntroller Start of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC1 Controll er S tart of
Tran sm ission (TxSOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC1 Controller will
generate an interr upt when it has started to transmit a data link mes-
sage.
0 = Disabl es the T ransmit HDL C1 Controlle r Start of Transm ission
(Tx S O T ) in te r ru p t.
1 = Enables the Transmit HDLC1 Controller Start of T ransmission
(Tx S O T ) in te r ru p t.
5RxSOT ENB R/W 0Receive HDLC1 Controll er St ar t of Reception ( RxSOT) Inter rupt
Enable
This bi t enables or disables the “Receive HDLC1 Contr oller Start of
Reception (RxSOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC1 Contr olle r will gen erate
an interrupt when it has started to receive a data link message.
0 = Disabl es the Receive HDLC1 Contr oller Start of Reception
(R xSOT) interru p t.
1 = Enables t he Receive HDLC1 Control ler Start of Reception
(R xSOT) interru p t.
4TxEOT ENB R/W 0Transmit HDLC1 Controller End of Transmission (TxEOT) Inter-
rupt Enabl e
This bi t enables or disables the “Transmit HDLC1 Controller End of
Tran sm ission (TxEOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC1 Controller will
generate an interrupt when it has fi nished transmitting a data link
message.
0 = Disabl es the T ransmit HDLC 1 Controlle r End of Transmission
(Tx E O T ) in te r ru p t.
1 = Enables the Transmi t HDLC1 Cont rol ler End of Transm ission
(Tx E O T ) in te r ru p t.
3RxEOT ENB R/W 0Receive HDLC1 Controller End of Reception (RxEOT) Interrupt
Enable
This bi t enables or disables the “Receive HDLC1 Contr oller End of
Reception (RxEOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC1 Contr olle r will gen erate
an interrupt when it has fi nished receiving a complete data li nk m es-
sage.
0 = Disabl es the Receive HDLC1 Contr oller End of Rece pti on
(R xEOT) interru p t.
1 = Enables t he Receive HDLC1 Controller End of Recept ion
(R xEOT) interru p t.
XRT86VL32
101
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
2FCS ERR ENB R/W 0FCS Err or In ter rupt Enable
This bi t enables or di sables the “Received FCS Erro r “Interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC1 Cont roller wi ll generate an interrupt when it has
detected the FCS error wit hin the inco ming data li nk message.
0 = Disabl es the “Receive FCS Error” interrupt.
1 = Enables t he “Receive FCS Error” interrupt.
1RxABORT ENB R/W 0Receipt of Abort Sequence Interrupt Enable
This bi t enables or di sables the “Receipt of Abor t Sequence “ Inter-
rupt within the XRT86VL32 device. Once this int err upt is enabled,
the Recei ve HDLC1 Controll er will gener ate an int errupt when it has
detected the Abort Sequence (i .e. a string of seven (7) consecutive
1’s) within the incoming data link channel.
0 = Disabl es the “Receipt o f Abort Sequence” interrupt.
1 = Enables the “R eceipt of Abor t Sequence” int errup t.
0RxIDLE ENB R/W 0Receipt of Idle Sequence Interrupt Enable
This bit enables or disables the “Receipt of Idle Seque nce“ Interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC1 Cont roller wi ll generate an interrupt when it has
detected the Idle Sequence Octet (i.e. 0x 7E) within the incoming
data link channel.
0 = Disabl es the “Receipt o f Idl e Sequence” int errupt.
1 = Enables the “R eceipt of I dle Sequence ” in terrupt.
TABLE 85: DATA LINK INTERRUPT ENABLE REGISTER 1 (DLIER1) HEX ADDRESS: 0XnB07
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
102
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 86: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XnB08
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxSB_FULL RUR/
WC 0Transmit Slip buffer Full Inter rupt Status
This Reset-Up on- Read bit indi cates whet her or not t he Tr ansmi t Sl ip
Buffer Full interrupt has occurred since the last read of this register.
The transmit Slip Buffer Full interrupt is declared when the t ransm it
sli p buffer is f il led. If the transmit slip buffer is ful l and a W RITE op er-
ation occurs, then a full frame of data will be deleted, and this inter-
rupt bit will be set to ‘1’.
0 = Indic ates that the Transmit Slip Buffer Ful l interrupt has not
occurred since the last read of this register.
1 = Ind ic ates t hat the T ransmi t Sli p Buf fer Ful l i nterr upt has o ccur red
since the last read of this register.
6TxSB_EMPT RUR/
WC 0T r ansmit Slip buffer Empty Interrupt Status
This Reset-Up on- Read bit indi cates whet her or not t he Tr ansmi t Sl ip
Buffer Empty interr upt has occurred since the l ast read of this regis-
ter. The transmit Slip Buffer Empty interrupt is declared when the
transmit slip buffer is empt ied. If the transmit slip buffer is emptied
and a READ operation occurs, then a full frame of data will be
repeated, and thi s interr upt bit will be set to ‘1 ’.
0 = Indic ates that the Transmit Slip Buffer Empty interrupt has not
occurred since the last read of this register.
1 = Indic ates that the Transmit Slip Buffer Empty interrupt has
occurred since the last read of this register.
5TxSB_SLIP RUR/
WC 0Transmit Slip Buffer Slip s Interrupt Status
This Reset-Up on- Read bit indi cates whet her or not t he Tr ansmi t Sl ip
Buf fer Sl ips i nterr upt has occu rred s ince t he last r ead of this reg ister.
The tr ansmit Sl ip Buf fer Sl ips inter rupt i s declar ed when the t ransmit
sli p buff er is either filled or emptied . This i nterr upt bit wi ll be set to ‘1’
in either one of these two conditi ons:
1. If the transmit slip buffer is emptied and a READ operation
occurs, then a full frame of data will be repeated, and this
interrupt bit will be set to ‘1’.
2. If the transmit sli p buffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit
will be set to ‘1’.
0 = Indic ates that the Transmit Slip Buffer Sl ips inter rupt has not
occurred since the last read of this register.
1 = Indic ates that the Transmit Slip Buffer Sl ips interrupt has
occurred since the last read of this register.
NOTE: Users still need to read the Transmit Slip Buffer Empty
Interrupt (bit 6 of this register) or the Transmit Slip Buffer
Full Interrupts (bit 7 of this register) to determine whether
transmit slip buff er empties or fills.
XRT86VL32
103
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
4SLC®96 LOCK RO 0SLC®96 is in SYNC
This READ ONLY bit f iel d indicates whether or n ot f rame synchroni-
zation is achieved when the XRT8 6VL32 is configured in SLC®96
framing mode.
0 = Indicates that f rame synchronization is not achieved in SLC®96
framing mode.
1 = Indic ates that fr am e synchronization is achieved in SLC®96
framing mode.
3Multifram e LOCK RO 0Multiframe is in SYNC
This READ ONLY bit f iel d indicat es whether or not the T 1 Recei ve
Framer Block is declaring T1 Multi frame LOCK status.
0 = Indic ates that the T1 Receive Framer is cur rently decl aring T1
multi frame LOSS OF LOCK status
0 = Indic ates that the T1 Receive Framer is cur rently decl aring T1
multi frame LOCK status
2RxSB_FULL RUR/
WC 0Receive Slip buffer Full I nterrupt Status
This Reset -Upon- Read bit indic ates whether or not the Receive Slip
Buffer Full interrupt has occurred since the last read of this register.
The Receive Slip Buffer Full interrupt is declared when the rec eive
slip buffer is filled. If the receive slip buffer is full and a WRITE oper-
ation occurs, then a full frame of data will be deleted, and this inter-
rupt bit will be set to ‘1’.
0 = Indic ates that the Rece ive Slip Buffer Full interrupt has not
occurred since the last read of this register.
1 = Indicates that the Receive Slip Buffer Ful l interrupt has occurred
since the last read of this register.
TABLE 86: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XnB08
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
104
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1RxSB_EMPT RUR/
WC 0Receive Slip buffer Empty Interrupt Status
This Reset -Upon- Read bit indic ates whether or not the Receive Slip
Buffer Empty interr upt has occurred since the l ast read of this regis-
ter. The Receive Slip Buffer Empty interrupt is decl ared when the
recei ve slip buff er i s empti ed. If the rec eive s lip b uf fer is empt ied and
a READ operation occurs, then a full frame of data will be re peated,
and this interrupt bit will be se t to ‘1’.
0 = Indic ates that the Rece ive Slip Buffer Empty interrupt has not
occurred since the last read of this register.
1 = Indic ates that the Rece ive Slip Buffer Empty interrupt has
occurred since the last read of this register.
0RxSB_SLIP RUR/
WC 0Receive Slip Buffer Slips Interrupt Status
This Reset -Upon- Read bit indic ates whether or not the Receive Slip
Buf fer Sl ips i nterr upt has occu rred s ince t he last r ead of this reg ister.
The Re ceive Sli p Buffer Sl ips int errupt i s declared when the receive
sli p buff er is either filled or emptied . This i nterr upt bit wi ll be set to ‘1’
in either one of these two conditi ons:
1. If the receive slip buffer is emptied and a READ operation
occurs, then a full frame of data will be repeated, and this
interrupt bit will be set to ‘1’.
2. If the receive slip buffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit
will be set to ‘1’.
0 = Indic ates that the Rece ive Slip Buffer Slip s interr upt has not
occurred since the last read of this register.
1 = Indic ates that the Rece ive Slip Buffer Slip s interr upt has
occurred since the last read of this register.
NOTE: Users still need to read the Receive Slip Buffer Empty
Interrupt (bit 1 of this r egister) or the Receive Slip Buffer Full
Interrupts (bit 2 of this register) to determine whether
transmit slip buff er empties or fills.
TABLE 86: SLIP BUFFER INTERRUPT STATUS REGISTER (SBISR) HEX ADDRESS: 0XnB08
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
105
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 87: SLIP BUFFER INTERRUPT ENABLE REGISTER (SBIER) HEX ADDRESS: 0XnB09
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7TxFULL_ENB R/W 0T r ansmit Slip Buffer Full Interrupt Enable
This bi t enables or di sables the Tr ansmit Slip Buffer Full interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
transmit Slip Buffer Ful l inter rupt is declared when t he tr ansm it sli p
buffer is filled. If the t ransmit slip buffer is full and a WRITE opera-
tio n occurs , then a f ull frame of dat a will be del eted, and the i nterr upt
status bit will be set to ‘1’.
0 - Di sab les the Transm it Sli p Buf fer Ful l i nterr upt when the Tr ansmi t
Slip B uffer fills
1 - Enables the Tr ansmit Sl ip Buf fer Full in terru pt when the T ransmi t
Slip B uffer fills.
6TxEMPT_ENB R/W 0Transmit Slip Buffer Empty Interrupt Enable
This bit enables or d isables the Tran sm it Slip Buffer Empty int errupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
transmit Slip Buffer Empty inter rupt is declared when the transmit
sli p buffer is emptied. If the transmit slip buf fer is emptied and a
READ operation occur s, t hen a ful l frame of dat a wil l be repeated,
and the interr upt st atus bit wil l be set t o ‘1’.
0 - Disables the T ransmi t Sl ip Buffer Empt y interr upt when the
Transmit Slip Buffer empties
1 - Enables t he T ra nsmi t Slip Buff er Empty interr upt when the T rans-
mit Slip Buffer empti es.
5TxSLIP_ENB R/W 0Transmit Slip Buffer Slips Interrupt Enable
This bi t enables or di sables the Transm it Slip Buffer Sli ps interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
transmit Slip Buffer Sl ips interrupt is declared when either the trans-
mit s lip b uf fer is fil led or empti ed. I f the transmi t sl ip buf f er is emptied
and a READ operation occurs, then a full frame of data will be
repeated, and the interrupt status bit will be set to ‘1’.
The interrupt status bit will be set to ‘1’ in either one of these two
conditions:
1. If the transmit slip buffer is emptied and a READ operation
occurs, then a full frame of data will be repeated, and this
interrupt bit will be set to ‘1’.
2. If the transmit sli p buffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit
will be set to ‘1’.
0 - Disables the T ransmi t Sl ip Buffer Slips int errupt when the Trans-
mit Slip Buffer empties or fills
1 - Enables the Transmit Sli p Buffer Slips inter rupt when the Trans-
mit Slip Buffer empties or fills.
4-3 Reserved - - Reserved
XRT86VL32
106
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2RxFULL_ENB R/W 0Receive Slip Buffer Full Interrupt Enable
This bi t enables or di sables the Recei ve Slip Buff er Full interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive Slip Buffer Full int errupt is dec lared when the receive slip
buffer is filled. If the Receive slip buffer is full and a WRITE opera-
tio n occurs , then a f ull frame of dat a will be del eted, and the i nterr upt
status bit will be set to ‘1’.
0 - Disables th e Receive Sli p Buff er Full inte rrupt when the T r ansmit
Slip B uffer fills
1 - Enables the Receive Sli p Buffer Full interrupt when the Transm it
Slip B uffer fills.
1RxEMPT_ENB R/W 0Receive Slip buffer Empty Interrupt Enable
This bi t enabl es or di sables the Recei ves Sli p Buff er Empty i nterr upt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive Slip Buffer Empty interrupt is declared when the Receive
sli p buffer is emptied. If the Receive sli p buffer is emptied and a
READ operation occurs, then a full frame of data will be repeated,
and the interr upt st atus bit wil l be set t o ‘1’.
0 - Disables the Receive Slip Buffer Empty interrupt when the Trans-
mit Slip Buffer empties
1 - Enables the Receiv e Sli p Buffer Empty interrupt when the Trans -
mit Slip Buffer empti es.
0RxSLIP_ENB R/W 0Receive Slip buffer Slips Interrupt Enable
This bi t enables or di sables the Recei ve Slip Buff er Slips int errupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive Slip Buffer Slip s interr upt is declared when either the
Receive slip buffer is f illed or emptied. If the Receiv e sli p buffer is
emptied and a READ operati on occur s, then a full f rame of data will
be repeated, and the interrupt status bit will be set to ‘1’.
The interrupt status bit will be set to ‘1’ in either one of these two
conditions:
1. If the Receive slip buffer is emptied and a READ operation
occurs, then a full frame of data will be repeated, and this
interrupt bit will be set to ‘1’.
2. If the Receive slip bu ffer is full and a WRITE operation occurs,
then a full frame of data will be deleted, and this interrupt bit
will be set to ‘1’.
0 - Disables the Receive Slip Buf fer Slip s int errupt when the Tran s-
mit Slip Buffer empties or fills
1 - Enables the Recei ve Slip Buf fer Slip s interru pt when t he Trans-
mit Slip Buffer empties or fills.
TABLE 87: SLIP BUFFER INTERRUPT ENABLE REGISTER (SBIER) HEX ADDRESS: 0XnB09
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
107
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 88: RECEIVE LOOPBACK CODE INTERRUPT AND STATUS REGISTER (RLCISR) HEX ADDRESS: 0 XnB0A
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 - - - Reserved (For E1 mode only)
3RXASTAT RO 0Rec eive Loopback Activation Code State
This READ ONLY bit ind icates whether o r not t he Receive T1 Frame r Block is
curr ently detect ing the Rec eive Loopb ack Act ivat ion Code, as spec ified i n the
Receive Loopback Activati on Code Register (RLACR - address 0xn126) if
Receive Loopback Activati on Code Detection is enabl ed.
0 = Ind icate s t hat the Receive T1 Frame r Block is NOT cur rentl y detec ting t he
Receive Loopback Activati on Code.
1 = I ndicates that the Receive T1 Framer Block is currently detecting the
Receive Loopback Activati on Code.
2RXDSTAT RO 0Rec eive Loopback Deac ti vation Code State
This READ ONLY bit ind icates whether o r not t he Receive T1 Frame r Block is
currently detecting t he Receive Loopb ack Deactivation Code, as specified i n
the Receive Loopback Deactivation Code Register (RLDCR - address
0xn127) if Recei ve Loopback Deactivation Code Dete cti on is enabled.
0 = Ind icate s t hat the Receive T1 Frame r Block is NOT cur rentl y detec ting t he
Receive Loopback Deactivation Code.
1 = I ndicates that the Receive T1 Framer Block is currently detecting the
Receive Loopback Deactivation Code.
1RXAINT RUR/
WC 0Change in Recei ve Loopback Activation Code inte rrupt Status
This Reset-Upon- Read bit field indicat es whether or not t he “Change in
Recei ve Loo pback Act ivati on Cod e” interr upt has occu rred si nce the las t read
of thi s register.
If this interru pt is enabled, then the Rece ive T1 Framer block will generate an
interrupt in re sponse to either one of the foll owing cond it ions.
1. Whenever the Receive T1 Framer block detects the Receive Loopback
Acti vation Code.
2. Whenever the Receive T1 Framer block no l onger detects the Receive
Loopback Activation Code.
0 = Indic ates that the “Change in Recei ve Loopback Activatio n Code” inter-
rupt has not occurred since the last read of this regi ster
1 = Indic ates that the “Change in Recei ve Loopback Activatio n Code” inter-
rupt has occurred since the last read of thi s register
0RXDINT RUR/
WC 0Change in Receive Loopback Deactivati on Code interrupt Sta tus
This Reset-Upon- Read bit field indicat es whether or not t he “Change in
Receive Loopb ack Deactivation Code” interrupt has occurred since the last
read of this reg ist er.
If this interru pt is enabled, then the Rece ive T1 Framer block will generate an
interrupt in re sponse to either one of the foll owing cond it ions.
1. Whenever the Receive T1 Framer block detects the Receive Loopback
Deacti vation Code.
2. Whenever the Receive T1 Framer block no l onger detects the Receive
Loopback Deactivation Code.
0 = Indicates that the “Change in Receive Loopback Deactivation Code” int er-
rupt has not occurred since the last read of this regi ster
1 = Indicates that the “Change in Receive Loopback Deactivation Code” int er-
rupt has occurred since the last read of thi s register
XRT86VL32
108
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 89: RECEIVE LOOPBACK CODE INTERRUPT ENABLE REGISTER (RLCIER) HEX ADDRESS: 0XnB0B
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-2 Reserved - - Reserved
1RXAENB R/W 0Receive Loopback Activation Code Interrupt Enable
This bit enabl es or di sables the “Change in Receiv e Loopback Acti-
vati on Code” inter rupt within th e T1 Receiv e Framer.
If t his interrupt is enabled, then the Recei ve T1 Framer block wil l
generate an interrupt in r esponse to either one of the following
conditions.
1. Whenever the Receive T1 Framer block detects the Receive
Loopback Activation Code.
2. Whenever the Receive T1 Framer block no longer detects
the Receive Loopback Activation Code.
0 - Disables the “Cha nge in Rec eive Loopba ck Activation Code”
int errupt within the T1 Receive Framer.
1 - Enables the “Change i n Receive Loopback Activation Code”
int errupt within the T1 Receive Framer.
0RXDENB R/W 0Receiv e Loopback Deactivation Code Interrupt Enable
This bit enabl es or di sables the “Change in Receiv e Loopback
Deactivation Code” inter rupt within the T1 Receive Framer.
If t his interrupt is enabled, then the Recei ve T1 Framer block wil l
generate an interrupt in r esponse to either one of the following
conditions.
1. Whenever the Receive T1 Framer block detects the Receive
Loopback Deactivation Code.
2. Whenever the Receive T1 Framer block no longer detects
the Receive Loopback Deactivation Code.
0 - Disabl es the “Change in Receive Loopback Deactivation Code”
int errupt within the T1 Receive Framer.
1 - Enables the “Change i n Receive Loopback Deactivation Code”
int errupt within the T1 Receive Framer.
XRT86VL32
109
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 90: EXCESSIVE ZERO STATUS REGISTER (EXZ SR) HEX ADDRESS: 0XnB0E
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-1 Reserved - - Reserved
0EXZ_STATUS RUR/
WC 0Change in Excessi ve Zero Condition I nter rupt Status
This Reset-Upon-Read bit field indicates whether or not the “Change in
Excessive Zero Condition” int errupt within the T1 Receive Fr amer Block
has occurred since the last re ad of this register.
If this in terrupt i s enabled, then the Receive T1 Framer bl ock will gener-
ate an int err upt in response to eithe r one of t he fol lowing condi tions.
1. Whenever the Receive T1 Framer block detects the Excessive
Zero Condition.
2. Whenever the Receive T1 Framer bl ock clears the Excessive Zero
Condition
0 = Indicates the “Change in Excessive Zero Condition” interrupt has
NOT occurred since the last read of this register
1 = Indicates the “Change in Excessive Zero Condition” interrupt has
occurred since the last read of this register
TABLE 91: EXCESSIVE ZERO ENABLE REGISTER (EXZER) HEX ADDRESS: 0XnB0F
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-1 - - - Reserved
0EXZ_ENB R/W 0Change in Excessive Zero Condition Interrupt Enable
This bi t enables or di sables the “Change in Excessive Zero Condi-
tio n” i nterrupt with in t he T1 Receive Framer.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt in res ponse to either one of th e fol lowing
conditions.
1. Whenever the Receive T1 Framer block detects the
Excessive Zero Condition.
2. Whenever the Receive T1 Framer block clears the Excessive
Zero Condition
0 - Disables the “Chan ge in Excessive Zero Condition” inter rupt
within the Receive T1 Framer Block
1 - Enables the “Change in Excessive Zero Condition” i nterrupt
within the Receive T1 Framer Block
XRT86VL32
110
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 92: SS7 STATUS REGISTER FOR LAPD1 (SS7SR1) HEX ADDRESS: 0XnB10
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_1_STATUS RUR/
WC 0SS7 Interrupt Status for LAPD Controller 1
This Reset-Upon- Read bit field indicates whether or not th e “SS7”
interrupt has occurred since the last read of this register.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 = Indicates that the “SS7” interrupt has not o ccurred since the last
read of this register
1 = I ndicates that the “SS7” interrupt has occurred si nce the last
read of this register
TABLE 93: SS7 ENABLE REGISTER FOR LAPD1 (SS7ER1) HEX ADDRESS: 0 XnB11
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_1_ENB R/W 0SS7 Interrupt Enable for LAPD Controller 1
This bi t enables or disables the “SS7” int errupt within the LAPD
Controller 1.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 - Disables the “SS7” interrupt withi n the LAPD Controller 1.
1 - Enables the “SS7 ” in ter rupt within th e LAPD Contr oller 1.
XRT86VL32
111
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 94: RXLOS/CRC INTERRUPT STATUS REGISTER (RLCISR) HEX ADDRESS: 0XNB12
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 - - - Reserved
3RxLOSINT RUR/
WC 0Change in Receive LOS condition Interrupt Status
This bit i ndicates whether or not the “Change in Receive LOS condi-
tion” interrupt has occurred since the last read of this r egister.
If t his interrupt is enable d, then the Receiv e T1 Framer block wil l
generate an inte rrupt in res ponse to either one of th e fol lowing
conditions.
1. Whenever the Receive T1 Framer block declares the Rece ive
LOS cond it ion.
2. Whenever the Receive T1 Framer block clears the Receive
LOS cond it ion.
0 = Indic ates that the “Change in Receive LOS Condition” int errupt
has n ot occurred si nce the last read of this register.
1 = Indic ates that the “Change in Receive LOS Condition” int errupt
has occurred since the last read of this register.
2-0 Reserved - -
TABLE 95: RXLOS/CRC INTERRUPT ENABLE REGISTER (RLCIER) HEX ADDRESS: 0XNB13
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
3RxLOS_ENB R/W 0Change in Receive LOS Condition Interrupt Enable
This bi t enables the “ Change in Receive LOS Condition” int errupt.
0 = Enables “Change in Recei ve LOS Condition” Int errupt.
1 = Disabl es “Change in Receive L OS Cond it ion” Inte rrupt.
2-0 - - - Reserved
XRT86VL32
112
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 96: DATA LINK STATUS REGISTER 2 (DLSR2) HEX ADDRESS: 0XnB16
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7MSG TYPE RO 0HDLC2 Message Type Identifier
This READ ONLY bit i ndicates the type of dat a li nk message
received by Recei ve HDLC 2 Controll er. T wo types of data li nk m es-
sages are supported within the XRT86VL32 dev ice: Message Ori-
ented Si gnaling (MOS) or Bit-Oriented Signalling (BOS).
0 = Indicates Bit-Ori ented Signa ling (BOS) type data li nk messa ge is
received
1 = Indic ates Message Oriented Signal ing (MOS) type data link
mess age is rece ived
6TxSOT RUR/
WC 0Transmit HDLC2 Contr oll er Start of Transmission (TxSOT)
Interrupt Status
This Reset-Upon- Read bit indi cates whether or n ot the “ Tr ansmit
HDLC2 Controller Start of Tra nsm ission (TxSOT) “Int errupt has
occurred since the last read of this register. Transmit HDLC2 Con-
trol ler wil l decl are thi s inter rupt whe n it has st art ed to tr ansmit a da t a
li nk me ssage. For sending large HDLC messages, start loading the
next availabl e buffer once this i nterrupt is detect ed.
0 = Transmi t HDLC2 Cont roller Start of Transmission (TxSOT) inter-
rupt has not occurred since t he last read of t his regist er
1 = Transmi t HDLC2 Cont roller Start of Tran sm ission interrupt
(TxSOT) has occurred since the last read of this r egister.
5RxSOT RUR/
WC 0Receive HDLC2 Controll er S tar t of Recept ion (RxSOT) Inter rupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC2 Controller Start of Reception (RxSOT) interrupt has
occurred since the last read of this register. Receive HDLC2 Con-
trol ler will declare t his interrupt when it has st arted to receive a data
link message.
0 = Receive HDLC2 Controller Start of Recepti on (RxSOT) interr upt
has n ot occurred si nce the last read of this register
1 = Receive HDLC2 Controller Start of Recepti on (RxSOT) interr upt
has occurred since the last read of this register
4TxEOT RUR/
WC 0Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Status
This Reset-Upon- Read bit indi cates whether or n ot the Transmi t
HDLC2 Controller End of Transm ission (TxEOT) Interrupt has
occurred since the last read of this register. Transmit HDLC2 Con-
trol ler will decl are this i nter rupt when it has comp leted it s tr ansm is-
sion of a da ta link message. For sendi ng large HDLC message s, it
is critical to load the nex t avai lable buffer bef ore this in terrupt
occurs.
0 = Transmi t HDLC2 Cont roller End of Transm ission (TxEOT) inter -
rupt has not occurred since t he last read of t his regist er
1 = Transmi t HDLC2 Cont roller End of Transm ission (TxEOT) inter -
rupt has occurred since t he last read of this register
XRT86VL32
113
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
3RxEOT RUR/
WC 0Receive HDLC2 Controlle r End of Reception (RxEOT) Interrupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC2 Cont roll er End of Rec eptio n (RxEOT) Inter rupt ha s oc curred
since the last read of thi s register. Receive HDLC2 Controller will
declare this interrupt once it has completely received a full data link
message, or once the buffer is full.
0 = Receive HDLC2 Cont rol ler End of Recept ion (RxEOT) interrupt
has n ot occurred si nce the last read of this register
1 = Receive HDLC2 Cont rol ler End of Recept ion (RxEOT) Int err upt
has occurred since the last read of this register
2FCS E r r or RUR/
WC 0FCS Error Inter rupt Status
This Reset-Upon- Read bit indi cates whether or not th e FC S Error
Interrupt has occurred since the last read of this register. Receive
HDLC2 Controll er will decl are thi s interrupt when it has detec ted the
FCS error in th e mos t recently recei ved dat a li nk m essage.
0 = FCS Error interrupt has not occurred since the last read of this
register
1 = FCS Error i nterrupt has occurred since the last read of this regis-
ter
1Rx ABORT RUR/
WC 0Receipt of Abort Sequence Interrupt Status
This Reset-Upon- Read bit indi cates whether or not the Re ceipt of
Abort Sequence int errupt has occurred since last r ead of this regis -
ter. Receive HDLC2 Controller will declar e thi s interr upt i f i t det ects
the Abor t Sequence (i .e. a stri ng of seve n (7) consec utive 1’ s) i n the
incoming data link channel.
0 = Receipt of Abort Sequence interrupt has no t occurred si nce last
read of this register
1 = Receipt of Abort Sequen ce interru pt has occurred si nce last
read of this register
0RxIDLE RUR/
WC 0Receipt of Idle Sequence Interrupt Status
This Reset-Upon- Read bit indi cates whether or not the Re ceipt of
Idle Se quence interrupt has occurred si nce the last read o f this reg-
ister. The Receive HDLC2 Controller will declare this interrupt if it
detects the flag sequence octet (0 x7E) in the incoming data link
channel. If RxIDLE "AND" RxEOT occur together, then the entire
HDLC messa ge has been received.
0 = Receipt of Idle Sequence interrupt has not occ urred since last
read of this register
1 = Receipt of Idle Sequence interrupt has occur red since last read
of thi s register.
TABLE 96: DATA LINK STATUS REGISTER 2 (DLSR2) HEX ADDRESS: 0XnB16
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
114
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 97: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2) HEX ADDRESS: 0XnB17
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6TxSOT ENB R/W 0Transmit HDLC2 Co ntroller Start of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC2 Controll er S tart of
Tran sm ission (TxSOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC2 Controller will
generate an interr upt when it has started to transmit a data link mes-
sage.
0 = Disabl es the T ransmit HDL C2 Controlle r Start of Transm ission
(Tx S O T ) in te r ru p t.
1 = Enables the Transmit HDLC2 Controller Start of T ransmission
(Tx S O T ) in te r ru p t.
5RxSOT ENB R/W 0Receive HDLC2 Controll er St ar t of Reception ( RxSOT) Inter rupt
Enable
This bi t enables or disables the “Receive HDLC2 Contr oller Start of
Reception (RxSOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC2 Contr olle r will gen erate
an interrupt when it has started to receive a data link message.
0 = Disabl es the Receive HDLC2 Contr oller Start of Reception
(R xSOT) interru p t.
1 = Enables t he Receive HDLC2 Control ler Start of Reception
(R xSOT) interru p t.
4TxEOT ENB R/W 0Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Enabl e
This bi t enables or disables the “Transmit HDLC2 Controller End of
Tran sm ission (TxEOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC2 Controller will
generate an interrupt when it has fi nished transmitting a data link
message.
0 = Disabl es the T ransmit HDLC 2 Controlle r End of Transmission
(Tx E O T ) in te r ru p t.
1 = Enables the Transmi t HDLC2 Cont rol ler End of Transm ission
(Tx E O T ) in te r ru p t.
3RxEOT ENB R/W 0Receive HDLC2 Controller End of Reception (RxEOT) Interrupt
Enable
This bi t enables or disables the “Receive HDLC2 Contr oller End of
Reception (RxEOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC2 Contr olle r will gen erate
an interrupt when it has fi nished receiving a complete data li nk m es-
sage.
0 = Disabl es the Receive HDLC2 Contr oller End of Rece pti on
(R xEOT) interru p t.
1 = Enables t he Receive HDLC2 Controller End of Recept ion
(R xEOT) interru p t.
XRT86VL32
115
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
2FCS ERR ENB R/W 0FCS Err or In ter rupt Enable
This bi t enables or di sables the “Received FCS Erro r “Interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC2 Cont roller wi ll generate an interrupt when it has
detected the FCS error wit hin the inco ming data li nk message.
0 = Disabl es the “Receive FCS Error” interrupt.
1 = Enables t he “Receive FCS Error” interrupt.
1RxABORT ENB R/W 0Receipt of Abort Sequence Interrupt Enable
This bi t enables or di sables the “Receipt of Abor t Sequence “I nter-
rupt within the XRT86VL32 device. Once this int err upt is enabled,
the Recei ve HDLC2 Controll er will gener ate an int errupt when it has
detected the Abort Sequence (i .e. a string of seven (7) consecutive
1’s) within the incoming data link channel.
0 = Disabl es the “Receipt o f Abort Sequence” interrupt.
1 = Enables the “R eceipt of Abor t Sequence” int errup t.
0RxIDLE ENB R/W 0Receipt of Idle Sequence Interrupt Enable
This bi t enables or di sables the “Receipt of I dle Sequence“Interr upt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC2 Cont roller wi ll generate an interrupt when it has
detected the Idle Sequence Octet (i.e. 0x 7E) within the incoming
data link channel.
0 = Disabl es the “Receipt o f Idl e Sequence” int errupt.
1 = Enables the “R eceipt of I dle Sequence ” in terrupt.
TABLE 97: DATA LINK INTERRUPT ENABLE REGISTER 2 (DLIER2) HEX ADDRESS: 0XnB17
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
116
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 98: SS7 STATUS REGISTER FOR LAPD2 (SS7SR2) HEX ADDRESS: 0XnB18
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_2_STATUS RUR/
WC 0SS7 Interrupt Status for LAPD Controller 2
This Reset-Upon- Read bit field indicates whether or not th e “SS7”
interrupt has occurred since the last read of this register.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 = Indicates that the “SS7” interrupt has not o ccurred since the last
read of this register
1 = I ndicates that the “SS7” interrupt has occurred si nce the last
read of this register
TABLE 99: SS7 ENABLE REGISTER FOR LAPD2 (SS7ER2) HEX ADDRESS: 0XnB19
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_2_ENB R/W 0SS7 Interrupt Enable for LAPD Controller 2
This bi t enables or disables the “SS7” int errupt within the LAPD
Controller 2.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 - Disables the “SS7” interrupt withi n the LAPD Controller 2.
1 - Enables the “SS7 ” in ter rupt within th e LAPD Contr oller 2.
XRT86VL32
117
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 100: DATA LINK STATUS REGISTER 3 (DLSR3) HEX ADDRESS: 0XNB26
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7MSG TYPE RUR/
WC 0HDLC3 Message Type Identifier
This READ ONLY bit i ndicates the type of dat a li nk message re ceived
by Receive HDLC 3 Controll er. T w o types of data link messages are
supported with in t he XRT86VL32 device: Message Orient ed Signaling
(MOS) or Bi t-Orient ed Signalling (BOS).
0 = Indic ates Bit-Or iented Signaling (BOS) type data link m essage is
received
1 = Indic ates Message Oriented Signal ing (MOS) type data link mes-
sage is received
6TxSOT RUR/
WC 0Transmit HDLC3 Controller Start of Transmission (TxSOT) Inter-
rupt Status
This Reset-Upon- Read bit indi cates whether or not the “Transmit
HDLC3 Controller Start of Tr ansmission (TxSOT) “Interrupt has
occur red sinc e the last read of th is regi ster . T ransm it HDLC3 Contr oller
will decl are thi s inter rupt when it has start ed to trans mit a dat a li nk mes-
sage. For sending lar ge HDLC me ssages, start load ing the next avai l-
able buff er once this interrupt is detected.
0 = T ra nsmit HDLC3 Con trol ler Star t of T ransm iss ion (TxSOT) inte rrupt
has n ot occurred si nce the last read of this register
1 = T ra nsmit HDLC3 Con trol ler Star t of T ransm iss ion int errup t (TxSOT)
has occurred since the last read of this register.
5RxSOT RUR/
WC 0Receive HDLC3 Controlle r Start of Reception (RxSOT) Inte rrupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC3 Controller Start of Reception (RxSOT) interrupt has occu rred
since the last read of thi s register. Receive HDLC3 Controller will
declare this interrupt when it has started to receive a da ta link mes-
sage.
0 = Receive HDLC3 Cont rol ler Start of Reception (RxSOT) int errupt
has n ot occurred si nce the last read of this register
1 = Receive HDLC3 Cont rol ler Start of Reception (RxSOT) int errupt
has occurred since the last read of this register
4TxEOT RUR/
WC 0T ransmi t HDLC3 Control ler End of T ransmission (TxEOT) Int errupt
Status
This Reset-Upon- Read bit indi cates whether or n ot the Transmi t
HDLC3 Contr oll er End of T rans miss ion (T xEOT) Int errupt has occ urred
since the last read of this register. Transmit HDLC3 Controller wil l
declare this interrupt when it has com pleted it s transm ission of a dat a
li nk me ssage. For sending large HDLC messages, it is cri ti cal to load
the next avail able buffer before this interrupt occurs.
0 = Tra nsm it HDLC3 Controll er End of Transmission (TxEOT) inte rrupt
has n ot occurred si nce the last read of this register
1 = Tra nsm it HDLC3 Controll er End of Transmission (TxEOT) inte rrupt
has occurred since the last read of this register
XRT86VL32
118
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3RxEOT RUR/
WC 0Receive HDLC3 Controlle r End of Reception (RxEOT) Interrupt
Status
This Reset-Upon- Read bit indi cates whether or not the Re ceive
HDLC3 Controller End of Recept ion (RxEOT) Interrupt has occurred
since the last read of thi s register. Receive HDLC3 Controller will
declare this interrupt once it has completely received a full data link
message, or once the buffer is full.
0 = Recei ve HDLC3 Cont roller End of Rece pti on (RxEOT) inte rrupt has
not occurred since the last read of this register
1 = Rece iv e HDLC3 Cont roll er End o f Recept ion ( RxEOT) Inter rupt has
occurred since the last read of this register
2FCS E r r or RUR/
WC 0FCS Error Inter rupt Status
This Reset -Upon-Re ad bit indicat es whether or not the FCS Error Inter-
rupt has occurred since the last read of this register. Receive HDLC3
Controller wil l declare this interrupt when it has detected the FCS error
in the most recently recei ved dat a li nk m essage.
0 = FCS Error interrupt has not occurred since the last read of this reg-
ister
1 = FCS Error interrupt has occurred since the last read of this regist er
1Rx ABORT RUR/
WC 0Receipt of Abort Sequence Interrupt Status
This Reset- Upon- Read bit indi cates whether or not the Rece ipt of Abort
Sequence interrupt has occurred since last r ead of this register.
Receive HDLC3 Cont roller will declare this interrupt if it detects the
Abort Sequence (i.e. a string of seven (7) consecutive 1’s) in the
incoming data link channel.
0 = Receipt of Abort Sequen ce interru pt has not occurred since la st
read of this register
1 = Recei pt of Abor t Sequence inter rup t has occur red si nce last read of
this register
0RxIDLE RUR/
WC 0Receipt of Idle Sequence Interrupt Status
This Reset-Upon- Read bit indi cates whether or not the Re ceipt of Idle
Sequence interrupt has occurred si nce the last read of this register.
The Recei ve HDL C3 Control ler wil l decl are this i nter rupt i f it detect s the
flag s equence octet (0x7E) in th e incoming data link channel. If RxI-
DLE "AND" RxE OT occur toge ther, then the en tire HDLC mess age has
been received.
0 = Receipt of Idle Seq uence in ter rupt has not occurr ed since last read
of thi s register
1 = Receipt of Idle Sequence interrupt has occur red since last read of
this register.
TABLE 100: DATA LINK STATUS REGISTER 3 (DLSR3) HEX ADDRESS: 0XNB26
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
119
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 101: DATA LINK INTERRUPT ENABLE REGISTER 3 (DLIER3) HEX ADDRESS: 0XnB27
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved - - Reserved
6TxSOT ENB R/W 0Transmit HDLC3 Co ntroller S ta rt of Transmission (TxSOT)
Interrupt Enable
This bit enables or disables the “Transmit HDLC3 Controll er Start of
Tran sm ission (TxSOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC3 Controller will
generate an interr upt when it has started to transmit a data link mes-
sage.
0 = Disabl es the T ransmit HDL C3 Controlle r Start of Transm ission
(Tx S O T ) in te r ru p t.
1 = Enables the Transmit HDLC3 Controller Start of T ransmission
(Tx S O T ) in te r ru p t.
5RxSOT ENB R/W 0Receive HDLC3 Controll er St ar t of Reception ( RxSOT) Inter rupt
Enable
This bi t enables or disables the “Receive HDLC3 Controller Start of
Reception (RxSOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC3 Contr olle r will gen erate
an interrupt when it has started to receive a data link message.
0 = Disabl es the Receive HDLC3 Contr oller Start of Reception
(RxSO T) i nterrupt.
1 = Enables t he Receive HDLC3 Control ler Start of Reception
(RxSO T) i nterrupt.
4TxEOT ENB R/W 0Transmit HDLC3 Controller End of Transmission (TxEOT) Inter-
rupt Enabl e
This bi t enables or disables the “Transmit HDLC3 Controller End of
Tran sm ission (TxEOT) “Inte rr upt within the XRT86VL32 device.
Once this i nterrupt is enabled, the Transmit HDLC3 Controller will
generate an interrupt when it has fi nished transmitting a data link
message.
0 = Disabl es the T ransmit HDLC 3 Controlle r End of Transmission
(Tx E O T ) in te r ru p t.
1 = Enables the Transmi t HDLC3 Cont rol ler End of Transm ission
(Tx E O T ) in te r ru p t.
3RxEOT ENB R/W 0Receive HDLC3 Controller End of Reception (RxEOT) Interrupt
Enable
This bi t enables or disables the “Receive HDLC3 Controller End of
Reception (RxEOT) “Interrupt within the XRT86VL32 device. Once
thi s int errupt is enable d, th e Recei ve HDLC3 Contr olle r will gen erate
an interrupt when it has fi nished receiving a complete data li nk m es-
sage.
0 = Disabl es the Receive HDLC3 Contr oller End of Rece pti on
(RxEO T) i nterrupt.
1 = Enables t he Receive HDLC3 Controller End of Recept ion
(RxEO T) i nterrupt.
XRT86VL32
120
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2FCS ERR ENB R/W 0FCS Err or In ter rupt Enable
This bi t enables or di sables the “Received FCS Erro r “Interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC3 Cont roller wi ll generate an interrupt when it has
detected the FCS error wit hin the inco ming data li nk message.
0 = Disabl es the “Receive FCS Error” interrupt.
1 = Enables t he “Receive FCS Error” interrupt.
1RxABORT ENB R/W 0Receipt of Abort Sequence Interrupt Enable
This bi t enables or di sables the “Receipt of Abor t Sequence “ Inter-
rupt within the XRT86VL32 device. Once this int err upt is enabled,
the Recei ve HDLC3 Controll er will gener ate an int errupt when it has
detected the Abort Sequence (i .e. a string of seven (7) consecutiv e
1’s) within the incoming data link channel.
0 = Disabl es the “Receipt o f Abort Sequence” interrupt.
1 = Enables the “R eceipt of Abor t Sequence” int errup t.
0RxIDLE ENB R/W 0Receipt of Idle Sequence Interrupt Enable
This bit enables or disables the “Receipt of Idle Seque nce“ Interrupt
with in t he XRT86VL32 device. Once th is interrupt is enable d, th e
Receive HDLC3 Cont roller wi ll generate an interrupt when it has
detected the Idle Sequence Octet (i.e. 0x 7E) within the incoming
data link channel.
0 = Disabl es the “Receipt o f Idl e Sequence” int errupt.
1 = Enables the “R eceipt of I dle Sequence ” in terrupt.
TABLE 101: DATA LINK INTERRUPT ENABLE REGISTER 3 (DLIER3) HEX ADDRESS: 0XnB27
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
121
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 102: SS7 STATUS REGISTER FOR LAPD3 (SS7SR3) HEX ADDRESS: 0XnB28
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_3_STATUS RUR/
WC 0SS7 Interrupt Status for LAPD Controller 3
This Reset-Upon- Read bit field indicates whether or not th e “SS7”
interrupt has occurred since the last read of this register.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 = Indicates that the “SS7” int errupt has no t occur red since the last
read of this register
1 = I ndicates that the “SS7” interrupt has occurred si nce the last
read of this register
TABLE 103: SS7 ENABLE REGISTER FOR LAPD3 (SS7ER3) HEX ADDRESS: 0XNB29
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0SS7_3_ENB R/W 0SS7 Interrupt Enable for LAPD Controller 3
This bi t enables or disables the “SS7” int errupt within the LAPD
Controller 3.
If t his interrupt is enable d, then the Receiv e T1 Framer block will
generate an inte rrupt when the Recei ved LAPD message is more
than 276 Bytes in leng th.
0 - Disables the “SS7” interrupt withi n the LAPD Controller 3.
1 - Enables the “SS7 ” in ter rupt within th e LAPD Contr oller 3.
XRT86VL32
122
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 104: CUSTOMER INSTALLATION ALARM STATUS REGISTER (CIASR) HEX ADDRESS: 0XnB40
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
[7:6] Reserved - - Reserved
5RxAIS-CI_state RO 0Receive Alarm In dication Signa l- Customer Installation (AIS-CI) State
This READ ONLY bit fiel d indicat es whether or not the Receive T1 Fra me r is
currently detecting the Alarm Indication Signal-Customer Installation (AIS-
CI) condition.
Alarm Indication Signal-Customer Installation (AIS-CI) is intended for use in
a network to differenti ate between an is sue within the networ k or th e Cus-
tom e r In s tal la ti on (C I ).
AIS-CI is an all ones signal with an embedded signature of 01111100
11111111 (right-to left) which recurs at 386 bit intervals in-the DS-1 sig nal.
0 = I ndicates the Receive T1 Framer is currently NOT detecting the AI S-CI
condition
1 = I ndicates the Receive T1 Framer is currently detecting the AIS-CI condi-
tion
NOTE: This bit only works if AIS-CI detection is enabled (Register 0xn11C)
4RxRAI-CI_state RO 0Rx RAI-CI State
This READ ONLY bit fiel d indicat es whether or not the Receive T1 Fra me r is
currentl y declaring t he Rem ote Al arm Indicat ion - Cus tomer Installation
(RAI-CI) condi tion. (This is for T1 ESF framing mode only)
Remote Alarm Indication - Customer Installation (RAI-CI) is inten ded for use
in a network to differentiate between an issue with in t he network or the Cus-
tom e r In s tal la ti on (C I ).
RAI-CI is a r epetiti ve p attern wi th a peri od of 1. 08 sec onds. I t is compr ised of
0.99 seconds of RAI message (00000000 11111111 Right-to-left) and a 90
ms of RAI-CI signature (00111110 11111111 Right to left) to form a RAI-CI
signal.
0 = I ndicates the Receive T1 Framer is currently NOT detecting the RAI-CI
condition
1 = I ndicates the Receive T1 Framer is currently detecting the RAI-CI condi-
tion
NOTE: This bit only works if RAI-CI detection is enabled (Register 0xn11C)
[3:2] Reserved - - Reserved
XRT86VL32
123
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
1RxAIS-CI RUR/
WC 0Change in Recei ve AIS-CI Condition I nter rupt Status
This Reset-Upon- Read bit field i ndicates whether or not the “Change in AIS-
CI Condition” int errupt within the T1 Receiv e Framer Block has occurred
since the last read of this reg ister.
If t his interrupt is enabled, then the Recei ve T1 Framer block wil l generate
an interrupt in r esponse to either one of the fo ll owing conditions.
1. When ever the Receive T1 Framer block detects the AI S-CI Co ndition.
2. Whenever the Receive T1 Framer block clears th e AIS-CI Condition
0 = Indic ates the “Change i n AIS- CI Condi tion” in ter rupt has NOT occurred
since the last read of this reg ister
1 = Indic ates the “Change i n AIS-CI Condition” interrupt has occurred sinc e
the last read of thi s register
0RxRAI-CI RUR/
WC 0Change in Recei ve RAI-CI Condition Interrup t Status
This Reset-Upon- Read bit fie ld indicates whether or not the “Change in RAI-
CI Condition” int errupt within the T1 Receiv e Framer Block has occurred
since the last read of this reg ister.
If t his interrupt is enabled, then the Recei ve T1 Framer block wil l generate
an interrupt in r esponse to either one of the fo ll owing conditions.
1. Whenever the Receive T1 Framer block det ects t he RAI-CI Condition.
2. Whenever the Receive T1 Framer block clears the RAI-CI Conditi on
0 = Indic ates the “Change i n RA I-CI Condition” interrupt has NOT occurred
since the last read of this reg ister
1 = Indic ates the “Change in RAI-CI Condi tion” in ter rupt has occurred since
the last read of thi s register
TABLE 105: CUSTOMER INSTALLATION ALARM STATUS REGISTER (CIAIER) HEX ADDRESS: 0XnB41
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
1RxAIS-CI_ENB R/W 0Change in Receive AIS-CI Condition Interrupt Enabl e
This bi t enables or disabl es the “Change in AIS-CI Condition” interrupt within
the T1 Receive Framer Block.
If this i nterr upt is enab led, th en the Receiv e T 1 Framer bloc k will generate an
interrupt in response to ei ther one of the following conditions.
1. Wheneve r the Receive T1 Framer block detects the AIS- CI Condi tion.
2. Whenever the Receive T1 Framer bl ock clears the AIS-CI Condition
0 - Disables the “Change in AIS-CI Condition” i nterrupt .
1 - Enables the “Change in AIS-CI Condition” int err upt.
0RxRAI-CI_ENB R/W 0Change in Receive RAI-CI Condition Interrupt Enable
This bi t enables or disables t he “Change in RAI-CI Co ndition” interr upt within
the T1 Receive Framer Block.
If this i nterr upt is enab led, th en the Receiv e T 1 Framer bloc k will generate an
interrupt in response to ei ther one of the following conditions.
1. Wheneve r the Receive T1 Framer block detects the RAI-CI Condi tion.
2. Whenever the Receive T1 Framer bl ock clears the AIS-CI Condition
0 - Disables the “Change in RAI-CI Condi tion” inter rupt.
1 - Enables the “Change in RAI-CI Condit ion” int err upt.
TABLE 104: CUSTOMER INSTALLATION ALARM STATUS REGISTER (CIASR) HEX ADDRESS: 0XnB40
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
124
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2.0 LINE INTERFACE UNIT (LIU SECTION) REGISTERS
TABLE 106: LIU CHANNEL CONTROL REGISTER 0 (LIUCCR0) HEX ADDRESS: 0X0FN0
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7QRSS_n/
PRBS_n R/W 0QRSS/PRBS Select Bits
These bits are used to select between QRSS and PRBS.
0 = PRBS_n (215 - 1)
1 = QRSS_n (220 - 1)
6PRBS_Rx_n/
PRBS_Tx_n
R/W 0PRBS Recei ve/Transmit Select :
This bi t is used to select where the o utput of the PRBS Generat or is
directed if PRBS generation is enabled.
0 = Normal Operat ion - PRBS g enerator is output on TTIP and
TRING if PRBS generation is enabl ed.
1 = PRBS Generator is output on RPOS and RCLK.
5RXON_n R/W 0Receiver ON:
This bi t permit s the use r to either t urn on or turn of f the Recei ve Sec-
tion o f XRT86VL32. If the user turns on the Receive Sect ion, then
XR T86VL32 will begin to receive the incoming data-stream vi a the
RTIP and RRING input pins.
Conversely, if the user turns off the Receive Section, t hen the e nti re
Receive Section except the MCLKIN Phase Locked Loop (PLL) will
be power ed down.
0 = Shuts off the Receive Section of XRT86VL32.
1 = Turns on the Receive Section o f XRT86VL32.
PBRS
Generator Tx TTIP
TRIN
G
+
-
Bit 6 = "0"
PBRS
Generator Rx RPOS
RNE
G
+
-
Bit 6 = "1"
XRT86VL32
125
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
4-0 EQC[4:0] R/W 00000 Equalizer Control [4:0]:
These bits are used to control the transm it pulse shaping, t ransmit
line build-out (LBO) and receive sensitivity level.
The Transmit Pulse Shape can be controll ed by adjusting the T rans-
mit Line Build-Out Settings for different cable length in T1 mode.
Tr ansmit pulse shape can also be controlled by using t he Arbitrary
mode, where us ers can sp ecify the amplit ude of the pulse s hape by
using the 8 Arbitrary Pulse Segments provided in the LIU registers
(0x0Fn8-0xnFnF), where n is the channel number.
The XR T86VL32 devi ce supports both long haul and short haul
appli cations which can also be sel ected using the EQC[4:0] bit s.
Table 107.pr esen ts th e corres pondi ng T ra nsmit Li ne Buil d Out a nd
Receive Sensitivity settings using different combinations of these
five EQC[4:0] bits.
TABLE 106: LIU CHANNEL CONTROL REGISTER 0 (LIUCCR0) HEX ADDRESS: 0X0FN0
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
126
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 107: EQUALIZER CONTROL AND TRANSMIT LINE BUILD OUT
EQC[4:0] T1 MODE/RECEIVE SENSITIVITY TRANSMIT LBO CABLE
0x00h T1 Long H aul/36dB 0dB 100Ω TP
0x01h T1 Long H aul/36dB -7.5dB 100Ω TP
0x02h T1 Long H aul/36dB -15dB 100Ω TP
0x03h T1 Long H aul/36dB -22.5dB 100Ω TP
0x04h T1 Long H aul/45dB 0dB 100Ω TP
0x05h T1 Long H aul/45dB -7.5dB 100Ω TP
0x06h T1 Long H aul/45dB -15dB 100Ω TP
0x07h T1 Long H aul/45dB -22.5dB 100Ω TP
0x08h T1 Short Haul/15dB 0 to 133 feet (0.6dB) 100Ω TP
0x09h T1 Short Haul/15dB 133 t o 266 feet (1.2dB) 100Ω TP
0x0Ah T1 Short Haul/15dB 266 to 3 99 feet (1.8dB) 100Ω TP
0x0Bh T1 Short Haul/15dB 399 to 5 33 feet (2.4dB) 100Ω TP
0x0Ch T1 Short Haul/15dB 533 t o 655 feet (3.0dB) 100Ω TP
0x0Dh T1 Short Haul/15dB Arbitrary Pulse 100Ω TP
0x0Eh T1 Gain Mode/29dB 0 to 133 feet (0.6dB) 100Ω TP
0x0Fh T1 Gain Mode/29dB 133 to 266 feet (1. 2dB) 100Ω TP
0x10h T1 Gain Mode/29dB 266 to 399 feet (1. 8dB) 100Ω TP
0x11h T1 Gain Mode/29dB 399 to 5 33 feet (2.4dB) 100Ω TP
0x12h T1 Gain Mode/29dB 533 to 655 feet (3. 0dB) 100Ω TP
0x13h T1 Gain Mode/29dB Arbitrary Pulse 100Ω TP
0x14h T1 Gain Mode/29dB 0dB 100Ω TP
0x15h T1 Gain Mode/29dB -7.5dB 100Ω TP
0x16h T1 Gain Mode/29dB -15dB 100Ω TP
0x17h T1 Gain Mode/29dB -22.5dB 100Ω TP
0x18h E1 Long Haul/36dB ITU G.703 75Ω Coax
0x19h E1 Long Haul/36dB ITU G.703 120Ω TP
0x1Ah E1 Long Haul/45dB ITU G.703 75Ω Coax
0x1Bh E1 Long Haul/45dB ITU G.703 120Ω TP
0x1Ch E1 Short Haul/15dB ITU G.703 75Ω Coax
0x1Dh E1 Short Haul/15dB ITU G.703 120Ω TP
0x1Eh E1 Gain Mode/29dB ITU G.703 75Ω Coax
0x1Fh E1 Gain Mode/29dB ITU G.703 120Ω TP
XRT86VL32
127
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 108: LIU CHANNEL CONTROL REGISTER 1 (L IUCCR1) HEX ADDRESS: 0X0FN1
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7RXTSEL_n R/W 0Rece iver Termin ation Select:
Upon power up, the receiv ers are in “High” impedance. The LIU pro-
vides an option fo r user to have eit her softwar e or hardware control
over re ceive termination . If RxTCNTL (bi t 6 in Re gister 0x0FE2 ) is
set to’0’, recei ve termination can be selected by programmi ng this
register bi t. To switch contr ol to the hardware pin (RxTSEL pin),
RxTCNT L mus t be pro gramm ed to “1”. Once control has been
granted to the har dware pin, RxTSEL must be pulled “High” to
switch to internal termination.
If RxTCNTL is set to’0’, receive termination can be selected by set-
ting this bit according t o the following table:
6TXTSEL_n R/W 0Transmi t Terminati on Select:
This bi t i s used to select between int ernal termi nation or “High”
impedance modes for the T1 transm it ter according to the f oll owing
table:
5-4 TERSEL[1:0] R/W 00 Termina tio n Im pe d a n c e Se lec t [1 :0 ] :
These bits are used to control the transmit and receive termi nation
impedance when th e LIU bl ock is configured in Internal Terminati on
Mode.
In internal ter mination mode, (i. e., TXTSEL = “1” and RXTSEL =
“1”), internal transmit and receive termination can be selected
ac c o r d ing to t he f o l l owin g table:
NOTE: In the internal termination mode, the transmitter output
should be AC coupled to the transformer.
RXTSEL RX Termination
0
1
"High" Impe dance
Internal
TXTSEL TX Termination
0
1
"High" Impedance
Internal
TERSEL1 TERSEL0
0 0
0 1
1 0
1 1
Internal Transmit
and Receive
Termination
100Ω
110Ω
75Ω
120Ω
XRT86VL32
128
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3RxJASEL_n R/W 0Receive Jitter Attenuator Enable
This bi t permits the user to ena ble or disabl e the Ji tter Attenuator in
the Recei ve Path withi n the XRT86VL32 device.
0 = Disabl es the Jitte r Attenuator to oper ate in the Recei ve Path
with in t he Receive T1 LIU Block.
1 = Enables the J it ter Attenu ator to operat e in the Receive Path
with in t he Receive T1 LIU Block.
2TxJASEL_n R/W 0Transmit Jitte r Attenuator Enable
This bi t permits the user to ena ble or disabl e the Ji tter Attenuator in
the Transm it Path within the XRT86VL32 device.
0 = Disabl es the Jitte r Attenuator to operate in the Tra nsm it Path
with in t he Transmit T1 LIU Block.
1 = Enables the J it ter Attenuator to operate in the T ransmi t Pat h
with in t he Transmit T1 LIU Block.
1JABW_n R/W 0Jitter Attenuator Bandwidth Sel ect:
In T1 mode, t he Jit ter Attenu ator Bandwidth is always 3Hz, and this
bit ha s no effect on t he Jitter Attenuator Bandwidth. The FIFOS (bit
D0 of this regist er) will be used to sele ct the FIFO size, acc ording to
the table bel ow.
0FIFOS_n R/W 0FIFO Size Select: See tabl e of bit D1 above for the fu nction of this
bit.
TABLE 108: LIU CHANNEL CONTROL REGISTER 1 (L IUCCR1) HEX ADDRESS: 0X0FN1
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
0
1
1
0
0
1
1
JABW
bit D1
T1
T1
T1
T1
E1
E1
E1
E1
Mode
32
64
32
64
32
64
64
64
FIFO
Size
3
3
3
3
10
10
1.5
1.5
JA B-W
Hz
XRT86VL32
129
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 109: LIU CHANNEL CONTROL REGISTER 2 (LIUCCR2) HEX ADDRESS: 0X0FN2
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7INVQRSS_n R/W 0Inver t QRSS Pattern:
This bi t i nverts the o utput PRBS/QRSS patt ern if the LIU Block is
confi gured to tra nsm it a PRBS/QRSS pattern.
0 = The LIU will NOT invert the output PRBS/QRSS pattern
1 = The LIU will invert the output PRBS/QRSS pattern
6-4 TXTEST[2:0] R/W 000 Transmi t Test Patter n [2:0]:
These bits are used to confi gure the Transmit T1 LIU Block to gen-
erate and transmit test patterns according to the followi ng table.
Use of these bit s automat ically places the LIU section in Single Rail
mode. When t his happens, th e Framer section must be placed in
Singl e Rail mode in Reg 0xn101.
TDQRSS (Transmit/Dete ct Quasi -Ran dom Signal):
QRSS pattern is a 220-1 pseudo-random bit sequence (PRBS) wit h
no more than 14 consecutive zeros.
TAO S (Trans mit All On e s) :
Whenever the user implements this configuration setting, the Trans-
mit T1 LIU Block will ignore the data that it is accepting from the
Transmit T1 Framer block (as well as the upst ream system-side t er-
minal equipment) and overwrit e this data wi th t he All Ones Pattern.
TLUC (Transmit Network Loop-Up Code):
The Transmit T1 LI U Block will generate and transmit the Network
Loop-Up Code of “00001” to the line for the selected channel num-
ber n.
When Network Loop-Up code is being transmitted, the XRT86VL32
will ignore the “Automati c Loop-Code detection and Remote Loop-
Back act ivation” (NLCDE1 =“ 1”, NLCDE0 =“1” of r egist er 0x0Fn3) in
order to avoid act ivating Remot e Digi tal Loop-Back automatical ly
when the remote terminal responds to the Loop- Back reque st.
TLDC (Transmit Network Loop-Down Code):
The Transmit T1 LI U Block will generate and transmit the Network
Loop-Down Code of “001” to the line for the sel ected chann el num-
ber n.
0 0
0 1
1 0
1 1
1
1
1
1
X X0 No P a tte rn
TDQRSS
TAOS
TLUC
Test Pattern
TLDC
TXTEST1 TXTEST0TXTEST2
XRT86VL32
130
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3TXON_n R/W 0Transm i tt er ON:
This bit per m its the user to eith er t urn on or tur n of f t he Transmit
Driver of XRT86VL32. If the user turns on the Transmit Driver, then
XR T86VL32 will begin to tr ansm i t T1 data (on the line) via the TTIP
and TRING out put pins.
Conv ers el y, if the user turns of f t he Transm it Driver, then the TTIP
and TRING out put pins will be tri-stated.
0 = Shuts of f the T ran sm it Dri ver associat ed with the XRT86VL32
device and t ri-states the TTIP and TRING output pins.
1 = T ur ns on the T ra nsm i t Driver associated wi th the XR T86VL32
device.
NOTE: If the user wishes to exercise software control over the state
of the Transmit Driver of the XRT86VL32, then it is
imperative that the user pull the TxON pin to a logic “HIGH”
level.
2-0 LOOP2_n R/W 000 Loop-Back control [2:0]:
These bits cont rol the Loop-B ack M odes of the LI U section, acc ord-
ing to the tabl e bel ow.
TABLE 109: LIU CHANNEL CONTROL REGISTER 2 (LIUCCR2) HEX ADDRESS: 0X0FN2
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
LOOP2
0
1
1
1
1
LOOP1
X
0
0
1
1
LOOP0
X
0
1
0
1
Loop-Back Mode
No Loop-Back
Dual Loop-Back
Analog Loop-Back
Remote Loop-Back
Digital Loop -Back
XRT86VL32
131
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 110: LIU CHANNEL CONTROL REGISTER 3 (LIUCCR3) HEX ADDRESS: 0X0FN3
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-6 NLCDE[1:0] R/W 00 Network Loop Code Det ection Enable [1:0]:
These bi ts are used to control the Loop-C ode det ection on the
recei ve path of each channel, ac cor din g to the table below. This
part must be in Single Rail mode to detect..
Loop-Up Code Dete ction Enabl e:
The XRT86VL32 is configured to monitor the recei ve data for the
Loop-Up code Patter n (i.e. a strin g of fou r ‘0’ s followed by one ‘1’
pattern) . When the presence of the “000 01” pattern is detec ted for
mor e than 5 seconds, the status o f the NLCD bit (b it 3 of reg is ter
0x0Fn5) is set to “1” and if the NLCD inte rr upt is enabled (bit 3 of
regi st er 0x0Fn4), an in terrupt will be gener ated.
Loop-Down Code Dete ction Enable:
The XRT86VL32 is configured to monitor the recei ve data for the
Loop-Down code Pat te rn ( i.e. a string of two ‘0’s follow ed by one ‘1’
pattern) . When the presence of the “001 ” pa tt er n is detected for
mor e than 5 seconds, the status o f the NLCD bit (b it 3 of reg is ter
0x0Fn5) is set to “1” and if the NLCD inte rr upt is enabled (bit 3 of
regi st er 0x0Fn4), an in terrupt will be gener ated.
Automatic Loop-Up Code Detection and Remote Loop Back
Activation Enable:
When t his mode is enabled, the state of the NLCD bi t (bit 3 of regis-
ter 0x0Fn5) is reset to “ 0” and the XRT86VL32 is con fi gur ed to mon-
ito r the recei ve data for the Loop -Up code. If the “00001” pattern is
detected f or longer t han 5 seconds, then t he NLCD bit ( bit 3 of regis-
ter 0 x0Fn5) is se t “1”, and Rem ote Loop- Back is activated . Once th e
remote loop-back is activated, the XRT86VL32 is automatically pro-
gramm ed to monitor the receive dat a for the Loop- Dow n code. The
NLCD bi t st ays set even af ter the chip stops recei vi ng the Loop-Up
code.
The Remote Loop-Back condition is removed only when the
XR T86VL32 rece ives the Lo op-Down code fo r more than 5 seco nds
or if the Autom atic Loop-Cod e detection mode is ter minated.
5-2 Reserved R/W 0This Bit Is Not Used
NLCDE[1:0] NETWORK LOOP CODE DETECTION
ENABLE
00 Disables Loop Code Detection
01 Enables Loop-Up Code Det ection on
the Recei ve Pat h.
10 Enables Loop-Down Code D etection
on the Recei ve Pat h.
11 Enables Automatic Loop-Up Code
Detection on the Receive Path and
Remote Loop-Back Activation upon
detect i ng Loop-Up Code.
XRT86VL32
132
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1INSBER_n R/W 0Insert Bit Error:
This bit is used to ins ert a singl e bit error on the transmi tter of the T1
LIU Block.
When t he T1 LIU Blo ck is configured to transm i t and det ect the
QRSS pattern, (i.e., TxTEST[2:0] bits set to ‘b100’), a “0” to “1” tran-
sition of this bit will insert a bit error in the transmitted QRSS pattern
of the selected channel num ber n.
The state of this bit is sampled on the r ising edge of the respective
TCLK_n.
NOTE: To ensure the insertion of bit error, a “0” should be written in
thi s bit location before writing a “1”.
0Reserved R/W 0Th is B it Is Not U s e d
TABLE 110: LIU CHANNEL CONTROL REGISTER 3 (LIUCCR3) HEX ADDRESS: 0X0FN3
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
133
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 111: LIU CHANNEL CONTROL INTERRUPT ENABLE REGISTER (LI UCCIER) HEX ADDRESS: 0X0FN4
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved RO 0This Bit Is Not Used
6DMOIE_n R/W 0Change of Transmi t DMO (Drive Monit or Output) Condition In ter-
rupt Enable:
This bit permits the user to either enabl e or disabl e the “Change of
T r ansm i t DM O Condition” Interr upt . If the user enables this in terrupt,
then the XRT86VL32 device will generate an interrupt any time when
either one of the fol l owing events occur.
1. Whenever the Transmit Sect ion toggl es t he D M O Status bi t (Bi t 6
or Regis ter 0x0Fn5) to “1”.
2. Whenever the Transmit Sect ion toggl es t he D M O Status bi t (Bi t 6
or Regis ter 0x0Fn5) to “0”.
0 – Disables the “Cha nge in the DMO Condi t io n” In ter ru pt.
1 – Enabl es the “Change in the DMO Condition” Interrupt.
5FLSIE_n R/W 0FIFO Limit Status In terrupt Enabl e:
This bit permits the user to either enabl e or disabl e the “FIFO Limi t Sta -
tus” Interrupt. If the user enabl es t his interrupt, then th e XRT86VL32
device wi ll gener ate an interrupt when the jitter atte nuat or Read/Wr i te
FIFO pointers are withi n +/- 3 bits.
0 = Disables the “ FIFO Limit Status” Interrupt
1 = Enables the “FIFO Limit Status” Interrupt
4Reserved - - This bit is not used.
3NLCDIE_n R/W 0Change in Netw ork Loop -Code Det ection Interrup t Enable:
This bit permits the user to either enabl e or disabl e the “Change in Net -
work Loop-Code Detection” Interrupt. If the user enables this interrupt,
then the XRT86VL32 device will generate an interrupt any time when
either one of the fol l owing events occur.
1. Whenever the Receive Section (within XRT86VL32) detects the
Network Loop-Code (Loop-Up or Loop-Down depending on which
Loop-Code the Receive LI U is confi gur ed to det ect ).
2. Whenever the Receive Section (within XRT86VL32) no longer
detects the Network Loop-Code (Loop-Up or Loop-Down
depending on which Loop-Code the Receive LIU is configured to
detect).
0 – Disables the “ Change in Network Loop-Code Detection” Interrupt.
1 – Enables the “C hange i n Network Loop-Code D et ection” Interrupt.
2Reserved - - This bit is not used
XRT86VL32
134
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
NOTE: Register 0x0FN4, 0x0FN5 and 0x0FN6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be pl aced in Single Rai l mode i n Register 0xn101.
1RLOSIE_n R/W 0Change of the Receive LOS (Loss of Signal) Defect Conditi on In ter-
rupt Enable:
This bit permits the user to either enabl e or disabl e the “Change of th e
Receive LOS D efe ct Condi t ion” Interr upt. If the use r enabl es this inter-
rupt, then the XR T86VL32 device will generate an int er rupt any time
when eithe r one of the foll owing events occur.
1. Whenever the Receive Section (within XRT86VL32) declares the
LOS Defect Condition.
2. Whenever the Receive Section (within XRT86VL32) clears the
LOS Defect condition.
0 – Disables the “Change in the LOS Defect Condition” Interrupt.
1 – Enables the “Change i n the LOS D efe ct Condi t io n” I nter r upt.
0QRPDIE_n R/W 0Change in QRSS Pat tern Detection Interrupt Enable:
This bit permits the user to either enabl e or disabl e the “Change in
QRSS Patte rn Det ect io n” In ter ru pt. If the user enables this interrupt,
then the XRT86VL32 device will generate an interrupt any time when
either one of the fol l owing events occur.
1. Whenever the Receive Section (within XRT86VL32) detects the
QRSS Pattern.
2. Whenever the Receive Section (within XRT86VL32) no longer
detect s t he QRSS Patte rn.
0 – Disables the “Change in QRSS Pattern Detection” Interrupt.
1 – Enables the “Change i n QRSS Patter n Detection ” Inter rup t.
TABLE 111: LIU CHANNEL CONTROL INTERRUPT ENABLE REGISTER (LI UCCIER) HEX ADDRESS: 0X0FN4
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
135
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 112: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved RO 0
6DMO_n RO 0Dr iv e r Monit o r Output (DMO ) Status:
This READ- ONLY bit indicates w het her or n ot the Transmit Secti on
is cur ren tly declarin g the DMO Alar m con diti on.
The Tran sm it Section will chec k the T ransmit Output T1 Lin e sig nal
for bipol ar pulses via the TTI P and TRING outp ut signals. If the
Tran sm it Section were to detect no bipolar signal for 128 consecu-
tive bit -p eri ods, then it will decla re th e Tra nsm i t DMO Alarm condi-
tio n. This particul ar al ar m can be used to chec k for fault conditions
on the Transm i t Out put Line Signal path.
The Transmit Section will clear the Transmit DMO Alarm condition
the in st ant that it dete ct s som e bipolar ac tivi ty on the Transmit Out-
put Li ne sig nal .
0 = Indicates that the Transmit Section of XR T86VL32 is NOT cur-
rent ly decl ari ng th e Tra nsm i t DMO Alarm conditi on.
1 = Indicates that the Transmit Section of XR T86VL32 is current ly
declaring the Tra nsm i t DMO Alarm condition.
NOTE: If the DMO interrupt is enabled (DMOIE - bit D6 of register
0x0Fn4), any tran sition on th is bit will gener ate an Inter rupt.
5FLS_n RO 0FIFO Limit Status:
This READ- ONLY bit indicates whether or not the XRT86VL32 is
currently decl aring the FIFO Limit Status.
This bit i s set to a “1” to indi cate that t he jitter att enuator Read/W ri te
FIFO poi nters are within +/- 3 bits.
0 = I ndicates that the XRT86VL32 is NOT currently declaring the
FIFO Li mit Status.
1 = Indicates that the XRT86VL32 is cur re ntly decl aring the FIFO
Limi t Status.
NOTE: If the FIFO Limit Status Interrupt is enabled, (FLSIE bit - bit
D5 of register 0x0Fn4), any transition on this bit will
generate an Inter rupt.
4Reserved - 0 T h is Bit Is Not Used
XRT86VL32
136
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3NLCD_n RO 0Network Loop-Code Det ect ion Stat us Bit:
This bit operates different l y in the M anual or the Automat ic Network
Loop-Code detection modes.
Manual Loop-Up Code detection mode
(.i.e If NLCD E 1 = “0” and NLC D E0 = “1 ” ), th is bi t ge ts set to “1” as
soon as the Loop- U p Code (“00001”) i s det ected in the receive dat a
for longer than 5 seconds.
This bit st ays high as lon g as the Receive T1 LIU Block detects t he
presence of the Loop- Up code i n the re cei ve data and it is reset to
“0” as soon as it stops receiving the Loop-Up Code.
If the NLCD interrupt is enabled, the XRT86VL32 will initiate an
interrupt on every transition of the NLCD status bit.
Manual Loop-Down Code detection mode
(i.e. , If NLC DE 1 = “1” and NLCDE0 = “0” ) , this bit gets set to “1” as
soon as the Loop-Do wn Code (“001” ) is detecte d in t he receiv e d ata
for longer than 5 seconds.
This bit st ays high as lon g as the Receive T1 LIU Block detects t he
presence of the Loop- Dow n code in the receive dat a and it is reset
to “0” as soon as i t st ops receiving t he Loop-Down Code.
If the NLCD interrupt is enabled, the XRT86VL32 will initiate an
interrupt on every transition of the NLCD status bit.
Autom atic Loop- code detection mode
(i.e. , I f NLCDE 1 = “1” and NLC DE 0 =” 1”) , t he st at e of the NLCD st a-
tus bi t is re set to “0 ” and t he XRT86VL32 is programmed to moni tor
the rec ei ve inp ut data for the Loop- Up code.
This bit is set to a “1” to ind ic ate that the Network Loop Code is
detected for more than 5 seconds. Simul t aneously, the Remote
Loop-Back con diti on i s aut om ati cally activated and the XRT86VL32
is pro gramm ed t o mon itor the receive dat a for the Networ k Loop
Down code. The NLCD bit st ays ‘high’ as lo ng as the Remote Loop-
Back condition is i n effect even if the chip stops receiving the Loop-
Up code. Remote Loop-Back is removed only if the XRT86VL32
detects the Loop- Down Code “001” pattern for longer than 5 sec-
onds i n the recei ve dat a. Upon det ecting t he Loop-Do wn Code “0 01”
pattern, the XRT86VL32 will reset the N LCD st atu s bit and an inter-
rupt will be gener at ed if the NLCD interru pt ena ble bit is enabled.
Users can monitor the state of this bit to determine if the Remote
Loop-Back is activat ed.
2Reserved - 0 T h is Bit Is Not Used
1RLOS_n RO 0Rece ive Loss of Signal Defect Condition Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is cur ren tly declarin g the LOS def ect condition.
0 = Indicates that the Rece iv e Section i s NOT curr ent ly decla ri ng
the LOS Defect Condition .
1 = Indicate s that the Recei ve Sect ion is cur rently d eclari ng the LOS
Defect condit ion .
NOTE: If the RLOSI E bit (bit D1 of Regi ster 0x0F n4) is enable d, any
transition on this bit will generate an Int errupt.
TABLE 112: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
137
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
NOTE: Register 0x0FN4, 0x0FN5 and 0x0FN6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be pl aced in Single Rai l mode i n Register 0xn101.
0QRPD_n RO 0Quasi-random Pattern Detection Status:
This READ-ONLY bit indicates whether or not the Receive LIU Block
is currently declar ing the QRSS Pattern LOCK st at us.
0 = I ndicates that the XRT86VL32 is NOT currently declaring the
QRSS Pattern LOCK.
1 = Indicates that the XR T86VL32 is curre ntly decl ar ing the QRSS
Pattern LOCK.
NOTE: If the QRPDIE bit (bit D0 of register 0x0Fn4) is enabled, any
transition on this bit will generate an Int errupt.
TABLE 112: LIU CHANNEL CONTROL STATUS REGISTER (LIUCCSR) HEX ADDRESS: 0X0FN5
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
138
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 113: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR) HEX ADDRESS: 0X0FN6
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved RO 0
6DMOIS_n RUR/
WC 0Change of Transmit DMO (Drive Moni tor Output) Condition
Inte rrupt Status:
This RESET - upon-READ b it indica tes whet her o r not the “Change o f
the Transmit DMO Condition” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “C hange of the Transmit DMO Condi tion”
Int err upt has NOT occurred since the last read of t his register.
1 = Indicates that the “C hange of the Transmit DMO Condi tion”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when DMO_n status bit (bit 6
of Register 0x0Fn5) has changed since the last read of this
register.
NOTE: Users can determine the current state of the “Transmit DMO
Condition” by reading out the conte nt of bit 6 within Register
0x0Fn5
5FLSIS_n RUR/
WC 0FIFO Li mit Interrupt Status:
This RESET-upon-READ bit indic ate s whethe r or not the “FIFO
Limit” Interrupt has occurred since the last read of this register.
0 = Indicates that the “F IFO Li mit Status ” Inter rup t has NO T
occurred since the last read of this register.
1 = Indicates that the “FIFO Li mit Status ” Inter rup t has occurred
since the last read of this register.
This bit is set to a “1” every time when FIFO Limit Status bit
(bit 5 of Re giste r 0x0Fn5 ) has c hang ed s ince the last read of
this register .
NOTE: Users can determine the current state of the “FIFO Limit” by
reading out the content of bit 5 within Regist er 0x0Fn5
4Reserved - - This bit is not used
3NLCDIS_n RUR/
WC 0Change in Networ k Loop- Code Detec ti on Interr upt Sta tus:
This RESET -upon- READ bit indicates whe ther o r not the “Change in
Netw or k Loop-Code Detection” Interrupt has occurred since t he last
read of this register.
0 = Indicates that the “Change i n Ne twor k Loop- C ode D et ect ion”
Int err upt has NOT occurred since the last read of t his register.
1 = Indicates that the “Change i n Ne twor k Loop- C ode D et ect ion”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every ti me w hen NL CD st atus bit (bit 3 of Reg -
ister 0x0Fn5) has changed since the last read of this r egister.
NOTE: Users can determine the current state of the “Network Loop-
Code Detection” by reading out the content of bit 3 within
Register 0x0Fn5
2Reserved --This bit is not used
XRT86VL32
139
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
NOTE: Register 0x0FN4, 0x0FN5 and 0x0FN6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be pl aced in Single Rai l mode i n Register 0xn101.
1RLOSIS_n RUR/
WC 0Change of Receive LOS (Loss of Si gnal ) De fect Condi tion Inter-
rupt Stat us:
This RESET - upon-READ b it indica tes whet her o r not the “Change o f
the Receive LOS Defect Condition ” I nt err upt has occurred since the
last read of this register.
0 = Indicates that the “C hange of the Recei ve LOS Defect Con di-
tio n” Inter rupt has NOT occ urr ed si nce th e las t rea d of th is regi ster.
1 - Ind icates tha t the “Cha nge of the Re ceive LOS Def ect Condi tion”
Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the “Receive
LOS Defect condition” by reading out the contents of Bit 1
(Receive LOS Defect Condition Status) within Register
0xnFn5.
0QRPDIS_n RUR/
WC 0Change in Quasi -Random Pattern Detec tion Interr upt Status:
This RESET -upon- READ bit indicates whe ther o r not the “Change in
QRSS Patter n De tec tion” Interrupt has occurred si nce th e las t rea d
of this re gis ter.
0 = Indicates that the “Chan ge in QRSS Pattern Detect ion” Interr upt
has NOT occurred since the last read of th is register.
1 = Indicates that the “Chan ge in QRSS Pattern Detect ion” Interr upt
has occurred since the last read of this r egister.
This bit is set t o a “1” ever y t i m e w hen QRPD sta tus bit (b it 0 of Reg-
ister 0x0Fn5) has changed since the last read of this r egister.
NOTE: Users can determine the current state of the “QRSS Pattern
Detection” by readi ng out the conte nt of bit 0 within Register
0x0Fn5
TABLE 114: LIU CHANNEL CONTROL CABLE LOSS REGISTER (LIUCCCCR) HEX ADDRESS: 0X0FN7
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved RO 0
6Reserved RO 0
5-0 CLOS[5:0] RO 0Cable Loss [5:0]:
These bits represent the six bit receive selective equaliz er setting
which is also a binary word that represents the cable attenuation
indication withi n ±1dB.
CLOS5_n is the most signifi cant bit (MSB) and CLO S0_n is the
least si gni fi cant bit (LSB ).
TABLE 113: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR) HEX ADDRESS: 0X0FN6
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
140
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 115: LIU CHANNEL CONTROL ARBITRARY REGISTER 1 (LIUCCAR1) HEX ADDRESS: 0X0FN8
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_Seg1 R/W 0Ar bitrar y Transmit Pulse Shape, Segm ent 1:
These seven bits form t he first of the ei ght segment s of the transmit
shape pul se when the XR T86VL32 is confi gured in “Arbitrar y Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
TABLE 116: LIU CHANNEL CONTROL ARBITRARY REGISTER 2 (LIUCCAR2) HEX ADDRESS: 0X0FN9
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_Seg2 R/W 0Ar bitrar y Transmit Pulse Shape, Segm ent 2
These seven bits form the second of the eight segments of the
transmit shape pulse when the XRT86VL32 is configured in “Arbi-
trary M ode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
TABLE 117: LIU CHANNEL CONTROL ARBITRARY REGISTER 3 (LIUCCAR3) HEX ADDRESS: 0X0FNA
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_seg3 R/W 0Arbit rar y Transmit Pulse Shape, Segment 3
These sev en bit s form th e third of the ei ght segments of the tran smit
shape pul se when the XR T86VL32 is confi gured in “Arbitrar y Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
NOTE: Arbitrary mode is enabled by writing to the EQC[4:0] bits in
register 0x0Fn0.
XRT86VL32
141
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 118: LIU CHANNEL CONTROL ARBITRARY REGISTER 4 (LIUCCAR4) HEX ADDRESS: 0X0FNB
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_seg4 R/W 0Arbit rar y Transmit Pulse Shape, Segment 4
These se ven bit s for m the for th of the ei ght se gments of the t ransmit
shape pul se when the XR T86VL32 is confi gured in “Arbitrar y Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
Arbitrary mode is enabl ed by writing to th e EQC[4:0] bit s in r egister
0x0Fn0.
TABLE 119: LIU CHANNEL CONTROL ARBITRARY REGISTER 5 (LIUCCAR5) HEX ADDRESS: 0X0FNC
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_seg5 R/W 0Arbit rar y Transmit Pulse Shape, Segment 5
These seven bits form th e fifth of the eight segments of the tran sm it
shape pul se when the XR T86VL32 is confi gured in “Arbitrar y Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
Arbitrary mode is enabl ed by writing to th e EQC[4:0] bit s in r egister
0x0Fn0.
TABLE 120: LIU CHANNEL CONTROL ARBITRARY REGISTER 6 (LIUCCAR6) HEX ADDRESS: 0X0FND
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6-0 Arb_seg6 R/W 0Arbit rar y Transmit Pulse Shape, Segment 6
These s even b its fo rm the s ixth o f the e ight segm ents of the transmit
shape pul se when the XR T86VL32 is confi gured in “Arbitrar y Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
Arbitrary mode is enabl ed by writing to th e EQC[4:0] bit s in r egister
0x0Fn0.
XRT86VL32
142
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 121: LIU CHANNEL CONTROL ARBITRARY REGISTER 7 (LIUCCAR7 ) HEX ADDRESS: 0X0FNE
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6Arb_seg7 R/W 0A r bit rar y Transmit Pulse Shape, Segm ent 7
These seven bits form the seventh of the eight segments of the
transmit shape pulse when the XRT86VL32 is configured in “Arbi-
trary M ode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
Arbitrary mode is enabl ed by writing to th e EQC[4:0] bit s in r egister
0x0Fn0.
TABLE 122: LIU CHANNEL CONTROL ARBITRARY REGISTER 8 (LIUCCAR8) HEX ADDRESS: 0X0FNF
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6Arb_seg8 R/W 0A r bit rar y Transmit Pulse Shape, Segm ent 8
These seven bits form the eight of the eight segments of the trans-
mit shape pul se when the XRT86VL32 is configured in “Arbitrary
Mode”.
These seven bits represent the amplitude of the nth channel's arbi-
trary pul se in signed magnitude form at wi th Bit 6 as the si gn bit and
Bit 0 as the least si gni ficant bit (LSB).
Arbitrary mode is enabl ed by writing to th e EQC[4:0] bit s in r egister
0x0Fn0.
XRT86VL32
143
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1.2.0
TABLE 123: LIU GLOBAL CONTROL REGISTER 0 (LIUGCR0) HEX ADDRESS: 0X0FE0
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7SR R/W 0Single Rail mode
This bit must se t to "1" for Si ngl e R ai l m ode to use LIU di agnotic f ea-
ture s. The F ramer secti on mu st be pr ogrammed as well in R egi ster
0xn101.
0 - Dual Rail
1 - Single Rail
6ATAOS R/W 0Automatic Transmit All Ones Upon RLOS:
This bit enables automa ti c transm i ssion of All Ones Pattern upon
detecting the Recei ve Loss of S ign al ( RLO S) condition.
Once this bi t i s enabl ed, the T ran sm it T1 Fra mer Blo ck w ill automat-
icall y tr ansm i t an All “One s” dat a to the line for the cha nnel that
detects an RLOS condition.
0 = Disabl es the “Aut om atic Transmit All Ones ” feature upon detec t-
ing RLOS
1 = Enables t he “Autom atic Transmit All Ones” f eat ure upon detect-
ing RLOS
5RCLKE R/W 0Receive Clock Data (Framer Bypass mode)
0 = RPOS/RNEG data is updated on the r is ing edge of RCLK
1 = RPOS/RNEG data is updated on the f alli ng edge of RCLK
4TCLKE R/W 0Transmi t Cloc k Data (Framer Bypass mode)
0 = TPOS/TNEG dat a i s sam pl ed on the fal ling edge of TCLK
1 = TPOS/TNEG dat a i s sam pl ed on the rising edge of TCLK
3DATAP R/W 0Data Polarity
0 = T r ansm i t i nput and receive outp ut data is active “Hi gh”
1 = T r ansm i t i nput and receive outp ut data is active “Low”
2Reserved This B it Is Not Used
XRT86VL32
144
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
1GIE R/W 0Glo b a l In t er rupt Ena b le :
This bit allows users to enable or disabl e the global interrupt gener-
ati on for all channels wit hin the T1 LIU Block. On ce this gl obal inter-
rupt is di sable d, no interrupt will be gener ated to the M icrop rocessor
Int err upt Pin even when the individual “source” interrupt status bi t
pulse s ‘high’ .
If this globa l interrupt is enabled, users still need to enab le t he ind i-
vidual “s ourc e” inte rrupt in or der for the T 1 LI U Bl ock to generate an
interrupt to the Microprocessor pin.
0 - Disables the global interr upt generation for all channel s w i thin
the T1 LIU Block.
1 - Enabl es the global interr upt gener ation for a ll channel s within t he
T1 LIU Bloc k.
0SRESET R/W 0Softwar e Reset μP Registers:
This bit allow s users to reset the XRT8 6VL32 d evice. W riti ng a “1” to
thi s bit and keepi ng i t at ’1’ for longer than 10µs initiate s a devi ce
reset thro ugh the mi cropr ocessor interfa ce. Once the XRT 86VL32 is
reset , al l internal circuits are placed in the reset st ate exce pt the
microprocessor regis ter bits.
0 = Disabl es sof t w are reset to the XRT86VL32 device.
1 = Enables sof t ware reset to the XRT86VL32 dev ice.
TABLE 124: LIU GLOBAL CONTROL REGISTER 1 (LIUGCR1) HEX ADDRESS: 0X0FE1
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7Reserved R/W 0
6Reserved R/W 0
5-4 Gauge [1:0] R/W 00 Wi re Gauge Sel ector [1:0]:
This bit t oget her with Guage0 bit (bit 4 within this regi st er) are used
to sel ect the wire gauge size as shown in the table bel ow.
3Reserved This bit is not used
TABLE 123: LIU GLOBAL CONTROL REGISTER 0 (LIUGCR0) HEX ADDRESS: 0X0FE0
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
GAUGE1
0
1
1
0
GAUGE0
0
1
0
1
Wire Si ze
22 and 24 Gauge
26 Gauge
24 Gauge
22 Gauge
XRT86VL32
145
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1. 2.0
2 RXMUTE R/W 0Receive Output Mute:
This bit per m its the user to con figur e the Receive T1 Bloc k to auto-
mat ic al ly pull it s Recovered Data Output pins to GND anytime (and
for the duration that) the Receive T1 LIU Block decl ares the LOS
defect conditi on.
In othe r word s, if t his feature is enabled , the Receive T1 LIU Block
will aut om atically “mute” the Recovered data that is being rout ed to
the Receive T1 Fr am er block any tim e (and for the duratio n that) the
Rec eiv e T1 LIU Blo ck decl ar es the LOS defect condi t ion.
0 – Disabl es the “Muting upon LOS” featur e.
1 – Enables t he “Mut ing upon LO S” featur e.
NOTE: The receive clock is not m uted when this feature is enabled.
1EXLOS Extended LOS Enable:
This bit al l ows users to extend the number of zeros at the rec eiv e
input of eac h channel bef ore RLOS is declared.
When Extended LOS is enabled, the Receive T1 LIU Block will
declare RLOS condition when it receives 4096 number of consecu-
tive zeros at the receive input.
When Ext ended LOS is d is abl ed, the Recei ve T1 LI U Block will
declare RLOS condition when it receives 175 number of consecu-
tive zeros at the receive input.
0 = Disables the Extended LOS Featur e.
1 = Enables the Exte nded LO S Feature.
0ICT R/W 0In-Ci rcuit-Testi n g E n a b le:
This bit al l ow s user s to t rist a t e the output pins of al l channel s for in-
cir cui t t est ing purposes.
When I n-Ci rc ui t- Testing is enabl ed, all output pins of the
XR T86VL32 are “Tri -state d”. Whe n In- Circuit-Testing is dis abl ed, all
output pi ns w ill resume to no rmal condi tion.
0 = Disabl es the In-Circuit-Testing Featur e.
1 = Enables t he In-C ircui t-Testing Feature.
TABLE 125: LIU GLOBAL CONTROL REGISTER 2 (LIUGCR2) HEX ADDRESS: 0X0FE2
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7For c e to "0 " R/W 0Set to "0 "
6RxTCNTL R/W 0Receive Termination Select Cont rol
This bit sets the LIU to cont ro l the Rx TSEL fun ction with either the
individual channel regist er bi t or the gl obal hardware pin.
0 = Control of th e rece iv e ter minat i on is set to the regis ter bits
1 = Control of th e rece iv e ter minat i on is set to the hardw are pin
5-0 Reserved R/W 0This Bit Is Not Used
TABLE 124: LIU GLOBAL CONTROL REGISTER 1 (LIUGCR1) HEX ADDRESS: 0X0FE1
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
XRT86VL32
146
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 126: LIU GLOBAL CONTROL REGISTER 3 (LIUGCR3) HEX ADDRESS: 0X0FE4
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-6 MCLKnT1[1:0] R/W 00 Master T1 Output Clock Reference [1:0]
These two bi ts allow users to select the progra mmable output clo ck
rates for the T1MCLKnOUT pin, according to the table below.
5-4 MCLKnE1[1:0] R/W 00 Master E1 Output Clock Reference [1:0]:
These two bi ts allow users to select the progra mmable output clo ck
rate s for the E1MCLKnO UT pin, accord ing to the tab le below:
3-0 Reserved R/W 0This Bit Is Not Used .
MCLKNT1[1:0] CLOCK RATE OF THE T1MCLKNOUT
OUTPUT PIN
00 1.544MHz
01 3.088MHz
10 6.176MHz
11 12.352MHz
MCLKNE1[1:0] CLOCK RATE OF THE E1MCLK NOUT
OUTPUT PIN
00 2.048MHz
01 4.096MHz
10 8.192MHz
11 16.384MHz
XRT86VL32
147
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1. 2.0
TABLE 127: LIU GLOBAL CONTROL REGISTER 4 (LIUGCR4) HEX ADDRESS: 0X0FE9
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-4 Reserved R/W 0
3-0 CLKSEL[3:0] R/W 1100 Clock Select Input [3:0]
These four bits allow user s to select the programmabl e in put clock
rate s for the MCLKIN i nput pin, acco rding to the table bel ow.
NOTE: User must provide any one of the above clock frequencies to
the MCL KIN input pin fo r the device to be fu nctional.
CLKSEL[3:0] CLOCK RATE OF THE MCLKIN
INPUT PIN
0000 2.048MHz
0001 1.544MHz
0010 8kHz
0011 16kHz
0100 56kHz
0101 64kHz
0110 128kHz
0111 256kHz
1000 4.096MHz
1001 3.088MHz
1010 8.192MHz
1011 6.176MHz
1100 16.384MHz
1101 12.352MH
1110 2.048MHz
1111 1.544MHz
XRT86VL32
148
REV. V1.2.0 DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 128: LIU GLOBAL CONTROL REGISTER 5 (LIUGCR5) HEX ADDRESS: 0X0FEA
BIT FUNCTION TYPE DEFAULT DESCRIPTION-OPERATION
7-3 Reserved - 0 These bits are re served
2GCHIS2 RUR/
WC 0Global Channel 2 Interrupt Status Indicator
This R eset -Upon-Re ad bi t field i ndicates whether or not an i nte rr upt
has occurred on Channel 2 within the XRT86VL32 device since the
last read of this register.
0 = Indicat es t hat No int err upt has occurred on Channel 2 wi thin the
XR T86VL32 device si nce the last read of this regi st er.
1 = Indi cat es that an interr upt has occurred on Channel 2 with in t he
XR T86VL32 device si nce the last read of this regi st er.
1Reserved - - This bit is reserved
0GCHIS0 RUR/
WC 0Global Channel 0 Interrupt Status Indicator
This R eset -Upon-Re ad bi t field i ndicates whether or not an i nte rr upt
has occurred on Channel 0 within the XRT86VL32 device since the
last read of this register.
0 = Indicat es t hat No int err upt has occurred on Channel 0 wi thin the
XR T86VL32 device si nce the last read of this regi st er.
1 = Indi cat es that an interr upt has occurred on Channel 0 with in t he
XR T86VL32 device si nce the last read of this regi st er.
XRT86VL32
149
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1. 2.0
ORDERING INFORMATION
PACKAGE DIMENSIONS
PRODUCT NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT86VL32IB 225 LEAD PBGA -400C to +850C
E
225 Ball Plastic Ball Grid Array
(19.0 mm x 19 .0 mm, 1.0mm p itch
PBGA)
Rev.
1.00
SYMBOL MIN MAX MIN MAX
A 0.049 0.096 1.24 2.45
A1 0.016 0.024 0.40 0.60
A2 0.013 0.024 0.32 0.60
A3 0.020 0.048 0.52 1.22
D 0.740 0.756 18.80 19.20
D1 0.669 BSC 17.00 BSC
D2 0.665 0.669 16.90 17.00
b 0.020 0.028 0.50 0.70
e 0.039 BSC 1.00 BSC
INCHES
MILLIMETERS
No t e : T he con trol di m e nsion is in m illim e ter .
1
24 37
86
5
1
7
1
61
4
1
5
1
2
1
31
1
1
09
1
8
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
D
D1
DD1
A1
Feature /
Mark
D2
AA
1
A
2
A
3
e
b
(A1 corner feature is mfger
option)
Se ati n g P lane
150
NOTICE
EXAR Corporati on res er ves t he right to m ak e c hanges to the pr oducts c ontained in t his publicat ion in order t o
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and m ay vary depen ding upo n a user’s specific a pplication . While the info rmation in th is public ation
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected t o cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corp oration r eceives, in writing, assurances to its sat isfaction that: (a) the risk of i njury or dam age has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 E XAR Corpor at ion
Datasheet January 2007.
Reproduct ion, in part or whole, without the prior written c ons ent of EXAR Corpor at ion is prohibit ed.
XRT86VL32
DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION REV. V1. 2.0
REVISI ON HISTORY
REVISION # DATE DESCRIPTION
V1.2.0 January 30, 2007 Released to production.
