NB3N502DG - ON SEMICONDUCTOR

May, 2012 − Rev. 1

1Publication Order Number:

NB3N502/D

NB3N502

14 MHz to 190 MHz PLL

Clock Multiplier

Description

The NB3N502 is a clock multiplier device that generates a low jitter,

TTL/CMOS level output clock which is a precise multiple of the

external input reference clock signal source. The device is a cost

efficient replacement for the crystal oscillators commonly used in

electronic systems. It accepts a standard fundamental mode crystal or

an external reference clock signal. Phase−Locked−Loop (PLL) design

techniques are used to produce an output clock up to 190 MHz with a

50% duty cycle. The NB3N502 can be programmed via two select

inputs (S0, S1) to provide an output clock (CLKOUT) at one of six

different multiples of the input frequency source, and at the same time

output the input aligned reference clock signal (REF).

Features

•Clock Output Frequency up to 190 MHz

•Operating Range: VDD = 3 V to 5.5 V

•Low Jitter Output of 15 ps One Sigma (rms)

•Zero ppm Clock Multiplication Error

•45% − 55% Duty Cycle

•25 mA TTL−level Drive Outputs

•Crystal Reference Input Range of 5 − 27 MHz

•Input Clock Frequency Range of 2 − 50 MHz

•Available in 8−pin SOIC Package or in Die Form

•Full Industrial Temperature Range −40°C to 85°C

•These are Pb−Free Devices

÷ MFeedback

VDD

Multiplier

Select

Reference

Clock

REF

Phase

Detector

Charge

Pump

Crystal

Oscillator

÷ P

X1/CLK

CLKOUT

Figure 1. NB3N502 Logic Diagram

GND

TTL/

CMOS

Output

VCO

TTL/

CMOS

Output

Device Package Shipping†

ORDERING INFORMATION

NB3N502DG SOIC−8

(Pb−Free)

98 Units / Rail

SOIC−8

D SUFFIX

CASE 751

MARKING DIAGRAM

http://onsemi.com

3N502 = Specific Device Code

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G= Pb−Free Package

3N502

ALYW

NB3N502DR2G SOIC−8

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

NB3N502

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Figure 2. Pin Configuration (Top View)

CLKOUT

X1/CLK

VDD

GND

REF

Table 1. CLOCK MULTIPLIER SELECT TABLE

S1* S0** Multiplier

L L 2X

L H 5X

M L 3X

M H 3.33X

H L 4X

H H 2.5X

L = GND

H = VDD

M = OPEN (unconnected)

* Pin S1 defaults to M when left open

** Pin S0 defaults to H when left open

Table 2. OUTPUT FREQUENCY EXAMPLES

Output Frequency (MHz) 20 25 33.3 48 50 54 64 66.66 75 100 108 120 135

Input Frequency (MHz) 10 10 10 16 20 13.5 16 20 15 20 27 24 27

S1, S0 0 ,0 1, 1 M, 1 M, 0 1, 1 1, 0 1, 0 M, 1 0, 1 0, 1 1, 0 0, 1 0, 1

Table 3. PIN DESCRIPTION

Pin # Name I/O Description

1 X1/CLK Input Crystal or External Reference Clock Input

2 VDD Power Supply Positive Supply Voltage (3 V to 5.5 V)

3 GND Power Supply 0 V Ground.

4 REF CMOS/TTL Output Buffered Crystal Oscillator Clock Output

5 CLKOUT CMOS/TTL Output Clock Output

6 S0 CMOS/TTL Input Multiplier Select Pin − Connect to VDD or GND. Internal Pull−up Resistor.

7 S1 Three−level Input Multiplier Select Pin − Connect to VDD, GND or Float to M.

8 X2 Crystal Input Crystal Input − Do Not Connect when Providing an External Clock Reference

Table 4. ATTRIBUTES

Characteristic Value

ESD Protection Human Body Model

Machine Model

> 8 kV

> 600 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 6700 Devices

Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test

1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

NB3N502

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Table 5. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Units

VDD Positive Power Supply GND = 0 V 7 V

VIInput Voltage GND – 0.5 = VI =

VDD + 0.5

TAOperating Temperature Range −40 to +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 LFPM

500 LFPM

SOIC−8

190

130

°C/W

qJC Thermal Resistance (Junction−to−Case) (Note 1) SOIC−841 to 44 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).

Table 6. DC CHARACTERISTICS (VDD = 3 V to 5.5 V unless otherwise noted, GND = 0 V, TA = −40°C to +85°C) (Note 2)

Symbol Characteristic Min Typ Max Unit

IDD Power Supply Current

(unloaded CLKOUT operating at 100 MHz with 20 MHz crystal)

20 mA

VOH Output HIGH Voltage IOH = −25 mA TTL High 2.4 V

VOL Output LOW Voltage IOL = 25 mA 0.4 V

VIH Input HIGH Voltage, CLK only (pin 1) (VDD / 2) + 1 VDD / 2 V

VIL Input LOW Voltage, CLK only (pin 1) VDD / 2 (VDD / 2) −1 V

VIH Input HIGH Voltage, S0, S1 VDD – 0.5 V

VIL Input LOW Voltage, S0, S1 0.5 V

VIM Input level of S1 when open (Input Mid Point) VDD ÷ 2 V

Cin Input Capacitance, S0, S1 4 pF

ISC Output Short Circuit Current ± 70 mA

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

2. Parameters are guaranteed by characterization and design, not tested in production.

Table 7. AC CHARACTERISTICS (VDD = 3 V to 5.5 V unless otherwise noted, GND = 0 V, TA = −40°C to +85°C) (Note 3)

Symbol Characteristic Min Typ Max Unit

fXtal Crystal Input Frequency 5 27 MHz

fCLK Clock Input Frequency 2 50 MHz

fOUT Output Frequency Range

VDD = 4.5 to 5.5 V (5.0 V ± 10%)

VDD = 3.0 to 3.6 V (3.3 V ± 10%)

190

120

MHz

DC Clock Output Duty Cycle at 1.5 V up to 190 MHz 45 50 55 %

tjitter (rms) Period Jitter (RMS, 1 σ) 15 ps

tjitter (pk−to−pk) Total Period Jitter, (peak−to−peak) ±40 ps

tr/tfOutput rise/fall time (0.8 V to 2.0 V / 2.0 V to 0.8 V) 1 2 ns

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. Parameters are guaranteed by characterization and design, not tested in production.

NB3N502

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APPLICATIONS INFORMATION

High Frequency CMOS/TTL Oscillators

The NB3N502, along with a low frequency fundamental

mode crystal, can build a high frequency CMOS/TTL output

oscillator. For example, a 20 MHz crystal connected to the

NB3N502 with the 5X output selected (S1 = L, S0 = H)

produces a 100 MHz CMOS/TTL output clock.

External Components

Decoupling Instructions

In order to isolate the NB3N502 from system power

supply, noise de−coupling is required. The 0.01 mF

decoupling capacitor has to be connected between VDD and

GND on pins 2 and 3. It is recommended to place

de−coupling capacitors as close as possible to the NB3N502

device to minimize lead inductance. Control input pins can

be connected to device pins VDD or GND, or to the VDD and

GND planes on the board.

Series Termination Resistor Recommendation

A 33 W series terminating resistor can be used on the

CLKOUT pin.

Crystal Load Capacitors Selection Guide

The total on−chip capacitance is approximately 12 pF per

pin (CIN1 and CIN2). A parallel resonant, fundamental mode

crystal should be used.

The device crystal connections should include pads for

small capacitors from X1/CLK to ground and from X2 to

ground. These capacitors, CL1 and CL2, are used to adjust the

stray capacitance of the board to match the nominally

required crystal load capacitance (CLOAD (crystal)).

Because load capacitance can only be increased in this

trimming process, it is important to keep stray capacitance

to a minimum by using very short PCB traces (and no vias)

between the crystal and device. Crystal load capacitors, if

needed, must be connected from each of the pins X1 and X2

to ground. The load capacitance of the crystal (CLOAD

(crystal)) must be matched by total load capacitance of the

oscillator circuitry network, CINX, CSX and CLX, as seen by

the crystal (see Figure 3 and equations below).

CIN1

12 pF

CIN2

12 pF

Internal

to Device

X1/CLK

CS1 CS2

CL1 CL2

Crystal

CLOAD1 = CIN1 + CS1 + CL1 [Total capacitance on X1/CLK]

CLOAD2 = CIN2 + CS2 + CL2 [Total capacitance on X2]

CIN1 [ CIN2 [ 12 pF (Typ) [Internal capacitance]

CS1 [ CS2 [ 5 pF (Typ) [External PCB stray capacitance]

CLOAD1,2 = 2 S CLOAD (Crystal)

CL2 = CLOAD2 − CIN2 − CS2 [External load capacitance on X2]

CL1 = CLOAD1 − CIN1 − CS1 [External load capacitance on X1/CLK]

Example 1: Equal stray capacitance on PCB

CLOAD (Crystal) = 18 pF (Specified by the crystal manufacturer)

CLOAD1 = CLOAD2 = 36 pF

CIN1 = CIN2 = 12 pF

CS1 = CS2 = 6 pF

CL1 = 36 − 12 − 6 = 18 pF

CL2 = 36 − 12 − 6 = 18 pF

Example 2: Different stray capacitance on PCB trace X1/CLK vs. X2

CLOAD (Crystal) = 18 pF

CLOAD1 = CLOAD2 = 36 pF

CIN1 = CIN2 = 12 pF

CS1 = 4 pF & CS2 = 8 pF

CL1 = 36 − 12 − 4 = 20 pF

CL2 = 36 − 12 − 8 = 16 pF

Figure 3. Using a Crystal as Reference Clock

NB3N502

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PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AK

SEATING

PLANE

X 45 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW

STANDARD IS 751−07.

0.10 (0.004)

DIM

MIN MAX MIN MAX

INCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B3.80 4.00 0.150 0.157

C1.35 1.75 0.053 0.069

D0.33 0.51 0.013 0.020

G1.27 BSC 0.050 BSC

H0.10 0.25 0.004 0.010

J0.19 0.25 0.007 0.010

K0.40 1.27 0.016 0.050

M0 8 0 8

N0.25 0.50 0.010 0.020

S5.80 6.20 0.228 0.244

−X−

−Y−

0.25 (0.010)

−Z−

0.25 (0.010) ZSXS

____

1.52

0.060

7.0

0.275

0.6

0.024

1.270

0.050

4.0

0.155

ǒmm

inchesǓ

SCALE 6:1

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

NB3N502/D

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